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MaximIntegratedProducts1GeneralDescriptionTheDS1308serialreal-timeclock(RTC)isalow-power,fullbinary-codeddecimal(BCD)clock/calendarplus56bytesofNVRAM.
AddressanddataaretransferredseriallythroughanI2Cinterface.
Theclock/calendarprovidesseconds,minutes,hours,day,date,month,andyearinformation.
Theendofthemonthdateisauto-maticallyadjustedformonthswithfewerthan31days,includingcorrectionsforleapyear.
Theclockoperatesineitherthe24-houror12-hourformatwithanAM/PMindicator.
TheDS1308hasabuilt-inpower-sensecircuitthatdetectspowerfailuresandautomaticallyswitchestothebackupsupply,maintainingtimeanddateoperation.
ApplicationsHandhelds(GPS,POSTerminal)ConsumerElectronics(Set-TopBox,DigitalRecording,NetworkAppliance)OfficeEquipment(Fax/Printer,Copier)Medical(Glucometer,MedicineDispenser)Telecommunications(Router,Switcher,Server)Other(UtilityMeter,VendingMachine,Thermostat,Modem)FeaturesSLowTimekeepingCurrentof250nA(typ)SCompatiblewithCrystalESRUpto100kωSRTCCountsSeconds,Minutes,Hours,Date,Month,DayoftheWeek,andYearwithLeap-YearCompensationUpto2400S56-Byte,Battery-Backed,General-PurposeRAMwithUnlimitedWritesSI2CSerialInterfaceSExternalClockSourceforSynchronizationClockReference(e.
g.
,32kHz,50Hz/60HzPowerline,GPS1PPS)SProgrammableSquare-WaveOutputSignalSAutomaticPower-FailDetectandSwitchCircuitryS-40NCto+85NCOperatingTemperatureRangeSUnderwritersLaboratories(UL)RecognizedTypicalOperatingCircuit19-6353;Rev0;5/12OrderingInformationappearsatendofdatasheet.
Forrelatedpartsandrecommendedproductstousewiththispart,referto:www.
maxim-ic.
com/DS1308.
relatedDS1308SCLSDASQW/CLKINX1X2VBATGNDVCCVCCRPURPURPUCPUVCCMaximIntegratedProducts2DS1308Low-CurrentI2CRTCwith56-ByteNVRAM(Allvoltagesrelativetoground.
)VoltageRangeonVCCorVBAT.
0.
3Vto+6.
0VVoltageonAnyNon-PowerPin.
0.
3Vto(VCC+0.
3V)OperatingTemperatureRange.
40NCto+85NCJunctionTemperatureMaximum.
150NCStorageTemperatureRange.
55NCto+125NCLeadTemperature(soldering,10s)300NCSolderingTemperature(reflow)260NCABSOLUTEMAXIMUMRATINGSStressesbeyondthoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionalopera-tionofthedeviceattheseoranyotherconditionsbeyondthoseindicatedintheoperationalsectionsofthespecificationsisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
RECOMMENDEDOPERATINGCONDITIONS(TA=-40NCto+85NC,unlessotherwisenoted.
)(Note2)DCELECTRICALCHARACTERISTICS(VCC=VCCMINtoVCCMAX,VBAT=VBATMINtoVBATMAX,TA=-40NCto+85NC,unlessotherwisenoted.
)(Note2)FSOPJunction-to-AmbientThermalResistance(BJA).
.
.
.
.
.
206.
3NC/WJunction-to-CaseThermalResistance(BJC)42NC/WNote1:PackagethermalresistanceswereobtainedusingthemethoddescribedinJEDECspecificationJESD51-7,usingafour-layerboard.
Fordetailedinformationonpackagethermalconsiderations,refertowww.
maxim-ic.
com/thermal-tutorial.
PACKAGETHERMALCHARACTERISTICS(Note1)PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperatingVoltageRangeVCCDS1308-181.
711.
85.
5VDS1308-32.
73.
05.
5DS1308-333.
03.
35.
5BatteryVoltageVBAT1.
35.
5VLogic1InputVIH0.
7xVCCVCC+0.
3VLogic0InputVIL-0.
30.
3xVCCVPARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPower-SupplyActiveCurrent(Note3)ICCA-3or-33:fSCL=400kHz325FAPower-SupplyStandbyCurrent(Note4)ICCS-33:VCC=3.
63V125FAVCC=VCCMAX200BatteryLeakageCurrentIBATLKGVCCRVPF-10025+100nAInputLeakage(SCL)IIVIN=0VtoVCC-0.
1+0.
1FAI/OLeakage(SDA,SQW/CLKIN)IIOI2Cbusinactive,ECLK=1-0.
1+0.
1FAOutputLogic0(SDA,SQW/CLKIN),VOL=0.
4VIOLVCCRVCCMIN3.
0mAVBATR1.
3VRVCC+0.
2V250FAPower-FailTripPointVPF-332.
702.
823.
00VSwitchoverVoltageVSWVBAT>VPFVPFVVBATVCCMaximIntegratedProducts3DS1308Low-CurrentI2CRTCwith56-ByteNVRAMDCELECTRICALCHARACTERISTICS(VCC=0V,VBAT=VBATMINtoVBATMAX,TA=-40NCto+85NC,unlessotherwisenoted.
)(Note2)ACELECTRICALCHARACTERISTICS(VCC=VCCMINtoVCCMAX,TA=-40NCto+85NC,unlessotherwisenoted.
)(Note2)PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBatteryCurrent,SQWOff(Note5)IBAT1VBAT=3V250nAVBAT=VBATMAX600BatteryCurrent,SQWOn(Note6)IBAT2VBAT=3V550nAVBAT=VBATMAX1100Data-RetentionCurrent(Note7)IBATDATVBAT=3V25100nAPARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLClockFrequencyfSCL(Note8)0.
03400kHzBusFreeTimeBetweenaSTOPandSTARTConditiontBUF1.
3FsHoldTime(Repeated)STARTConditiontHD:STA(Note9)0.
6FsLowPeriodofSCLClocktLOW1.
3FsHighPeriodofSCLClocktHIGH0.
6FsDataHoldTimetHD:DAT(Notes10,11)00.
9FsDataSetupTimetSU:DAT(Note12)100nsSetupTimeforaRepeatedSTARTConditiontSU:STA0.
6FsRiseTimeofBothSDAandSCLSignalstR(Note13)20+0.
1CB300nsFallTimeofBothSDAandSCLSignalstF(Note13)20+0.
1CB300nsSetupTimeforSTOPConditiontSU:STO0.
6FsCapacitiveLoadforeachBusLineCB(Note13)400pFSCLSpikeSuppressiontSP60nsOscillatorStopFlag(OSF)DelaytOSF(Note14)100msTimeoutIntervaltTIMEOUT(Note15)2535msMaximIntegratedProducts4DS1308Low-CurrentI2CRTCwith56-ByteNVRAMPOWER-UP/DOWNCHARACTERISTICS(TA=-40NCto+85NC,unlessotherwisenoted.
)(Notes2,16)CAPACITANCE(TA=+25NC,unlessotherwisenoted.
)(Note16)Warning:Negativeundershootsbelow-0.
3Vwhilethepartisinbattery-backedmodemaycauselossofdata.
Note2:Limitsare100%productiontestedatTA=+25NCandTA=+85NC.
Limitsovertheoperatingtemperaturerangeandrelevantsupplyvoltageareguaranteedbydesignandcharacterization.
Typicalvaluesarenotguaranteed.
Note3:SCLclockingatmaxfrequency.
VSCL=0VtoVCC.
Note4:SpecifiedwithI2Cbusinactive.
Timekeepingandsquare-wavefunctionsoperational.
Note5:CH=ECLK=SQWE=0.
Note6:CH=ECLK=0,SQWE=RS1=RS0=1,IOUT=0mA.
Note7:CH=1.
ECLK=SQWE=0.
Note8:TheminimumSCLclockfrequencyislimitedbythebustimeoutfeature,whichresetstheserialbusinterfaceifSCLisheldlowfortTIMEOUT.
Note9:Afterthisperiod,thefirstclockpulseisgenerated.
Note10:Adevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignal(referencedtotheVIHMINoftheSCLsignal)tobridgetheundefinedregionofthefallingedgeofSCL.
Note11:ThemaximumtHD:DAThasonlytobemetifthedevicedoesnotstretchthelowperiod(tLOW)oftheSCLsignal.
Note12:Afast-modedevicecanbeusedinastandard-modesystem,buttherequirementtSU:DATRto250nsmustthenbemet.
ThisisautomaticallythecaseifthedevicedoesnotstretchthelowperiodoftheSCLsignal.
IfsuchadevicedoesstretchthelowperiodoftheSCLsignal,itmustoutputthenextdatabittotheSDAlinetRMAX+tSU:DAT=1000+250=1250nsbeforetheSCLlineisreleased.
Note13:CBisthetotalcapacitanceofonebusline,includingallconnecteddevices,inpF.
Note14:TheparametertOSFistheperiodoftimetheoscillatormustbestoppedfortheOSFflagtobesetoverthevoltagerangeof2.
4VPVCCPVCCMAX.
Note15:TheDS1308candetectanysingleSCLclockheldlowlongerthantTIMEOUTMIN.
Thedevice'sI2CinterfaceisinresetstateandcanreceiveanewSTARTconditionwhenSCLisheldlowforatleasttTIMEOUTMAX.
OncethepartdetectsthisconditiontheSDAoutputisreleased.
Theoscillatormustberunningforthisfunctiontowork.
Note16:Guaranteedbydesignandnot100%productiontested.
PARAMETERSYMBOLMINTYPMAXUNITSRecoveryatPower-UptREC12msVCCSlewRate(VPFto0V)tVCCF1/50V/FsVCCSlewRate(0VtoVPF)tVCCR1/1V/FsPARAMETERSYMBOLMINTYPMAXUNITSInputCapacitanceCI10pFI/OCapacitanceCO10pFMaximIntegratedProducts5DS1308Low-CurrentI2CRTCwith56-ByteNVRAMFigure1.
DataTransferonI2CSerialBusFigure2.
Power-Up/Power-DownTimingSCLNOTE:TIMINGISREFERENCEDTOVILMAXANDVIHMIN.
SDASTOPSTARTREPEATEDSTARTtBUFtHD:STAtHD:DATtSU:DATtSU:STOtHD:STAtSPtSU:STAtHIGHtRtFtLOWVCCSCLSDAVALIDRECOGNIZEDVALIDRECOGNIZEDVPFtVCCFDON'TCAREHIGHIMPEDANCEtRECtVCCRMaximIntegratedProducts6TypicalOperatingCharacteristics(VCC=+3.
3V,TA=+25NC,unlessotherwisespecified.
)POWER-SUPPLYCURRENTvs.
SCLFREQUENCYDS1308toc05SCLFREQUENCY(kHz)POWER-SUPPLYCURRENT(A)300200100100150200500400TA=+25°C,IOUT=0mA5.
0V3.
0VSQW/CLKINOUTPUT-VOLTAGELOWvs.
OUTPUTCURRENTDS1308toc04OUTPUTCURRENT(mA)OUTPUTVOLTAGE(V)3210.
10.
20.
30.
4004TA=+25°C,OUT=ECLK=SQWE=0VCC=3.
0VVCC=5.
0VVCC=1.
3VBATTERYCURRENT(SQWON)vs.
BATTERYVOLTAGEDS1308toc03BATTERYVOLTAGE(V)BATTERYCURRENT(nA)4.
53.
52.
53004005006007008002001.
55.
5RS1=RS0=SQWE=1,IOUT=0mA+85°C+25°C-40°CBATTERYCURRENT(SQWOFF)vs.
BATTERYVOLTAGEDS1308toc02BATTERYVOLTAGE(V)BATTERYCURRENT(nA)4.
53.
52.
51502002503003504001001.
55.
5SQWE=0,IOUT=0mA+85°C+25°C-40°CSUPPLYCURRENTvs.
SUPPLYVOLTAGEDS1308toc01SUPPLYVOLTAGE(V)SUPPLYCURRENT(A)5.
04.
53.
54.
08090100110130120140150703.
05.
5SQWE=1,IOUT=0mA+85°C+25°C-40°CMaximIntegratedProducts7DS1308Low-CurrentI2CRTCwith56-ByteNVRAMPinConfigurationPinDescriptionPINNAMEFUNCTION1X132.
768kHzCrystalConnections.
Theinternaloscillatorcircuitryisdesignedforusewithacrystalhavingaspecifiedloadcapacitance(CL)of6pF.
Note:Formoreinformationaboutcrystalselectionandcrystallayoutconsiderations,refertoApplicationNote58:CrystalConsiderationswithMaximReal-TimeClocks(RTCs).
2X23VBATBatterySupplyInputforLithiumCellorOtherEnergySource.
Batteryvoltagemustbeheldbetweentheminimumandmaximumlimitsforproperoperation.
DiodesplacedinseriesbetweenthebackupsourceandtheVBATpincanpreventproperoperation.
Ifabackupsupplyisnotrequired,VBATmustbegrounded.
ULrecognizedtoensureagainstreversechargingwhenusedwithalithiumcell.
4GNDGround5SDASerialDataInput/OutputfortheI2Cserialinterface.
Itisanopen-drainoutputandrequiresanexternalpullupresistor.
Thepullupvoltagecanbeupto5.
5V,regardlessofthevoltageonVCC.
6SCLSerialClockInputfortheI2Cserialinterface.
Usedtosynchronizedatamovementontheserialinterface.
Thepullupvoltagecanbeupto5.
5V,regardlessofthevoltageonVCC.
7SQW/CLKINSquare-WaveOutput/ClockInput.
ThisI/Opinisusedtooutputoneoffoursquare-wavefrequencies(1Hz,4kHz,8kHz,32kHz)oracceptanexternalclockinputtodrivetheRTCcounter.
Intheoutputmode(ECLK=0),itisopendrainandrequiresanexternalpullupresistor.
Thesquare-waveoperatesonVCC,oronVBATwithBBCLK=1.
Thepullupvoltagecanbeupto5.
5V,regardlessofthevoltageonVCC.
Ifnotused,thispinmaybeleftunconnected.
8VCCPrimaryPowerSupply.
Decouplethepowersupplywitha0.
1FFcapacitortoground.
SOP27SQW/CLKINX218VCCX1SCLVBAT36SDAGND45DS1308TOPVIEW+MaximIntegratedProducts8DS1308Low-CurrentI2CRTCwith56-ByteNVRAMFunctionalDiagramDetailedDescriptionTheDS1308serialRTCisalow-power,fullBCDclock/calendarplus56bytesofNVSRAM.
AddressanddataaretransferredseriallythroughanI2Cinterface.
Theclock/calendarprovidesseconds,minutes,hours,day,date,month,andyearinformation.
Theendofthemonthdateisautomaticallyadjustedformonthswithfewerthan31days,includingcorrectionsforleapyear.
Theclockoperatesineitherthe24-houror12-hourformatwithanAM/PMindicator.
TheDS1308hasabuilt-inpower-sensecircuitthatdetectspowerfailuresandautomaticallyswitchestotheVBATsupply.
OperationTheDS1308operatesasaslavedeviceontheserialbus.
AccessisobtainedbyimplementingaSTARTconditionandprovidingadeviceidentificationcode,followedbydata.
Subsequentregisterscanbeaccessedsequen-tiallyuntilaSTOPconditionisexecuted.
ThedeviceisfullyaccessibleanddatacanbewrittenandreadwhenVCCisgreaterthanVPF.
However,whenVCCfallsbelowVPF,theinternalclockregistersareblockedfromanyaccess.
IfVBATisgreaterthanVBAT,thedevicepowerisswitchedfromVCCtoVBATwhenVCCdropsbelowVPF.
IfVBATislessthanVPF,thedevicepowerisswitchedfromVCCtoVBATwhenVCCdropsbelowVBAT.
TheoscillatorandtimekeepingfunctionsaremaintainedfromtheVBATsourceuntilVCCreturnsaboveVPF,readandwriteaccessisallowedaftertREC.
TheFunctionalDiagramshowsthemainelementsoftheDS1308.
Anenablebitinthesecondsregister(CH)controlstheoscillator.
Oscillatorstartuptimesarehighlydependentuponcrystalcharacteristics,PCBleakage,andlayout.
HighESRandexcessivecapacitiveloadsarethemajorcontributorstolongstartuptimes.
Acircuitusingacrystalwiththerecommendedcharacteristicsandproperlayoutusuallystartswithin1second.
Onthefirstapplicationofpowertothedevice,thetimeanddateregistersareresetto01/01/000100:00:00(DD/MM/YYDOWHH:MM:SS),andCHbitinthesecondsregisterissetto0.
DS1308NN/4/32EXTSYNCCONTROLLOGICOSC-1HzPOWERCONTROLRAMCLOCKANDCALENDARREGISTERS/2128HzOSC-1HzSQW/CLKINX1X2SCLSDA4.
096kHz8.
192kHz32.
768kHzMUX/BUFFERDIVIDEREXT-1HzSERIALBUSINTERFACEANDADDRESSREGISTERVCCVBATMaximIntegratedProducts9DS1308Low-CurrentI2CRTCwith56-ByteNVRAMFreshnessSealModeWhenabatteryisfirstattachedtothedevice,thedevicedoesnotimmediatelyprovidebattery-backuppowertotheRTCorinternalcircuitry.
AfterVCCexceedsVPF,thedevicesleavethefreshnesssealmodeandprovidebattery-backuppowerwheneverVCCsubsequentlyfallsbelowVBAT.
Thismodeallowsattachmentofthebatteryduringproductmanufacturing,butnobatterycapacityisconsumeduntilafterthesystemhasbeenactivatedforthefirsttime.
Asaresult,minimumbatteryenergyisusedduringstorageandshipping.
OscillatorCircuitTheDS1308usesanexternal6pF32.
768kHzcrystal.
Theoscillatorcircuitdoesnotrequireanyexternalresistorsorcapacitorstooperate.
SeeTable2fortheexternalcrystalparameters.
TheFunctionalDiagramshowsasimplifiedschematicoftheoscillatorcircuit.
Thestartuptimeisusuallylessthan1secondwhenusingacrystalwiththespecifiedcharacteristics.
WheneverVCC>VPF,a5Fsglitchfilterattheoutputofthecrystaloscillatorisenabled.
ClockAccuracyTheaccuracyoftheclockisdependentupontheaccuracyofthecrystalandtheaccuracyofthematchbetweenthecapacitiveloadoftheoscillatorcircuitandthecapacitiveloadforwhichthecrystalwastrimmed.
Crystalfrequencydriftcausedbytemperatureshiftscreatesadditionalerror.
Externalcircuitnoisecoupledintotheoscillatorcircuitcanresultintheclockrunningfast.
Figure3showsatypicalPCBlayoutforisolatingthecrystalandoscillatorfromnoise.
RefertoApplicationNote58:CrystalConsiderationswithMaximReal-TimeClocks(RTCs)fordetailedinformation.
Table1.
PowerControlTable2.
CrystalSpecificationsNote:Thecrystal,traces,andcrystalinputpinsshouldbeisolatedfromRFgenerat-ingsignals.
RefertoApplicationNote58:CrystalConsiderationsforMaximReal-TimeClocks(RTCs)foradditionalspecifications.
Figure3.
TypicalPCBLayoutforCrystalSUPPLYCONDITIONREAD/WRITEACCESSPOWEREDBYVCCVBATNoVCCVCC>VPF,VCCVPF,VCC>VBATYesVCCPARAMETERSYMBOLMINTYPMAXUNITSNominalFrequencyfO32.
768kHzSeriesResistanceESR100kILoadCapacitanceCL6pFCRYSTALX1X2GNDLOCALGROUNDPLANE(LAYER2)NOTE:AVOIDROUTINGSIGNALSINTHECROSSHATCHEDAREA(UPPERLEFT-HANDQUADRANT)OFTHEPACKAGEUNLESSTHEREISAGROUNDPLANEBETWEENTHESIGNALLINEANDTHEPACKAGE.
MaximIntegratedProducts10DS1308Low-CurrentI2CRTCwith56-ByteNVRAMRTCandRAMAddressMapTable3showstheaddressmapfortheRTCandRAMregisters.
TheRTCregistersandcontrolregisterarelocatedinaddresslocations00h–07h.
TheRAMregis-tersarelocatedinaddresslocations08h–3Fh.
Duringamultibyteaccess,whentheregisterpointerreaches3Fh(theendofRAMspace)itwrapsaroundtolocation00h(thebeginningoftheclockspace).
OnanI2CSTART,orregisterpointerincrementingtolocation00h,thecurrenttimeanddateistransferredtoasecondsetofregisters.
Thetimeanddateinthesecondaryregistersarereadinamultibytedatatransfer,whiletheclockcontinuestorun.
Thiseliminatestheneedtore-readtheregistersincaseofanupdateofthemainregistersduringaread.
ClockandCalendarThetimeandcalendarinformationisobtainedbyreadingtheappropriateregisterbytes.
Thetimeandcalendararesetorinitializedbywritingtheappropriateregisterbytes.
ThecontentsofthetimeandcalendarregistersareintheBCDformat.
Bit7ofRegister0istheclockhalt(CH)bit.
Whenthisbitissetto1,theoscillatorisdisabled.
Whenclearedto0,theoscillatorisenabled.
Theclockcanbehaltedwheneverthetimekeepingfunctionsarenotrequired,whichminimizesVBATcurrent(IBATDAT)whenVCCisnotapplied.
Theday-of-weekregisterincrementsatmidnight.
Valuesthatcorrespondtothedayofweekareuser-definedbutmustbesequential(i.
e.
,if1equalsSunday,then2equalsMonday,andsoon).
Illogicaltimeanddateentriesresultinundefinedoperation.
Whenreadingorwritingthetimeanddateregisters,secondary(user)buffersareusedtopreventerrorswhentheinternalregistersupdate.
Whenreadingthetimeanddateregisters,theuserbuffersaresynchronizedtotheinternalregistersonanySTARTandwhentheregisterpointerrollsovertozero.
Thecountdownchainisresetwheneverthesecondsregisteriswritten.
WritetransfersoccurontheacknowledgefromtheDS1308.
Oncethecountdownchainisreset,toavoidrolloverissuestheremainingtimeanddateregistersmustbewrittenwithin1second.
The1Hzsquare-waveoutput,ifenabled,transitionshigh500msafterthesecondsdatatransfer,providedtheoscillatorisalreadyrunning.
TheDS1308runsineither12-houror24-hourmode.
Bit6ofthehoursregisterisdefinedasthe12-houror24-hourmode-selectbit.
Whenhigh,the12-hourmodeisselected.
Inthe12-hourmode,bit5istheAM/PMbit,withlogichighbeingPM.
Inthe24-hourmode,bit5isthe20-hourbit(20–23hours).
Ifthe12/24-hourmodeselectischanged,thehoursregistermustbere-initializedtothenewformat.
Table3.
RTCandRAMAddressMapNote:Bitslistedas"0"alwaysreadasa0.
ADDRESSBIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT0FUNCTIONRANGE00hCH10SecondsSecondsSeconds00–5901h010MinutesMinutesMinutes00–5902h012/24AM/PM10HourHourHours1–12+AM/PM00–2320Hour03h00000DayDay1–704h0010DateDateDate01–3105h00010MonthMonthMonth01–1206h10YearYearYear00–9907hOUTECLKOSFSQWELOSBBCLKRS1RS0Control08h–3FhRAM56x800h–FFhMaximIntegratedProducts11DS1308Low-CurrentI2CRTCwith56-ByteNVRAMControlRegister(07h)ThecontrolregistercontrolstheoperationoftheSQW/CLKINpinandprovidesoscillatorstatus.
Bit7:OutputControl(OUT).
ControlstheoutputleveloftheSQW/CLKINpinwhenthesquare-waveoutputisdisabledandVCC>VPF.
IfSQWE=0,thelogiclevelontheSQW/CLKINpinis1ifOUT=1;itis0ifOUT=0.
SeeTable4.
Bit6:EnableClockInput(ECLK).
ThisbitcontrolsthedirectionoftheSQW/CLKINpin(seeTable4).
WhenECLK=1,theSQW/CLKINpinisaninput,withtheexpectedinputratedefinedbythestatesofRS1andRS0.
WhenECLK=0,theSQW/CLKINpinisanoutput,withthesquare-wavefrequencydefinedbythestatesofRS1andRS0.
Bit5:OscillatorStopFlag(OSF).
Alogic1inthisbitindicatesthattheoscillatorhasstoppedorwasstoppedforsometimeperiodandcanbeusedtojudgethevalidityoftheclockandcalendardata.
Thisbitisedgetriggered,andissettologic1whentheinternalcircuitrysensestheoscillatorhastransitionedfromanormalrunstatetoaSTOPcondition.
ThefollowingareexamplesofconditionsthatmaycausetheOSFbittobeset:Thefirsttimepowerisapplied.
ThevoltagepresentonVCCandVBATareinsufficienttosupportoscillation.
TheCHbitissetto1,disablingtheoscillator.
Externalinfluencesonthecrystal(i.
e.
,noise,leakage,etc.
).
Thisbitremainsatlogic1untilwrittentologic0.
Thisbitcanonlybewrittentologic0.
AttemptingtowriteOSFtologic1leavesthevalueunchanged.
Bit4:Square-WaveEnable(SQWE).
Whensettologic1,thisbitenablestheoscillatoroutputtooperatewitheitherVCCorVBATapplied.
Thefrequencyofthesquare-waveoutputdependsuponthevalueoftheRS0andRS1bits.
Bit3:LossofSignal(LOS).
ThisstatusbitindicatesthestateoftheCLKINpin.
TheLOSbitissetto1whentheRTCcounterisnolongerconditionedbytheexternalclock.
Thisoccurswhen1)ECLK=0,or2)whentheCLKINinputsignalstopstoggling,or3)whentheCLKINfrequencydiffersbymorethanQ0.
8%fromtheselectedinputfrequency.
Thisbitremainsa1untilwrittento0.
AttemptingtowriteLOS=1leavesthevalueunchanged.
ClearingtheLOSflagwhentheCLKINfrequencyisinvalidinhibitssubsequentdetectionsoftheinputfrequencydeviation.
Bit2:BatteryBackupClock(BBCLK).
Whensettologic1,thisbitenablestheSQW/CLKINI/Owhilethepartispow-eredbyVBAT.
Whensettologic0,thisbitdisablestheSQW/CLKINI/OwhilethepartispoweredbyVBAT.
Bits1and0:RateSelect(RS1andRS0).
ThesebitscontrolthefrequencyoftheSQW/CLKINoutputwhenthesquare-wavehasbeenenabled(SQWE=1).
Table4liststhesquare-wavefrequenciesthatcanbeselectedwiththeRSbits.
Table4.
SQW/CLKINPinFunctionsX=Don'tcare.
Bit#BIT7BIT6BIT5BIT4BIT3BIT2BIT1BIT0NameOUTECLKOSFSQWELOSBBCLKRS1RS0POR10111111OUTECLKSQWERS1RS0SQW/CLKINX01001HzoutputX01014.
096kHzoutputX01108.
192kHzoutputX011132.
768kHzoutput000XX0100XX1X1X001HzinputX1X0150HzinputX1X1060HzinputX1X1132.
768kHzinputMaximIntegratedProducts12DS1308Low-CurrentI2CRTCwith56-ByteNVRAMExternalSynchronizationWhenanexternalclockreferenceisused,theinputfromSQW/CLKINisdivideddownto1Hz.
The1Hzfromthedivider(Ext-1Hz,seeFunctionalDiagram)isusedtocorrectthe1Hzthatisderivedfromthe32.
768kHzoscil-lator(Osc-1Hz).
AsOsc-1HzdriftsinrelationtoExt-1Hz,Osc-1Hzisdigitallyadjusted.
AsshownintheFunctionalDiagram,thethreehighestfrequenciesdrivingtheSQW/CLKINpinarederivedfromtheuncorrectedoscillator,whilethe1HzoutputisderivedfromtheadjustedOsc-1Hzsignal.
Conceptually,thecircuitcanbethoughtofastwo1Hzsignals,onederivedfromtheinternaloscillatorandtheotherfromtheexternalreferenceclock,withtheoscillator-derived1Hzsignalbeinglockedtothe1Hzsignalderivedfromtheexternalreferenceclock.
Theedgesofthe1Hzsignalsdonotneedtobealignedwitheachother.
Whiletheexternalclocksourceispresentandwithintolerance,theExt-1HzandOsc-1Hzmaintaintheirexistinglock,regardlessoftheiredgealignment,withperiodiccorrectionoftheOsc1Hzsignal.
Iftheexternalsignalislostandthenregainedsometimelater,thesignalsre-lockwithwhatevernewalignmentexists(Figure4).
TheExt-1Hzisusedbythedeviceaslongasitiswithintolerance,whichisabout0.
8%ofOsc-1Hz.
WhileExt-1Hziswithintolerance,theskewbetweenthetwosignalsmayshiftuntilachangeofabout7.
8msaccumulates,afterwhichOsc-1Hzsignalisadjusted(Figure5).
Theadjust-mentisaccomplishedbydigitallyadjustingthe32kHzoscillatordividerchain.
Figure4.
LossandReacquisitionofExternalReferenceClockFigure5.
DriftAdjustmentofInternal1HztoExternalReferenceClockOSC-1HzFROMOSCILLATOREXT-1HzFROMEXTERNALREFERENCESKEWSKEWBREAKINEXTERNALREFERENCESIGNALCURRENTLOCKSHIFTEDBACKTOCURRENTLOCKDRIFTAFTERNCYCLESOSC-1HzFROMOSCILLATOREXT-1HzFROMEXTERNALREFERENCEMaximIntegratedProducts13DS1308Low-CurrentI2CRTCwith56-ByteNVRAMIfthedifferencebetweenExt-1HzandOsc-1Hzisgreaterthanabout0.
8%,Osc-1Hzrunsunadjusted(seeFigure4)andthelossofsignal(LOS)isset,providedtheenableexternalclockinputbit(ECLK)isset.
I2CSerialPortOperationI2CSlaveAddressTheDS1308'sslaveaddressbyteisD0h.
ThefirstbytesenttothedeviceincludesthedeviceidentifierandtheR/Wbit(Figure6).
ThedeviceaddresssentbytheI2Cmastermustmatchtheaddressassignedtothedevice.
I2CDefinitionsThefollowingterminologyiscommonlyusedtodescribeI2Cdatatransfers.
MasterDevice:Themasterdevicecontrolstheslavedevicesonthebus.
ThemasterdevicegeneratesSCLclockpulsesandSTARTandSTOPconditions.
SlaveDevices:Slavedevicessendandreceivedataatthemaster'srequest.
BusIdleorNotBusy:TimebetweenSTOPandSTARTconditionswhenbothSDAandSCLareinac-tiveandintheirlogic-highstates.
Whenthebusisidleitofteninitiatesalow-powermodeforslavedevices.
STARTCondition:ASTARTconditionisgeneratedbythemastertoinitiateanewdatatransferwithaslave.
TransitioningSDAfromhightolowwhileSCLremainshighgeneratesaSTARTcondition.
SeeFigure1forapplicabletiming.
STOPCondition:ASTOPconditionisgeneratedbythemastertoendadatatransferwithaslave.
TransitioningSDAfromlowtohighwhileSCLremainshighgeneratesaSTOPcondition.
SeeFigure1forapplicabletiming.
RepeatedSTARTCondition:ThemastercanusearepeatedSTARTconditionattheendofonedatatransfertoindicatethatitimmediatelyinitiatesanewdatatransferfollowingthecurrentone.
RepeatedSTARTsarecommonlyusedduringreadoperationstoidentifyaspecificmemoryaddresstobeginadatatransfer.
ArepeatedSTARTconditionisissuedidenti-callytoanormalSTARTcondition.
SeeFigure1forapplicabletiming.
BitWrite:TransitionsofSDAmustoccurduringthelowstateofSCL.
ThedataonSDAmustremainvalidandunchangedduringtheentirehighpulseofSCLplusthesetupandholdtimerequirements(Figure1).
DataisshiftedintothedeviceduringtherisingedgeoftheSCL.
BitRead:Attheendawriteoperation,themastermustreleasetheSDAbuslinefortheproperamountofsetuptimebeforethenextrisingedgeofSCLdur-ingabitread(Figure1).
ThedeviceshiftsouteachbitofdataonSDAatthefallingedgeofthepreviousSCLpulseandthedatabitisvalidattherisingedgeofthecurrentSCLpulse.
RememberthatthemastergeneratesallSCLclockpulsesincludingwhenitisreadingbitsfromtheslave.
Acknowledge(ACKandNACK):Anacknowledge(ACK)ornot-acknowledge(NACK)isalwaysthe9thbittransmittedduringabytetransfer.
Thedevicereceivingdata(themasterduringareadortheslaveduringawriteoperation)performsanACKbytrans-mittingazeroduringthe9thbit.
AdeviceperformsaNACKbytransmittingaoneduringthe9thbit.
TimingfortheACKandNACKisidenticaltoallotherbitwrites.
AnACKistheacknowledgmentthatthedeviceisproperlyreceivingdata.
ANACKisusedtoterminateareadsequenceorasanindicationthatthedeviceisnotreceivingdata.
ByteWrite:Abytewriteconsistsof8bitsofinforma-tiontransferredfromthemastertotheslave(mostsignificantbitfirst)plusa1-bitacknowledgmentfromtheslavetothemaster.
The8bitstransmittedbythemasteraredoneaccordingtothebitwritedefinitionandtheacknowledgmentisreadusingthebitreaddefinition.
ByteRead:Abytereadisan8-bitinformationtransferfromtheslavetothemasterplusa1-bitACKorNACKfromthemastertotheslave.
The8bitsofinformationthataretransferred(mostsignificantbitfirst)fromtheslavetothemasterarereadbythemasterusingthebitreaddefinition,andthemastertransmitsanACKusingthebitwritedefinitiontoreceiveadditionaldataFigure6.
SlaveAddressByte1110R/W000MSBLSBREAD/WRITEBITDEVICEIDENTIFIERMaximIntegratedProducts14DS1308Low-CurrentI2CRTCwith56-ByteNVRAMbytes.
ThemastermustNACKthelastbytereadtoterminatecommunicationsotheslavereturnscontrolofSDAtothemaster.
SlaveAddressByte:EachslaveontheI2CbusrespondstoaslaveaddressbytesentimmediatelyfollowingaSTARTcondition.
Theslaveaddressbytecontainstheslaveaddressinthemostsignificant7bitsandtheR/Wbitintheleastsignificantbit.
TheslaveaddressisD0handcannotbemodifiedbytheuser.
WhentheR/Wbitis0(suchasinD0h),themas-terisindicatingitwritesdatatotheslave.
IfR/W=1,(D1hinthiscase),themasterisindicatingitwantstoreadfromtheslave.
Ifanincorrectslaveaddressiswritten,theDS1308assumesthemasteriscom-municatingwithanotherI2CdeviceandignoresthecommunicationuntilthenextSTARTconditionissent.
MemoryAddress:DuringanI2Cwriteoperation,themastermusttransmitamemoryaddresstoidentifythememorylocationwheretheslaveistostorethedata.
Thememoryaddressisalwaysthesecondbytetransmittedduringawriteoperationfollowingtheslaveaddressbyte.
I2CCommunicationWritingaSingleBytetoaSlave:ThemastermustgenerateaSTARTcondition,writetheslaveaddressbyte(R/W=0),writethememoryaddress,writethebyteofdata,andgenerateaSTOPcondition.
Rememberthemastermustreadtheslave'sacknowl-edgmentduringallbytewriteoperations.
WritingMultipleBytestoaSlave:Towritemultiplebytestoaslave,themastergeneratesaSTARTcondi-tion,writestheslaveaddressbyte(R/W=0),writesthestartingmemoryaddress,writesmultipledatabytes,andgeneratesaSTOPcondition.
ReadingaSingleBytefromaSlave:Unlikethewriteoperationthatusesthespecifiedmemoryaddressbytetodefinewherethedataistobewritten,thereadoperationoccursatthepresentvalueofthememoryaddresscounter.
Toreadasinglebytefromtheslave,themastergeneratesaSTARTcondition,writestheslaveaddressbytewithR/W=1,readsthedatabytewithaNACKtoindicatetheendofthetransfer,andgeneratesaSTOPcondition.
However,sincerequiringthemas-tertokeeptrackofthememoryaddresscounterisFigure7.
I2CTransactionsSLAVEADDRESSSTARTSTART1101000SLAVEACKSLAVEACKSLAVEACKR/WMSBLSBMSBLSBMSBLSBb7b6b5b4b3b2b1b0READ/WRITEREGISTERADDRESSb7b6b5b4b3b2b1b0DATASTOPSINGLEBYTEWRITE-WRITECONTROLREGISTERTOBFhMULTIBYTEWRITE-WRITEDATEREGISTERTO"02"ANDMONTHREGISTERTO"11"SINGLEBYTEREAD-READCONTROLREGISTERMULTIBYTEREAD-READHOURSANDDAYREGISTERVALUESSTARTREPEATEDSTARTD1hMASTERNACKSTOP110100000000011107h110100011101000000000111D0h07hSTOPVALUESTART1101000000000100D0h04hDATAMASTERNACKSTOPVALUEDATA02hBFhEXAMPLEI2CTRANSACTIONSTYPICALI2CWRITETRANSACTION1011111100000010D0hA)C)B)D)SLAVEACKSLAVEACKSLAVEACKSLAVEACKSLAVEACKSLAVEACKSLAVEACKREPEATEDSTARTD1hMASTERACK11010001VALUEDATASLAVEACKSLAVEACKSLAVEACKSTART1101000000000010D0h02hSLAVEACKSLAVEACKSTOP11h00010001SLAVEACKMaximIntegratedProducts15DS1308Low-CurrentI2CRTCwith56-ByteNVRAMimpractical,thefollowingmethodshouldbeusedtoperformreadsfromaspecifiedmemorylocation.
ManipulatingtheAddressCounterforReads:Adummywritecyclecanbeusedtoforcetheaddresscountertoaparticularvalue.
Todothisthemas-tergeneratesaSTARTcondition,writestheslaveaddressbyte(R/W=0),writesthememoryaddresswhereitdesirestoread,generatesarepeatedSTARTcondition,writestheslaveaddressbyte(R/W=1),readsdatawithACKorNACKasapplicable,andgeneratesaSTOPcondition.
SeeFigure7forareadexampleusingtherepeatedSTARTconditiontospecifythestartingmemorylocation.
ReadingMultipleBytesFromaSlave:Thereadoperationcanbeusedtoreadmultiplebyteswithasingletransfer.
Whenreadingbytesfromtheslave,themastersimplyACKsthedatabyteifitdesirestoreadanotherbytebeforeterminatingthetransaction.
AfterthemasterreadsthelastbyteitmustNACKtoindicatetheendofthetransferandthenitgeneratesaSTOPcondition.
BusTimeoutToavoidanunintendedI2Cinterfacetimeout,SCLshouldnotbeheldlowlongerthantTIMEOUTMIN.
TheI2CinterfaceisintheresetstateandcanreceiveanewSTARTconditionwhenSCLisheldlowforatleasttTIMEOUTMAX.
Whenthepartdetectsthiscondition,SDAisreleasedandallowedtofloat.
Forthetimeoutfunctiontowork,theoscillatormustbeenabledandrunning.
ApplicationsInformationPower-SupplyDecouplingToachievethebestresultswhenusingtheDS1308,decoupletheVCCpowersupplywitha0.
01FFand/or0.
1FFcapacitor.
Useahigh-quality,ceramic,surface-mountcapacitorifpossible.
Surface-mountcomponentsminimizeleadinductance,whichimprovesperformance,andceramiccapacitorstendtohaveadequatehigh-frequencyresponsefordecouplingapplications.
UsingOpen-DrainOutputsTheSQW/CLKINoutputisopendrainandthereforerequiresanexternalpullupresistortorealizealogic-highoutputlevel.
SDAandSCLPullupResistorsSDAisanopen-drainoutputandrequiresanexternalpullupresistortorealizealogic-highoutputlevel.
BecausetheDS1308doesnotuseclockcyclestretch-ing,amasterusingeitheranopen-drainoutputwithapullupresistororCMOSoutputdriver(push-pull)couldbeusedforSCL.
BatteryChargeProtectionTheDS1308containsMaxim'sredundantbattery-chargeprotectioncircuittopreventanychargingofanexternalbattery.
Handling,PCBLayout,andAssemblyAvoidrunningsignaltracesunderthepackage,unlessagroundplaneisplacedbetweenthepackageandthesignalline.
Thelead(Pb)-free/RoHSpackagecanbesolderedusingareflowprofilethatcomplieswithJEDECJ-STD-020.
Moisture-sensitivepackagesareshippedfromthefac-torydry-packed.
Handlinginstructionslistedonthepack-agelabelmustbefollowedtopreventdamageduringreflow.
RefertotheIPC/JEDECJ-STD-020standardformoisture-sensitivedevice(MSD)classifications.
ChipInformationPROCESS:CMOSSUBSTRATECONNECTEDTOGROUNDOrderingInformationPackageInformationForthelatestpackageoutlineinformationandlandpatterns(footprints),gotowww.
maxim-ic.
com/packages.
Notethataor"-"inthepackagecodeindicatesRoHSstatusonly.
Packagedrawingsmayshowadifferentsuffixcharacter,butthedrawingpertainstothepackageregardlessofRoHSstatus.
+Denotesalead(Pb)-free/RoHS-compliantpackage.
*Futureproduct—contactfactoryforavailability.
PARTTEMPRANGEPIN-PACKAGEDS1308U-18+*-40NCto+85NC8FSOPDS1308U-3+*-40NCto+85NC8FSOPDS1308U-33+-40NCto+85NC8FSOPPACKAGETYPEPACKAGECODEOUTLINENO.
LANDPATTERNNO.
8SOPU8+121-003690-0092MaximcannotassumeresponsibilityforuseofanycircuitryotherthancircuitryentirelyembodiedinaMaximproduct.
Nocircuitpatentlicensesareimplied.
Maximreservestherighttochangethecircuitryandspecificationswithoutnoticeatanytime.
Theparametricvalues(minandmaxlimits)shownintheElectricalCharacteristicstableareguaranteed.
Otherparametricvaluesquotedinthisdatasheetareprovidedforguidance.
MaximIntegrated,Inc.
,160RioRoblesDrive,SanJose,CA95134408-601-1000162012MaximIntegratedProductsMaximisaregisteredtrademarkofMaximIntegratedProducts,Inc.
RevisionHistoryREVISIONNUMBERREVISIONDATEDESCRIPTIONPAGESCHANGED05/12Initialrelease—