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1SEPTEMBER2003DSC-5907/172003IntegratedDeviceTechnology,Inc.
Allrightsreserved.
Productspecificationssubjecttochangewithoutnotice.
2.
5VOLTHIGH-SPEEDTeraSyncTMFIFO36-BITCONFIGURATIONS1,024x36,2,048x36,4,096x36,8,192x36,16,384x36,32,768x36,65,536x36,131,072x36and262,144x36IDT72T3645,IDT72T3655,IDT72T3665,IDT72T3675,IDT72T3685,IDT72T3695,IDT72T36105,IDT72T36115,IDT72T36125IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
TheTeraSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIALANDINDUSTRIALTEMPERATURERANGESFEATURES:Chooseamongthefollowingmemoryorganizations:IDT72T36451,024x36IDT72T36552,048x36IDT72T36654,096x36IDT72T36758,192x36IDT72T368516,384x36IDT72T369532,768x36IDT72T3610565,536x36IDT72T36115131,072x36IDT72T36125262,144x36Upto225MHzOperationofClocksUserselectableHSTL/LVTTLInputand/orOutput2.
5VLVTTLor1.
8V,1.
5VHSTLPortSelectableInput/Ouputvoltage3.
3VInputtolerantReadEnable&ReadClockEchooutputsaidhighspeedoperationUserselectableAsynchronousreadand/orwriteporttimingMark&Retransmit,resetsreadpointertousermarkedpositionWriteChipSelect(WCS)inputenables/disablesWriteoperationsReadChipSelect(RCS)synchronoustoRCLKProgrammableAlmost-EmptyandAlmost-Fullflags,eachflagcandefaulttooneofeightpreselectedoffsetsProgramprogrammableflagsbyeitherserialorparallelmeansSelectablesynchronous/asynchronoustimingmodesforAlmost-EmptyandAlmost-FullflagsSeparateSCLKinputforSerialprogrammingofflagoffsetsUserselectableinputandoutputportbus-sizing-x36intox36out-x36intox18out-x36intox9out-x18intox36out-x9intox36outBig-Endian/Little-EndianuserselectablebyterepresentationAutopowerdownminimizesstandbypowerconsumptionMasterResetclearsentireFIFOPartialResetclearsdata,butretainsprogrammablesettingsEmpty,FullandHalf-FullflagssignalFIFOstatusSelectIDTStandardtiming(usingEFandFFflags)orFirstWordFallThroughtiming(usingORandIRflags)OutputenableputsdataoutputsintohighimpedancestateJTAGport,providedforBoundaryScanfunctionAvailablein208-pin(17mmx17mm)or240-pin(19mmx19mm)PlasticBallGridArray(PBGA)EasilyexpandableindepthandwidthIndependentReadandWriteClocks(permitreadingandwritingsimultaneously)High-performancesubmicronCMOStechnologyIndustrialtemperaturerange(–40°°°°°Cto+85°°°°°C)isavailableINPUTREGISTEROUTPUTREGISTERRAMARRAY1,024x36,2,048x364,096x36,8,192x3616,384x36,32,768x3665,536x36,131,072x36262,144x36FLAGLOGICFF/IRPAFEF/ORPAEHFREADPOINTERREADCONTROLLOGICWRITECONTROLLOGICWRITEPOINTERRESETLOGICWENWCLK/WRD0-Dn(x36,x18orx9)LDMRSRENRCLK/RDOEQ0-Qn(x36,x18orx9)OFFSETREGISTERPRSFWFT/SISENRT5907drw01BUSCONFIGURATIONBMCONTROLLOGICBEOWIPPFMFSEL0FSEL1IWMARKSCLKRCSJTAGCONTROL(BOUNDARYSCAN)TCKTMSTDOTDITRSTASYRWCSERCLKERENHSTLI/0CONTROLVrefWHSTLRHSTLASYWSHSTLFUNCTIONALBLOCKDIAGRAM2COMMERCIALANDINDUSTRIALTEMPERATURERANGESIDT72T3645/55/65/75/85/95/105/115/1252.
5VTeraSync36-BITFIFO1Kx36,2Kx36,4Kx36,8Kx36,16Kx36,32Kx36,64Kx36,128Kx36and256Kx36PINCONFIGURATIONABCDEFGHJKLMNPRTWCSSCLKVREFSEND33D31D29D14D11D9D10D8PRSTCKFWFT/SIASYRSHSTLBETDIRHSTLRTTMSEFD3PAEWCLKTRSTMRSD0D5VCCD7RENRCLKRCSQ32Q30Q2812345678910111213141516A1BALLPADCORNERVDDQVCCVCCVCCVCCVCCGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDHFLDVCCVCCVCCVCCVCCD13IPBMVDDQVCCD27D24D22D20D18D16IWD34D32D30D28D26D23D25D21D19D17D15D12D1Q12Q10Q8Q26Q24Q21Q19Q17Q15ERCLKQ1Q3Q9Q7Q5PFMMARKERENVCCVCCVCCVCCVCCASYWWHSTLFFVCCVCCVCCVCCVDDQVCCVDDQVDDQQ35VDDQVDDQVDDQGNDVCCGNDVCCGNDGNDGNDGNDQ33VCCVDDQVDDQGNDGNDGNDVCCVDDQVDDQQ4VCCGNDGNDGNDD6D2D4TDOQ2Q0Q6Q11Q23Q22Q20Q18Q16Q13Q31Q29Q27Q25VCCGNDGNDGNDGNDGNDVCCGNDGNDVCCGNDVCCGNDGNDGNDGNDVCCVCCVCCVCCVCCVDDQVCCVDDQVDDQVDDQQ14VDDQWENOEQ34D35OWFSIPAFFSOVCC5907drw02IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695OnlyPBGA:1mmpitch,17mmx17mm(BB208-1,ordercode:BB)TOPVIEW3COMMERCIALANDINDUSTRIALTEMPERATURERANGESIDT72T3645/55/65/75/85/95/105/115/1252.
5VTeraSync36-BITFIFO1Kx36,2Kx36,4Kx36,8Kx36,16Kx36,32Kx36,64Kx36,128Kx36and256Kx36IDT72T36105/72T36115/72T36125OnlyPBGA:1mmpitch,19mmx19mm(BB240-1,ordercode:BB)TOPVIEWPINCONFIGURATION(CONTINUED)ABCDEFGHJKLMNPRTD21D19D20D13GNDTDOGNDD4TMSGNDD5D10D23D22D1Q24Q14GNDQ0Q2Q11Q8Q3GNDGNDGNDGNDGNDGNDGNDGNDGNDVCCVCCVCCVCCVCCVCCVCCD24VCCGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDVCCRENGNDPAFERENVDDQOERCLKVCCVCCVCCVDDQVDDQVDDQVDDQVDDQVDDQ12345678910111213141516A1BALLPADCORNERMRSVCCVCCD35D32D29D26FFEFVCCVCCVCCD33D30D27VCCVCCVCCVCCSENVCCVCCVCCD34D31D28D25Q27VDDQVDDQVDDQVDDQQ33Q30RCSVDDQVDDQVCCVCCVCCSCLKVCCVCCVCCVCCWCSVCCVCCVCCPAELDHFGNDVDDQMARKVDDQRTSHSTLFWFT/SIFS0OWIPFS1BEGNDPFMBMASYRRHSTLGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDWHSTLASYWVREFIWGNDGNDGNDGNDVCCVDDQVDDQVCCWENGNDWCLKPRSVCC5907drw02AUVD18VCCD16D15TDITCKTRSTD6D0D2D9D12D14D17D3Q15Q16GNDERCLKQ4Q13Q10Q7Q5D11D8D7GNDQ6Q1Q9Q121718Q22Q20Q21Q23VDDQVDDQVDDQVDDQVDDQVDDQQ25VDDQVDDQVDDQQ34Q31Q28VDDQVDDQVDDQVDDQVDDQQ35Q32Q29Q26VDDQVDDQVDDQVDDQVDDQVDDQQ19VDDQQ17Q184COMMERCIALANDINDUSTRIALTEMPERATURERANGESIDT72T3645/55/65/75/85/95/105/115/1252.
5VTeraSync36-BITFIFO1Kx36,2Kx36,4Kx36,8Kx36,16Kx36,32Kx36,64Kx36,128Kx36and256Kx36DESCRIPTION:TheIDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/72T36125areexceptionallydeep,extrememlyhighspeed,CMOSFirst-In-First-Out(FIFO)memorieswithclockedreadandwritecontrolsandaflexibleBus-Matchingx36/x18/x9dataflow.
TheseFIFOsofferseveralkeyuserbenefits:Flexiblex36/x18/x9Bus-MatchingonbothreadandwriteportsAuserselectableMARKlocationforretransmitUserselectableI/OstructureforHSTLorLVTTLAsynchronous/SynchronoustranslationonthereadorwriteportsThefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoanemptyFIFOtothetimeitcanberead,isfixedandshort.
Highdensityofferingsupto9MbitBus-MatchingTeraSyncFIFOsareparticularlyappropriatefornetwork,video,telecommunications,datacommunicationsandotherapplicationsthatneedtobufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhasadatainputport(Dn)andadataoutputport(Qn),bothofwhichcanassumeeithera36-bit,18-bitora9-bitwidthasdeterminedbythestateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-Matching(BM)pinduringtheMasterResetcycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,orAsynchronousinterface.
DuringSynchronousoperationtheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input.
DatapresentontheDndatainputsiswrittenintotheFIFOoneveryrisingedgeofWCLKwhenWENisasserted.
DuringAsynchronousoperationonlytheWRinputisusedtowritedataintotheFIFO.
DataiswrittenonarisingedgeofWR,theWENinputshouldbetiedtoitsactivestate,(LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,orAsynchronousinterface.
DuringSynchronousoperationtheoutputportiscontrolledbyaReadClock(RCLK)inputandReadEnable(REN)input.
DataisreadfromtheFIFOoneveryrisingedgeofRCLKwhenRENisasserted.
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromtheFIFO.
DataisreadonarisingedgeofRD,theRENinputshouldbetiedtoitsactivestate,LOW.
WhenAsynchronousoperationisselectedontheoutputporttheFIFOmustbeconfiguredforStandardIDTmode,alsotheRCSshouldbetiedLOWandtheOEinputusedtoprovidethree-statecontroloftheoutputs,Qn.
Theoutputportcanbeselectedforeither2.
5VLVTTLorHSTLoperation,thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset.
AnOutputEnable(OE)inputisprovidedforthree-statecontroloftheoutputs.
AReadChipSelect(RCS)inputisalsoprovided,theRCSinputissynchronizedtothereadclock,andalsoprovidesthree-statecontroloftheQndataoutputs.
WhenRCSisdisabled,thedataoutputswillbehighimpedance.
DuringAsynchronousoperationoftheoutputport,RCSshouldbeenabled,heldLOW.
EchoReadEnable,ERENandEchoReadClock,ERCLKoutputsareprovided.
TheseareoutputsfromthereadportoftheFIFOthatarerequiredforhighspeeddatacommunication,toprovidetightersynchronizationbetweenthedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedbytheinputdevice.
DatareadfromthereadportisavailableontheoutputbuswithrespecttoERENandERCLK,thisisveryusefulwhendataisbeingreadathighspeed.
TheERCLKandERENoutputsarenon-functionalwhentheReadportissetupforAsynchronousmode.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0tofMAXwithcompleteindependence.
Therearenorestrictionsonthefrequencyoftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDTStandardmodeandFirstWordFallThrough(FWFT)mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappearonthedataoutputlinesunlessaspecificreadoperationisperformed.
Areadoperation,whichconsistsofactivatingRENandenablingarisingRCLKedge,willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlytothedataoutputlinesafterthreetransitionsoftheRCLKsignal.
ARENdoesnothavetobeassertedforaccessingthefirstword.
However,subsequentwordswrittentotheFIFOdorequireaLOWonRENforaccess.
ThestateoftheFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcanprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOsinseries(i.
e.
thedataoutputsofoneFIFOareconnectedtothecorrespondingdatainputsofthenext).
Noexternallogicisrequired.
TheseFIFOshavefiveflagpins,EF/OR(EmptyFlagorOutputReady),FF/IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(ProgrammableAlmost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag).
TheEFandFFfunctionsareselectedinIDTStandardmode.
TheIRandORfunctionsareselectedinFWFTmode.
HF,PAEandPAFarealwaysavailableforuse,irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointinmemory.
Programmableoffsetsdeterminetheflagswitchingthresholdandcanbeloadedbytwomethods:parallelorserial.
Eightdefaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchatapredefinednumberoflocationsfromtheemptyboundaryandthePAFthresholdcanalsobesetatsimilarpredefinedvaluesfromthefullboundary.
ThedefaultoffsetvaluesaresetduringMasterResetbythestateoftheFSEL0,FSEL1,andLDpins.
Forserialprogramming,SENtogetherwithLDoneachrisingedgeofSCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI).
Forparallelprogramming,WENtogetherwithLDoneachrisingedgeofWCLK,areusedtoloadtheoffsetregistersviaDn.
RENtogetherwithLDoneachrisingedgeofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhetherserialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur:thereadandwritepointersaresettothefirstlocationoftheFIFO.
TheFWFTpinselectsIDTStandardmodeorFWFTmode.
ThePartialReset(PRS)alsosetsthereadandwritepointerstothefirstlocationofthememory.
However,thetimingmode,programmableflagprogrammingmethod,anddefaultorprogrammedoffsetsettingsexistingbeforePartialResetremainunchanged.
Theflagsareupdatedaccordingtothetimingmodeandoffsetsineffect.
PRSisusefulforresettingadeviceinmid-operation,whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag)outputs.
ThetimingmodescanbesettobeeitherasynchronousorsynchronousforthePAEandPAFflags.
IfasynchronousPAE/PAFconfigurationisselected,thePAEisassertedLOWontheLOW-to-HIGHtransitionofRCLK.
PAEisresettoHIGHontheLOW-to-HIGHtransitionofWCLK.
Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKandPAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedandupdatedontherisingedgeofRCLKonlyandnotWCLK.
Similarly,PAFisassertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.
ThemodedesiredisconfiguredduringMasterResetbythestateoftheProgrammableFlagMode(PFM)pin.
5COMMERCIALANDINDUSTRIALTEMPERATURERANGESIDT72T3645/55/65/75/85/95/105/115/1252.
5VTeraSync36-BITFIFO1Kx36,2Kx36,4Kx36,8Kx36,16Kx36,32Kx36,64Kx36,128Kx36and256Kx36DESCRIPTION(CONTINUED)ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrolinputs,MARKand,RT(Retransmit).
IftheMARKinputisenabledwithrespecttotheRCLK,thememorylocationbeingreadatthatpointwillbemarked.
Anysubsequentretransmitoperation,RTgoesLOW,willresetthereadpointertothis'marked'location.
ThedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsasshowninTable1.
ABig-Endian/Little-Endiandatawordformatisprovided.
ThisfunctionisusefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andreadoutoftheFIFOinsmallword(x18/x9)format.
IfBig-Endianmodeisselected,thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillbereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.
IfLittle-Endianformatisselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFOwillbereadoutfirst,followedbythemostsignificantbyte.
ThemodedesiredisconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.
SeeFigure5forBus-MatchingByteArrangement.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheusertoselecttheparitybitinthewordloadedintotheparallelport(D0-Dn)whenprogrammingtheflagoffsets.
IfInterspersedParitymodeisselected,thentheFIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26andD35duringtheparallelprogrammingoftheflagoffsets.
IfNon-InterspersedParitymodeisselected,thenD8,D17andD26areassumedtobevalidbitsandD32,D33,D34andD35areignored.
IPmodeisselectedduringMasterResetbythestateoftheIPinputpin.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwillautomaticallypowerdown.
Onceinthepowerdownstate,thestandbysupplycurrentconsumptionisminimized.
Initiatinganyoperation(byactivatingcontrolinputs)willimmediatelytakethedeviceoutofthepowerdownstate.
BothanAsynchronousOutputEnablepin(OE)andSynchronousReadChipSelectpin(RCS)areprovidedontheFIFO.
TheSynchronousReadChipSelectissynchronizedtotheRCLK.
BoththeoutputenableandreadchipselectcontroltheoutputbufferoftheFIFO,causingthebuffertobeeitherHIGHimpedanceorLOWimpedance.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundaryScanfeature,compliantwithIEEE1449.
1StandardTestAccessPortandBoundaryScanArchitecture.
TheTeraSyncFIFOhasthecapabilityofoperatingitsports(writeand/orread)ineitherLVTTLorHSTLmode,eachportsselectionindependentoftheother.
ThewriteportselectionismadeviaWHSTLandthereadportselectionviaRHSTL.
AnadditionalinputSHSTLisalsoprovided,thisallowstheusertoselectHSTLoperationforotherpinsonthedevice(notassociatedwiththewriteorreadports).
TheIDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/72T36125arefabricatedusingIDT'shighspeedsub-micronCMOStechnology.
6COMMERCIALANDINDUSTRIALTEMPERATURERANGESIDT72T3645/55/65/75/85/95/105/115/1252.
5VTeraSync36-BITFIFO1Kx36,2Kx36,4Kx36,8Kx36,16Kx36,32Kx36,64Kx36,128Kx36and256Kx36BMIWOWWritePortWidthReadPortWidthLLLx36x36HLLx36x18HLHx36x9HHLx18x36HHHx9x36TABLE1—BUS-MATCHINGCONFIGURATIONMODESNOTE:1.
PinstatusduringMasterReset.
Figure1.
SingleDeviceConfigurationSignalFlowDiagram(x36,x18,x9)DATAOUT(Q0-Qn)(x36,x18,x9)DATAIN(D0-Dn)MASTERRESET(MRS)READCLOCK(RCLK/RD)READENABLE(REN)OUTPUTENABLE(OE)EMPTYFLAG/OUTPUTREADY(EF/OR)PROGRAMMABLEALMOST-EMPTY(PAE)WRITECLOCK(WCLK/WR)WRITEENABLE(WEN)LOAD(LD)FULLFLAG/INPUTREADY(FF/IR)PROGRAMMABLEALMOST-FULL(PAF)IDT72T364572T365572T366572T367572T368572T369572T3610572T3611572T36125PARTIALRESET(PRS)FIRSTWORDFALLTHROUGH/SERIALINPUT(FWFT/SI)RETRANSMIT(RT)5907drw03HALF-FULLFLAG(HF)SERIALENABLE(SEN)INPUTWIDTH(IW)OUTPUTWIDTH(OW)BIG-ENDIAN/LITTLE-ENDIAN(BE)INTERSPERSED/NON-INTERSPERSEDPARITY(IP)BUS-MATCHING(BM)SERIALCLOCK(SCLK)MARKREADCHIPSELECT(RCS)RCLKECHO,ERCLKRENECHO,ERENWRITECHIPSELECT(WCS)7COMMERCIALANDINDUSTRIALTEMPERATURERANGESIDT72T3645/55/65/75/85/95/105/115/1252.
5VTeraSync36-BITFIFO1Kx36,2Kx36,4Kx36,8Kx36,16Kx36,32Kx36,64Kx36,128Kx36and256Kx36PINDESCRIPTIONASYR(1)AsynchronousLVTTLAHIGHonthisinputduringMasterResetwillselectSynchronousreadoperationfortheoutputport.
ALOWReadPortINPUTwillselectAsynchronousoperation.
IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.

ASYW(1)AsynchronousLVTTLAHIGHonthisinputduringMasterResetwillselectSynchronouswriteoperationfortheinputport.
ALOWWritePortINPUTwillselectAsynchronousoperation.
BE(1)Big-Endian/LVTTLDuringMasterReset,aLOWonBEwillselectBig-Endianoperation.
AHIGHonBEduringMasterResetLittle-EndianINPUTwillselectLittle-Endianformat.
BM(1)Bus-MatchingLVTTLBMworkswithIWandOWtoselectthebussizesforbothwriteandreadports.
SeeTable1forbussizeINPUTconfiguration.
D0–D35DataInputsHSTL-LVTTLDatainputsfora36-,18-or9-bitbus.
Whenin18-or9-bitmode,theunusedinputpinsshouldbetiedtoGND.
INPUTEF/OREmptyFlag/HSTL-LVTTLIntheIDTStandardmode,theEFfunctionisselected.
EFindicateswhetherornottheFIFOmemoryisempty.
OutputReadyOUTPUTInFWFTmode,theORfunctionisselected.
ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
ERCLKRCLKEchoHSTL-LVTTLReadclockEchooutput,onlyavailablewhentheReadissetupforSynchronousmode.
OUTPUTERENReadEnableEchoHSTL-LVTTLReadEnableEchooutput,onlyavailablewhentheReadissetupforSynchronousmode.
OUTPUTFF/IRFullFlag/HSTL-LVTTLIntheIDTStandardmode,theFFfunctionisselected.
FFindicateswhetherornottheFIFOmemoryisInputReadyOUTPUTfull.
IntheFWFTmode,theIRfunctionisselected.
IRindicateswhetherornotthereisspaceavailableforwritingtotheFIFOmemory.
FSEL0(1)FlagSelectBit0LVTTLDuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesfortheINPUTprogrammableflagsPAEandPAF.
Thereareuptoeightpossiblesettingsavailable.
FSEL1(1)FlagSelectBit1LVTTLDuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesfortheINPUTprogrammableflagsPAEandPAF.
Thereareuptoeightpossiblesettingsavailable.
FWFT/FirstWordFallHSTL-LVTTLDuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.
AfterMasterReset,thispinSIThrough/SerialInINPUTfunctionsasaserialinputforloadingoffsetregisters.
IfAsynchronousoperationofthereadporthasbeenselectedthentheFIFOmustbeset-upinIDTStandardmode.
HFHalf-FullFlagHSTL-LVTTLHFindicateswhethertheFIFOmemoryismoreorlessthanhalf-full.
OUTPUTIP(1)InterspersedParityLVTTLDuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.
AHIGHwillselectInterspersedINPUTParitymode.
IW(1)InputWidthLVTTLThispin,alongwithOWandBM,selectsthebuswidthofthewriteport.
SeeTable1forbussizeconfiguration.

INPUTLDLoadHSTL-LVTTLThisisadualpurposepin.
DuringMasterReset,thestateoftheLDinputalongwithFSEL0andFSEL1,INPUTdeterminesoneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscanbeprogrammed,parallelorserial(seeTable2).
AfterMasterReset,thispinenableswritingtoandreadingfromtheoffsetregisters.
THISPINMUSTBEHIGHAFTERMASTERRESETTOWRITEORREADDATATO/FROMTHEFIFOMEMORY.
MARKMarkforRetransmitHSTL-LVTTLWhenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.
AnysubsequentRetransmitINPUToperationwillresetthereadpointertothisposition.
MRSMasterResetHSTL-LVTTLMRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.
DuringMasterINPUTReset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OEOutputEnableHSTL-LVTTLOEprovidesAsynchronousthree-statecontrolofthedataoutputs,Qn.
DuringaMasterorPartialResettheINPUTOEinputistheonlyinputthatprovideHigh-Impedancecontrolofthedataoutputs.
OW(1)OutputWidthLVTTLThispin,alongwithIWandBM,selectsthebuswidthofthereadport.
SeeTable1forbussizeconfiguration.
INPUTPAEProgrammableHSTL-LVTTLPAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmptyAlmost-EmptyFlagOUTPUTOffsetregister.
PAEgoesHIGHifthenumberofwordsintheFIFOmemoryisgreaterthanorequaltooffsetn.
PAFProgrammableHSTL-LVTTLPAFgoesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstoredintheAlmost-FullFlagOUTPUTFullOffsetregister.
PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthanorequaltom.

PFM(1)ProgrammableLVTTLDuringMasterReset,aLOWonPFMwillselectAsynchronousProgrammableflagtimingmode.
AHIGHonFlagModeINPUTPFMwillselectSynchronousProgrammableflagtimingmode.
SymbolNameI/OTYPEDescription8COMMERCIALANDINDUSTRIALTEMPERATURERANGESIDT72T3645/55/65/75/85/95/105/115/1252.
5VTeraSync36-BITFIFO1Kx36,2Kx36,4Kx36,8Kx36,16Kx36,32Kx36,64Kx36,128Kx36and256Kx36PINDESCRIPTION(CONTINUED)SymbolNameI/OTYPEDescriptionPRSPartialResetHSTL-LVTTLPRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.
DuringPartialReset,INPUTtheexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
Q0–Q35DataOutputsHSTL-LVTTLDataoutputsforan36-,18-or9-bitbus.
Whenin18-or9-bitmode,anyunusedoutputpinsshouldnotOUTPUTbeconnected.
Outputsarenot5VtolerantregardlessofthestateofOEandRCS.
RCLK/ReadClock/HSTL-LVTTLIfSynchronousoperationofthereadporthasbeenselected,whenenabledbyREN,therisingedgeofRCLKRDReadStobeINPUTreadsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.
IfLDisLOW,thevaluesloadedintotheoffsetregistersisoutputonarisingedgeofRCLK.
IfAsynchronousoperationofthereadporthasbeenselected,arisingedgeonRDreadsdatafromtheFIFOinanAsynchronousmanner.
RENshouldbetiedLOW.
RCSReadChipSelectHSTL-LVTTLRCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.
DuringINPUTaMasterResetorPartialResettheRCSinputisdon'tcare,ifOEisLOWthedataoutputswillbeLow-ImpedanceregardlessofRCS.
RENReadEnableHSTL-LVTTLIfSynchronousoperationofthereadporthasbeenselected,RENenablesRCLKforreadingdatafromtheINPUTFIFOmemoryandoffsetregisters.
IfAsynchronousoperationofthereadporthasbeenselected,theRENinputshouldbetiedLOW.
RHSTL(1)ReadPortHSTLLVTTLThispinisusedtoselectHSTLor2.
5vLVTTLoutputsfortheFIFO.
IfHSTLoreHSTLoutputsareSelectINPUTrequired,thisinputmustbetiedHIGH.
OtherwiseitshouldbetiedLOW.
RTRetransmitHSTL-LVTTLRTassertedontherisingedgeofRCLKinitializestheREADpointertozero,setstheEFflagtoLOW(ORtoINPUTHIGHinFWFTmode)anddoesn'tdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammableflagsettings.
IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwilljumptothe'mark'location.
SCLKSerialClockHSTL-LVTTLArisingedgeonSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregistersprovidingthatINPUTSENisenabled.
SENSerialEnableHSTL-LVTTLSENenablesserialloadingofprogrammableflagoffsets.
INPUTSHSTLSystemHSTLLVTTLAllinputsnotassociatedwiththewriteorreadportcanbeselectedforHSTLoperationviatheSHSTLinput.
SelectINPUTTCK(2)JTAGClockHSTL-LVTTLClockinputforJTAGfunction.
OneoffourterminalsrequiredbyIEEEStandard1149.
1-1990.
TestoperationsINPUTofthedevicearesynchronoustoTCK.
DatafromTMSandTDIaresampledontherisingedgeofTCKandoutputschangeonthefallingedgeofTCK.
IftheJTAGfunctionisnotusedthissignalneedstobetiedtoGND.
TDI(2)JTAGTestDataHSTL-LVTTLOneoffourterminalsrequiredbyIEEEStandard1149.
1-1990.
DuringtheJTAGboundaryscanoperation,InputINPUTtestdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
TDO(2)JTAGTestDataHSTL-LVTTLOneoffourterminalsrequiredbyIEEEStandard1149.
1-1990.
DuringtheJTAGboundaryscanoperation,OutputOUTPUTtestdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypassRegister.
Thisoutputishighimpedanceexceptwhenshifting,whileinSHIFT-DRandSHIFT-IRcontrollerstates.
TMS(2)JTAGModeHSTL-LVTTLTMSisaserialinputpin.
OneoffourterminalsrequiredbyIEEEStandard1149.
1-1990.
TMSdirectstheSelectINPUTthedevicethroughitsTAPcontrollerstates.
Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.