Edgencsetting

8BitMicrocontrollerTLCS-870/XSeriesTMP88CS42NGTheinformationcontainedhereinissubjecttochangewithoutnotice.
021023_DTOSHIBAiscontinuallyworkingtoimprovethequalityandreliabilityofitsproducts.
Nevertheless,semiconductordevicesingeneralcanmalfunctionorfailduetotheirinherentelectricalsensitivityandvulnerabilitytophysicalstress.
Itistheresponsibilityofthebuyer,whenutilizingTOSHIBAproducts,tocomplywiththestandardsofsafetyinmakingasafedesignfortheentiresystem,andtoavoidsituationsinwhichamalfunctionorfailureofsuchTOSHIBAproductscouldcauselossofhumanlife,bodilyinjuryordamagetoproperty.
Indevelopingyourdesigns,pleaseensurethatTOSHIBAproductsareusedwithinspecifiedoperatingrangesassetforthinthemostrecentTOSHIBAproductsspecifications.
Also,pleasekeepinmindtheprecautionsandconditionssetforthinthe"HandlingGuideforSemiconductorDevices,"or"TOSHIBASemiconductorReliabilityHandbook"etc.
021023_ATheTOSHIBAproductslistedinthisdocumentareintendedforusageingeneralelectronicsapplications(computer,personalequipment,officeequipment,measuringequipment,industrialrobotics,domesticappliances,etc.
).
TheseTOSHIBAproductsareneitherintendednorwarrantedforusageinequipmentthatrequiresextraordinarilyhighqualityand/orreliabilityoramalfunctionorfailureofwhichmaycauselossofhumanlifeorbodilyinjury("UnintendedUsage").
UnintendedUsageincludeatomicenergycontrolinstruments,airplaneorspaceshipinstruments,transportationinstruments,trafficsignalinstruments,combustioncontrolinstruments,medicalinstruments,alltypesofsafetydevices,etc.
UnintendedUsageofTOSHIBAproductslistedinthisdocumentshallbemadeatthecustomer'sownrisk.
021023_BTheproductsdescribedinthisdocumentshallnotbeusedorembeddedtoanydownstreamproductsofwhichmanufacture,useand/orsaleareprohibitedunderanyapplicablelawsandregulations.
060106_QTheinformationcontainedhereinispresentedonlyasaguidefortheapplicationsofourproducts.
NoresponsibilityisassumedbyTOSHIBAforanyinfringementsofpatentsorotherrightsofthethirdpartieswhichmayresultfromitsuse.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentsorotherrightsofTOSHIBAorthethirdparties.
070122_CTheproductsdescribedinthisdocumentaresubjecttoforeignexchangeandforeigntradecontrollaws.
060925_EForadiscussionofhowthereliabilityofmicrocontrollerscanbepredicted,pleaserefertoSection1.
3ofthechapterentitledQualityandReliabilityAssurance/HandlingPrecautions.
030619_S2008TOSHIBACORPORATIONAllRightsReservedRevisionHistoryDateRevision2007/7/131FirstRelease2008/2/252ContentsRevised2008/9/303ContentsRevisedCautioninSettingtheUARTNoiseRejectionTimeWhenUARTisused,settingsofRXDNCarelimiteddependingonthetransferclockspecifiedbyBRG.
Thecom-bination"O"isavailablebutpleasedonotselectthecombination"–".
Thetransferclockgeneratedbytimer/counterinterruptiscalculatedbythefollowingequation:Transferclock[Hz]=Timer/countersourceclock[Hz]÷TTREGsetvalueBRGsettingTransferclock[Hz]RXDNCsetting00(Nonoiserejection)01(Rejectpulsesshorterthan31/fc[s]asnoise)10(Rejectpulsesshorterthan63/fc[s]asnoise)11(Rejectpulsesshorterthan127/fc[s]asnoise)000fc/13OOO–110(Whenthetransferclockgen-eratedbytimer/counterinter-ruptisthesameastherightsidecolumn)fc/8O–––fc/16OO––fc/32OOO–ThesettingexcepttheaboveOOOOiTableofContentsTMP88CS42NG1.
1Features11.
2PinAssignment31.
3BlockDiagram41.
4PinNamesandFunctions52.
FunctionalDescription2.
1FunctionsoftheCPUCore92.
1.
1MemoryAddressMap.
92.
1.
2ProgramMemory(ROM)102.
1.
3DataMemory(RAM)102.
1.
4SystemClockControlCircuit112.
1.
4.
1ClockGenerator2.
1.
4.
2TimingGenerator2.
1.
4.
3StandbyControlCircuit2.
1.
4.
4ControllingOperationModes2.
1.
5ResetCircuit232.
1.
5.
1ExternalResetInput2.
1.
5.
2AdressTrapReset2.
1.
5.
3WatchdogTimerReset2.
1.
5.
4SystemClockReset3.
InterruptControlCircuit3.
1Interruptlatches(IL38toIL2)263.
2Interruptenableregister(EIR)273.
2.
1Interruptmasterenableflag(IMF)273.
2.
2Individualinterruptenableflags(EF38toEF3)273.
3InterruptSequence303.
3.
1Interruptacceptanceprocessingispackagedasfollows.
303.
3.
2Saving/restoringgeneral-purposeregisters.
313.
3.
2.
1UsingAutomaticregisterbankswitcing3.
3.
2.
2Usingregisterbankswitching3.
3.
2.
3UsingPUSHandPOPinstructions3.
3.
2.
4Usingdatatransferinstructions3.
3.
3Interruptreturn333.
4SoftwareInterrupt(INTSW)343.
4.
1Addresserrordetection343.
4.
2Debugging343.
5ExternalInterrupts354.
SpecialFunctionRegister4.
1SFR374.
2DBR39ii5.
Input/OutputPorts5.
1PortP0(P03toP00)455.
2PortP1(P17toP10)465.
3PortP2(P22toP20)475.
4PortP3(P37toP30)485.
5PortP4(P47toP40)495.
6PortP5(P57toP50)505.
7PortP6(P67toP60)515.
8PortP7(P77toP70)536.
TimeBaseTimer(TBT)andDividerOutput(DVO)6.
1TimeBaseTimer556.
2DividerOutput(DVO)577.
WatchdogTimer(WDT)7.
1WatchdogTimerConfiguration597.
2WatchdogTimerControl607.
2.
1MalfunctionDetectionMethodsUsingtheWatchdogTimer.
607.
2.
2WatchdogTimerEnable617.
2.
3WatchdogTimerDisable627.
2.
4WatchdogTimerInterrupt(INTWDT)627.
2.
5WatchdogTimerReset638.
16-BitTimerCounter1(TC1)8.
1Configuration658.
2TimerCounterControl668.
3Function.
688.
3.
1Timermode.
688.
3.
2ExternalTriggerTimerMode708.
3.
3EventCounterMode.
728.
3.
4WindowMode738.
3.
5PulseWidthMeasurementMode.
748.
3.
6ProgrammablePulseGenerate(PPG)OutputMode779.
16-BitTimer(CTC)9.
1Configuration819.
2Control.
829.
3Function.
859.
3.
1Timermodewithsoftwarestart.
859.
3.
2Timermodewithexternaltriggerstart869.
3.
3Eventcountermode.
879.
3.
4ProgrammablePulseGenerate(PPG)outputmode88iii10.
8-BitTimerCounter3(TC3)10.
1Configuration9510.
2TimerCounterControl9610.
3Function.
9710.
3.
1Timermode.
97Figure10-39910.
3.
3CaptureMode10011.
8-BitTimerCounter4(TC4)11.
1Configuration10111.
2TimerCounterControl10211.
3Function.
10311.
3.
1TimerMode.
10311.
3.
2EventCounterMode.
10311.
3.
3ProgrammableDividerOutput(PDO)Mode10311.
3.
4PulseWidthModulation(PWM)OutputMode10412.
8-BitTimerCounter5,6(TC5,6)12.
1Configuration10712.
2TimerCounterControl10812.
3Function.
11212.
3.
18-BitTimerMode(TC5and6)11212.
3.
28-BitEventCounterMode(TC5,6)11312.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC5,6)11312.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC5,6)11512.
3.
516-BitTimerMode(TC5and6)11712.
3.
616-BitEventCounterMode(TC5and6)11812.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC5and6)11812.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC5and6)12113.
MotorControlCircuit(PMD:Programmablemotordriver)13.
1OutlineofMotorControl12413.
2ConfigurationoftheMotorControlCircuit12613.
3PositionDetectionUnit12713.
3.
1Configurationofthepositiondetectionunit.
12813.
3.
2PositionDetectionCircuitRegisterFunctions.
12913.
3.
3OutlineProcessinginthePositionDetectionUnit13213.
4TimerUnit13313.
4.
1ConfigurationoftheTimerUnit.
13413.
4.
1.
1TimerCircuitRegisterFunctions13.
4.
1.
2OutlineProcessingintheTimerUnit13.
5Three-phasePWMOutputUnit13813.
5.
1Configurationofthethree-phasePWMoutputunit.
13813.
5.
1.
1Pulsewidthmodulationcircuit(PWMwaveformgeneratingunit)13.
5.
1.
2Commutationcontrolcircuit13.
5.
2RegisterFunctionsoftheWaveformSynthesisCircuit.
14213.
5.
3PortoutputassetwithUOC/VOC/WOCbitsandUPWM/VPWM/WPWMbits.
14413.
5.
4ProtectiveCircuit.
14613.
5.
5FunctionsofProtectiveCircuitRegisters.
14813.
6ElectricalAngleTimerandWaveformArithmeticCircuit150iv13.
6.
1ElectricalAngleTimerandWaveformArithmeticCircuit15113.
6.
1.
1FunctionsoftheElectricalAngleTimerandWaveformArithmeticCircuitRegisters13.
6.
1.
2ListofPMDRelatedControlRegisters14.
AsynchronousSerialinterface(UART)14.
1Configuration16314.
2Control16414.
3TransferDataFormat16614.
4TransferRate.
16714.
5DataSamplingMethod16714.
6STOPBitLength16814.
7Parity16814.
8Transmit/ReceiveOperation16814.
8.
1DataTransmitOperation16814.
8.
2DataReceiveOperation16814.
9StatusFlag16914.
9.
1ParityError.
16914.
9.
2FramingError.
16914.
9.
3OverrunError.
16914.
9.
4ReceiveDataBufferFull.
17014.
9.
5TransmitDataBufferEmpty17014.
9.
6TransmitEndFlag17115.
SynchronousSerialInterface(SIO)15.
1Configuration17315.
2Control17415.
3Serialclock17515.
3.
1Clocksource17515.
3.
1.
1Internalclock15.
3.
1.
2Externalclock15.
3.
2Shiftedge.
17715.
3.
2.
1Leadingedge15.
3.
2.
2Trailingedge15.
4Numberofbitstotransfer17715.
5Numberofwordstotransfer17715.
6TransferMode17815.
6.
14-bitand8-bittransfermodes.
17815.
6.
24-bitand8-bitreceivemodes18015.
6.
38-bittransfer/receivemode18116.
10-bitADConverter(ADC)16.
1Configuration18316.
2Registerconfiguration18416.
3Function.
18716.
3.
1SoftwareStartMode18716.
3.
2RepeatMode18716.
3.
3RegisterSetting188Example18916.
4STOPmodeduringADConversion.
18916.
5AnalogInputVoltageandADConversionResult19016.
6PrecautionsaboutADConverter.
191v16.
6.
1Analoginputpinvoltagerange19116.
6.
2Analoginputsharedpins19116.
6.
3NoiseCountermeasure.
19117.
8-BitHigh-speedPWM(HPWM0andHPWM1)17.
1Configuration19317.
2Control19417.
3FunctionalDescription19417.
3.
1Operationmodes19417.
3.
1.
18-bitmode17.
3.
1.
27-bitmode17.
3.
1.
36-bitmode17.
3.
2Settingoutputdata.
19718.
Input/OutputCircuitry18.
1Controlpins19918.
2Input/outputports.
20019.
ElectricalCharacteristics19.
1AbsoluteMaximumRatings.
20119.
2OperatingConditions.
20219.
3DCCharacteristics.
20219.
4ADConversionCharacteristics20319.
5ACCharacteristics.
20319.
520319.
520319.
520319.
6RecommendedOscillationConditions.
20419.
7HandlingPrecaution20420.
PackageDimensionsThisisatechnicaldocumentthatdescribestheoperatingfunctionsandelectricalspecificationsofthe8-bitmicrocontrollerseriesTLCS-870/X(LSI).
viPage1TMP88CS42NGCMOS8-BitMicrocontrollerTheinformationcontainedhereinissubjecttochangewithoutnotice.
021023_DTOSHIBAiscontinuallyworkingtoimprovethequalityandreliabilityofitsproducts.
Nevertheless,semiconductordevicesingeneralcanmalfunctionorfailduetotheirinherentelectricalsensitivityandvulnerabilitytophysicalstress.
Itistheresponsibilityofthebuyer,whenutilizingTOSHIBAproducts,tocomplywiththestandardsofsafetyinmakingasafedesignfortheentiresystem,andtoavoidsituationsinwhichamalfunctionorfailureofsuchTOSHIBAproductscouldcauselossofhumanlife,bodilyinjuryordamagetoproperty.
Indevelopingyourdesigns,pleaseensurethatTOSHIBAproductsareusedwithinspecifiedoperatingrangesassetforthinthemostrecentTOSHIBAproductsspecifications.
Also,pleasekeepinmindtheprecautionsandconditionssetforthinthe"HandlingGuideforSemiconductorDevices,"or"TOSHIBASemiconductorReliabilityHandbook"etc.
021023_ATheTOSHIBAproductslistedinthisdocumentareintendedforusageingeneralelectronicsapplications(computer,personalequip-ment,officeequipment,measuringequipment,industrialrobotics,domesticappliances,etc.
).
TheseTOSHIBAproductsareneitherintendednorwarrantedforusageinequipmentthatrequiresextraordinarilyhighqualityand/orreliabilityoramalfunctionorfailureofwhichmaycauselossofhumanlifeorbodilyinjury("UnintendedUsage").
UnintendedUsageincludeatomicenergycontrolinstruments,airplaneorspaceshipinstruments,transportationinstruments,trafficsignalinstruments,combustioncontrolinstruments,medicalinstru-ments,alltypesofsafetydevices,etc.
UnintendedUsageofTOSHIBAproductslistedinthisdocumentshallbemadeatthecustomer'sownrisk.
021023_BTheproductsdescribedinthisdocumentshallnotbeusedorembeddedtoanydownstreamproductsofwhichmanufacture,useand/orsaleareprohibitedunderanyapplicablelawsandregulations.
060106_QTheinformationcontainedhereinispresentedonlyasaguidefortheapplicationsofourproducts.
NoresponsibilityisassumedbyTOSHIBAforanyinfringementsofpatentsorotherrightsofthethirdpartieswhichmayresultfromitsuse.
Nolicenseisgrantedbyimpli-cationorotherwiseunderanypatentsorotherrightsofTOSHIBAorthethirdparties.
070122_CTheproductsdescribedinthisdocumentaresubjecttoforeignexchangeandforeigntradecontrollaws.
060925_EForadiscussionofhowthereliabilityofmicrocontrollerscanbepredicted,pleaserefertoSection1.
3ofthechapterentitledQualityandReliabilityAssurance/HandlingPrecautions.
030619_STMP88CS42NG1.
1Features1.
8-bitsinglechipmicrocomputerTLCS-870/Xseries-Instructionexecutiontime:0.
20μs(at20MHz)-181types&842basicinstructions2.
35interruptsources(External:6Internal:29)3.
Input/Outputports(55pins)Largecurrentoutput:24pins(Typ.
20mA),LEDdirectdrive4.
Prescaler-TimebasetimerDivideroutputfunction(DVO)5.
WatchdogTimerSelectof"internalresetrequest"or"interruptrequest".
6.
16-bittimercounter:1ch-Timer,Externaltrigger,Window,Pulsewidthmeasurement,Eventcounter,Programmablepulsegenerate(PPG)modes7.
16-bittimer/counter(CTC):1ch-CTC:Timer,eventcounterorPPG(ProgrammablePulse)output8.
8-bittimercounter:1ch-Timer,Eventcounter,Capturemodes9.
8-bittimercounter:1chProductNo.
ROM(MaskROM)RAMPackageOTPMCUTMP88CS42NG65536bytes2176bytesSDIP64-P-750-1.
78TMP88PS42NGPage21.
1FeaturesTMP88CS42NG-Timer,Eventcounter,Pulsewidthmodulation(PWM)output,Programmabledivideroutput(PDO)modes10.
8-bittimercounter:2ch-Timer,Eventcounter,Programmabledivideroutput(PDO),Pulsewidthmodulation(PWM)output,Programmablepulsegeneration(PPG)modes11.
Programmablemotordriver(PMD):2ch-Sinewavedrivecircuit(built-insinewavedata-tableRAM)RotorpositiondetectfunctionMotorcontrotimerandcapturefunctionOverloadprotectivefunctionAutocommutationandautopositiondetectionstartfunction12.
8-bitUART:1ch13.
8-bitSIO:1ch14.
10-bitsuccessiveapproximationtypeADconverter-Analoginput:16ch15.
8-bitHigh-speedPWM(HPWM0andHPWM1)16.
Clockoscillationcircuit:1set17.
Lowpowerconsumptionoperation(2modes)-STOPmode:Oscillationstops.
(Battery/Capacitorback-up.
)-IDLEmode:CPUstops.
Onlyperipheralsoperateusinghighfrequencyclock.
Releasebyinterruputs(CPUrestarts).
18.
Operationvoltage:4.
5Vto5.
5Vat20MHzPage3TMP88CS42NG1.
2PinAssignmentFigure1-1PinAssignment12345678910111213141516171819202122232425262728293031326463626160595857565554535251504948474645444342414039383736353433P61(AIN1)P62(AIN2)P63(AIN3)P64(AIN4)P67(AIN7/DBOUT1)P70(AIN8)P71(AIN9)P72(AIN10)P66(AIN6)P65(AIN5)P73(AIN11)P74(AIN12)P75(AIN13)P76(AIN14)AVDDAVSSP00(RXD2/TC6)P01(TXD2/PDO6/PWM6/PPG6)VAREFP77(AIN15/DBOUT2)P02(HPWM0)P03(HPWM1)P10(INT0)P11(INT1)P14(PPG1/PWM5/PDO5)P15(PDU2)P13(TC5/DVO)P12(INT2/TC1)P16(PDV2)P17(PDW2)P50(CL2)P51(EMG2)(U2)P52(W2)P54(X2)P55(Y2)P56(Z2)P57VSSXINXOUTTESTVDD(V2)P53(TC3/INT3)P21RESET(STOP/INT5)P20(Z1)P30(X1)P32(W1)P33(V1)P34(U1)P35(PWM4/PDO4/TC4/INT4)P22(Y1)P31(PDV1)P41(SCK)P43(SI/RXD1)P44(PPG2)P46(SO/TXD1)P45(AIN0)P60(CTC)P47(PDU1)P42(PDW1)P40(CL1)P37(EMG1)P36Page41.
3BlockDiagramTMP88CS42NG1.
3BlockDiagramFigure1-2BlockDiagramPage5TMP88CS42NG1.
4PinNamesandFunctionsTable1-1PinNamesandFunctions(1/3)PinNamePinNumberInput/OutputFunctionsP03HPWM154IOOPORT03High-sppedPWM1outputP02HPWM053IOOPORT02High-sppedPWM0outputP01TXD2PDO6/PWM6/PPG652IOOOPORT01UARTdataoutput2PDO6/PWM6/PPG6outputP00RXD2TC651IOIIPORT00UARTdatainput2TC6inputP17PDW262IOIPORT17PMDcontrolinputW2P16PDV261IOIPORT16PMDcontrolinputV2P15PDU260IOIPORT15PMDcontrolinputU2P14PPG1PWM5/PDO559IOOOPORT14PPG1outputPWM5/PDO5outputP13TC5DVO58IOIOPORT13TC5inputDividerOutputP12INT2TC157IOIIPORT12Externalinterrupt2inputTC1inputP11INT156IOIPORT11Externalinterrupt1inputP10INT055IOIPORT10Externalinterrupt0inputP22INT4TC4PWM4/PDO413IOIIOPORT22Externalinterrupt4inputTC4inputPWM4/PDO4outputP21INT3TC312IOIIPORT21Externalinterrupt3inputTC3pininputP20INT5STOP15IOIIPORT20Externalinterrupt5inputSTOPmodereleasesignalinputP37CL123IOIPORT37PMDoverloadprotectioninput1P36EMG122IOIPORT36PMDemergencystopinput1P35U121IOOPORT35PMDcontroloutputU1Page61.
4PinNamesandFunctionsTMP88CS42NGP34V120IOOPORT34PMDcontroloutputV1P33W119IOOPORT33PMDcontroloutputW1P32X118IOOPORT32PMDcontroloutputX1P31Y117IOOPORT31PMDcontroloutputY1P30Z116IOOPORT30PMDcontroloutputZ1P47CTC31IOIPORT47CTCinputP46PPG230IOOPORT46PPG2outputP45TXD1SO29IOOOPORT45UARTdataoutput1SerialDataOutputP44RXD1SI28IOIIPORT44UARTdatainput1SerialDataInputP43SCK27IOIOPORT43SerialClockI/OP42PDU126IOIPORT42PMDcontrolinputU1P41PDV125IOIPORT41PMDcontrolinputV1P40PDW124IOIPORT40PMDcontrolinputW1P57Z26IOOPORT57PMDcontroloutputZ2P56Y25IOOPORT56PMDcontroloutputY2P55X24IOOPORT55PMDcontroloutputX2P54W23IOOPORT54PMDcontroloutputW2P53V22IOOPORT53PMDcontroloutputV2P52U21IOOPORT52PMDcontroloutputU2P51EMG264IOIPORT51PMDemergencystopinput2P50CL263IOIPORT50PMDoverloadprotectioninput2P67AIN7DBOUT139IOIOPORT67AnalogInput7PMDdebugoutput1Table1-1PinNamesandFunctions(2/3)PinNamePinNumberInput/OutputFunctionsPage7TMP88CS42NGP66AIN638IOIPORT66AnalogInput6P65AIN537IOIPORT65AnalogInput5P64AIN436IOIPORT64AnalogInput4P63AIN335IOIPORT63AnalogInput3P62AIN234IOIPORT62AnalogInput2P61AIN133IOIPORT61AnalogInput1P60AIN032IOIPORT60AnalogInput0P77AIN15DBOUT247IOIOPORT77AnalogInput15PMDdebugoutput2P76AIN1446IOIPORT76AnalogInput14P75AIN1345IOIPORT75AnalogInput13P74AIN1244IOIPORT74AnalogInput12P73AIN1143IOIPORT73AnalogInput11P72AIN1042IOIPORT72AnalogInput10P71AIN941IOIPORT71AnalogInput9P70AIN840IOIPORT70AnalogInput8XIN8IResonatorconnectingpinsforhigh-frequencyclockXOUT9OResonatorconnectingpinsforhigh-frequencyclockRESET14IResetsignalTEST10ITestpinforout-goingtestandtheSerialPROMmodecontrolpin.
Usuallyfixtolowlevel.
FixtohighlevelwhentheSerialPROMmodestarts.
VAREF48IAnalogBaseVoltageInputPinforA/DConversionAVDD49IAnalogPowerSupplyAVSS50IAnalogPowerSupplyVDD11I+5VVSS7I0(GND)Table1-1PinNamesandFunctions(3/3)PinNamePinNumberInput/OutputFunctionsPage81.
4PinNamesandFunctionsTMP88CS42NGPage9TMP88CS42NG2.
FunctionalDescription2.
1FunctionsoftheCPUCoreTheCPUcoreconsistsmainlyoftheCPU,systemclockcontrolcircuit,andinterruptcontrolcircuit.
ThischapterdescribestheCPUcore,programmemory,datamemory,andresetcircuitoftheTMP88CS42NG.
2.
1.
1MemoryAddressMapThememoryoftheTMP88CS42NGconsistsoffourblocks:ROM,RAM,SFR(SpecialFunctionRegisters),andDBR(DataBufferRegisters),whicharemappedintoone1-Mbyteaddressspace.
Thegeneral-purposeregistersconsistof16banks,whicharemappedintotheRAMaddressspace.
Figure2-1showsamemoryaddressmapoftheTMP88CS42NG.
Figure2-1MemoryaddressmapVectorTableforVectorCallInstructionsInterruptVectorTableInterruptVectorTableProgramMemoryROM(bytes)RAM(bytes)RAM(128bytes)SFRROM:Read-OnlyMemoryProgrammemoryVectorTableSFR:SpecialFunctionRegistersInput/outputportPeripheralhardwarecontrolregisterPeripheralhardwarestatusregisterSystemcontrolregisterInterruptcontrolregisterProgramstatuswordDBR:DataBufferRegistersInput/outputportPeripheralhardwarecontrolregisterPeripheralhardwarestatusregisterRAM:RandomAccessMemoryDatamemoryStackGeneral-purposeregisterbankRandom-AccessMemorySpecialFunctionRegisterGeneral-purposeRegisterBank(8registers*16banks)DataBufferRegister(peripheralhardwarecontrolregister/statusregister)64bytes64bytes64bytes128bytesbytesbytes128bytes00000H000C0H000BFH04000H0003FH00040H01FFFHFFFFFHFFF7FHFFF80HFFF40HFFF00HFFF3FHbytes2K204864K65280DBR01F80H13EFFH008BFH128Page102.
FunctionalDescription2.
1FunctionsoftheCPUCoreTMP88CS42NG2.
1.
2ProgramMemory(ROM)TheTMP88CS42NGcontains64Kbytesprogrammemory(MaskROM)locatedataddresses04000Hto13EFFHandaddressesFFF00HtoFFFFFH.
2.
1.
3DataMemory(RAM)TheTMP88CS42NGcontains2Kbytes+128bytesRAM.
Thefirst128byteslocation(00040Hto000BFH)oftheinternalRAMissharedwithageneral-purposeregisterbank.
Thecontentofthedatamemoryisindeterminateatpower-on,sobesuretoinitializeitintheinitializerou-tine.
Note:Becausegeneral-purposeregistersexistintheRAM,neverclearthecurrentbankaddressofRAM.
Intheaboveexample,theRAMisclearedexceptbank0.
Example:ClearingtheinternalRAMoftheTMP88CS42NG(clearallRAMaddressesto0,exceptbank0)LDHL,0048H;SetthestartaddressLDA,00H;Settheinitializationdata(00H)LDBC,877H;Setbytecounts(-1)SRAMCLR:LD(HL+),ADECBCJRSF,SRAMCLRPage11TMP88CS42NG2.
1.
4SystemClockControlCircuitTheSystemClockControlCircuitconsistsofaclockgenerator,timinggenerator,andstandbycontrolcir-cuit.
Figure2-2SystemClockControlCircuit2.
1.
4.
1ClockGeneratorTheClockGeneratorgeneratesthefundamentalclockwhichservesasthereferenceforthesystemclockssuppliedtotheCPUcoreandperipheralhardwareunits.
Thehigh-frequencyclock(frequencyfc)canbeobtainedeasilybyconnectingaresonatortotheXINandXOUTpins.
Oraclockgeneratedbyanexternaloscillatorcanalsobeused.
Inthiscase,entertheexternalclockfromtheXINpinandleavetheXOUTpinopen.
TheTMP88CS42NGdoesnotsupporttheCRnetworkthatproducesatimeconstant.
Figure2-3ExampleforConnectingaResonatorAdjustingtheoscillationfrequencyNote:Althoughnohardwarefunctionsareprovidedthatallowthefundamentalclocktobemonitoreddirectlyfromtheoutside,theoscillationfrequencycanbeadjustedbyforwardingthepulseofafixedfrequency(e.
g.
,clockoutput)toaportandmonitoringitinaprogramwhileinterruptsandthewatchdogtimeraredisabled.
Forsystemsthatrequireadjustingtheoscillationfrequency,anadjustmentprogrammustbecreatedbeforehand.
2.
1.
4.
2TimingGeneratorTheTimingGeneratorgeneratesvarioussystemclocksfromthefundamentalclockthataresuppliedtotheCPUcoreandperipheralhardwareunits.
TheTimingGeneratorhasthefollowingfunctions:TiminggeneratorStandbycontrolcircuitHigh-frequencyclockoscillatorcircuitTBTCRSYSCR2SYSCR1XINXOUTClockgeneratorfc00036H00038H00039HSystemclocksTiminggeneratorcontrolregisterSystemcontrolregisterXINHigh-frequencyClockXOUT(a)UsingacrystalorceramicresonatorXINXOUT(b)Usinganexternaloscillator(Open)Page122.
FunctionalDescription2.
1FunctionsoftheCPUCoreTMP88CS42NG1.
Generateadivideroutput(DVO)pulse2.
Generatethesourceclockforthetimebasetimer3.
Generatethesourceclockforthewatchdogtimer4.
Generatetheinternalsourceclockforthetimercounter5.
Generateawarm-upclockwhenexitingSTOPmode(1)ConfigurationoftheTimingGeneratorTheTimingGeneratora3-stageprescaler,21-stagedividers,andamachinecyclecounter.
Whenresetandwhenentering/exitingSTOPmode,theprescaleranddividersareclearedto0.
Figure2-4ConfigurationoftheTimingGeneratorDV1CKfcPrescalerDividerDividerSelectorTimercounterMachinecyclecounter212019181716151413121110987SAYB654321120StandbycontrolcircuitWatchdogtimerTimebasetimerDividerOutputetc.
Page13TMP88CS42NGNote1:fc:thehigh-frequencyclock[Hz],*:Don'tcareNote2:TheCGCRRegisterbits4and3showanindeterminatevaluewhenread.
Note3:Besuretowrite"0"toCGCRRegisterbits7,6,2,1and0.
Note1:*:Don'tcareNote2:Besuretowrite"0"toTBTCRRegisterbit4.
(2)MachinecycleInstructionexecutionandtheinternalhardwareoperationsaresynchronizedtothesystemclocks.
Theminimumunitofinstructionexecutionisreferredtoasthe"machinecycle".
TheTLCS-870/Xserieshas15typesofinstructions,from1-cycleinstructionswhichareexecutedinonemachinecycleupto15-cycleinstructionsthatrequireamaximumof15machinecycles.
Amachinecycleconsistsoffourstates(S0toS3),witheachstatecomprisedofonemainsystemclockcycle.
Figure2-5MachineCyclesDividerControlRegisterCGCR(0030H)7654321000DV1CK000(Initialvalue:000**000)DV1CKSelectsinputclocktothefirstdividerstage0:fc/41:fc/8R/WTimingGeneratorControlRegisterTBTCR(0036H)76543210DVOENDVOCK0TBTENTBTCK(Initialvalue:00000000)MainsystemclockStatesS0S1S2S3S0S1S2S31/fc(0.
20μsat20MHz)MachinecyclePage142.
FunctionalDescription2.
1FunctionsoftheCPUCoreTMP88CS42NG2.
1.
4.
3StandbyControlCircuitTheStandbyControlCircuitstarts/stopsthehigh-frequencyclockoscillatorcircuitandselectsthemainsystemclock.
TheSystemControlRegisters(SYSCR1,SYSCR2)areusedtocontroloperationmodesofthiscircuit.
Figure2-6showsanoperationmodetransitiondiagram,followedbydescriptionoftheSys-temControlRegisters.
(1)SingleclockmodeOnlythehigh-frequencyclockoscillatorcircuitisused.
Becausethemainsystemclockisgener-atedfromthehigh-frequencyclock,themachinecycletimeinsingleclockmodeis4/fc[s].
1.
NORMALmodeInthismode,theCPUcoreandperipheralhardwareunitsareoperatedwiththehigh-fre-quencyclock.
TheTMP88CS42NGentersthisNORMALmodeafterreset.
2.
IDLEmodeInthismode,theCPUandwatchdogtimerareturnedoffwhiletheperipheralhardwareunitsareoperatedwiththehigh-frequencyclock.
IDLEmodeisenteredintobyusingSystemControlRegister2.
ThedeviceisplacedoutofthismodeandbackintoNORMALmodebyaninterruptfromtheperipheralhardwareoranexternalinterrupt.
WhenIMF(interruptmas-terenableflag)=1(interruptenabled),thedevicereturnstonormaloperationaftertheinter-rupthasbeenserviced.
WhenIMF=0(interruptdisabled),thedevicerestartsexecutionbeginningwiththeinstructionnexttoonethatplaceditinIDLEmode.
3.
STOPmodeTheentiresystemoperationincludingtheoscillatorcircuitishalted,retainingtheinternalstateimmediatelybeforebeingstopped,withaminimalamountofpowerconsumed.
STOPmodeisenteredintobyusingSystemControlRegister1,andisexitedbySTOPpininput(leveloredgeselectable).
Afteranelapseofthewarm-uptime,thedevicerestartsexe-cutionbeginningwiththeinstructionnexttoonethatplaceditinSTOPmode.
Figure2-6OperationModeTransitionDiagramTable2-1SingleClockModeOperationModeOscillatorCircuitCPUCorePeripheralCircuitMachineCycleTimeHighFrequencyLowFrequencySingleClockRESETOscillate-ResetReset4/fc[s]NORMALOperateOperateIDLEStopSTOPStopStop-RESETSTOPmodeNORMALmodeIDLEmodeInterruptInstructionInputforreleasingmodeInstructionResetdeassertedPage15TMP88CS42NGNote1:WhenenteringfromNORMALmodeintoSTOPmode,alwaysbesuretosetSYSCR1to0.
Note2:WhenthedeviceisreleasedfromSTOPmodebyRESETpininput,italwaysreturnstoNORMALmoderegardlessofhowSYSCR1isset.
Note3:fc:High-frequencyclock[Hz],*:Don'tcareNote4:ThevaluesoftheSYSCR1Registerbits1and0areindeterminatewhenread.
Note5:WhenplacedthedeviceinSTOPmode,makesuretoset"1"toSYSCR1.
Note6:ReleasingthedevicefromtheSTOPmodecausestheSTOPbittobeautomaticallyclearedto"0".
Note7:Selectanappropriatevalueforthewarm-uptimeaccordingtothecharacteristicoftheresonatorused.
Note1:WhenexitingSTOPmode,SYSCR2areautomaticallyrewrittenaccordingtoSYSCR1.
.
Note2:WhenSYSCR2isclearedto0,thedeviceisreset.
Note3:WDT:WatchdogTimer,*:Don'tcareNote4:Besuretowrite"0"toSYSCR2Registerbit6.
Note5:ThevaluesoftheSYSCR2Registerbits3to0areindeterminatewhenread.
Note6:Changetheoperationmodeafterdisablingexternalinterrupts.
Ifinterruptsareenabledafterchangingoperationmode,clearinterruptlatchesasappropriateinadvance.
SystemControlRegister1SYSCR1(0038H)76543210STOPRELMRETMOUTENWUT(Initialvalue:000000**)STOPPlacethedeviceinSTOPmode0:KeeptheCPUcoreandperipheralhardwareoperating1:StoptheCPUcoreandperipheralhardware(placedinSTOPmode)R/WRELMSelectmethodbywhichthedeviceisreleasedfromSTOPmode0:ReleasedbyarisingedgeonSTOPpininput1:ReleasedbyahighlevelonSTOPpininputRETMSelectoperationmodeafterexitingSTOPmode0:ReturnstoNORMALmode1:ReservedOUTENSelectportoutputstateduringSTOPmode0:High-impedancestate1:HoldoutputWUTUnitofwarm-uptimewhenexitingSTOPmodeWhenReturningtoNORMALModeDV1CK=0DV1CK=1003*216/fc3*217/fc01216/fc217/fc10214/fc215/fc11ReservedReservedSystemControlRegister2SYSCR2(0039H)76543210XEN0SYSCKIDLE(Initialvalue:1000****)XENControlhigh-frequencyoscilla-tor0:Stoposcillation1:ContinueorstartoscillatingR/WSYSCKSelect(write)/monitor(read)systemclock0:High-frequencyclock(NORMAL/IDLE)1:ReservedR/WIDLEPlacethedeviceinIDLEmode0:KeeptheCPUandWDToperating1:StoptheCPUandWDT(IDLEmodeentered)R/WRETMOperationModeafterReleasingSTOPModeXENSYSCK0NORMALmode101Nooperation01Page162.
FunctionalDescription2.
1FunctionsoftheCPUCoreTMP88CS42NG2.
1.
4.
4ControllingOperationModes(1)STOPmodeSTOPmodeiscontrolledbySystemControlRegister1(SYSCR1)andtheSTOPpininput.
TheSTOPpinissharedwithP20portandINT5(externalinterruptinput5).
STOPmodeisenteredintobysettingSTOP(SYSCR1Registerbit7)to1.
DuringSTOPmode,thedeviceretainsthefollowingstate.
1.
Stoposcillation,therebystoppingoperationofallinternalcircuits.
2.
Thedatamemory,register,programstatusword,andportoutputlatchholdthestateinwhichtheywereimmediatelybeforeenteringSTOPmode.
3.
Cleartheprescaleranddividerforthetiminggeneratorto0.
4.
TheprogramcounterholdstheinstructionaddresstwoinstructionsaheadtheonethatplacedthedeviceinSTOPmode(e.
g.
,"SET(SYSCR1).
7").
ThedeviceisreleasedfromSTOPmodebytheactiveleveloredgeonSTOPpininputasselectedbySYSCR1.
Note:BeforeenteringSTOPmode,besuretodisableinterrupts.
ThisisbecauseifthesignalonanexternalinterruptpinchangesstateduringSTOP(fromenteringSTOPmodetillcompletionofwarm-up)theinterruptlatchissetto1,sothatthedevicemayaccepttheinterruptimmediatelyafterexitingSTOPmode.
Also,whenreenablinginterruptsafterexitingSTOPmode,besuretocleartheunnecessaryinterruptlatchesbeforehand.
a.
Releasedbylevel(whenRELM=1)ThedeviceisreleasedfromSTOPmodebyahighlevelonSTOPpininput.
AnyinstructiontoplacethedeviceinSTOPmodeisignoredwhenexecutedwhileSTOPpininputlevelishigh,andthedeviceimmediatelygoestoareleasesequence(warm-up)withoutenteringSTOPmode.
Therefore,beforeSTOPmodecanbeenteredwhileRELM=1,theSTOPpininputmustbeverifiedtobelowinaprogram.
Therearefollowingmethodstodothisverification.
1.
Testingtheportstatus2.
INT5interrupt(interruptgeneratedatafallingedgeonINT5pininput)Example1:EnteringSTOPmodefromNORMALmodebytestingP20portLD(SYSCR1),01010000B;SelecttobereleasedfromSTOPmodebylevelSSTOPH:TEST(P2DR).
0;WaituntilSTOPpininputgoeslowJRSF,SSTOPHDI;IMF←0SET(SYSCR1).
7;PlacethedeviceinSTOPmodeExample2:EnteringSTOPmodefromNORMALmodebyINT5interruptPINT5:TEST(P2DR).
0;DonotenterSTOPmodeifP20portinputlevelishigh,toeliminatenoiseJRSF,SINT5;DonotenterSTOPmodeifP20portinputlevelishigh,toeliminatenoiseLD(SYSCR1),01010000B;SelecttobereleasedfromSTOPmodebylevelDI;IMF←0SET(SYSCR1).
7;PlacethedeviceinSTOPmodeSINT5:RETIPage17TMP88CS42NGFigure2-7ReleasedfromSTOPModebyLevelNote1:Oncewarm-upstarts,thedevicedoesnotreturntoSTOPmodeevenwhentheSTOPpininputispulledlowagain.
Note2:IfRELMischangedto1(levelmode)afterbeingsetto0(edgemode),STOPmoderemainsunchangedunlessarisingedgeonSTOPpininputisdetected.
a.
Releasedbyedge(whenRELM=0)ThedeviceisreleasedfromSTOPmodebyarisingedgeonSTOPpininput.
Thismethodisusedinapplicationswherearelativelyshorttimeofprogramprocessingisrepeatedatcer-tainfixedintervals.
Applyafixed-periodsignal(e.
g.
,clockfromthelow-poweroscillatingsource)totheSTOPpin.
WhenRELM=0(edgemode),thedeviceisplacedinSTOPmodeevenwhentheSTOPpininputlevelishigh.
Figure2-8ReleasedfromSTOPModebyEdgeExample:EnteringSTOPmodefromNORMALmodeDI;IMF←0LD(SYSCR1),10010000B;SettobereleasedbyedgewhenenteringSTOPmodeSTOPpinXOUTpinNORMALoperationReleasedfromSTOPmodeinhardwareNORMALoperationVIHSTOPmodeWarm-upDetectlowonSTOPpininputinaprogrambeforeenteringSTOPmodeAlwaysreleasedbyahighlevelonSTOPpininputSTOPpinXOUTpinNORMALoperationVIHSTOPmodeWarm-upSTOPmodePlacedintoSTOPmodeinaprogramReleasedfromSTOPmodeinhardwarebyarisingedgeonSTOPpininput.
NORMALoperationPage182.
FunctionalDescription2.
1FunctionsoftheCPUCoreTMP88CS42NGThedeviceisreleasedfromSTOPmodefollowingthesequencedescribedbelow.
1.
Onlythehigh-frequencyoscillatorisoscillating.
2.
Awarm-uptimeisinsertedinordertoallowfortheclockoscillationtostabilize.
Duringwarm-up,theinternalcircuitsremainidle.
Thewarm-uptimecanbeselectedfromthreechoicesaccordingtotheoscillatorcharacteristicsbyusingSYSCR1.
3.
Afteranelapseofthewarm-uptime,thedevicerestartsnormaloperationbeginningwiththeinstructionnexttoonethatplaceditinSTOPmode.
Atthistime,theprescaleranddividerforthetiminggeneratorstartfromthezero-clearedstate.
Note:Becausethewarm-uptimeisobtainedfromthefundamentalclockbydividingit,iftheoscillationfrequencyfluctuateswhileexitingSTOPmode,thewarm-uptimebecomestohavesomeerror.
Therefore,thewarm-uptimemustbehandledasanapproximatevalue.
ThedevicecanalsobereleasedfromSTOPmodebypullingtheRESETpininputlow,inwhichcasethedeviceisimmediatelyresetasisnormallyresetbyRESET.
Afterreset,thedevicestartsoper-atingfromNORMALmode.
Note:WhenexitingSTOPmodewhilethedeviceisretainedatlowvoltage,thefollowingcautionisrequired.
BeforeexitingSTOPmode,thepowersupplyvoltagemustberaisedtotheoperatingvoltage.
Atthistime,theRESETpinlevelalsoishighandrisesalongwiththepowersupplyvoltage.
Ifthedevicehasatime-constantcircuitaddedexternaltothechip,thevoltageonRESETpininputdoesnotriseasfastasthepowersupplyvoltage.
Therefore,ifthevoltagelevelonRESETpininputisbelowtheRESETpin'snoninverted,high-levelinputvoltage(hysteresisinput),thedevicemaybereset.
Table2-2Warm-upTime(Example:fc=20MHz)WUTWarm-upTime[ms]WhenReturningtoNORMALModeDV1CK=0DV1CK=1009.
83119.
662013.
2776.
554100.
8191.
63811ReservedReservedPage19TMP88CS42NGFigure2-9EnteringandExitingSTOPMode(whenDV1CK=0)OscillationInstructionexecutionDivider(a)EnteringSTOPmode(Example:EnteredintobytheSET(SYSCR1).
7instructionplacedataddressa)MainsystemclockMainsystemclockProgramcounterStopStopa+2a+3nn+1n+2n+3n+40SET(SYSCR1).
7OscillatorcircuitOscillatorcircuitWarm-up(b)ExitingSTOPmodeOscillationInstructionexecutionDividerProgramcounterStopStopCountup00123a+3Instructionataddressa+4Instructionataddressa+3Instructionataddressa+2STOPpininputa+4a+5a+6Page202.
FunctionalDescription2.
1FunctionsoftheCPUCoreTMP88CS42NG(2)IDLEmodeIDLEmodeiscontrolledbySystemControlRegister2(SYSCR2)andamaskableinterrupt.
Dur-ingIDLEmode,thedeviceretainsthefollowingstate.
1.
TheCPUandwatchdogtimerstopoperating.
Theperipheralhardwarecontinuesoperating.
2.
Thedatamemory,register,programstatusword,andportoutputlatchholdthestateinwhichtheywereimmediatelybeforeenteringIDLEmode.
3.
TheprogramcounterholdstheinstructionaddresstwoinstructionsaheadtheonethatplacedthedeviceinIDLEmode.
Figure2-10IDLEModeExample:PlacingthedeviceinIDLEmodeSET(SYSCR2).
4PlacethedeviceinIDLEmode(byinstruction)StoptheCPUandWDTInterrupthandlingExecutetheinstructionnexttoonethatplaceddeviceIDLEmodeResetYesNoNoNoInterruptrequestIMF=1ResetinputYesYes(Releasedbyinterrupt)(Releasednormally)Page21TMP88CS42NGThedevicecanbereleasedfromIDLEmodenormallyorbyaninterruptasselectedwiththeinter-ruptmasterenableflag(IMF).
a.
Releasednormally(whenIMF=0)ThedevicecanbereleasedfromIDLEmodebytheinterruptsourceenabledbytheinter-ruptindividualenableflag(EF),andrestartsexecutionbeginningwiththeinstructionnexttoonethatplaceditinIDLEmode.
Theinterruptlatch(IL)fortheinterruptsourceusedtoexitIDLEmodenormallyneedstobeclearedto0usingaloadinstruction.
b.
Releasedbyinterrupt(whenIMF=1)ThedevicecanbereleasedfromIDLEmodebytheinterruptsourceenabledbytheinter-ruptindividualenableflag(EF),andentersinterrupthandling.
Afterinterrupthandling,thedevicereturnstotheinstructionnexttoonethatplaceditinIDLEmode.
ThedevicecanalsobereleasedfromIDLEmodebypullingtheRESETpininputlow,inwhichcasethedeviceisimmediatelyresetasisnormallyresetbyRESET.
Afterreset,thedevicestartsoper-atingfromNORMALmode.
Note:IfawatchdogtimerinterruptoccursimmediatelybeforeenteringIDLEmode,thedevicepro-cessesthewatchdogtimerinterruptwithoutenteringIDLEmode.
Page222.
FunctionalDescription2.
1FunctionsoftheCPUCoreTMP88CS42NGFigure2-11EnteringandExitingIDLEMode(b)ExitingIDLEmode(a)EnteringIDLEmode(Example:EnteredintobytheSETinstructionplacedataddressa)IDLEa+2a+3SET(SYSCR2).
4Operating1.
ReleasednormallyIDLEIDLEa+3a+4Instructionataddressa+2Operating2.
ReleasedbyinterruptIDLEIDLEa+3InterruptacceptedOperatingMainsystemclockInterruptrequestProgramcounterInstructionexecutionMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerWatchdogtimerPage23TMP88CS42NG2.
1.
5ResetCircuitTheTMP88CS42NGhasfourwaystogenerateareset:externalresetinput,addresstrapreset,watchdogtimerresetandsystemclockreset.
Table2-3showshowtheinternalhardwareisinitializedbyresetoperation.
Atpower-ontime,theinternalcauseresetcircuits(watchdogtimerreset,addresstrapreset,andsystemclockreset)arenotinitialized.
2.
1.
5.
1ExternalResetInputTheRESETpinisahysteresisinputwithapull-upresistorincluded.
ByholdingtheRESETpinlowforatleastthreemachinecycles(12/fc[s])ormorewhilethepowersupplyvoltageiswithintheratedoperat-ingvoltagerangeandtheoscillatorisoscillatingstably,thedeviceisresetanditsinternalstateisinitial-ized.
WhentheRESETpininputisreleasedbackhigh,thedeviceisfreedfromresetandstartsexecutingtheprogrambeginningwiththevectoraddressstoredataddressesFFFFCHtoFFFFEH.
Figure2-12ResetCircuit2.
1.
5.
2AdressTrapResetIftheCPUshouldstartloopingforreasonsofnoise,etc.
andattemptstofetchinstructionsfromtheinternalRAM,SFRorDBRarea,thedevicegeneratsaninternalreset.
Table2-3InternalHardwareInitializationbyResetOperationInternalHardwareInitialValueInternalHardwareInitialValueProgramCounter(PC)(FFFFEHtoFFFFCH)Prescaleranddividerforthetiminggenerator0StackPointer(SP)NotinitializedGeneral-purposeRegisters(W,A,B,C,D,E,H,L)NotinitializedRegisterBankSelector(RBS)0WatchdogtimerEnableJumpStatusFlag(JF)1ZeroFlag(ZF)NotinitializedOutputlatchofinput/outputportSeedescriptionofeachinput/outputport.
CarryFlag(CF)NotinitializedHalfCarryFlag(HF)NotinitializedSignFlag(SF)NotinitializedOverflowFlag(VF)NotinitializedInterruptMasterEnableFlag(IMF)0InterruptIndividualEnableFlag(EF)0ControlregisterSeedescriptionofeachcontrolregister.
InterruptLatch(IL)0InterruptNestingFlag(INF)0RAMNotinitializedResetinputVDDRESETPage242.
FunctionalDescription2.
1FunctionsoftheCPUCoreTMP88CS42NGTheaddesstrappermission/prohibitionissetbytheaddresstrapresetcontrolregister(ATAS,ATKEY).
TheaddresstrapispermitedinitiallyandtheinternalresetisgeneratedbyfetchingfrominternalRAM,SFRorDBRarea.
Iftheaddresstrapisprohibited,instructionsintheinternalRAMareacanbeexecuted.
Note:Read-modify-writeinstructions,suchasabitmanipulation,cannotaccessATASorATKEYregisterbecausetheseregisterarewriteonly.
Note1:Indevelopmenttools,addresstrapcannotbeprohibitedintheinternalRAM,SFRorDBRareawiththeaddresstrapcontrolregisters.
Whenusingdevelopmenttools,eveniftheaddresstrappermis-sion/prohibitionsettingischangedintheuser'sprogram,thischangeisineffective.
ToexecuteinstructionsfromtheRAMarea,developmenttoolsmustbesetaccordingly.
Note2:WhiletheSWIinstructionatanaddressimmediatelybeforetheaddresstrapareaisexecuting,theprogramcounterisincrementedtopointtothenextaddressintheaddresstraparea;anaddresstrapisthereforetakenimmediately.
DevelopmenttoolsettingToprohibittheaddresstrap:1.
Modifytheiram(mappingattribute)areato(00040Hto000BFH)inthememorymapwin-dow.
2.
Set000C0Hto"addresstrapprohibitionarea"asaneweram(mappingattribute)area.
3.
Loadtheuserprogram4.
Executetheaddresstrapprohibitioncodeintheuser'sprogram2.
1.
5.
3WatchdogTimerResetRefertotheSection"WatchdogTimer.
"2.
1.
5.
4SystemClockResetWhenSYSCR2isclearedto0orwhenSYSCR2isclearedto0whileSYSCR2=0,thesystemclockisturnedoff,causingtheCPUtobecomelockedup.
Topreventthisproblem,upondetectingSYSCR2=0,SYSCR2=SYSCR2=0orSYSCR2=1,thedeviceautomaticallygeneratesaninternalresetsignaltoletthesystemclockcontinueoscillating.
AddressTrapControlRegisterATAS(1F94H)76543210ATAS(initialvalue:0)ATASSelecttheaddresstrappermission/prohibition0:Permitaddresstrap1:Prohibitaddresstrap(ItmaybeavailableaftersettingcontrolcodeforATKEYregister)WriteonlyAddressTrapControlCodeRegisterATKEY(1F95H)76543210(initialvalue:ATKEYWritecontrolcodetoprohibitaddresstrapD2H:AddresstrapprohibitioncodeOthers:IneffectiveWriteonlyPage25TMP88CS42NG3.
InterruptControlCircuitTheTMP88CS42NGhasatotalof35interruptsourcesexcludingreset.
Interruptscanbenestedwithpriorities.
Twooftheinternalinterruptsourcesarepseudononmaskablewhiletherestaremaskable.
Interruptsourcesareprovidedwithinterruptlatches(IL),whichholdinterruptrequests,andindependentvectors.
Theinterruptlatchissetto"1"bythegenerationofitsinterruptrequestwhichrequeststheCPUtoacceptitsinter-rupts.
Interruptsareenabledordisabledbysoftwareusingtheinterruptmasterenableflag(IMF)andinterruptenableflag(EF).
Ifmorethanoneinterruptsaregeneratedsimultaneously,interruptsareacceptedinorderwhichisdomi-natedbyhardware.
However,therearenoprioritizedinterruptfactorsamongnon-maskableinterrupts.
InterruptFactorsEnableConditionInterruptLatchVectorAddressPriorityInternal/External(Reset)Nonmaskable–FFFFCHigh0InternalINTSWI(Softwareinterrupt)Pseudononmaskable–FFFF81InternalINTWDT(Watchdogtimerinterrupt)PseudononmaskableIL2FFFF42ExternalINT0(Externalinterrupt0)IMFEF3=1,INT0EN=1IL3FFFF03ReservedIMFEF4=1IL4FFFEC4ExternalINT1(Externalinterrupt1)IMFEF5=1IL5FFFE85InternalINTTBT(TBTinterrupt)IMFEF6=1IL6FFFE46ReservedIMFEF7=1IL7FFFE07InternalINTEMG1(ch1Errordetectinterrupt)IMFEF8=1IL8FFFDC8InternalINTEMG2(ch2Errordetectinterrupt)IMFEF9=1IL9FFFD89InternalINTCLM1(ch1Overloadprotectioninterrupt)IMFEF10=1IL10FFFD410InternalINTCLM2(ch2Overloadprotectioninterrupt)IMFEF11=1IL11FFFD011InternalINTTMR31(ch1Timer3interrupt)IMFEF12=1IL12FFFCC12InternalINTTMR32(ch2Timer3interrupt)IMFEF13=1IL13FFFC813ReservedIMFEF14=1IL14FFFC414ExternalINT5(Externalinterrupt5)IMFEF15=1IL15FFFC015InternalINTPDC1(ch1Posisiondetectinterrupt)IMFEF16=1IL16FFFBC16InternalINTPDC2(ch2Posisiondetectinterrupt)IMFEF17=1IL17FFFB817InternalINTPWM1(ch1Waveformgeneraterinterrupt)IMFEF18=1IL18FFFB418InternalINTPWM2(ch2Waveformgeneraterinterrupt)IMFEF19=1IL19FFFB019InternalINTEDT1(ch1ErectricangleTimerinterrupt)IMFEF20=1IL20FFFAC20InternalINTEDT2(ch2ErectricangleTimerinterrupt)IMFEF21=1IL21FFFA821InternalINTTMR11(ch1Timer1interrupt)IMFEF22=1IL22FFFA422InternalINTTMR12(ch2Timer1interrupt)IMFEF23=1IL23FFFA023InternalINTTMR21(ch1Timer2interrupt)IMFEF24=1IL24FFF9C24InternalINTTMR22(ch2Timer2interrupt)IMFEF25=1IL25FFF9825InternalINTTC1(TC1interrupt)IMFEF26=1IL26FFF9426InternalINTCTC1(CTCinterrupt)IMFEF27=1IL27FFF9027InternalINTTC6(TC68bit/16bitinterrupt)IMFEF28=1IL28FFF8C28ExternalINT2(Externalinterrupt2)IMFEF29=1IL29FFF8829ExternalINT3(Externalinterrupt3)IMFEF30=1IL30FFF8430ExternalINT4(Externalinterrupt4)IMFEF31=1IL31FFF8031InternalINTRXD(UARTreceiveinterrupt)IMFEF32=1IL32FFF3C32InternalINTTXD(UARTtransmitinterrupt)IMFEF33=1IL33FFF3833InternalINTSIO(SIOinterrupt)IMFEF34=1IL34FFF3434InternalINTTC3(TC3interrupt)IMFEF35=1IL35FFF3035InternalINTTC4(TC4interrupt)IMFEF36=1IL36FFF2C36InternalINTTC5(TC5interrupt)IMFEF37=1IL37FFF2837InternalINTADC(A/Dconverterinterrupt)IMFEF38=1IL38FFF24Low38Page263.
InterruptControlCircuit3.
1Interruptlatches(IL38toIL2)TMP88CS42NGNote1:Tousethewatchdogtimerinterrupt(INTWDT),clearWDTCR1to"0"(Itissetforthe"Resetrequest"afterresetisreleased).
Itisdescribedinthesection"WatchdogTimer"fordetails.
3.
1Interruptlatches(IL38toIL2)Aninterruptlatchisprovidedforeachinterruptsource,exceptforasoftwareinterruptandanexecutedtheunde-finedinstructioninterrupt.
Wheninterruptrequestisgenerated,thelatchissetto"1",andtheCPUisrequestedtoaccepttheinterruptifitsinterruptisenabled.
Theinterruptlatchisclearedto"0"immediatelyafteracceptinginter-rupt.
Allinterruptlatchesareinitializedto"0"duringreset.
Theinterruptlatchesarelocatedonaddress003CH,003DH,002EH,002FHand002BHinSFRarea.
Eachlatchcanbeclearedto"0"individuallybyinstruction.
However,IL2andIL3shouldnotbeclearedto"0"bysoftware.
Forclearingtheinterruptlatch,loadinstructionshouldbeusedandthenIL2shouldbesetto"1".
Iftheread-modify-writeinstructionssuchasbitmanipulationoroperationinstructionsareused,interruptrequestwouldbeclearedinadequatelyifinterruptisrequestedwhilesuchinstructionsareexecuted.
Sinceinterruptlatchescanberead,thestatusforinterruptrequestscanbemonitoredbysoftware.
Butinterruptlatchesarenotsetto"1"byaninstruction.
Note:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninterruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexecutedbeforesettingIMF="1".
Example1:ClearsinterruptlatchesDI;IMF←0LD(ILL),1110100000111111B;IL2toIL7←0LD(ILH),1110100000111111B;IL8toIL15←0LD(ILE),1110100000111111B;IL16toIL23←0LD(ILD),1110100000111111B;IL24toIL31←0LD(ILC),1110100000111111B;IL32toIL38←0EI;IMF←1Example2:ReadsinterruptlatchesLDWA,(ILL);W←(ILH),A←(ILL)LDBC,(ILE);B←(ILD),C←(ILE)LDD,(ILC);D←(ILC)Example3:TestsinterruptlatchesTEST(ILL).
7;ifIL7=1thenjumpJRF,SSETPage27TMP88CS42NG3.
2Interruptenableregister(EIR)Theinterruptenableregister(EIR)enablesanddisablestheacceptanceofinterrupts,exceptforthepseudonon-maskableinterrupts(Softwareinterrupt,undefinedinstructioninterrupt,addresstrapinterruptandwatchdoginter-rupt).
Pseudonon-maskableinterruptisacceptedregardlessofthecontentsoftheEIR.
TheEIRconsistsofaninterruptmasterenableflag(IMF)andtheindividualinterruptenableflags(EF).
Theseregistersarelocatedonaddress003AH,003BH,002CH,002DHand002AHinSFRarea,andtheycanbereadandwrittenbyaninstructions(Includingread-modify-writeinstructionssuchasbitmanipulationoroperationinstruc-tions).
3.
2.
1Interruptmasterenableflag(IMF)Theinterruptenableregister(IMF)enablesanddisablestheacceptanceofthewholemaskableinterrupt.
WhileIMF="0",allmaskableinterruptsarenotacceptedregardlessofthestatusoneachindividualinterruptenableflag(EF).
BysettingIMFto"1",theinterruptbecomesacceptableiftheindividualsareenabled.
Whenaninterruptisaccepted,IMFisclearedto"0"afterthelateststatusonIMFisstacked.
Thusthemaskableinterruptswhichfollowaredisabledtemporarily.
IMFflagissetto"1"bythemaskableinterruptreturninstruction[RETI]afterexecutingtheinterruptserviceprogramroutine,andMCUcanaccepttheinter-ruptagain.
Thelatestinterruptrequestisgeneratedalready,itisavailableimmediatelyafterthe[RETI]instruc-tionisexecuted.
Onthepseudonon-maskableinterrupt,thenon-maskablereturninstruction[RETN]isadopted.
Inthiscase,IMFflagissetto"1"onlywhenitperformsthepseudonon-maskableinterruptserviceroutineontheinterruptacceptablestatus(IMF=1).
However,IMFissetto"0"inthepseudonon-maskableinterruptserviceroutine,itmaintainsitsstatus(IMF="0").
TheIMFislocatedonbit0inEIRL(Address:003AHinSFR),andcanbereadandwrittenbyaninstruction.
TheIMFisnormallysetandclearedby[EI]and[DI]instructionrespectively.
Duringreset,theIMFisinitial-izedto"0".
3.
2.
2Individualinterruptenableflags(EF38toEF3)Eachoftheseflagsenablesanddisablestheacceptanceofitsmaskableinterrupt.
Settingthecorrespondingbitofanindividualinterruptenableflagto"1"enablesacceptanceofitsinterrupt,andsettingthebitto"0"dis-ablesacceptance.
Duringreset,alltheindividualinterruptenableflags(EF38toEF3)areinitializedto"0"andallmaskableinterruptsarenotaccepteduntiltheyaresetto"1".
Note:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenor-mallyoninterruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulat-ingEForILshouldbeexecutedbeforesettingIMF="1".
Example:EnablesinterruptsindividuallyandsetsIMFDI;IMF←0SET(EIRL),.
5;EF5←1CLR(EIRL),.
6;EF6←0CLR(EIRH),.
4;EF12←0CLR(EIRD),.
0;EF24←0:EI;IMF←1Page283.
InterruptControlCircuit3.
2Interruptenableregister(EIR)TMP88CS42NGNote1:IL2cannotalonebecleard.
Note2:Unabletodetecttheunder-flowofcounter.
Note3:Thenestingcounterisset"0"initially,itperformscount-upbytheinterruptacceptanceandcount-downbyexecutingtheinterruptreturninstruction.
Note4:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninter-ruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexe-cutedbeforesettingIMF="1".
Note5:DonotclearILwithread-modify-writeinstructionssuchasbitoperations.
InterruptLatches(Initialvalue:0*000000*00*0000)ILH,ILL(003DH,003CH)1514131211109876543210IL15-IL13IL12IL11IL10IL9IL8-IL6IL5-IL3IL2INFILH(003DH)ILL(003CH)(Initialvalue:0000000000000000)ILD,ILE(002FH,002EH)1514131211109876543210IL31IL30IL29IL28IL27IL26IL25IL24IL23IL22IL21IL20IL19IL18IL17IL16ILD(002FH)ILE(002EH)(Initialvalue:*0000000)ILC(002BH)76543210-IL38IL37IL36IL35IL34IL33IL32ILE(002BH)IL38toIL2InterruptlatchesReadWriteR/W0:Nointerruptrequest1:Interruptrequest0:Clearstheinterruptrequest(Note1)1:(Unabletosetinterruptlatch)INFInterruptNestingFlag00:Outofinterruptservice01:Oninterruptserviceoflevel110:Oninterruptserviceofmorethanlevel211:Oninterruptserviceofmorethanlevel300:Reserved01:Clearthenestingcounter10:Count-down1stepforthenestingcounter(Note2)11:ReservedInterruptEnableRegisters(Initialvalue:0*000000*00*0**0)EIRH,EIRL(003BH,003AH)1514131211109876543210EF15-EF13EF12EF11EF10EF9EF8-EF6EF5-EF3IMFEIRH(003BH)EIRL(003AH)(Initialvalue:0000000000000000)EIRD,EIRE(002DH,002CH)1514131211109876543210EF31EF30EF29EF28EF27EF26EF25EF24EF23EF22EF21EF20EF19EF18EF17EF16EIRD(002DH)EIRE(002CH)(Initialvalue:*0000000)EIRE(002AH)76543210-EF38EF37EF36EF35EF34EF33EF32EIRE(002AH)Page29TMP88CS42NGNote1:DonotsetIMFandtheinterruptenableflag(EF38toEF3)to"1"atthesametime.
Note2:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninter-ruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexe-cutedbeforesettingIMF="1".
EF38toEF3Individual-interruptenableflag(Specifiedforeachbit)0:1:Disablestheacceptanceofeachmaskableinterrupt.
Enablestheacceptanceofeachmaskableinterrupt.
R/WIMFInterruptmasterenableflag0:1:DisablestheacceptanceofallmaskableinterruptsEnablestheacceptanceofallmaskableinterruptsPage303.
InterruptControlCircuit3.
3InterruptSequenceTMP88CS42NG3.
3InterruptSequenceAninterruptrequest,whichraisedinterruptlatch,isheld,untilinterruptisacceptedorinterruptlatchisclearedto"0"byresettingoraninstruction.
Interruptacceptancesequencerequires12machinecycles(2.
4μs@20MHz)afterthecompletionofthecurrentinstruction.
Theinterruptservicetaskterminatesuponexecutionofaninterruptreturninstruction[RETI](formaskableinterrupts)or[RETN](fornon-maskableinterrupts).
Figure3-1showsthetimingchartofinterruptacceptanceprocessing.
3.
3.
1Interruptacceptanceprocessingispackagedasfollows.
a.
Theinterruptmasterenableflag(IMF)isclearedto"0"inordertodisabletheacceptanceofanyfol-lowinginterrupt.
b.
Theinterruptlatch(IL)fortheinterruptsourceacceptedisclearedto"0".
c.
Thecontentsoftheprogramcounter(PC)andtheprogramstatusword,includingtheinterruptmasterenableflag(IMF),aresaved(Pushed)onthestackinsequenceofPSWH,PSWL,PCE,PCH,PCL.
Meanwhile,thestackpointer(SP)isdecrementedby5.
d.
Theentryaddress(Interruptvector)ofthecorrespondinginterruptserviceprogram,loadedonthevec-tortable,istransferredtotheprogramcounter.
e.
ReadtheRBScontrolcodefromthevectortable,additsMSB(4bit)totheregisterbankselecter(RBS).
f.
Countuptheinterruptnestingcounter.
g.
Theinstructionstoredattheentryaddressoftheinterruptserviceprogramisexecuted.
Note:WhenthecontentsofPSWaresavedonthestack,thecontentsofIMFarealsosaved.
Note1:a:Returnaddress,b:Entryaddress,c:AddresswhichRETIinstructionisstoredNote2:Onconditionthatinterruptisenabled,ittakes62/fc[s]atmaximum(Iftheinterruptlatchissetatthefirstmachinecycleon15cycleinstruction)tostartinterruptacceptanceprocessingsinceitsinterruptlatchisset.
Figure3-1TimingChartofInterruptAcceptance/ReturnInterruptInstructionExample:CorrespondencebetweenvectortableaddressforINTTBTandtheentryaddressoftheinterruptserviceprogramInterruptrequestInterruptlatch(IL)IMFExecuteinstructionPCSP1-machinecycleInterruptservicetaskn-3n-4n-4an-3nn-5a-1abb+1b+2a+1a+2b+3c+2c+1ExecuteinstructionExecuteinstructionExecuteRETIinstructionInterruptacceptancea+1ann-2n-1n-2n-1Page31TMP88CS42NGFigure3-2Vectortableaddress,EntryaddressAmaskableinterruptisnotaccepteduntiltheIMFissetto"1"evenifthemaskableinterrupthigherthanthelevelofcurrentservicinginterruptisrequested.
Inordertoutilizenestedinterruptservice,theIMFissetto"1"intheinterruptserviceprogram.
Inthiscase,acceptableinterruptsourcesareselectivelyenabledbytheindividualinterruptenableflags.
Butdon'tusetheread-modify-writeinstructionforEIRL(0003AH)onthepseudonon-maskableinterruptservicetask.
Toavoidoverloadednesting,cleartheindividualinterruptenableflagwhoseinterruptiscurrentlyserviced,beforesettingIMFto"1".
Asfornon-maskableinterrupt,keepinterruptserviceshortencomparedwithlengthbetweeninterruptrequests;otherwisethestatuscannotberecoveredasnon-maskableinterruptwouldsimplynested.
3.
3.
2Saving/restoringgeneral-purposeregistersDuringinterruptacceptanceprocessing,theprogramcounter(PC)andtheprogramstatusword(PSW,includesIMF)areautomaticallysavedonthestack,buttheaccumulatorandothersarenot.
Theseregistersaresavedbysoftwareifnecessary.
Whenmultipleinterruptservicesarenested,itisalsonecessarytoavoidusingthesamedatamemoryareaforsavingregisters.
Thefollowingfourmethodsareusedtosave/restorethegen-eral-purposeregisters.
3.
3.
2.
1UsingAutomaticregisterbankswitcingByswitchingtonon-useregisterbank,itcanrestorethegeneral-purposeregisterathigespeed.
Usuallythebankregister"0"isassignedformaintaskandthebankregister"1to15"arefortheeachinterruptservicetask.
Tomakeupitsdatamemoryefficiency,thecommonbankisassignedfornon-mul-tipleintrruptfactor.
Itcanreturnbacktomain-flowbyexecutingtheinterruptreturninstructions([RETI]/[RETN])fromthecurrentinterruptregisterbankautomatically.
Thus,noneedtorestoretheRBSbyaprogram.
3.
3.
2.
2UsingregisterbankswitchingByswitchingtonon-useregisterbank,itcanrestorethegeneral-purposeregisterathigespeed.
Usuallythebankregister"0"isassignedformaintaskandthebankregister"1to15"arefortheeachinterruptser-vicetask.
Example:RegisterbankswitchingPINTxx:(interruptprocessing);BeginofinterruptroutineRETI;Endofinterrupt:VINTxx:DPPINTxx;PINTxxvectoraddresssettingDB1;RBS="1"),193/fc[s](atEINTCR="0")(2)INT2toINT4pins25/fc[s]Note2:WhenEINTCR="0",IL3isnotsetevenifafallingedgeisdetectedontheINT0pininput.
Note3:Whenapinwithmorethanonefunctionisusedasanoutputandachangeoccursindataorinput/outputstatus,aninter-ruptrequestsignalisgeneratedinapseudomanner.
Inthiscase,itisnecessarytoperformappropriateprocessingsuchasdisablingtheinterruptenableflag.
SourcePinSub-PinEnableConditionsReleaseEdge(level)DigitalNoiseRejectINT0INT0P10IMF+EF3+INT0EN=1FallingedgePulsesoflessthan2/fc[s]areeliminatedasnoise.
Pulsesof6/fc[s]ormoreareconsideredtobesignals.
(atCGCR=0).
INT1INT1P11IMF+EF5=1FallingedgeorRisingedgePulsesoflessthan15/fcor63/fc[s]areelimi-natedasnoise.
Pulsesof48/fcor192/fc[s]ormoreareconsideredtobesignals.
(atCGCR=0).
INT2INT2P12/TC1IMF+EF29=1Pulsesoflessthan7/fc[s]areeliminatedasnoise.
Pulsesof24/fc[s]ormoreareconsideredtobesignals.
(atCGCR=0).
INT3INT3P21/TC3IMF+EF30=1INT4INT4P22/TC4IMF+EF31=1INT5INT5P20/STOPIMF+EF15=1FallingedgePulsesoflessthan2/fc[s]areeliminatedasnoise.
Pulsesof6/fc[s]ormoreareconsideredtobesignals.
Page363.
InterruptControlCircuit3.
5ExternalInterruptsTMP88CS42NGNote1:fc:High-frequencyclock[Hz],*:Don'tcareNote2:Whentheexternalinterruptcontrolregister(EINTCR)isoverwritten,thenoisecancellermaynotoperatenormally.
Itisrecommendedthatexternalinterruptsaredisabledusingtheinterruptenableregister(EIR).
Note3:ThemaximumtimefrommodifyingEINTCRuntilanoiserejecttimeischangedis26/fc.
Note4:IncaseRESETpinisreleasedwhilethestateofINT4pinkeeps"H"level,theexternalinterrupt4requestisnotgeneratedeveniftheINT4edgeselect(EINTCR)isspecifiedas"H"level.
TherisingedgeisneededafterRESETpinisreleased.
ExternalInterruptControlRegisterEINTCR76543210(0037H)INT1NCINT0ENINT4ESINT3ESINT2ESINT1ES(Initialvalue:0000000*)INT1NCNoiserejecttimeselect0:Pulsesoflessthan63/fc[s]areeliminatedasnoise1:Pulsesoflessthan15/fc[s]areeliminatedasnoiseR/WINT0ENP10/INT0pinconfiguration0:P10input/outputport1:INT0pin(PortP10shouldbesettoaninputmode)R/WINT4ESINT4edgeselect00:Risingedge01:Fallingedge10:RisingedgeandFallingedge11:HlevelR/WINT3ESINT3edgeselect0:Risingedge1:FallingedgeR/WINT2ESINT2edgeselectINT1ESINT1edgeselectPage37TMP88CS42NG4.
SpecialFunctionRegisterTheTMP88CS42NGadoptsthememorymappedI/Osystem,andallperipheralcontrolandtransfersareper-formedthroughthespecialfunctionregister(SFR)orthedatabufferregister(DBR).
TheSFRismappedonaddress0000Hto003FH,DBRismappedonaddress01F80Hto01FFFH.
Thischaptershowsthearrangementofthespecialfunctionregister(SFR)anddatabufferregister(DBR)forTMP88CS42NG.
4.
1SFRAddressReadWrite0000HP0DR0001HP1DR0002HP2DR0003HP3DR0004HP4DR0005HP5DR0006HP6DR0007HP7DR0008HReserved0009HReserved000AHP0CR000BHP1CR000CHHPWMCR000DHHPWMDR0000EHHPWMDR1000FHTC1CR0010HTC1DRAL0011HTC1DRAH0012HTC1DRBL0013HTC1DRBH0014HCTC1CR10015HCTC1CR20016H-CTC1DRL0017H-CTC1DRH0018HReserved0019HReserved001AHTC4CR001BHTC4DR001CHTC3DRA001DHTC3DRB-001EHTC3CR001FHReserved0020HTC5CR0021HTC6CR0022HTTREG50023HTTREG60024HPWREG50025HPWREG6Page384.
SpecialFunctionRegister4.
1SFRTMP88CS42NGNote1:Donotaccessreservedareasbytheprogram.
Note2:;Cannotbeaccessed.
Note3:Write-onlyregistersandinterruptlatchescannotusetheread-modify-writeinstructions(BitmanipulationinstructionssuchasSET,CLR,etc.
andlogicaloperationinstructionssuchasAND,OR,etc.
).
0026HADCCRA0027HADCCRB0028HADCDRL-0029HADCDRH-002AHEIRC002BHILC002CHEIRE002DHEIRD002EHILE002FHILD0030HCGCR0031HReserved0032HReserved0033HReserved0034H-WDTCR10035H-WDTCR20036HTBTCR0037HEINTCR0038HSYSCR10039HSYSCR2003AHEIRL003BHEIRH003CHILL003DHILH003EHPSWL003FHPSWHAddressReadWritePage39TMP88CS42NG4.
2DBRAddressPMDchReadWrite1F80HP0ODE1F81H1F82H1F83HP3ODE1F84HP4ODE1F85HP5ODE1F86H1F87H1F88H1F89HP3CR1F8AHP4CR1F8BHP5CR1F8CHP6CR1F8DHP7CR1F8EH1F8FH1F90HUARTSEL1F91HUARTSRUARTCRA1F92HUARTCRB1F93HRDBUFTDBUF1F94HATAS1F95HATKEY1F96HSIOCR11F97HSIOSRSIOCR21F98HSIOBR01F99HSIOBR11F9AHSIOBR21F9BHSIOBR31F9CHSIOBR41F9DHSIOBR51F9EHSIOBR61F9FHSIOBR71FA0HforPMDch.
1PDCRA1FA1HforPMDch.
1PDCRB1FA2HforPMDch.
1PDCRC1FA3HforPMDch.
1SDREG1FA4HforPMDch.
1MTCRA1FA5HforPMDch.
1MTCRB1FA6HforPMDch.
1MCAPL1FA7HforPMDch.
1MCAPH1FA8HforPMDch.
1CMP1L1FA9HforPMDch.
1CMP1H1FAAHforPMDch.
1CMP2L1FABHforPMDch.
1CMP2H1FACHforPMDch.
1CMP3L1FADHforPMDch.
1CMP3H1FAEHforPMDch.
1MDCRA1FAFHforPMDch.
1MDCRBPage404.
SpecialFunctionRegister4.
2DBRTMP88CS42NG1FB0HforPMDch.
1EMGCRA1FB1HforPMDch.
1EMGCRB1FB2HforPMDch.
1MDOUTL1FB3HforPMDch.
1MDOUTH1FB4HforPMDch.
1MDCNTL1FB5HforPMDch.
1MDCNTH1FB6HforPMDch.
1MDPRDL1FB7HforPMDch.
1MDPRDH1FB8HforPMDch.
1CMPUL1FB9HforPMDch.
1CMPUH1FBAHforPMDch.
1CMPVL1FBBHforPMDch.
1CMPVH1FBCHforPMDch.
1CMPWL1FBDHforPMDch.
1CMPWH1FBEHforPMDch.
1DTR1FBFHforPMDch.
1EMGREL1FC0HforPMDch.
1EDCRA1FC1HforPMDch.
1EDCRB1FC2HforPMDch.
1EDSETL1FC3HforPMDch.
1EDSETH1FC4HforPMDch.
1ELDEGL1FC5HforPMDch.
1ELDEGH1FC6HforPMDch.
1AMPL1FC7HforPMDch.
1AMPH1FC8HforPMDch.
1EDCAPL1FC9HforPMDch.
1EDCAPH1FCAHforPMDch.
1WFMDR1FCBH1FCCHReserved1FCDHReserved1FCEHReserved1FCFHReserved1FD0HforPMDch.
2PDCRA1FD1HforPMDch.
2PDCRB1FD2HforPMDch.
2PDCRC1FD3HforPMDch.
2SDREG1FD4HforPMDch.
2MTCRA1FD5HforPMDch.
2MTCRB1FD6HforPMDch.
2MCAPL1FD7HforPMDch.
2MCAPH1FD8HforPMDch.
2CMP1L1FD9HforPMDch.
2CMP1H1FDAHforPMDch.
2CMP2L1FDBHforPMDch.
2CMP2H1FDCHforPMDch.
2CMP3L1FDDHforPMDch.
2CMP3H1FDEHforPMDch.
2MDCRA1FDFHforPMDch.
2MDCRB1FE0HforPMDch.
2EMGCRA1FE1HforPMDch.
2EMGCRB1FE2HforPMDch.
2MDOUTLAddressPMDchReadWritePage41TMP88CS42NGNote1:Donotaccessreservedareasbytheprogram.
Note2:;Cannotbeaccessed.
Note3:Write-onlyregistersandinterruptlatchescannotusetheread-modify-writeinstructions(BitmanipulationinstructionssuchasSET,CLR,etc.
andlogicaloperationinstructionssuchasAND,OR,etc.
).
1FE3HforPMDch.
2MDOUTH1FE4HforPMDch.
2MDCNTL1FE5HforPMDch.
2MDCNTH1FE6HforPMDch.
2MDPRDL1FE7HforPMDch.
2MDPRDH1FE8HforPMDch.
2CMPUL1FE9HforPMDch.
2CMPUH1FEAHforPMDch.
2CMPVL1FEBHforPMDch.
2CMPVH1FECHforPMDch.
2CMPWL1FEDHforPMDch.
2CMPWH1FEEHforPMDch.
2DTR1FEFHforPMDch.
2EMGREL1FF0HforPMDch.
2EDCRA1FF1HforPMDch.
2EDCRB1FF2HforPMDch.
2EDSETL1FF3HforPMDch.
2EDSETH1FF4HforPMDch.
2ELDEGL1FF5HforPMDch.
2ELDEGH1FF6HforPMDch.
2AMPL1FF7HforPMDch.
2AMPH1FF8HforPMDch.
2EDCAPL1FF9HforPMDch.
2EDCAPH1FFAHforPMDch.
2WFMDR1FFBH1FFCHReserved1FFDHReserved1FFEHReserved1FFFHReservedAddressPMDchReadWritePage424.
SpecialFunctionRegister4.
2DBRTMP88CS42NGPage43TMP88CS42NG5.
Input/OutputPortsTheTMP88CS42NGcontains8input/outputportscomprisedof55pins.
Alloutputportscontainalatch,andtheoutputdatathereforeareretainedbythelatch.
Butnoneoftheinputportshavealatch,soitisdesirablethattheinputdataberetainedexternallyuntilitisreadout,orreadseveraltimesbeforebeingprocessed.
Figure5-1showsinput/outputtiming.
Thetimingatwhichexternaldataisreadinfrominput/outputportsisS1stateinthereadcycleofinstructionexe-cution.
Becausethistimingcannotberecognizedfromtheoutside,transientinputdatasuchaschatteringneedstobedealtwithinaprogram.
Thetimingatwhichdataisforwardedtoinput/outputportsisS2stateinthewritecycleofinstructionexecution.
Note:Theread/writecyclepositionsvarydependingoninstructions.
Figure5-1ExampleofInput/OutputTimingPrimaryFunctionSecondaryFunctionsPortP04-bitI/OportTimer/counterinput,serialinterfaceinput/output,andhigh-speedPWMout-putPortP18-bitI/OportExternalinterruptinput,timer/counterinput/output,divideroutput,andmotorcontrolcircuitinputPortP23-bitI/OportExternalinterruptinput,timer/counterinput/output,andSTOPmodereleasesignalinputPortP38-bitI/OportMotorcontrolinput/outputPortP48-bitI/OportTimer/counteroutput,serialinterfaceinput/output,motorcontrolcircuitinputPortP58-bitI/OportMotorcontrolcircuitinput/outputPortP68-bitI/OportAnaloginputandmotorcontrolcircuitoutputPortP78-bitI/OportAnaloginputandmotorcontrolcircuitoutputInstructionexecutioncycleInputstrobeDatainputExample:LDA,(x)FetchcycleFetchcycleReadcycleS0S1S2S3S0S1S2S3S0S1S2S3InstructionexecutioncycleOutputlatchpulseDataoutputExample:LD(x),AFetchcycleFetchcycleWritecycleS0S1S2S3S0S1S2S3S0S1S2S3(a)Inputtiming(b)OutputtimingPage445.
Input/OutputPortsTMP88CS42NGWhenanoperationisperformedforreadfromanyinput/outputportexceptprogrammableinput/outputports,whethertheinputvalueofthepinorthecontentoftheoutputlatchisreaddependsontheinstructionexecuted,asshownbelow.
1.
Instructionswhichreadthecontentoftheoutputlatch-XCHr,(src)-SET/CLR/CPL(src).
b-SET/CLR/CPL(pp).
g-LD(src).
b,CF-LD(pp).
b,CF-XCHCF,(src).
b-ADD/ADDC/SUB/SUBB/AND/OR/XOR(src),n-ADD/ADDC/SUB/SUBB/AND/OR/XOR(src),(HL)instructions,the(src)sidethereof-MXOR(src),m2.
InstructionswhichreadtheinputvalueofthepinAnyinstructionsotherthanthoselistedaboveandADD/ADDC/SUB/SUBB/AND/OR/XOR(src),(HL)instructions,the(HL)sidethereofPage45TMP88CS42NG5.
1PortP0(P03toP00)PortP0isa4-bitinput/outputportsharedwithserialinterfaceinput/output.
ThisportisswitchedbetweeninputandoutputmodesusingtheP0portinput/outputcontrolregister(P0CR).
Whenreset,theP0CRregisterisinitializedto0,withtheP0portsetforinputmode.
Also,theoutputlatch(P0DR)isinitializedto0whenreset.
TheP0portcontainsbitwiseprogrammableopen-draincontrol.
TheP0portopen-draincontrolregister(P0ODE)isusedtoselectopen-drainortri-statemodefortheport.
Whenreset,theP0ODEregisterisinitializedto0,withtri-statemodeselectedfortheport.
Figure5-2PortP0Note1:Evenwhenopen-drainmodeisselected,theprotectivedioderemainsconnected.
Therefore,donotapplyvoltagesexceedingVDD.
Note2:Read-Modify-Write(RMW)operationexecutesatopen-drainmodeisselected,readouttheoutputlatchstates.
Whenanyotherinstructionisexecuted,externalpinstatesisreadout.
Note3:*:Don'tcareP0PortInput/OutputRegistersP0DR(00000H)76543210P03HPWM1P02HPWM0P01TC6OTXD2P00TC6IRXD2Read/Write(Initialvalue:****0000)TC6O:PDO6,PWM6,PPG6P0CR(0000AH)76543210(Initialvalue:****0000)P0CRP0portinput/outputcontrol(Specifybitwise)0:Inputmode1:OutputmodeR/WP0ODE(01F80H)76543210(Initialvalue:****0000)P0ODEP0portopen-draincontrol(Specifybitwise)0:Tri-state1:OpendrainR/WOutputlatchP0CRiDataoutputControlinputvaluesExternalinputCRControlinputControloutputDatainputP0iNote:i=3to0DQ10100001Page465.
Input/OutputPortsTMP88CS42NG5.
2PortP1(P17toP10)PortP1isan8-bitinput/outputportsharedwithexternalinterruptinput,timer/counterinput/output,anddivideroutput.
ThisportisswitchedbetweeninputandoutputmodesusingtheP1portinput/outputcontrolregister(P1CR).
Whenreset,theP1CRregisterisinitializedto0,withtheP1portsetforinputmode.
Also,theoutputlatch(P1DR)isinitializedto0whenreset.
Figure5-3PortP1P1PortInput/OutputRegistersP1DR(00001H)76543210P17PDW2P16PDV2P15PDU2P14PPG1TC5OP13DVOTC5IP12INT2TC1P11INT1P10INT0Read/Write(Initialvalue:00000000)TC5O:PDO5,PWM5P1CR(0000BH)76543210(Initialvalue:00000000)P1CRP1portinput/outputcontrol(Specifybitwise)0:Inputmode1:OutputmodeR/WOutputlatchP1CRiDataoutputCRControlinputControloutputDatainputP1iDQ10100001ControlinputvaluesExternalinputNote:i=7to0Page47TMP88CS42NG5.
3PortP2(P22toP20)PortP2isa3-bitinput/outputportsharedwithexternalinterruptinputandSTOPmodereleasesignal.
Whenusingthisportasthesefunctionalpinsoraninputport,settheoutputlatchto1.
Whenreset,theoutputlatchisinitializedto1.
WerecommendusingtheP20pinasexternalinterruptinput,STOPmodereleasesignalinput,orinputport.
Whenusingthisportasanoutputport,notethattheinterruptlatchissetbyafallingedgeofoutputpulse.
AndnotethatoutputsonthisportduringSTOPmodegotoahigh-impedancestateevenifSYSCR1isset"1",becauseP20portisalsousedasSTOPport.
WhenareadinstructionisexecutedonP2port,indeterminatevaluesarereadinfrombits7to3.
Whenanyread-modify-writeinstructionisexecutedonP2port,thecontentoftheoutputlatchisreadout.
Whenanyotherinstructionisexecuted,theexternalpinstateisreadout.
Figure5-4PortP2Note1:WhenareadinstructionisexecutedonP2port,indeterminatevaluesarereadinfrombits7to3.
Note2:PortP20isusedasSTOPpin.
Therefore,whenstopmodeisstarted,SYSCR1doesnotaffecttoP20,andP20becomesHigh-Zmode.
Note3:*:Don'tcareP2PortInput/OutputRegistersP2DR(00002H)76543210P22TC4INT4PWM4PDO4P21TC3INT3P20INT5STOPRead/Write(Initialvalue:*****111)OutputlatchDataoutputDatainputControlinputSET/CLR/CPL,etc.
CMP/MCMP/TEST,etc.
P20,P21,P22DQPage485.
Input/OutputPortsTMP88CS42NG5.
4PortP3(P37toP30)PortP3isan8-bitinput/outputport.
ThisportisswitchedbetweeninputandoutputmodesusingtheP3portInput/outputcontrolregister(P3CR).
Whenreset,theP3CRregisterisinitializedto0,withtheP3portsetforinputmode.
Also,theoutputlatch(P3DR)isinitializedto0whenreset.
TheP3portcontainsbitwiseprogrammableopen-draincontrol.
TheP3portopen-draincontrolregister(P3ODE)isusedtoselectopen-drainortri-statemodefortheport.
Whenreset,theP3ODEregisterisinitializedto0,withtri-statemodeselectedfortheport.
Figure5-5PortP3Note1:Evenwhenopen-drainmodeisselected,theprotectivedioderemainsconnected.
Therefore,donotapplyvoltagesexceedingVDD.
Note2:Read-modify-write(RMW)operationexecutesatopen-drainmodeisselected,readouttheoutputlatchstates.
Whenanyotherinstructionisexecuted,externalpinstatesisreadout.
Note3:ForPMDcircuitoutput,settheP3DRoutputlatchto1.
Note4:WhenusingP3portasaninput/outputport,disabletheEMG1circuit.
P3PortInput/OutputRegistersP3DR(00003H)76543210P37CL1P36EMG1P35U1P34V1P33W1P32X1P31Y1P30Z1Read/Write(Initialvalue:00000000)P3CR(01F89H)76543210(Initialvalue:00000000)P3CRP3portinput/outputcontrol(Specifybitwise)0:Inputmode1:OutputmodeR/WP3ODE(01F83H)76543210(Initialvalue:00000000)P3ODEP3portopen-draincontrol(Specifybitwise)0:Tri-state1:OpendrainR/WOutputlatchP3CRiDataoutputControlinputvaluesExternalinputCRControlinputControloutputDatainputP3iNote:i=7to0DQ10100001Page49TMP88CS42NG5.
5PortP4(P47toP40)PortP4isan8-bitinput/outputportsharedwithserialinterfaceinput/output.
ThisportisswitchedbetweeninputandoutputmodesusingtheP4portinput/outputcontrolregister(P4CR).
Whenreset,theP4CRregisterisinitializedto0,withtheP4portsetforinputmode.
Also,theoutputlatch(P4DR)isinitializedto0whenreset.
TheP4portcontainsbitwiseprogrammableopen-draincontrol.
TheP4portopen-draincontrolregister(P4ODE)isusedtoselectopen-drainortri-statemodefortheport.
Whenreset,theP4ODEregisterisinitializedto0,withtri-statemodeselectedfortheport.
Figure5-6PortP4Note1:Evenwhenopen-drainmodeisselected,theprotectivedioderemainsconnected.
Therefore,donotapplyvoltagesexceedingVDD.
Note2:Read-modify-write(RMW)operationexecutesatopen-drainmodeisselected,readouttheoutputlatchstates.
Whenanyotherinstructionisexecuted,externalpinstatesisreadout.
Note3:Whenusingthe16-bittimer(CTC)asanordinarytimer,setP47(CTC)foroutputmode.
P4PortInput/OutputRegistersP4DR(00004H)76543210P47CTCP46PPG2P45SOTXD1P44SIRXD1P43SCKP42PDU1P41PDV1P40PDW1(Initialvalue:00000000)P4CR(01F8AH)76543210(Initialvalue:00000000)P4CRP4portinput/outputcontrol(Specifybitwise)0:Inputmode1:OutputmodeR/WP4ODE(01F84H)76543210(Initialvalue:00000000)P4ODEP4portopen-draincontrol(Specifybitwise)0:Tri-state1:OpendrainR/WOutputlatchP4CRiDataoutputControlinputvaluesExternalinputCRControlinputControloutputDatainputP4iNote:i=7to0DQ10100001Page505.
Input/OutputPortsTMP88CS42NG5.
6PortP5(P57toP50)PortP5isan8-bitinput/outputport.
ThisportisswitchedbetweeninputandoutputmodesusingtheP5portinput/outputcontrolregister(P5CR).
Whenreset,theP5CRregisterisinitializedto0,withtheP5portsetforinputmode.
Also,theoutputlatch(P5DR)isinitializedto0whenreset.
TheP5portcontainsbitwiseprogrammableopen-draincontrol.
TheP5portopen-draincontrolregister(P5ODE)isusedtoselectopen-drainortri-statemodefortheport.
Whenreset,theP5ODEregisterisinitializedto0,withtri-statemodeselectedfortheport.
Figure5-7PortP5Note1:Evenwhenopen-drainmodeisselected,theprotectivedioderemainsconnected.
Therefore,donotapplyvoltagesexceedingVDD.
Note2:Read-modify-write(RMW)operationexecutesatopen-drainmodeisselected,readouttheoutputlatchstates.
Whenanyotherinstructionisexecuted,externalpinstatesisreadout.
Note3:ForPMDcircuitoutput,settheP5DRoutputlatchto1.
Note4:WhenusingP5portasaninput/outputport,disabletheEMG2circuit.
P5PortInput/OutputRegistersP5DR(00005H)76543210P57Z2P56Y2P55X2P54W2P53V2P52U2P51EMG2P50CL2Read/Write(Initialvalue:00000000)P5CR(01F8BH)76543210(Initialvalue:00000000)P5CRP5portinput/outputcontrol(Specifybitwise)0:Inputmode1:OutputmodeR/WP5ODE(01F85H)76543210(Initialvalue:00000000)P5ODEP5portopen-draincontrol(Specifybitwise)0:Tri-state1:OpendrainR/WOutputlatchP5CRiDataoutputControlinputvalueExternalinputCRControlinputControloutputDatainputP5iNote:i=7to0DQ10100001Page51TMP88CS42NG5.
7PortP6(P67toP60)PortP6isan8-bitinput/outputportsharedwithADconverteranaloginput.
ThisportisswitchedbetweeninputandoutputmodesusingtheP6portinput/outputcontrolregister(P6CR),P6portoutputlatch(P6DR),andADC-CRA.
Whenreset,theP6CRRegisterandtheP6DRoutputlatchareinitializedto0whileADC-CRAissetto1,sothatP67toP60havetheirinputsfixedlow(=0).
WhenusingtheP6portasaninputport,setthecorrespondingbitsforinputmode(P6CR=0,P6DR=1).
Thereasonwhytheoutputlatch=1isbecauseitisnecessarytopreventcurrentfromflowingintotheshareddatainputcircuit.
Whenusingtheportasanoutputport,settheP6CRRegister'scorrespondingbitsto1.
Whenusingtheportforanaloginput,setthecorre-spondingbitsforanaloginput(P6CR=0,P6DR=0).
ThensetADCCRA=0,andADconversionwillstart.
Theportsusedforanaloginputmusthavetheiroutputlatchessetto0beforehand.
TheactualinputchannelsforADconversionareselectedusingADCCRA.
AlthoughthebitsofP6portnotusedforanaloginputcanbeusedasinput/outputports,donotexecuteoutputinstructionsontheseportsduringADconversion.
ThisisnecessarytomaintaintheaccuracyofADconversion.
Also,donotapplyrapidlychangingsignalstoportsadjacenttoanaloginputduringADconversion.
IfaninputinstructionisexecutedwhiletheP6DRoutputlatchisclearedto0,data"0"isreadinfromsaidbits.
Figure5-8PortP6Datainput(P6)Dataoutput(P6)STOPAINDSSAINP6CRiP6CRiinputP6iNote1:i=7to0Note2:STOPexistsinSYSCR1registerbit7.
Note3:SAINselectsADinputchannels.
DQDQAnaloginputPage525.
Input/OutputPortsTMP88CS42NGNote1:Thepinsusedforanaloginputcannotbesetforoutputmode(P6CR=1)becausetheybecomeshortedwithexternalsig-nals.
Note2:Whenareadinstructionisexecutedonbitsofthisportwhicharesetforanaloginputmode,data"0"isreadin.
Note3:ForDBOUT1output,settheP6DR(P67)outputlatchto1.
Note4:Whenusingthisportininputmode(includinganaloginput),donotusebitmanipulatingorotherread-modify-writeinstruc-tions.
Whenareadinstructionisexecutedonthebitsofthisportthataresetforinput,thecontentsofthepinsarereadin,sothatifaread-modify-writeinstructionisexecuted,theiroutputlatchesmayberewritten,makingthepinsunabletoacceptinput.
(Aread-modify-writeinstructionfirstreadsdatafromalloftheeightbitsandaftermodifyingthem(bitmanip-ulation),writesdataforalloftheeightbitstotheoutputlatches.
)P6PortInput/OutputRegistersP6DR(00006H)76543210P67AIN7DBOUT1P66AIN6P65AIN5P64AIN4P63AIN3P62AIN2P61AIN1P60AIN0Read/Write(Initialvalue:00000000)P6CR(01F8CH)76543210(Initialvalue:00000000)P6CRP6portinput/outputcontrol(Specifybitwise)AINDS=1(whennotusingAD)AINDS=0(whenusingAD)R/WP6DR="0"P6DR="1"P6DR="0"P6DR="1"0Inputsfixedto0InputmodeAnalogInputmode(Note2)Inputmode1OutputmodePage53TMP88CS42NG5.
8PortP7(P77toP70)PortP7isan8-bitinput/outputportsharedwithADconverteranaloginput.
ThisportisswitchedbetweeninputandoutputmodesusingtheP7portinput/outputcontrolregister(P7CR),P7portoutputlatch(P7DR),andADC-CRA.
Whenreset,theP7CRregisterandtheP7DRoutputlatchareinitializedto0whileADC-CRAissetto1,sothatP77toP70havetheirinputsfixedlow(=0).
WhenusingtheP7portasaninputport,setthecorrespondingbitsforinputmode(P7CR=0,P7DR=1).
Thereasonwhytheoutputlatch=1isbecauseitisnecessarytopreventcurrentfromflowingintotheshareddatainputcircuit.
Whenusingtheportasanoutputport,settheP7CRRegister'scorrespondingbitsto1.
Whenusingtheportforanaloginput,setthecorre-spondingbitsforanaloginput(P7CR=0,P7DR=0).
ThensetADCCRA=0,andADconversionwillstart.
Theportsusedforanaloginputmusthavetheiroutputlatchessetto0beforehand.
TheactualinputchannelsforADconversionareselectedusingADCCRA.
AlthoughthebitsofP7portnotusedforanaloginputcanbeusedasinput/outputports,donotexecuteoutputinstructionsontheseportsduringADconversion.
ThisisnecessarytomaintaintheaccuracyofADconversion.
Also,donotapplyrapidlychangingsignalstoportsadjacenttoanaloginputduringADconversion.
IfaninputinstructionisexecutedwhiletheP7DRoutputlatchisclearedto0,data"0"isreadinfromsaidbits.
Figure5-9PortP7Datainput(P7)Dataoutput(P7)STOPAINDSSAINP7CRiP7CRiinputP7iNote1:i=7to0Note2:STOPexistsinSYSCR1registerbit7.
Note3:SAINselectsADinputchannels.
DQDQAnaloginputPage545.
Input/OutputPortsTMP88CS42NGNote1:Thepinsusedforanaloginputcannotbesetforoutputmode(P7CR=1)becausetheybecomeshortedwithexternalsig-nals.
Note2:Whenareadinstructionisexecutedonbitsofthisportwhicharesetforanaloginputmode,data"0"isreadin.
Note3:ForDBOUT2output,settheP7DR(P77)outputlatchto1.
Note4:Whenusingthisportininputmode(includinganaloginput),donotusebitmanipulatingorotherread-modify-writeinstruc-tions.
Whenareadinstructionisexecutedonthebitsofthisportthataresetforinput,thecontentsofthepinsarereadin,sothatifaread-modify-writeinstructionisexecuted,theiroutputlatchesmayberewritten,makingthepinsunabletoacceptinput.
(Aread-modify-writeinstructionfirstreadsdatafromalloftheeightbitsandaftermodifyingthem(bitmanip-ulation),writesdataforallofthe8bitstotheoutputlatches.
)P7PortInput/OutputRegistersP7DR(00007H)76543210P77AIN15DBOUT2P76AIN14P75AIN13P74AIN12P73AIN11P72AIN10P71AIN9P70AIN8Read/Write(Initialvalue:00000000)P7CR(01F8DH)76543210(Initialvalue:00000000)P7CRP7portinput/outputcontrol(Specifybitwise)AINDS=1(whennotusingAD)AINDS=0(whenusingAD)R/WP7DR="0"P7DR="1"P7DR="0"P7DR="1"0Inputsfixedto0InputmodeAnalogInputmode(Note2)Inputmode1OutputmodePage55TMP88CS42NG6.
TimeBaseTimer(TBT)andDividerOutput(DVO)6.
1TimeBaseTimerThetimebasetimergeneratestimebaseforkeyscanning,dynamicdisplaying,etc.
Italsoprovidesatimebasetimerinterrupt(INTTBT).
AnINTTBT(TimeBaseTimerInterrupt)isgeneratedonthefirstfallingedgeofsourceclock(Thedividerout-putofthetiminggeneratorwhichisselectedbyTBTCK.
)aftertimebasetimerhasbeenenabled.
Thedividerisnotclearedbytheprogram;therefore,onlythefirstinterruptmaybegeneratedaheadofthesetinterruptperiod(Figure6-2).
Theinterruptfrequency(TBTCK)mustbeselectedwiththetimebasetimerdisabled(TBTEN="0").
(Theinter-ruptfrequencymustnotbechangedwiththedisblefromtheenablestate.
)Bothfrequencyselectionandenablingcanbeperformedsimultaneously.
Figure6-1TimeBaseTimerconfigurationFigure6-2TimeBaseTimerInterruptExample:Setthetimebasetimerfrequencytofc/216[Hz]andenableanINTTBTinterrupt.
LD(TBTCR),00000010B;TBTCK←010(Freq.
set)LD(TBTCR),00001010B;TBTEN←1(TBTenable)DISET(EIRL).
6EIfc/223,fc/224fc/221,fc/222fc/216,fc/217fc/214,fc/215fc/213,fc/214fc/212,fc/213fc/211,fc/212fc/29,fc/210TBTCRTBTENTBTCK3MPXSourceclockFallingedgedetectorTimebasetimercontrolregisterINTTBTinterruptrequestSourceclockEnableTBTInterruptperiodTBTCRINTTBTinterruptrequestPage566.
TimeBaseTimer(TBT)andDividerOutput(DVO)6.
1TimeBaseTimerTMP88CS42NGTimeBaseTimeriscontroledbyTimeBaseTimercontrolregister(TBTCR).
Note1:fc;High-frequencyclock[Hz],*;Don'tcareNote2:Alwaysset"0"inbit4onTBTCRregister.
TimeBaseTimerControlRegister76543210TBTCR(00036H)(DVOEN)(DVOCK)0TBTENTBTCK(InitialValue:00000000)TBTENTimeBaseTimerEnable/Disable0:Disable1:EnableTBTCKTimeBaseTimerinterruptFrequencyselect:[Hz]NORMAL,IDLEModeR/WDV1CK=0DV1CK=1000fc/223fc/224001fc/221fc/222010fc/216fc/217011fc/214fc/215100fc/213fc/214101fc/212fc/213110fc/211fc/212111fc/29fc/210Table6-1TimeBaseTimerInterruptFrequency(Example:fc=20.
0MHz)TBTCKTimeBaseTimerInterruptFrequency[Hz]NORMAL,IDLEModeDV1CK=0DV1CK=10002.
381.
200019.
534.
78010305.
18153.
500111220.
70610.
351002441.
401220.
701014882.
832441.
401109765.
634882.
8311139063.
0019531.
25Page57TMP88CS42NG6.
2DividerOutput(DVO)Approximately50%dutypulsecanbeoutputusingthedivideroutputcircuit,whichisusefulforpiezoelectricbuzzerdrive.
DivideroutputisfromDVOpin.
Figure6-3DividerOutputTheDividerOutputiscontrolledbytheTimeBaseTimerControlRegister(TBTCR).
Note1:Selectionofdivideroutputfrequency(DVOCK)mustbemadewhiledivideroutputisdisabled(DVOEN="0").
Also,inotherwords,whenchangingthestateofthedivideroutputfrequencyfromenabled(DVOEN="1")todisable(DVOEN="0"),donotchangethesettingofthedivideroutputfrequency.
Note2:IncaseofusingDVOoutput,setoutputmodebyP1CRregisteraftersettingtherelatedportoutputlatchto"1"byP1DRregister.
Note3:fc;High-frequencyclock[Hz],*;Don'tcareNote4:Besuretowrite"0"toTBTCRRegisterbit4.
TimeBaseTimerControlRegister76543210TBTCR(00036H)DVOENDVOCK"0"(TBTEN)(TBTCK)(Initialvalue:00000000)DVOENDivideroutputenable/disable0:Disable1:EnableR/WDVOCKDividerOutput(DVO)frequencyselection:[Hz]NORMAL,IDLEModeR/WDV1CK=0DV1CK=100fc/213fc/21401fc/212fc/21310fc/211fc/21211fc/210fc/211TBTCROutputlatchPortoutputlatchMPXDVOENTBTCRDVOpinoutputDVOCKDivideroutputcontrolregister(a)configuration(b)TimingchartDataoutput2ABCYDSDQDVOpinfc/213,fc/214fc/212,fc/213fc/211,fc/212fc/210,fc/211Page586.
TimeBaseTimer(TBT)andDividerOutput(DVO)6.
2DividerOutput(DVO)TMP88CS42NGExample:2.
44kHzpulseoutput(fc=20.
0MHz)PortsettingLD(TBTCR),00000000B;DVOCK←"00"LD(TBTCR),10000000B;DVOEN←"1"Table6-2DividerOutputFrequency(Example:fc=20.
0MHz)DVOCKDividerOutputFrequency[Hz]NORMAL,IDLEModeDV1CK=0DV1CK=1002.
4415k1.
22075k014.
8825k2.
4415k109.
765k4.
8825k1119.
5325k9.
765kPage59TMP88CS42NG7.
WatchdogTimer(WDT)Thewatchdogtimerisafail-safesystemtodetectrapidlytheCPUmalfunctionssuchasendlessloopsduetospu-riousnoisesorthedeadlockconditions,andreturntheCPUtoasystemrecoveryroutine.
Thewatchdogtimersignalfordetectingmalfunctionscanbeprogrammedonlyonceas"resetrequest"or"pseudononmaskableinterruptrequest".
Upontheresetrelease,thissignalisinitializedto"resetrequest".
Whenthewatchdogtimerisnotusedtodetectmalfunctions,itcanbeusedasthetimertoprovideaperiodicinter-rupt.
Note:Caremustbetakeninsystemdesignsincethewatchdogtimerfunctionsarenotbeoperatedcompletelyduetoeffectofdisturbingnoise.
7.
1WatchdogTimerConfigurationFigure7-1WatchdogTimerConfiguration0034HOverflowWDToutputInternalresetBinarycountersWDTOUTWritingclearcodeWritingdisablecodeWDTENWDTT20035HWatchdogtimercontrolregistersWDTCR1WDTCR2INTWDTinterruptrequestInterruptrequestResetrequestResetreleaseClockClear12ControllerQSRSRQSelectorfc/223,fc/224fc/221,fc/222fc/219,fc/220fc/217,fc/218Page607.
WatchdogTimer(WDT)7.
2WatchdogTimerControlTMP88CS42NG7.
2WatchdogTimerControlThewatchdogtimeriscontrolledbythewatchdogtimercontrolregisters(WDTCR1andWDTCR2).
Thewatch-dogtimerisautomaticallyenabledaftertheresetrelease.
7.
2.
1MalfunctionDetectionMethodsUsingtheWatchdogTimerTheCPUmalfunctionisdetected,asshownbelow.
1.
Setthedetectiontime,selecttheoutput,andclearthebinarycounter.
2.
Clearthebinarycounterrepeatedlywithinthespecifieddetectiontime.
IftheCPUmalfunctionssuchasendlessloopsorthedeadlockconditionsoccurforsomereason,thewatch-dogtimeroutputisactivatedbythebinary-counteroverflowunlessthebinarycountersarecleared.
WhenWDTCR1issetto"1"atthistime,theresetrequestisgeneratedandtheninternalhardwareisinitialized.
WhenWDTCR1issetto"0",awatchdogtimerinterrupt(INTWDT)isgenerated.
ThewatchdogtimertemporarilystopscountingintheSTOPmodeincludingthewarm-uporIDLEmode,andautomaticallyrestarts(continuescounting)whentheSTOP/IDLEmodeisinactivated.
Note:Thewatchdogtimerconsistsofaninternaldividerandatwo-stagebinarycounter.
Whentheclearcode4EHiswritten,onlythebinarycounteriscleared,butnottheinternaldivider.
Theminimumbinary-counteroverflowtime,thatdependsonthetimingatwhichtheclearcode(4EH)iswrittentotheWDTCR2register,maybe3/4ofthetimesetinWDTCR1.
Therefore,writetheclearcodeusingacycleshorterthan3/4ofthetimesettoWDTCR1.
Example:Settingthewatchdogtimerdetectiontimeto221/fc[s],andresettingtheCPUmalfunctiondetectionLD(WDTCR2),4EH:Clearsthebinarycounters.
LD(WDTCR1),00001101B:WDTT←10,WDTOUT←1LD(WDTCR2),4EH:Clearsthebinarycounters(alwaysclearsimmediatelybeforeandafterchangingWDTT).
Within3/4ofWDTdetectiontime::LD(WDTCR2),4EH:Clearsthebinarycounters.
Within3/4ofWDTdetectiontime::LD(WDTCR2),4EH:Clearsthebinarycounters.
Page61TMP88CS42NGNote1:AfterclearingWDTCR1to"0",theprogramcannotsetitto"1".
Note2:fc:High-frequencyclock[Hz],*:Don'tcareNote3:WDTCR1isawrite-onlyregisterandmustnotbeusedwithanyofread-modify-writeinstructions.
IfWDTCR1isread,aunknowndataisread.
Note4:ToactivatetheSTOPmode,disablethewatchdogtimerorclearthecounterimmediatelybeforeenteringtheSTOPmode.
Afterclearingthecounter,clearthecounteragainimmediatelyaftertheSTOPmodeisinactivated.
Note5:ToclearWDTCR1,settheregisterinaccordancewiththeproceduresshownin"7.
2.
3WatchdogTimerDis-able".
Note6:Ifthewatchdogtimerisdisabledduringwatchdogtimerinterruptprocessing,thewatchdogtimerinterruptwillneverbecleared.
Therefore,clearthewatchdogtimer(settheclearcode(4EH)toWDTCR2)beforedisablingit,ordisablethewatchdogtimerasufficienttimebeforeitoverflows.
Note7:Thewatchdogtimerconsistsofaninternaldividerandatwo-stagebinarycounter.
Whenclearcode(4EH)iswritten,onlythebinarycounteriscleared,nottheinternaldivider.
Dependingonthetimingatwhichclearcode(4EH)iswrittenontheWDTCR2register,theoverflowtimeofthebinarycountermaybeatminimum3/4ofthetimesetinWDTCR1.
Thus,writetheclearcodeusingashortercyclethan3/4ofthetimesetinWDTCR1.
Note1:ThedisablecodeisvalidonlywhenWDTCR1=0.
Note2:*:Don'tcareNote3:Thebinarycounterofthewatchdogtimermustnotbeclearedbytheinterrupttask.
Note4:Writetheclearcode(4EH)usingacycleshorterthan3/4ofthetimesetinWDTCR1.
Note5:WDTCR2isawrite-onlyregisterandmustnotbeusedwithanyofread-modify-writeinstructions.
IfWDTCR2isread,aunknowndataisread.
7.
2.
2WatchdogTimerEnableSettingWDTCR1to"1"enablesthewatchdogtimer.
SinceWDTCR1isinitializedto"1"duringreset,thewatchdogtimerisenabledautomaticallyaftertheresetrelease.
WatchdogTimerControlRegister1WDTCR1(0034H)76543210WDTENWDTTWDTOUT(Initialvalue:****1001)WDTENWatchdogtimerenable/disable0:Disable(WritingthedisablecodetoWDTCR2isrequired.
)1:EnableWriteonlyWDTTWatchdogtimerdetectiontime[s]NORMALmodeWriteonlyDV1CK=0DV1CK=100225/fc226/fc01223/fc224/fc10221fc222fc11219/fc220/fcWDTOUTWatchdogtimeroutputselect0:Interruptrequest1:ResetrequestWriteonlyWatchdogTimerControlRegister2WDTCR2(0035H)76543210(Initialvalue:WDTCR2WriteWatchdogtimercontrolcode4EH:Clearthewatchdogtimerbinarycounter(Clearcode)B1H:Disablethewatchdogtimer(Disablecode)Others:InvalidWriteonlyPage627.
WatchdogTimer(WDT)7.
2WatchdogTimerControlTMP88CS42NG7.
2.
3WatchdogTimerDisableTodisablethewatchdogtimer,settheregisterinaccordancewiththefollowingprocedures.
Settingthereg-isterinotherprocedurescausesamalfunctionofthemicrocontroller.
1.
Settheinterruptmasterflag(IMF)to"0".
2.
SetWDTCR2totheclearcode(4EH).
3.
SetWDTCR1to"0".
4.
SetWDTCR2tothedisablecode(B1H).
Note:Whilethewatchdogtimerisdisabled,thebinarycountersofthewatchdogtimerarecleared.
Note:Ifthewatchdogtimerisdisabledduringwatchdogtimerinterruptprocessing,thewatchdogtimerinterruptwillneverbecleared.
Therefore,clearthewatchdogtimer(settheclearcode(4EH)toWDTCR2)beforedisablingit,ordisablethewatchdogtimerasufficienttimebeforeitoverflows.
7.
2.
4WatchdogTimerInterrupt(INTWDT)WhenWDTCR1isclearedto"0",awatchdogtimerinterruptrequest(INTWDT)isgeneratedbythebinary-counteroverflow.
Awatchdogtimerinterruptisthenon-maskableinterruptwhichcanbeacceptedregardlessoftheinterruptmasterflag(IMF).
Whenawatchdogtimerinterruptisgeneratedwhiletheotherinterruptincludingawatchdogtimerinterruptisalreadyaccepted,thenewwatchdogtimerinterruptisprocessedimmediatelyandthepreviousinterruptisheldpending.
Therefore,ifwatchdogtimerinterruptsaregeneratedcontinuouslywithoutexecutionoftheRETNinstruction,toomanylevelsofnestingmaycauseamalfunctionofthemicrocontroller.
Togenerateawatchdogtimerinterrupt,setthestackpointerbeforesettingWDTCR1.
Example:DisablingthewatchdogtimerDI:IMF←0LD(WDTCR2),04EH:ClearsthebinarycoutnerLDW(WDTCR1),0B101H:WDTEN←0,WDTCR2←DisablecodeEI:IMF←1Table7-1WatchdogTimerDetectionTime(Example:fc=20MHz)WDTTWatchdogTimerDetectionTime[s]NORMALModeDV1CK=0DV1CK=1001.
6783.
35501419.
430m838.
861m10104.
858m209.
715m1126.
214m52.
429mPage63TMP88CS42NG7.
2.
5WatchdogTimerResetWhenabinary-counteroverflowoccurswhileWDTCR1issetto"1",awatchdogtimerresetrequestisgenerated.
Whenawatchdogtimerresetrequestisgenerated,theinternalhardwareisreset.
Theresettimeismaximum24/fc[s](max.
1.
2μs@fc=20MHz).
Figure7-2WatchdogtimerInterruptandResetExample:SettingwatchdogtimerinterruptLDSP,08BFH:SetsthestackpointerLD(WDTCR1),00001000B:WDTOUT←0ClockBinarycounterOverflowINTWDTinterruptrequest(WDTCR1="0")217/fc219/fc[s](WDTT=11B)Write4EHtoWDTCR212301230Internalreset(WDTCR1="1")AresetoccursPage647.
WatchdogTimer(WDT)7.
2WatchdogTimerControlTMP88CS42NGPage65TMP88CS42NG8.
16-BitTimerCounter1(TC1)8.
1ConfigurationFigure8-1TimerCounter1(TC1)pinTC1METT1StartCaptureClearSourceclockPPGoutputmodeWritetoTC1CR16-bitup-counterClearTC1DRBSelectorTC1DRATC1CRTC1controlregisterMatchINTTC1interriptTFF1ACAP1TC1CKWindowmodeSetToggleQ2ToggleSetClearQYADBCSBAYSTC1SclearMPPG1PPGoutputmodeInternalresetSEnableMCAP1SYABTC1S2SetClearCommandstartDecoderExternaltriggerstartEdgedetectorNote:FunctionI/OmaynotoperatedependingonI/Oportsetting.
Formoredetails,seethechapter"I/OPort".
Port(Note)QPulsewidthmeasurementmodeFallingRisingtriggerExternalCMP16-bittimerregisterA,BPulsewidthmeasurementmodePort(Note)fc/211,fc/212fc/27,fc/28fc/23,fc/24Page668.
16-BitTimerCounter1(TC1)8.
2TimerCounterControlTMP88CS42NG8.
2TimerCounterControlTheTimerCounter1iscontrolledbytheTimerCounter1controlregister(TC1CR)andtwo16-bittimerregisters(TC1DRAandTC1DRB).
Note1:fc:High-frequencyclock[Hz]Note2:Thetimerregisterconsistsoftwoshiftregisters.
Avaluesetinthetimerregisterbecomesvalidattherisingedgeofthefirstsourceclockpulsethatoccursaftertheupperbyte(TC1DRAHandTC1DRBH)iswritten.
Therefore,writethelowerbyteandtheupperbyteinthisorder(itisrecommendedtowritetheregisterwitha16-bitaccessinstruction).
Writingonlythelowerbyte(TC1DRALandTC1DRBL)doesnotenablethesettingofthetimerregister.
Note3:Tosetthemode,sourceclock,PPGoutputcontrolandtimerF/Fcontrol,writetoTC1CRduringTC1CR=00.
SetthetimerF/F1controluntilthefirsttimerstartaftersettingthePPGmode.
Note4:Auto-capturecanbeusedonlyinthetimer,eventcounter,andwindowmodes.
TimerRegister1514131211109876543210TC1DRA(0011H,0010H)TC1DRAH(0011H)TC1DRAL(0010H)(Initialvalue:1111111111111111)Read/WriteTC1DRB(0013H,0012H)TC1DRBH(0013H)TC1DRBL(0012H)(Initialvalue:1111111111111111)Read/Write(WriteenabledonlyinthePPGoutputmode)TimerCounter1ControlRegisterTC1CR(000FH)76543210TFF1ACAP1MCAP1METT1MPPG1TC1STC1CKTC1MRead/Write(Initialvalue:00000000)TFF1TimerF/F1control0:Clear1:SetR/WACAP1Autocapturecontrol0:Auto-capturedisable1:Auto-captureenableR/WMCAP1Pulsewidthmeasure-mentmodecontrol0:Doubleedgecapture1:SingleedgecaptureMETT1Externaltriggertimermodecontrol0:Triggerstart1:TriggerstartandstopMPPG1PPGoutputcontrol0:Continuouspulsegeneration1:One-shotTC1STC1startcontrolTimerExtrig-gerEventWin-dowPulsePPGR/W00:StopandcounterclearOOOOOO01:CommandstartO––––O10:Risingedgestart(Ex-trigger/Pulse/PPG)Risingedgecount(Event)Positivelogiccount(Window)–OOOOO11:Fallingedgestart(Ex-trigger/Pulse/PPG)Fallingedgecount(Event)Negativelogiccount(Window)–OOOOOTC1CKTC1sourceclockselect[Hz]NORMAL,IDLEmodeR/WDV1CK=0DV1CK=100fc/211fc/21201fc/27fc/2810fc/23fc/2411Externalclock(TC1pininput)TC1MTC1operatingmodeselect00:Timer/externaltriggertimer/eventcountermode01:Windowmode10:Pulsewidthmeasurementmode11:PPG(Programmablepulsegenerate)outputmodeR/WPage67TMP88CS42NGNote5:Tosetthetimerregisters,thefollowingrelationshipmustbesatisfied.
TC1DRA>TC1DRB>1(PPGoutputmode),TC1DRA>1(othermodes)Note6:SetTC1CRto"0"inthemodeexceptPPGoutputmode.
Note7:SetTC1DRBaftersettingTC1CRtothePPGoutputmode.
Note8:WhentheSTOPmodeisentered,thestartcontrol(TC1CR)isclearedto"00"automatically,andthetimerstops.
AftertheSTOPmodeisexited,settheTC1CRtousethetimercounteragain.
Note9:Usetheauto-capturefunctionintheoperativeconditionofTC1.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondition.
Note10:Sincetheup-countervalueiscapturedintoTC1DRBbythesourceclockofup-counteraftersettingTC1CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC1DRBforthefirsttime.
Page688.
16-BitTimerCounter1(TC1)8.
3FunctionTMP88CS42NG8.
3FunctionTimerCounter1hassixtypesofoperatingmodes:timer,externaltriggertimer,eventcounter,window,pulsewidthmeasurement,programmablepulsegeneratoroutputmodes.
8.
3.
1TimermodeInthetimermode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthetimerregister1A(TC1DRA)valueisdetected,anINTTC1interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscounting.
SettingTC1CRto"1"capturestheup-countervalueintothetimerregister1B(TC1DRB)withtheauto-capturefunction.
Usetheauto-capturefunctionintheoperativeconditionofTC1.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondition.
Sincetheup-countervalueiscapturedintoTC1DRBbythesourceclockofup-counteraftersettingTC1CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC1DRBforthefirsttime.
Table8-1SourceClockforTimerCounter1(Example:fc=20MHz)TC1CKNORMAL,IDLEModeDV1CK=0DV1CK=1Resolution[μs]MaximumTimeSetting[s]Resolution[μs]MaximumTimeSetting[s]00102.
46.
7108204.
813.
4216016.
40.
419412.
80.
8388100.
526.
214m0.
852.
428mExample1:Settingthetimermodewithsourceclockfc/211[Hz]andgeneratinganinterrupt1secondlater(fc=20MHz,CGCR="0")LDW(TC1DRA),2625H;Setsthetimerregister(1s÷211/fc=2625H)DI;IMF="0"SET(EIRD).
2;EnablesINTTC1EI;IMF="1"LD(TC1CR),00000000B;SelectsthesourceclockandmodeLD(TC1CR),00010000B;StartsTC1Example2:Auto-captureLD(TC1CR),01010000B;ACAP1←1::;WaitatleastonecycleoftheinternalsourceclockLDWA,(TC1DRB);ReadsthecapturevaluePage69TMP88CS42NGFigure8-2TimerModeTimingChartMatchdetectACAP1TC1DRBTC1DRAINTTC1interruputrequestSourceclockCounterSourceclockCounter(a)Timermode(b)Auto-capture763450Timerstart1232140CounterclearCapturen+1nnnm+2m+1mmCapturem+2m+1n+1nm1m1m2n1n1n1Page708.
16-BitTimerCounter1(TC1)8.
3FunctionTMP88CS42NG8.
3.
2ExternalTriggerTimerModeIntheexternaltriggertimermode,theup-counterstartscountingbytheinputpulsetriggeringoftheTC1pin,andcountsupattheedgeoftheinternalclock.
Forthetriggeredgeusedtostartcounting,eithertherisingorfallingedgeisdefinedinTC1CR.
WhenTC1CRissetto"1"(triggerstartandstop)Whenamatchbetweentheup-counterandtheTC1DRAvalueisdetectedafterthetimerstarts,theup-counterisclearedandhaltedandanINTTC1interruptrequestisgenerated.
Iftheedgeoppositetotriggeredgeisdetectedbeforedetectingamatchbetweentheup-counterandtheTC1DRA,theup-counterisclearedandhaltedwithoutgeneratinganinterruptrequest.
Therefore,thismodecanbeusedtodetectexceedingthespecifiedpulsebyinterrupt.
Afterbeinghalted,theup-counterrestartscountingwhenthetriggeredgeisdetected.
WhenTC1CRissetto"0"(triggerstart)Whenamatchbetweentheup-counterandtheTC1DRAvalueisdetectedafterthetimerstarts,theup-counterisclearedandhaltedandanINTTC1interruptrequestisgenerated.
Theedgeoppositetothetriggeredgehasnoeffectincountup.
Thetriggeredgeforthenextcount-ingisignoredifdetectingitbeforedetectingamatchbetweentheup-counterandtheTC1DRA.
SincetheTC1pininputhasthenoiserejection,pulsesof4/fc[s]orlessarerejectedasnoise.
Apulsewidthof12/fc[s]ormoreisrequiredtoensureedgedetection.
Example1:Generatinganinterrupt1msaftertherisingedgeoftheinputpulsetotheTC1pin(fc=20MHz,CGCR="1")LDW(TC1DRA),007DH;1ms÷27/fc=7DHDI;IMF="0"SET(EIRD).
2;EnablesINTTC1interruptEI;IMF="1"LD(TC1CR),00001000B;SelectsthesourceclockandmodeLD(TC1CR),00111000B;StartsTC1externaltrigger,METT1=0Example2:Generatinganinterruptwhenthelow-levelpulsewith4msormorewidthisinputtotheTC1pin(fc=20MHz,CGCR="1")LDW(TC1DRA),0138H;4ms÷28/fc=0138HDI;IMF="0"SET(EIRD).
2;EnablesINTTC1interruptEI;IMF="1"LD(TC1CR),00000100B;SelectsthesourceclockandmodeLD(TC1CR),01110100B;StartsTC1externaltrigger,METT1=0Page71TMP88CS42NGFigure8-3ExternalTriggerTimerModeTimingChartINTTC1interruptrequestSourceclockUp-counterTC1DRATC1pininputINTTC1interruptrequestSourceclockUp-counterTC1DRATC1pininput0Attherisingedge(TC1S=10)Attherisingedge(TC1S=10)(a)Triggerstart(METT1=0)CountstartMatchdetectCountstart0123423n(b)Triggerstartandstop(METT1=1)CountstartCountstart0123m0nn0CountclearNote:m.
Whenamatchbetweentheup-counterandtheTC1DRAvalueisdetected,anINTTC1interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingateachedgeoftheinputpulsetotheTC1pin.
Sinceamatchbetweentheup-counterandthevaluesettoTC1DRAisdetectedattheedgeoppositetotheselectededge,anINTTC1interruptrequestisgeneratedafteramatchofthevalueattheedgeoppositetotheselectededge.
Twoormoremachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC1pin.
SettingTC1CRto"1"capturestheup-countervalueintoTC1DRBwiththeautocapturefunction.
Usetheauto-capturefunctionintheoperativeconditionofTC1.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondi-tion.
Sincetheup-countervalueiscapturedintoTC1DRBbythesourceclockofup-counteraftersettingTC1CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC1DRBforthefirsttime.
Figure8-4EventCounterModeTimingChartTable8-2InputPulthWidthtoTC1PinMinimumPulseWidth[s]NORMAL,IDLEModeHigh-going23/fcLow-going23/fcAttherisingedge(TC1S=10)INTTC1interrputrequestTC1pinInputUp-counterTC1DRA210nTimerstart210nMatchdetectCounterclearn1Page73TMP88CS42NG8.
3.
4WindowModeInthewindowmode,theup-countercountsupattherisingedgeofthepulsethatislogicalANDedproductoftheinputpulsetotheTC1pin(windowpulse)andtheinternalsourceclock.
Eitherthepositivelogic(countupduringhigh-goingpulse)ornegativelogic(countupduringlow-goingpulse)canbeselected.
Whenamatchbetweentheup-counterandtheTC1DRAvalueisdetected,anINTTC1interruptisgeneratedandtheup-counteriscleared.
Definethewindowpulsetothefrequencywhichissufficientlylowerthantheinternalsourceclockpro-grammedwithTC1CR.
Figure8-5WindowModeTimingChartMatchdetectTC1DRAINTTC1interrputrequestinterrputrequestInternalclockCounterTC1DRATC1pininputInternalclockCounterTC1pininputINTTC1(a)Positivelogic(TC1S=10)(b)Negativelogic(TC1S=11)Matchdetect107475463121075362023CounterclearTimerstart89019TimerstartCounterclearCountstartCountstopCountstartCountstartCountstopCountstartPage748.
16-BitTimerCounter1(TC1)8.
3FunctionTMP88CS42NG8.
3.
5PulseWidthMeasurementModeInthepulsewidthmeasurementmode,theup-counterstartscountingbytheinputpulsetriggeringoftheTC1pin,andcountsupattheedgeoftheinternalclock.
EithertherisingorfallingedgeoftheinternalclockisselectedasthetriggeredgeinTC1CR.
Eitherthesingle-ordouble-edgecaptureisselectedasthetrig-geredgeinTC1CR.
WhenTC1CRissetto"1"(single-edgecapture)Eitherhigh-orlow-levelinputpulsewidthcanbemeasured.
Tomeasurethehigh-levelinputpulsewidth,settherisingedgetoTC1CR.
Tomeasurethelow-levelinputpulsewidth,setthefallingedgetoTC1CR.
Whendetectingtheedgeoppositetothetriggeredgeusedtostartcountingafterthetimerstarts,theup-countercapturestheup-countervalueintoTC1DRBandgeneratesanINTTC1interruptrequest.
Theup-counterisclearedatthistime,andthenrestartscountingwhendetectingthetriggeredgeusedtostartcounting.
WhenTC1CRissetto"0"(double-edgecapture)Thecyclestartingwitheitherthehigh-orlow-goinginputpulsecanbemeasured.
Tomeasurethecyclestartingwiththehigh-goingpulse,settherisingedgetoTC1CR.
Tomeasurethecyclestartingwiththelow-goingpulse,setthefallingedgetoTC1CR.
Whendetectingtheedgeoppositetothetriggeredgeusedtostartcountingafterthetimerstarts,theup-countercapturestheup-countervalueintoTC1DRBandgeneratesanINTTC1interruptrequest.
Theup-countercontinuescountingup,andcapturestheup-countervalueintoTC1DRBandgeneratesanINTTC1interruptrequestwhendetectingthetriggeredgeusedtostartcounting.
Theup-counterisclearedatthistime,andthencontinuescounting.
Note1:ThecapturedvaluemustbereadfromTC1DRBuntilthenexttriggeredgeisdetected.
Ifnotread,thecap-turedvaluebecomesadon'tcare.
Itisrecommendedtousea16-bitaccessinstructiontoreadthecapturedvaluefromTC1DRB.
Note2:Forthesingle-edgecapture,thecounteraftercapturingthevaluestopsat"1"untildetectingthenextedge.
Therefore,thesecondcapturedvalueis"1"largerthanthecapturedvalueimmediatelyaftercountingstarts.
Note3:Thefirstcapturedvalueafterthetimerstartsmaybereadincorrectively,therefore,ignorethefirstcapturedvalue.
Page75TMP88CS42NGExample:Dutymeasurement(resolutionfc/27[Hz],CGCR="0")CLR(INTTC1SW).
0;INTTC1serviceswitchinitialsettingAddresssettoconvertINTTC1SWateachINTTC1LD(TC1CR),00000110B;SetstheTC1modeandsourceclockDI;IMF="0"SET(EIRD).
2;EnablesINTTC1EI;IMF="1"LD(TC1CR),00100110B;StartsTC1withanexternaltriggeratMCAP1=0:PINTTC1:CPL(INTTC1SW).
0;INTTC1interrupt,invertsandtestsINTTC1serviceswitchJRSF,SINTTC1LDA,(TC1DRBL);ReadsTC1DRB(High-levelpulsewidth)LDW,(TC1DRBH)LD(HPULSE),WA;Storeshigh-levelpulsewidthinRAMRETISINTTC1:LDA,(TC1DRBL);ReadsTC1DRB(Cycle)LDW,(TC1DRBH)LD(WIDTH),WA;StorescycleinRAM:RETI;Dutycalculation:VINTTC1:DWPINTTC1;INTTC1InterruptvectorWIDTHHPULSETC1pinINTTC1interruptrequestINTTC1SWPage768.
16-BitTimerCounter1(TC1)8.
3FunctionTMP88CS42NGFigure8-6PulseWidthMeasurementModeTC1DRBINTTC1interruptrequestinterruptrequestTC1pininputCounterInternalclock(MCAP1="1")23nCountstartCountstartTrigger(TC1S="10")132140n0Capturen-1TC1DRBINTTC1TC1pininputCounterInternalclock(MCAP1="0")12nCountstartCountstart(TC1S="10")32140nCaptureCapturen+1m-2n+3n+2n+1m-1m0m[Application]High-orlow-levelpulsewidthmeasurement[Application](1)Cycle/frequencymeasurement(2)Dutymeasurement(a)Single-edgecapture(b)Double-edgecapturePage77TMP88CS42NG8.
3.
6ProgrammablePulseGenerate(PPG)OutputModeIntheprogrammablepulsegeneration(PPG)mode,anarbitrarydutypulseisgeneratedbycountingper-formedintheinternalclock.
Tostartthetimer,TC1CRspecifieseithertheedgeoftheinputpulsetotheTC1pinorthecommandstart.
TC1CRspecifieswhetheradutypulseisproducedcontinuouslyornot(one-shotpulse).
WhenTC1CRissetto"0"(Continuouspulsegeneration)Whenamatchbetweentheup-counterandtheTC1DRBvalueisdetectedafterthetimerstarts,thelevelofthePPGpinisinvertedandanINTTC1interruptrequestisgenerated.
Theup-countercontin-uescounting.
Whenamatchbetweentheup-counterandtheTC1DRAvalueisdetected,thelevelofthePPGpinisinvertedandanINTTC1interruptrequestisgenerated.
Theup-counterisclearedatthistime,andthencontinuescountingandpulsegeneration.
WhenTC1CRisclearedto"00"duringPPGoutput,thePPGpinretainsthelevelimmedi-atelybeforethecounterstops.
WhenTC1CRissetto"1"(One-shotpulsegeneration)Whenamatchbetweentheup-counterandtheTC1DRBvalueisdetectedafterthetimerstarts,thelevelofthePPGpinisinvertedandanINTTC1interruptrequestisgenerated.
Theup-countercontin-uescounting.
Whenamatchbetweentheup-counterandtheTC1DRAvalueisdetected,thelevelofthePPGpinisinvertedandanINTTC1interruptrequestisgenerated.
TC1CRisclearedto"00"automaticallyatthistime,andthetimerstops.
ThepulsegeneratedbyPPGretainsthesamelevelasthatwhenthetimerstops.
SincetheoutputlevelofthePPGpincanbesetwithTC1CRwhenthetimerstarts,apositiveorneg-ativepulsecanbegenerated.
SincetheinvertedlevelofthetimerF/F1outputlevelisoutputtothePPGpin,specifyTC1CRto"0"tosetthehighleveltothePPGpin,and"1"tosetthelowleveltothePPGpin.
Uponreset,thetimerF/F1isinitializedto"0".
Note1:TochangeTC1DRAorTC1DRBduringarunofthetimer,setavaluesufficientlylargerthanthecountvalueofthecounter.
Settingavaluesmallerthanthecountvalueofthecounterduringarunofthetimermaygenerateapulsedifferentfromthatspecified.
Note2:DonotchangeTC1CRduringarunofthetimer.
TC1CRcanbesetcorrectlyonlyatinitial-ization(afterreset).
WhenthetimerstopsduringPPG,TC1CRcannotbesetcorrectlyfromthispointonwardifthePPGoutputhasthelevelwhichisinvertedofthelevelwhenthetimerstarts.
(SettingTC1CRspecifiesthetimerF/F1tothelevelinvertedoftheprogrammedvalue.
)Therefore,thetimerF/F1needstobeinitializedtoensureanarbitrarylevelofthePPGoutput.
ToinitializethetimerF/F1,changeTC1CRtothetimermode(itisnotrequiredtostartthetimermode),andthensetthePPGmode.
SetTC1CRatthistime.
Note3:InthePPGmode,thefollowingrelationshipmustbesatisfied.
TC1DRA>TC1DRBNote4:SetTC1DRBafterchangingthemodeofTC1MtothePPGmode.
Page788.
16-BitTimerCounter1(TC1)8.
3FunctionTMP88CS42NGFigure8-7PPGOutputExample:Generatingapulsewhichishigh-goingfor800sandlow-goingfor200μs(fc=20MHz,CGCR="0")SettingportLD(TC1CR),10001011B;SetsthePPGmode,selectsthesourceclockLDW(TC1DRA),04E2H;Setsthecycle(1ms÷24/fcμs=04E2H)LDW(TC1DRB),00FAH;Setsthelow-levelpulsewidth(200μs÷24/fc=00FAH)LD(TC1CR),10010111B;StartsthetimerQRDPPGpinFunctionoutputPortoutputenableI/OportoutputlatchsharedwithPPGoutputDataoutputToggleSetClearQTC1CRWritetoTC1CRInternalresetMatchtoTC1DRBMatchtoTC1DRATC1CRclearTimerF/F1INTTC1interruptrequestPage79TMP88CS42NGFigure8-8PPGModeTimingChartINTTC1TC1DRAInternalclockCounterTC1DRBTC1DRAPPGpinoutput0INTTC1interruptrequestinterruptrequest12m012nm01n2nn+1n+1m(a)Continuouspulsegeneration(TC1S=01)TC1DRBTriggerCountstartTimerstartCounterInternalclockTC1pininputPPGpinoutput01mnnn+1m0(b)One-shotpulsegeneration(TC1S=10)MatchdetectNote:m>nNote:m>n[Application]One-shotpulseoutputPage808.
16-BitTimerCounter1(TC1)8.
3FunctionTMP88CS42NGPage81TMP88CS42NG9.
16-BitTimer(CTC)9.
1ConfigurationFigure9-1CTCBlockDiagramCTC1CR2CTC1CR1322233ToggleQSetClearCTC1SCTC1SMCTC1SECTC1CYCTC1ERisingedgeFallingedgeSAYBCTCpinHABCDYESfc/211orfc/212fc/27orfc/28fc/25orfc/26fc/23orfc/24fc/22orfc/23fc/2orfc/22CTC1CKCTC1SCTC1RESEXTRGDISCTC1REGCTC1CKCTC1FF0PPGFF0CTC1MCTC1CYCTC1SECTC1ECTC1SMCTC1MCTC1FF0PPGFF0CTC1MCTC1REGLastcoincidenceInterruptStopTriggerclearStartStartcontrolRead/WritecontrolandclearinterruptSelectwriteregisterSelectreadregisterCTC1DRACTC1DRBCTC1DRC16-bitupcounterINTCTC1interruptPPG2pinEdgedetectionComparatorEXTRGDISPage829.
16-BitTimer(CTC)9.
1ConfigurationTMP88CS42NG9.
2ControlComparetimer/counter1iscontrolledusingComparetimer/counter1ControlRegisters(CTC1CR1andCTC1CR2),aswellasthree16-bitTimerRegisters(CTC1DRA,CTC1DRB,andCTC1DRC).
Note:CTC1DRA,CTC1DRB,andCTC1DRCarewrite-onlyregistersandmustnotbeusedwithanyoftheread-modify-writeinstructionssuchasSET,CLR,etc.
Note1:*:Don'tcareNote2:TheCTC1CR1is0whenread.
Note3:UsetheLDWinstructionforwritetotheCTC1DRH/LRegisters.
Setavalueequaltoorgreaterthan2.
Note4:WritetoCTC1DRH/LA,B,andCRegistersasmanyassetwiththeCTC1CR2RegisterCTC1REGbit.
Note5:DataarewrittentoCTC1DRH/LRegistersinorderofCTC1DRA,CTC1DRB,andCTC1DRC.
CompareTimerRegisters(CTC1DRH:00017h,CTC1DRL:00016h)CTC1DRA1514131211109876543210Writeonly(Initialvalue:CTC1DRAHCTC1DRALCTC1DRB1514131211109876543210Writeonly(Initialvalue:CTC1DRBHCTC1DRBLCTC1DRC1514131211109876543210Writeonly(Initialvalue:CTC1DRCHCTC1DRCLCompareTimer/Counter1ControlRegisters(CTC1CR2:00015h,CTC1CR1:00014h)CTC1CR1loweraddress76543210R/W(Initialvalue:00000000)CTC1RESPPGFF0CTC1MCTC1CYCTC1SECTC1ECTC1SMCTC1SCTC1CR2upperaddress76543210R/W(Initialvalue:*0000000)*EXTRG-DISCTC1REGCTC1CKCTC1FF0Page83TMP88CS42NGNote1:fc:Clock[Hz]Note2:Makesurethetimer/counterisidle(CTC1CR1=00)beforesettingoperationmode,edge,start,sourceclock,externaltriggertimermodecontrol,andPPGoutputcontrol.
Note3:WhenDV1CK=1,CTC1CR2=100cannotbeused.
Note4:WhenCTC1inputisnotusedintheCTC1timer,externaltriggerinputmustbedisabled(CTC1CR2=1)regardlessoftheselectedmode.
Note5:TheCTC1DRBandCTC1DRCRegisterscannotbeaccessedforwriteunlesstheyaresetforPPGoutputmodeandspecifiedwithCTC1CR2.
Note6:CTC1CR1iseffectiveonlywhenusinganexternalclockastrigger(CTC1CR1).
Note7:DatamustbewrittentoasmanydataregistersassetwithCTC1CR2.
Note8:TowritedatatoCTC1DRA/B/C,usetheLDWinstruction,orusetheLDinstructionwritinginorderofL,H.
Note9:Dataregistervaluesmustbewrittentotherespectiveregistersbeforestarting.
Tomodifythevaluesafterstarting,writethenewdatawithinanintervalfromanINTCTC1interrupttothenextINTCTC1.
Setting-uptheCTC1CR1RegisterCTC1SControlstart0:Stopandclearcounter1:CommandstartTimerEventPPGR/WοοοοοοCTC1SMSelectstart0:Softwarestart1:Externaltriggerstartοοοο*οCTC1ESelectexternaltriggeredge0:Enableoneedge1:Enablebothedgesοοοο*οCTC1SESelectexternaltriggerstartedge0:Risingedge1:FallingedgeοοοοοοCTC1CYSelectcycle0:Successive1:Oneshotοοοο*οCTC1MSetoperationmode0:Timer/Eventcountermodes1:PPG(programmablepulsegenerator)outputmodePPGFF0SelectPPGoutput0:Forwardoutputimmediatelyafterstart1:ReverseoutputimmediatelyafterstartCTC1RESResetall0:Normaloperation1:CTC1resetSetting-uptheCTC1CR2RegisterCTC1FF0ControltimeroutputF/F00:Clear1:SetR/WCTC1CKSelecttimer/counterclocksourceUnit:HzNORMALandIDLEModesDV1CK=0DV1CK=1TimerEventPPG000fc/211fc/212ο-*001fc/27fc/28ο-*010fc/25fc/26ο-*011fc/23fc/24ο-*100fc/22fc/23ο-οNote3101fc/2fc/22ο-ο110111Externalclockinput(CTC1pininput)-*CTC1REGSetregistersusedbytimer/counter00:CTC1DRA01:CTC1DRA+CTC1DRB10:CTC1DRA+CTC1DRB+CTC1DRC11:Reserved1REG2REG3REGEXTRGDISExternaltriggerinputNote40:Enableexternaltriggerinput1:DisableexternaltriggerinputPage849.
16-BitTimer(CTC)9.
1ConfigurationTMP88CS42NGNote10:SpecifyingCTC1CR1=1causesallconditionstobereset.
EvenwhentheCTCcircuitisoperating,theyarereset,andthePPGoutputbecomes"0".
However,onlytheINTCTC1signalisnotresetifthesignalisbeinggener-ated.
Note11:Foreventcountermode(whenCTCpininputisselectedintimermode),theactiveedgeoftheexternaltriggertocountcanbeselectedwithCTC1CR1.
Note12:DisablingexternaltriggerinputwithCTC1CR2createsthe0inputstate.
Note13:Tostopthecounterbysoftwareattriggerstart,setCTC1CR2=00.
Note14:Thenumberofregisterssetandthevaluessetinthetimerregistersmustmeettheconditionsshownbelow.
NumberofRegistersTimerRegisterValueConditionsCTC1REG1RegisterCTC1DRA≥22RegisterCTC1DRB>CTC1DRA+1,andCTC1DRA≥23RegisterCTC1DRC>CTC1DRB+1,CTC1DRB>CTC1DRA+1,andCTC1DRA≥2Page85TMP88CS42NG9.
3FunctionComparetimer/counter1hasthreemodes:timer,eventcounter,andprogrammablepulsegeneratoroutputmodes.
9.
3.
1TimermodewithsoftwarestartInthismode,thetimer/counter(16-bitcounter)countsupsynchronouslywiththeinternalclock.
WhenthecountervalueandthesetvalueofCompareTimerRegister1A(CTC1DRA)match,anINTCTC1interruptisgeneratedandthecounteriscleared.
Afterthecounteriscleared,itrestartsandcontinuescountingup.
Figure9-2TimerModeTimingChartNote:IftheCTCinputport(P47)issetforinputmode,thetimer/counterisresetbyaninputedgeonport.
Whenusingthetimer/counterasanordinarytimer,setCTC1CR2to1orsetP47foroutputmode.
Table9-1InternalClockSourceforCompareTimer/Counter1(Example:fc=20MHz)CTC1CKNORMALandIDLEModesDV1CK=0DV1CK=1Resolution[μs]MaximumSettingTime[s]Resolution[μs]MaximumSettingTime[s]000102.
46.
71204.
813.
420016.
40.
41912.
80.
8390101.
60.
1053.
20.
2100110.
426.
21m0.
852.
43m1000.
213.
11m0.
426.
21m1010.
16.
55m0.
213.
11m110----1230nn-1254839671nTimerRegisterAInternalclockCounterINTCTC1interruptSuccessivePage869.
16-BitTimer(CTC)9.
1ConfigurationTMP88CS42NG9.
3.
2TimermodewithexternaltriggerstartInthistimermode,thetimer/counterstartscountingastriggeredbyinputonCTCpin(risingorfallingedgeselectedwithCTC1CR1).
Thesourceclockisaninternalclock.
Forsuccessivecycles,whenthecountervalueandthesetvalueoftheCTC1DRARegistermatch,anINTCTC1interruptisgeneratedandthecounterisclearedandthenrestarted.
ThecounterisstoppedbyatriggerinputonCTCpinandrestartedbythenexttriggerinput.
Foraone-shotcycle,whenthecountervalueandthesetvalueoftheCTC1DRARegistermatch,anINTCTC1interruptisgeneratedandthecounterisclearedandstopped.
Thecounterrestartscount-ingupbyinputonCTCpin.
WhenCTC1CR1=1,thecounterisclearedandstopscountingatanedgeonCTCpininputoppositetheactiveedgethattriggersthecountertostartcounting.
Inthismode,aninterruptcanbegeneratedbyenteringapulsewhichhasacertainwidth.
WhenCTC1CR1=0,oppositeedgesonCTCinputareignored.
Figure9-3ExternalTriggerModeTimingChart12n-102211n34CTCpininputInternalclockCounter(I)Whenrisingedgestartisselected,withcountingenabledononeedge(CTC1SE=0,CTC1E=0)TimerRegisterACountstartCountstartStopINTCTC1interruptnSuccessiveClearTriggerTriggerTrigger12n-103605n412CTCpininputInternalclockCounterTimerRegisterACountstartCountstartINTCTC1interruptnOneShotStopTriggerTriggera)Successiveb)OneShotPage87TMP88CS42NGFigure9-4ExternalTriggerModeTimingChart9.
3.
3EventcountermodeInthismode,thetimer/countercountsupattheactiveedgeonCTCpininput(risingorfallingedgeselectedwiththeCTC1CR1whichisprovidedforselectingexternaltriggeredge).
WhenthecountervalueandthesetvalueoftheCTC1DRARegistermatch,anINTCTC1interruptisgeneratedandthecounteriscleared.
Afterthecounteriscleared,itrestartsandcontinuescountingupateachedgeonCTCpininput.
Themaximumappliedfrequencyisshowninthetablebelow.
Becausecoincidencedetectionismadeatanedgeoppositetheselectededge,theexternalclocksignalonCTCpinmustalwaysbeentered.
Figure9-5EventCounterModeTimingChart12001n-1m132nCTCpininputInternalclockCounter(II)Whenrisingstartedgeisselected,withcountingenabledonbothedges(CTC1SE=0,CTC1E=1)TimerRegisterACountstartCountstopCountstartINTCTC1interruptnSuccessiveTriggerTriggerTrigger120302n5013412CTCpininputInternalclockCounterTimerRegisterACountstartCountclearCountstartINTCTC1interruptnOneShotTriggerTriggerTriggerNote)mandCTC1CR1).
Thesourceclockisaninternalclock.
WhenmatchedwiththeCTC1DRA/B/CRegisters,thetimeroutputF/Fcorrespondingtoeachmodeisinverted.
WhenmatchedwiththeCTC1DRA/B/CRegistersnexttime,thetimeroutputF/Fisinvertedagain.
AnINTCTC1interruptrequestisgeneratedwhenthecountervaluematchesthemaximumregistervaluesetbyCTC1CR2.
ThetimeroutputF/Fisclearedto0whenreset.
BecauseCTC1CR2canbeusedtosettheinitialvalueforthetimeroutputF/F,anactive-highoractive-lowpulsewhicheverisdesiredcanbeoutput.
TheCTC1DRBandCTC1DRCRegisterscannotbeaccessedforwriteunlesstheyaresetforPPGoutputmodeandtheregistersusedareselectedwithCTC1CR2.
Thenumberofregisterssetcanbealteredduringoperation.
Inthiscase,however,besuretosetthenumberofregistersusedandwritevaluestothedataregistersbeforethenextCTC1INIT1isoutputafterthefirstCTC1INIT1output.
Evenwhenonlyalteringthedataregistervalueswhileleavingthenumberofregistersunchanged,besuretodothiswithinthesameperiodoftime.
Note:WhenPortP47issetasaCTCinputport,anedgeinputresetsthetimer/counter.
whenPPGoutputmodeisselectedandexternaltriggerstartisnotused,setCTC1CR2to"1"orsetP47asanoutputport.
Table9-2ExternalClockSourceforCompareTimer/Counter1NORMALandIDLEModesMaximumappliedfrequency[Hz]Uptofc/22Minimumpulsewidth22/fcandoverTable9-3InternalClockSourceforCompareTimer/Counter1(Example:fc=20MHz)CTC1CKNORMALandIDLEModesDV1CK=0DV1CK=1Resolution[μs]MaximumSettingTime[s]Resolution[μs]MaximumSettingTime[s]0000010100111000.
213.
11m1010.
16.
55m0.
213.
11m110Page89TMP88CS42NGFigure9-6OneRegisterCommandStartModeTimingChart(I)Oneregisterused(CTC1REG=00)Whensettocommandstart.
CTCpininputCounterTimerRegisterA111nn0INTCTC1interruptCommandstartnPPG2pinoutput1n123nSuccessivePage909.
16-BitTimer(CTC)9.
1ConfigurationTMP88CS42NGFigure9-7TwoRegisterOneEdgeTriggerStartModeTimingChart(II)Tworegistersused(CTC1REG=01)Whensettotheexternaltriggerrisingedgestartandtheoneedgeenable.
CTCpininputCounterInternalclockTimerRegisterATimerRegisterB1mm+1mm+11n0INTCTC1interruptStartStopmnPPG2pinoutput120nSuccessiveInitialvalueCTCpininputCounterInternalclockTimerRegisterATimerRegisterB1mm+10n0INTCTC1interruptStartStartmnPPG2pinoutput1Oneshota)Successiveb)OneshotPage91TMP88CS42NGFigure9-8TwoRegsterBothedgesTriggerStartModeTimingChartWhensettotheexternaltriggerrisingedgestartandthebothedgesenable.
CTCpininputCounterInternalclockTimerRegisterATimerRegisterB1mm+1m1n0INTCTC1interruptStartStartStopmnPPG2pinoutput10SuccessiveInitialvalueCTCpininputCounterInternalclockTimerRegisterATimerRegisterB1mm+1mnm+1011n2000INTCTC1interruptStartmnPPG2pinoutputm1m+10OneshotStartStartStarta)Successiveb)OneshotPage929.
16-BitTimer(CTC)9.
1ConfigurationTMP88CS42NGNote:Inthesingle-shotmode,thePPGpinoutputisnottoggledatthelastregistermatch;itstaysatthevaluespecifiedwithCTC1CR2.
Figure9-9ThreeRegisterCommandStartModeTimingChart(III)Threeregistersused(CTC1REG=10)Whensettocommandstart.
CTCpininputCounterTimerRegisterATimerRegisterB1mm+1sn+1n0INTCTC1interruptCommandstartmnTimerRegisterCsPPG2pinoutputm+1mn1SuccessiveCTCpininputCounterTimerRegisterATimerRegisterB11mmm+1sn+1n0INTCTC1interruptCommandstartCommandrestartmnTimerRegisterCsPPG2pinoutputm+10Oneshota)Successiveb)OneshotPage93TMP88CS42NGDetailoperationatstartthatvariesdependingonhowCTC1CR2andCTC1CR1aresetduringPPGoutput.
Bychangingtheport-sharedoutputforPPGoutputbeforethecounterstartscountingaftersettingCTC1CR2,itispossibletodeterminetheinitialvalueofPPGoutput.
Table9-4VaryingPPGOutputTimingDependingonSettingsCTC1FF0=0PPGFF0=0CTC1FF0=1PPGFF0=0CTC1FF0=0PPGFF0=1CTC1FF0=1PPGFF0=1102nn+1n+3n+23InternalclockCounterPPGoutputCTC1FF0setting(writetoCTC1CR1Register)Commandstartortriggerstart102nn+1n+3n+23InternalclockCounterPPGoutputCTC1FF0setting(writetoCTC1CR1Register)Commandstartortriggerstart102nn+1n+3n+23InternalclockCounterPPGoutputCTC1FF0setting(writetoCTC1CR1Register)Commandstartortriggerstart102nn+1n+3n+23InternalclockCounterPPGoutputCTC1FF0setting(writetoCTC1CR1Register)CommandstartortriggerstartPage949.
16-BitTimer(CTC)9.
1ConfigurationTMP88CS42NGPage95TMP88CS42NG10.
8-BitTimerCounter3(TC3)10.
1ConfigurationNote:FunctioninputmaynotoperatedependingonI/Oportsetting.
Formoredetails,seethechapter"I/OPort".
Figure10-1TimerCounter3(TC3)TC3CKTC3Sfc/213,fc/214fc/212,fc/213fc/211,fc/212fc/210,fc/211fc/29,fc/2,fc/29,fc/283SourceclockCaptureClearTC3SINTTC3interruptTC3contorolregister8-bittimerregisterOverflowdetectHABCDEFGSTC3MTC3CREdgedetectorTC3DRBTC3DRACaptureACAPTC3SFallingRisingAYBSMatchdetectY8-bitup-counterTC3pinPort(Note)CMPfc/28fc/2710Page9610.
8-BitTimerCounter3(TC3)10.
1ConfigurationTMP88CS42NG10.
2TimerCounterControlTheTimerCounter3iscontrolledbytheTimerCounter3controlregister(TC3CR)andtwo8-bittimerregisters(TC3DRAandTC3DRB).
Note1:fc:High-frequencyclock[Hz],*:Don'tcareNote2:SettheoperatingmodeandsourceclockwhenTimerCounterstops(TC3CR=0).
Note3:Tosetthetimerregisters,thefollowingrelationshipmustbesatisfied.
TC3DRA>1(Timer/eventcountermode)Note4:Auto-capture(TC3CR)canbeusedonlyinthetimerandeventcountermodes.
Note5:WhenthereadinstructionisexecutedtoTC3CR,thebit5and7arereadasadon'tcare.
Note6:DonotprogramTC3DRAwhenthetimerisrunning(TC3CR=1).
Note7:WhentheSTOPmodeisentered,thestartcontrol(TC3CR)isclearedto0automatically,andthetimerstops.
AftertheSTOPmodeisexited,TC3CRmustbesetagaintousethetimercounter.
TimerRegisterandControlRegisterTC3DRA(001CH)76543210Read/Write(Initialvalue:11111111)TC3DRB(001DH)Readonly(Initialvalue:11111111)TC3CR(001EH)76543210ACAPTC3STC3CKTC3M(Initialvalue:*0*00000)ACAPAutocapturecontrol0:–1:AutocaptureR/WTC3STC3startcontrol0:Stopandcounterclear1:StartR/WTC3CKTC3sourceclockselect[Hz]NORMAL,IDLEmodeR/WDV1CK=0DV1CK=1000fc/213fc/214001fc/212fc/213010fc/211fc/212011fc/210fc/211100fc/29fc/210101fc/28fc/29110fc/27fc/28111Externalclock(TC3pininput)TC3MTC3operatingmodeselect0:Timer/eventcountermode1:CapturemodeR/WPage97TMP88CS42NG10.
3FunctionTimerCounter3hasthreetypesofoperatingmodes:timer,eventcounterandcapturemodes.
10.
3.
1TimermodeInthetimermode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthetimerregister3A(TC3DRA)valueisdetected,anINTTC3interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscounting.
SettingTC3CRto1capturestheup-countervalueintothetimerregister3B(TC3DRB)withtheauto-capturefunction.
ThecountvalueduringtimeroperationcanbecheckedbyexecutingthereadinstructiontoTC3DRB.
Note:00Hwhichisstoredintheup-counterimmediatelyafterdetectionofamatchisnotcapturedintoTC3DRB.
(Figure10-2)Figure10-2Auto-CaptureFunctionTable10-1SourceClockforTimerCounter3(Example:fc=20MHz)TC3CKNORMAL,IDLEmodeDV1CK=0DV1CK=1Resolution[μs]MaximumTimeSetting[ms]Resolution[μs]MaximumTimeSetting[ms]000409.
6104.
45819.
2208.
90001204.
852.
22409.
6104.
45010102.
426.
11204.
852.
2201151.
213.
06102.
426.
1110025.
66.
5351.
213.
0610112.
83.
0625.
66.
531106.
41.
6312.
83.
06TC3DRBNote:InthecasethatTC3DRBisC8HClockUp-counterMatchdetectC7C8TC3DRAC80001C7C8C6C601Page9810.
8-BitTimerCounter3(TC3)10.
1ConfigurationTMP88CS42NGFigure10-3TimerModeTimingChartMatchdetectTC3CRTC3DRBTC3DRAINTTC3interruptSourceclockCounterSourceclockCounter(a)Timermode(b)Autocapture763450nTimerstart1232140nCounterclearCapturen+1nm+2m+1mmCapturem+2m+1n+1nPage99TMP88CS42NG10.
3.
2EventCounterModeIntheeventcountermode,theup-countercountsupattherisingedgeoftheinputpulsetotheTC3pin.
Whenamatchbetweentheup-counterandTC3DRAvalueisdetected,anINTTC3interruptisgeneratedandup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingateachrisingedgeoftheinputpulsetotheTC3pin.
SinceamatchisdetectedatthefallingedgeoftheinputpulsetoTC3pin,anINTTC3interruptrequestisgeneratedatthefallingedgeimmediatelyaftertheup-counterreachesthevaluesetinTC3DRA.
ThemaximumappliedfrequenciesareshowninTable10-2.
Thepulsewidthlargerthanonemachinecycleisrequiredforhigh-goingandlow-goingpulses.
SettingTC3CRto1capturestheup-countervalueintoTC3DRBwiththeauto-capturefunction.
ThecountvalueduringatimeroperationcanbecheckedbythereadinstructiontoTC3DRB.
Note:00Hwhichisstoredintheup-counterimmediatelyafterdetectionofamatchisnotcapturedintoTC3DRB.
(Figure10-2)Figure10-4EventCounterModeTimingChartExample:Inputting50HzpulsetoTC3,andgeneratinginterruptsevery0.
5sLD(TC3CR),00001110B:SetstheclockmodeLD(TC3DRA),19H:0.
5s÷1/50=25=19HLD(TC3CR),00011110B:StartsTC3.
Table10-2MaximumFrequenciesAppliedtoTC3MinimumPulseWidthNORMAL,IDLEmodeHigh-going22/fcLow-going22/fcnINTTC3interruptTC3pininputCounterTC3DRAMatchdetectCounterclearTimerstart0123n0123Page10010.
8-BitTimerCounter3(TC3)10.
1ConfigurationTMP88CS42NG10.
3.
3CaptureModeInthecapturemode,thepulsewidth,frequencyanddutycycleofthepulseinputtotheTC3pinaremea-suredwiththeinternalclock.
Thecapturemodeisusedtodecoderemotecontrolsignals,andidentifyAC50/60Hz.
WhenthefallingedgeoftheTC3inputisdetectedafterthetimerstarts,theup-countervalueiscapturedintoTC3DRB.
Hereafter,whenevertherisingedgeisdetected,theup-countervalueiscapturedintoTC3DRAandtheINTTC3interruptrequestisgenerated.
Theup-counterisclearedatthistime.
Generally,readTC3DRBandTC3DRAduringINTTC3interruptprocessing.
Aftertheup-counteriscleared,countingiscontinuedandthenextup-countervalueiscapturedintoTC3DRB.
Whentherisingedgeisdetectedimmediatelyafterthetimerstarts,theup-countervalueiscapturedintoTC3DRAonly,butnotintoTC3DRB.
TheINTTC3interruptrequestisgenerated.
WhenthereadinstructionisexecutedtoTC3DRBatthistime,thevalueatthecompletionofthelastcapture(FFimmediatelyafterareset)isread.
TheminimuminputpulsewidthmustbelargerthanonecyclewidthofthesourceclockprogrammedinTC3CR.
TheINTTC3interruptrequestisgeneratediftheup-counteroverflow(FFH)occursduringcaptureoperationbeforetheedgeisdetected.
TC3DRAissettoFFHandtheup-counteriscleared.
Countingiscontinuedbytheup-counter,butcaptureoperationandoverflowdetectionarestoppeduntilTC3DRAisread.
Generally,readTC3DRBfirstbecausecaptureoperationandoverflowdetectionresumebyreadingTC3DRA.
Figure10-5CaptureModeTimingChartReadofTC3DRASourceclockCounterTC3DRATC3pininputTC3DRBINTTC3interruptrequestiFE23101k-11CaptureCaptureCaptureCaptureCapturemFF(Overflow)kn0FFTC3CRii+1i-10kmm+1m-1n-10n213InternalwaveformFEOverflowTimerstartPage101TMP88CS42NG11.
8-BitTimerCounter4(TC4)11.
1ConfigurationFigure11-1TimerCounter4(TC4)PWMoutputmodeClear32SourceClock8-bitup-counterOverflowdetectToggleClearTimerF/FMatchdetectSY01YSS10YPDOmodePort(Note)(Note)ABCDEFGHYSCMPNote:FunctionI/OmaynotoperatedependingonI/Oportsetting.
Formoredetails,seethechapter"I/OPort".
TC4CRTC4DRINTTC4interruptTC4STC4STC4STC4MTC4CKTC4pinPWM4/PDO4/pinfc/211,fc212fc/27,fc28fc/25,fc26fc/23,fc24fc/22,fc23fc/2,fc22fc,fc/2Page10211.
8-BitTimerCounter4(TC4)11.
1ConfigurationTMP88CS42NG11.
2TimerCounterControlTheTimerCounter4iscontrolledbytheTimerCounter4controlregister(TC4CR)andtimerregisters4(TC4DR).
Note1:fc:High-frequencyclock[Hz],*:Don'tcareNote2:Tosetthetimerregisters,thefollowingrelationshipmustbesatisfied.
1≤TC4DR≤255Note3:Tostarttimeroperation(TC4CR=0→1)ordisabletimeroperation(TC4CR=1→0),donotchangetheTC4CRsetting.
Duringtimeroperation(TC4CR=1→1),donotchangeit,either.
Ifthesettingisprogrammedduringtimeroperation,countingisnotperformedcorrectly.
Note4:TheeventcounterandPWMoutputmodesareusedonlyintheNOMALandIDLEmodes.
Note5:WhentheSTOPmodeisentered,thestartcontrol(TC4S)isclearedto"0"automatically.
Note6:Thebit6and7ofTC4CRarereadasadon'tcarewhenthesebitsareread.
Note7:Inthetimer,eventcounterandPDOmodes,donotchangetheTC4DRsettingwhenthetimerisrunning.
Note8:Whenthehigh-frequencyclockfcexceeds10MHz,donotselectthesourceclockofTC4CR=110.
Note9:Foravailablesourceclocksdependingontheoperationmode,refertothefollowingtable.
Note:O:AvailablesourceclockTimerRegisterandControlRegisterTC4DR(001BH)76543210Read/Write(Initialvalue:11111111)TC4CR(001AH)76543210TC4STC4CKTC4MRead/Write(Initialvalue:**000000)TC4STC4startcontrol0:Stopandcounterclear1:StartR/WTC4CKTC4sourceclockselect[Hz]NORMAL,IDLEmodeR/WDV1CK=0DV1CK=1000fc/211fc/212001fc/27fc/28010fc/25fc/26011fc/23fc/24100fc/22fc/23101fc/2fc/22110(fc)Note8(fc/2)Note8111Externalclock(TC4pininput)TC4MTC4operatingmodeselect00:Timer/eventcountermode01:Reserved10:Programmabledivideroutput(PDO)mode11:Pulsewidthmodulation(PWM)outputmodeR/WTC4CKTimerModeEventCounterModePDOModePWMMode000OO001OO010OO011OO100O101O110O111O*Page103TMP88CS42NG11.
3FunctionTimerCounter4hasfourtypesofoperatingmodes:timer,eventcounter,programmabledivideroutput(PDO),andpulsewidthmodulation(PWM)outputmodes.
11.
3.
1TimerModeInthetimermode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandtheTC4DRvalueisdetected,anINTTC4interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscounting.
11.
3.
2EventCounterModeIntheeventcountermode,theup-countercountsupattherisingedgeoftheinputpulsetotheTC4pin.
Whenamatchbetweentheup-counterandtheTC4DRvalueisdetected,anINTTC4interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatrisingedgeoftheTC4pin.
SinceamatchisdetectedatthefallingedgeoftheinputpulsetotheTC4pin,theINTTC4interruptrequestisgeneratedatthefallingedgeimmediatelyaftertheup-counterreachesthevaluesetinTC4DR.
TheminimumpulsewidthappliedtotheTC4pinareshowninTable11-2.
Thepulsewidthlargerthantwomachinecyclesisrequiredforhigh-andlow-goingpulses.
Note:TheeventcountermodecanusedintheNORMALandIDLEmodesonly.
11.
3.
3ProgrammableDividerOutput(PDO)ModeTheprogrammabledivideroutput(PDO)modeisusedtogeneratedapulsewitha50%dutycyclebycount-ingwiththeinternalclock.
Whenamatchbetweentheup-counterandtheTC4DRvalueisdetected,thelogicleveloutputfromthePDO4pinisswitchedtotheoppositestateandINTTC4interruptrequestisgenerated.
Theup-counterisclearedatthistimeandthencountingiscontinued.
Whenamatchbetweentheup-counterandtheTC4DRvalueisdetected,thelogicleveloutputfromthePDO4pinisswitchedtotheoppositestateagainandINTTC4interruptrequestisgenerated.
Theup-counterisclearedatthistime,andthencountingandPDOarecontinued.
Whenthetimerisstopped,thePDO4pinishigh.
Therefore,ifthetimerisstoppedwhenthePDO4pinislow,thedutypulsemaybeshorterthantheprogrammedvalue.
Table11-1InternalSourceClockforTimerCounter4(Example:fc=20MHz)TC4CKNORMAL,IDLEModeDV1CK=0DV1CK=1Resolution[μs]MaximumTimeSetting[ms]Resolution[μs]MaximumTimeSetting[ms]000102.
426.
11204.
852.
220016.
41.
6312.
83.
280101.
60.
413.
20.
820110.
40.
100.
80.
20Table11-2ExternalSourceClockforTimerCounter4MinimumPulseWidthNORMAL,IDLEmodeHigh-going23/fcLow-going23/fcPage10411.
8-BitTimerCounter4(TC4)11.
1ConfigurationTMP88CS42NGFigure11-2PDOModeTimingChart11.
3.
4PulseWidthModulation(PWM)OutputModeThepulsewidthmodulation(PWM)outputmodeisusedtogeneratethePWMpulsewithupto8bitsofres-olutionbyaninternalclock.
Whenamatchbetweentheup-counterandtheTC4DRvalueisdetected,thelogicleveloutputfromthePWM4pinbecomeslow.
Theup-countercontinuescounting.
Whentheup-counteroverflowoccurs,thePWM4pinbecomeshigh.
TheINTTC4interruptrequestisgeneratedatthistime.
Whenthetimerisstopped,thePWM4pinishigh.
Therefore,ifthetimerisstoppedwhenthePWM4pinislow,onePMWcyclemaybeshorterthantheprogrammedvalue.
TC4DRisseriallyconnectedtotheshiftregister.
IfTC4DRisprogrammedduringPWMoutput,thedatasettoTC4DRisnotshifteduntilonePWMcycleiscompleted.
Therefore,apulsecanbemodulatedperiodically.
Forthefirsttime,thedatawrittentoTC4DRisshiftedwhenthetimerisstartedbysettingTC4CRto1.
Note1:ThePWMoutputmodecanbeusedonlyintheNORMALandIDELmodes.
Note2:InthePWMoutputmode,programTC4DRimmediatelyaftertheINTTC4interruptrequestisgenerated(typicallyintheINTTC4interruptserviceroutine.
)WhentheprogrammingofTC4DRandtheINTTC4inter-ruptoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofpulsedifferentfromtheprogrammedvalueuntilthenextINTTC4interruptrequestisissued.
Example:Generating1024Hzpulse(fc=20.
0MhzandCGCR=0)LD(TC4CR),00000110B:SetsthePDOmode.
(TC4M=10,TC4CK=001)SET(P2DR),2:SetstheP22outputlatchto1.
LD(TC4DR),4CH:1/1024÷27/fc÷2(halfcycleperiod)=4CHLD(TC4CR),00100110B:StartTC4InternalclockCounterMatchdetect012n012n012n012n01nTC4DRPDO4pinINTTC4interruptrequestTimerF/FPage105TMP88CS42NGFigure11-3PWMoutputModeTimingChart(TC4)Table11-3PWMMode(Example:fc=20MHz)TC4CKNORMAL,IDLEModeDV1CK=0DV1CK=1Resolution[ns]Cycle[μs]Resolution[ns]Cycle[μs]000––––001––––010––––011400102.
4800204.
810020051.
2400102.
410110025.
620051.
2110––––InternalclockShiftregisterCountern01n+1FF01nn+1FF01mPWMcycleMatchdetectmpnnmDatashiftRewriteDatashiftMatchdetectMatchdetectDatashiftnnmRewriteRewritePWM4pinINTTC4interruptrequestTimerF/FTC4DRTC4CRPage10611.
8-BitTimerCounter4(TC4)11.
1ConfigurationTMP88CS42NGPage107TMP88CS42NG12.
8-BitTimerCounter5,6(TC5,6)12.
1ConfigurationFigure12-18-BitTimerCouter5,68-bitup-counterDecodeENAYBSABYCDEFGHSAYBSSAYBToggleQSetClear8-bitup-counterABYCDEFGHSDecodeENToggleQSetClearPWMmodePDO,PPGmodePDOmodePWM,PPGmodePWMmodePWMmode16-bitmode16-bitmode16-bitmode16-bitmodeTimer,EventCountermodeOverflowOverflowTimer,EventCoutermode16-bitmodeClearClearfc/27,fc/28fc/25,fc/26fc/23,fc/24PDO,PWM,PPGmodePDO,PWMmode16-bitmodefc/27,fc/28fc/25,fc/26fc/23,fc/24fc/211,fc/212fc/211,fc/212TC6CRTC5CRTTREG6PWREG6TTREG5PWREG5TC5pinTC6pinTC6STC5SINTTC5interruptrequestINTTC6interruptrequestTFF6TFF5PDO6/PWM6/PPG6pinPDO5/PWM5/pinTC5CKTC6CKTC5MTC5STFF5TC6MTC6STFF6TimerF/F6TimerF/F5Page10812.
8-BitTimerCounter5,6(TC5,6)12.
1ConfigurationTMP88CS42NG12.
2TimerCounterControlTheTimerCounter5iscontrolledbytheTimerCounter5controlregister(TC5CR)andtwo8-bittimerregisters(TTREG5,PWREG5).
Note1:Donotchangethetimerregister(TTREG5)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG5)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]Note2:DonotchangetheTC5M,TC5CKandTFF5settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC5S=1→0),donotchangetheTC5M,TC5CKandTFF5settings.
Tostartthetimeroper-ation(TC5S=0→1),TC5M,TC5CKandTFF5canbeprogrammed.
Note4:TousetheTimerCounterinthe16-bitmode,settheoperatingmodebyprogrammingTC6CR,whereTC5Mmustbefixedto011.
Note5:TousetheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC5CK.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC6CRandTC6CR,respectively.
Note6:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable12-1.
TimerCounter5TimerRegisterTTREG5(0022H)R/W76543210(Initialvalue:11111111)PWREG5(0024H)R/W76543210(Initialvalue:11111111)TimerCounter5ControlRegisterTC5CR(0020H)76543210TFF5TC5CKTC5STC5M(Initialvalue:00000000)TFF5TimeF/F5control0:1:ClearSetR/WTC5CKOperatingclockselection[Hz]NORMAL,IDLEmodeR/WDV1CK=0DV1CK=1000fc/211fc/212001fc/27fc/28010fc/25fc/26011fc/23fc/24100--101--110--111TC5IpininputTC5STC5startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC5MTC5Moperatingmodeselect000:001:010:011:1**:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmode16-bitmode(EachmodeisselectablewithTC6M.
)ReservedR/WPage109TMP88CS42NGNote7:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable12-2.
Page11012.
8-BitTimerCounter5,6(TC5,6)12.
1ConfigurationTMP88CS42NGTheTimerCounter6iscontrolledbytheTimerCounter6controlregister(TC6CR)andtwo8-bittimerregisters(TTREG6andPWREG6).
Note1:Donotchangethetimerregister(TTREG6)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG6)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]Note2:DonotchangetheTC6M,TC6CKandTFF6settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC6S=1→0),donotchangetheTC6M,TC6CKandTFF6settings.
Tostartthetimeroperation(TC6S=0→1),TC6M,TC6CKandTFF6canbeprogrammed.
Note4:WhenTC6M=1**(upperbyteinthe16-bitmode),thesourceclockbecomestheTC6overflowsignalregardlessoftheTC5CKsetting.
Note5:TousetheTimerCounterinthe16-bitmode,selecttheoperatingmodebyprogrammingTC6M,whereTC5CRmustbesetto011.
Note6:TotheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC5CR.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC6SandTFF6,respectively.
TimerCounter6TimerRegisterTTREG6(0023H)R/W76543210(Initialvalue:11111111)PWREG6(0025H)R/W76543210(Initialvalue:11111111)TimerCounter6ControlRegisterTC6CR(0021H)76543210TFF6TC6CKTC6STC6M(Initialvalue:00000000)TFF6TimerF/F6control0:1:ClearSetR/WTC6CKOperatingclockselection[Hz]NORMAL,IDLEmodeR/WDV1CK=0DV1CK=1000fc/211fc/212001fc/27fc/28010fc/25fc/25011fc/23fc/23100--101--110--111TC6IpininputTC6STC6startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC6MTC6Moperatingmodeselect000:001:010:011:100:101:110:111:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmodeReserved16-bittimer/eventcountermodeWarm-upcountermode16-bitpulsewidthmodulation(PWM)outputmode16-bitPPGmodeR/WPage111TMP88CS42NGNote7:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable12-1.
Note8:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable12-2.
Note1:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC5CK).
Note2:Ο:AvailablesourceclockNote:n=5to6Table12-1OperatingModeandSelectableSourceClock(NORMALandIDLEModes)Operatingmodefc/211fc/27fc/25fc/23TC5pininputTC6pininput8-bittimerΟΟΟΟ––8-biteventcounter––––ΟΟ8-bitPDOΟΟΟΟ––8-bitPWMΟΟΟΟ––16-bittimerΟΟΟΟ––16-biteventcounter––––Ο–16-bitPWMΟΟΟΟΟ–16-bitPPGΟΟΟΟΟ–Table12-2ConstraintsonRegisterValuesBeingComparedOperatingmodeRegisterValue8-bittimer/eventcounter1≤(TTREGn)≤2558-bitPDO1≤(TTREGn)≤2558-bitPWM2≤(PWREGn)≤25416-bittimer/eventcounter1≤(TTREG6,5)≤6553516-bitPWM2≤(PWREG6,5)≤6553416-bitPPG1≤(PWREG6,5)to0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Figure12-28-BitTimerModeTimingChart(TC6)Table12-3SourceClockforTimerCounter5,6(InternalClock)SourceClockResolutionRepeatedCycleNORMAL,IDLEmodeDV1CK=0fc=20MHzDV1CK=0fc=20MHzDV1CK=0DV1CK=1fc/211[Hz]fc/212[Hz]128μs32.
6msfc/27fc/288μs2.
0msfc/25fc/262μs510μsfc/23fc/24500ns127.
5μsExample:Settingthetimermodewithsourceclockfc/27Hzandgeneratinganinterrupt64μslater(TimerCounter6,fc=20.
0MHz)LD(TTREG6),0AH:Setsthetimerregister(80μs÷27/fc=0AH).
DISET(EIRC).
EF37:EnablesINTTC6interrupt.
EILD(TC6CR),00010000B:Setstheoperatingcocktofc/27,and8-bittimermode.
LD(TC6CR),00011000B:StartsTC6.
123n-1n01n-1n20120nInternalSourceClockCounterMatchdetectCounterclearMatchdetectCounterclearTC6CRTTREG6INTTC6interruptrequestPage113TMP88CS42NG12.
3.
28-BitEventCounterMode(TC5,6)Inthe8-biteventcountermode,theup-countercountsupatthefallingedgeoftheinputpulsetotheTCjpin.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,anINTTCjinterruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTCjpin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTCjpin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMALorIDLEmode.
Note1:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Figure12-38-BitEventCounterModeTimingChart(TC6)12.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC5,6)Thismodeisusedtogenerateapulsewitha50%dutycyclefromthePDOjpin.
InthePDOmode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,thelogicleveloutputfromthePDOjpinisswitchedtotheoppositestateandtheup-counteriscleared.
TheINTTCjinterruptrequestisgeneratedatthetime.
ThelogicstateoppositetothetimerF/FjlogiclevelisoutputfromthePDOjpin.
AnarbitraryvaluecanbesettothetimerF/FjbyTCjCR.
Uponreset,thetimerF/Fjvalueisinitializedto0.
Tousetheprogrammabledivideroutput,settheoutputlatchoftheI/Oportto1.
Note1:Intheprogrammabledivideroutputmode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheprogrammabledivideroutputmode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPDOoutput,thePDOjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRsettinguponstoppingofthetimer.
Example:FixingthePDOjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePDOjpintothehighlevel.
Note3:j=5,6Example:Generating1024HzpulseusingTC6(fc=20.
0MHz)SettingportLD(TTREG6),3DH:1/1024÷27/fc÷2=3DHLD(TC6CR),00010001B:Setstheoperatingclocktofc/27,and8-bitPDOmode.
LD(TC6CR),00011001B:StartsTC6.
102n-1n0120nCounterMatchdetectCounterclearn-1n201MatchdetectCounterclearTC6CRTTREG6INTTC6interruptrequestTC6pininputPage11412.
8-BitTimerCounter5,6(TC5,6)12.
1ConfigurationTMP88CS42NGFigure12-48-BitPDOModeTimingChart(TC6)120n0n0n0n01221212310nInternalsourceclockCounterMatchdetectMatchdetectMatchdetectMatchdetectHeldatthelevelwhenthetimerisstoppedSetF/FWriteof"1"TC6CRTC6CRTTREG6TimerF/F6PDO6pinINTTC6interruptrequestPage115TMP88CS42NG12.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC5,6)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto8bitsofresolution.
Theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthePWREGjvalueisdetected,thelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestateagainbytheup-counteroverflow,andthecounteriscleared.
TheINTTCjinterruptrequestisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/FjbyTCjCR,positiveandnegativepulsescanbegen-erated.
Uponreset,thetimerF/Fjisclearedto0.
(ThelogicleveloutputfromthePWMjpinistheoppositetothetimerF/Fjlogiclevel.
)SincePWREGjinthePWMmodeisseriallyconnectedtotheshiftregister,thevaluesettoPWREGjcanbechangedwhilethetimerisrunning.
ThevaluesettoPWREGjduringarunofthetimerisshiftedbytheINTTCjinterruptrequestandloadedintoPWREGj.
Whilethetimerisstopped,thevalueisshiftedimmedi-atelyaftertheprogrammingofPWREGj.
IfexecutingthereadinstructiontoPWREGjduringPWMoutput,thevalueintheshiftregisterisread,butnotthevaluesetinPWREGj.
Therefore,afterwritingtoPWREGj,thereadingdataofPWREGjispreviousvalueuntilINTTCjisgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREGjimmediatelyaftertheINTTCjinterruptrequestisgenerated(normallyintheINTTCjinterruptserviceroutine.
)IftheprogrammingofPWREGjandtheinter-ruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofthepulsedifferentfromtheprogrammedvalueuntilthenextINTTCjinterruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWMjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRuponstoppingofthetimer.
Example:FixingthePWMjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePWMjpintothehighlevel.
Note3:ToentertheSTOPmodeduringPWMoutput,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwithoutstoppingthetimerwhenfcorfc/2isselectedasthesourceclock,apulseisoutputfromthePWMjpinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Note4:j=5,6Table12-4PWMOutputModeSourceClockResolutionRepeatedCycleNORMAL,IDLEmodeDV1CK=0fc=20MHzDV1CK=1fc=20MHzDV1CK=0fc=20MHzDV1CK=1fc=20MHzDV1CK=0DV1CK=1fc/211[Hz]fc/212[Hz]102.
4μs204.
8μs26.
21ms52.
43msfc/27fc/286.
4μs12.
8μs1.
64ms3.
28msfc/25fc/261.
6μs3.
2μs410μs819μsfc/23fc/240.
4μs0.
8μs102μs205μsPage11612.
8-BitTimerCounter5,6(TC5,6)12.
1ConfigurationTMP88CS42NGFigure12-58-BitPWMModeTimingChart(TC6)10nn+1FF0nn+1FF01mm+1FF011pnInternalsourceclockCountermpmpnShiftregistarShiftShiftShiftShiftMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectnmpnTC6CRTC6CRPWREG6TimerF/F6PWM6pinINTTC6interruptrequestWritetoPWREG6WritetoPWREG6Page117TMP88CS42NG12.
3.
516-BitTimerMode(TC5and6)Inthetimermode,theup-countercountsupusingtheinternalclock.
TheTimerCounter5and6arecascad-abletoforma16-bittimer.
Whenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,anINTTC6interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-countercontinuescounting.
Programthelowerbyteandupperbyteinthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Inthetimermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMj,andPPGjpinsmayoutputapulse.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogrammingofTTREGj.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Figure12-616-BitTimerModeTimingChart(TC5andTC6)Table12-5SourceClockfor16-BitTimerModeSourceClockResolutionMaximumTimeSettingNORMAL,IDLEmodeDV1CK=0fc=20MHzDV1CK=1fc=20MHzDV1CK=0fc=20MHzDV1CK=1fc=20MHzDV1CK=0DV1CK=1fc/211fc/212102.
4μs204.
8μs6.
7s13.
4sfc/27fc/286.
4μs12.
8μs419.
4ms838.
8msfc/25fc/261.
6μs3.
2μs104.
9μs209.
7msfc/23fc/240.
4μs0.
8μs26.
2μs52.
4msExample:Settingthetimermodewithsourceclockfc/27[Hz],andgeneratinganinterrupt240mslater(fc=20.
0MHz)LDW(TTREG5),927CH:Setsthetimerregister(300ms÷27/fc=927CH).
DISET(EIRD).
EF28:EnablesINTTC6interrupt.
EILD(TC5CR),13H:Setstheoperatingcocktofc/27,and16-bittimermode(lowerbyte).
LD(TC6CR),04H:Setsthe16-bittimermode(upperbyte).
LD(TC6CR),0CH:Startsthetimer.
1023mn-1mn01mn-1mn20120nmInternalsourceclockCounterMatchdetectCounterclearMatchdetectCounterclearTC6CRTTREG5(Lowerbyte)INTTC6interruptrequestTTREG6(Upperbyte)Page11812.
8-BitTimerCounter5,6(TC5,6)12.
1ConfigurationTMP88CS42NG12.
3.
616-BitEventCounterMode(TC5and6)12.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC5and6)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto16bitsofresolution.
TheTimerCounter5and6arecascadabletoformthe16-bitPWMsignalgenerator.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG5,PWREG6)valueisdetected,thelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestateagainbythecounteroverflow,andthecounteriscleared.
TheINTTC6interruptisgeneratedatthistime.
Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC5pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1orIDLE1mode.
SincetheinitialvaluecanbesettothetimerF/F6byTC6CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F6isclearedto0.
(ThelogicleveloutputfromthePWM6pinistheoppositetothetimerF/F6logiclevel.
)SincePWREG6and5inthePWMmodeareseriallyconnectedtotheshiftregister,thevaluessettoPWREG6and5canbechangedwhilethetimerisrunning.
ThevaluessettoPWREG6and5duringarunofthetimerareshiftedbytheINTTCjinterruptrequestandloadedintoPWREG6and5.
Whilethetimerisstopped,thevaluesareshiftedimmediatelyaftertheprogrammingofPWREG6and5.
Setthelowerbyte(PWREG5)andupperbyte(PWREG5)inthisordertoprogramPWREG6and5.
(Programmingonlythelowerorupperbyteoftheregistershouldnotbeattempted.
)IfexecutingthereadinstructiontoPWREG6and5duringPWMoutput,thevaluessetintheshiftregisterisread,butnotthevaluessetinPWREG6and5.
Therefore,afterwritingtothePWREG6and5,readingdataofPWREG6and5ispreviousvalueuntilINTTC6isgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREG6and5immediatelyaftertheINTTC6interruptrequestisgenerated(normallyintheINTTC6interruptserviceroutine.
)IftheprogrammingofPWREGjandtheinterruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofpulsedifferentfromtheprogrammedvalueuntilthenextINTTC6interruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWM6pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC6CRafterthetimerisstopped.
DonotprogramTC6CRuponstoppingofthetimer.
Example:FixingthePWM6pintothehighlevelwhentheTimerCounterisstoppedCLR(TC6CR).
3:Stopsthetimer.
CLR(TC6CR).
7:SetsthePWM6pintothehighlevel.
Intheeventcountermode,theup-countercountsupatthefallingedgetotheTC5pin.
TheTimerCounter5and6arecascadabletoforma16-biteventcounter.
Whenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,anINTTC6interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTC5pin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC5pin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMALorIDLEmode.
Programthelowerbyte(TTREG5),andupperbyte(TTREG6)inthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Note2:Note3:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimme-diatelyaftertheprogramming.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
j=5,6Page119TMP88CS42NGNote3:ToentertheSTOPmode,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwith-outstoppingofthetimerwhenfcorfc/2isselectedasthesourceclock,apulseisoutputfromthePWM6pinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Table12-616-BitPWMOutputModeSourceClockResolutionRepeatedCycleNORMAL,IDLEmodeDV1CK=0fc=20MHzDV1CK=1fc=20MHzDV1CK=0fc=20MHzDV1CK=1fc=20MHzDV1CK=0DV1CK=1fc/211[Hz]fc/212[Hz]102.
4μs204.
8μs6.
7s13.
4sfc/27fc/286.
4μs12.
8μs419.
4ms838.
8msfc/25fc/261.
6μs3.
2μs104.
9ms209.
7msfc/23fc/240.
4μs0.
8μs26.
2ms52.
4msExample:Generatingapulsewith1-mshigh-levelwidthandaperiodof32.
768ms(fc=20.
0MHz)SettingportsLDW(PWREG5),07D0H:Setsthepulsewidth.
LD(TC5CR),33H:Setstheoperatingclocktofc/23,and16-bitPWMoutputmode(lowerbyte).
LD(TC6CR),056H:SetsTFF6totheinitialvalue0,and16-bitPWMsignalgenerationmode(upperbyte).
LD(TC6CR),05EH:Startsthetimer.
Page12012.
8-BitTimerCounter5,6(TC5,6)12.
1ConfigurationTMP88CS42NGFigure12-716-BitPWMModeTimingChart(TC5andTC6)10anan+1FFFF0anan+1FFFF01bmbm+1FFFF0bmcpbc11cpnaanInternalsourceclock16-bitshiftregisterShiftShiftShiftShiftCounterMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectanbmcpanmpTC6CRTC6CRPWREG5(Lowerbyte)TimerF/F6PWM6pinINTTC6interruptrequestPWREG6(Upperbyte)WritetoPWREG6WritetoPWREG6WritetoPWREG5WritetoPWREG5Page121TMP88CS42NG12.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC5and6)Thismodeisusedtogeneratepulseswithupto16-bitsofresolution.
Thetimercounter5and6arecascad-abletoenterthe16-bitPPGmode.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG5,PWREG6)valueisdetected,thelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestateagainwhenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetected,andthecounteriscleared.
TheINTTC6interruptisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/F6byTC6CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F6isclearedto0.
(ThelogicleveloutputfromthePPG6pinistheoppositetothetimerF/F6.
)Setthelowerbyteandupperbyteinthisordertoprogramthetimerregister.
(TTREG5→TTREG6,PWREG5→PWREG6)(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)ForPPGoutput,settheoutputlatchoftheI/Oportto1.
Note1:InthePPGmode,donotchangethePWREGiandTTREGisettingswhilethetimerisrunning.
SincePWREGiandTTREGiarenotintheshiftregisterconfigurationinthePPGmode,thenewvaluespro-grammedinPWREGiandTTREGiareineffectimmediatelyafterprogrammingPWREGiandTTREGi.
Therefore,ifPWREGiandTTREGiarechangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPPGoutput,thePPG6pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC6CRafterthetimerisstopped.
DonotchangeTC6CRuponstoppingofthetimer.
Example:FixingthePPG6pintothehighlevelwhentheTimerCounterisstoppedCLR(TC6CR).
3:StopsthetimerCLR(TC6CR).
7:SetsthePPG6pintothehighlevelNote3:i=5,6Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof16.
385ms(fc=20.
0MHz)SettingportsLDW(PWREG5),07D0H:Setsthepulsewidth.
LDW(TTREG5),8002H:Setsthecycleperiod.
LD(TC5CR),33H:Setstheoperatingclocktofc/23,and16-bitPPGmode(lowerbyte).
LD(TC6CR),057H:SetsTFF6totheinitialvalue0,and16-bitPPGmode(upperbyte).
LD(TC6CR),05FH:Startsthetimer.
Page12212.
8-BitTimerCounter5,6(TC5,6)12.
1ConfigurationTMP88CS42NGFigure12-816-BitPPGModeTimingChart(TC5andTC60)10mnmn+1qr-1mnqr-11mnmn+1mn+10qr0qr10InternalsourceclockCounterWriteof"0"MatchdetectMatchdetectMatchdetectmnmnmnMatchdetectMatchdetectnmrqHeldatthelevelwhenthetimerstopsF/FclearTC6CRTC6CRPWREG5(Lowerbyte)TimerF/F6PPG6pinINTTC6interruptrequestPWREG6(Upperbyte)TTREG5(Lowerbyte)TTREG6(Upperbyte)Page123TMP88CS42NG13.
MotorControlCircuit(PMD:Programmablemotordriver)TheTMP88CS42NGcontainstwochannelsofmotorcontrolcircuitsusedforsinusoidalwaveformoutput.
ThismotorcontrolcircuitcancontrolbrushlessDCmotorsorACmotorswithorwithoutsensors.
Withitsprimaryfunc-tionslikethoselistedbelowincorporatedinhardware,ithelpstoaccomplishsinewavemotorcontroleasily,withthesoftwareloadsignificantlyreduced.
1.
RotorpositiondetectfunctionCandetecttherotorposition,withorwithoutsensorsCanbesettodeterminetherotorpositionwhendetectionmatchedanumberoftimes,topreventerro-neousdetectionCansetapositiondetectioninhibitperiodimmediatelyafterPWM-on2.
IndependenttimerandtimercapturefunctionsformotorcontrolContainsone-channelmagnitudecomparisontimerandtwo-channelcoincidencecomparisontimersthatoperatesynchronouslyforpositiondetection3.
PWMwaveformgeneratingfunctionGenerates12-bitPWMwith100nsresolutionCansetafrequencyofPWMinterruptoccurrenceCansetthedeadtimeatPWM-on4.
ProtectivefunctionProvidesoverloadprotectivefunctionbasedonprotectionsignalinput5.
EmergencystopfunctionincaseoffailureCanbemadetostopinanemergencybyEMGinputortimeroverflowinterruptNoteasilyclearedbysoftwarerunaway6.
Autocommutation/AutopositiondetectionstartfunctionComprisedofdual-buffers,canactivateautocommutationsynchronouslywithpositiondetectionortimerCansetapositiondetectionperiodusingthetimerfunctionandstartautopositiondetectionatthesettime7.
ElectricalangletimerfunctionCancount360degreesofelectricalanglewithasetperiodintherangeof0to383Canoutputthecountedelectricalangletothewaveformarithmeticcircuit8.
WaveformarithmeticcircuitCalculatetheoutputdutycyclefromthesinewavedataandvoltagedatawhicharereadfromtheRAMbasedontheelectricalangletimerOutputthecalculationresulttothewaveformsynthesiscircuitPage12413.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
1OutlineofMotorControlThefollowingexplainsthemethodforcontrollingabrushlessDCmotorwithsinewavedrive.
InabrushlessDCmotor,therotorwindingstowhichtoapplyelectriccurrentaredeterminedfromtherotor'smagneticpoleposition,andthecurrent-appliedwindingsarechangedastherotorturns.
Therotor'smagneticpolepositionisdeterminedusingasensorsuchasahallICorbydetectingpolaritychange(zero-cross)pointsoftheinducedvoltagethatdevel-opsinthemotorwindings(sensorlesscontrol).
Forthesensorlesscase,theinducedvoltageisdetectedbyapplyingelectriccurrenttotwophasesandnotapplyingelectriccurrenttotheremainingotherphase.
Inthistwo-phasecur-rentoncase,therearesixcurrentapplicationpatternsasshowninTable13-1,whicharechangedsynchronouslywiththephasesoftherotor.
Inthistwo-phasecurrentoncase,thecurrentontimeineachphaseis120degreesrela-tiveto180degreesoftheinducedvoltage.
Note:OneoftheupperorlowertransistorsisPWMcontrolled.
ForbrushlessDCmotors,thenumberofrevolutionsiscontrolledbyanappliedvoltage,andthevoltageapplica-tioniscontrolledbyPWM.
Atthistime,thecurrentonwindingsneedtobechangedinsynchronismwiththephasesofthevoltageinducedbyrevolutions.
ControltimingincaseswherethecurrentonwindingsarechangedbymeansofsensorlesscontrolisillustratedinFigure13-4.
Forthree-phasemotors,zero-crossingoccurssixtimesduringonecycleoftheinducedvoltage(electricalangle360degrees),sothattheelectricalanglefromonezero-crosspointtothenextis60degrees.
Assumingthatthisperiodcomprisesonemode,therotorpositioncanbedividedintosixmodesbyzero-crosspoints.
Thesixcurrentapplicationpatternsshownabovecorrespondoneforonetothesesixmodes.
Thetimingatwhichthecurrentapplicationpatternsarechanged(commutation)isoutofphaseby30degreesofelectricalangle,withrespecttothepositiondetectionbyaninducedvoltage.
Modetimeisobtainedbydetectingazero-crosspointatsometimingandfindinganelapsedtimefromthepreced-ingzero-crosspoint.
Becausemodetimecorrespondsto60degreesofelectricalangle,thefollowingappliesforthecaseillustratedinFigure13-4.
1.
Currentonwindingschangeover(commutation)timing30degreesofelectricalangle=modetime/22.
Positiondetectionstarttiming45degreesofelectricalangle=modetime*3/43.
Failuredeterminationtiming120degreesofelectricalangle=modetime*2Timingsarecalculatedinthisway.
Thepositiondetectionstarttimingin2isneededtopreventerroneousdetec-tionoftheinducedvoltageforreasonsthatevenaftercurrentapplicationisturnedoff,thecurrentcontinuesflowingduetothemotorreactance.
Controlisexercisedbycalculatingtheabovetimingssuccessivelyforeachofthezero-crosspointsdetectedsixtimesduring360degreesofelectricalangleandactivatingcommutation,positiondetectionstart,andotheropera-tionsaccordingtothattiming.
Inthisway,operationscanbesynchronizedtothephasesoftheinducedvoltageofthemotor.
Thetimingneededformotorcontrolasinthisexamplecanbesetfreelyasdesiredbyusingtheinternaltimersofthemicrocontroller'sPMDunit.
Also,sinewavecontrolrequirescontrollingthePWMdutycycleforeachpulse.
ControlofPWMdutycyclesisaccomplishedbycountingdegreesofelectricalangleandcalculatingthesinewavedataandvoltagedataatthecounteddegreeofelectricalangle.
Table13-1CurrentApplicationPatternsCurrentApplicationPatternUpperTransistorLowerTransistorCurrentonWindinguvwxyzMode0ONOFFOFFOFFONOFFU→VMode1ONOFFOFFOFFOFFONU→WMode2OFFONOFFOFFOFFONV→WMode3OFFONOFFONOFFOFFV→UMode4OFFOFFONONOFFOFFW→UMode5OFFOFFONOFFONOFFW→VPage125TMP88CS42NGFigure13-1ConceptualDiagramofDCMotorControlFigure13-2ExampleofSensorlessDCMotorControlTimingChartMCUDCcurrentCL,EMGPDU,PDV,PDWU,V,W,X,Y,ZPowerdriveUpperphase:u,v,wLowerphase:x,y,zPMDcircuitThree-phasePWMProtectivecontrolPositiondetectionElectricalangletimerWaveformcalculationSpeedcontrolErrorhandling,etc.
DCmotorWphaseVphaseUphaseZphasePositiondetectionPositiondetectionstartFailuredeterminationCommutationYphaseXphaseInternalsignalSix-phaseoutputModeInducedvoltageHWphaseVphaseUphaseL102345120453060ZerocrossingPage12613.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
2ConfigurationoftheMotorControlCircuitThemotorcontrolcircuitconsistsofvariousunits.
Theseincludeapositiondetectionunittodetectthezero-crosspointsoftheinducedvoltageorpositionsensorsignal,atimerunittogenerateeventsatthreeinstancesofelectricalangletiming,andathree-phasePWMoutputunittoproducethree-phaseoutputPWMwaveforms.
Alsoincludedareanelectricalangletimerunittocountdegreesofelectricalangleandawaveformarithmeticunittocalculatesinuso-idalwaveformoutputdutycycles.
Theinput/outputunitsareconfiguredasshowninthediagrambelow.
WhenusingportsforthePMDfunction,setthePortinput/outputcontrolregister(P3CRiandP5CRi)to0fortheinputports,andfortheoutputports,setthedataoutputlatch(P3iandP5i)to1andthentheportinput/outputcontrolregisterto1.
Otherinput/outputportscanbesetinthesamewayforuseofthePMDfunction.
Figure13-3BlockDiagramoftheMotorControlCircuitNote1:AlwaysusetheLDWinstructiontosetdatainthe9,12and16-bitdataregisters.
Note2:TheEMGcircuitinitiallyisenabled.
ForPMDoutput,fixtheEMGinputport(P36andP51)"H"highlevelordis-abletheEMGcircuitbeforeusingforPMDoutput.
Note3:TheEMGcircuitinitiallyisenabled.
WhenusingPortP3andP5asinput/outputIOports,disableEMG.
Note4:WhengoingtoSTOPmode,besuretoturnallofthePMDfunctionsoffbeforeenteringSTOPmode.
TimercircuitPositiondetectioncircuitElectricalangletimercircuitWaveformgenerationcircuitWaveformarithmeticcircuitCPUcorePositionsignalinputErrordetectioninputU,V,W,X,Y,ZMotorcontrolcircuitDataandaddressbusesPage127TMP88CS42NG13.
3PositionDetectionUnitThePositionDetectionUnitidentifiesthemotor'srotorpositionfrominputpatternsonthepositionsignalinputport.
AppliedtothispositionsignalinputportisthevoltagestatusofthemotorwindingsforthecaseofsensorlessDCmotorsoraHallelementsignalforthecaseofDCmotorswithsensorsincluded.
Theexpectedpatternscorre-spondingtospecificrotorpositionsaresetinthePMDOutputRegister(MDOUT)beforehand,andwhentheinputpositionsignalandtheexpectedvaluematchastherotation,apositiondetectioninterrupt(INTPDC)isgenerated.
Also,unmatchdetectionmodeisusedtodetectthedirectionofmotorrotation,wherewhenthestatusofthepositiondetectioninputportchangesfromthestatusinwhichitwasatstartofsampling,apositiondetectioninterruptisgen-erated.
Forthree-phasebrushlessDCmotors,therearesixpatternsofpositionsignals,oneforeachmode,assummarizedinTable13-2fromthetimingchartinFigure13-2.
OnceapredictedpositionsignalpatternissetintheMDOUTregister,apositiondetectioninterruptisgeneratedthemomentthepositionsignalinputportgoestomodeindicatedbythisexpectedvalue.
Thepositionsignalsateachphaseinthediagramareinternalsignalswhichcannotbeobservedfromtheoutside.
Table13-2PositionSignalInputPatternsPositionDetectionModeUPhase(PDU)VPhase(PDV)WPhase(PDW)Mode0HLHMode1HLLMode2HHLMode3LHLMode4LHHMode5LLHPage12813.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
3.
1ConfigurationofthepositiondetectionunitFigure13-4ConfigurationofthePositionDetectionCircuitThepositiondetectionunitiscontrolledbythePositionDetectionControlRegister(PDCRA,PDCRB).
Afterthepositiondetectionfunctionisenabled,theunitstartssamplingthepositiondetec-tionportwithTimer2orinsoftware.
Forthecaseofordinarymode,whenthestatusofthepositiondetectioninputportmatchestheexpectedvalueofthePMDOutputRegister,theunitgeneratesaposi-tiondetectioninterruptandfinishessampling,waitingforstartofthenextsampling.
Whenunmatchdetectionmodeisselectedforpositiondetection,theunitstoresthesampledstatusofthepositiondetectionportinmemoryatthetimeitstartedsampling.
Whentheportinputstatuschangesfromthestatusinwhichitwasatstartofsampling,aninterruptisgenerated.
Inunmatchdetectionmode,theportstatusatstartofsamplingcanberead(PDCRC).
Whenstartingandstoppingpositiondetectionsynchronouslywiththetimer,positiondetectionisstartedbyTimer2andpositiondetectionisstoppedbyTimer3.
Samplingmodecanbeselectedfromthreemodesavailable:modewheresamplingisperformedonlywhilePWMison,modewheresensorssuchasHallelementsaresampledregularly,andmodewheresamplingisperformedwhilethelowersideisconductingcurrent(whenperformingsamplingonlywhilePWMison,DUTYmustbesetforallthreephasesincommon).
Whensamplingmodeisselectedfordetectingpositionwhilethelowerphasesareconductingcurrent,samplingisperformedforaperiodfromwhenthesetsamplingdelaytimehaselapsedafterthelowersidestartedconductingcurrenttillwhenthecurrentapplicationisturnedoff.
Samplingisperformedindependentlyateachphase,andthesamplingresultisretainedwhilesamplingisidle.
Ifwhilesam-plingatsomephaseisidle,theinputandtheexpectedvalueatotherphasebeingsampledmatch,posi-tionisdetectedandaninterruptisgenerated.
Clockselector224DelaycircuitResetcontrolSamplingcontrolCounterLatchPWMONfc/4PDUPDVPDWPDNUMMDOUTsyncTimerinterruptINTTMR2/3PositiondetectioninterruptINTPDCPositionsignalinputCoincidencedetectionErroneousdetectionpreventioncircuitLatchSamplingcontrolcircuitPositiondetectioncontrolregisterSamplingdelaysetregisterPositionsignalexpectedvaluePMDoutputregisterSDREG-,6,5,4,3,2,1,00PDCRA1237,6,5,4PDCRB3,2,1,05,47,6----E,D,C-MDOUTPage129TMP88CS42NGAsamplingdelayisprovidedforuseinmodeswheresamplingismadewhilePWMisonorthelowerphasesareconductingcurrent.
Ithelpstopreventerroneousdetectionduetonoisethatoccursimmedi-atelyafterthetransistorturnson,bystartingsamplingasettimeafterthePWMsignalturnedon.
WhendetectingpositionwhilePWMisonorthelowerphasesareconductingcurrent,amethodcanbeselectedwhethertorecountoccurrencesofmatchedpositiondetectionafterbeingcomparedforeachPWMsignalon(logicalsumofthree-phasePWMsignals)(e.
g.
,startingfrom0ineachPWMcycle)orcountingoccurrencesofmatchingcontinuously(PDCRBisusedtoenable/disablerecount-ingoccurrencesofmatchingwhilePWMison).
13.
3.
2PositionDetectionCircuitRegisterFunctionsPDCRC5,4EMEMHoldresultofpositiondetec-tionatPWMedge(Detectpositiondetectedposition)ThesebitsholdthecomparisonresultofpositiondetectionatfallingorrisingedgeofPWMpulse.
Bits5and4aresetto1whenpositionisdetectedatthefallingortherisingedge,respectively.
TheyshowwhetherpositionisdetectedinthecurrentPWMpulse,duringPWMoff,orintheimmediatelyprecedingPWMpulse.
3SMONMonitorsamplingstatusWhenread,thisbitshowsthesamplingstatus.
2to0PDTCTHoldpositionsignalinputsta-tusThisbitholdsthestatusofthepositionsignalinputatthetimepositiondetectionstartedinunmatchmode.
PDCRB7,6SPLCKSamplingperiodSelectfc/22,fc/23,fc/24,orfc/25forthepositiondetectionsamplingperiod.
5,4SPLMDSamplingmodeSelectoneofthreemodes:samplingonlywhenPWMsignalisactive(whenPWMison),samplingregularly,orsamplingwhenthelowerside(X,Y,Z)phasesareconductingcur-rent.
3to0PDCMPSamplingcountInordinarymode,whentheportstatusandthesetexpectedvaluematchandcontinu-ouslymatchasmanytimesasthesamplingcountsset,apositiondetectionsignalisout-putandaninterruptisgenerated.
Inunmatchdetectionmode,whenthesaidstatusandvaluedonotmatchandcontinuouslyunmatchasmanytimesasthesamplingcountsset,apositiondetectionsignalisoutputandaninterruptisgenerated.
PDCRA7SWSTPStopsamplinginsoftwareSamplingcanbestoppedinsoftwarebysettingthisbitto1(e.
g.
,bywritingtothisregis-ter).
Samplingisperformedbeforestoppingandwhenpositiondetectionresultsmatch,aposi-tiondetectioninterruptisgenerated,withsamplingtherebystopped.
6SWSTTStartsamplinginsoftwareSamplingcanbestartedbysettingthisbitto1(e.
g.
,bywritingtothisregister).
5SPTM3StopsamplingusingTimer3SamplingcanbestoppedbyatriggerfromTimer3bysettingthisbitto1.
Samplingisperformedbeforestoppingandwhenpositiondetectionresultsmatch,aposi-tiondetectioninterruptisgenerated,withsamplingtherebystopped.
4STTM2StartsamplingusingTimer2SamplingcanbestartedbyatriggerfromTimer3bysettingthisbitto1.
3PDNUMNumberofpositionsignalinputpinsSelectwhethertousethreepins(PDU/PDV/PDW)oronepin(PDUonly)forpositionsig-nalinput.
Whenonepinisselected,theexpectedvaluesofPDVandPDWareignored.
WhenperformingpositiondetectionwithtwopinsorapinotherthanPDU,positionsignalinputcanbemaskedas0bysettingunusedpin(s)foroutput.
2RCENRecountoccurrencesofmatchingwhenPWMisonWhenperformingsamplingwhilePWMison,occurrencesofmatchingarerecountedeachtimePWMsignalturnsonbysettingthisbitto1(whenrecountingoccurrencesofmatching,thecountisreseteachtimePWMturnsoff).
Whenthisbitissetto0,occur-rencesofmatchingarecountedcontinuouslyregardlessPWMinterval.
1DTMDPositiondetectionmodeSettingthisbitto0selectsordinarymodewherepositionisdetectedwhentheexpectedvaluesetintheregisterandtheportinputunmatchandthenmatch.
Settingthisbitto1selectsunmatchdetectionmodewherepositionisdetectedatthetimetheportstatuschangestoanotheronefromthestatusinwhichitwaswhensamplingstarted.
0PDCENPositiondetectionfunctionThepositiondetectionfunctionisactivatedbysettingthisbitto1.
Page13013.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NGFigure13-5PositionDetectionSamplingTimingwiththePWMONPeriodSelectedFigure13-6DetectionTimingofthePositionDetectionPositionSDREG6to0SDREGSamplingdelaySetatimeforwhichtostopsamplinginordertopreventerroneousdetectionduetonoisethatoccursimmediatelyafterPWMoutputturnson(immediatelyafterthetransistorturnson).
(Figure13-5)1234500PWMNumberofpositiondetectionmatches(n=5)MatchPWMONperiodONOFFPositiondetectionmatchAlignthearrowtothestartofcounterswitching.
SamplingperiodSamplingdelaySamplingpausePWMCASE1CASE2CASE3CASE4EMEMvalueEMEM:Detectswhenapositiondetectionmatchhasoccurred(thevalueisheldaftrpositiondetection).
(Checkonwhethersamplinghasstartedonthepreviouspulse)ON1101101110000010OFFErroneousdetectionMatch(Samplingstart)Amatchwithn=5meansthatithasstartedonthepreviouspulse.
00101101Page131TMP88CS42NGNote:Whenchangingsetting,keepthePDCENbitresetto"0"(disablepositiondetectionfunction).
Note:Read-modify-writeinstructions,suchasabitmanipulationinstruction,cannotaccessthePDCRAbecauseitcontainsawriteonlybit.
PositionDetectionCircuitRegisters[Addresses(PMD1andPMD2)]PDCRC(01FA2H)(01FD2H)76543210––EMEMSMONPDTCT(Initialvalue:**000000)5,4EMEMHoldresultofpositiondetectionatPWMedge(Detectpositiondetectedposition)00:Detectedinthecurrentpulse01:DetectedwhilePWMoff10:Detectedinthecurrentpulse11:DetectedintheprecedingpulseR3SMONMonitorsamplingstatus0:Samplingidle1:Samplinginprogress2to0PDTCTHoldpositionsignalinputsta-tusHoldsthestatusofthepositionsignalinputduringunmatchdetectionmode.
Bits2to0correspondtoW,V,andUphases.
PDCRB(01FA1H)(01FD1H)76543210SPLCKSPLMDPDCMP(Initialvalue:00000000)7,6SPLCKSelectsamplinginputclock00:fc/22[Hz](200nsat20MHz)01:fc/23(400nsat20MHz)10:fc/24(800nsat20MHz)11:fc/25(1.
6μsat20MHz)R/W5,4SPLMDSamplingmode00:SamplewhenPWMison01:Sampleregularly10:Samplewhenlowerphasesconductingcurrent11:Reserved3to0PDCMPPositiondetectionmatchedcounts1to15times(Counts0and1areassumedtobeonetime.
)PDCRA(01FA0H)(01FD0H)76543210SWSTPSWSTTSPTM3STTM2PDNUMRCENDTMDPDCEN(Initialvalue:00000000)7SWSTPStopsamplinginsoftware0:Nooperation1:StopsamplingW6SWSTTStartsamplinginsoftware0:Nooperation1:Startsampling5SPTM3StopsamplingusingTimer30:Disable1:EnableR/W4STTM2StartsamplingusingTimer20:Disable1:Enable3PDNUMNumberofpositionsignalinputpins0:Comparethreepins(PDU/PDV/PDW)1:Compareonepin(PDU)only2RCENRecountoccurrencesofmatch-ingwhenPWMison0:ContinuecountingfrompreviouslyPWMon1:RecounteachtimePWMturnson1DTMDPositiondetectionmode0:Ordinarymode1:Unmatchdetectionmode0PDCENEnable/Disablepositiondetec-tionfunction0:Disable1:Enable(Samplingstarts)Page13213.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NGNote:Whenchangingsetting,keepthePDCENbitresetto"0"(disablepositiondetectionfunction).
13.
3.
3OutlineProcessinginthePositionDetectionUnitSDREG(01FA3H)(01FD3H)76543210–D6D5D4D3D2D1D0(Initialvalue:*0000000)6to0SDREGSamplingdelay23/fc*nbits(n=0to6,maximum50.
8μs,resolutionof400nsat20MHz)R/WEndofpositiondetectionStartpositiondetectionNoNoSpecifiedcountreachedMatchwithexpectedvalueYesYesIncrementmatchingcountsSamplepositionsignalinputINTTMR2INTPDCMDOUT(E,D,C)TimerunitSoftwareHardwareSetmodepatternIncrementmodecountsWriteexpectedvalueInterrupthandlingGenerateINTPDCinterruptPage133TMP88CS42NG13.
4TimerUnitFigure13-7TimerCircuitConfigurationThetimerunithasanupcounter(modetimer)whichisclearedbyapositiondetectioninterrupt(INTPDC).
Usingthiscounter,itcangeneratethreetypesoftimerinterrupts(INTTMR1to3).
Thesetimerinterruptsmaybeusedtoproduceacommutationtrigger,positiondetectionstarttrigger,etc.
Also,themodetimerhasacapturefunctionwhichautomaticallycapturesregisterdatainsynchronismwithpositiondetectionoroverloadprotection.
Thiscap-turefunctionallowsmotorrevolutionstobecalculatedbymeasuringpositiondetectionintervals.
Clockselector343ModetimerTimerresetcontrolcircuitCapturecontrolcircuitTimer1magnitudecomparisonfc/4Timer1interruptINTTMR1(Commutation)Timer2interruptINTTMR2(Positiondetectionstart)Timer3interruptINTTMR3(Overflow)OverloadprotectiveinterruptINTCLMPositiondetectioninterruptINTPDCOverflowCaptureCaptureoverwriteTimercompareregisterModecaptureregisterModetimercontrolregistersDebugoutput07,6,54,3,2,1MTCRA--53,2,17-MTCRBFto0Timer2matchingcomparisonTimer3matchingcomparisonFto0CMP1CMP2Fto0MCAPFto0CMP3Page13413.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
4.
1ConfigurationoftheTimerUnitThetimerunitconsistsmainlyofamodetimer,threetimercomparator,andmodecaptureregister,andiscontrolledbytimercontrolregistersandtimercompareregisters.
Themodetimercanberesetbyasignalfromthepositiondetectioncircuit,Timer3,oroverloadpro-tectivecircuit.
Ifthemodetimeroverflowswithoutbeingreset,itstopsatFFFFHandsetsanoverflowflaginthecontrolregister.
Thevalueofthemodetimerduringcountingcanbereadbycapturingthecountinsoftwareandread-ingthecaptureregister.
Timer1andTimers2and3generateaninterruptsignalbymagnitudecomparisonandmatchingcom-parison,respectively.
Therefore,Timer1cangenerateaninterruptsignalevenwhenitcouldnotwritetothecompareregisterintimeandthecountervalueatthetimeofwritinghappenstoexceedtheregis-ter'ssetvalue.
WhenanyoneofTimers1to3interruptsoccurs,thenextinterruptscanbeenabledbywritinganewvaluetotherespectivecompareregisters(CMP1,CMP2,CMP3).
Whencapturingbypositiondetectionisenabled,thecaptureregisterhasthetimervaluecapturediniteachtimepositionisdetected.
Inthisway,thecaptureregisteralwaysholdsthelatestvalue.
Page135TMP88CS42NG13.
4.
1.
1TimerCircuitRegisterFunctionsFigure13-8DBOUTDebugOutputDiagramMTCRB7DBOUTDebugoutputDebugoutputcanbeproducedbysettingthisbitto1.
Becauseinterruptsignalstotheinterruptcontrolcircuitareusedforeachinterrupt,hardwaredebuggingwithoutsoftwaredelaysarepossible.
Seethedebugoutputdiagram(Figure13-8).
Outputports:P67forPMD1,P77forPMD2.
5TMOFModetimeroverflowThisbitshowsthatthetimerhasoverflowed.
3CLCPCapturemodetimerbyover-loadprotectionWhenthisbitissetto1,thetimervaluecanbecapturedusingtheoverloadprotectionsignal(CL)asatrigger.
2SWCPCapturemodetimerinsoft-wareWhenthisbitissetto1,thetimervaluecanbecapturedinsoftware(e.
g.
,bywritingtothisregister).
1PDCCPCapturemodetimerbyposi-tiondetectionWhenthisbitissetto1,thetimervaluecanbecapturedusingthepositiondetectionsig-nalasatrigger.
MTCRA7,6,5TMCKSelectclockSelectthetimerclock.
4RBTM3ResetmodetimerfromTimer3Whenthisbitissetto1,themodetimerisresetbyatriggerfromTimer3.
3RBCLResetmodetimerbyover-loadprotectionWhenthisbitissetto1,themodetimerisresetbytheoverloadprotectionsignal(CL)asatrigger.
2SWRESResetmodetimerinsoftwareWhenthisbitissetto1,themodetimerisresetinsoftware(e.
g.
,bywritingtothisregis-ter)1RBPDCResetmodetimerbypositiondetectionWhenthisbitissetto1,themodetimerisresetbythepositiondetectionsignalasatrig-ger.
0TMENEnable/disablemodetimerThemodetimerisstartedbysettingthisbitto1.
Therefore,Timers1to3mustbesetwithCMPbeforesettingthisbit.
Ifthisbitissetto0aftersettingCMP,CMPsettingsbecomeineffective.
MCAPModecapturePositiondetectionintervalcanbereadout.
CMP1Timer1(commutation)Timers1to3areenabledwhilethemodetimerisoperating.
Aninterruptcanbegener-atedoncebysettingthecorrespondingbitinthisregister.
Theinterruptisdisablewhenaninterruptisgeneratedorthetimerisreset.
Tousethetimeragain,settheregisterbackagainevenifdataissame.
CMP2Timer2(positiondetectionstart)CMP3Timer3(overflow)Timer1interrupt(commutation)Timer2interrupt(positiondetectionstart)Timer3interruptorpositiondetectioninterruptDebugoutput(P67,P77)Page13613.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NGNote:Read-modify-writeinstructions,suchasabitmanipulationinstruction,cannotaccesstheMTCRBbecauseitcontainsawrite-onlybit.
Note1:WhenchangingMTCRAsetting,keeptheMTCRAbitresetto"0"(disablemodetimer).
Note2:Read-modify-writeinstructions,suchasabitmanipulationinstruction,cannotaccesstheMTCRAbecauseitcontainsawrite-onlybit.
TimerCircuitRegisters[Addresses(PMD1andPMD2)]MTCRB(01FA5H)(01FD5H)76543210DBOUT–TMOF–CLCPSWCPPDCCP–(Initialvalue:0*0*0000*)7DBOUTDebugoutput0:Disable1:Enable(P67forPMD1,P77forPMD2)R/W5TMOFModetimeroverflow0:Nooverflow1:OverflowedR3CLCPCapturemodetimerbyover-loadprotection0:Disable1:EnableR/W2SWCPCapturemodetimerinsoftware0:Nooperation1:CaptureW1PDCCPCapturemodetimerbypositiondetection0:Disable1:EnableR/WMTCRA(01FA4H)(01FD4H)76543210TMCKRBTM3RBCLSWRESRBPDCTMEN(Initialvalue:00000000)7,6,5TMCKSelectclock000:fc/23(400nsat20MHz)010:fc/24(800nsat20MHz)100:fc/25(1.
6μsat20MHz)110:fc/26(3.
2μsat20MHz)001:fc/27(6.
4μsat20MHz)011:Reserved101:Reserved111:ReservedR/W4RBTM3ResetmodetimerfromTimer30:Disable1:Enable3RBCLResetmodetimerbyoverloadprotection0:Disable1:Enable2SWRESResetmodetimerinsoftware0:Nooperation1:ResetW1RBPDCResetmodetimerbypositiondetection0:Disable1:EnableR/W0TMENEnable/disablemodetimer0:Disable1:EnabletimerstartMCAP(01FA7H,01FA6H)(01FD7H,01FD6H)FEDCBA9876543210(Initialvalue:0000000000000000)DFDEDDDCDBDAD9D8D7D6D5D4D3D2D1D0MCAPModecapturePositiondetectionintervalRCMP1(01FA9H,01FA8H)(01FD9H,01FD8H)FEDCBA9876543210(Initialvalue:0000000000000000)DFDEDDDCDBDAD9D8D7D6D5D4D3D2D1D0CMP2(01FABH,01FAAH)(01FDBH,01FDAH)FEDCBA9876543210(Initialvalue:0000000000000000)DFDEDDDCDBDAD9D8D7D6D5D4D3D2D1D0Page137TMP88CS42NGNote:Read-modify-writeinstructions,suchasabitmanipulationinstruction,cannotaccesstheMTCRBorMTCRAregisterbecausetheseregisterscontainwrite-onlybits.
13.
4.
1.
2OutlineProcessingintheTimerUnitCMP3(01FADH,01FACH)(01FDDH,01FDCH)FEDCBA9876543210(Initialvalue:0000000000000000)DFDEDDDCDBDAD9D8D7D6D5D4D3D2D1D0CMP1Timer1MagnitudecomparisoncompareregisterR/WCMP2Timer2MatchingcomparisoncompareregisterCMP3Timer3MatchingcomparisoncompareregisterEndoftimer1StartYesGreaterthancompare1NoModetimercountupStartEndModetimerMCAPClearmodetimerGenerateINTTMR1interruptGenerateINTTMR2interruptGenerateINTTMR3interruptINTPDCErrordeterminationINTTMR3PositiondetectionstartINTTMR2CommutationINTTMR1MCAPCMP1,CMP2,CMP3PositiondetectionunitSoftwareHardtwareCalculatetimersetvalueMCAP1/2MCAP3/4MCAP2InterrupthandlingerrorhandlingReadMCAPSettimerInterrupthandlingProcessingunnecessaryProcessingunnecessaryEndoftimer2YesMatchwithcompare2NoEndoftimer3YesMatchwithcompare3NoToPWMTothepositiondetectionunitPage13813.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
5Three-phasePWMOutputUnitTheThree-phasePWMOutputUnithasthefunctiontogeneratethree-phasePWMwaveswithanydesiredpulsewidthandthecommutationfunctioncapableofbrushlessDCmotorcontrol.
Inaddition,ithastheprotectivefunc-tionssuchasoverloadprotectionandemergencystopfunctionsnecessarytoprotectthepowerdriveunit,andthedeadtimeaddingfunctionwhichhelpstopreventthein-phaseupper/lowertransistorsfromgettingshortedbysimul-taneousturn-onwhenswitchedover.
ForthePWMoutputpin(U,V,W,X,Y,Z),settheportregisterPxDRandPxCR(x=3,5)to1.
ThePWMoutputinitiallyissettobeactivelow,sothatiftheoutputneedstobeusedactivehigh,setuptheMDCRARegisteraccord-ingly.
13.
5.
1Configurationofthethree-phasePWMoutputunitThethree-phasePWMoutputunitconsistsofapulsewidthmodulationcircuit,commutationcontrolcircuit,protectivecircuit(emergencystopandoverload),andadeadtimecontrolcircuit.
13.
5.
1.
1Pulsewidthmodulationcircuit(PWMwaveformgeneratingunit)Thiscircuitproducesthree-phaseindependentPWMwaveformswithanequalPWMfrequency.
ForPWMwaveformmode,triangularwavemodulationorsawtoothwavemodulationcanbeselectedbyusingthePMDControlRegister(MDCRA)bit1.
ThePWMfrequencyissetbyusingthePMDPeriodRegister(MDPRD).
ThefollowingshowstherelationshipbetweenthevalueofthisregisterandthePWMcounterclocksetbytheMDCRBRegister,PWMCK.
ThePMDPeriodRegister(MDPRD)iscomprisedofdual-buffers,sothatCMPU,V,WRegisterisupdatedwithPWMperiod.
Whenthewaveformarithmeticcircuitisoperating,thePWMwaveformoutputunitreceivescalculationresultsfromthewaveformarithmeticcircuitandbyusingtheresultsasCMPU,V,WRegistersetvalue,itoutputsindependentthree-phasePWMwaveforms.
WhenthewaveformcalculationfunctionisenabledbythewaveformarithmeticcircuitandtransferofcalculationresultsintotheCMPUtoWRegistersisenabled(withEDCRARegisterbit2),theCMPUtoWRegistersaredisabledagainstwriting.
Whenthewaveformcalculationfunctionisenabled(withEDCRARegisterbit1)andtransferofcalcu-lationresultsintotheCMPU,V,WRegistersisdisabled(withEDCRARegisterbit4),thecalculationresultsaretransferredtothebuffersofCMPU,V,WRegisters,butnotoutputtotheport.
Read-accessingtheCMPU,V,andWregisterscanreadthecalculationresultsofthewaveformarith-meticcircuitthathavebeeninputtoabuffer.
Afterchangingthereadcalculationresultdatabysoftware,writingthechangeddatatotheCMPU,V,andWregistersenablesanarbitrarywaveformotherthanasinusoidalwavetobeoutput.
Whentheregistersarereadafterwriting,thevalueswrittentotheregistersarereadoutifaccessedbeforethecalculationresultsaretransferredaftercalculationisfinished.
TriangularwavePWM:MDPRDRegistersetvalue1PWMfrequencyHz][2P*WMCK*-=SawtoothwavePWM:MDPRDRegistersetvalue1PWMfrequencyHz][PWMCK*-=Page139TMP88CS42NGFigure13-9PWMWaveformsThevaluesofthePWMCompareRegisters(CMPU/V/W)andthecarrierwavegeneratedbythePWMCounter(MDCNT)arecomparedfortherelativemagnitudebythecomparatortoproducePWMwave-forms.
ThePWMCounterisa12-bitup/downcounterwitha100ns(atfc=20MHz)resolution.
Forthree-phaseoutputcontrol,twomethodsofgeneratingthree-phasePWMwaveformscanbeset.
1.
Three-phaseindependentmode:Valuesaresetindependentlyinthethree-phasePMDCompareRegisterstoproducethree-phaseindependentPWMwaveforms.
Thismethodmaybeusedtoproducesinusoidaloranyotherdesireddrivewaveforms.
2.
Three-phasecommonmode:AvalueissetinonlytheU-phasePMDCompareRegistertopro-ducethreein-phasePWMwaveformsusingtheUphasesetvalue.
ThismethodmaybeusedforDCmotorsquarewavedrive.
Thethree-phasePMDCompareRegisterseachhaveacomparisonregistertocompriseadual-bufferstructure.
ThevaluesofthePMDCompareRegistersareloadedintotheirrespectivecomparisonregisterssynchronouslywithPWMperiod.
OnPWMUwaveformOffOnPWMUwaveformOff[MDPRD]MDCNTMDCNT[Sawtoothwave][Triangularwave][CMPU]TimeDataupdate[MDPRD][CMPU]TimeDataupdatePage14013.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
5.
1.
2CommutationcontrolcircuitOutputportsarecontrolleddependingonthecontentssetinthePMDOutputRegister(MDOUT).
Thecontentssetinthisregisteraredividedintotwo,oneforselectingthesynchronizingsignalforportoutput,andoneforsettingupportoutput.
ThesynchronizingsignalcanbeselectedfromTimers1or2,positiondetectionsignal,orwithoutsync.
PortoutputcanbesynchronizedtothissynchronizingsignalbeforebeingfurthersynchronizedtothePWMsignalsync.
TheMDOUTRegister'ssynchronizingsignalselectbitbecomeseffectiveimmediatelyafterwriting.
Otherbitsaredual-buffered,andareupdatedbytheselectedsynchronizingsignal.
Example:CommutationtimingforonetimerperiodwithPWMsynchronizationspecifiedOutputonsixportscanbesettobeactivehighoractivelowindependentlyofeachotherbyusingtheMDCRARegisterbits5and4.
Furthermore,theU,V,andWphasescanindividuallybeselectedbetweenPWMoutputandH/LoutputbyusingtheMDOUTRegisterbitsAto8and5to0.
WhenPWMoutputisselected,PWMwaveformsareoutput;whenH/Loutputisselected,awaveformwhichisfixedhighorlowisoutput.
TheMDOUTRegisterbitsEtoCsettheexpectedpositionsignalvalueforthepositiondetectioncircuit.
Figure13-10PulseWidthModulationCircuitINTTMRPWMCommutation3Selector/LatchPWMcontrolPWMinterruptINTPWMClockselectorPMDperiodregisterPMDcompareregisterPWMcounterPWMcontrolregister3,2,1760MDCRABto0MDPRDBto0MDCNT1to0MDCRBBto0CMPUBto0CMPWBto0CMPVBufferWBufferVBufferUSelector/LatchThree-phasecommon/Three-phaseUp/DownPWMUPWMVPWMWStopMDCNTPWMsynchronizingclockfc/2Page141TMP88CS42NGFigure13-11CommutationControlCircuitFigure13-12DeadTimeCircuitSSelectorSSelectorGatecontrolSetResetLatch632MDOUT5,4,3,2,1,0A,9,87,6B,,MDOUTsyncfc/4PWMsynchronizingclockPositiondetectioninterruptINTPDCTimer1interruptINTTMR1Timer2interruptINTTMR2PMDoutputregisteruxvywzPWMUPWMVPWMWONdelaycircuitONdelaycircuitONdelaycircuitfc/8u'x'v'y'w'z'DeadtimeregisterPMDcontrolregisterUXVYWZ-----MDCRA45-DTR-,-,5,4,3,2,1,0Page14213.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
5.
2RegisterFunctionsoftheWaveformSynthesisCircuitMDCRBPWMCKSelectPWMcounterclockSelectPWMcounterclock.
MDCRA7HLFINTSelecthalf-periodinterruptWhenthisbitissetto1,INTPWMisgeneratedeveryhalfperiod(attriangularwavepeakandvalley)inthecaseofcenterPWMoutputandPINT=00.
Inothercases,thissettinghasnomeaning.
6DTYMDDUTYmodeSelectwhethertosetthedutycycleindependentlyforthreephasesusingtheCMPUtoWRegistersorincommonforallthreephasesbysettingtheCMPURegisteronly.
5POLHUpper-phaseportpolaritySelecttheupper-phaseoutputportpolarity.
Makesurethewaveformsynthesisfunction(MDCRARegisterbit0)isidlebeforeselectingthisportpolarity.
4POLLLower-phaseportpolaritySelectthelower-phaseoutputportpolarity.
Makesurethewaveformsynthesisfunction(MDCRARegisterbit0)isidlebeforeselectingthisportpolarity.
3,2PINTPWMinterruptfrequencySelectthefrequencyatwhichtogenerateaPWMinterruptfromfourchoicesavailable:everyPWMperiodoronceevery2,4,or8PWMperiods.
Whensettingofthisbitisalteredwhileoperating,aninterruptmaybegeneratedatthetimethebitisaltered.
1PWMMDPWMmodeSelectPWMmode.
PWMmode0isanedgePWM(sawtoothwave),andPWMmode1isacenterPWM(triangularwave).
0PWMENEnable/DisablewaveformgenerationcircuitWhenenablingthiscircuit(forwaveformoutput),besuretosettheoutputportpolarityandotherbitsofthisregister(otherthanMDCRAbit0)beforehand.
DTRDTRDeadtimeSetthedeadtimebetweentheupper-phaseandlower-phaseoutputs.
MDOUTFUPDWNPWMcounterflagThisbitindicateswhetherthePWMcounteriscountingupordown.
WhenedgePWM(sawtoothwave)isselected,itisalwayssetto0.
E,D,CPDEXPModecompareregisterSetthedatatobecomparedwiththepositiondetectioninputport.
ThecomparisondataisadoptedastheexpectedvaluesimultaneouslywhenportoutputsyncsettingsmadewithMDOUTarereflectedintheports.
(ThisistheexpectedpositiondetectioninputvaluefortheoutputsetwithMDOUTnexttime.
)BPSYNCSelectPWMsynchronizationSelectwhetherornottosynchronizeportoutputtoPWMperiodafterbeingsynchronizedtothesynchronizingsignalselectedwithSYNCS.
IfselectedtobesynchronizedtoPWM,outputiskeptwaitingforthenextPWMafterbeingsynchronizedwithSYNCS.
Waveformsettingsareoverwrittenifnewsettingsarewrittentotheregisterduringthistime,andout-putisgeneratedwiththosesettings.
A98WPWMVPWMUPWMControlUVW-phasePWMoutputsSetU,V,andW-phaseportoutputs.
(SeetheTable13-3)7,6SYNCSSelectportoutputsyncsignalSelectthesynchronizingsignalwithwhichtooutputUVW-phasesettingstoports.
ThesynchronizingsignalcanbeselectedfromTimers1or2,positiondetection,orasynchro-nous.
Selectasynchronouswhentheinitialsetting,otherwisetheabovesettingisn'treflectedimmediately.
5,43,21,0WOCVOCUOCControlUVW-phaseoutputsSetU,V,andW-phaseportoutputs.
(SeetheTable13-3)MDCNTPWMcounterThisisa12-bitread-onlyregisterusedtocountPWMperiods.
MDPRDSetPWMperiodThisregisterdeterminesPWMperiod,andisdual-buffered,allowingPWMperiodtobealteredevenwhilethePWMcounterisoperating.
ThebuffersareloadedeveryPWMperiod.
When100nsisselectedforthePWMcounterclock,makesuretheleastsignifi-cantbitissetto0.
Page143TMP88CS42NGNote:Whenchangingsetting,keepthePWMENbitresetto"0"(disablewaveformsynthesisfunction).
Note:Whenchangingsetting,keeptheMDCRAbitresetto"0"(disablewaveformsynthesisfunction).
CMPUCMPVCMPWSetPWMpulsewidthThiscomparisonregisterdeterminesthepulsewidthsoutputintherespectiveUVWphases.
Thisregisterisdual-buffered,andthepulsewidthsaredeterminedbycomparingthebufferandPWMcounter.
WaveformSynthesisCircuitRegisters[Addresses(PMD1andPMD2)]MDCRB(01FAFH)(01FDFH)76543210PWMCK(Initialvalue:00)1,0PWMCKPWMcounterSelectclock00:fc/2[Hz](100nsat20MHz)01:fc/22(200nsat20MHz)10:fc/23(400nsat20MHz)11:fc/24(800nsat20MHz)R/WMDCRA(01FAEH)(01FDEH)76543210HLFINTDTYMDPOLHPOLLPINTPWMMDPWMEN(Initialvalue:00000000)7HLFINTSelecthalf-periodinterrupt0:InterruptasspecifiedinPINT1:InterrupteveryhalfperiodwhenPINT=00R/W6DTYMDDUTYmode0:Uphaseincommon1:Threephasesindependent5POLHUpper-phaseportpolarity0:Activelow1:Activehigh4POLLLower-phaseportpolarity0:Activelow1:Activehigh3,2PINTSelectPWMinterrupt(trigger)00:Interrupteveryperiod01:Interruptonceevery2periods10:Interruptonceevery4periods11:Interruptonceevery8periods1PWMMDPWMmode0:PWMmode0(Edge:Sawtoothwave)1:PWMmode1(Center:Triangularwave)0PWMENEnable/disablewaveformsyn-thesisfunction0:Disable1:Enable(Waveformoutput)DTR(01FBEH)(01FEEH)76543210––D5D4D3D2D1D0(Initialvalue:**000000)5to0DTRDeadtime23/fc*6bit(maximum25.
2μsat20MHz)R/WPage14413.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
5.
3PortoutputassetwithUOC/VOC/WOCbitsandUPWM/VPWM/WPWMbitsMDOUT(01FB3H,01FB2H)(01FE3H,01FE2H)FEDCBA98UPDWNPDEXPPSYNCWPWMVPWMUPWM76543210SYNCSWOCVOCUOC(Initialvalue:0000000000000000)FUPDWNPWMcounterflag0:Countingup1:CountingdownRE,D,CPDEXPComparisonregisterforposi-tiondetectionbitE:W-phaseexpectedvaluebitD:V-phaseexpectedvaluebitC:U-phaseexpectedvalueR/WBPSYNCSelectPWMsynchronization0:Asynchronous1:SynchronizedAWPWMW-phasePWMoutput0:H/Lleveloutput1:PWMwaveformoutput9VPWMV-phasePWMoutput0:H/Lleveloutput1:PWMwaveformoutput8UPWMU-phasePWMoutput0:H/Lleveloutput1:PWMwaveformoutput7,6SYNCSSelectportoutputsynchronizingsignal00:Asynchronous01:Synchronizedtopositiondetection10:SynchronizedtoTimer111:SynchronizedtoTimer25,4WOCControlW-phaseoutputSeethetable1-33,2VOCControlV-phaseoutput1,0UOCControlU-phaseoutputTable13-3ExampleofPinOutputSettingsU-phaseoutputpolarity:Activehigh(POLH,POLL=1)U-phaseoutputpolarity:Activelow(POLH,POLL=0)UOCUPWMUOCUPWM1:PWMoutput0:H/Lleveloutput1:PWMoutput0:H/LleveloutputUphaseXphaseUphaseXphaseUphaseXphaseUphaseXphase00PWMPWMLL00PWMPWMHH01LPWMLH01HPWMHL10PWMLHL10PWMHLH11PWMPWMHH11PWMPWMLLPage145TMP88CS42NGMDCNT(01FB5H,01FB4H)(01FE5H,01FE4H)FEDCBA9876543210(Initialvalue:****000000000000)––––DBDAD9D8D7D6D5D4D3D2D1D0Bto0PWMcounterPWMperiodcountervalueRMDPRD(01FB7H,01FB6H)(01FE7H,01FE6H)FEDCBA9876543210(Initialvalue:****000000000000)––––DBDAD9D8D7D6D5D4D3D2D1D0Bto0PWMperiodPWMperiodMDPRD≥010HR/WCMPU(01FB9H,01FB8H)(01FE9H,01FE8H)FEDCBA9876543210(Initialvalue:****000000000000)––––DBDAD9D8D7D6D5D4D3D2D1D0CMPV(01FBBH,01FBAH)(01FEBH,01FEAH)FEDCBA9876543210(Initialvalue:****000000000000)––––DBDAD9D8D7D6D5D4D3D2D1D0CMPW(01FBDH,01FBCH)(01FEDH,01FECH)FEDCBA9876543210(Initialvalue:****000000000000)––––DBDAD9D8D7D6D5D4D3D2D1D0Bto0CMPUPWMcompareUregisterSetU-phasedutycycleR/WCMPVPWMcompareVregisterSetV-phasedutycycleCMPWPWMcompareWregisterSetW-phasedutycyclePage14613.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
5.
4ProtectiveCircuitThiscircuitconsistsofanEMGprotectivecircuitandoverloadprotectivecircuit.
Thesecircuitsareactivatedbydrivingtheirrespectiveportinputsactive.
Figure13-13ConfigurationoftheProtectiveCircuita.
EMGprotectivecircuitThisprotectivecircuitisusedforemergencystop,whentheEMGprotectivecircuitisenabled.
WhenthesignalonEMGinputportgoesactive(negativeedgetriggered),thesixportsareimmedi-atelydisabledhigh-impedanceagainstoutputandanEMGinterrupt(INTEMG)isgenerated.
TheEMGControlRegister(EMGCRA)isusedtosetEMGprotection.
IftheEMGCRAshowsthevalue"1"whenread,itmeansthattheEMGprotectivecircuitisoperating.
ToreturnfromtheEMGprotectivestate,resettheMDOUTRegisterbitsAto0andsettheEMGCRAto1.
ReturningfromtheEMGprotectivestateiseffectivewhentheEMGprotectiveinputhasbeenreleasedbackhigh.
TodisabletheEMGfunction,setdata"5AH"and"A5H"sequentiallyintheEMGdisableRegister(EMGREL)andresettheEMGCRAto0.
WhentheEMGfunc-tionisdisabled,EMGinterrupts(INTEMG)arenotgenerated.
TheEMGprotectivecircuitisinitiallyenabled.
Beforedisablingit,fullystudyonadequacy.
b.
OverloadprotectivecircuitTheoverloadprotectivecircuitissetbyusingtheEMGControlRegisters(EMGCRA/B).
Toacti-vateoverloadprotection,settheEMGCRBto1toenabletheoverloadprotectivecircuit.
Thecircuitstartsoperatingwhentheoverloadprotectiveinputispulledlow.
Toreturnfromoverloadstate,therearethreemethodstouse:returnbyatimer(EMGCRB),returnbyPWMsync(EMGCRB),orreturnmanually(EMGCRB).
Thesemethodsareusablewhentheoverloadprotectiveinputhasbeenreleasedbackhigh.
CLdetectionResetcontrolEMGprotectivecontrolTimer1interruptINTTMR1PWMsynchronizingclockPWMsyncOverloadprotectiveinterruptINTCLMOverloadprotectiveinputCLStopMDCNTuxvywzu'x'v'y'w'z'EMGdisablecoderegisterEMGcontrolregister2107,6,5,4EMGCRA3,2,1,07EMGCRB46,5EMGREL7,6,5,4,3,2,1,0MDOUTAto022448OverloadprotectivecontrolSet"0"EMGEMGinputINTEMGEMGinterruptUnderprote-ctionPage147TMP88CS42NGThenumberoftimestheoverloadprotectiveinputissampledcanbesetbyusingtheEMGCRA.
Thesamplingtimescanbesetintherangeof1to15timesat200nsperiod(whenfc=20MHz).
Ifalowlevelisdetectedasmanytimesasthespecifiednumber,overloadpro-tectionisassumed.
TheoutputdisabledphasesduringoverloadprotectionaresetbyusingtheEMGCRB.
Thisfacilityallowsselectingtodisablenophases,allphases,PWMphases,orallupperphases/alllowerphases.
Whenselectedtodisableallupperphases/alllowerphases,portoutputisdeterminedbytheirturn-onstatusimmediatelybeforebeingdisabled.
Whentwoormoreupperphasesareactive,allupperphasesareturnedonandalllowerphasesareturnedoff;whentwoormorelowerphasesareactive,allupperphasesareturnedoffandalllowerphasesareturnedon.
Whenoutputphasearecutoff,outputisinactive(lowinthecaseofhighactive).
Whentheover-loadprotectivecircuitisdisabled,overloadprotectiveinterrupts(INTCLM)arenotgenerated.
Figure13-14ExampleofProtectionCircuitOperationEMGsettingcurrentInputEMGpinInputCLpinPWMoutput("H"active)OverloadprotectionsettingcurrentI(Current)EMGprotection(High-Zoutput)Overloadprotection(Outputcutoff)t(time)Page14813.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
5.
5FunctionsofProtectiveCircuitRegistersEMGRELEMGdisableTheEMGprotectivecircuitisdisablefromthedisabledstatebywriting"5AH"and"A5H"tothisregisterinthatorder.
Afterthat,theEMGCRARegisterneedstobeset.
EMGCRB7RTCLReturnfromoverloadprotec-tivestateWhenthisbitissetto1,themotorcontrolcircuitisreturnedfromoverloadprotectivestateinsoftware(e.
g.
,bywritingtothisregister).
Also,thecurrentstatecanbeknownbyread-ingthisbit.
MDOUToutputsatreturnfromtheoverloadprotectivestateremainassetbeforetheoverloadprotectiveinputwasdrivenactive.
6RTPWMReturnbyPWMsyncWhenthisbitissetto1,themotorcontrolcircuitisreturnedfromoverloadprotectivestatebyPWMsync.
IfRTCLissetto1,RTCLhaspriority.
5RTTM1ReturnbytimersyncWhenthisbitissetto1,themotorcontrolcircuitisreturnedfromoverloadprotectivestatebyTimer1sync.
IfRTCLissetto1,RTCLhaspriority.
4CLSTOverloadprotectivestateThestatusofoverloadprotectioncanbeknownbyreadingthisbit.
3,2CLMDSelectoutputdisabledphasesduringoverloadpro-tectionSelectthephasestobedisabledagainstoutputduringoverloadprotection.
Thisfacilityallowsselectingtodisablenophases,allphases,PWMphases,orallupperphases/alllowerphases.
1CNTSTStopcounterduringoverloadprotectionCanstopthePWMcounterduringoverloadprotection.
0CLENEnable/Disableoverloadpro-tectionEnableordisabletheoverloadprotectivefunction.
EMGCRA7to4CLCNTOverloadprotectionsamplingtimeSetthelengthoftimetheoverloadprotectiveinputportissampled.
2EMGSTEMGprotectivestateThestatusofEMGprotectioncanbeknownbyreadingthisbit.
1RTEReturnfromEMGprotectivestateThemotorcontrolcircuitisreturnedfromEMGprotectivestatebysettingthisbitto"1".
Whenreturning,settheMDOUTRegisterAto0bitsto"0".
ThensettheEMGCRAReg-isterbit1to"1"andsetMDOUTwaveformoutput.
ThensetuptheMDCRARegister.
0EMGENEnable/DisableEMGprotec-tivecircuitTheEMGprotectivecircuitisactivatedbysettingthisbitto1.
Thiscircuitinitiallyisenabled.
(Todisablethiscircuit,makesurekeycode5AHandA5HarewrittentotheEMGREL1Registerbeforehand.
)Page149TMP88CS42NGNote:Read-modify-writeinstructions,suchasabitmanipulationinstruction,cannotaccesstheEMGRELregisterbecausethisregisteriswriteonly.
Note:Ifduringoverloadprotectiontheportoutputstateintwoormoreupperphasesison,alllowerphasesaredisabledandallupperphasesareenabledforoutput;whentwoormorelowerphasesareon,allupperphasesaredisabledandalllowerphasesareenabledforoutput.
Note1:AninstructionspecifyingareturnfromtheEMGstateisinvalidiftheEMGinputis"L".
Note2:Read-modify-writeinstructions,suchasabitmanipulationinstruction,cannotaccesstheEMGCRBorEMGCRAregisterbecausetheseregisterscontainwrite-onlybits.
ProtectiveCircuitRegisters[Addresses(PMD1andPMD2)]EMGREL(01FBFH)(01FEFH)76543210D7D6D5D4D3D2D1D0(Initialvalue:00000000)7to0EMGRELEMGdisableCandisablebywriting5AHandthenA5H.
WEMGCRB(01FB1H)(01FE1H)76543210RTCLRTPWMRTTM1CLSTCLMDCNTSTCLEN(Initialvalue:00000000)7RTCLReturnfromoverloadprotec-tivestate0:Nooperation1:ReturnfromprotectivestateW6RTPWMEnable/DisablereturnfromoverloadprotectivestatebyPWMsync0:Disable1:EnableR/W5RTTM1Enable/Disablereturnfromoverloadprotectivestatebytimer10:Disable1:Enable4CLSTOverloadprotectivestate0:Nooperation1:UnderprotectionR3,2CLMDSelectoutputdisabledphasesduringoverloadprotection00:Nophasesdisabledagainstoutput01:Allphasesdisabledagainstoutput10:PWMphasesdisabledagainstoutput11:Allupper/Alllowerphasesdisabledagainstoutput(Note)R/W1CNTSTStopPWMcounterduringover-loadprotection0:Donotstop1:Stopthecounter0CLENEnable/Disableoverloadpro-tectivecircuit0:Disable1:EnableEMGCRA(01FB0H)(01FE0H)76543210CLCNTEMGSTRTEEMGEN(Initialvalue:0000*001)7to4CLCNTOverloadprotectionsamplingnumberoftimes.
22/fc*n(n=1to15,0and1aresetas1at20MHz)R/W2EMGSTEMGprotectivestate0:Nooperation1:UnderprotectionR1RTEReturnfromEMGstate0:Nooperation1:Returnfromprotectivestate(Note1)W0EMGENEnable/DisableEMGprotectivecircuit0:Disable1:EnableR/WPage15013.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
6ElectricalAngleTimerandWaveformArithmeticCircuitElectricalAngleTimerFigure13-15ElectricalAngleTimerCircuitWaveformArithmeticCircuitFigure13-16WaveformArithmeticCircuit24-bitcounterClockselectanddividecircuitDecoderCountstopPositiondetectionCaputure(EDCAP)12-bitcounterResetComparatorfc/85,4-7EDCRAELDEG8,7,6,5,4,3,2,1,0EDSETFtoCBto0PeriodcorrectioncircuitPeriodregisterbufferCorrectionvalue(4bits)Electricalangleperiod(12bits)9-bitelectricalangleregisterSelectorCalculationfinish8bits12bitsElectricalangletimer(9bits)ELDEG8,7,6,5,4,3,2,1,0AMPB,A,8,7,6,5,4,3,2,1,0Multiplier2-/3-phasemodulationswitchSelectorU-phasecalculationresultV-phasecalculationresultW-phasecalculationresultCMPVCMPUCMPW12bits12bits12bitsElectricalangletimerinterrupt(INTEDT)01234567WFMDREDCRA-,-0123EDCRBVoltagesetregister(12bits)ElectricalangleRAM384bytes0123-6Page151TMP88CS42NG13.
6.
1ElectricalAngleTimerandWaveformArithmeticCircuitTheElectricalAngleTimerfinishescountinguponreachingthevaluesetbythePeriodSetRegister(EDSET).
TheElectricalAngleTimercounts360degreesofelectricalangleintherangeof0to383(17FH)andisclearedto0uponreaching383.
Inthisway,itispossibletoobtaintheelectricalangleofthefrequencyproportionaltothevaluesetbythePeriodSetRegister.
TheperiodwithwhichtocountupcanbecorrectedbyusingthePeriodCorrectionRegister,allowingforfineadjustmentofthefrequency.
TheelectricalanglescountedbytheElectricalAngleTimerarepresentedtotheWaveformArithmeticCircuit.
AnelectricalangletimerinterruptsignalisgeneratedeachtimetheElectricalAngleTimerfinishescounting.
TheWaveformArithmeticCircuithasasinewavedatatable,whichisusedtoextractsinewavedatabasedontheelectricalangledatareceivedfromtheElectricalAngleTimer.
ThissinewavedataismultipliedbythevalueoftheVoltageAmplitudeRegister.
For2-phasemodulation,theproductobtainedbythismultiplicationispresentedtothewaveformsynthesiscircuit.
For3-phasemodulation,waveformdataisfurthercalculatedbasedontheproductofmultiplicationandtheelectricalangledataandthevalueofthePWMPeriodRegister.
ThecalculationisperformedeachtimetheElectricalAngleTimerfinishescountingorwhenavalueissetintheElectricalAngleRegister,andthecalculationresultsconsistingoftheUphase,theVphase(+120degrees),andtheWphase(+240degrees)aresequentiallypresentedtothePWMwaveformoutputcircuit.
ThesinewavedatatableisstoredintheRAMandrequiresinitialization.
Tocorrecttheperiod,setthenumberoftimes'n'tobecorrectedinthePeriodCorrectionRegister(EDSETRegisterFtoCbits).
Theperiodiscorrectedbyadding1toelectricalanglecounts16for'n'times.
Forexample,whenavalue3issetinthePeriodCorrectionRegister,theperiodfor13timesoutofelectricalanglecounts16isthevalue"mH"setinthePeriodSetRegister,andthatfor3timesis"m+1H".
(Correctionismadealmostatequalintervals.
)Becausetheelectricalanglecounter(ELDEG)canbeaccessedevenwhiletheElectricalAngleTimerisoperating,theelectricalanglescanbecorrectedduringoperation.
TheElectricalAngleCaptureEDCAPcapturestheelectricalanglevaluefromtheElectricalAngleCounteratthetimethepositionisdetected.
Whenthewaveformcalculationfunctionisenabled,waveformcalculationisperformedeachtimetheelectricalanglecounter(ELDEG)areaccessedforwriteortheElectricalAngleTimerfinishescount-ing.
Thecalculationisperformedin35machinecycleofexecutiontime,or7s(at20MHz).
WhentransferofcalculationresulttotheCMPRegistersisenabled(EDCRA),thecalcula-tionresultsaretransferredtotheCMPUtoWRegisters.
(Thisappliesonlywhenthewaveformcalcu-lationfunctionisenabledwiththeEDCRA.
)TheCMPUtoWRegistersaredisabledagainstwritewhilethetransferremainsenabled.
ThecalculationresultscanbereadfromtheCMPUtoWRegisterswhilethewaveformcalculationfunctionremainsenabled.
ThecalculatedresultscanbemodifiedandthemodifieddatacanbesetintheCMPUtoWRegistersinsoftware.
Thismakesitpossibletooutputanydesiredwaveformotherthansinewaves.
Ifatransfer(EDCRAregisterbit2)ofthecalculatedresultstotheCMPregisterisdisabled,read-accessingtheCMPUtoWregisterscanreadthecalculatedresults.
(Beforeread-accessingtheseregis-ters,makesurethatthecalculationiscompleted.
)ToinitializetheentireRAMdataofthesinewavedatatable,settheaddressesatwhichtoset,sequen-tiallyfrom000Hto17FH,intheELDEGRegister,andwritewaveformdatatotheWFMDRRegistereachtime.
MakesuretheWaveformArithmeticCircuitisdisabledwhenwritingthisdata.
Note1:ThevaluesetinthePeriodSetRegister(EDSETRegisterEDTbits)mustbeequaltoorgreaterthan010H.
Anyvaluesmallerthanthisisassumedtobe010H.
Note2:ThesinewavedatathatisreadconsistsoftheUphase,theVphasewhoseelectricalangleis+120degreesrelativetotheUphase,andtheWphasewhoseelectricalangleis+240degreesrelativetotheUphase.
Note3:Ifaperiodcorrespondingtoanelectricalangleofonedegreeisshorterthantherequiredcalculationtime,thepreviouslycalculatedresultsareused.
Page15213.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
6.
1.
1FunctionsoftheElectricalAngleTimerandWaveformArithmeticCircuitRegistersEDCRB3CALCSTStartcalculationbysoftwareForcefullystartcalculation.
Whenthisbitiswrittenwhilethewaveformarithmeticcircuitiscalculating,thecalculationisterminatedandthennewlystarted.
2CALCBSYCalculationflagByreadingthisbit,theoperationstatusofthewaveformarithmeticcircuitcanbeobtained.
1EDCALENEnable/disablecalculationstartsynchronizedwithelec-tricalangleSelectwhethertostartcalculationwhentheelectricalangletimerfinishescountingorwhenavalueissetintheelectricalangleregister.
Whendisabled,calculationisonlystartedwhenCALCSTissetto1.
0EDISELElectricalangleinterruptSettheelectricalangleinterruptsignalrequesttimingtoeitherwhentheelectricalangletimerfinishescountingoruponendofcalculation.
EDCRA7EDCNTElectricalanglecountup/downSetwhethertheelectricalangletimercountsupordown.
6EDRVSelectV-,W-phaseSelectphasedirectionofV-phaseandW-phaseinrelationtoU-phase.
5,4EDCKSelectclockSelecttheclockfortheelectricalangletimer.
Thissettingcanbealteredevenwhiletheelectricalangletimerisoperating.
3C2PENSwitchbetween2-phaseand3-phasemodulationsSelectthemodulationmethodwithwhichtoperformwaveformcalculation.
Two-phasemodulationDATA=ramdata(ELDEG)*AMPNote:The±signduring3-phasemodulationchangesdependingontheelectricalangle.
+forelectricalangles0to179degrees(191)forelectricalangles180(192)to360(383)degrees2RWRENAutotransfercalculationresultstoCPMregistersEnable/disabletransferofcalculationresultsbythewaveformarithmeticcircuit.
Whenthewaveformcalculationfunctionisenabledwhileatthesametimetransferisenabled,cal-culationresultsaresetasU,V,andW-phasedutycyclesofthePWMgenerationcircuitandarereflectedintheports.
1CALCENEnable/disablewaveformcal-culationfunctionEnable/disablethewaveformcalculationfunction.
Calculationsareperformedbythewaveformarithmeticcircuitbyenablingthewaveformcalculationfunction.
Whenthewaveformcalculationfunctionisenabled,thecalculatedresultscanbereadfromtheU,V,andW-phasecompareregisters(CMPU,V,W)ofthePWMgenerationcircuit.
0EDTENElectricalangletimerEnable/disabletheelectricalangletimer.
Whenenabled,theelectricalangletimerstartscounting;whendisabled,theelectricalangletimerstopscountingandisclearedto0.
EDSETFtoCEDTHCorrectelectricalangleperiodCorrecttheperiodbyadding1toelectricalanglecounts16for"n"times.
Thetimercountstheelectricalangleperiodsetvalue"m"'for(16n)timesandcounts(m+1)for"n"timesBto0EDTElectricalangleperiodSettheelectricalangleperiod.
ELDEGElectricalangleReadtheelectricalangle.
Thisregistercanalsobesettoinitializeorcorrecttheanglewhilecounting.
Anyvaluegreaterthan17FHcannotbeset.
AMPSetvoltageamplitudeSetthevoltageamplitude.
ThewaveformarithmeticcircuitmultipliesthedatasetherebythesinewavedatareadoutfromthesinewaveRAM.
TheamplitudehasitsupperlimitdeterminedbythesetvalueoftheMDPRDregisterwhenperformingthismultiplication.
EDCAPCaptureelectricalangleCapturethevaluefromtheelectricalangletimerwhenthepositionisdetected.
WFMDRSetsinewavedataToinitializetheentireRAMdataofthesinewavetable,settheaddressesatwhichtoset,sequentiallyfrom000Hto17FH,intheELDEGregister,andwritewaveformdatatotheWFMDRregistereachtime.
Makesurethewaveformarithmeticcircuitisdisabledwhenwritingthisdata.
Three-phasemodulation:DATAMOPRD2-ramdataELDEG()AMP*2-±=Page153TMP88CS42NGTypicalSettingsofSineWaveDataNote:During3-phasemodulation,thesignchangesat180degreesofelectricalangle.
Figure13-17TypicalSettingsofSineWaveDataData255100%amplitude100%amplitudeTwo-phasemodulationData255Three-phasemodulation0064(40H)(80H)(C0H)(100H)(140H)(17FH)60128120192180256240320300383360(ELDEG)Electricalangle0064(40H)(80H)(C0H)(100H)(140H)(17FH)60128120192180256240320300383360(ELDEG)ElectricalanglePage15413.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NGNote:Read-modify-writeinstructions,suchasabitmanipulationinstruction,cannotaccesstheEDCRBregisterbecausethisreg-isteriswriteonly.
Note:WhenchangingtheEDCRAsetting,keeptheEDCRAbitreset"0"(Disableelectricalangletimer).
ListoftheElectricalAngleTimerandWaveformArithmeticCircuitRegisters[Addresses(PMD1andPMD2)]EDCRB(01FC1H)(01FF1H)76543210––––CALCSTCALCBSYEDCALENEDISEL(Initialvalue:****0000)3CALCSTStartcalculationbysoftware0:Nooperation1:StartcalculationW2CALCBSYCalculationflag0:WaveformArithmeticCircuitstopped1:WaveformArithmeticCircuitcalculatingR1EDCALENEnable/disablecalculationstartsynchronizedwithelectricalangle0:Startcalculationinsyncwithelectricalangle1:DonotcalculationinsyncwithelectricalangleR/W0EDISELElectricalangleinterrupt0:InterruptwhentheElectricalAngleTimerfinishescounting1:InterruptuponendofcalculationEDCRA(01FC0H)(01FF0H)76543210EDCNTEDRVEDCKC2PENRWRENCALCENEDTEN(Initialvalue:00000000)7EDCNTElectricalanglecountup/down0:Countup1:CountdownR/W6EDRVSelectV-,W-phase0:V=U+120°,W=U+240°1:V=U120°,W=U240°5,4EDCKSelectclock00:fc/23(400nsat20MHz)01:fc/24(800nsat20MHz)10:fc/25(1.
6μsat20MHz)11:fc/26(3.
2μsat20MHz)3C2PENSwitchbetween2-/3-phasemodulations0:2-phasemodulation1:3-phasemodulation2RWRENTransfercalculationresulttoCMPregisters0:Disable1:Enable1CALCEnable/disablewaveformcal-culationfunction0:Disable1:Enable0EDTENElectricalangleEnable/disablemodetimer0:Disable1:EnablePage155TMP88CS42NGOneperiodoftheElectricalAngleTimer,T,isexpressedbytheequationbelow.
Note:Read-modify-writeinstructions,suchasabitmanipulationinstruction,cannotaccesstheWFMDRregisterbecausethisregisteriswriteonly.
EDSET(01FC3H,01FC2H)(01FF3H,01FF2H)FEDCBA9876543210(Initialvalue:0000000000010000)EDTHEDTFtoCEDTHCorrectperiod(n)0to15timesR/WBto0EDTSetperiod(m)≥010HELDEG(01FC5H,01FC4H)(01FF5H,01FF4H)FEDCBA9876543210(Initialvalue:000000000)D8D7D6D5D4D3D2D1D08to0ELDEGElectricalangleSettheInitiallyandthecountvaluesofelectricalangle.
R/WAMP(01FC7H,01FC6H)(01FF7H,01FF6H)FEDCBA9876543210(Initialvalue:****000000000000)––––DBDAD9D8D7D6D5D4D3D2D1D0Bto0AMPSetvoltageSetthevoltagetobeusedduringwaveformcalculation.
R/WEDCAP(01FC9H,01FC8H)(01FF9H,01FF8H)FEDCBA9876543210(Initialvalue:******000000000)D8D7D6D5D4D3D2D1D08to0EDCAPCapturedvalueofelectricalangleElectricalangletimervaluewhenpositionisdetected.
RWFMDR(01FCAH)(01FFAH)76543210D7D6D5D4D3D2D1D0(Initialvalue:7to0WFMDRSinewavedataWritesinewavedatatoRAMofsinewaveWTmn16------+384setclock**s[]wheremsetperiod,nperiodcorrection===Page15613.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NG13.
6.
1.
2ListofPMDRelatedControlRegisters(1)Input/outputPinsandInput/outputControlRegistersPMD1Input/OutputPins(P3,P4)andPortInput/OutputControlRegisters(P3CR,P4CR)PMD2Input/OutputPins(P5,P1)andPortInput/OutputControlRegisters(P5CR,P1CR)Note:WhenusingthesepinsasPMDfunctionorinputport,settheOutputLatch(P*DR)to1.
ExampleofthePMDPinPortSettingNameAddressBitRorWDescriptionP3DR00003H7R/WOverloadprotection(CL1)6R/WEMGinput(EMG1)5to0R/WU1/V1/W1/X1/Y1/Z1outputs.
P4DR00004H2to0R/WPositionsignalinputs(PDU1,PDV1,PDW1).
P3CR01F89H7to0R/WP3portinput/outputcontrol(canbesetbitwise).
0:Inputmode1:OutputmodeP4CR01F8AH2,1,0R/WP0portinput/outputcontrol(canbesetbitwise).
0:Inputmode1:OutputmodeNameAddressBitRorWDescriptionP5DR00005H0R/WOverloadprotection(CL2)1R/WEMGinput(EMG2)2to7R/WU2/V2/W2/X2/Y2/Z2outputs.
P1DR00001H5to7R/WPositionsignalinputs(PDU2,PDV2,PDW2).
P5CR01F8BH7to0R/WP3portinput/outputcontrol(canbesetbitwise).
0:Inputmode1:OutputmodeP1CR0000BH5,6,7R/WP0portinput/outputcontrol(canbesetbitwise).
0:Inputmode1:OutputmodeInput/OutputP3DRP3CRP4DRP4CRCL1Input*0––EMG1Input*0––U1Output11––PDU1Input––*0Input/OutputP5DRP5CRP1DRP1CRCL2Input*0––EMG2Input*0––U2Output11––PDU2Input––*0Page157TMP88CS42NG(2)MotorControlCircuitControlRegisters[AddressUpperStage:PMD1,LowerStage:PMD2]PositionDetectionControlRegister(PDCR)andSamplingDelayRegister(SDREG)NameAddressBitRorWDescriptionPDCRC01FA2H01FD2H5,4RDetecttheposition-detectedposition.
00:Withinthecurrentpulse01:WhenPWMisoff10:Withinthecurrentpulse11:Withintheprecedingpulse3RMonitorthesamplingstatus.
0:Samplingidle1:Samplinginprogress2to0RHoldsthestatusofthepositionsignalinputduringunmatchdetectionmode.
Bits2,1,and0:W,V,andUphasesPDCRB01FA1H01FD1H7,6R/WSelectthesamplinginputclock[Hz].
00:fc/2201:fc/2310:fc/2411:fc/255,4R/WSamplingmode.
00:WhenPWMison01:Regularly10:Whenlowerphasesareturnedon3to0R/WDetectionpositionmatchcounts1to15.
PDCRA01FA0H01FD0H7W0:Nooperation1:Stopsamplinginsoftware6W0:Nooperation1:Startsamplinginsoftware5R/WStopsamplingusingTimer3.
0:Disable1:Enable4R/WStartsamplingusingTimer2.
0:Disable1:Enable3R/WNumberofpositionsignalinputpins.
0:Comparethreepins(PDU/PDV/PDW)1:Compareonepin(PDU)only2R/WCountoccurrencesofmatchingwhenPWMison.
0:SubsequenttomatchingcountswhenPWMpreviouslywason1:EecountoccurrencesofmatchingeachtimePWMison1R/WPositiondetectionmode.
0:Ordinarymode1:Unmatchdetectionmode0R/WEnable/Disablepositiondetectionfunction.
0:Disable1:Enable(Samplingstarts)SDREG01FA3H01FD3H6to0R/WSamplingdelay.
23/fc*nbits(n=0to6,maximum50.
8μsat20MHz).
Page15813.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NGModeTimerControlRegister(MTCR),ModeCaptureRegister(MCAP),andCompareRegisters(CMP1,CMP2,CMP3)NameAddressBitRorWDescriptionMTCRB01FA5H01FD5H7R/WDebugoutput.
0:Disable1:Enable(P67forPMD1,P77forPMD2)5RModetimeroverflow.
0:Nooverflow1:Overflowedoccurred3R/WCapturemodetimerbyoverloadprotection.
0:Disable1:Enable2WCapturemodetimerbysoftware.
0:Nooperation1:Capture1R/WCapturemodetimerbypositiondetection.
0:Disable1:EnableMTCRA01FA4H01FD4H7,6,5R/WSelectclockformodetimer[Hz].
000:fc/23(400nsat20MHz)010:fc/24(800nsat20MHz)100:fc/25(1.
6μsat20MHz)110:fc/26(3.
2μsat20MHz)001:fc/27(6.
4μsat20MHz)011:Reserved101:Reserved111:Reserved4R/WResettimerbyTimer3.
0:Disable1:Enable3R/WResettimerbyoverloadprotection.
0:Disable1:Enable2WResettimerbysoftware.
0:Nooperation1:Reset1R/WResettimerbypositiondetection.
0:Disable1:Enable0R/WEnable/Disablemodetimer.
0:Disable1:Enable(timerstarts)MCAP01FA7H,01FA6H01FD7H,01FD6HFto0RModecaptureregister.
CMP101FA9H,01FA8H01FD9H,01FD8HFto0R/WCompareRegister1.
CMP201FABH,01FAAH01FDBH,01FDAHFto0R/WCompareRegister2.
CMP301FADH,01FACH01FDDH,01FDCHFto0R/WCompareRegister3.
Page159TMP88CS42NGPMDControlRegister(MDCR),DeadTimeRegister(DTR),andPMDOutputRegister(MDOUT)NameAddressBitRorWDescriptionMDCRB01FAFH01FDFH1,0R/WSelectclockforPWMcounter.
00:fc/2(100nsat20MHz)01:fc/22(200nsat20MHz)10:fc/23(400nsat20MHz)11:fc/24(800nsat20MHz)MDCRA01FAEH01FDEH7R/WSelecthalf-periodinterrupt0:InterrupteveryperiodasspecifiedinPINT.
1:Interrupteveryhalf-periodonlyPINT=00.
6R/WDUTYmode.
0:Uphaseincommon1:Threephasesindependent5R/WUpper-phaseportpolarity.
0:Activelow1:Activehigh4R/WLower-phaseportpolarity.
0:Activelow1:Activehigh3,2R/WSelectPWMinterrupt(trigger).
00:Interruptonceeveryperiod01:Interruptonce2periods10:Interruptonce4periods11:Interruptonce8periods1R/WPWMmode.
0:PWMmode0(edge:sawtoothwave)1:PWMmode1(center:triangularwave)0R/WEnable/disablewaveformsynthesisfunction.
0:Disable1:Enable(waveformoutput)DTR01FBEH01FEEH5to0R/WSetdeadtime.
23/fc*6bit(maximum25.
2μsat20MHz).
MDOUT01FB3H,01FB2H01FE3H,01FE2HFR0:Countup1:CountdownE,D,CR/WComparisonregisterforpositiondetection.
6:W5:V4:UBR/WSelectPWMsynchronization.
0:AsynchronouswithPWMperiod1:SynchronizedAR/WW-phasePWMoutput.
0:H/Lleveloutput1:PWMwaveformoutput9R/WV-phasePWMoutput.
0:H/Lleveloutput1:PWMwaveformoutput8R/WU-phasePWMoutput.
0:H/Lleveloutput1:PWMwaveformoutput7,6R/WSelectportoutputsynchronizingsignal.
00:Asynchronous01:Synchronizedtopositiondetection10:SynchronizedtoTimer111:SynchronizedtoTimer25,4R/WControlW-phaseoutput3,2R/WControlV-phaseoutput1,0R/WControlU-phaseoutputPage16013.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NGPWMCounter(MDCNT),PMDPeriodRegister(MDPRD),andPMDCompareRegisters(CMPU,CMPV,CMPW)EMGDisableCodeRegister(EMGREL)andEMGControlRegister(EMGCR)NameAddressBitRorWDescriptionMDCNT01FB5H,01FB4H01FE5H,01FE4HBto0RReadthePWMperiodcountervalue.
MDPRD01FB7H,01FB6H01FE7H,01FE6HBto0R/WPWMperiodMDPRD≥010H.
CMPU01FB9H,01FB8H01FE9H,01FE8HBto0R/WSetU-phasePWMdutycycle.
CMPV01FBBH,01FBAH01FEBH,01FEAHBto0R/WSetV-phasePWMdutycycle.
CMPW01FBDH,01FBCH01FEDH,01FECHBto0R/WSetW-phasePWMdutycycle.
NameAddressBitRorWDescriptionEMGREL01FBFH01FEFH7to0WCodeinputfordisableEMGprotectioncircuit.
Canbedisablebywriting5AHandthenA5H.
EMGCRB01FB1H01FE1H7WReturnfromoverloadprotectivestate.
0:Nooperation1:Returnfromprotectivestate6R/WConditionforreturningfromoverloadprotectivestate:SynchronizedtoPWM.
0:Disable1:Enable5R/WEnable/Disablereturnfromoverloadprotectivestatebytimer1.
0:Disable1:Enable4ROverloadprotectivestate.
0:Nooperation1:Underprotection3,2R/WSelectoutputdisabledphasesduringoverloadprotection.
00:Nophasesdisabledagainstoutput01:Allphasesdisabledagainstoutput10:PWMphasesdisabledagainstoutput11:Allupper/Alllowerphasesdisabledagainstoutput1R/WStopPWMcounter(MDCNT)duringoverloadprotection.
0:Donotstop1:Stop0R/WEnable/Disableoverloadprotectivecircuit.
0:Disable1:EnableEMGCRA01FB0H01FE0H7to4R/WOverloadprotectionsamplingtime.
22/fc*n(n=1to15,at20MHz)2REMGprotectivestate.
0:Nooperation1:Underprotection1WReturnfromEMGprotectivestate.
0:Nooperation1:Returnfromprotectivestate0R/WEnable/DisablefanctionoftheEMGprotectivecircuit.
0:Disable1:Enable(Thiscircuitinitiallyisenabled(=1).
Todisablethiscircuit,makesurekeycode5AHandA5HarewrittentotheEMGREL1Registerbefore-hand.
)Page161TMP88CS42NGElectricalAngleControlRegister(EDCR),ElectricalAnglePeriodRegister(EDSET),ElectricalAngleSetRegister(ELDEG),VoltageSetRegister(AMP),andElectricalAngleCaptureRegister(EDCAP).
NameAddressBitRorWDescriptionEDCRB01FC1H01FF1H3W0:Nooperation1:Startcalculation2R0:WaveformArithmeticCircuitstopped1:WaveformArithmeticCircuitcalculatin1R/W0:Startcalculationinsyncwithelectricalangle1:Donotcalculationinsyncwithelectricalangle0R/W0:InterruptwhentheElectricalAngleTimerfinishescounting1:InterruptuponendofcalculationEDCRA01FC0H01FF0H7R/W0:Countup1:Countdown6R/W0:V=U+120°,W=U+240°1:V=U120°,W=U240°5,4R/WSelectclock.
00:fc/2301:fc/2410:fc/2511:fc/263R/WSwitchbetween2/3-phasemodulations.
0:Two-phasemodulation1:Three-phasemodulation2R/WTransfercalculationresulttoCMPregisters.
0:Disable1:Enable1R/WEnable/disablewaveformcalculationfunction.
0:Disable1:Enable0R/WElectricalangletimer.
0:Disable1:EnableEDSET01FC3H,01FC2H01FF3H,01FF2HFtoCR/WCorrectperiod(n)0to15times.
Bto0R/WSetperiod(1/mcounter)≥010HELDEG01FC5H,01FC4H01FF5H,01FF4H8to0R/WInitiallysetandcountvaluesofelectricalangle.
AMP01FC7H,01FC6H01FF7H,01FF6HBto0R/WSetvoltageusedduringwaveformcalculation.
EDCAP01FC9H,01FC8H01FF9H,01FF8H8to0RElectricalangletimervaluewhenpositionisdetected.
WFMDR01FCAH01FFAH7to0WSetsinewavedata.
Page16213.
MotorControlCircuit(PMD:Programmablemotordriver)TMP88CS42NGPage163TMP88CS42NG14.
AsynchronousSerialinterface(UART)TheTMP88CS42NGhasaasynchronousserialinterface(UART).
ItcanconnecttheperipheralcircuitsthroughTXDandRXDpin.
TXDandRXDpinarealsousedasthegeneralport.
ForTXDpin,thecorrespondinggeneralportshouldbesetoutputmode(Setitsoutputcontrolregisterto"1"afteritsoutputportlatchto"1").
ForRXDpin,shouldbesetinputmode.
Theasynchronousserialinterface(UART)canselecttheconnectionpinwiththeperipheralcircuits.
RXD1andTXD1arecorrespondtoP44andP45pins,RXD2andTXD2aretoP00andP01pins.
Butthesynchronousserialinterface(SIO)alsouseP44andP45pins,thereforetheseP44andP45arenotavailableforUARTwhenSIOisonworking.
14.
1ConfigurationFigure14-1UART(AsynchronousSerialInterface)CounterYABCSSABCDYEFGHUARTstatusregisterUARTcontrolregister2UARTpinselectregisterIrDAoutputcontrolregisterUARTcontrolregister1TransmitdatabufferReceivedatabufferfc/13fc/26fc/52fc/104fc/208fc/416fc/96StopbitParitybitfc/26fc/27fc/28RXD1RXD2TXD1TXD2BaudrategeneratorTransmit/receiveclock243222NoiserejectioncircuitIrDAcontrolIRDACRUARTSELShiftregisterTransmitcontrolcircuitReceivecontrolcircuitShiftregisterMPXMPXMPXMPX:MultiplexerUARTCRATDBUFRDBUFINTTXDINTRXDUARTSRUARTCRBINTTC4Page16414.
AsynchronousSerialinterface(UART)14.
2ControlTMP88CS42NG14.
2ControlUARTiscontrolledbytheUARTControlRegisters(UARTCRA,UARTCRB).
Theoperatingstatuscanbemon-itoredusingtheUARTstatusregister(UARTSR).
TXDpinandRXDpincanbeselectedaportassignmentbyUARTPinSelectRegister(UARTSEL).
Note1:WhenoperationsaredisabledbysettingUARTCRAbitsto"0",thesettingbecomesvalidwhendatatransmitorreceivecomplete.
Whenthetransmitdataisstoredinthetransmitdatabuffer,thedataarenottransmitted.
Evenifdatatransmitisenabled,untilnewdataarewrittentothetransmitdatabuffer,thecurrentdataarenottransmitted.
Note2:Thetransmitclockandtheparityarecommontotransmitandreceive.
Note3:UARTCRAandUARTCRAshouldbesetto"0"beforeUARTCRAischanged.
Note4:Incasefc=20MHz,thetimercounter4(TC4)isavailableasabaudrategenerator.
Note:WhenUARTCRB="01",pulseslongerthan96/fc[s]arealwaysregardedassignals;whenUART-CRB="10",longerthan192/fc[s];andwhenUARTCRB="11",longerthan384/fc[s].
UARTControlRegister1UARTCRA(01F91H)76543210TXERXESTBTEVENPEBRG(Initialvalue:00000000)TXETransferoperation0:1:DisableEnableWriteonlyRXEReceiveoperation0:1:DisableEnableSTBTTransmitstopbitlength0:1:1bit2bitsEVENEven-numberedparity0:1:Odd-numberedparityEven-numberedparityPEParityaddition0:1:NoparityParityBRGTransmitclockselect000:001:010:011:100:101:110:111:fc/13[Hz]fc/26fc/52fc/104fc/208fc/416InputINTTC4fc/96UARTControlRegister2UARTCRB(01F92H)76543210RXDNCSTOPBR(Initialvalue:*****000)RXDNCSelectionofRXDinputnoiserejectiotime00:01:10:11:Nonoiserejection(Hysteresisinput)Rejectspulsesshorterthan31/fc[s]asnoiseRejectspulsesshorterthan63/fc[s]asnoiseRejectspulsesshorterthan127/fc[s]asnoiseWriteonlySTOPBRReceivestopbitlength0:1:1bit2bitsPage165TMP88CS42NGNote:WhenanINTTXDisgenerated,TBEPflagissetto"1"automatically.
Note1:DonotchangeUARTSELregisterduringUARToperation.
Note2:SetUARTSELregisterbeforeperformingthesettingterminalofaI/Oportwhenchangingaterminal.
UARTStatusRegisterUARTSR(01F91H)76543210PERRFERROERRRBFLTENDTBEP(Initialvalue:000011**)PERRParityerrorflag0:1:NoparityerrorParityerrorReadonlyFERRFramingerrorflag0:1:NoframingerrorFramingerrorOERROverrunerrorflag0:1:NooverrunerrorOverrunerrorRBFLReceivedatabufferfullflag0:1:ReceivedatabufferemptyReceivedatabufferfullTENDTransmitendflag0:1:OntransmittingTransmitendTBEPTransmitdatabufferemptyflag0:1:Transmitdatabufferfull(Transmitdatawritingisfinished)TransmitdatabufferemptyUARTReceiveDataBufferRDBUF(01F93H)76543210Readonly(Initialvalue:00000000)UARTTransmitDataBufferTDBUF(01F93H)76543210Writeonly(Initialvalue:00000000)UARTPinSelectRegisterUARTSEL(01F90H)76543210TXDSELRXDSEL(Initialvalue:00)RXDSELRXDconnectpinselect0:1:RXD1RXD2R/WTXDSELTXDconnectpinselect0:1:TXD1TXD2Page16614.
AsynchronousSerialinterface(UART)14.
3TransferDataFormatTMP88CS42NG14.
3TransferDataFormatInUART,anone-bitstartbit(Lowlevel),stopbit(Bitlengthselectableathighlevel,byUARTCRA),andparity(SelectparityinUARTCRA;even-orodd-numberedparitybyUARTCRA)areaddedtothetransferdata.
Thetransferdataformatsareshownasfollows.
Figure14-2TransferDataFormatFigure14-3CautiononChangingTransferDataFormatNote:Inordertoswitchthetransferdataformat,performtransmitoperationsintheaboveFigure14-3sequenceexceptfortheinitialsetting.
StartBit0Bit1Bit6Bit7Stop1StartBit0Bit1Bit6Bit7Stop1Stop2StartBit0Bit1Bit6Bit7ParityStop1StartBit0Bit1Bit6Bit7ParityStop1Stop2PE0011STBTFrameLength011238910111201Withoutparity/1STOPbitWithparity/1STOPbitWithoutparity/2STOPbitWithparity/2STOPbitPage167TMP88CS42NG14.
4TransferRateThebaudrateofUARTissetofUARTCRA.
Theexampleofthebaudrateareshownasfollows.
WhenINTTC4isusedastheUARTtransferrate(whenUARTCRA="110"),thetransferclockandtrans-ferratearedeterminedasfollows:Transferclock[Hz]=TC4sourceclock[Hz]/TC4DRsettingvalueTransferRate[baud]=Transferclock[Hz]/1614.
5DataSamplingMethodTheUARTreceiverkeepssamplinginputusingtheclockselectedbyUARTCRAuntilastartbitisdetectedinRXDpininput.
RTclockstartsdetecting"L"leveloftheRXDpin.
Onceastartbitisdetected,thestartbit,databits,stopbit(s),andparitybitaresampledatthreetimesofRT7,RT8,andRT9duringonereceiverclockinterval(RTclock).
(RT0isthepositionwherethebitsupposedlystarts.
)Bitisdeterminedaccordingtomajorityrule(Thedataarethesametwiceormoreoutofthreesamplings).
Figure14-4DataSamplingMethodTable14-1TransferRate(Example)BRGSourceClock16MHz8MHz00076800[baud]38400[baud]0013840019200010192009600011960048001004800240010124001200RT012345678910111213141501234567891011Bit0StartbitBit0Startbit(a)WithoutnoiserejectioncircuitRTclockInternalreceivedataRT012345678910111213141501234567891011Bit0StartbitBit0StartbitRTclockInternalreceivedata(b)WithnoiserejectioncircuitRXDpinRXDpinPage16814.
AsynchronousSerialinterface(UART)14.
6STOPBitLengthTMP88CS42NG14.
6STOPBitLengthSelectatransmitstopbitlength(1bitor2bits)byUARTCRA.
14.
7ParitySetparity/noparitybyUARTCRAandsetparitytype(Odd-orEven-numbered)byUARTCRA.
14.
8Transmit/ReceiveOperation14.
8.
1DataTransmitOperationSetUARTCRAto"1".
ReadUARTSRtocheckUARTSR="1",thenwritedatainTDBUF(Transmitdatabuffer).
WritingdatainTDBUFzero-clearsUARTSR,transfersthedatatothetrans-mitshiftregisterandthedataaresequentiallyoutputfromtheTXDpin.
Thedataoutputincludeaone-bitstartbit,stopbitswhosenumberisspecifiedinUARTCRAandaparitybitifparityadditionisspecified.
SelectthedatatransferbaudrateusingUARTCRA.
Whendatatransmitstarts,transmitbufferemptyflagUARTSRissetto"1"andanINTTXDinterruptisgenerated.
WhileUARTCRA="0"andfromwhen"1"iswrittentoUARTCRAtowhensenddataarewrittentoTDBUF,theTXDpinisfixedathighlevel.
Whentransmittingdata,firstreadUARTSR,thenwritedatainTDBUF.
Otherwise,UARTSRisnotzero-clearedandtransmitdoesnotstart.
14.
8.
2DataReceiveOperationSetUARTCRAto"1".
WhendataarereceivedviatheRXDpin,thereceivedataaretransferredtoRDBUF(Receivedatabuffer).
Atthistime,thedatatransmittedincludesastartbitandstopbit(s)andaparitybitifparityadditionisspecified.
Whenstopbit(s)arereceived,dataonlyareextractedandtransferredtoRDBUF(Receivedatabuffer).
ThenthereceivebufferfullflagUARTSRissetandanINTRXDinterruptisgenerated.
SelectthedatatransferbaudrateusingUARTCRA.
Ifanoverrunerror(OERR)occurswhendataarereceived,thedataarenottransferredtoRDBUF(Receivedatabuffer)butdiscarded;dataintheRDBUFarenotaffected.
Note:WhenareceiveoperationisdisabledbysettingUARTCRAbitto"0",thesettingbecomesvalidwhendatareceiveiscompleted.
However,ifaframingerroroccursindatareceive,thereceive-disablingsettingmaynotbecomevalid.
Ifaframingerroroccurs,besuretoperformare-receiveoperation.
Page169TMP88CS42NG14.
9StatusFlag14.
9.
1ParityErrorWhenparitydeterminedusingthereceivedatabitsdiffersfromthereceivedparitybit,theparityerrorflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterread-ingtheUARTSR.
Figure14-5GenerationofParityError14.
9.
2FramingErrorWhen"0"issampledasthestopbitinthereceivedata,framingerrorflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
Figure14-6GenerationofFramingError14.
9.
3OverrunErrorWhenallbitsinthenextdataarereceivedwhileunreaddataarestillinRDBUF,overrunerrorflagUARTSRissetto"1".
Inthiscase,thereceivedataisdiscarded;datainRDBUFarenotaffected.
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
ParityStopShiftregisterpxxxx0*1pxxxx0xxxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsPERR.
FinalbitStopShiftregisterxxxx0*0xxxx0xxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsFERR.
Page17014.
AsynchronousSerialinterface(UART)14.
9StatusFlagTMP88CS42NGFigure14-7GenerationofOverrunErrorNote:ReceiveoperationsaredisableduntiltheoverrunerrorflagUARTSRiscleared.
14.
9.
4ReceiveDataBufferFullLoadingthereceiveddatainRDBUFsetsreceivedatabufferfullflagUARTSRto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
Figure14-8GenerationofReceiveDataBufferFullNote:IftheoverrunerrorflagUARTSRissetduringtheperiodbetweenreadingtheUARTSRandreadingtheRDBUF,itcannotbeclearedbyonlyreadingtheRDBUF.
Therefore,afterreadingtheRDBUF,readtheUARTSRagaintocheckwhetherornottheoverrunerrorflagwhichshouldhavebeenclearedstillremainsset.
14.
9.
5TransmitDataBufferEmptyWhennodataisinthetransmitbufferTDBUF,thatis,whendatainTDBUFaretransferredtothetransmitshiftregisteranddatatransmitstarts,transmitdatabufferemptyflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheTDBUFiswrittenafterreadingtheUARTSR.
FinalbitStopShiftregisterxxxx0*1xxxx0yyyyxxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsOERR.
RDBUFUARTSRFinalbitStopShiftregisterxxxx0*1xxxx0xxxxyyyyxxx0**RXDpinUARTSRINTRXDinterruptRDBUFAfterreadingUARTSRthenRDBUFclearsRBFL.
Page171TMP88CS42NGFigure14-9GenerationofTransmitDataBufferEmpty14.
9.
6TransmitEndFlagWhendataaretransmittedandnodataisinTDBUF(UARTSR="1"),transmitendflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whenthedatatransmitisstatedafterwritingtheTDBUF.
Figure14-10GenerationofTransmitEndFlagandTransmitDataBufferEmptyShiftregisterDatawriteDatawritezzzzxxxxyyyyStartBit0FinalbitStop1xxxx0*****1*1xxxx****1x*****11yyyy0TDBUFTXDpinUARTSRINTTXDinterruptAfterreadingUARTSRwritingTDBUFclearsTBEP.
Shiftregister*1yyyy***1xx****1x*****1StopStart1yyyy0Bit0TXDpinUARTSRUARTSRINTTXDinterruptDatawriteforTDBUFPage17214.
AsynchronousSerialinterface(UART)14.
9StatusFlagTMP88CS42NGPage173TMP88CS42NG15.
SynchronousSerialInterface(SIO)TheTMP88CS42NGhasaclocked-synchronous8-bitserialinterface.
Serialinterfacehasan8-bytetransmitandreceivedatabufferthatcanautomaticallyandcontinuouslytransferupto64bitsofdata.
SerialinterfaceisconnectedtooutsideperipherldevicesviaSO,SI,SCKport.
15.
1ConfigurationFigure15-1SerialInterfaceSIOcontrol/statusregisterSerialclockShiftclockShiftregister32107654Transmitandreceivedatabuffer(8bytesinDBR)ControlcircuitCPUSerialdataoutputSerialdatainput8-bittransfer4-bittransferSerialclockI/OBuffercontrolcircuitSOSISCKSIOCR2SIOCR1SIOSRINTSIOinterruptrequestPage17415.
SynchronousSerialInterface(SIO)15.
2ControlTMP88CS42NG15.
2ControlTheserialinterfaceiscontrolledbySIOcontrolregisters(SIOCR1/SIOCR2).
TheserialinterfacestatuscanbedeterminedbyreadingSIOstatusregister(SIOSR).
ThetransmitandreceivedatabufferiscontrolledbytheSIOCR2.
Thedatabufferisassignedtoaddress01F98Hto01F9FHforSIOintheDBRarea,andcancontinuouslytransferupto8words(bytesornibbles)atonetime.
Whenthespecifiednumberofwordshasbeentransferred,abufferempty(inthetransmitmode)orabufferfull(inthereceivemodeortransmit/receivemode)interrupt(INTSIO)isgenerated.
Whentheinternalclockisusedastheserialclockinthe8-bitreceivemodeandthe8-bittransmit/receivemode,afixedintervalwaitcanbeappliedtotheserialclockforeachwordtransferred.
FourdifferentwaittimescanbeselectedwithSIOCR2.
Note1:fc;High-frequencyclock[Hz]Note2:SetSIOCR1to"0"andSIOCR1to"1"whensettingthetransfermodeorserialclock.
Note3:SIOCR1iswrite-onlyregister,whichcannotaccessanyofinread-modify-writeinstructionsuchasbitoperate,etc.
SIOControlRegister1SIOCR176543210(1F96H)SIOSSIOINHSIOMSCK(Initialvalue:00000000)SIOSIndicatetransferstart/stop0:StopWriteonly1:StartSIOINHContinue/aborttransfer0:Continuouslytransfer1:Aborttransfer(Automaticallyclearedafterabort)SIOMTransfermodeselect000:8-bittransmitmode010:4-bittransmitmode100:8-bittransmit/receivemode101:8-bitreceivemode110:4-bitreceivemodeExcepttheabove:ReservedSCKSerialclockselectNORMAL,IDLEmodeWriteonlyDV1CK=0DV1CK=0000fc/213fc/214001fc/28fc/29010fc/27fc/28011fc/26fc/27100fc/25fc/26101fc/24fc/25110Reserved111Externalclock(InputfromSCKpin)SIOControlRegister2SIOCR276543210(1F97H)WAITBUF(Initialvalue:***00000)Page175TMP88CS42NGNote1:Thelower4bitsofeachbufferareusedduring4-bittransfers.
Zeros(0)arestoredtotheupper4bitswhenreceiving.
Note2:Transmittingstartsatthelowestaddress.
Receiveddataarealsostoredstartingfromthelowestaddresstothehighestaddress.
(Thefirstbufferaddresstransmittedis01F98H).
Note3:ThevaluetobeloadedtoBUFisheldaftertransferiscompleted.
Note4:SIOCR2mustbesetwhentheserialinterfaceisstopped(SIOF=0).
Note5:*:Don'tcareNote6:SIOCR2iswrite-onlyregister,whichcannotaccessanyofinread-modify-writeinstructionsuchasbitoperate,etc.
Note7:Tf;Frametime,TD;DatatransfertimeFigure15-2Frametime(Tf)andDatatransfertime(TD)Note1:AfterSIOCR1isclearedto"0",SIOSRisclearedto"0"attheterminationoftransferorthesettingofSIOCR1to"1".
15.
3Serialclock15.
3.
1ClocksourceInternalclockorexternalclockforthesourceclockisselectedbySIOCR1.
WAITWaitcontrolAlwayssets"00"except8-bittransmit/receivemode.
Writeonly00:Tf=TD(Nonwait)01:Tf=2TD(Wait)10:Tf=4TD(Wait)11:Tf=8TD(Wait)BUFNumberoftransferwords(Bufferaddressinuse)000:1wordtransfer01F98H001:2wordstransfer01F98H~01F99H010:3wordstransfer01F98H~01F9AH011:4wordstransfer01F98H~01F9BH100:5wordstransfer01F98H~01F9CH101:6wordstransfer01F98H~01F9DH110:7wordstransfer01F98H~01F9EH111:8wordstransfer01F98H~01F9FHSIOStatusRegisterSIOSR76543210(1F97H)SIOFSEF(Initialvalue:00******)SIOFSerialtransferoperatingstatusmoni-tor0:1:TransferterminatedTransferinprocessReadonlySEFShiftoperatingstatusmonitor0:1:ShiftoperationterminatedShiftoperationinprocessTDTf(output)SCKoutputPage17615.
SynchronousSerialInterface(SIO)15.
3SerialclockTMP88CS42NG15.
3.
1.
1InternalclockAnyofsixfrequenciescanbeselected.
TheserialclockisoutputtotheoutsideontheSCKpin.
TheSCKpingoeshighwhentransferstarts.
Whendatawriting(inthetransmitmode)orreading(inthereceivemodeorthetransmit/receivemode)cannotkeepupwiththeserialclockrate,thereisawaitfunctionthatautomaticallystopstheserialclockandholdsthenextshiftoperationuntiltheread/writeprocessingiscompleted.
Note:1Kbit=1024bit(fc=20MHz)Figure15-3AutomaticWaitFunction(at4-bittransmitmode)15.
3.
1.
2ExternalclockAnexternalclockconnectedtotheSCKpinisusedastheserialclock.
Inthiscase,theSCK(P43)portshouldbesettoinputmode.
Toensureshifting,apulsewidthofmorethan24/fcisrequired.
Thispulseisneededfortheshiftoperationtoexecutecertainly.
Actually,thereisnecessaryprocessingtimeforinter-rupting,writing,andreading.
Theminimumpulseisdeterminedbysettingthemodeandtheprogram.
Figure15-4ExternalclockpulsewidthTable15-1SerialClockRateNORMAL,IDLEmodeSCKClockBaudRate000fc/2132.
44Kbps001fc/2878.
13Kbps010fc/27156.
25Kbps011fc/26312.
50Kbps100fc/25625.
00Kbps101fc/24125.
00Kbps110--111ExternalExternala1a2b0b1b2b3c0c1a3acba0pin(output)pin(output)WrittentransmitdataAutomaticallywaitfunctionSCKSOtSCKLtSCKHtSCKL,tSCKH>24/fcSCKpin(Input)Page177TMP88CS42NG15.
3.
2ShiftedgeTheleadingedgeisusedtotransmit,andthetrailingedgeisusedtoreceive.
15.
3.
2.
1LeadingedgeTransmitteddataareshiftedontheleadingedgeoftheserialclock(fallingedgeoftheSCKpininput/output).
15.
3.
2.
2TrailingedgeReceiveddataareshiftedonthetrailingedgeoftheserialclock(risingedgeoftheSCKpininput/out-put).
Figure15-5Shiftedge15.
4NumberofbitstotransferEither4-bitor8-bitserialtransfercanbeselected.
When4-bitserialtransferisselected,onlythelower4bitsofthetransmit/receivedatabufferregisterareused.
Theupper4bitsareclearedto"0"whenreceiving.
Thedataistransferredinsequencestartingattheleastsignificantbit(LSB).
15.
5NumberofwordstotransferUpto8wordsconsistingof4bitsofdata(4-bitserialtransfer)or8bits(8-bitserialtransfer)ofdatacanbetrans-ferredcontinuously.
ThenumberofwordstobetransferredcanbeselectedbySIOCR2.
AnINTSIOinterruptisgeneratedwhenthespecifiednumberofwordshasbeentransferred.
Ifthenumberofwordsistobechangedduringtransfer,theserialinterfacemustbestoppedbeforemakingthechange.
Thenumberofwordscanbechangedduringautomatic-waitoperationofaninternalclock.
Inthiscase,theserialinterfaceisnotrequiredtobestopped.
Bit1Bit2Bit3*3213210**32***3Bit0ShiftregisterShiftregisterBit1Bit0Bit2Bit30*******210*10**3210(a)Leadingedge(b)Trailingedge*;Don'tcareSOpinSIpinSCKpinSCKpinPage17815.
SynchronousSerialInterface(SIO)15.
6TransferModeTMP88CS42NGFigure15-6Numberofwordstotransfer(Example:1word=4bit)15.
6TransferModeSIOCR1isusedtoselectthetransmit,receive,ortransmit/receivemode.
15.
6.
14-bitand8-bittransfermodesInthesemodes,firstlysettheSIOcontrolregistertothetransmitmode,andthenwritefirsttransmitdata(numberoftransferwordstobetransferred)tothedatabufferregisters(DBR).
Afterthedataarewritten,thetransmissionisstartedbysettingSIOCR1to"1".
ThedataarethenoutputsequentiallytotheSOpininsynchronouswiththeserialclock,startingwiththeleastsignificantbit(LSB).
AssoonastheLSBhasbeenoutput,thedataaretransferredfromthedatabufferregistertotheshiftregister.
Whenthefinaldatabithasbeentransferredandthedatabufferregisterisempty,anINTSIO(Bufferempty)interruptisgeneratedtorequestthenexttransmitteddata.
Whentheinternalclockisused,theserialclockwillstopandanautomatic-waitwillbeinitiatedifthenexttransmitteddataarenotloadedtothedatabufferregisterbythetimethenumberofdatawordsspecifiedwiththeSIOCR2hasbeentransmitted.
Writingevenonewordofdatacancelstheautomatic-wait;therefore,whentransmittingtwoormorewords,alwayswritethenextwordbeforetransmissionofthepreviouswordiscompleted.
Note:AutomaticwaitsarealsocanceledbywritingtoaDBRnotbeingusedasatransmitdatabufferregister;there-fore,duringSIOdonotusesuchDBRforotherapplications.
Forexample,when3wordsaretransmitted,donotusetheDBRoftheremained5words.
Whenanexternalclockisused,thedatamustbewrittentothedatabufferregisterbeforeshiftingnextdata.
Thus,thetransferspeedisdeterminedbythemaximumdelaytimefromthegenerationoftheinterruptrequesttowritingofthedatatothedatabufferregisterbytheinterruptserviceprogram.
ThetransmissionisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inbufferemptyinterruptserviceprogram.
a1a2a3a0a1a2a3b0b1b2b3c0c1c2c3a0a1a0a2a3b0b1b2b3c0c1c2c3(a)1wordtransmit(b)3wordstransmit(c)3wordsreceiveSOpinINTSIOinterruptINTSIOinterruptINTSIOinterruptSOpinSIpinSCKpinSCKpinSCKpinPage179TMP88CS42NGSIOCR1iscleared,theoperationwillendafterallbitsofwordsaretransmitted.
ThatthetransmissionhasendedcanbedeterminedfromthestatusofSIOSRbecauseSIOSRisclearedto"0"whenatransferiscompleted.
WhenSIOCR1isset,thetransmissionisimmediatelyendedandSIOSRisclearedto"0".
Whenanexternalclockisused,itisalsonecessarytoclearSIOCR1to"0"beforeshiftingthenextdata;IfSIOCR1isnotclearedbeforeshiftout,dummydatawillbetransmittedandtheoperationwillend.
Ifitisnecessarytochangethenumberofwords,SIOCR1shouldbeclearedto"0",thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Figure15-7TransferMode(Example:8bit,1wordtransfer,Internalclock)Figure15-8TransferMode(Example:8bit,1wordtransfer,Externalclock)a1a2a3a4a5a6a7b0b1b2b3b4b5b6b7a0DBRbaClearSIOSWrite(a)Write(b)SCKpin(Output)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRSIOSRa1a2a3a4a5a6a7b0b1b2b3b4b5b6b7a0DBRbaClearSIOSWrite(a)Write(b)SCKpin(Input)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRPage18015.
SynchronousSerialInterface(SIO)15.
6TransferModeTMP88CS42NGFigure15-9TransmiiiedDataHoldTimeatEndofTransfer15.
6.
24-bitand8-bitreceivemodesAftersettingthecontrolregisterstothereceivemode,setSIOCR1to"1"toenablereceiving.
ThedataarethentransferredtotheshiftregisterviatheSIpininsynchronouswiththeserialclock.
Whenonewordofdatahasbeenreceived,itistransferredfromtheshiftregistertothedatabufferregister(DBR).
WhenthenumberofwordsspecifiedwiththeSIOCR2hasbeenreceived,anINTSIO(Bufferfull)interruptisgeneratedtorequestthatthesedatabereadout.
Thedataarethenreadfromthedatabufferregistersbytheinterruptserviceprogram.
Whentheinternalclockisused,andthepreviousdataarenotreadfromthedatabufferregisterbeforethenextdataarereceived,theserialclockwillstopandanautomatic-waitwillbeinitiateduntilthedataareread.
Awaitwillnotbeinitiatedifevenonedatawordhasbeenread.
Note:WaitsarealsocanceledbyreadingaDBRnotbeingusedasareceiveddatabufferregisterisread;therefore,duringSIOdonotusesuchDBRforotherapplications.
Whenanexternalclockisused,theshiftoperationissynchronizedwiththeexternalclock;therefore,thepreviousdataarereadbeforethenextdataaretransferredtothedatabufferregister.
Ifthepreviousdatahavenotbeenread,thenextdatawillnotbetransferredtothedatabufferregisterandthereceivingofanymoredatawillbecanceled.
Whenanexternalclockisused,themaximumtransferspeedisdeterminedbythedelaybetweenthetimewhentheinterruptrequestisgeneratedandwhenthedatareceivedhavebeenread.
ThereceivingisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inbufferfullinterruptserviceprogram.
WhenSIOCR1iscleared,thecurrentdataaretransferredtothebuffer.
AfterSIOCR1cleared,thereceivingisendedatthetimethatthefinalbitofthedatahasbeenreceived.
ThatthereceivinghasendedcanbedeterminedfromthestatusofSIOSR.
SIOSRisclearedto"0"whenthereceiv-ingisended.
Afterconfirmedthereceivingtermination,thefinalreceivingdataisread.
WhenSIOCR1isset,thereceivingisimmediatelyendedandSIOSRisclearedto"0".
(Thereceiveddataisignored,anditisnotrequiredtobereadout.
)Ifitisnecessarytochangethenumberofwordsinexternalclockoperation,SIOCR1shouldbeclearedto"0"thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Ifitisnecessarytochangethenumberofwordsininternalclock,duringautomatic-waitoperationwhichoccursaftercompletionofdatareceiving,SIOCR2mustberewrittenbeforethereceiveddataisreadout.
Note:Thebuffercontentsarelostwhenthetransfermodeisswitched.
Ifitshouldbecomenecessarytoswitchthetransfermode,endreceivingbyclearingSIOCR1to"0",readthelastdataandthenswitchthetrans-fermode.
MSBoflastwordtSODH=min3.
5/fc[s](IntheNORMAL,IDLEmodes)SCKpinSOpinSIOSRPage181TMP88CS42NGFigure15-10ReceiveMode(Example:8bit,1wordtransfer,Internalclock)15.
6.
38-bittransfer/receivemodeAftersettingtheSIOcontrolregistertothe8-bittransmit/receivemode,writethedatatobetransmittedfirsttothedatabufferregisters(DBR).
Afterthat,enablethetransmit/receivebysettingSIOCR1to"1".
Whentransmitting,thedataareoutputfromtheSOpinatleadingedgesoftheserialclock.
Whenreceiving,thedataareinputtotheSIpinatthetrailingedgesoftheserialclock.
Whentheallreceiveisenabled,8-bitdataaretransferredfromtheshiftregistertothedatabufferregister.
AnINTSIOinterruptisgeneratedwhenthenumberofdatawordsspecifiedwiththeSIOCR2hasbeentransferred.
Usually,readthereceivedatafromthebufferregisterintheinterruptservice.
Thedatabufferregisterisusedforbothtransmittingandreceiving;therefore,alwayswritethedatatobetransmittedafterreadingtheallreceiveddata.
Whentheinternalclockisused,awaitisinitiateduntilthereceiveddataarereadandthenexttransferdataarewritten.
Awaitwillnotbeinitiatedifevenonetransferdatawordhasbeenwritten.
Whenanexternalclockisused,theshiftoperationissynchronizedwiththeexternalclock;therefore,itisnecessarytoreadthereceiveddataandwritethedatatobetransmittednextbeforestartingthenextshiftoper-ation.
Whenanexternalclockisused,thetransferspeedisdeterminedbythemaximumdelaybetweengenera-tionofaninterruptrequestandthereceiveddataarereadandthedatatobetransmittednextarewritten.
Thetransmit/receiveoperationisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inINTSIOinterruptserviceprogram.
WhenSIOCR1iscleared,thecurrentdataaretransferredtothebuffer.
AfterSIOCR1cleared,thetransmitting/receivingisendedatthetimethatthefinalbitofthedatahasbeentransmitted.
Thatthetransmitting/receivinghasendedcanbedeterminedfromthestatusofSIOSR.
SIOSRisclearedto"0"whenthetransmitting/receivingisended.
WhenSIOCR1isset,thetransmit/receiveoperationisimmediatelyendedandSIOSRisclearedto"0".
Ifitisnecessarytochangethenumberofwordsinexternalclockoperation,SIOCR1shouldbeclearedto"0",thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Ifitisnecessarytochangethenumberofwordsininternalclock,duringautomatic-waitoperationwhichoccursaftercompletionoftransmit/receiveoperation,SIOCR2mustberewrittenbeforereadingandwritingofthereceive/transmitdata.
a1a0a2a3a4a5a6a7b0b1b2b3b4b5b6b7DBRbaClearSIOSReadoutReadoutSCKpin(Output)SIpinINTSIOInterruptSIOCR1SIOSRSIOSRPage18215.
SynchronousSerialInterface(SIO)15.
6TransferModeTMP88CS42NGNote:Thebuffercontentsarelostwhenthetransfermodeisswitched.
Ifitshouldbecomenecessarytoswitchthetransfermode,endreceivingbyclearingSIOCR1to"0",readthelastdataandthenswitchthetrans-fermode.
Figure15-11Transfer/ReceiveMode(Example:8bit,1wordtransfer,Internalclock)Figure15-12TransmittedDataHoldTimeatEndofTransfer/Receivea1a0a2a3a4a5a6a7b0b1b2b3b4b5b6b7c1c0c2c3c4c5cbc6c7d0d1d2d3d4d5d6d7ClearSIOSDBRdaReadout(c)Write(a)Readout(d)Write(b)SCKpin(output)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRSIpinBit7oflastwordBit6tSODH=min4/fc[s](IntheNORMAL,IDLEmodes)SCKpinSOpinSIOSRPage183TMP88CS42NG16.
10-bitADConverter(ADC)TheTMP88CS42NGhavea10-bitsuccessiveapproximationtypeADconverter.
16.
1ConfigurationThecircuitconfigurationofthe10-bitADconverterisshowninFigure16-1.
ItconsistsofcontrolregisterADCCRAandADCCRB,convertedvalueregisterADCDRHandADCDRL,aDAconverter,asample-holdcircuit,acomparator,andasuccessivecomparisoncircuit.
Note:BeforeusingADconverter,setappropriatevaluetoI/Oportregisterconbiningaanaloginputport.
Fordetails,seethesec-tionon"I/Oports".
Figure16-110-bitADConverter24108AINDSADRSR/2R/2RACKAMDIREFONADconversionresultregister1,2ADconvertercontrolregister1,2ADBFEOCFINTADCSAINnSuccessiveapproximatecircuitADCCRBADCDRHADCDRLADCCRASampleholdcircuitASENShiftclockDAconverterAnaloginputmultiplexerYReferencevoltageAnalogcomparator23ControlcircuitAVSSVAREFAVDDAIN0AIN15Page18416.
10-bitADConverter(ADC)16.
2RegisterconfigurationTMP88CS42NG16.
2RegisterconfigurationTheADconverterconsistsofthefollowingfourregisters:1.
ADconvertercontrolregister1(ADCCRA)Thisregisterselectstheanalogchannelsandoperationmode(Softwarestartorrepeat)inwhichtoper-formADconversionandcontrolstheADconverterasitstartsoperating.
2.
ADconvertercontrolregister2(ADCCRB)ThisregisterselectstheADconversiontimeandcontrolstheconnectionoftheDAconverter(Ladderresistornetwork).
3.
ADconvertedvalueregister1(ADCDRH)ThisregisterusedtostorethedigitalvalueafterbeingconvertedbytheADconverter.
4.
ADconvertedvalueregister2(ADCDRL)ThisregistermonitorstheoperatingstatusoftheADconverter.
Note1:SelectanaloginputchannelduringADconverterstops(ADCDRL="0").
Note2:Whentheanaloginputchannelisallusedisabling,theADCCRAshouldbesetto"1".
Note3:Duringconversion,Donotperformportoutputinstructiontomaintainaprecisionforallofthepinsbecauseanaloginputportuseasgeneralinputport.
Andforportneartoanaloginput,Donotinputintensesignalingofchange.
Note4:TheADCCRAisautomaticallyclearedto"0"afterstartingconversion.
Note5:DonotsetADCCRAnewlyagainduringADconversion.
BeforesettingADCCRAnewlyagain,checkADCDRLtoseethattheconversioniscompletedorwaituntiltheinterruptsignal(INTADC)isgenerated(e.
g.
,interrupthandlingroutine).
Note6:AfterSTOPmodeisstarted,ADconvertercontrolregister1(ADCCRA)isallinitializedandnodatacanbewritteninthisregister.
Therfore,touseADconverteragain,settheADCCRAnewlyafterreturningtoNORMALmode.
Note7:AfterRESET,ADCCRAisinitializedReservedsetting.
Therfore,settheappropriateanaloginputchanneltoADC-CRAwhenuseADconverter.
Note8:AfterADCCRAissetto00H,ADconversioncannotbestartedforfourcycles.
Thus,fourNOPsmustbeinsertedbeforesettingtheADCCRA.
ADConverterControlRegister1ADCCRA(0026H)76543210ADRSAMDAINDSSAIN(Initialvalue:00010000)ADRSADconversionstart0:1:-ADconversionstartR/WAMDADoperatingmode00:01:10:11:ADoperationdisableSoftwarestartmodeReservedRepeatmodeAINDSAnaloginputcontrol0:1:AnaloginputenableAnaloginputdisableSAINAnaloginputchannelselect0000:0001:0010:0011:0100:0101:0110:0111:1000:1001:1010:1011:1100:1101:1110:1111:AIN0AIN1AIN2AIN3AIN4AIN5AIN6AIN7AIN8AIN9AIN10AIN11AIN12AIN13AIN14AIN15Page185TMP88CS42NGNote1:Alwayssetbit0inADCCRBto"0"andsetbit4inADCCRBto"1".
Note2:WhenareadinstructionforADCCRB,bit6to7inADCCRBreadinasundefineddata.
Note3:AfterSTOPmodeisstarted,ADconvertercontrolregister2(ADCCRB)isallinitializedandnodatacanbewritteninthisregister.
Therfore,touseADconverteragain,settheADCCRBnewlyafterreturningtoNORMALmode.
Note1:Settingfor""intheabovetableareinhibited.
fc:HighFrequencyoscillationclock[Hz]Note2:SetconversiontimesettingshouldbekeptmorethanthefollowingtimebyAnalogreferencevoltage(VAREF).
ADConverterControlRegister2ADCCRB(0027H)76543210IREFON"1"ACK"0"(Initialvalue:**0*000*)IREFONDAconverter(Ladderresistor)connectioncontrol0:1:ConnectedonlyduringADconversionAlwaysconnectedR/WACKADconversiontimeselect(Refertothefollowingtableaboutthecon-versiontime)000:001:010:011:100:101:110:111:39/fcReserved78/fc156/fc312/fc624/fc1248/fcReservedTable16-1ACKsettingandConversiontime(atCGCR="0")ConditionConversiontime20MHz16MHz8MHzACK00039/fc---001Reserved01078/fc---011156/fc--19.
5μs100312/fc15.
6μs19.
5μs39.
0μs101624/fc31.
2μs39.
0μs78.
0μs1101248/fc62.
4μs78.
0μs156.
0μs111ReservedTable16-2ACKsettingandConversiontime(atCGCR="1")ConditionConversiontime20MHz16MHz8MHzACK00039/fc---001Reserved01078/fc---011156/fc--19.
5μs100312/fc15.
6μs19.
5μs39.
0μs101624/fc31.
2μs39.
0μs78.
0μs1101248/fc62.
4μs78.
0μs156.
0μs111Reserved-VAREF=4.
5to5.
5V15.
6μsandmorePage18616.
10-bitADConverter(ADC)16.
2RegisterconfigurationTMP88CS42NGNote1:TheADCDRLisclearedto"0"whenreadingtheADCDRH.
Therfore,theADconversionresultshouldbereadtoADCDRLmorefirstthanADCDRH.
Note2:TheADCDRLissetto"1"whenADconversionstarts,andclearedto"0"whenADconversionfinished.
ItalsoiscleareduponenteringSTOPmode.
Note3:IfareadinstructionisexecutedforADCDRL,readdataofbit3tobit0areunstable.
ADConvertedvalueRegister1ADCDRH(0029H)76543210AD09AD08AD07AD06AD05AD04AD03AD02(Initialvalue:00000000)ADConvertedvalueRegister2ADCDRL(0028H)76543210AD01AD00EOCFADBF(Initialvalue:0000****)EOCFADconversionendflag0:1:BeforeorduringconversionConversioncompletedReadonlyADBFADconversionBUSYflag0:1:DuringstopofADconversionDuringADconversionPage187TMP88CS42NG16.
3Function16.
3.
1SoftwareStartModeAftersettingADCCRAto"01"(softwarestartmode),setADCCRAto"1".
ADconver-sionofthevoltageattheanaloginputpinspecifiedbyADCCRAistherebystarted.
AftercompletionoftheADconversion,theconversionresultisstoredinADconvertedvalueregisters(ADCDRH,ADCDRL)andatthesametimeADCDRLissetto1,theADconversionfinishedinter-rupt(INTADC)isgenerated.
ADRSisautomaticallyclearedafterADconversionhasstarted.
DonotsetADCCRAnewlyagain(Restart)duringADconversion.
BeforesettingADCCRAnewlyagain,checkADCDRLtoseethattheconversioniscompletedorwaituntiltheinterruptsignal(INTADC)isgenerated(e.
g.
,interrupthandlingroutine).
Figure16-2SoftwareStartMode16.
3.
2RepeatModeADconversionofthevoltageattheanaloginputpinspecifiedbyADCCRAisperformedrepeat-edly.
Inthismode,ADconversionisstartedbysettingADCCRAto"1"aftersettingADC-CRAto"11"(Repeatmode).
AftercompletionoftheADconversion,theconversionresultisstoredinADconvertedvalueregisters(ADCDRH,ADCDRL)andatthesametimeADCDRLissetto1,theADconversionfinishedinter-rupt(INTADC)isgenerated.
Inrepeatmode,eachtimeoneADconversioniscompleted,thenextADconversionisstarted.
TostopADconversion,setADCCRAto"00"(Disablemode)bywriting0s.
TheADconvertoperationisstoppedimmediately.
TheconvertedvalueatthistimeisnotstoredintheADconvertedvalueregister.
ADCDRHstatusEOCFclearedbyreadingconversionresultConversionresultreadADCDRLINTADCinterruptrequestADCDRLADCCRA1stconversionresult2ndconversionresultIndeterminateADconversionstartADconversionstartADCDRHADCDRLConversionresultreadConversionresultreadConversionresultreadPage18816.
10-bitADConverter(ADC)16.
3FunctionTMP88CS42NGFigure16-3RepeatMode16.
3.
3RegisterSetting1.
SetuptheADconvertercontrolregister1(ADCCRA)asfollows:ChoosethechanneltoADconvertusingADinputchannelselect(SAIN).
Specifyanaloginputenableforanaloginputcontrol(AINDS).
SpecifyAMDfortheADconvertercontroloperationmode(softwareorrepeatmode).
2.
SetuptheADconvertercontrolregister2(ADCCRB)asfollows:SettheADconversiontimeusingADconversiontime(ACK).
Fordetailsonhowtosetthecon-versiontime,refertoFigure16-1,Figure16-2andADconvertercontrolregister2.
ChooseIREFONforDAconvertercontrol.
3.
Aftersettingup(1)and(2)above,setADconversionstart(ADRS)ofADconvertercontrolregister1(ADCCRA)to"1".
Ifsoftwarestartmodehasbeenselected,ADconversionstartsimmediately.
4.
AfteranelapseofthespecifiedADconversiontime,theADconvertedvalueisstoredinADcon-vertedvalueregister1(ADCDRH)andtheADconversionfinishedflag(EOCF)ofADconvertedvalueregister2(ADCDRL)issetto"1",uponwhichtimeADconversioninterruptINTADCisgen-erated.
5.
EOCFisclearedto"0"byareadoftheconversionresult.
However,ifreconvertedbeforearegisterread,althoughEOCFisclearedthepreviousconversionresultisretaineduntilthenextconversioniscompleted.
ADCDRH,ADCDRLEOCFclearedbyreadingconversionresultConversionresultreadADCDRLINTADCinterruptrequestConversionoperationADCCRAIndeterminateADconversionstartADCCRA"11""00"1stconversionresultADconvertoperationsuspended.
Conversionresultisnotstored.
2ndconversionresult3rdconversionresultADCDRHADCDRL2ndconversionresult3rdconversionresult1stconversionresultConversionresultreadConversionresultreadConversionresultreadConversionresultreadConversionresultreadPage189TMP88CS42NG16.
4STOPmodeduringADConversionWhenstandbymode(STOPmode)isenteredforciblyduringADconversion,theADconvertoperationissus-pendedandtheADconverterisinitialized(ADCCRAandADCCRBareinitializedtoinitialvalue).
Also,thecon-versionresultisindeterminate.
(Conversionresultsuptothepreviousoperationarecleared,sobesuretoreadtheconversionresultsbeforeenteringstandbymode(STOPmode).
)Whenrestoredfromstandbymode(STOPmode),ADconversionisnotautomaticallyrestarted,soitisnecessarytorestartADconversion.
Notethatsincetheanalogreferencevoltageisautomaticallydisconnected,thereisnopossibilityofcurrentflowingintotheanalogreferencevoltage.
Example:Afterselectingtheconversiontime15.
6μsat20MHzandtheanaloginputchannelAIN4pin,performADcon-versiononce.
AftercheckingEOCF,readtheconvertedvalue,storethelower2bitsinaddress0009EHandstoretheupper8bitsinaddress0009FHinRAM.
Theoperationmodeissoftwarestartmode.
:(portsetting):;SetportregisterapprorriatelybeforesettingADconverterregisters.
::(RefertosectionI/Oportindetails)LD(ADCCRA),00100100B;SelectSoftwarestartmode,Analoginputenable,andAIN4LD(ADCCRB),00011000B;Selectconversiontime(312/fc)andoperationmodeSET(ADCCRA).
7;ADRS=1(ADconversionstart)SLOOP:TEST(ADCDRB).
5;EOCF=1JRST,SLOOPLDA,(ADCDRL);ReadresultdataLD(9EH),ALDA,(ADCDRH);ReadresultdataLD(9FH),APage19016.
10-bitADConverter(ADC)16.
5AnalogInputVoltageandADConversionResultTMP88CS42NG16.
5AnalogInputVoltageandADConversionResultTheanaloginputvoltageiscorrespondedtothe10-bitdigitalvalueconvertedbytheADasshowninFigure16-4.
Figure16-4AnalogInputVoltageandADConversionResult(Typ.
)1001H02H03H3FDH3FEH3FFH231021102210231024Analoginputvoltage1024ADconversionresultVAREFAVSSPage191TMP88CS42NG16.
6PrecautionsaboutADConverter16.
6.
1AnaloginputpinvoltagerangeMakesuretheanaloginputpins(AIN0toAIN15)areusedatvoltageswithinVAREFtoAVSS.
Ifanyvolt-ageoutsidethisrangeisappliedtooneoftheanaloginputpins,theconvertedvalueonthatpinbecomesuncer-tain.
Theotheranaloginputpinsalsoareaffectedbythat.
16.
6.
2AnaloginputsharedpinsTheanaloginputpins(AIN0toAIN15)aresharedwithinput/outputports.
WhenusinganyoftheanaloginputstoexecuteADconversion,donotexecuteinput/outputinstructionsforallotherports.
ThisisnecessarytopreventtheaccuracyofADconversionfromdegrading.
Notonlytheseanaloginputsharedpins,someotherpinsmayalsobeaffectedbynoisearisingfrominput/outputtoandfromadjacentpins.
16.
6.
3NoiseCountermeasureTheinternalequivalentcircuitoftheanaloginputpinsisshowninFigure16-5.
Thehighertheoutputimpedanceoftheanaloginputsource,moreeasilytheyaresusceptibletonoise.
Therefore,makesuretheout-putimpedanceofthesignalsourceinyourdesignis5kΩorless.
Toshibaalsorecommendsattachingacapac-itorexternaltothechip.
Figure16-5AnalogInputEquivalentCircuitandExampleofInputPinProcessingDAconverterAINiAnalogcomparatorInternalresistancePermissiblesignalsourceimpedanceInternalcapacitance5kΩ(typ)C=22pF(typ.
)5kΩ(max)Note)i=15to0Page19216.
10-bitADConverter(ADC)16.
6PrecautionsaboutADConverterTMP88CS42NGPage193TMP88CS42NG17.
8-BitHigh-speedPWM(HPWM0andHPWM1)TheTMP88CS42NGcontainstwo-channelsofhigh-speedPWM.
Thehigh-speedPWMworksinsuchawaythatwhendataarewrittentothedataregistersfortherespectivechannels,waveformsdifferingfromeachothercanbeoutput.
Thehigh-speedPWMissharedwithports,P02(HPWM0)andP03(HPWM1).
Whenusingthesepinsforhigh-speedPWM,settheportoutputlatchesforP02andP03to1.
17.
1ConfigurationFigure17-1High-speedPWM(HPWM0andHPWM1)AdditionalPulseGeneratorcircuitfcHPE0ComparatorHPE1HPE1HPE0HPWM0HPWM18-bitupcounterHPWMCRHPWMDR0HPWMDR1X1PWMSTPWMMODHight-speedPWMcontrolregisterDataregisterDataregisterHPWM1sectionHPWM0sectionPage19417.
8-BitHigh-speedPWM(HPWM0andHPWM1)17.
2ControlTMP88CS42NG17.
2ControlNote1:ThePWMoutputpulsewidthvarieswiththeclockdutycycle.
Note2:Forthedataregisters,setdata10HtoF0H.
Note3:WhenHPWMCR=0,theinternalcounterisclearedanddata"1"isoutputtotheport.
Note4:BeforeselectingPWMmode,makesureHPWMCR=0.
Note5:BeforeenteringSTOPmode,setHPWMCRallto0.
Note6:IfHPWMCRisalteredinthemiddleofPWMperiod,thewaveformmaybedistorted.
Toavoidwaveformdistortion,makesureHPWMCR=0whenenablingHPWMoutput.
17.
3FunctionalDescriptionThehigh-speedPWMiscontrolledusingtheControlRegister(HPWMCR)andDataRegisters(HPWMDR0,1).
Beforewritingtotheseregisters,settheHPWMCR=1tomakethemreadyforsetup.
WhentheHPW-MCRissetto0,eachcontrolregisterisreset,sothatthehigh-speedPWMcanberesetinsoftware.
17.
3.
1OperationmodesThehigh-speedPWMhasthefollowingthreemodesofoperation:8-bitmode:(T=28*clockperiod,f≈78kHz)7-bitmode:(T=27*clockperiod,f≈156kHz)6-bitmode:(T=26*clockperiod,f≈313kHz)Note:Thesevaluesapplytothecasewherethesourceclock(X1)is20MHz.
UsetheHPWMCRtoselectoperationmode.
Notethatoperationmodeiscommontobothchannels,andcannotbesetseparatelyforeachchannel.
ControlRegisterHPWMCR(000CH)76543210HPE1HPE0PWMSTPWMMODR/W(Initialvalue:00**0*00)PWMMODSelectPWMmode00:Mode0(8bits)01:Mode1(7bits)10:Mode2(6bits)11:ReservedR/WPWMSTRun/stop8-bitupcounter0:STOP1:RUNHPE0ControlHPWM0output0:Disable1:EnableHPE1ControlHPWM1output0:Disable1:EnableDataRegisterHPWMDR0(000DH)76543210DATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0R/W(Initialvalue:HPWMDR1(000EH)76543210DATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0R/W(Initialvalue:Page195TMP88CS42NG17.
3.
1.
18-bitmodeIn8-bitmode,itispossibletogenerateapulsewith12.
8μsperiodandapproximately78kHzfrequency(whenX1=20MHz).
Theminimumwidthofthepulseis0.
8μs(data"10"),andthemaximumwidthofthepulseis12.
0μs(data"F0").
Pulsewidth=8-bitdata*50nsFigure17-2showsatypicalwaveformin8-bitmode.
(ThevaluesareforX1=20MHz.
)Figure17-28-BitMode17.
3.
1.
27-bitmodeIn7-bitmode,itispossibletogenerateapulsewith6.
4μsperiodandapproximately156kHzfrequency(whenX1=20MHz).
In7-bitmode,theperiodiscomprisedof7bits(period=27*50ns)andoneotherbitprovidesa25nsresolution(halfperiodofthesourceclock(X1)).
Therefore,whentheonelow-orderbit=1,aplus-25nspulseisoutput.
Theminimumwidthofthepulseis0.
4μs(data"10"),andthemaximumwidthofthepulseis6.
0μs(data"F0":"78"+"0").
Pulsewidth=(7high-orderBitsofdata*50ns)+(1low-orderBitofdata*25ns)Figure17-3showsatypicalwaveformin7-bitmode.
(ThevaluesareforX1=20MHz.
)Dataregister8-bitdata12.
8μs12.
8μsDataregistervalue*50nsDataregistervalue*50ns70Data"10h""11h""F0h"12.
8s12.
8s800ns800ns850ns850ns12.
0s12.
0s6.
4μs6.
4μsValueof7high-orderbits*50nsValueof1low-orderbits*25nsValueof7high-orderbits*50nsDataregister7hight-orderbits1low-orderbit70Page19617.
8-BitHigh-speedPWM(HPWM0andHPWM1)17.
3FunctionalDescriptionTMP88CS42NGFigure17-37-BitModeNote:TheresolutionoftheLSB1bit(25nsec)isatypicalvalueanditsprecisionisnotguaranteed.
17.
3.
1.
36-bitmodeIn6-bitmode,itispossibletogenerateapulsewith3.
2μsperiodandapproximately313kHzfrequency(whenX1=20MHz).
In6-bitmode,theperiodiscomprisedof6bits(period=26*50ns)andtwootherbitsprovidea12.
5nsresolution.
However,becausetheactuallyobtainedresolutionis25ns,saidresolutionisaccomplishedartificially.
Toobtaina12.
5nsresolution,thefirst,second,andthirdpulsesareoutputbyadding25ns,0ns,and25ns,respectively.
Inthisway,a12.
5nsresolutionisrealizedasbeing"equivalentto.
"Theminimumequivalentwidthofthepulseis0.
2μs(data"10"),andthemaximumequivalentwidthofthepulseis3.
0μs(data"F0":"3B"+"0").
Pulsewidth=(6high-orderbitsofdata*50ns)+(2low-orderbitsofdata*)*Theequivalentplustimesin2low-orderbitsofdataareshownbelow.
Figure17-4Showsatypicalwaveformin6-bitmode.
(ThevaluesareforX1=20MHz.
)2-bitdataEquivalentplustime000ns0112.
5ns1025ns1137.
5nsData"10h""11h""F0h"6.
4s6.
4s400ns400ns425ns425ns6.
000s6.
000s3.
2μs3.
2μs6high-orderbits*50nsVarieswithvalueof2low-orderbits6high-orderbits*50nsDataregister6high-orderbits2low-orderbits70Page197TMP88CS42NGFigure17-46-BitModeNote:TheresolutionoftheLSB2bit(12.
5nsec)isatypicalvalueanditsprecisionisnotguaranteed.
17.
3.
2SettingoutputdataTosetoutputdata,writeittotheDataRegisters(HPWMDR0and1).
Example:Tooutputa5.
75μswaveformin7-bitmodeusingHPWM0whenthesourceclock(X1)=20MHzBecausetheresolutionin7-bitmodeis50ns,tooutputa5.
75μspulse5.
75μs÷50ns=115=73HBecause73Hisplacedinthe7high-orderbits,thevalueisshiftedonebittobecomeE6H.
Therefore,setE6HintheDataRegister(HPWMDR0).
Data"12h""13h""F0h"3.
2s3.
2s3.
2s225ns225ns"11h"225ns225ns225ns250ns225ns250ns250ns"14h"250ns250ns3.
0s3.
0s3.
0s200ns6.
4μs5.
75μsPage19817.
8-BitHigh-speedPWM(HPWM0andHPWM1)17.
3FunctionalDescriptionTMP88CS42NGPage199TMP88CS42NG18.
Input/OutputCircuitry18.
1ControlpinsTheinput/outputcircuitriesoftheTMP88CS42NGcontrolpinsareshownbelow.
Note:TheTESTpinofTMP88PS42doesnothaveapull-downresistor(RIN)andprotectdiode(D1).
FixtheTESTpinat"L"levelinMCUmode.
ControlPinI/OInput/OutputCircuitryRemarkXINXOUTInputOutputHigh-frequencyresonatorconnectingpinsRf=1.
2MΩ(typ.
)RO=0.
5kΩ(typ.
)RESETInputHysteresisinputPull-upresistorincludedRIN=220kΩ(typ.
)TESTInputPull-downresistorincludedRIN=70kΩ(typ.
)FixtheTESTpinat"L"levelinMCUmode.
fcRfROOsc.
enableXINXOUTVDDVDDRINVDDVDDD1RINPage20018.
Input/OutputCircuitry18.
2Input/outputportsTMP88CS42NG18.
2Input/outputportsPortTypeInput/outputCircuitRemarkP0P3P4P5I/OTri-stateoutputProgrammableopen-drainP3,P4,P5:Large-currentportHysteresisinputP6P7I/OTri-stateoutputP1I/OTri-stateoutputHysteresisinputP2I/OOpen-drainoutputHysteresisinputInitial"High-Z"DisableOutputcontrolDataoutputPininputInitial"High-Z"DisableDataoutputPininputInitial"High-Z"DisableDataoutputPininputInitial"High-Z"DataoutputPininputPage201TMP88CS42NG19.
ElectricalCharacteristics19.
1AbsoluteMaximumRatingsTheAbsoluteMaximumRatingsstipulatethestandards,anyparameterofwhichcannotbeexceededeveninaninstant.
IfthedeviceisusedunderconditionsexceedingtheAbsoluteMaximumRatings,itmaybreakdownordegrade,causinginjuryduetoruptureorburning.
Therefore,alwaysmakesuretheAbsoluteMaximumRatingswillnotbeexceededwhendesigningyourapplicationequipment.
(VSS=0V)ParameterSymbolPinsStandardUnitRemarkPowersupplyvoltageVDD0.
3to6.
5VInputvoltageVIN0.
3toVDD+0.
3OutputvoltageVOUT0.
3toVDD+0.
3OutputcurrentIOHP0,P1,P3,P4,P5,P6,P71.
8mAIOL1P0,P1,P2,P6,P73.
2IOL2P3,P4,P530MeanoutputcurrentΣIOUT1P0,P1,P2,P6,P760Totalofallportsexceptlarge-currentportsΣIOUT2P360Totalof8pinsoflarge-currentportsP30to7ΣIOUT3P460Totalof8pinsoflarge-currentportsP40to7ΣIOUT4P560Totalof8pinsoflarge-currentportsP50to7PowerdissipationPDTMP88CS42NG600mWSDIPOperatingtemperatureTopr40to85°CSolderingtemperature(time)Tsld260(10s)StoragetemperatureTstg55to125Page20219.
ElectricalCharacteristics19.
3DCCharacteristicsTMP88CS42NG19.
2OperatingConditionsTheOperatingConditionsshowtheconditionsunderwhichthedevicebeusedinorderforittooperatenormallywhilemaintainingitsquality.
IfthedeviceisusedoutsidetherangeofOperatingConditions(powersupplyvoltage,operatingtemperaturerange,orAC/DCratedvalues),itmayoperateerratically.
Therefore,whendesigningyourapplicationequipment,alwaysmakesureitsintendedworkingconditionswillnotexceedtherangeofOperatingConditions.
19.
3DCCharacteristicsNote1:TypicalvaluesshowthoseatTopr=25°C,VDD=5V.
Note2:Inputcurrent(IIN1,IIN3);Thecurrentthroughpull-uporpull-downresistorisnotincluded.
Note3:IDDdoesnotincludeIREFcurrent.
(VSS=0V,Topr=40to85°C)ParameterSymbolPinsConditionMinMaxUnitPowersupplyvoltageVDDfc=20MHzNORMAL/IDLE/STOP4.
55.
5VHighlevelinputvoltageVIH1Normal(P6,P7)VDD≥4.
5VVDD*0.
70VDDVVIH2Hysteresis(P0,P1,P2,P3,P4,P5,RESET)VDD*0.
75LowlevelinputvoltageVIL1Normal(P6,P7)VDD≥4.
5V0VDD*0.
30VIL2Hysteresis(P0,P1,P2,P3,P4,P5,RESET)VDD*0.
25ClockfrequencyfcXIN,XOUTVDD=4.
5Vto5.
5V820MHz(VSS=0V,Topr=40to85°C)ParameterSymbolPinsConditionMinTyp.
MaxUnitInputcurrentIIN1TESTVDD=5.
5V,VIN=5.
5V/0V––±2μAIIN2Sinkopendrain,Tri-stateIIN3RESET,STOPInputResistanceRIN1TEST-70-kΩRIN2RESET90220510OutputleakagecurrentILOSinkopendrain,Tri-stateVDD=5.
5V,VIN=5.
5V/0V––±2μAHighleveloutputvoltageVOHTri-stateportVDD=4.
5V,IOH=0.
7mA4.
1––VLowleveloutputvoltageIOL1P0,P1,P2,P6,P7VDD=4.
5V,VOL=0.
4V1.
6––mAIOL2P3,P4,P5VDD=4.
5V,VOL=1.
0V–20–NORMALmodepowersupplycurrentIDDVDD=5.
5V,VIN=5.
3V/0.
2Vfc=20MHz–1825IDLEmodepowersupplycurrent–1623STOPmodepowersupplycurrent–2100μAPage203TMP88CS42NG19.
4ADConversionCharacteristicsNote1:Thetotalerrorincludesallerrorsexceptaquantizationerror,andisdefinedasamaximumdeviationfromtheideaconversionline.
Note2:Conversiontimeisdifferentinrecommendedvaluebypowersupplyvoltage.
Aboutconversiontime,pleasereferto"RegisterConfiguration"inthesectionofADconverter.
Note3:PleaseuseinputvoltagetoAINinputpininlimitofVAREF-VSS.
Whenvoltageorrangeoutsideisinput,conversionvaluebecomesunsettledandgivesaffecttootherchannelconversionvalue.
Note4:Analogreferencevoltagerange;ΔVAREF=VAREF-VSS19.
5ACCharacteristics(Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnit8bit10bitAnalogreferencevoltageVAREFVSS=0V,VDD=AVDDVDD1.
0–VDDVAnaloginputvoltagerangeVAINVASS–VAREFAnalogreferencepowersupplycurrentIREFVDD=AVDD=VAREF=5.
0VVSS=AVSS=0V–0.
51.
0mANonlinearityerrorVDD=5V,VSS=0VAVDD=VAREF=5VAVSS=0V––±1±2LSBZeroerror––±1±2Fullscaleerror––±1±2Overallerror––±2±4(VSS=0V,VDD=4.
5to5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitMachinecycletimetcyDuringNORMALmode0.
2–0.
5μsDuringIDLEmodeHighlevelclockpulsewidthtWCHWhenoperatingwithexternalclock(XINinput)fc=20MHz–25–nsLowlevelclockpulsewidthtWCLPage20419.
ElectricalCharacteristics19.
7HandlingPrecautionTMP88CS42NG19.
6RecommendedOscillationConditionsNote1:Toensurestableoscillation,theresonatorposition,loadcapacitance,etc.
mustbeappropriate.
Becausethesefactorsaregreatlyaffectedbyboardpatterns,pleasebesuretoevaluateoperationontheboardonwhichthedevicewillactuallybemounted.
Note2:FortheresonatorstobeusedwithToshibamicrocontrollers,werecommendceramicresonatorsmanufacturedbyMurataManufacturingCo.
,Ltd.
Fordetails,pleasevisitthewebsiteofMurataatthefollowingURL:http://www.
murata.
com19.
7HandlingPrecaution-Thesolderabilitytestconditionsforlead-freeproducts(indicatedbythesuffixGinproductname)areshownbelow.
1.
WhenusingtheSn-37PbsolderbathSolderbathtemperature=230°CDippingtime=5secondsNumberoftimes=onceR-typefluxused2.
WhenusingtheSn-3.
0Ag-0.
5CusolderbathSolderbathtemperature=245°CDippingtime=5secondsNumberoftimes=onceR-typefluxusedNote:Thepasscriteronoftheabovetestisasfollows:Solderabilityrateuntilforming≥95%-Whenusingthedevice(oscillator)inplacesexposedtohighelectricfieldssuchascathode-raytubes,werecommendelec-tricallyshieldingthepackageinordertomaintainnormaloperatingcondition.
High-frequencyoscillationXINXOUTC2C1Page205TMP88CS42NG20.
PackageDimensionsSDIP64-P-750-1.
78Rev01Unit:mmPage20620.
PackageDimensionsTMP88CS42NGThisisatechnicaldocumentthatdescribestheoperatingfunctionsandelectricalspecificationsofthe8-bitmicrocontrollerseriesTLCS-870/X(LSI).
Toshibaprovidesavarietyofdevelopmenttoolsandbasicsoftwaretoenableefficientsoftwaredevelopment.
Thesedevelopmenttoolshavespecificationsthatsupportadvancesinmicrocomputerhardware(LSI)andcanbeusedextensively.
Boththehardwareandsoftwarearesupportedcontinuouslywithversionupdates.
TherecentadvancesinCMOSLSIproductiontechnologyhavebeenphenomenalandmicrocomputersystemsforLSIdesignareconstantlybeingimproved.
Theproductsdescribedinthisdocumentmayalsoberevisedinthefuture.
Besuretocheckthelatestspecificationsbeforeusing.
Toshibaisdevelopinghighlyintegrated,high-performancemicrocomputersusingadvancedMOSproductiontechnologyandespeciallywellprovenCMOStechnology.
Wearepreparedtomeettherequestsforcustompackagingforavarietyofapplicationareas.
Weareconfidentthatourproductscansatisfyyourapplicationneedsnowandinthefuture.