SYSCKncsetting

8BitMicrocontrollerTLCS-870/CSeriesTMP86FS23UGPage2TMP86FS23UGTheinformationcontainedhereinissubjecttochangewithoutnotice.
021023_DTOSHIBAiscontinuallyworkingtoimprovethequalityandreliabilityofitsproducts.
Nevertheless,semiconductordevicesingeneralcanmalfunctionorfailduetotheirinherentelectricalsensitivityandvulnerabilitytophysicalstress.
Itistheresponsibilityofthebuyer,whenutilizingTOSHIBAproducts,tocomplywiththestandardsofsafetyinmakingasafedesignfortheentiresystem,andtoavoidsituationsinwhichamalfunctionorfailureofsuchTOSHIBAproductscouldcauselossofhumanlife,bodilyinjuryordamagetoproperty.
Indevelopingyourdesigns,pleaseensurethatTOSHIBAproductsareusedwithinspecifiedoperatingrangesassetforthinthemostrecentTOSHIBAproductsspecifications.
Also,pleasekeepinmindtheprecautionsandconditionssetforthinthe"HandlingGuideforSemiconductorDevices,"or"TOSHIBASemiconductorReliabilityHandbook"etc.
021023_ATheToshibaproductslistedinthisdocumentareintendedforusageingeneralelectronicsapplications(computer,personalequipment,officeequipment,measuringequipment,industrialrobotics,domesticappliances,etc.
).
TheseToshibaproductsareneitherintendednorwarrantedforusageinequipmentthatrequiresextraordinarilyhighqualityand/orreliabilityoramalfunctionorfailureofwhichmaycauselossofhumanlifeorbodilyinjury("UnintendedUsage").
UnintendedUsageincludeatomicenergycontrolinstruments,airplaneorspaceshipinstruments,transportationinstruments,trafficsignalinstruments,combustioncontrolinstruments,medicalinstruments,alltypesofsafetydevices,etc.
UnintendedUsageofToshibaproductslistedinthisdocumentshallbemadeatthecustomer'sownrisk.
021023_BTheproductsdescribedinthisdocumentshallnotbeusedorembeddedtoanydownstreamproductsofwhichmanufacture,useand/orsaleareprohibitedunderanyapplicablelawsandregulations.
060106_QTheinformationcontainedhereinispresentedonlyasaguidefortheapplicationsofourproducts.
NoresponsibilityisassumedbyTOSHIBAforanyinfringementsofpatentsorotherrightsofthethirdpartieswhichmayresultfromitsuse.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofTOSHIBAorothers.
021023_CTheproductsdescribedinthisdocumentmayincludeproductssubjecttotheforeignexchangeandforeigntradelaws.
021023_FForadiscussionofhowthereliabilityofmicrocontrollerscanbepredicted,pleaserefertoSection1.
3ofthechapterentitledQualityandReliabilityAssurance/HandlingPrecautions.
030619_S2006TOSHIBACORPORATIONAllRightsReservedRevisionHistoryDateRevision2005/9/121FirstRelease2005/12/82ContentsRevised2006/8/283ContentsRevised2008/8/294ContentsRevisedCautioninSettingtheUARTNoiseRejectionTimeWhenUARTisused,settingsofRXDNCarelimiteddependingonthetransferclockspecifiedbyBRG.
Thecom-bination"O"isavailablebutpleasedonotselectthecombination"–".
Thetransferclockgeneratedbytimer/counterinterruptiscalculatedbythefollowingequation:Transferclock[Hz]=Timer/countersourceclock[Hz]÷TTREGsetvalueBRGsettingTransferclock[Hz]RXDNCsetting00(Nonoiserejection)01(Rejectpulsesshorterthan31/fc[s]asnoise)10(Rejectpulsesshorterthan63/fc[s]asnoise)11(Rejectpulsesshorterthan127/fc[s]asnoise)000fc/13OOO–110(Whenthetransferclockgen-eratedbytimer/counterinter-ruptisthesameastherightsidecolumn)fc/8O–––fc/16OO––fc/32OOO–ThesettingexcepttheaboveOOOOiTableofContentsTMP86FS23UG1.
1Features11.
2PinAssignment31.
3BlockDiagram41.
4PinNamesandFunctions52.
OperationalDescription2.
1CPUCoreFunctions92.
1.
1MemoryAddressMap.
92.
1.
2ProgramMemory(Flash)92.
1.
3DataMemory(RAM)92.
2SystemClockController102.
2.
1ClockGenerator.
102.
2.
2TimingGenerator.
122.
2.
2.
1Configurationoftiminggenerator2.
2.
2.
2Machinecycle2.
2.
3OperationModeControlCircuit132.
2.
3.
1Single-clockmode2.
2.
3.
2Dual-clockmode2.
2.
3.
3STOPmode2.
2.
4OperatingModeControl182.
2.
4.
1STOPmode2.
2.
4.
2IDLE1/2modeandSLEEP1/2mode2.
2.
4.
3IDLE0andSLEEP0modes(IDLE0,SLEEP0)2.
2.
4.
4SLOWmode2.
3ResetCircuit312.
3.
1ExternalResetInput312.
3.
2Addresstrapreset322.
3.
3Watchdogtimerreset.
322.
3.
4Systemclockreset.
323.
InterruptControlCircuit3.
1Interruptlatches(IL19toIL2)353.
2Interruptenableregister(EIR)363.
2.
1Interruptmasterenableflag(IMF)363.
2.
2Individualinterruptenableflags(EF19toEF4)37Note3:383.
3InterruptSequence393.
3.
1Interruptacceptanceprocessingispackagedasfollows.
393.
3.
2Saving/restoringgeneral-purposeregisters.
403.
3.
2.
1UsingPUSHandPOPinstructions3.
3.
2.
2Usingdatatransferinstructions3.
3.
3Interruptreturn413.
4SoftwareInterrupt(INTSW)423.
4.
1Addresserrordetection423.
4.
2Debugging42ii3.
5UndefinedInstructionInterrupt(INTUNDEF)423.
6AddressTrapInterrupt(INTATRAP)423.
7ExternalInterrupts434.
SpecialFunctionRegister(SFR)4.
1SFR454.
2DBR475.
I/OPorts5.
1PortP1(P17toP10)525.
2PortP2(P22toP20)545.
3PortP3(P37toP30)555.
4PortP5(P57toP50)575.
5PortP6(P67toP60)595.
6PortP7(P77toP70)625.
7PortP8(P87toP80)646.
TimeBaseTimer(TBT)6.
1TimeBaseTimer676.
1.
1Configuration676.
1.
2Control676.
1.
3Function686.
2DividerOutput(DVO)696.
2.
1Configuration696.
2.
2Control697.
WatchdogTimer(WDT)7.
1WatchdogTimerConfiguration717.
2WatchdogTimerControl727.
2.
1MalfunctionDetectionMethodsUsingtheWatchdogTimer.
727.
2.
2WatchdogTimerEnable737.
2.
3WatchdogTimerDisable747.
2.
4WatchdogTimerInterrupt(INTWDT)747.
2.
5WatchdogTimerReset757.
3AddressTrap767.
3.
1SelectionofAddressTrapinInternalRAM(ATAS)767.
3.
2SelectionofOperationatAddressTrap(ATOUT)767.
3.
3AddressTrapInterrupt(INTATRAP)767.
3.
4AddressTrapReset.
778.
18-BitTimer/Counter(TC1)8.
1Configuration798.
2Control808.
3Function.
83iii8.
3.
1Timermode.
838.
3.
2EventCountermode.
848.
3.
3PulseWidthMeasurementmode.
858.
3.
4FrequencyMeasurementmode.
869.
8-BitTimerCounter(TC3,TC4)9.
1Configuration899.
2TimerCounterControl909.
3Function.
959.
3.
18-BitTimerMode(TC3and4)959.
3.
28-BitEventCounterMode(TC3,4)969.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC3,4)969.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC3,4)999.
3.
516-BitTimerMode(TC3and4)1019.
3.
616-BitEventCounterMode(TC3and4)1029.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC3and4)1029.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC3and4)1059.
3.
9Warm-UpCounterMode.
1079.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)9.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)10.
8-BitTimerCounter(TC5,TC6)10.
1Configuration10910.
2TimerCounterControl11010.
3Function.
11510.
3.
18-BitTimerMode(TC5and6)11510.
3.
28-BitEventCounterMode(TC5,6)11610.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC5,6)11610.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC5,6)11910.
3.
516-BitTimerMode(TC5and6)12110.
3.
616-BitEventCounterMode(TC5and6)12210.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC5and6)12210.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC5and6)12510.
3.
9Warm-UpCounterMode.
12710.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)10.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)11.
AsynchronousSerialinterface(UART)11.
1Configuration12911.
2Control13011.
3TransferDataFormat13211.
4TransferRate.
13311.
5DataSamplingMethod13311.
6STOPBitLength13411.
7Parity13411.
8Transmit/ReceiveOperation13411.
8.
1DataTransmitOperation13411.
8.
2DataReceiveOperation13411.
9StatusFlag135iv11.
9.
1ParityError.
13511.
9.
2FramingError.
13511.
9.
3OverrunError.
13511.
9.
4ReceiveDataBufferFull.
13611.
9.
5TransmitDataBufferEmpty13611.
9.
6TransmitEndFlag13712.
SynchronousSerialInterface(SIO)12.
1Configuration13912.
2Control14012.
3Serialclock14112.
3.
1Clocksource14112.
3.
1.
1Internalclock12.
3.
1.
2Externalclock12.
3.
2Shiftedge.
14312.
3.
2.
1Leadingedge12.
3.
2.
2Trailingedge12.
4Numberofbitstotransfer14312.
5Numberofwordstotransfer14312.
6TransferMode14412.
6.
14-bitand8-bittransfermodes.
14412.
6.
24-bitand8-bitreceivemodes14612.
6.
38-bittransfer/receivemode14713.
10-bitADConverter(ADC)13.
1Configuration14913.
2Registerconfiguration15013.
3Function.
15313.
3.
1SoftwareStartMode15313.
3.
2RepeatMode15313.
3.
3RegisterSetting15413.
4STOP/SLOWModesduringADConversion15513.
5AnalogInputVoltageandADConversionResult15613.
6PrecautionsaboutADConverter.
15713.
6.
1RestrictionsforADConversioninterrupt(INTADC)usage.
15713.
6.
2Analoginputpinvoltagerange15713.
6.
3Analoginputsharedpins15713.
6.
4NoiseCountermeasure.
15714.
Key-onWakeup(KWU)14.
1Configuration15914.
2Control15914.
3Function.
15915.
LCDDriver15.
1Configuration16115.
2Control16215.
2.
1LCDdrivingmethods16315.
2.
2Framefrequency.
164v15.
2.
3LCDdrivevoltage16515.
2.
4AdjustingtheLCDpaneldrivecapability16515.
3LCDDisplayOperation16615.
3.
1Displaydatasetting16615.
3.
2Blanking16615.
4ControlMethodofLCDDriver16715.
4.
1Initialsetting.
16715.
4.
2Storeofdisplaydata16715.
4.
3ExampleofLCDdriveroutput.
16916.
Real-TimeClock16.
1Configuration17516.
2ControloftheRTC.
17516.
3Function.
17617.
Multiply-Accumulate(MAC)Unit17.
1Configuration17717.
2Registers17717.
2.
1CommandRegister.
17717.
2.
2StatusRegister17817.
2.
3MultiplierdataRegister17817.
2.
4MultiplicanddataRegister17817.
2.
5ResultRegister17817.
2.
6AddendRegister17817.
3Control17817.
4RegisterDescription18017.
4.
1EMAC18017.
4.
2CMOD.
18017.
4.
3RCLR18017.
5ArithmeticModes.
18117.
5.
1UnsignedMultiplyMode18117.
5.
2SignedMultiplyMode18117.
5.
3UnsignedMultiply-AccumulateMode18117.
5.
4SignedMultiply-AccumulateMode18217.
5.
5ValidNumericalRanges18217.
6StatusFlags.
18217.
6.
1OperationStatusFlag(CALC)18317.
6.
2OverflowFlag(OVRF)18317.
6.
3CarryFlag(CARF)18317.
6.
4SignFlag(SIGN)18317.
6.
5ZeroFlag(ZERF)18317.
7ExampleofSoftwareProcessing.
18318.
FlashMemory18.
1FlashMemoryControl18618.
1.
1FlashMemoryCommandSequenceExecutionControl(FLSCR18618.
1.
2FlashMemoryBankSelectControl(FLSCR18618.
1.
3FlashMemoryStandbyControl(FLSSTB18718.
2CommandSequence.
18818.
2.
1ByteProgram.
18818.
2.
2SectorErase(4-kbyteErase)18818.
2.
3ChipErase(AllErase)189vi18.
2.
4ProductIDEntry18918.
2.
5ProductIDExit.
18918.
2.
6ReadProtect.
18918.
3ToggleBit(D6)19018.
4AccesstotheFlashMemoryArea.
19118.
4.
1FlashMemoryControlintheSerialPROMMode.
19118.
4.
1.
1HowtowritetotheflashmemorybyexecutingthecontrolprogramintheRAMarea(intheRAMloadermodewithintheserialPROMmode)18.
4.
2FlashMemoryControlintheMCUmode.
19318.
4.
2.
1HowtowritetotheflashmemorybyexecutingauserwritecontrolprogramintheRAMarea(intheMCUmode)19.
SerialPROMMode19.
1Outline19519.
2MemoryMapping.
19519.
3SerialPROMModeSetting19619.
3.
1SerialPROMModeControlPins19619.
3.
2PinFunction.
19619.
3.
3ExampleConnectionforOn-BoardWriting.
19719.
3.
4ActivatingtheSerialPROMMode19819.
4InterfaceSpecificationsforUART19919.
5OperationCommand20119.
6OperationMode.
20119.
6.
1FlashMemoryErasingMode(Operatingcommand:F0H)20319.
6.
2FlashMemoryWritingMode(Operationcommand:30H)20519.
6.
3RAMLoaderMode(OperationCommand:60H)20819.
6.
4FlashMemorySUMOutputMode(OperationCommand:90H)21019.
6.
5ProductIDCodeOutputMode(OperationCommand:C0H)21119.
6.
6FlashMemoryStatusOutputMode(OperationCommand:C3H)21319.
6.
7FlashMemoryReadProtectionSettingMode(OperationCommand:FAH)21419.
7ErrorCode21619.
8Checksum(SUM)21619.
8.
1CalculationMethod21619.
8.
2Calculationdata21719.
9IntelHexFormat(Binary)21819.
10Passwords21819.
10.
1PasswordString.
21919.
10.
2HandlingofPasswordError.
21919.
10.
3PasswordManagementduringProgramDevelopment21919.
11ProductIDCode22019.
12FlashMemoryStatusCode22019.
13SpecifyingtheErasureArea22219.
14PortInputControlRegister22219.
15Flowchart22419.
16UARTTiming22520.
Input/OutputCircuitry20.
1ControlPins22720.
2Input/OutputPorts22821.
ElectricalCharacteristics21.
1AbsoluteMaximumRatings.
229vii21.
2RecommendedOperatingCondition23021.
2.
1WhenProgrammingFlashmemoryinMCUmode23021.
2.
2WhenNotProgrammingFlashMemoryinMCUMode.
23021.
2.
3SerialPROMmode.
23121.
3DCCharacteristics.
23221.
4ADConversionCharacteristics23421.
5ACCharacteristics.
23521.
6TimerCounter1input(ECIN)Characteristics23521.
7FlashCharacteristics23521.
7.
1Write/RetentionCharacteristics23521.
8RecommendedOscillatingConditions.
23621.
9HandlingPrecaution23622.
PackageDimensionThisisatechnicaldocumentthatdescribestheoperatingfunctionsandelectricalspecificationsofthe8-bitmicrocontrollerseriesTLCS-870/C(LSI).
viiiPage1060116EBPTMP86FS23UGCMOS8-BitMicrocontrollerTheinformationcontainedhereinissubjecttochangewithoutnotice.
021023_DTOSHIBAiscontinuallyworkingtoimprovethequalityandreliabilityofitsproducts.
Nevertheless,semiconductordevicesingeneralcanmalfunctionorfailduetotheirinherentelectricalsensitivityandvulnerabilitytophysicalstress.
Itistheresponsibilityofthebuyer,whenutilizingTOSHIBAproducts,tocomplywiththestandardsofsafetyinmakingasafedesignfortheentiresystem,andtoavoidsituationsinwhichamalfunctionorfailureofsuchTOSHIBAproductscouldcauselossofhumanlife,bodilyinjuryordamagetoproperty.
Indevelopingyourdesigns,pleaseensurethatTOSHIBAproductsareusedwithinspecifiedoperatingrangesassetforthinthemostrecentTOSHIBAproductsspecifications.
Also,pleasekeepinmindtheprecautionsandconditionssetforthinthe"HandlingGuideforSemiconductorDevices,"or"TOSHIBASemiconductorReliabilityHandbook"etc.
021023_ATheTOSHIBAproductslistedinthisdocumentareintendedforusageingeneralelectronicsapplications(computer,personalequip-ment,officeequipment,measuringequipment,industrialrobotics,domesticappliances,etc.
).
TheseTOSHIBAproductsareneitherintendednorwarrantedforusageinequipmentthatrequiresextraordinarilyhighqualityand/orreliabilityoramalfunctionorfailureofwhichmaycauselossofhumanlifeorbodilyinjury("UnintendedUsage").
UnintendedUsageincludeatomicenergycontrolinstruments,airplaneorspaceshipinstruments,transportationinstruments,trafficsignalinstruments,combustioncontrolinstruments,medicalinstru-ments,alltypesofsafetydevices,etc.
UnintendedUsageofTOSHIBAproductslistedinthisdocumentshallbemadeatthecustomer'sownrisk.
021023_BTheproductsdescribedinthisdocumentshallnotbeusedorembeddedtoanydownstreamproductsofwhichmanufacture,useand/orsaleareprohibitedunderanyapplicablelawsandregulations.
060106_QTheinformationcontainedhereinispresentedonlyasaguidefortheapplicationsofourproducts.
NoresponsibilityisassumedbyTOSHIBAforanyinfringementsofpatentsorotherrightsofthethirdpartieswhichmayresultfromitsuse.
Nolicenseisgrantedbyimpli-cationorotherwiseunderanypatentorpatentrightsofTOSHIBAorothers.
021023_CTheproductsdescribedinthisdocumentaresubjecttotheforeignexchangeandforeigntradelaws.
021023_EForadiscussionofhowthereliabilityofmicrocontrollerscanbepredicted,pleaserefertoSection1.
3ofthechapterentitledQualityandReliabilityAssurance/HandlingPrecautions.
030619_SThisproductusestheSuperFlashtechnologyunderthelicenceofSiliconStorageTechnology,Inc.
SuperFlashisregisteredtrademarkofSiliconStorageTechnology,Inc.
TMP86FS23UGTheTMP86FS23UGisasingle-chip8-bithigh-speedandhigh-functionalitymicrocomputerincorporating61440bytesofFlashMemory.
Itispin-compatiblewiththeTMP86CM23/CP23AUG(MaskROMversion).
TheTMP86FS23UGcanrealizeoperationsequivalenttothoseoftheTMP86CM23/CP23AUGbyprogrammingtheon-chipFlashMemory.
1.
1Features1.
8-bitsinglechipmicrocomputerTLCS-870/Cseries-Instructionexecutiontime:0.
25s(at16MHz)122s(at32.
768kHz)-132types&731basicinstructions2.
20interruptsources(External:5Internal:15)3.
Input/Outputports(I/O:48pinsOutput:3pins)Largecurrentoutput:5pins(Typ.
20mA),LEDdirectdrive4.
Prescaler-Timebasetimer-Divideroutputfunction5.
WatchdogTimer6.
18-bitTimer/Counter:1ch-TimerMode-EventCounterMode-PulseWidthMeasurementMode-FrequencyMeasurementModeProductNo.
ROM(FLASH)RAMPackageMASKROMMCUEmulationChipTMP86FS23UG61440bytes2048bytesP-LQFP64-1010-0.
50DTMP86CM23/CP23AUGTMP86C923XBPage21.
1FeaturesTMP86FS23UG7.
8-bittimercounter:4ch-Timer,Eventcounter,Programmabledivideroutput(PDO),Pulsewidthmodulation(PWM)output,Programmablepulsegeneration(PPG)modes8.
8-bitUART:1ch9.
8-bitSIO:1ch10.
10-bitsuccessiveapproximationtypeADconverter-Analoginput:8ch11.
Key-onwakeup:4ch12.
LCDdriver/controller-LCDdirectdrivecapability(MAX32seg*4com)-1/4,1/3,1/2dutiesorstaticdriveareprogrammablyselectable13.
Multiplyaccumulateunit(MAC)-MultiplyorMACmodeareselectable-Signedorunsignedoperationareselectable14.
ClockoperationSingleclockmodeDualclockmode15.
LowpowerconsumptionoperationSTOPmode:Oscillationstops.
(Battery/Capacitorback-up.
)SLOW1mode:Lowpowerconsumptionoperationusinglow-frequencyclock.
(High-frequencyclockstop.
)SLOW2mode:Lowpowerconsumptionoperationusinglow-frequencyclock.
(High-frequencyclockoscillate.
)IDLE0mode:CPUstops,andonlytheTime-Based-Timer(TBT)onperipheralsoperateusinghighfre-quencyclock.
ReleasebyfallingedgeofthesourceclockwhichissetbyTBTCR.
IDLE1mode:CPUstopsandperipheralsoperateusinghighfrequencyclock.
Releasebyinterru-puts(CPUrestarts).
IDLE2mode:CPUstopsandperipheralsoperateusinghighandlowfrequencyclock.
Releasebyinter-ruputs.
(CPUrestarts).
SLEEP0mode:CPUstops,andonlytheTime-Based-Timer(TBT)onperipheralsoperateusinglowfre-quencyclock.
ReleasebyfallingedgeofthesourceclockwhichissetbyTBTCR.
SLEEP1mode:CPUstops,andperipheralsoperateusinglowfrequencyclock.
Releasebyinterru-put.
(CPUrestarts).
SLEEP2mode:CPUstopsandperipheralsoperateusinghighandlowfrequencyclock.
Releasebyinterruput.
16.
Wideoperationvoltage:3.
5Vto5.
5Vat16MHz/32.
768kHz2.
7Vto5.
5Vat8MHz/32.
768kHzPage3TMP86FS23UG1.
2PinAssignmentFigure1-1PinAssignmentVSSXOUTTESTVDD(XTIN)P21(XTOUT)P22RESET(INT5/STOP)P20AVDD(AIN0)P60(ECNT/AIN2)P62(ECIN/AIN1)P61(INT0/AIN3)P63(STOP2/AIN4)P6412345678910111213141516484746454443424140393837363534333231302928272625242322212019181749505152535455565758596061626364P15(SEG26)P17(SEG24)P50(SEG23)P52(SEG21)P51(SEG22)P54(SEG19)P53(SEG20)P16(SEG25)P84(SEG3)P83(SEG4)P82(SEG5)P81(SEG6)P80(SEG7)P77(SEG8)P76(SEG9)P75(SEG10)VAREFXINP65(AIN5/STOP3)P67(AIN7/STOP5)P10(SEG31/RXD/BOOT)P11(SEG30/TXD)P14(SEG27/INT3)P12(SEG29/INT1)P66(AIN6/STOP4)P13(SEG28/INT2)P74(SEG11)P73(SEG12)P72(SEG13)P71(SEG14)P70(SEG15)P57(SEG16)P56(SEG17)P55(SEG18)(SEG2)P85(SEG1)P86(SEG0)P87COM3COM2COM1COM0VLC(TC4/SI)P30(TC3/SO)P31(SCK)P32(TC6/PDO6/PWM6/PPG6)P33(TC5/PDO5/PWM5)P34(PDO4/PWM4/PPG4)P35(PDO3/PWM3)P36(DVO)P37Page41.
3BlockDiagramTMP86FS23UG1.
3BlockDiagramFigure1-2BlockDiagramPage5TMP86FS23UG1.
4PinNamesandFunctionsTheTMP86FS23UGhasMCUmode,parallelPROMmode,andserialPROMmode.
Table1-1showsthepinfunctionsinMCUmode.
TheserialPROMmodeisexplainedlaterinaseparatechapter.
Table1-1PinNamesandFunctions(1/3)PinNamePinNumberInput/OutputFunctionsP17SEG2427IOOPORT17LCDsegmentoutput24P16SEG2526IOOPORT16LCDsegmentoutput25P15SEG2625IOOPORT15LCDsegmentoutput26P14SEG27INT324IOOIPORT14LCDsegmentoutput27Externalinterrupt3inputP13SEG28INT223IOOIPORT13LCDsegmentoutput28Externalinterrupt2inputP12SEG29INT122IOOIPORT12LCDsegmentoutput29Externalinterrupt1inputP11SEG30TXD21IOOOPORT11LCDsegmentoutput30UARTdataoutputP10SEG31RXD20IOOIPORT10LCDsegmentoutput31UARTdatainputP22XTOUT7IOOPORT22Resonatorconnectingpins(32.
768kHz)forinputtingexternalclockP21XTIN6IOIPORT21Resonatorconnectingpins(32.
768kHz)forinputtingexternalclockP20STOPINT59IOIIPORT20STOPmodereleasesignalinputExternalinterrupt5inputP37DVO64OOPORT37DividerOutputP36PDO3/PWM363OOPORT36PDO3/PWM3outputP35PDO4/PWM4/PPG462OOPORT35PDO4/PWM4/PPG4outputP34PDO5/PWM5TC561IOOIPORT34PDO5/PWM5outputTC5inputP33PDO6/PWM6/PPG6TC660IOOIPORT33PDO6/PWM6/PPG6outputTC6inputP32SCK59IOIOPORT32SerialClockI/OPage61.
4PinNamesandFunctionsTMP86FS23UGP31SOTC358IOOIPORT31SerialDataOutputTC3inputP30SITC457IOIIPORT30SerialDataInputTC4inputP57SEG1635IOOPORT57LCDsegmentoutput16P56SEG1734IOOPORT56LCDsegmentoutput17P55SEG1833IOOPORT55LCDsegmentoutput18P54SEG1932IOOPORT54LCDsegmentoutput19P53SEG2031IOOPORT53LCDsegmentoutput20P52SEG2130IOOPORT52LCDsegmentoutput21P51SEG2229IOOPORT51LCDsegmentoutput22P50SEG2328IOOPORT50LCDsegmentoutput23P67AIN7STOP519IOIIPORT67AnalogInput7STOP5inputP66AIN6STOP418IOIIPORT66AnalogInput6STOP4inputP65AIN5STOP317IOIIPORT65AnalogInput5STOP3inputP64AIN4STOP216IOIIPORT64AnalogInput4STOP2inputP63AIN3INT015IOIIPORT63AnalogInput3Externalinterrupt0inputP62AIN2ECNT14IOIIPORT62AnalogInput2ECNTinputP61AIN1ECIN13IOIIPORT61AnalogInput1ECINinputP60AIN012IOIPORT60AnalogInput0P77SEG843IOOPORT77LCDsegmentoutput8P76SEG942IOOPORT76LCDsegmentoutput9Table1-1PinNamesandFunctions(2/3)PinNamePinNumberInput/OutputFunctionsPage7TMP86FS23UGP75SEG1041IOOPORT75LCDsegmentoutput10P74SEG1140IOOPORT74LCDsegmentoutput11P73SEG1239IOOPORT73LCDsegmentoutput12P72SEG1338IOOPORT72LCDsegmentoutput13P71SEG1437IOOPORT71LCDsegmentoutput14P70SEG1536IOOPORT70LCDsegmentoutput15P87SEG051IOOPORT87LCDsegmentoutput0P86SEG150IOOPORT86LCDsegmentoutput1P85SEG249IOOPORT85LCDsegmentoutput2P84SEG348IOOPORT84LCDsegmentoutput3P83SEG447IOOPORT83LCDsegmentoutput4P82SEG546IOOPORT82LCDsegmentoutput5P81SEG645IOOPORT81LCDsegmentoutput6P80SEG744IOOPORT80LCDsegmentoutput7COM352OLCDcommonoutput3COM253OLCDcommonoutput2COM154OLCDcommonoutput1COM055OLCDcommonoutput0XIN2IResonatorconnectingpinsforhigh-frequencyclockXOUT3OResonatorconnectingpinsforhigh-frequencyclockRESET8IResetsignalTEST4ITestpinforout-goingtest.
Normally,befixedtolow.
VAREF11IAnalogBaseVoltageInputPinforA/DConversionAVDD10IAnalogPowerSupplyVDD5I+5VVSS1I0(GND)Table1-1PinNamesandFunctions(3/3)PinNamePinNumberInput/OutputFunctionsPage81.
4PinNamesandFunctionsTMP86FS23UGPage9TMP86FS23UG2.
OperationalDescription2.
1CPUCoreFunctionsTheCPUcoreconsistsofaCPU,asystemclockcontroller,andaninterruptcontroller.
ThissectionprovidesadescriptionoftheCPUcore,theprogrammemory,thedatamemory,andtheresetcircuit.
2.
1.
1MemoryAddressMapTheTMP86FS23UGmemoryiscomposedFlash,RAM,DBR(Databufferregister)andSFR(Specialfunc-tionregister).
Theyareallmappedin64-Kbyteaddressspace.
Figure2-1showstheTMP86FS23UGmemoryaddressmap.
Figure2-1MemoryAddressMap2.
1.
2ProgramMemory(Flash)TheTMP86FS23UGhasa61440bytes(Address1000HtoFFFFH)ofprogrammemory(Flash).
2.
1.
3DataMemory(RAM)TheTMP86FS23UGhas2048bytes(Address0040Hto083FH)ofinternalRAM.
Thefirst192bytes(0040Hto00FFH)oftheinternalRAMarelocatedinthedirectarea;instructionswithshortenoperationsareavailableagainstsuchanarea.
SFR0000H64bytesSFR:RAM:Specialfunctionregisterincludes:I/OportsPeripheralcontrolregistersPeripheralstatusregistersSystemcontrolregistersProgramstatuswordRandomaccessmemoryincludes:DatamemoryStack003FHRAM0040H2048bytes083FHDBR0F80H128bytesDBR:Databufferregisterincludes:PeripheralcontrolregistersPeripheralstatusregistersLCDdisplaymemory0FFFH1000HFlash:ProgrammemoryFlash61440bytesFFB0HVectortableforinterrupts(16bytes)FFBFHFFC0HVectortableforvectorcallinstructions(32bytes)FFDFHFFE0HVectortableforinterrupts(32bytes)FFFFHPage102.
OperationalDescription2.
2SystemClockControllerTMP86FS23UGThedatamemorycontentsbecomeunstablewhenthepowersupplyisturnedon;therefore,thedatamemoryshouldbeinitializedbyaninitializationroutine.
2.
2SystemClockControllerThesystemclockcontrollerconsistsofaclockgenerator,atiminggenerator,andastandbycontroller.
Figure2-2SystemColckControl2.
2.
1ClockGeneratorTheclockgeneratorgeneratesthebasicclockwhichprovidesthesystemclockssuppliedtotheCPUcoreandperipheralhardware.
Itcontainstwooscillationcircuits:Oneforthehigh-frequencyclockandoneforthelow-frequencyclock.
Powerconsumptioncanbereducedbyswitchingofthestandbycontrollertolow-poweroperationbasedonthelow-frequencyclock.
Thehigh-frequency(fc)clockandlow-frequency(fs)clockcaneasilybeobtainedbyconnectingaresonatorbetweentheXIN/XOUTandXTIN/XTOUTpinsrespectively.
Clockinputfromanexternaloscillatorisalsopossible.
Inthiscase,externalclockisappliedtoXIN/XTINpinwithXOUT/XTOUTpinnotconnected.
Example:ClearsRAMto"00H".
(TMP86FS23UG)LDHL,0040H;StartaddresssetupLDA,H;Initialvalue(00H)setupLDBC,07FFHSRAMCLR:LD(HL),AINCHLDECBCJRSF,SRAMCLRTBTCRSYSCR2SYSCR1XINXOUTXTINXTOUTfc0036H0038H0039HfsTiminggeneratorcontrolregisterTiminggeneratorStandbycontrollerSystemclocksClockgeneratorcontrolHigh-frequencyclockoscillatorLow-frequencyclockoscillatorClockgeneratorSystemcontrolregistersPage11TMP86FS23UGFigure2-3ExamplesofResonatorConnectionNote:Thefunctiontomonitorthebasicclockdirectlyatexternalisnotprovidedforhardware,however,withdis-ablingallinterruptsandwatchdogtimers,theoscillationfrequencycanbeadjustedbymonitoringthepulsewhichthefixedfrequencyisoutputtedtotheportbytheprogram.
Thesystemtorequiretheadjustmentoftheoscillationfrequencyshouldcreatetheprogramfortheadjust-mentinadvance.
XOUTXIN(Open)XOUTXINXTOUTXTIN(Open)XTOUTXTIN(a)Crystal/Ceramicresonator(b)Externaloscillator(c)Crystal(d)ExternaloscillatorHigh-frequencyclockLow-frequencyclockPage122.
OperationalDescription2.
2SystemClockControllerTMP86FS23UG2.
2.
2TimingGeneratorThetiminggeneratorgeneratesthevarioussystemclockssuppliedtotheCPUcoreandperipheralhardwarefromthebasicclock(fcorfs).
Thetiminggeneratorprovidesthefollowingfunctions.
1.
Generationofmainsystemclock2.
Generationofdivideroutput(DVO)pulses3.
Generationofsourceclocksfortimebasetimer4.
Generationofsourceclocksforwatchdogtimer5.
Generationofinternalsourceclocksfortimer/counters6.
Generationofwarm-upclocksforreleasingSTOPmode7.
LCD2.
2.
2.
1ConfigurationoftiminggeneratorThetiminggeneratorconsistsofa2-stageprescaler,a21-stagedivider,amainsystemclockgenerator,andmachinecyclecounters.
Aninputclocktothe7thstageofthedividerdependsontheoperatingmode,SYSCR2andTBTCR,thatisshowninFigure2-4.
AsresetandSTOPmodestarted/canceled,theprescalerandthedividerareclearedto"0".
Figure2-4ConfigurationofTimingGeneratorMulti-plexerHigh-frequencyclockfcLow-frequencyclockfsDividerSYSCKfc/4fcorfsMachinecyclecountersMainsystemclockgenerator12143287109121114131615DV7CKMultiplexerWarm-upcontrollerWatchdogtimerASBYSB0A0Y0B1A1Y1561718192021Timercounter,Serialinterface,Time-base-timer,divideroutput,etc.
(Peripheralfunctions)Page13TMP86FS23UGNote1:Insingleclockmode,donotsetDV7CKto"1".
Note2:Donotset"1"onDV7CKwhilethelow-frequencyclockisnotoperatedstably.
Note3:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*:Don'tcareNote4:InSLOW1/2andSLEEP1/2modes,theDV7CKsettingisineffective,andfsisinputtothe7thstageofthedivider.
Note5:WhenSTOPmodeisenteredfromNORMAL1/2mode,theDV7CKsettingisineffectiveduringthewarm-upperiodafterreleaseofSTOPmode,andthe6thstageofthedividerisinputtothe7thstageduringthisperiod.
2.
2.
2.
2MachinecycleInstructionexecutionandperipheralhardwareoperationaresynchronizedwiththemainsystemclock.
Theminimuminstructionexecutionunitiscalledan"machinecycle".
Thereareatotalof10differenttypesofinstructionsfortheTLCS-870/CSeries:Rangingfrom1-cycleinstructionswhichrequireonemachinecycleforexecutionto10-cycleinstructionswhichrequire10machinecyclesforexecution.
Amachinecycleconsistsof4states(S0toS3),andeachstateconsistsofonemainsystemclock.
Figure2-5MachineCycle2.
2.
3OperationModeControlCircuitTheoperationmodecontrolcircuitstartsandstopstheoscillationcircuitsforthehigh-frequencyandlow-frequencyclocks,andswitchesthemainsystemclock.
Therearethreeoperatingmodes:Singleclockmode,dualclockmodeandSTOPmode.
Thesemodesarecontrolledbythesystemcontrolregisters(SYSCR1andSYSCR2).
Figure2-6showstheoperatingmodetransitiondiagram.
2.
2.
3.
1Single-clockmodeOnlytheoscillationcircuitforthehigh-frequencyclockisused,andP21(XTIN)andP22(XTOUT)pinsareusedasinput/outputports.
Themain-systemclockisobtainedfromthehigh-frequencyclock.
Inthesingle-clockmode,themachinecycletimeis4/fc[s].
(1)NORMAL1modeInthismode,boththeCPUcoreandon-chipperipheralsoperateusingthehigh-frequencyclock.
TheTMP86FS23UGisplacedinthismodeafterreset.
TimingGeneratorControlRegisterTBTCR(0036H)76543210(DVOEN)(DVOCK)DV7CK(TBTEN)(TBTCK)(Initialvalue:00000000)DV7CKSelectionofinputtothe7thstageofthedivider0:fc/28[Hz]1:fsR/WMainsystemclockStateMachinecycleS3S2S1S0S3S2S1S01/fcor1/fs[s]Page142.
OperationalDescription2.
2SystemClockControllerTMP86FS23UG(2)IDLE1modeInthismode,theinternaloscillationcircuitremainsactive.
TheCPUandthewatchdogtimerarehalted;howeveron-chipperipheralsremainactive(Operateusingthehigh-frequencyclock).
IDLE1modeisstartedbySYSCR2="1",andIDLE1modeisreleasedtoNORMAL1modebyaninterruptrequestfromtheon-chipperipheralsorexternalinterruptinputs.
WhentheIMF(Interruptmasterenableflag)is"1"(Interruptenable),theexecutionwillresumewiththeacceptanceoftheinterrupt,andtheoperationwillreturntonormalaftertheinterruptserviceiscompleted.
WhentheIMFis"0"(Interruptdisable),theexecutionwillresumewiththeinstructionwhichfollowstheIDLE1modestartinstruction.
(3)IDLE0modeInthismode,allthecircuit,exceptoscillatorandthetimer-base-timer,stopsoperation.
ThismodeisenabledbySYSCR2="1".
WhenIDLE0modestarts,theCPUstopsandthetiminggeneratorstopsfeedingtheclocktotheperipheralcircuitsotherthanTBT.
Then,upondetectingthefallingedgeofthesourceclockselectedwithTBTCR,thetiminggeneratorstartsfeedingtheclocktoallperipheralcircuits.
WhenreturnedfromIDLE0mode,theCPUrestartsoperating,enteringNORMAL1modebackagain.
IDLE0modeisenteredandreturnedregardlessofhowTBTCRisset.
WhenIMF="1",EF6(TBTinterruptindividualenableflag)="1",andTBTCR="1",interruptpro-cessingisperformed.
WhenIDLE0modeisenteredwhileTBTCR="1",theINTTBTinterruptlatchissetafterreturningtoNORMAL1mode.
2.
2.
3.
2Dual-clockmodeBoththehigh-frequencyandlow-frequencyoscillationcircuitsareusedinthismode.
P21(XTIN)andP22(XTOUT)pinscannotbeusedasinput/outputports.
Themainsystemclockisobtainedfromthehigh-frequencyclockinNORMAL2andIDLE2modes,andisobtainedfromthelow-frequencyclockinSLOWandSLEEPmodes.
Themachinecycletimeis4/fc[s]intheNORMAL2andIDLE2modes,and4/fs[s](122satfs=32.
768kHz)intheSLOWandSLEEPmodes.
TheTLCS-870/Cisplacedinthesignal-clockmodeduringreset.
Tousethedual-clockmode,thelow-frequencyoscillatorshouldbeturnedonatthestartofaprogram.
(1)NORMAL2modeInthismode,theCPUcoreoperateswiththehigh-frequencyclock.
On-chipperipheralsoperateusingthehigh-frequencyclockand/orlow-frequencyclock.
(2)SLOW2modeInthismode,theCPUcoreoperateswiththelow-frequencyclock,whileboththehigh-frequencyclockandthelow-frequencyclockareoperated.
AstheSYSCR2becomes"1",thehard-warechangesintoSLOW2mode.
AstheSYSCR2becomes"0",thehardwarechangesintoNORMAL2mode.
AstheSYSCR2becomes"0",thehardwarechangesintoSLOW1mode.
DonotclearSYSCR2to"0"duringSLOW2mode.
(3)SLOW1modeThismodecanbeusedtoreducepower-consumptionbyturningoffoscillationofthehigh-fre-quencyclock.
TheCPUcoreandon-chipperipheralsoperateusingthelow-frequencyclock.
Page15TMP86FS23UGSwitchingbackandforthbetweenSLOW1andSLOW2modesareperformedbySYSCR2.
InSLOW1andSLEEPmodes,theinputclocktothe1ststageofthedividerisstopped;outputfromthe1stto6thstagesisalsostopped.
(4)IDLE2modeInthismode,theinternaloscillationcircuitremainactive.
TheCPUandthewatchdogtimerarehalted;however,on-chipperipheralsremainactive(Operateusingthehigh-frequencyclockand/orthelow-frequencyclock).
StartingandreleasingofIDLE2modearethesameasforIDLE1mode,exceptthatoperationreturnstoNORMAL2mode.
(5)SLEEP1modeInthismode,theinternaloscillationcircuitofthelow-frequencyclockremainsactive.
TheCPU,thewatchdogtimer,andtheinternaloscillationcircuitofthehigh-frequencyclockarehalted;how-ever,on-chipperipheralsremainactive(Operateusingthelow-frequencyclock).
Startingandreleas-ingofSLEEPmodearethesameasforIDLE1mode,exceptthatoperationreturnstoSLOW1mode.
InSLOW1andSLEEP1modes,theinputclocktothe1ststageofthedividerisstopped;outputfromthe1stto6thstagesisalsostopped.
(6)SLEEP2modeTheSLEEP2modeistheidlemodecorrespondingtotheSLOW2mode.
ThestatusundertheSLEEP2modeissameasthatundertheSLEEP1mode,exceptfortheoscillationcircuitofthehigh-frequencyclock.
(7)SLEEP0modeInthismode,allthecircuit,exceptoscillatorandthetimer-base-timer,stopsoperation.
Thismodeisenabledbysetting"1"onbitSYSCR2.
WhenSLEEP0modestarts,theCPUstopsandthetiminggeneratorstopsfeedingtheclocktotheperipheralcircuitsotherthanTBT.
Then,upondetectingthefallingedgeofthesourceclockselectedwithTBTCR,thetiminggeneratorstartsfeedingtheclocktoallperipheralcircuits.
WhenreturnedfromSLEEP0mode,theCPUrestartsoperating,enteringSLOW1modebackagain.
SLEEP0modeisenteredandreturnedregardlessofhowTBTCRisset.
WhenIMF="1",EF6(TBTinterruptindividualenableflag)="1",andTBTCR="1",interruptpro-cessingisperformed.
WhenSLEEP0modeisenteredwhileTBTCR="1",theINTTBTinterruptlatchissetafterreturningtoSLOW1mode.
2.
2.
3.
3STOPmodeInthismode,theinternaloscillationcircuitisturnedoff,causingallsystemoperationstobehalted.
TheinternalstatusimmediatelypriortothehaltisheldwithalowestpowerconsumptionduringSTOPmode.
STOPmodeisstartedbythesystemcontrolregister1(SYSCR1),andSTOPmodeisreleasedbyainputting(Eitherlevel-sensitiveoredge-sensitivecanbeprogrammablyselected)totheSTOPpin.
Afterthewarm-upperiodiscompleted,theexecutionresumeswiththeinstructionwhichfollowstheSTOPmodestartinstruction.
Page162.
OperationalDescription2.
2SystemClockControllerTMP86FS23UGNote1:NORMAL1andNORMAL2modesaregenericallycalledNORMAL;SLOW1andSLOW2arecalledSLOW;IDLE0,IDLE1andIDLE2arecalledIDLE;SLEEP0,SLEEP1andSLEEP2arecalledSLEEP.
Note2:ThemodeisreleasedbyfallingedgeofTBTCRsetting.
Figure2-6OperatingModeTransitionDiagramTable2-1OperatingModeandConditionsOperatingModeOscillatorCPUCoreTBTOtherPeripheralsMachineCycleTimeHighFrequencyLowFrequencySingleclockRESETOscillationStopResetResetReset4/fc[s]NORMAL1OperateOperateOperateIDLE1HaltIDLE0HaltSTOPStopHalt–DualclockNORMAL2OscillationOscillationOperatewithhighfrequencyOperateOperate4/fc[s]IDLE2HaltSLOW2Operatewithlowfrequency4/fs[s]SLEEP2HaltSLOW1StopOperatewithlowfrequencySLEEP1HaltSLEEP0HaltSTOPStopHalt–Note2SYSCR2="1"STOPpininputSTOPpininputSTOPpininputInterruptInterruptSYSCR2="0"SYSCR2="1"SYSCR2="0"SYSCR2="0"SYSCR1="1"SYSCR1="1"SYSCR1="1"SYSCR2="1"SYSCR2="1"InterruptSYSCR2="1"SYSCR2="1"InterruptSYSCR2="1"ResetreleaseNORMAL1modeIDLE0mode(a)Single-clockmodeIDLE1modeNORMAL2modeIDLE2modeSYSCR2="1"SLOW2modeSLEEP2modeSLOW1modeSLEEP1modeSLEEP0modeRESET(b)Dual-clockmodeSTOPSYSCR2="1"Note2Page17TMP86FS23UGNote1:AlwayssetRETMto"0"whentransitingfromNORMALmodetoSTOPmode.
AlwayssetRETMto"1"whentransitingfromSLOWmodetoSTOPmode.
Note2:WhenSTOPmodeisreleasedwithRESETpininput,areturnismadetoNORMAL1regardlessoftheRETMcontents.
Note3:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*;Don'tcareNote4:Bits1and0inSYSCR1arereadasundefineddatawhenareadinstructionisexecuted.
Note5:AsthehardwarebecomesSTOPmodeunderOUTEN="0",inputvalueisfixedto"0";thereforeitmaycauseexternalinterruptrequestonaccountoffallingedge.
Note6:Whenthekey-onwakeupisused,RELMshouldbesetto"1".
Note7:PortP20isusedasSTOPpin.
Therefore,whenstopmodeisstarted,OUTENdoesnotaffecttoP20,andP20becomesHigh-Zmode.
Note8:Thewarmig-uptimeshouldbesetcorrectlyforusingoscillator.
Note1:AresetisappliedifbothXENandXTENareclearedto"0",XENisclearedto"0"whenSYSCK="0",orXTENisclearedto"0"whenSYSCK="1".
Note2:*:Don'tcare,TG:Timinggenerator,*;Don'tcareNote3:Bits3,1and0inSYSCR2arealwaysreadasundefinedvalue.
Note4:DonotsetIDLEandTGHALTto"1"simultaneously.
Note5:BecausereturningfromIDLE0/SLEEP0toNORMAL1/SLOW1isexecutedbytheasynchronousinternalclock,theperiodofIDLE0/SLEEP0modemightbeshorterthantheperiodsettingbyTBTCR.
Note6:WhenIDLE1/2orSLEEP1/2modeisreleased,IDLEisautomaticallyclearedto"0".
Note7:WhenIDLE0orSLEEP0modeisreleased,TGHALTisautomaticallyclearedto"0".
Note8:BeforesettingTGHALTto"1",besuretostopperipherals.
Ifperipheralsarenotstopped,theinterruptlatchofperipheralsmaybesetafterIDLE0orSLEEP0modeisreleased.
SystemControlRegister1SYSCR176543210(0038H)STOPRELMRETMOUTENWUT(Initialvalue:000000**)STOPSTOPmodestart0:CPUcoreandperipheralsremainactive1:CPUcoreandperipheralsarehalted(StartSTOPmode)R/WRELMReleasemethodforSTOPmode0:Edge-sensitiverelease1:Level-sensitivereleaseR/WRETMOperatingmodeafterSTOPmode0:ReturntoNORMAL1/2mode1:ReturntoSLOW1modeR/WOUTENPortoutputduringSTOPmode0:Highimpedance1:OutputkeptR/WWUTWarm-uptimeatreleasingSTOPmodeReturntoNORMALmodeReturntoSLOWmodeR/W000110113x216/fc216/fc3x214/fc214/fc3x213/fs213/fs3x26/fs26/fsSystemControlRegister2SYSCR2(0039H)76543210XENXTENSYSCKIDLETGHALT(Initialvalue:1000*0**)XENHigh-frequencyoscillatorcontrol0:Turnoffoscillation1:TurnonoscillationR/WXTENLow-frequencyoscillatorcontrol0:Turnoffoscillation1:TurnonoscillationSYSCKMainsystemclockselect(Write)/mainsystemclockmoni-tor(Read)0:High-frequencyclock(NORMAL1/NORMAL2/IDLE1/IDLE2)1:Low-frequencyclock(SLOW1/SLOW2/SLEEP1/SLEEP2)IDLECPUandwatchdogtimercontrol(IDLE1/2andSLEEP1/2modes)0:CPUandwatchdogtimerremainactive1:CPUandwatchdogtimerarestopped(StartIDLE1/2andSLEEP1/2modes)R/WTGHALTTGcontrol(IDLE0andSLEEP0modes)0:FeedingclocktoallperipheralsfromTG1:StopfeedingclocktoperipheralsexceptTBTfromTG.
(StartIDLE0andSLEEP0modes)Page182.
OperationalDescription2.
2SystemClockControllerTMP86FS23UG2.
2.
4OperatingModeControl2.
2.
4.
1STOPmodeSTOPmodeiscontrolledbythesystemcontrolregister1,theSTOPpininputandkey-onwakeupinput(STOP5toSTOP2)whichiscontrolledbytheSTOPmodereleasecontrolregister(STOPCR).
TheSTOPpinisalsousedbothasaportP20andanINT5(externalinterruptinput5)pin.
STOPmodeisstartedbysettingSYSCR1to"1".
DuringSTOPmode,thefollowingstatusismaintained.
1.
Oscillationsareturnedoff,andallinternaloperationsarehalted.
2.
Thedatamemory,registers,theprogramstatuswordandportoutputlatchesareallheldinthestatusineffectbeforeSTOPmodewasentered.
3.
Theprescalerandthedividerofthetiminggeneratorareclearedto"0".
4.
Theprogramcounterholdstheaddress2aheadoftheinstruction(e.
g.
,[SET(SYSCR1).
7])whichstartedSTOPmode.
STOPmodeincludesalevel-sensitivemodeandanedge-sensitivemode,eitherofwhichcanbeselectedwiththeSYSCR1.
Donotuseanykey-onwakeupinput(STOP5toSTOP2)forreleas-ingSTOPmodeinedge-sensitivemode.
Note1:TheSTOPmodecanbereleasedbyeithertheSTOPorkey-onwakeuppin(STOP5toSTOP2).
However,becausetheSTOPpinisdifferentfromthekey-onwakeupandcannotinhibitthereleaseinput,theSTOPpinmustbeusedforreleasingSTOPmode.
Note2:DuringSTOPperiod(fromstartofSTOPmodetoendofwarmup),duetochangesintheexternalinterruptpinsignal,interruptlatchesmaybesetto"1"andinterruptsmaybeacceptedimmediatelyafterSTOPmodeisreleased.
BeforestartingSTOPmode,therefore,disableinterrupts.
Also,beforeenablinginterruptsafterSTOPmodeisreleased,clearunnecessaryinterruptlatches.
(1)Level-sensitivereleasemode(RELM="1")Inthismode,STOPmodeisreleasedbysettingtheSTOPpinhighorsettingtheSTOP5toSTOP2pininputwhichisenabledbySTOPCR.
Thismodeisusedforcapacitorbackupwhenthemainpowersupplyiscutoffandlongtermbatterybackup.
EvenifaninstructionforstartingSTOPmodeisexecutedwhileSTOPpininputishighorSTOP5toSTOP2inputislow,STOPmodedoesnotstartbutinsteadthewarm-upsequencestartsimmedi-ately.
Thus,tostartSTOPmodeinthelevel-sensitivereleasemode,itisnecessaryfortheprogramtofirstconfirmthattheSTOPpininputisloworSTOP5toSTOP2inputishigh.
Thefollowingtwomethodscanbeusedforconfirmation.
1.
Testingaport.
2.
UsinganexternalinterruptinputINT5(INT5isafallingedge-sensitiveinput).
Example1:StartingSTOPmodefromNORMALmodebytestingaportP20.
LD(SYSCR1),01010000B;Setsupthelevel-sensitivereleasemodeSSTOPH:TEST(P2PRD).
0;WaituntiltheSTOPpininputgoeslowlevelJRSF,SSTOPHDI;IMF←0SET(SYSCR1).
7;StartsSTOPmodePage19TMP86FS23UGFigure2-7Level-sensitiveReleaseModeNote1:EveniftheSTOPpininputislowafterwarm-upstart,theSTOPmodeisnotrestarted.
Note2:Inthiscaseofchangingtothelevel-sensitivemodefromtheedge-sensitivemode,thereleasemodeisnotswitcheduntilarisingedgeoftheSTOPpininputisdetected.
(2)Edge-sensitivereleasemode(RELM="0")Inthismode,STOPmodeisreleasedbyarisingedgeoftheSTOPpininput.
Thisisusedinappli-cationswherearelativelyshortprogramisexecutedrepeatedlyatperiodicintervals.
Thisperiodicsignal(forexample,aclockfromalow-powerconsumptionoscillator)isinputtotheSTOPpin.
Intheedge-sensitivereleasemode,STOPmodeisstartedevenwhentheSTOPpininputishighlevel.
DonotuseanySTOP5toSTOP2pininputforreleasingSTOPmodeinedge-sensitivereleasemode.
Figure2-8Edge-sensitiveReleaseModeExample2:StartingSTOPmodefromNORMALmodewithanINT5interrupt.
PINT5:TEST(P2PRD).
0;Torejectnoise,STOPmodedoesnotstartifJRSF,SINT5portP20isathighLD(SYSCR1),01010000B;Setsupthelevel-sensitivereleasemode.
DI;IMF←0SET(SYSCR1).
7;StartsSTOPmodeSINT5:RETIExample:StartingSTOPmodefromNORMALmodeDI;IMF←0LD(SYSCR1),10010000B;Startsafterspecifiedtotheedge-sensitivereleasemodeVIHNORMALoperationWarmupSTOPoperationConfirmbyprogramthattheSTOPpininputislowandstartSTOPmode.
AlwaysreleasediftheSTOPpininputishigh.
STOPpinXOUTpinSTOPmodeisreleasedbythehardware.
NORMALoperationNORMALoperationNORMALoperationVIHSTOPmodeisreleasedbythehardwareattherisingedgeofSTOPpininput.
WarmupSTOPmodestartedbytheprogram.
STOPoperationSTOPoperationSTOPpinXOUTpinPage202.
OperationalDescription2.
2SystemClockControllerTMP86FS23UGSTOPmodeisreleasedbythefollowingsequence.
1.
Inthedual-clockmode,whenreturningtoNORMAL2,boththehigh-frequencyandlow-frequencyclockoscillatorsareturnedon;whenreturningtoSLOW1mode,onlythelow-frequencyclockoscillatoristurnedon.
Inthesingle-clockmode,onlythehigh-frequencyclockoscillatoristurnedon.
2.
Awarm-upperiodisinsertedtoallowoscillationtimetostabilize.
Duringwarmup,allinternaloperationsremainhalted.
Fourdifferentwarm-uptimescanbeselectedwiththeSYSCR1inaccordancewiththeresonatorcharacteristics.
3.
Whenthewarm-uptimehaselapsed,normaloperationresumeswiththeinstructionfollow-ingtheSTOPmodestartinstruction.
Note1:WhentheSTOPmodeisreleased,thestartismadeaftertheprescalerandthedividerofthetiminggeneratorareclearedto"0".
Note2:STOPmodecanalsobereleasedbyinputtinglowlevelontheRESETpin,whichimmediatelyperformsthenormalresetoperation.
Note3:WhenSTOPmodeisreleasedwithalowholdvoltage,thefollowingcautionsmustbeobserved.
ThepowersupplyvoltagemustbeattheoperatingvoltagelevelbeforereleasingSTOPmode.
TheRESETpininputmustalsobe"H"level,risingtogetherwiththepowersupplyvoltage.
Inthiscase,ifanexternaltimeconstantcircuithasbeenconnected,theRESETpininputvoltagewillincreaseataslowerpacethanthepowersupplyvoltage.
Atthistime,thereisadangerthataresetmayoccurifinputvoltageleveloftheRESETpindropsbelowthenon-invertinghigh-levelinputvoltage(Hysteresisinput).
Note1:Thewarm-uptimeisobtainedbydividingthebasicclockbythedivider.
Therefore,thewarm-uptimemayincludeacertainamountoferrorifthereisanyfluctuationoftheoscillationfrequencywhenSTOPmodeisreleased.
Thus,thewarm-uptimemustbeconsideredasanapproximatevalue.
Table2-2Warm-upTimeExample(atfc=16.
0MHz,fs=32.
768kHz)WUTWarm-upTime[ms]ReturntoNORMALModeReturntoSLOWMode0001101112.
2884.
0963.
0721.
0247502505.
851.
95Page21TMP86FS23UGFigure2-9STOPModeStart/ReleaseInstructionaddressa+40Instructionaddressa+3TurnonTurnonWarmup0nHaltSET(SYSCR1).
7Turnoff(a)STOPmodestart(Example:StartwithSET(SYSCR1).
7instructionlocatedataddressa)a+6a+5a+4a+3a+2n+2n+3n+4a+3n+1Instructionaddressa+22103(b)STOPmodereleaseCountupTurnoffHaltOscillatorcircuitProgramcounterInstructionexecutionDividerMainsystemclockOscillatorcircuitSTOPpininputProgramcounterInstructionexecutionDividerMainsystemclockPage222.
OperationalDescription2.
2SystemClockControllerTMP86FS23UG2.
2.
4.
2IDLE1/2modeandSLEEP1/2modeIDLE1/2andSLEEP1/2modesarecontrolledbythesystemcontrolregister2(SYSCR2)andmaskableinterrupts.
Thefollowingstatusismaintainedduringthesemodes.
1.
OperationoftheCPUandwatchdogtimer(WDT)ishalted.
On-chipperipheralscontinuetooperate.
2.
Thedatamemory,CPUregisters,programstatuswordandportoutputlatchesareallheldinthestatusineffectbeforethesemodeswereentered.
3.
Theprogramcounterholdstheaddress2aheadoftheinstructionwhichstartsthesemodes.
Figure2-10IDLE1/2andSLEEP1/2ModesResetResetinput"0""1"(Interruptreleasemode)YesNoNoCPUandWDTarehaltedInterruptrequestIMFInterruptprocessingNormalreleasemodeYesStartingIDLE1/2andSLEEP1/2modesbyinstructionExecutionoftheinstruc-tionwhichfollowstheIDLE1/2andSLEEP1/2modesstartinstructionPage23TMP86FS23UGStarttheIDLE1/2andSLEEP1/2modesAfterIMFissetto"0",settheindividualinterruptenableflag(EF)whichreleasesIDLE1/2andSLEEP1/2modes.
TostartIDLE1/2andSLEEP1/2modes,setSYSCR2to"1".
ReleasetheIDLE1/2andSLEEP1/2modesIDLE1/2andSLEEP1/2modesincludeanormalreleasemodeandaninterruptreleasemode.
Thesemodesareselectedbyinterruptmasterenableflag(IMF).
AfterreleasingIDLE1/2andSLEEP1/2modes,theSYSCR2isautomaticallyclearedto"0"andtheoperationmodeisreturnedtothemodeprecedingIDLE1/2andSLEEP1/2modes.
IDLE1/2andSLEEP1/2modescanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
(1)Normalreleasemode(IMF="0")IDLE1/2andSLEEP1/2modesarereleasedbyanyinterruptsourceenabledbytheindividualinterruptenableflag(EF).
Aftertheinterruptisgenerated,theprogramoperationisresumedfromtheinstructionfollowingtheIDLE1/2andSLEEP1/2modesstartinstruction.
Normally,theinterruptlatches(IL)oftheinterruptsourceusedforreleasingmustbeclearedto"0"byloadinstructions.
(2)Interruptreleasemode(IMF="1")IDLE1/2andSLEEP1/2modesarereleasedbyanyinterruptsourceenabledwiththeindividualinterruptenableflag(EF)andtheinterruptprocessingisstarted.
Aftertheinterruptisprocessed,theprogramoperationisresumedfromtheinstructionfollowingtheinstruction,whichstartsIDLE1/2andSLEEP1/2modes.
Note:WhenawatchdogtimerinterruptsisgeneratedimmediatelybeforeIDLE1/2andSLEEP1/2modesarestarted,thewatchdogtimerinterruptwillbeprocessedbutIDLE1/2andSLEEP1/2modeswillnotbestarted.
Page242.
OperationalDescription2.
2SystemClockControllerTMP86FS23UGFigure2-11IDLE1/2andSLEEP1/2ModesStart/ReleaseHaltHaltHaltHaltOperateInstructionaddressa+2a+3a+2a+4a+3a+3HaltSET(SYSCR2).
4OperateOperateOperateAcceptanceofinterruptNormalreleasemodeInterruptreleasemodeMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimer(a)IDLE1/2andSLEEP1/2modesstart(Example:StartingwiththeSETinstructionlocatedataddressa)(b)IDLE1/2andSLEEP1/2modesreleasePage25TMP86FS23UG2.
2.
4.
3IDLE0andSLEEP0modes(IDLE0,SLEEP0)IDLE0andSLEEP0modesarecontrolledbythesystemcontrolregister2(SYSCR2)andthetimebasetimercontrolregister(TBTCR).
ThefollowingstatusismaintainedduringIDLE0andSLEEP0modes.
1.
TiminggeneratorstopsfeedingclocktoperipheralsexceptTBT.
2.
Thedatamemory,CPUregisters,programstatuswordandportoutputlatchesareallheldinthestatusineffectbeforeIDLE0andSLEEP0modeswereentered.
3.
Theprogramcounterholdstheaddress2aheadoftheinstructionwhichstartsIDLE0andSLEEP0modes.
Note:BeforestartingIDLE0orSLEEP0mode,besuretostop(Disable)peripherals.
Figure2-12IDLE0andSLEEP0ModesYes(Normalreleasemode)Yes(Interruptreleasemode)NoYesResetinputCPUandWDTarehaltedResetTBTsourceclockfallingedgeTBTCR="1"InterruptprocessingIMF="1"YesTBTinterruptenableNoNoNoNoStoppingperipheralsbyinstructionYesStartingIDLE0,SLEEP0modesbyinstructionExecutionoftheinstructionwhichfollowstheIDLE0,SLEEP0modesstartinstructionPage262.
OperationalDescription2.
2SystemClockControllerTMP86FS23UGStarttheIDLE0andSLEEP0modesStop(Disable)peripheralssuchasatimercounter.
TostartIDLE0andSLEEP0modes,setSYSCR2to"1".
ReleasetheIDLE0andSLEEP0modesIDLE0andSLEEP0modesincludeanormalreleasemodeandaninterruptreleasemode.
Thesemodesareselectedbyinterruptmasterflag(IMF),theindividualinterruptenableflagofTBTandTBTCR.
AfterreleasingIDLE0andSLEEP0modes,theSYSCR2isautomaticallyclearedto"0"andtheoperationmodeisreturnedtothemodeprecedingIDLE0andSLEEP0modes.
BeforestartingtheIDLE0orSLEEP0mode,whentheTBTCRissetto"1",INTTBTinterruptlatchissetto"1".
IDLE0andSLEEP0modescanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
Note:IDLE0andSLEEP0modesstart/releasewithoutreferencetoTBTCRsetting.
(1)Normalreleasemode(IMFEF6TBTCR="0")IDLE0andSLEEP0modesarereleasedbythesourceclockfallingedge,whichissettingbytheTBTCR.
Afterthefallingedgeisdetected,theprogramoperationisresumedfromtheinstructionfollowingtheIDLE0andSLEEP0modesstartinstruction.
BeforestartingtheIDLE0orSLEEP0mode,whentheTBTCRissetto"1",INTTBTinterruptlatchissetto"1".
(2)Interruptreleasemode(IMFEF6TBTCR="1")IDLE0andSLEEP0modesarereleasedbythesourceclockfallingedge,whichissettingbytheTBTCRandINTTBTinterruptprocessingisstarted.
Note1:BecausereturningfromIDLE0,SLEEP0toNORMAL1,SLOW1isexecutedbytheasynchro-nousinternalclock,theperiodofIDLE0,SLEEP0modemightbetheshorterthantheperiodset-tingbyTBTCR.
Note2:WhenawatchdogtimerinterruptisgeneratedimmediatelybeforeIDLE0/SLEEP0modeisstarted,thewatchdogtimerinterruptwillbeprocessedbutIDLE0/SLEEP0modewillnotbestarted.
Page27TMP86FS23UGFigure2-13IDLE0andSLEEP0ModesStart/ReleaseHaltHaltOperateInstructionaddressa+2HaltOperateSET(SYSCR2).
2HaltOperateAcceptanceofinterruptHaltNormalreleasemodeInterruptreleasemodeMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockTBTclockTBTclockProgramcounterInstructionexecutionWatchdogtimerMainsystemclockProgramcounterInstructionexecutionWatchdogtimera+3a+2a+4a+3a+3(a)IDLE0andSLEEP0modesstart(Example:StartingwiththeSETinstructionlocatedataddressa(b)IDLEandSLEEP0modesreleasePage282.
OperationalDescription2.
2SystemClockControllerTMP86FS23UG2.
2.
4.
4SLOWmodeSLOWmodeiscontrolledbythesystemcontrolregister2(SYSCR2).
Thefollowingisthemethodstoswitchthemodewiththewarm-upcounter.
(1)SwitchingfromNORMAL2modetoSLOW1modeFirst,setSYSCR2toswitchthemainsystemclocktothelow-frequencyclockforSLOW2mode.
Next,clearSYSCR2toturnoffhigh-frequencyoscillation.
Note:Thehigh-frequencyclockcanbecontinuedoscillationinordertoreturntoNORMAL2modefromSLOWmodequickly.
Alwaysturnoffoscillationofhigh-frequencyclockwhenswitchingfromSLOWmodetostopmode.
Example1:SwitchingfromNORMAL2modetoSLOW1mode.
SET(SYSCR2).
5;SYSCR2←1(Switchesthemainsystemclocktothelow-frequencyclockforSLOW2)CLR(SYSCR2).
7;SYSCR2←0(Turnsoffhigh-frequencyoscillation)Example2:SwitchingtotheSLOW1modeafterlow-frequencyclockhasstabilized.
SET(SYSCR2).
6;SYSCR2←1LD(TC3CR),43H;SetsmodeforTC4,3(16-bitmode,fsforsource)LD(TC4CR),05H;Setswarming-upcountermodeLDW(TTREG3),8000H;Setswarm-uptime(Dependonoscillatoraccompanied)DI;IMF←0SET(EIRH).
4;EnablesINTTC4EI;IMF←1SET(TC4CR).
3;StartsTC4,3:PINTTC4:CLR(TC4CR).
3;StopsTC4,3SET(SYSCR2).
5;SYSCR2←1(Switchesthemainsystemclocktothelow-frequencyclock)CLR(SYSCR2).
7;SYSCR2←0(Turnsoffhigh-frequencyoscillation)RETI:VINTTC4:DWPINTTC4;INTTC4vectortablePage29TMP86FS23UG(2)SwitchingfromSLOW1modetoNORMAL2modeNote:AfterSYSCKisclearedto"0",executingtheinstructionsiscontiniuedbythelow-frequencyclockfortheperiodsynchronizedwithlow-frequencyandhigh-frequencyclocks.
First,setSYSCR2toturnonthehigh-frequencyoscillation.
Whentimeforstabilization(Warmup)hasbeentakenbythetimer/counter(TC4,TC3),clearSYSCR2toswitchthemainsystemclocktothehigh-frequencyclock.
SLOWmodecanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
Example:SwitchingfromtheSLOW1modetotheNORMAL2mode(fc=16MHz,warm-uptimeis4.
0ms).
SET(SYSCR2).
7;SYSCR2←1(Startshigh-frequencyoscillation)LD(TC3CR),63H;SetsmodeforTC4,3(16-bitmode,fcforsource)LD(TC4CR),05H;Setswarming-upcountermodeLD(TTREG4),0F8H;Setswarm-uptimeDI;IMF←0SET(EIRH).
4;EnablesINTTC4EI;IMF←1SET(TC4CR).
3;StartsTC4,3:PINTTC4:CLR(TC4CR).
3;StopsTC4,3CLR(SYSCR2).
5;SYSCR2←0(Switchesthemainsystemclocktothehigh-frequencyclock)RETI:VINTTC4:DWPINTTC4;INTTC4vectortableHigh-frequencyclockLow-frequencyclockMainsystemclockSYSCKPage302.
OperationalDescription2.
2SystemClockControllerTMP86FS23UGFigure2-14SwitchingbetweentheNORMAL2andSLOWModesSET(SYSCR2).
7NORMAL2modeCLR(SYSCR2).
7SET(SYSCR2).
5NORMAL2modeTurnoff(a)SwitchingtotheSLOWmodeSLOW1modeSLOW2modeCLR(SYSCR2).
5(b)SwitchingtotheNORMAL2modeHigh-frequencyclockLow-frequencyclockMainsystemclockInstructionexecutionSYSCKXENHigh-frequencyclockLow-frequencyclockMainsystemclockInstructionexecutionSYSCKXENSLOW1modeWarmupduringSLOW2modePage31TMP86FS23UG2.
3ResetCircuitTheTMP86FS23UGhasfourtypesofresetgenerationprocedures:Anexternalresetinput,anaddresstrapreset,awatchdogtimerresetandasystemclockreset.
Ofthesereset,theaddresstrapreset,thewatchdogtimerandthesys-temclockresetareamalfunctionreset.
Whenthemalfunctionresetrequestisdetected,resetoccursduringthemax-imum24/fc[s].
Themalfunctionresetcircuitsuchaswatchdogtimerreset,addresstrapresetandsystemclockresetisnotinitial-izedwhenpoweristurnedon.
Therefore,resetmayoccurduringmaximum24/fc[s](1.
5sat16.
0MHz)whenpoweristurnedon.
Table2-3showson-chiphardwareinitializationbyresetaction.
2.
3.
1ExternalResetInputTheRESETpincontainsaSchmitttrigger(Hysteresis)withaninternalpull-upresistor.
WhentheRESETpinisheldat"L"levelforatleast3machinecycles(12/fc[s])withthepowersupplyvolt-agewithintheoperatingvoltagerangeandoscillationstable,aresetisappliedandtheinternalstateisinitial-ized.
WhentheRESETpininputgoeshigh,theresetoperationisreleasedandtheprogramexecutionstartsatthevectoraddressstoredataddressesFFFEHtoFFFFH.
Figure2-15ResetCircuitTable2-3InitializingInternalStatusbyResetActionOn-chipHardwareInitialValueOn-chipHardwareInitialValueProgramcounter(PC)(FFFEH)Prescaleranddivideroftiminggenerator0Stackpointer(SP)NotinitializedGeneral-purposeregisters(W,A,B,C,D,E,H,L,IX,IY)NotinitializedJumpstatusflag(JF)NotinitializedWatchdogtimerEnableZeroflag(ZF)NotinitializedOutputlatchesofI/OportsRefertoI/OportcircuitryCarryflag(CF)NotinitializedHalfcarryflag(HF)NotinitializedSignflag(SF)NotinitializedOverflowflag(VF)NotinitializedInterruptmasterenableflag(IMF)0Interruptindividualenableflags(EF)0ControlregistersRefertoeachofcontrolregisterInterruptlatches(IL)0LCDdatabufferNotinitializedRAMNotinitializedInternalresetRESETVDDMalfunctionresetoutputcircuitWatchdogtimerresetAddresstrapresetSystemclockresetPage322.
OperationalDescription2.
3ResetCircuitTMP86FS23UG2.
3.
2AddresstrapresetIftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whenWDTCR1issetto"1"),DBRortheSFRarea,addresstrapresetwillbegenerated.
Theresettimeismaximum24/fc[s](1.
5sat16.
0MHz).
Note:Theoperatingmodeunderaddresstrappedisalternativeofresetorinterrupt.
Theaddresstrapareaisalter-native.
Note1:Address"a"isintheSFR,DBRoron-chipRAM(WDTCR1="1")space.
Note2:Duringresetrelease,resetvector"r"isreadout,andaninstructionataddress"r"isfetchedanddecoded.
Figure2-16AddressTrapReset2.
3.
3WatchdogtimerresetRefertoSection"WatchdogTimer".
2.
3.
4SystemclockresetIftheconditionasfollowsisdetected,thesystemclockresetoccursautomaticallytopreventdeadlockoftheCPU.
(Theoscillationiscontinuedwithoutstopping.
)-IncaseofclearingSYSCR2andSYSCR2simultaneouslyto"0".
-IncaseofclearingSYSCR2to"0",whentheSYSCR2is"0".
-IncaseofclearingSYSCR2to"0",whentheSYSCR2is"1".
Theresettimeismaximum24/fc(1.
5sat16.
0MHz).
Instructionataddressr16/fc[s]maximum24/fc[s]InstructionexecutionInternalresetJPaResetreleaseAddresstrapisoccurred4/fcto12/fc[s]Page33TMP86FS23UGPage342.
OperationalDescription2.
3ResetCircuitTMP86FS23UGPage35TMP86FS23UG3.
InterruptControlCircuitTheTMP86FS23UGhasatotalof20interruptsourcesexcludingreset.
Interruptscanbenestedwithpriorities.
Fouroftheinternalinterruptsourcesarenon-maskablewhiletherestaremaskable.
Interruptsourcesareprovidedwithinterruptlatches(IL),whichholdinterruptrequests,andindependentvectors.
Theinterruptlatchissetto"1"bythegenerationofitsinterruptrequestwhichrequeststheCPUtoacceptitsinter-rupts.
Interruptsareenabledordisabledbysoftwareusingtheinterruptmasterenableflag(IMF)andinterruptenableflag(EF).
Ifmorethanoneinterruptsaregeneratedsimultaneously,interruptsareacceptedinorderwhichisdomi-natedbyhardware.
However,therearenoprioritizedinterruptfactorsamongnon-maskableinterrupts.
Note1:Tousetheaddresstrapinterrupt(INTATRAP),clearWDTCR1to"0"(Itissetforthe"resetrequest"afterresetiscancelled).
Fordetails,see"AddressTrap".
Note2:Tousethewatchdogtimerinterrupt(INTWDT),clearWDTCR1to"0"(Itissetforthe"Resetrequest"afterresetisreleased).
Fordetails,see"WatchdogTimer".
Note3:IfanINTADCinterruptrequestisgeneratedwhileaninterruptwithprioritylowerthantheinterruptlatchIL15(INTADC)isbeingaccepted,theINTADCinterruptlatchmaybeclearedwithouttheINTADCinterruptbeingprocessed.
Fordetails,refertothecorrespondingnotesinthechapterontheADconverter.
3.
1Interruptlatches(IL19toIL2)Aninterruptlatchisprovidedforeachinterruptsource,exceptforasoftwareinterruptandanexecutedtheunde-finedinstructioninterrupt.
Wheninterruptrequestisgenerated,thelatchissetto"1",andtheCPUisrequestedtoaccepttheinterruptifitsinterruptisenabled.
Theinterruptlatchisclearedto"0"immediatelyafteracceptinginter-rupt.
Allinterruptlatchesareinitializedto"0"duringreset.
InterruptFactorsEnableConditionInterruptLatchVectorAddressPriorityInternal/External(Reset)Non-maskable–FFFE1InternalINTSWI(Softwareinterrupt)Non-maskable–FFFC2InternalINTUNDEF(Executedtheundefinedinstructioninterrupt)Non-maskable–FFFC2InternalINTATRAP(Addresstrapinterrupt)Non-maskableIL2FFFA2InternalINTWDT(Watchdogtimerinterrupt)Non-maskableIL3FFF82ExternalINT0IMFEF4=1,INT0EN=1IL4FFF65ExternalINT1IMFEF5=1IL5FFF46InternalINTTBTIMFEF6=1IL6FFF27InternalINTTC1IMFEF7=1IL7FFF08InternalINTSIOIMFEF8=1IL8FFEE9ExternalINT2IMFEF9=1IL9FFEC10InternalINTRXDIMFEF10=1IL10FFEA11InternalINTTXDIMFEF11=1IL11FFE812InternalINTTC4IMFEF12=1IL12FFE613InternalINTTC6IMFEF13=1IL13FFE414InternalINTRTCIMFEF14=1IL14FFE215InternalINTADCIMFEF15=1IL15FFE016InternalINTTC3IMFEF16=1IL16FFBE17ExternalINT3IMFEF17=1IL17FFBC18InternalINTTC5IMFEF18=1IL18FFBA19ExternalINT5IMFEF19=1IL19FFB820-ReservedIMFEF20=1IL20FFB621-ReservedIMFEF21=1IL21FFB422-ReservedIMFEF22=1IL22FFB223-ReservedIMFEF23=1IL23FFB024Page363.
InterruptControlCircuit3.
2Interruptenableregister(EIR)TMP86FS23UGTheinterruptlatchesarelocatedonaddress002EH,003CHand003DHinSFRarea.
Eachlatchcanbeclearedto"0"individuallybyinstruction.
However,IL2andIL3shouldnotbeclearedto"0"bysoftware.
Forclearingtheinterruptlatch,loadinstructionshouldbeusedandthenIL2andIL3shouldbesetto"1".
Iftheread-modify-writeinstructionssuchasbitmanipulationoroperationinstructionsareused,interruptrequestwouldbeclearedinade-quatelyifinterruptisrequestedwhilesuchinstructionsareexecuted.
Interruptlatchesarenotsetto"1"byaninstruction.
Sinceinterruptlatchescanberead,thestatusforinterruptrequestscanbemonitoredbysoftware.
Note:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninterruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexecutedbeforesettingIMF="1".
3.
2Interruptenableregister(EIR)Theinterruptenableregister(EIR)enablesanddisablestheacceptanceofinterrupts,exceptforthenon-maskableinterrupts(Softwareinterrupt,undefinedinstructioninterrupt,addresstrapinterruptandwatchdoginterrupt).
Non-maskableinterruptisacceptedregardlessofthecontentsoftheEIR.
TheEIRconsistsofaninterruptmasterenableflag(IMF)andtheindividualinterruptenableflags(EF).
Theseregistersarelocatedonaddress002CH,003AHand003BHinSFRarea,andtheycanbereadandwrittenbyaninstructions(Includingread-modify-writeinstructionssuchasbitmanipulationoroperationinstructions).
3.
2.
1Interruptmasterenableflag(IMF)Theinterruptenableregister(IMF)enablesanddisablestheacceptanceofthewholemaskableinterrupt.
WhileIMF="0",allmaskableinterruptsarenotacceptedregardlessofthestatusoneachindividualinterruptenableflag(EF).
BysettingIMFto"1",theinterruptbecomesacceptableiftheindividualsareenabled.
Whenaninterruptisaccepted,IMFisclearedto"0"afterthelateststatusonIMFisstacked.
Thusthemaskableinter-ruptswhichfollowaredisabled.
Byexecutingreturninterruptinstruction[RETI/RETN],thestackeddata,whichwasthestatusbeforeinterruptacceptance,isloadedonIMFagain.
TheIMFislocatedonbit0inEIRL(Address:003AHinSFR),andcanbereadandwrittenbyaninstruction.
TheIMFisnormallysetandclearedby[EI]and[DI]instructionrespectively.
Duringreset,theIMFisinitial-izedto"0".
Example1:ClearsinterruptlatchesDI;IMF←0LDW(ILL),1110100000111111B;IL12,IL10toIL6←0EI;IMF←1Example2:ReadsinterruptlatchessLDWA,(ILL);W←ILH,A←ILLExample3:TestsinterruptlatchesTEST(ILL).
7;ifIL7=1thenjumpJRF,SSETPage37TMP86FS23UG3.
2.
2Individualinterruptenableflags(EF19toEF4)Eachoftheseflagsenablesanddisablestheacceptanceofitsmaskableinterrupt.
Settingthecorrespondingbitofanindividualinterruptenableflagto"1"enablesacceptanceofitsinterrupt,andsettingthebitto"0"dis-ablesacceptance.
Duringreset,alltheindividualinterruptenableflags(EF19toEF4)areinitializedto"0"andallmaskableinterruptsarenotaccepteduntiltheyaresetto"1".
Note:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenor-mallyoninterruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulat-ingEForILshouldbeexecutedbeforesettingIMF="1".
Example1:EnablesinterruptsindividuallyandsetsIMFDI;IMF←0LDW:(EIRL),1110100010100000B;EF15toEF13,EF11,EF7,EF5←1Note:IMFshouldnotbeset.
:EI;IMF←1Example2:Ccompilerdescriptionexampleunsignedint_io(3AH)EIRL;/*3AHshowsEIRLaddress*/_DI();EIRL=10100000B;:_EI();Page383.
InterruptControlCircuit3.
2Interruptenableregister(EIR)TMP86FS23UGNote1:ToclearanyoneofbitsIL7toIL4,besuretowrite"1"intoIL2andIL3.
Note2:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninter-ruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexe-cutedbeforesettingIMF="1".
Note3:DonotclearILwithread-modify-writeinstructionssuchasbitoperations.
Note1:*:Don'tcareNote2:DonotsetIMFandtheinterruptenableflag(EF15toEF4)to"1"atthesametime.
Note3:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninter-ruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexe-cutedbeforesettingIMF="1".
InterruptLatches(Initialvalue:00000000000000**)ILH,ILL(003DH,003CH)1514131211109876543210IL15IL14IL13IL12IL11IL10IL9IL8IL7IL6IL5IL4IL3IL2ILH(003DH)ILL(003CH)(Initialvalue:****0000)ILE(002EH)76543210IL19IL18IL17IL16ILE(002EH)IL19toIL2InterruptlatchesatRD0:Nointerruptrequest1:InterruptrequestatWR0:Clearstheinterruptrequest1:(Interruptlatchisnotset.
)R/WInterruptEnableRegisters(Initialvalue:000000000000***0)EIRH,EIRL(003BH,003AH)1514131211109876543210EF15EF14EF13EF12EF11EF10EF9EF8EF7EF6EF5EF4IMFEIRH(003BH)EIRL(003AH)(Initialvalue:****0000)EIRE(002CH)76543210EF19EF18EF17EF16EIRE(002CH)EF19toEF4Individual-interruptenableflag(Specifiedforeachbit)0:1:Disablestheacceptanceofeachmaskableinterrupt.
Enablestheacceptanceofeachmaskableinterrupt.
R/WIMFInterruptmasterenableflag0:1:DisablestheacceptanceofallmaskableinterruptsEnablestheacceptanceofallmaskableinterruptsPage39TMP86FS23UG3.
3InterruptSequenceAninterruptrequest,whichraisedinterruptlatch,isheld,untilinterruptisacceptedorinterruptlatchisclearedto"0"byresettingoraninstruction.
Interruptacceptancesequencerequires8machinecycles(2s@16MHz)afterthecompletionofthecurrentinstruction.
Theinterruptservicetaskterminatesuponexecutionofaninterruptreturninstruction[RETI](formaskableinterrupts)or[RETN](fornon-maskableinterrupts).
Figure3-1showsthetimingchartofinterruptacceptanceprocessing.
3.
3.
1Interruptacceptanceprocessingispackagedasfollows.
a.
Theinterruptmasterenableflag(IMF)isclearedto"0"inordertodisabletheacceptanceofanyfol-lowinginterrupt.
b.
Theinterruptlatch(IL)fortheinterruptsourceacceptedisclearedto"0".
c.
Thecontentsoftheprogramcounter(PC)andtheprogramstatusword,includingtheinterruptmasterenableflag(IMF),aresaved(Pushed)onthestackinsequenceofPSW+IMF,PCH,PCL.
Mean-while,thestackpointer(SP)isdecrementedby3.
d.
Theentryaddress(Interruptvector)ofthecorrespondinginterruptserviceprogram,loadedonthevec-tortable,istransferredtotheprogramcounter.
e.
Theinstructionstoredattheentryaddressoftheinterruptserviceprogramisexecuted.
Note:WhenthecontentsofPSWaresavedonthestack,thecontentsofIMFarealsosaved.
Note1:a:Returnaddressentryaddress,b:Entryaddress,c:AddresswhichRETIinstructionisstoredNote2:Onconditionthatinterruptisenabled,ittakes38/fc[s]or38/fs[s]atmaximum(Iftheinterruptlatchissetatthefirstmachinecycleon10cycleinstruction)tostartinterruptacceptanceprocessingsinceitsinterruptlatchisset.
Figure3-1TimingChartofInterruptAcceptance/ReturnInterruptInstructionExample:CorrespondencebetweenvectortableaddressforINTTBTandtheentryaddressoftheinterruptserviceprogramFigure3-2Vectortableaddress,Entryaddressabac+1ExecuteinstructionSPPCExecuteinstructionnn2n-3n2n1n1na+2a+1c+2b+3b+2b+1a+1aa1ExecuteRETIinstructionInterruptacceptanceExecuteinstructionInterruptservicetask1-machinecycleInterruptrequestInterruptlatch(IL)IMFD2H03HD203HD204H06HVectortableaddressEntryaddress0FHVectorInterruptserviceprogramFFF2HFFF3HPage403.
InterruptControlCircuit3.
3InterruptSequenceTMP86FS23UGAmaskableinterruptisnotaccepteduntiltheIMFissetto"1"evenifthemaskableinterrupthigherthanthelevelofcurrentservicinginterruptisrequested.
Inordertoutilizenestedinterruptservice,theIMFissetto"1"intheinterruptserviceprogram.
Inthiscase,acceptableinterruptsourcesareselectivelyenabledbytheindividualinterruptenableflags.
Toavoidoverloadednesting,cleartheindividualinterruptenableflagwhoseinterruptiscurrentlyserviced,beforesettingIMFto"1".
Asfornon-maskableinterrupt,keepinterruptserviceshortencomparedwithlengthbetweeninterruptrequests;otherwisethestatuscannotberecoveredasnon-maskableinterruptwouldsimplynested.
3.
3.
2Saving/restoringgeneral-purposeregistersDuringinterruptacceptanceprocessing,theprogramcounter(PC)andtheprogramstatusword(PSW,includesIMF)areautomaticallysavedonthestack,buttheaccumulatorandothersarenot.
Theseregistersaresavedbysoftwareifnecessary.
Whenmultipleinterruptservicesarenested,itisalsonecessarytoavoidusingthesamedatamemoryareaforsavingregisters.
Thefollowingmethodsareusedtosave/restorethegeneral-purposeregisters.
3.
3.
2.
1UsingPUSHandPOPinstructionsIfonlyaspecificregisterissavedorinterruptsofthesamesourcearenested,general-purposeregisterscanbesaved/restoredusingthePUSH/POPinstructions.
Figure3-3Save/storeregisterusingPUSHandPOPinstructions3.
3.
2.
2UsingdatatransferinstructionsTosaveonlyaspecificregisterwithoutnestedinterrupts,datatransferinstructionsareavailable.
Example:Save/storeregisterusingPUSHandPOPinstructionsPINTxx:PUSHWA;SaveWAregister(interruptprocessing)POPWA;RestoreWAregisterRETI;RETURNPCLPCHPSWAtacceptanceofaninterruptAtexecutionofPUSHinstructionAtexecutionofRETIinstructionAtexecutionofPOPinstructionb-4b-3b-2b-1bPCLPCHPSWPCLPCHPSWSPAddress(Example)SPSPSPAWb-5Page41TMP86FS23UGFigure3-4Saving/RestoringGeneral-purposeRegistersunderInterruptProcessing3.
3.
3InterruptreturnInterruptreturninstructions[RETI]/[RETN]performasfollows.
Asforaddresstrapinterrupt(INTATRAP),itisrequiredtoalterstackeddataforprogramcounter(PC)torestartingaddress,duringinterruptserviceprogram.
Note:If[RETN]isexecutedwiththeabovedataunaltered,theprogramreturnstotheaddresstrapareaandINTATRAPoccursagain.
Wheninterruptacceptanceprocessinghascompleted,stackeddataforPCLandPCHarelocatedonaddress(SP+1)and(SP+2)respectively.
Example:Save/storeregisterusingdatatransferinstructionsPINTxx:LD(GSAVA),A;SaveAregister(interruptprocessing)LDA,(GSAVA);RestoreAregisterRETI;RETURN[RETI]/[RETN]InterruptReturn1.
Programcounter(PC)andprogramstatusword(PSW,includesIMF)arerestoredfromthestack.
2.
Stackpointer(SP)isincrementedby3.
Example1:Returningfromaddresstrapinterrupt(INTATRAP)serviceprogramPINTxx:POPWA;RecoverSPby2LDWA,ReturnAddress;PUSHWA;Alterstackeddata(interruptprocessing)RETN;RETURNInterruptacceptanceInterruptservicetaskRestoringregistersSavingregistersInterruptreturnSaving/Restoringgeneral-purposeregistersusingPUSH/POPdatatransferinstructionMaintaskPage423.
InterruptControlCircuit3.
4SoftwareInterrupt(INTSW)TMP86FS23UGInterruptrequestsaresampledduringthefinalcycleoftheinstructionbeingexecuted.
Thus,thenextinter-ruptcanbeacceptedimmediatelyaftertheinterruptreturninstructionisexecuted.
Note1:ItisrecommendedthatstackpointerbereturntoratebeforeINTATRAP(Increment3times),ifreturninter-ruptinstruction[RETN]isnotutilizedduringinterruptserviceprogramunderINTATRAP(suchasExample2).
Note2:Whentheinterruptprocessingtimeislongerthantheinterruptrequestgenerationtime,theinterruptservicetaskisperformedbutnotthemaintask.
3.
4SoftwareInterrupt(INTSW)ExecutingtheSWIinstructiongeneratesasoftwareinterruptandimmediatelystartsinterruptprocessing(INTSWishighestprioritizedinterrupt).
UsetheSWIinstructiononlyfordetectionoftheaddresserrororfordebugging.
3.
4.
1AddresserrordetectionFFHisreadifforsomecausesuchasnoisetheCPUattemptstofetchaninstructionfromanon-existentmemoryaddressduringsinglechipmode.
CodeFFHistheSWIinstruction,soasoftwareinterruptisgener-atedandanaddresserrorisdetected.
TheaddresserrordetectionrangecanbefurtherexpandedbywritingFFHtounusedareasoftheprogrammemory.
AddresstrapresetisgeneratedincasethataninstructionisfetchedfromRAM,DBRorSFRareas.
3.
4.
2DebuggingDebuggingefficiencycanbeincreasedbyplacingtheSWIinstructionatthesoftwarebreakpointsettingaddress.
3.
5UndefinedInstructionInterrupt(INTUNDEF)TakingcodewhichisnotdefinedasauthorizedinstructionforinstructioncausesINTUNDEF.
INTUNDEFisgen-eratedwhentheCPUfetchessuchacodeandtriestoexecuteit.
INTUNDEFisacceptedevenifnon-maskableinter-ruptisinprocess.
ContemporaryprocessisbrokenandINTUNDEFinterruptprocessstarts,soonafteritisrequested.
Note:Theundefinedinstructioninterrupt(INTUNDEF)forcesCPUtojumpintovectoraddress,assoftwareinterrupt(SWI)does.
3.
6AddressTrapInterrupt(INTATRAP)Fetchinginstructionfromunauthorizedareaforinstructions(Addresstrappedarea)causesresetoutputoraddresstrapinterrupt(INTATRAP).
INTATRAPisacceptedevenifnon-maskableinterruptisinprocess.
Contemporarypro-cessisbrokenandINTATRAPinterruptprocessstarts,soonafteritisrequested.
Note:Theoperatingmodeunderaddresstrapped,whethertoberesetoutputorinterruptprocessing,isselectedonwatchdogtimercontrolregister(WDTCR).
Example2:Restartingwithoutreturninginterrupt(Inthiscase,PSW(IncludesIMF)beforeinterruptacceptanceisdiscarded.
)PINTxx:INCSP;RecoverSPby3INCSP;INCSP;(interruptprocessing)LDEIRL,data;SetIMFto"1"orclearitto"0"JPRestartAddress;JumpintorestartingaddressPage43TMP86FS23UG3.
7ExternalInterruptsTheTMP86FS23UGhas5externalinterruptinputs.
Theseinputsareequippedwithdigitalnoiserejectcircuits(Pulseinputsoflessthanacertaintimeareeliminatedasnoise).
EdgeselectionisalsopossiblewithINT1toINT3.
TheINT0/P63pincanbeconfiguredaseitheranexternalinter-ruptinputpinoraninput/outputport,andisconfiguredasaninputportduringreset.
Edgeselection,noiserejectcontrolandINT0/P63pinfunctionselectionareperformedbytheexternalinterruptcontrolregister(EINTCR).
Note1:InNORMAL1/2orIDLE1/2mode,ifasignalwithnonoiseisinputonanexternalinterruptpin,ittakesamaximumof"sig-nalestablishmenttime+6/fs[s]"fromtheinputsignal'sedgetosettheinterruptlatch.
Note2:WhenINT0EN="0",IL4isnotsetevenifafallingedgeisdetectedontheINT0pininput.
Note3:Whenapinwithmorethanonefunctionisusedasanoutputandachangeoccursindataorinput/outputstatus,aninter-ruptrequestsignalisgeneratedinapseudomanner.
Inthiscase,itisnecessarytoperformappropriateprocessingsuchasdisablingtheinterruptenableflag.
SourcePinEnableConditionsReleaseEdgeDigitalNoiseRejectINT0INT0IMFEF4INT0EN=1FallingedgePulsesoflessthan2/fc[s]areeliminatedasnoise.
Pulsesof7/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT1INT1IMFEF5=1FallingedgeorRisingedgePulsesoflessthan15/fcor63/fc[s]areelimi-natedasnoise.
Pulsesof49/fcor193/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsideredtobesignals.
INT2INT2IMFEF9=1FallingedgeorRisingedgePulsesoflessthan7/fc[s]areeliminatedasnoise.
Pulsesof25/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT3INT3IMFEF17=1FallingedgeorRisingedgePulsesoflessthan7/fc[s]areeliminatedasnoise.
Pulsesof25/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT5INT5IMFEF19=1FallingedgePulsesoflessthan2/fc[s]areeliminatedasnoise.
Pulsesof7/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
Page443.
InterruptControlCircuit3.
7ExternalInterruptsTMP86FS23UGNote1:fc:High-frequencyclock[Hz],*:Don'tcareNote2:Whenthesystemclockfrequencyisswitchedbetweenhighandloworwhentheexternalinterruptcontrolregister(EINTCR)isoverwritten,thenoisecancellermaynotoperatenormally.
Itisrecommendedthatexternalinterruptsaredis-abledusingtheinterruptenableregister(EIR).
Note3:ThemaximumtimefrommodifyingINT1NCuntilanoiserejecttimeischangedis26/fc.
ExternalInterruptControlRegisterEINTCR76543210(0037H)INT1NCINT0EN--INT3ESINT2ESINT1ES(Initialvalue:00**000*)INT1NCNoiserejecttimeselect0:Pulsesoflessthan63/fc[s]areeliminatedasnoise1:Pulsesoflessthan15/fc[s]areeliminatedasnoiseR/WINT0ENP63/INT0pinconfiguration0:P63input/outputport1:INT0pin(PortP63shouldbesettoaninputmode)R/WINT3ESINT3edgeselect0:Risingedge1:FallingedgeR/WINT2ESINT2edgeselect0:Risingedge1:FallingedgeR/WINT1ESINT1edgeselect0:Risingedge1:FallingedgeR/WPage45TMP86FS23UG4.
SpecialFunctionRegister(SFR)TheTMP86FS23UGadoptsthememorymappedI/Osystem,andallperipheralcontrolanddatatransfersareper-formedthroughthespecialfunctionregister(SFR)orthedatabufferregister(DBR).
TheSFRismappedonaddress0000Hto003FH,DBRismappedonaddress0F80Hto0FFFH.
Thischaptershowsthearrangementofthespecialfunctionregister(SFR)anddatabufferregister(DBR)forTMP86FS23UG.
4.
1SFRAddressReadWrite0000HReserved0001HP1DR0002HP2DR0003HP3DR0004HP3OUTCR0005HP5DR0006HP6DR0007HP7DR0008HP8DR0009HP1CR000AHP5CR000BHP6CR1000CHP6CR2000DHP7CR000EHADCCR1000FHADCCR20010HTREG1AL0011HTREG1AM0012HTREG1AH0013HTREG1B0014HTC1CR1TC1CR0015HTC1CR20016HTC1SR-0017HRTCCR0018HTC3CR0019HTC4CR001AHTC5CR001BHTC6CR001CHTTREG3001DHTTREG4001EHTTREG5001FHTTREG60020HADCDR2-0021HADCDR1-0022HReserved0023HReserved0024HP8CR0025HUARTSRUARTCR1Page464.
SpecialFunctionRegister(SFR)4.
1SFRTMP86FS23UGNote1:Donotaccessreservedareasbytheprogram.
Note2:;Cannotbeaccessed.
Note3:Write-onlyregistersandinterruptlatchescannotusetheread-modify-writeinstructions(BitmanipulationinstructionssuchasSET,CLR,etc.
andlogicaloperationinstructionssuchasAND,OR,etc.
).
0026H-UARTCR20027HLCDCR0028HPWREG30029HPWREG4002AHPWREG5002BHPWREG6002CHEIRE002DHReserved002EHILE002FHReserved0030HReserved0031HReserved0032HReserved0033HReserved0034H-WDTCR10035H-WDTCR20036HTBTCR0037HEINTCR0038HSYSCR10039HSYSCR2003AHEIRL003BHEIRH003CHILL003DHILH003EHReserved003FHPSWAddressReadWritePage47TMP86FS23UG4.
2DBRAddressReadWrite0F80HSEG1/00F81HSEG3/20F82HSEG5/40F83HSEG7/60F84HSEG9/80F85HSEG11/100F86HSEG13/120F87HSEG15/140F88HSEG17/160F89HSEG19/180F8AHSEG21/200F8BHSEG23/220F8CHSEG25/240F8DHSEG27/260F8EHSEG29/280F8FHSEG31/300F90HSIOBR00F91HSIOBR10F92HSIOBR20F93HSIOBR30F94HSIOBR40F95HSIOBR50F96HSIOBR60F97HSIOBR70F98H-SIOCR10F99HSIOSRSIOCR20F9AH-STOPCR0F9BHRDBUFTDBUF0F9CHP2PRD-0F9DHP3PRD-0F9EHP1LCR0F9FHP5LCRPage484.
SpecialFunctionRegister(SFR)4.
2DBRTMP86FS23UGAddressReadWrite0FA0HP7LCR0FA1HP8LCR0FA2HReserved0FA3HReserved0FA4HMACCR0FA5HMACSR-0FA6HMPLDRL0FA7HMPLDRH0FA8HMPCDRL0FA9HMPCDRH0FAAHRCALDR1MADDR10FABHRCALDR2MADDR20FACHRCALDR3MADDR30FADHRCALDR4MADDR40FAEHReserved0FAFHReserved0FB0HReserved0FB1HReserved0FB2HReserved0FB3HReserved0FB4HReserved0FB5HReserved0FB6HReserved0FB7HReserved0FB8HReserved0FB9HReserved0FBAHReserved0FBBHReserved0FBCHReserved0FBDHReserved0FBEHReserved0FBFHReservedAddressReadWrite0FC0HReserved::::0FDFHReservedPage49TMP86FS23UGNote1:Donotaccessreservedareasbytheprogram.
Note2:;Cannotbeaccessed.
Note3:Write-onlyregistersandinterruptlatchescannotusetheread-modify-writeinstructions(BitmanipulationinstructionssuchasSET,CLR,etc.
andlogicaloperationinstructionssuchasAND,OR,etc.
).
AddressReadWrite0FE0HReserved0FE1HReserved0FE2HReserved0FE3HReserved0FE4HReserved0FE5HReserved0FE6HReserved0FE7HReserved0FE8HReserved0FE9H-FLSSTB0FEAHSPCR0FEBHReserved0FECHReserved0FEDHReserved0FEEHReserved0FEFHReserved0FF0HReserved0FF1HReserved0FF2HReserved0FF3HReserved0FF4HReserved0FF5HReserved0FF6HReserved0FF7HReserved0FF8HReserved0FF9HReserved0FFAHReserved0FFBHReserved0FFCHReserved0FFDHReserved0FFEHReserved0FFFHFLSCRPage504.
SpecialFunctionRegister(SFR)4.
2DBRTMP86FS23UGPage51TMP86FS23UG5.
I/OPortsTheTMP86FS23UGhas7parallelinput/outputports(48pins)andoutputports(3pins)asfollows.
Eachoutputportcontainsalatch,whichholdstheoutputdata.
Allinputportsdonothavelatches,sotheexternalinputdatashouldbeexternallyhelduntiltheinputdataisreadfromoutsideorreadingshouldbeperformedseveraltimerbeforeprocessing.
Figure5-1showsinput/outputtimingexamples.
ExternaldataisreadfromanI/OportintheS1stateofthereadcycleduringexecutionofthereadinstruction.
Thistimingcannotberecognizedfromoutside,sothattransientinputsuchaschatteringmustbeprocessedbythepro-gram.
OutputdatachangesintheS2stateofthewritecycleduringexecutionoftheinstructionwhichwritestoanI/Oport.
Note:Thepositionsofthereadandwritecyclesmayvary,dependingontheinstruction.
Figure5-1Input/OutputTiming(Example)PrimaryFunctionSecondaryFunctionsPortP18-bitI/OportExternalinterruptinput,UARTinput/output,SerialPROMmodecontrolinputandsegmentoutput.
PortP23-bitI/OportLow-frequencyresonatorconnections,externalinterruptinput,STOPmodereleasesignalinput.
PortP35-bitI/OportTimer/counterinput/outputserialinterfaceinput/outputanddivideroutput.
3-bitI/OportTimer/counterinput/output.
PortP58-bitI/OportLCDsegmentoutput.
PortP68-bitI/OportAnaloginput,externalinterruptinput,timer/counterinputandSTOPmodereleasesignalinput.
PortP78-bitI/OportLCDsegmentoutput.
PortP88-bitI/OportLCDsegmentoutput.
InstructionexecutioncycleInputstrobeDatainputEx:LDA,(x)FetchcycleFetchcycleReadcycleS0S1S2S3S0S1S2S3S0S1S2S3InstructionexecutioncycleOutputstrobeDataoutputEx:LD(x),AFetchcycleFetchcycleWritecycleS0S1S2S3S0S1S2S3S0S1S2S3(a)Inputtiming(b)OutputtimingOldNewPage525.
I/OPorts5.
1PortP1(P17toP10)TMP86FS23UG5.
1PortP1(P17toP10)PortP1isan8-bitinput/outputportwhichcanbeconfiguredasaninputoranoutputinone-bitunit.
PortP1isalsousedasaUARTinput/output,anexternalinterruptinput,aserialPROMmodecontrolinputandsegmentoutputofLCD.
Input/outputmodeisspecifiedbytheP1controlregister(P1CR).
Whenusedasaninputportorasecondaryfunctioninputpins(UARTinputorexternalinterruptinput),thecorre-spondingbitofP1CRandP1LCRshouldbeclearedto"0".
Whenusedasanoutputport,thecorrespondingbitofP1CRshouldbesetto"1",andtherespectiveP1LCRbitshouldbeclearedto"0".
WhenusedasanUARToutputpin,thecorrespondingbitofP1CRandtheoutputlatch(P1DR)shouldbesetto"1",andtherespectiveP1LCRbitshouldbeclearedto"0".
WhenusedasasegmentpinsofLCD,therespectivebitofP1LCRshouldbesetto"1".
Duringreset,theP1DR,P1CRandP1LCRareinitializedto"0".
WhenthebitofP1CRandP1LCRis"0",thecorrespondingbitdatabyreadinstructionisaterminalinputdata.
WhenthebitofP1CRis"0"andthatofP1LCRis"1",thecorrespondingbitdatabyreadinstructionisalways"0".
WhenthebitofP1CRis"1",thecorrespondingbitdatabyreadinstructionisthevalueofP1DR.
Note:Asterisk(*)indicates"1"or"0"eitherofwhichcanbeselected.
Table5-1RegisterProgrammingforMulti-functionPortsFunctionProgrammedValueP1DRP1CRP1LCRPortinput,UARTinput,andexternalinterruptinput*"0""0"Port"0"output"0""1""0"Port"1"outputandUARToutput"1""1""0"LCDsegmentoutput**"1"Table5-2ValuesReadfromP1DRandRegisterProgrammingConditionsValuesReadfromP1DRP1CRP1LCR"0""0"Terminalinputdata"0""1""0""1""0"Outputlatchcontents"1"Page53TMP86FS23UGFigure5-2PortP1Note:Theportplacedininputmodereadsthepininputstate.
Therefore,whentheinputandoutputmodesareusedtogether,theoutputlatchcontentsfortheportininputmodemightbechangedbyexecutingabitmanipulationinstruction.
P1DR(0001H)R/W76543210P17SEG24P16SEG25P15SEG26P14SEG27INT3P13SEG28INT2P12SEG29INT1P11SEG30TXDP10SEG31RXDBOOT(Initialvalue:00000000)P1LCR(0F9EH)76543210(Initialvalue:00000000)P1LCRPortP1/segmentoutputcontrol(setforeachbitindividually)0:P1input/outputportorsecondaryfunction(expectforsegment)1:LCDsegmentoutputR/WP1CR(0009H)76543210(Initialvalue:00000000)P1CRP1portinput/outputcontrol(setforeachbitindividually)0:Inputmode1:OutputmodeR/WP1LCRiOutputlatchDataoutput(P1DRi)LCDdataoutputControloutputSTOPOUTENP1LCRiinputP1CRiP1CRiinputDatainput(P1DRi)ControlinputP1iNote:i=7to0DQDQDQPage545.
I/OPorts5.
2PortP2(P22toP20)TMP86FS23UG5.
2PortP2(P22toP20)PortP2isa3-bitinput/outputport.
Itisalsousedasanexternalinterrupt,aSTOPmodereleasesignalinput,andlow-frequencycrystaloscillatorcon-nectionpins.
Whenusedasaninputportorasecondaryfunctionpins,respectiveoutputlatch(P2DR)shouldbesetto"1".
Duringreset,theP2DRisinitializedto"1".
Alow-frequencycrystaloscillator(32.
768kHz)isconnectedtopinsP21(XTIN)andP22(XTOUT)inthedual-clockmode.
Inthesingle-clockmode,pinsP21andP22canbeusedasnormalinput/outputports.
ItisrecommendedthatpinP20shouldbeusedasanexternalinterruptinput,aSTOPmodereleasesignalinput,oraninputport.
Ifitisusedasanoutputport,theinterruptlatchissetonthefallingedgeoftheoutputpulse.
P2portoutputlatch(P2DR)andP2portterminalinput(P2PRD)arelocatedontheirrespectiveaddress.
Whenreadtheoutputlatchdata,theP2DRshouldbereadandwhenreadtheterminalinputdata,theP2PRDreg-istershouldberead.
IfareadinstructionisexecutedforportP2,readdataofbits7to3areunstable.
Figure5-3PortP2Note:PortP20isusedasSTOPpin.
Therefore,whenstopmodeisstarted,OUTENdoesnotaffecttoP20,andP20becomesHigh-Zmode.
P2DR(0002H)R/W76543210P22XTOUTP21XTINP20INT5STOP(Initialvalue:*****111)P2PRD(0F9CH)Readonly76543210P22P21P20OutputlatchOutputlatchOutputlatchDatainput(P20PRD)Outputlatchread(P21)Dataoutput(P21)Dataoutput(P20)Datainput(P20)ControlinputDatainput(P21PRD)Outputlatchread(P22)Datainput(P22PRD)Dataoutput(P22)STOPOUTENXTENfsP22(XTOUT)P21(XTIN)P20(INT5,STOP)Osc.
enableDQDQDQPage55TMP86FS23UG5.
3PortP3(P37toP30)PortP3isa3-bitoutputanda5-bitinput/outputport.
Itisalsousedasatimer/counterinput/output,serialinterfaceinput/outputordivideroutput.
Whenusedasatimer/counteroutput,serialinterfaceoutputordivideroutput,respectiveoutputlatch(P3DR)shouldbesetto"1".
ItcanbeselectedwhetheroutputcircuitofP30toP34portisC-MOSoutputorasinkopendrainindividually,bysettingP3OUTCR.
WhenacorrespondingbitofP3OUTCRis"0",theoutputcircuitisselectedtoasinkopendrainandwhenacorrespondingbitofP3OUTCRis"1",theoutputcircuitisselectedtoaC-MOSoutput.
Whenusedasaninputport,serialinterfaceinputortimer/counterinput,respectiveoutputcontrol(P3OUTCR)shouldbesetto"0"afterP3DRissetto"1".
Duringreset,theP3DRisinitializedto"1",andtheP3OUTCRisinitializedto"0".
P3portoutputlatch(P3DR)andP3portterminalinput(P3PRD)arelocatedontheirrespectiveaddress.
Whenreadtheoutputlatchdata,theP3DRshouldbereadandwhenreadtheterminalinputdata,theP3PRDreg-istershouldberead.
IfareadinstructionisexecutedfortheP3PRDandtheP3OUTCR,readdataofbits7to5areunstable.
Figure5-4PortP3Table5-3RegisterProgrammingforMulti-functionports(P34toP30)FunctionProgrammedValueP3DRP3OUTCRPortinput,serialinterfaceinput,ortimercounterinput"1""0"Port"0"output"0"ProgrammingforeachapplicationsPort"1"output,serialinterfaceoutput,ortimercounteroutput"1"Table5-4RegisterProgrammingforMulti-function(P37toP35)FunctionProgrammedValueP3DRPort"0"output"0"Port"1"output,timercounteroutput,ordivideroutput"1"OutputlatchDatainput(P3PRD)Outputlatchread(P3DR)Outputlatchread(P3DRj)ControlinputSTOPOUTENSTOPOUTENP3OUTCRiinputControloutputControloutputDataoutput(P3DR)P3OUTCRiP3iNote:i=4to0OutputlatchDataoutput(P3DRj)P3jNote:j=7to5DQDQDQPage565.
I/OPorts5.
3PortP3(P37toP30)TMP86FS23UGP3DR(0003H)R/W76543210P37DVOP36PWM3PDO3P35PWM4PDO4PPG4P34PWM5PDO5TC5P33PWM6PDO6PPG6TC6P32SCKP31SOTC3P30SITC4(Initialvalue:1111111)P3OUTCR(0004H)76543210(Initialvalue:***00000)P3OUTCRPortP3outputcircuitcontrol(setforeachbitindividually)0:Sinkopen-drainoutput1:C-MOSoutputR/WP3PRD(0F9DH)Readonly76543210P34P33P32P31P30Page57TMP86FS23UG5.
4PortP5(P57toP50)PortP5isan8-bitinput/outputportwhichcanbeconfiguredasaninputoranoutputinone-bitunit.
PortP5isalsousedasasegmentoutputofLCD.
Input/outputmodeisspecifiedbytheP5controlregister(P5CR).
Whenusedasaninputport,thecorrespondingbitofP5CRandP5LCRshouldbeclearedto"0".
Whenusedasanoutputport,thecorrespondingbitofP5CRshouldbesetto"1",andtherespectiveP5LCRbitshouldbeclearedto"0".
WhenusedasasegmentpinsofLCD,therespectivebitofP5LCRshouldbesetto"1".
Duringreset,theoutputlatch(P5DR),P5CRandP5LCRareinitializedto"0".
WhenthebitofP5CRandP5LCRis"0",thecorrespondingbitdatabyreadinstructionisaterminalinputdata.
WhenthebitofP5CRis"0"andthatofP5LCRis"1",thecorrespondingbitdatabyreadinstructionisalways"0".
WhenthebitofP5CRis"1",thecorrespondingbitdatabyreadinstructionisthevalueofP5DR.
Note:Asterisk(*)indicates"1"or"0"eitherofwhichcanbeselected.
Figure5-5PortP5Table5-5RegisterProgrammingforMulti-functionPortsFunctionProgrammedValueP5DRP5CRP5LCRPortinput*"0""0"Port"0"output"0""1""0"Port"1"output"1""1""0"LCDsegmentoutput**"1"Table5-6ValuesReadfromP5DRandRegisterProgrammingConditionsValuesReadfromP5DRP5CRP5LCR"0""0"Terminalinputdata"0""1""0""1""0"Outputlatchcontents"1"P5LCRiOutputlatchDataoutput(P5DRi)LCDdataoutputSTOPOUTENP5LCRiinputP5CRiP5CRiinputDatainput(P5DRi)P5iNote:i=7to0DQDQDQPage585.
I/OPorts5.
4PortP5(P57toP50)TMP86FS23UGNote:Theportplacedininputmodereadsthepininputstate.
Therefore,whentheinputandoutputmodesareusedtogether,theoutputlatchcontentsfortheportininputmodemightbechangedbyexecutingabitmanipulationinstruction.
P5DR(0005H)R/W76543210P57SEG16P56SEG17P55SEG18P54SEG19P53SEG20P52SEG21P51SEG22P50SEG23(Initialvalue:00000000)P5LCR(0F9FH)76543210(Initialvalue:00000000)P5LCRPortP5/segmentoutputcontrol(Setforeachbitindividually)0:P5input/outputport1:LCDsegmentoutputR/WP5CR(000AH)76543210(Initialvalue:00000000)P5CRP5portinput/outputcontrol(Setforeachbitindividually)0:Inputmode1:OutputmodeR/WPage59TMP86FS23UG5.
5PortP6(P67toP60)PortP6isan8-bitinput/outputportwhichcanbeconfiguredasaninputoranoutputinone-bitunit.
PortP6isalsousedasananaloginput,KeyonWakeupinput,timer/counterinputandexternalinterruptinput.
Input/outputmodeisspecifiedbytheP6controlregister(P6CR1)andinputcontrolregister(P6CR2).
Whenusedasanoutputport,thecorrespondingbitofP6CR1shouldbesetto"1".
Whenusedasaninputport,timer/counterinputoranexternalinterruptinput,thecorrespondingbitofP6CR1shouldbeclearedto"0",andthen,thecorrespondingbitofP6CR2shouldbesetto"1".
Whenusedasananaloginputorkeyonwakeupinput,thecorrespondingbitofP6CR1shouldbeclearedto"0",andthen,thecorrespondingbitofP6CR2shouldbeclearedto"0".
Theoutputlatchofeachdigitalinputportwithmultiplefunctionsshouldbesetto"0"topreventflow-throughcur-rent.
Therefore,theoutputlatchofeachporttobeusedforanaloginputshouldbepreprogrammedto"0".
Thecon-versioninputchanneltobeusedisactuallyselectedbyADCCR1.
Duringreset,theoutputlatch(P6DR)andP6CR1areinitializedto0",P6CR2isinitializedto"1".
WhenthebitofP6CR1andP6CR2is"0",thecorrespondingbitdatabyreadinstructionisalways"0".
WhenthebitofP6CR1is"0"andthatofP6CR2is"1",thecorrespondingbitdatabyreadinstructionisaterminalinputdata.
WhenthebitofP6CR1is"1",thecorrespondingbitdatabyreadinstructionisthevalueofP6DR.
Note:Asterisk(*)indicates"1"or"0"eitherofwhichcanbeselected.
Table5-7RegisterProgrammingforMulti-functionPortsFunctionProgrammedValueP6DRP6CR1P6CR2Portinputexternalinterruptinputortimercounterinput*"0""1"Analoginputorkey-onwake-upinput*"0""0"Port"0"output"0""1"*Port"1"output"1""1"*Table5-8ValuesReadfromP6DRandRegisterProgrammingConditionsValuesReadfromP6DRP6CR1P6CR2"0""0""0""0""1"Terminalinputdata"1""0"Outputlatchcontents"1"Page605.
I/OPorts5.
5PortP6(P67toP60)TMP86FS23UGFigure5-6PortP6Note1:Theportplacedininputmodereadsthepininputstate.
Therefore,whentheinputandoutputmodesareusedtogether,theoutputlatchcontentsfortheportininputmodemightbechangedbyexecutingabitmanipulationinstruction.
Note2:Whenusedasananaloginport,besuretoclearthecorrespondingbitofP6CR2todisabletheportinput.
Note3:Donotsettheoutputmode(P6CR1="1")forthepinusedasaanaloginputpin.
Note4:PinsnotusedforanaloginputcanbeusedasI/Oports.
DuringADconversion,outputinstructionsshouldnotbeexecutedtokeepaprecision.
Inaddition,avariablesignalshouldnotbeinputtoaportadjacenttotheanaloginputduringADconversion.
ControlinputAnaloginputDataoutput(P6DR)Datainput(P6DR)STOPOUTENAINDSSAINP6CR2iinputP6CR1iinputP6CR2iP6CR1iP6iNote1:i=0to3,j=4to7,k=2to5Note2:STOPisbit7inSYSCR1Note3:SAINisADinputselectsignal.
Note4:STOPkisinputselectsignalinakeyonwakeup.
AnaloginputKeyonwakeupDataoutput(P6DR)Datainput(P6DR)STOPSTOPkOUTENAINDSSAINP6CR2jinputP6CR1jinputP6CR2jP6CR1jP6jDQDQDQDQDQDQPage61TMP86FS23UGP6DR(0006H)R/W76543210P67AIN7STOP5P66AIN6STOP4P65AIN5STOP3P64AIN4STOP2P63AIN3INT0P62AIN2ECNTP61AIN1ECINP60AIN0(Initialvalue:00000000)P6CR1(000BH)76543210(Initialvalue:00000000)P6CR1I/OcontrolforportP6(Specifiedforeachbit)0:Portinput,Keyonwakeupinput,Analoginput,externalinterruptinputortimercounterinput1:PortoutputR/WP6CR2(000CH)76543210(Initialvalue:11111111)P6CR2P6portinputcontrol(Specifiedforeachbit)0:AnaloginputorKeyonwakeupinput1:Portinput,externalinterruptinputortimercounterinputR/WPage625.
I/OPorts5.
6PortP7(P77toP70)TMP86FS23UG5.
6PortP7(P77toP70)PortP7isan8-bitinput/outputportwhichcanbeconfiguredasaninputoranoutputinone-bitunit.
PortP7isalsousedasasegmentoutputofLCD.
Input/outputmodeisspecifiedbytheP7controlregister(P7CR).
Whenusedasaninputport,thecorrespondingbitofP7CRandP7LCRshouldbeclearedto"0".
Whenusedasanoutputport,thecorrespondingbitofP7CRshouldbesetto"1",andtherespectiveP7LCRbitshouldbeclearedto"0".
WhenusedasasegmentpinsofLCD,therespectivebitofP7LCRshouldbesetto"1".
Duringreset,theoutputlatch(P7DR),P7CRandP7LCRareinitializedto"0".
WhenthebitofP7CRandP7LCRis"0",thecorrespondingbitdatabyreadinstructionisaterminalinputdata.
WhenthebitofP7CRis"0"andthatofP7LCRis"1",thecorrespondingbitdatabyreadinstructionisalways"0".
WhenthebitofP7CRis"1",thecorrespondingbitdatabyreadinstructionisthevalueofP7DR.
Note:Asterisk(*)indicates"1"or"0"eitherofwhichcanbeselected.
Figure5-7PortP7Table5-9RegisterProgrammingforMulti-functionPortsFunctionProgrammedValueP7DRP7CRP7LCRPortinput*"0""0"Port"0"output"0""1""0"Port"1"output"1""1""0"LCDsegmentoutput**"1"Table5-10ValuesReadfromP7DRandRegisterProgrammingConditionsValuesReadfromP7DRP7CRP7LCR"0""0"Terminalinputdata"0""1""0""1""0"Outputlatchcontents"1"P7LCRiOutputlatchDataoutput(P7DRi)LCDdataoutputSTOPOUTENP7LCRiinputP7CRiP7CRiinputDatainput(P7DRi)P7iNote:i=7to0DQDQDQPage63TMP86FS23UGNote:Theportplacedininputmodereadsthepininputstate.
Therefore,whentheinputandoutputmodesareusedtogether,theoutputlatchcontentsfortheportininputmodemightbechangedbyexecutingabitmanipulationinstruction.
P7DR(0007H)R/W76543210P77SEG8P76SEG9P75SEG10P74SEG11P73SEG12P72SEG13P71SEG14P70SEG15(Initialvalue:00000000)P7LCR(0FA0H)76543210(Initialvalue:00000000)P7LCRPortP7/segmentoutputcontrol(setforeachbitindividually)0:P7input/outputport1:SegmentoutputR/WP7CR(000DH)76543210(Initialvalue:00000000)P7CRP7portinput/outputcontrol(setforeachbitindividually)0:Inputmode1:OutputmodeR/WPage645.
I/OPorts5.
7PortP8(P87toP80)TMP86FS23UG5.
7PortP8(P87toP80)PortP8isan8-bitinput/outputportwhichcanbeconfiguredasaninputoranoutputinone-bitunit.
PortP8isalsousedasasegmentoutputofLCD.
Input/outputmodeisspecifiedbytheP8controlregister(P8CR).
Whenusedasaninputport,thecorrespondingbitofP8CRandP8LCRshouldbeclearedto"0".
Whenusedasanoutputport,thecorrespondingbitofP8CRshouldbesetto"1",andtherespectiveP8LCRbitshouldbeclearedto"0".
WhenusedasasegmentpinsofLCD,therespectivebitofP8LCRshouldbesetto"1".
Duringreset,theoutputlatch(P8DR),P8CRandP8LCRareinitializedto"0".
WhenthebitofP8CRandP8LCRis"0",thecorrespondingbitdatabyreadinstructionisaterminalinputdata.
WhenthebitofP8CRis"0"andthatofP8LCRis"1",thecorrespondingbitdatabyreadinstructionisalways"0".
WhenthebitofP8CRis"1",thecorrespondingbitdatabyreadinstructionisthevalueofP8DR.
Note:Asterisk(*)indicates"1"or"0"eitherofwhichcanbeselected.
Figure5-8PortP8Table5-11RegisterProgrammingforMulti-functionportsFunctionPortInputP8DRP8CRP8LCRPortinput*"0""0"Port"0"output"0""1""0"Port"1"output"1""1""0"LCDsegmentoutput**"1"Table5-12ValuesReadfromP8DRandRegisterProgrammingConditionsValuesReadfromP8DRP8CRP8LCR"0""0"Terminalinputdata"0""1""0""1""0"Outputlatchcontents"1"P8LCRiOutputlatchDataoutput(P8DRi)LCDdataoutputSTOPOUTENP8LCRiinputP8CRiP8CRiinputDatainput(P8DRi)P8iNote:i=7to0DQDQDQPage65TMP86FS23UGNote:Theportplacedininputmodereadsthepininputstate.
Therefore,whentheinputandoutputmodesareusedtogether,theoutputlatchcontentsfortheportininputmodemightbechangedbyexecutingabitmanipulationinstruction.
P8DR(0008H)R/W76543210P87SEG0P86SEG1P85SEG2P84SEG3P83SEG4P82SEG5P81SEG6P80SEG7(Initialvalue:00000000)P8LCR(0FA1H)76543210(Initialvalue:00000000)P8LCRP8portsegmentoutputcontrol(Specifiedforeachbit)0:Input/Outputport1:LCDsegmentoutputR/WP8CR(0024H)76543210(Initialvalue:00000000)P8CRP8portinput/outputcontrol(Specifiedforeachbit)0:Inputmode1:OutputmodeR/WPage665.
I/OPorts5.
7PortP8(P87toP80)TMP86FS23UGPage67TMP86FS23UG6.
TimeBaseTimer(TBT)Thetimebasetimergeneratestimebaseforkeyscanning,dynamicdisplaying,etc.
Italsoprovidesatimebasetimerinterrupt(INTTBT).
6.
1TimeBaseTimer6.
1.
1ConfigurationFigure6-1TimeBaseTimerconfiguration6.
1.
2ControlTimeBaseTimeriscontroledbyTimeBaseTimercontrolregister(TBTCR).
Note1:fc;High-frequencyclock[Hz],fs;Low-frequencyclock[Hz],*;Don'tcareTimeBaseTimerControlRegister76543210TBTCR(0036H)(DVOEN)(DVOCK)(DV7CK)TBTENTBTCK(InitialValue:00000000)TBTENTimeBaseTimerenable/disable0:Disable1:EnableTBTCKTimeBaseTimerinterruptFrequencyselect:[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2SLEEP1/2ModeR/WDV7CK=0DV7CK=1000fc/223fs/215fs/215001fc/221fs/213fs/213010fc/216fs/28–011fc/214fs/26–100fc/213fs/25–101fc/212fs/24–110fc/211fs/23–111fc/29fs/2–fc/223orfs/215fc/221orfs/213fc/216orfs/28fc/214orfs/26fc/213orfs/25fc/212orfs/24fc/211orfs/23fc/29orfs/2TBTCRTBTENTBTCK3MPXSourceclockFallingedgedetectorTimebasetimercontrolregisterINTTBTinterruptrequestIDLE0,SLEEP0releaserequestPage686.
TimeBaseTimer(TBT)6.
1TimeBaseTimerTMP86FS23UGNote2:Theinterruptfrequency(TBTCK)mustbeselectedwiththetimebasetimerdisabled(TBTEN="0").
(Theinterruptfre-quencymustnotbechangedwiththedisablefromtheenablestate.
)Bothfrequencyselectionandenablingcanbeper-formedsimultaneously.
6.
1.
3FunctionAnINTTBT(TimeBaseTimerInterrupt)isgeneratedonthefirstfallingedgeofsourceclock(ThedivideroutputofthetiminggeneratowhichisselectedbyTBTCK.
)aftertimebasetimerhasbeenenabled.
Thedividerisnotclearedbytheprogram;therefore,onlythefirstinterruptmaybegeneratedaheadofthesetinterruptperiod(Figure6-2).
Figure6-2TimeBaseTimerInterruptExample:Setthetimebasetimerfrequencytofc/216[Hz]andenableanINTTBTinterrupt.
LD(TBTCR),00000010B;TBTCK←010LD(TBTCR),00001010B;TBTEN←1DI;IMF←0SET(EIRL).
6Table6-1TimeBaseTimerInterruptFrequency(Example:fc=16.
0MHz,fs=32.
768kHz)TBTCKTimeBaseTimerInterruptFrequency[Hz]NORMAL1/2,IDLE1/2ModeNORMAL1/2,IDLE1/2ModeSLOW1/2,SLEEP1/2ModeDV7CK=0DV7CK=10001.
91110017.
6344010244.
14128–011976.
56512–1001953.
131024–1013906.
252048–1107812.
54096–1113125016384–SourceclockEnableTBTInterruptperiodTBTCRINTTBTPage69TMP86FS23UG6.
2DividerOutput(DVO)Approximately50%dutypulsecanbeoutputusingthedivideroutputcircuit,whichisusefulforpiezoelectricbuzzerdrive.
DivideroutputisfromDVOpin.
6.
2.
1ConfigurationFigure6-3DividerOutput6.
2.
2ControlTheDividerOutputiscontrolledbytheTimeBaseTimerControlRegister.
Note:Selectionofdivideroutputfrequency(DVOCK)mustbemadewhiledivideroutputisdisabled(DVOEN="0").
Also,inotherwords,whenchangingthestateofthedivideroutputfrequencyfromenabled(DVOEN="1")todisable(DVOEN="0"),donotchangethesettingofthedivideroutputfrequency.
TimeBaseTimerControlRegister76543210TBTCR(0036H)DVOENDVOCK(DV7CK)(TBTEN)(TBTCK)(Initialvalue:00000000)DVOENDivideroutputenable/disable0:Disable1:EnableR/WDVOCKDividerOutput(DVO)frequencyselection:[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2SLEEP1/2ModeR/WDV7CK=0DV7CK=100fc/213fs/25fs/2501fc/212fs/24fs/2410fc/211fs/23fs/2311fc/210fs/22fs/22TBTCROutputlatchPortoutputlatchMPXDVOENTBTCRDVOpinoutputDVOCKDivideroutputcontrolregister(a)configuration(b)TimingchartDataoutput2ABCYDSDQDVOpinfc/213orfs/25fc/212orfs/24fc/211orfs/23fc/210orfs/22Page706.
TimeBaseTimer(TBT)6.
2DividerOutput(DVO)TMP86FS23UGExample:1.
95kHzpulseoutput(fc=16.
0MHz)LD(TBTCR),00000000B;DVOCK←"00"LD(TBTCR),10000000B;DVOEN←"1"Table6-2DividerOutputFrequency(Example:fc=16.
0MHz,fs=32.
768kHz)DVOCKDividerOutputFrequency[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2,SLEEP1/2ModeDV7CK=0DV7CK=1001.
953k1.
024k1.
024k013.
906k2.
048k2.
048k107.
813k4.
096k4.
096k1115.
625k8.
192k8.
192kPage71TMP86FS23UG7.
WatchdogTimer(WDT)Thewatchdogtimerisafail-safesystemtodetectrapidlytheCPUmalfunctionssuchasendlessloopsduetospu-riousnoisesorthedeadlockconditions,andreturntheCPUtoasystemrecoveryroutine.
Thewatchdogtimersignalfordetectingmalfunctionscanbeprogrammedonlyonceas"resetrequest"or"inter-ruptrequest".
Upontheresetrelease,thissignalisinitializedto"resetrequest".
Whenthewatchdogtimerisnotusedtodetectmalfunctions,itcanbeusedasthetimertoprovideaperiodicinter-rupt.
Note:Caremustbetakeninsystemdesignsincethewatchdogtimerfunctionsarenotbeoperatedcompletelyduetoeffectofdisturbingnoise.
7.
1WatchdogTimerConfigurationFigure7-1WatchdogTimerConfiguration0034HOverflowWDToutputInternalresetBinarycountersWDTOUTWritingclearcodeWritingdisablecodeWDTENWDTT20035HWatchdogtimercontrolregistersWDTCR1WDTCR2INTWDTinterruptrequestInterruptrequestResetrequestResetreleaseClockClear12ControllerQSRSRQSelectorfc/223orfs/215fc/221orfs/213fc/219orfs/211fc/217orfs/29Page727.
WatchdogTimer(WDT)7.
2WatchdogTimerControlTMP86FS23UG7.
2WatchdogTimerControlThewatchdogtimeriscontrolledbythewatchdogtimercontrolregisters(WDTCR1andWDTCR2).
Thewatch-dogtimerisautomaticallyenabledaftertheresetrelease.
7.
2.
1MalfunctionDetectionMethodsUsingtheWatchdogTimerTheCPUmalfunctionisdetected,asshownbelow.
1.
Setthedetectiontime,selecttheoutput,andclearthebinarycounter.
2.
Clearthebinarycounterrepeatedlywithinthespecifieddetectiontime.
IftheCPUmalfunctionssuchasendlessloopsorthedeadlockconditionsoccurforsomereason,thewatch-dogtimeroutputisactivatedbythebinary-counteroverflowunlessthebinarycountersarecleared.
WhenWDTCR1issetto"1"atthistime,theresetrequestisgeneratedandtheninternalhardwareisinitialized.
WhenWDTCR1issetto"0",awatchdogtimerinterrupt(INTWDT)isgenerated.
ThewatchdogtimertemporarilystopscountingintheSTOPmodeincludingthewarm-uporIDLE/SLEEPmode,andautomaticallyrestarts(continuescounting)whentheSTOP/IDLE/SLEEPmodeisinactivated.
Note:Thewatchdogtimerconsistsofaninternaldividerandatwo-stagebinarycounter.
Whentheclearcode4EHiswritten,onlythebinarycounteriscleared,butnottheinternaldivider.
Theminimumbinary-counteroverflowtime,thatdependsonthetimingatwhichtheclearcode(4EH)iswrittentotheWDTCR2register,maybe3/4ofthetimesetinWDTCR1.
Therefore,writetheclearcodeusingacycleshorterthan3/4ofthetimesettoWDTCR1.
Example:Settingthewatchdogtimerdetectiontimeto221/fc[s],andresettingtheCPUmalfunctiondetectionLD(WDTCR2),4EH:Clearsthebinarycounters.
LD(WDTCR1),00001101B:WDTT←10,WDTOUT←1LD(WDTCR2),4EH:Clearsthebinarycounters(alwaysclearsimmediatelybeforeandafterchangingWDTT).
Within3/4ofWDTdetectiontime::LD(WDTCR2),4EH:Clearsthebinarycounters.
Within3/4ofWDTdetectiontime::LD(WDTCR2),4EH:Clearsthebinarycounters.
Page73TMP86FS23UGNote1:AfterclearingWDTOUTto"0",theprogramcannotsetitto"1".
Note2:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*:Don'tcareNote3:WDTCR1isawrite-onlyregisterandmustnotbeusedwithanyofread-modify-writeinstructions.
IfWDTCR1isread,adon'tcareisread.
Note4:ToactivatetheSTOPmode,disablethewatchdogtimerorclearthecounterimmediatelybeforeenteringtheSTOPmode.
Afterclearingthecounter,clearthecounteragainimmediatelyaftertheSTOPmodeisinactivated.
Note5:ToclearWDTEN,settheregisterinaccordancewiththeproceduresshownin"1.
2.
3WatchdogTimerDisable".
Note1:ThedisablecodeisvalidonlywhenWDTCR1=0.
Note2:*:Don'tcareNote3:Thebinarycounterofthewatchdogtimermustnotbeclearedbytheinterrupttask.
Note4:Writetheclearcode4EHusingacycleshorterthan3/4ofthetimesetinWDTCR1.
7.
2.
2WatchdogTimerEnableSettingWDTCR1to"1"enablesthewatchdogtimer.
SinceWDTCR1isinitializedto"1"duringreset,thewatchdogtimerisenabledautomaticallyaftertheresetrelease.
WatchdogTimerControlRegister1WDTCR1(0034H)76543210(ATAS)(ATOUT)WDTENWDTTWDTOUT(Initialvalue:**111001)WDTENWatchdogtimerenable/disable0:Disable(WritingthedisablecodetoWDTCR2isrequired.
)1:EnableWriteonlyWDTTWatchdogtimerdetectiontime[s]NORMAL1/2modeSLOW1/2modeWriteonlyDV7CK=0DV7CK=100225/fc217/fs217/fs01223/fc215/fs215fs10221fc213/fs213fs11219/fc211/fs211/fsWDTOUTWatchdogtimeroutputselect0:Interruptrequest1:ResetrequestWriteonlyWatchdogTimerControlRegister2WDTCR2(0035H)76543210(Initialvalue:WDTCR2WriteWatchdogtimercontrolcode4EH:Clearthewatchdogtimerbinarycounter(Clearcode)B1H:Disablethewatchdogtimer(Disablecode)D2H:EnableassigningaddresstrapareaOthers:InvalidWriteonlyPage747.
WatchdogTimer(WDT)7.
2WatchdogTimerControlTMP86FS23UG7.
2.
3WatchdogTimerDisableTodisablethewatchdogtimer,settheregisterinaccordancewiththefollowingprocedures.
Settingthereg-isterinotherprocedurescausesamalfunctionofthemicrocontroller.
1.
Settheinterruptmasterflag(IMF)to"0".
2.
SetWDTCR2totheclearcode(4EH).
3.
SetWDTCR1to"0".
4.
SetWDTCR2tothedisablecode(B1H).
Note:Whilethewatchdogtimerisdisabled,thebinarycountersofthewatchdogtimerarecleared.
7.
2.
4WatchdogTimerInterrupt(INTWDT)WhenWDTCR1isclearedto"0",awatchdogtimerinterruptrequest(INTWDT)isgeneratedbythebinary-counteroverflow.
Awatchdogtimerinterruptisthenon-maskableinterruptwhichcanbeacceptedregardlessoftheinterruptmasterflag(IMF).
Whenawatchdogtimerinterruptisgeneratedwhiletheotherinterruptincludingawatchdogtimerinterruptisalreadyaccepted,thenewwatchdogtimerinterruptisprocessedimmediatelyandthepreviousinterruptisheldpending.
Therefore,ifwatchdogtimerinterruptsaregeneratedcontinuouslywithoutexecutionoftheRETNinstruction,toomanylevelsofnestingmaycauseamalfunctionofthemicrocontroller.
Togenerateawatchdogtimerinterrupt,setthestackpointerbeforesettingWDTCR1.
Example:DisablingthewatchdogtimerDI:IMF←0LD(WDTCR2),04EH:ClearsthebinarycoutnerLDW(WDTCR1),0B101H:WDTEN←0,WDTCR2←DisablecodeTable7-1WatchdogTimerDetectionTime(Example:fc=16.
0MHz,fs=32.
768kHz)WDTTWatchdogTimerDetectionTime[s]NORMAL1/2modeSLOWmodeDV7CK=0DV7CK=1002.
0974401524.
288m1110131.
072m250m250m1132.
768m62.
5m62.
5mExample:SettingwatchdogtimerinterruptLDSP,083FH:SetsthestackpointerLD(WDTCR1),00001000B:WDTOUT←0Page75TMP86FS23UG7.
2.
5WatchdogTimerResetWhenabinary-counteroverflowoccurswhileWDTCR1issetto"1",awatchdogtimerresetrequestisgenerated.
Whenawatchdogtimerresetrequestisgenerated,theinternalhardwareisreset.
Theresettimeismaximum24/fc[s](1.
5s@fc=16.
0MHz).
Note:WhenawatchdogtimerresetisgeneratedintheSLOW1mode,theresettimeismaximum24/fc(high-fre-quencyclock)sincethehigh-frequencyclockoscillatorisrestarted.
However,whencrystalshaveinaccura-ciesuponstartofthehigh-frequencyclockoscillator,theresettimeshouldbeconsideredasanapproximatevaluebecauseithasslighterrors.
Figure7-2WatchdogTimerInterruptClockBinarycounterOverflowINTWDTinterruptrequest(WDTCR1="0")217/fc219/fc[s](WDTT=11)Write4EHtoWDTCR212301230Internalreset(WDTCR1="1")AresetoccursPage767.
WatchdogTimer(WDT)7.
3AddressTrapTMP86FS23UG7.
3AddressTrapTheWatchdogTimerControlRegister1and2sharetheaddresseswiththecontrolregisterstogenerateaddresstraps.
7.
3.
1SelectionofAddressTrapinInternalRAM(ATAS)WDTCR1specifieswhetherornottogenerateaddresstrapsintheinternalRAMarea.
ToexecuteaninstructionintheinternalRAMarea,clearWDTCR1to"0".
ToenabletheWDTCR1set-ting,setWDTCR1andthenwriteD2HtoWDTCR2.
ExecutinganinstructionintheSFRorDBRareageneratesanaddresstrapunconditionallyregardlessofthesettinginWDTCR1.
7.
3.
2SelectionofOperationatAddressTrap(ATOUT)Whenanaddresstrapisgenerated,eithertheinterruptrequestortheresetrequestcanbeselectedbyWDTCR1.
7.
3.
3AddressTrapInterrupt(INTATRAP)WhileWDTCR1is"0",iftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whileWDTCR1is"1"),DBRortheSFRarea,addresstrapinterrupt(INTATRAP)willbegenerated.
Anaddresstrapinterruptisanon-maskableinterruptwhichcanbeacceptedregardlessoftheinterruptmas-terflag(IMF).
Whenanaddresstrapinterruptisgeneratedwhiletheotherinterruptincludingawatchdogtimerinterruptisalreadyaccepted,thenewaddresstrapisprocessedimmediatelyandthepreviousinterruptisheldpending.
Therefore,ifaddresstrapinterruptsaregeneratedcontinuouslywithoutexecutionoftheRETNinstruction,toomanylevelsofnestingmaycauseamalfunctionofthemicrocontroller.
Togenerateaddresstrapinterrupts,setthestackpointerbeforehand.
WatchdogTimerControlRegister1WDTCR1(0034H)76543210ATASATOUT(WDTEN)(WDTT)(WDTOUT)(Initialvalue:**111001)ATASSelectaddresstrapgenerationintheinternalRAMarea0:Generatenoaddresstrap1:Generateaddresstraps(AftersettingATASto"1",writingthecontrolcodeD2HtoWDTCR2isreguired)WriteonlyATOUTSelectopertionataddresstrap0:Interruptrequest1:ResetrequestWatchdogTimerControlRegister2WDTCR2(0035H)76543210(Initialvalue:WDTCR2WriteWatchdogtimercontrolcodeandaddresstrapareacontrolcodeD2H:Enableaddresstrapareaselection(ATRAPcontrolcode)4EH:Clearthewatchdogtimerbinarycounter(WDTclearcode)B1H:Disablethewatchdogtimer(WDTdisablecode)Others:InvalidWriteonlyPage77TMP86FS23UG7.
3.
4AddressTrapResetWhileWDTCR1is"1",iftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whileWDTCR1is"1"),DBRortheSFRarea,addresstrapresetwillbegenerated.
Whenanaddresstrapresetrequestisgenerated,theinternalhardwareisreset.
Theresettimeismaximum24/fc[s](1.
5s@fc=16.
0MHz).
Note:WhenanaddresstrapresetisgeneratedintheSLOW1mode,theresettimeismaximum24/fc(high-fre-quencyclock)sincethehigh-frequencyclockoscillatorisrestarted.
However,whencrystalshaveinaccura-ciesuponstartofthehigh-frequencyclockoscillator,theresettimeshouldbeconsideredasanapproximatevaluebecauseithasslighterrors.
Page787.
WatchdogTimer(WDT)7.
3AddressTrapTMP86FS23UGPage79TMP86FS23UG8.
18-BitTimer/Counter(TC1)8.
1ConfigurationFigure8-1Timer/Counter1TC1CR1TREG1BF/FTC1SRCMPTC1CR2CBYASHCDEFGBAABYCSTREG1ALTREG1AMTREG1AHWindowpulsegeneratorEdgedetector18-bitup-counterEdgedetector101100SYYPinECNTPinCLEARsignalECINPinWGPSCKTC1MSGEDGINTTC12322112121WGPSCKSGEDGSGPSEGTC1CTC1STC1MTC1CK21111SEG1PulsewidthmeasurementmodeFrequencymeasurementmodeTimer/EventcountmodesP33TC6OUTTC6OUTfc/212orfs/24fc/213orfs/25fc/214orfs/26fs/215orfc/223fs/25orfc/213fs/23orfc/211fc/27fc/23fsfcPWM6/PDO6/PPG6Page808.
18-BitTimer/Counter(TC1)8.
2ControlTMP86FS23UG8.
2ControlTheTimer/counter1iscontrolledbytimer/counter1controlregisters(TC1CR1/TC1CR2),an18-bittimerregister(TREG1A),andan8-bitinternalwindowgatepulsesettingregister(TREG1B).
Timerregister76543210TREG1AH(0012H)R/WTREG1AH(Initialvalue:00)76543210TREG1AM(0011H)R/WTREG1AM(Initialvalue:00000000)76543210TREG1AL(0010H)R/WTREG1AL(Initialvalue:00000000)76543210TREG1B(0013H)TaTb(Initialvalue:00000000)WGPSCKNORMAL1/2,IDLE1/2modesSLOW1/2,SLEEP1/2modesR/WDV7CK=0DV7CK=1TaSetting"H"levelperiodofthewindowgatepulse000110(16-Ta)*212/fc(16-Ta)*213/fc(16-Ta)*214/fc(16-Ta)*24/fs(16-Ta)*25/fs(16-Ta)*26/fs(16-Ta)*24/fs(16-Ta)*25/fs(16-Ta)*26/fsTbSetting"L"levelperiodofthewindowgatepulse000110(16-Tb)*212/fc(16-Tb)*213/fc(16-Tb)*214/fc(16-Tb)*24/fs(16-Tb)*25/fs(16-Tb)*26/fs(16-Tb)*24/fs(16-Tb)*25/fs(16-Tb)*26/fsPage81TMP86FS23UGNote1:fc;High-frequencyclock[Hz]fs;Low-frequencyclock[Hz]*;Don'tcareNote2:Writingtothelow-byteofthetimerregister1A(TREG1AL,TREG1AM),thecomparefunctionisinhibiteduntilthehigh-byte(TREG1AH)iswritten.
Note3:Setthemodeandsourceclock,andedge(selection)whentheTC1stops(TC1S=00).
Note4:"fc"canbeselectedasthesourceclockonlyinthetimermodeduringSLOWmodeandinthepulsewidthmeasurementmodeduringNORMAL1/2orIDLE1/2mode.
Note5:Whenareadinstructionisexecutedtothetimerregister(TREG1A),thecounterimmediatevalue,nottheregistersetvalue,isreadout.
ThereforeitisimpossibletoreadoutthewrittenvalueofTREG1A.
Toreadthecountervalue,thereadinstructionshouldbeexecutedwhenthecounterstopstoavoidreadingunstablevalue.
Note6:Setthetimerregister(TREG1A)to≥1.
Note7:Whenusingthetimermodeandpulsewidthmeasurementmode,setTC1CK(TC1sourceclockselect)tointernalclock.
Note8:Whenusingtheeventcountermode,setTC1CK(TC1sourceclockselect)toexternalclock.
Note9:Becausethereadvalueisdifferentfromthewrittenvalue,donotuseread-modify-writeinstructionstoTREG1A.
Note10:fc/27,fc/23cannotbeusedassourceclockinSLOW/SLEEPmode.
Note11:Thereaddataofbits7to2inTREG1AHarealways"0".
(Data"1"cannotbewritten.
)Timer/counter1controlregister176543210TC1CR1(0014H)TC1CTC1STC1CKTC1M(Initialvalue:10001000)TC1CCounter/overfowflagcontroll0:1:ClearCounter/overflowflag("1"isautomaticallysetafterclearing.
)NotclearCounter/overflowflagR/WTC1STC1startcontrol00:10:*1:StopandcounterclearandoverflowflagclearStartReservedR/WTC1CKTC1sourceclockselectNORMAL1/2,IDLE1/2modesSLOW1/2modeSLEEP1/2modeR/WDV7CK="0"DV7CK="1"000:001:010:011:100:101:110:fcfsfc/223fc/213fc/211fc/27fc/23fcfsfs/215fs/25fs/23fc/27fc/23fc-fs/215fs/25fs/23--fc-fs/215fs/25fs/23--111:Externalclock(ECINpininput)TC1MTC1modeselect00:01:10:11:Timer/EventcountermodeReservedPulsewidthmeasurementmodeFrequencymeasurementmodeR/WPage828.
18-BitTimer/Counter(TC1)8.
2ControlTMP86FS23UGNote1:fc;High-frequencyclock[Hz]fs;Low-frequencyclock[Hz]*;Don'tcareNote2:Setthemode,sourceclock,andedge(selection)whentheTC1stops(TC1S=00).
Note3:IfthereisnoneedtousePWM6/PDO6/PPG6aswindowgatepulseofTC1alwayswrite"0"toTC6OUT.
Note4:MakesuretowriteTC1CR2"0"tobit0inTC1CR2.
Note5:Whenusingtheeventcountermodeorpulsewidthmeasurementmode,setSEGto"0".
Timer/Counter1controlregister276543210TC1CR2(0015H)SEGSGPSGEDGWGPSCKTC6OUT"0"(Initialvalue:0000000*)SEGExternalinputclock(ECIN)edgeselect0:1:CountsatthefallingedgeCountsattheboth(falling/rising)edgesR/WSGPWindowgatepulseselect00:01:10:11:ECNTinputInternalwindowgatepulse(TREG1B)PWM6/PDO6/PPG6(TC6)outputReservedR/WSGEDGWindowgatepulseinterruptedgeselect0:1:InterruptsatthefallingedgeInterruptsatthefalling/risingedgesWGPSCKWindowgatepulsesourceclockselectNORMAL1/2,IDLE1/2modesSLOW1/2modeSLEEP1/2modeR/WDV7CK="0"DV7CK="1"00:01:10:11:212/fc213/fc214/fcReserved24/fs25/fs26/fsReserved24/fs25/fs26/fsReserved24/fs25/fs26/fsReservedTC6OUTTC6output(PWM6/PDO6/PPG6)externaloutputselect0:1:OutputtoP33NooutputtoP33R/WPage83TMP86FS23UG8.
3FunctionTC1hasfouroperatingmodes.
ThetimermodeoftheTC1isusedatwarm-upwhenswitchingformSLOWmodetoNORMAL2mode.
8.
3.
1TimermodeInthismode,countingupisperformedusingtheinternalclock.
ThecontentsofTREGIAarecomparedwiththecontentsofup-counter.
Ifamatchisfound,anINTTC1interruptisgenerated,andthecounteriscleared.
Countingupresumesafterthecounteriscleared.
Note:WhenfcisselectedforthesourceclockinSLOWmode,thelowerbits11ofTREG1Aisinvalid,andamatchoftheupperbits7makesinterrupts.
TC1statusregisterTC1SR(0016H)76543210HECFHEOVF"0""0""0""0""0""0"(Initialvalue:00000000)HECFOperatingStatusmonitor0:1:Stop(duringTb)ordisableUndercounting(duringTa)ReadonlyHEOVFCounteroverflowmonitor0:1:NooverflowOverflowstatusTable8-1Sourceclock(internalclock)ofTimer/Counter1SourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2ModeSLOWModeSLEEPModefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/223[Hz]fs/215[Hz]fs/215[Hz]fs/215[Hz]0.
52s1s38.
2h72.
8hfc/213fs/25fs/25fs/25512ms0.
98ms2.
2min4.
3minfc/211fs/23fs/23fs/23128ms244ms0.
6min1.
07minfc/27fc/27--8ms-2.
1s-fc/23fc/23--0.
5ms-131.
1ms-fcfcfc(Note)-62.
5ns-16.
4ms-fsfs---30.
5ms-8sPage848.
18-BitTimer/Counter(TC1)8.
3FunctionTMP86FS23UGFigure8-2Timingchartfortimermode8.
3.
2EventCountermodeItisamodetocountupatthefallingedgeoftheECINpininput.
Whenusingthismode,setTC1CR1totheexternalclockandthensetTC1CR2to"0"(Bothedgescannotbeused).
ThecountentsofTREG1Aarecomparedwiththecontentsofup-counter.
Ifamatchisfound,anINTTC1interruptisgenerated,andthecounteriscleared.
CountingupresumesforECINpininputedgeeachafterthecounteriscleared.
Themaximumappliedfrequencyisfc/24[Hz]inNORMAL1/2orIDLE1/2modeandfs/24[Hz]inSLOWorSLEEPmode.
Twoormoremachinecyclesarerequiredforboththe"H"and"L"levelsofthepulsewidth.
Figure8-3Eventcountermodetimingchart10234n01n-123456nTREG1AInternalclockUpcounterCommandStartMatchdetectCounterclearINTTC1interrupt1022n-1n01nTREG1AECINpininputUpcounterStartMatchDetectCounterclearINTTC1interruptPage85TMP86FS23UG8.
3.
3PulseWidthMeasurementmodeInthismode,pulsewidthsarecountedonthefallingedgeoflogicalAND-edpulsebetweenECINpininput(windowpulse)andtheinternalclock.
Whenusingthismode,setTC1CR1tosuitableinternalclockandthensetTC1CR2to"0"(Bothedgescannotbeused).
AnINTTC1interruptisgeneratedwhentheECINinputdetectsthefallingedgeofthewindowpulseorbothrisingandfallingedgesofthewindowpulse,thatcanbeselectedbyTC1CR2.
ThecontentsofTREG1Ashouldbereadwhilethecountisstopped(ECINpinislow),thenclearthecounterusingTC1CR1(Normally,executetheseprocessintheinterruptprogram).
WhenthecounterisnotclearedbyTC1CR1,counting-upresumesfrompreviousstoppingvalue.
Whenupcounteriscountedupfrom3FFFFHto00000H,anoverflowoccurs.
Atthattime,TC1SRissetto"1".
TC1SRremainsthepreviousdatauntilthecounterisrequiredtobeclearedbyTC1CR1.
Note:Inpulsewidthmeasurementmode,ifTC1CR1iswrittento"00"whileECINinputis"1",INTTC1inter-ruptoccurs.
Accordingtothefollowingstep,whentimercounterisstopped,INTTC1interruptlatchshouldbeclearedto"0".
Note1:WhenSGEDG(windowgatepulseinterruptedgeselect)issettobothedgesandECINpininputis"1"inthepulsewidthmeasurementmode,anINTTC1interruptisgeneratedbysettingTC1S(TC1startcontrol)to"10"(start).
Note2:Inthepulsewidthmeasurementmode,HECF(operatingstatusmonitor)cannotused.
Note3:BecausetheupcounteriscountedonthefallingedgeoflogicalAND-edpulse(betweenECINpininputandtheinternalclock),ifECINinputbecomesfallingedgewhileinternalsourceclockis"H"level,theupcounterstopsplus"1".
Figure8-4PulsewidthmeasurementmodetimingchartExample:TC1STOP:DI;ClearIMFCLR(EIRL).
7;Clearbit7ofEIRLLD(TC1CR1),00011010B;Stoptimercouter1LD(ILL),01111111B;Clearbit7ofILLSET(EIRL).
7;Setbit7ofEIRLEI;SetIMF1023n-2n-1nn+1012ECINpininputINTTC1interruptInternalclockAND-edpulse(Internalsignal)UpcounterTC1CR1InterruptReadClearCountStartCountStartCountStopPage868.
18-BitTimer/Counter(TC1)8.
3FunctionTMP86FS23UG8.
3.
4FrequencyMeasurementmodeInthismode,thefrequencyofECINpininputpulseismeasured.
Whenusingthismode,setTC1CR1totheexternalclock.
TheedgeoftheECINinputpulseiscountedduring"H"levelofthewindowgatepulseselectedbyTC1CR2.
TouseECNTinputasawindowgatepulse,TC1CR2shouldbesetto"00".
AnINTTC1interruptisgeneratedonthefallingedgeorboththerising/fallingedgesofthewindowgatepulse,thatcanbeselectedbyTC1CR2.
Intheinterruptserviceprogram,readthecontentsofTREG1Awhilethecountisstopped(windowgatepulseislow),thenclearthecounterusingTC1CR1.
Whenthecounterisnotcleared,countingupresumesfrompreviousstoppingvalue.
ThewindowpulsestatuscanbemonitoredbyTC1SR.
Whenupcounteriscountedupfrom3FFFFHto00000H,anoverflowoccurs.
Atthattime,TC1SRissetto"1".
TC1SRremainsthepreviousdatauntilthecounterisrequiredtobeclearedbyTC1CR1.
UsingTC6output(PWM6/PDO6/PPG6)forthewindowgatepulse,externaloutputofPWM6/PDO6/PPG6toP33canbecontrolledusingTC1CR2.
Zero-clearingTC1CR2outputsPWM6/PDO6/PPG6toP33;setting1inTC1CR2doesnotoutputPWM6/PDO6/PPG6toP33.
(TC1CR2isusedtocontroloutputtoP33only.
Thus,usethetimercounter6controlregistertooperate/stopPWM6/PDO6/PPG6.
)Whentheinternalwindowgatepulseisselected,thewindowgatepulseissetasfollows.
Theinternalwindowgatepulseconsistsof"H"levelperiod(Ta)thatiscountingtimeand"L"levelperiod(Tb)thatiscountingstoptime.
TaorTbcanbeindividuallysetbyTREG1B.
OnecyclecontainsTa+Tb.
Note1:Becausetheinternalwindowgatepulseisgeneratedinsynchronizationwiththeinternaldivider,itmaybedelayedforamaximumofonecycleofthesourceclock(WGPSCK)immediatelyafterstartofthetimer.
Note2:SettheinternalwindowgatepulsewhenthetimercounterisnotoperatingorduringtheTbperiod.
WhenTbisoverwrittenduringtheTbperiod,theupdateisvalidfromthenextTbperiod.
Note3:IncaseofTC1CR2="1",ifwindowgatepulsebecomesfallingedge,theupcounterstopsplus"1"regardlessofECINinputlevel.
Therefore,ifECINisalways"H"or"L"level,countvaluebecomes"1".
Note4:IncaseofTC1CR2="0",becausetheupcounteriscountedonthefallingedgeoflogicalAND-edpulse(betweenECINpininputandwindowgatepulse),ifwindowgatepulsebecomesfallingedgewhileECINinputis"H"level,theupcounterstopsplus"1".
Therefore,ifECINinputisalways"H"level,countvaluebecomes"1".
Table8-2InternalwindowgatepulsesettingtimeWGPSCKNORMAL1/2,IDLE1/2modesSLOW1/2,SLEEP1/2modesR/WDV7CK=0DV7CK=1TaSetting"H"levelperiodofthewindowgatepulse000110(16-Ta)*212/fc(16-Ta)*213/fc(16-Ta)*214/fc(16-Ta)*24/fs(16-Ta)*25/fs(16-Ta)*26/fs(16-Ta)*24/fs(16-Ta)*25/fs(16-Ta)*26/fsTbSetting"L"levelperiodofthewindowgatepulse000110(16-Tb)*212/fc(16-Tb)*213/fc(16-Tb)*214/fc(16-Tb)*24/fs(16-Tb)*25/fs(16-Tb)*26/fs(16-Tb)*24/fs(16-Tb)*25/fs(16-Tb)*26/fsPage87TMP86FS23UGTable8-3TableSettingTaandTb(WGPSCK=10,fc=16MHz)SettingValueSettingtimeSettingValueSettingtime016.
38ms88.
19ms115.
36ms97.
17ms214.
34msA6.
14ms313.
31msB5.
12ms412.
29msC4.
10ms511.
26msD3.
07ms610.
24msE2.
05ms79.
22msF1.
02msTable8-4TableSettingTaandTb(WGPSCK=10,fs=32.
768kHz)SettingValuenSettingtimeSettingValueSettingtime031.
25ms815.
63ms129.
30ms913.
67ms227.
34msA11.
72ms325.
39msB9.
77ms423.
44msC7.
81ms521.
48msD5.
86ms619.
53msE3.
91ms717.
58msF1.
95msPage888.
18-BitTimer/Counter(TC1)8.
3FunctionTMP86FS23UGFigure8-5Timingchartforthefrequencymeasurementmode(Windowgatepulsefallinginterrupt)10235412356460ECINpininputAND-edpulse(Internalsignal)INTTC1interruptWindowgatepulseUpcounterTC1CR1ReadClearTaTbTa0131211012123456789101234567891011ECINpininputINTTC1interruptWindowgatepulseUpcounterTC1CR1TC1CR2a)TC1CR2="0"a)TC1CR2="1"ReadClearTaTbTaPage89TMP86FS23UG9.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationFigure9-18-BitTimerCouter3,48-bitup-counterDecodeENAYBSABYCDEFGHSAYBSSAYBToggleQSetClear8-bitup-counterABYCDEFGHSDecodeENToggleQSetClearPWMmodePDO,PPGmodePDOmodePWM,PPGmodePWMmodePWMmode16-bitmode16-bitmode16-bitmode16-bitmodeTimer,EventCountermodeOverflowOverflowTimer,EventCoutermode16-bitmodeClearClearfc/27fc/25fc/23fc/2fcfc/27fc/25fc/23fc/2fcPDO,PWM,PPGmodePDO,PWMmode16-bitmodefc/211orfs/23fc/211orfs/23fsfsTC4CRTC3CRTTREG4PWREG4TTREG3PWREG3TC3pinTC4pinTC4STC3SINTTC3interruptrequestINTTC4interruptrequestTFF4TFF3PDO4/PWM4/PPG4pinPDO3/PWM3/pinTC3CKTC4CKTC3MTC3STFF3TC4MTC4STFF4TimerF/F4TimerF/F3Page909.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UG9.
2TimerCounterControlTheTimerCounter3iscontrolledbytheTimerCounter3controlregister(TC3CR)andtwo8-bittimerregisters(TTREG3,PWREG3).
Note1:Donotchangethetimerregister(TTREG3)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG3)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC3M,TC3CKandTFF3settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC3S=1→0),donotchangetheTC3M,TC3CKandTFF3settings.
Tostartthetimeropera-tion(TC3S=0→1),TC3M,TC3CKandTFF3canbeprogrammed.
Note4:TousetheTimerCounterinthe16-bitmode,settheoperatingmodebyprogrammingTC4CR,whereTC3Mmustbefixedto011.
Note5:TousetheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC3CK.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC4CRandTC4CR,respectively.
Note6:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-1andTable9-2.
TimerCounter3TimerRegisterTTREG3(001CH)R/W76543210(Initialvalue:11111111)PWREG3(0028H)R/W76543210(Initialvalue:11111111)TimerCounter3ControlRegisterTC3CR(0018H)76543210TFF3TC3CKTC3STC3M(Initialvalue:00000000)TFF3TimeF/F3control0:1:ClearSetR/WTC3CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfcfc(Note8)111TC3pininputTC3STC3startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC3MTC3Moperatingmodeselect000:001:010:011:1**:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmode16-bitmode(EachmodeisselectablewithTC4M.
)ReservedR/WPage91TMP86FS23UGNote7:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-3.
Note8:TheoperatingclockfcintheSLOWorSLEEPmodecanbeusedonlyasthehigh-frequencywarm-upmode.
Page929.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UGTheTimerCounter4iscontrolledbytheTimerCounter4controlregister(TC4CR)andtwo8-bittimerregisters(TTREG4andPWREG4).
Note1:Donotchangethetimerregister(TTREG4)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG4)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC4M,TC4CKandTFF4settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC4S=1→0),donotchangetheTC4M,TC4CKandTFF4settings.
Tostartthetimeroperation(TC4S=0→1),TC4M,TC4CKandTFF4canbeprogrammed.
Note4:WhenTC4M=1**(upperbyteinthe16-bitmode),thesourceclockbecomestheTC4overflowsignalregardlessoftheTC3CKsetting.
Note5:TousetheTimerCounterinthe16-bitmode,selecttheoperatingmodebyprogrammingTC4M,whereTC3CRmustbesetto011.
TimerCounter4TimerRegisterTTREG4(001DH)R/W76543210(Initialvalue:11111111)PWREG4(0029H)R/W76543210(Initialvalue:11111111)TimerCounter4ControlRegisterTC4CR(0019H)76543210TFF4TC4CKTC4STC4M(Initialvalue:00000000)TFF4TimerF/F4control0:1:ClearSetR/WTC4CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfc–111TC4pininputTC4STC4startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC4MTC4Moperatingmodeselect000:001:010:011:100:101:110:111:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmodeReserved16-bittimer/eventcountermodeWarm-upcountermode16-bitpulsewidthmodulation(PWM)outputmode16-bitPPGmodeR/WPage93TMP86FS23UGNote6:TotheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC3CR.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC4SandTFF4,respectively.
Note7:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-1andTable9-2.
Note8:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-3.
Note1:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC3CK).
Note2:Ο:AvailablesourceclockTable9-1OperatingModeandSelectableSourceClock(NORMAL1/2andIDLE1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC3pininputTC4pininput8-bittimerΟΟΟΟ8-biteventcounterΟΟ8-bitPDOΟΟΟΟ8-bitPWMΟΟΟΟΟΟΟ––16-bittimerΟΟΟΟ16-biteventcounterΟ–Warm-upcounter––––Ο––––16-bitPWMΟΟΟΟΟΟΟΟ–16-bitPPGΟΟΟΟ–––Ο–Table9-2OperatingModeandSelectableSourceClock(SLOW1/2andSLEEP1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC3pininputTC4pininput8-bittimerΟ8-biteventcounterΟΟ8-bitPDOΟ8-bitPWMΟ–––Ο––––16-bittimerΟ16-biteventcounterΟ–Warm-upcounterΟ––16-bitPWMΟ–––Ο––Ο–16-bitPPGΟΟ–Note1:Note2:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC3CK).
Ο:AvailablesourceclockPage949.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UGNote:n=3to4Table9-3ConstraintsonRegisterValuesBeingComparedOperatingmodeRegisterValue8-bittimer/eventcounter1≤(TTREGn)≤2558-bitPDO1≤(TTREGn)≤2558-bitPWM2≤(PWREGn)≤25416-bittimer/eventcounter1≤(TTREG4,3)≤65535Warm-upcounter256≤(TTREG4,3)≤6553516-bitPWM2≤(PWREG4,3)≤6553416-bitPPG1≤(PWREG4,3)to0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Table9-4SourceClockforTimerCounter3,4(InternalClock)SourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
6ms62.
3msfc/27fc/27–8s–2.
0ms–fc/25fc/25–2s–510s–fc/23fc/23–500ns–127.
5s–Example:Settingthetimermodewithsourceclockfc/27Hzandgeneratinganinterrupt80slater(TimerCounter4,fc=16.
0MHz)LD(TTREG4),0AH:Setsthetimerregister(80s÷27/fc=0AH).
DISET(EIRH).
4:EnablesINTTC4interrupt.
EILD(TC4CR),00010000B:Setstheoperatingcocktofc/27,and8-bittimermode.
LD(TC4CR),00011000B:StartsTC4.
Page969.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UGFigure9-28-BitTimerModeTimingChart(TC4)9.
3.
28-BitEventCounterMode(TC3,4)Inthe8-biteventcountermode,theup-countercountsupatthefallingedgeoftheinputpulsetotheTCjpin.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,anINTTCjinterruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTCjpin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTCjpin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24HzintheSLOW1/2orSLEEP1/2mode.
Note1:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Figure9-38-BitEventCounterModeTimingChart(TC4)9.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC3,4)Thismodeisusedtogenerateapulsewitha50%dutycyclefromthePDOjpin.
InthePDOmode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,thelogicleveloutputfromthePDOjpinisswitchedtotheoppositestateandtheup-counteriscleared.
TheINTTCjinterruptrequestisgeneratedatthetime.
ThelogicstateoppositetothetimerF/FjlogiclevelisoutputfromthePDOjpin.
AnarbitraryvaluecanbesettothetimerF/FjbyTCjCR.
Uponreset,thetimerF/Fjvalueisinitializedto0.
Tousetheprogrammabledivideroutput,settheoutputlatchoftheI/Oportto1.
123n-1n01n-1n20120nInternalSourceClockCounterMatchdetectCounterclearMatchdetectCounterclearTC4CRTTREG4INTTC4interruptrequest102n-1n0120nCounterMatchdetectCounterclearn-1n201MatchdetectCounterclearTC4CRTTREG4INTTC4interruptrequestTC4pininputPage97TMP86FS23UGNote1:Intheprogrammabledivideroutputmode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheprogrammabledivideroutputmode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPDOoutput,thePDOjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRsettinguponstoppingofthetimer.
Example:FixingthePDOjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePDOjpintothehighlevel.
Note3:j=3,4Example:Generating1024HzpulseusingTC4(fc=16.
0MHz)SettingportLD(TTREG4),3DH:1/1024÷27/fc÷2=3DHLD(TC4CR),00010001B:Setstheoperatingclocktofc/27,and8-bitPDOmode.
LD(TC4CR),00011001B:StartsTC4.
Page989.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UGFigure9-48-BitPDOModeTimingChart(TC4)120n0n0n0n01221212310nInternalsourceclockCounterMatchdetectMatchdetectMatchdetectMatchdetectHeldatthelevelwhenthetimerisstoppedSetF/FWriteof"1"TC4CRTC4CRTTREG4TimerF/F4PDO4pinINTTC4interruptrequestPage99TMP86FS23UG9.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC3,4)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto8bitsofresolution.
Theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthePWREGjvalueisdetected,thelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestateagainbytheup-counteroverflow,andthecounteriscleared.
TheINTTCjinterruptrequestisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/FjbyTCjCR,positiveandnegativepulsescanbegen-erated.
Uponreset,thetimerF/Fjisclearedto0.
(ThelogicleveloutputfromthePWMjpinistheoppositetothetimerF/Fjlogiclevel.
)SincePWREGjinthePWMmodeisseriallyconnectedtotheshiftregister,thevaluesettoPWREGjcanbechangedwhilethetimerisrunning.
ThevaluesettoPWREGjduringarunofthetimerisshiftedbytheINTTCjinterruptrequestandloadedintoPWREGj.
Whilethetimerisstopped,thevalueisshiftedimmedi-atelyaftertheprogrammingofPWREGj.
IfexecutingthereadinstructiontoPWREGjduringPWMoutput,thevalueintheshiftregisterisread,butnotthevaluesetinPWREGj.
Therefore,afterwritingtoPWREGj,thereadingdataofPWREGjispreviousvalueuntilINTTCjisgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREGjimmediatelyaftertheINTTCjinterruptrequestisgenerated(normallyintheINTTCjinterruptserviceroutine.
)IftheprogrammingofPWREGjandtheinter-ruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofthepulsedifferentfromtheprogrammedvalueuntilthenextINTTCjinterruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWMjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRuponstoppingofthetimer.
Example:FixingthePWMjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePWMjpintothehighlevel.
Note3:ToentertheSTOPmodeduringPWMoutput,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwithoutstoppingthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisout-putfromthePWMjpinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Note4:j=3,4Table9-5PWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
8ms62.
5msfc/27fc/27–8s–2.
05ms–fc/25fc/25–2s–512s–fc/23fc/23–500ns–128s–fsfsfs30.
5s30.
5s7.
81ms7.
81msfc/2fc/2–125ns–32s–fcfc–62.
5ns–16s–Page1009.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UGFigure9-58-BitPWMModeTimingChart(TC4)10nn+1FF0nn+1FF01mm+1FF011pnInternalsourceclockCounterWritetoPWREG4WritetoPWREG4mpmpnShiftregistarShiftShiftShiftShiftMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectnmpnTC4CRTC4CRPWREG4TimerF/F4PWM4pinINTTC4interruptrequestPage101TMP86FS23UG9.
3.
516-BitTimerMode(TC3and4)Inthetimermode,theup-countercountsupusingtheinternalclock.
TheTimerCounter3and4arecascad-abletoforma16-bittimer.
Whenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,anINTTC4interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-countercontinuescounting.
Programtheupperbyteandlowerbyteinthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Inthetimermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMj,andPPGjpinsmayoutputapulse.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogrammingofTTREGj.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Figure9-616-BitTimerModeTimingChart(TC3andTC4)Table9-6SourceClockfor16-BitTimerModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23fs/23128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–Example:Settingthetimermodewithsourceclockfc/27Hz,andgeneratinganinterrupt300mslater(fc=16.
0MHz)LDW(TTREG3),927CH:Setsthetimerregister(300ms÷27/fc=927CH).
DISET(EIRH).
4:EnablesINTTC4interrupt.
EILD(TC3CR),13H:Setstheoperatingcocktofc/27,and16-bittimermode(lowerbyte).
LD(TC4CR),04H:Setsthe16-bittimermode(upperbyte).
LD(TC4CR),0CH:Startsthetimer.
1023mn-1mn01mn-1mn20120nmInternalsourceclockCounterMatchdetectCounterclearMatchdetectCounterclearTC4CRTTREG3(Lowerbyte)INTTC4interruptrequestTTREG4(Upperbyte)Page1029.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UG9.
3.
616-BitEventCounterMode(TC3and4)9.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC3and4)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto16bitsofresolution.
TheTimerCounter3and4arecascadabletoformthe16-bitPWMsignalgenerator.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG3,PWREG4)valueisdetected,thelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestateagainbythecounteroverflow,andthecounteriscleared.
TheINTTC4interruptisgeneratedatthistime.
Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC3pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1orIDLE1mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
SincetheinitialvaluecanbesettothetimerF/F4byTC4CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F4isclearedto0.
(ThelogicleveloutputfromthePWM4pinistheoppositetothetimerF/F4logiclevel.
)SincePWREG4and3inthePWMmodeareseriallyconnectedtotheshiftregister,thevaluessettoPWREG4and3canbechangedwhilethetimerisrunning.
ThevaluessettoPWREG4and3duringarunofthetimerareshiftedbytheINTTCjinterruptrequestandloadedintoPWREG4and3.
Whilethetimerisstopped,thevaluesareshiftedimmediatelyaftertheprogrammingofPWREG4and3.
Setthelowerbyte(PWREG3)andupperbyte(PWREG3)inthisordertoprogramPWREG4and3.
(Programmingonlythelowerorupperbyteoftheregistershouldnotbeattempted.
)IfexecutingthereadinstructiontoPWREG4and3duringPWMoutput,thevaluessetintheshiftregisterisread,butnotthevaluessetinPWREG4and3.
Therefore,afterwritingtothePWREG4and3,readingdataofPWREG4and3ispreviousvalueuntilINTTC4isgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREG4and3immediatelyaftertheINTTC4interruptrequestisgenerated(normallyintheINTTC4interruptserviceroutine.
)IftheprogrammingofPWREGjandtheinterruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofpulsedifferentfromtheprogrammedvalueuntilthenextINTTC4interruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWM4pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC4CRafterthetimerisstopped.
DonotprogramTC4CRuponstoppingofthetimer.
Example:FixingthePWM4pintothehighlevelwhentheTimerCounterisstoppedIntheeventcountermode,theup-countercountsupatthefallingedgetotheTC3pin.
TheTimerCounter3and4arecascadabletoforma16-biteventcounter.
Whenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,anINTTC4interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTC3pin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC3pin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1orIDLE1mode,andfs/24intheSLOW1/2orSLEEP1/2mode.
Programthelowerbyte(TTREG3),andupperbyte(TTREG4)inthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Note2:Note3:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimme-diatelyaftertheprogramming.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
j=3,4Page103TMP86FS23UGCLR(TC4CR).
3:Stopsthetimer.
CLR(TC4CR).
7:SetsthePWM4pintothehighlevel.
Note3:ToentertheSTOPmode,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwith-outstoppingofthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisoutputfromthePWM4pinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Table9-716-BitPWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23[Hz]fs/23[Hz]128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–fsfsfs30.
5s30.
5s2s2sfc/2fc/2–125ns–8.
2ms–fcfc–62.
5ns–4.
1ms–Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof32.
768ms(fc=16.
0MHz)SettingportsLDW(PWREG3),07D0H:Setsthepulsewidth.
LD(TC3CR),33H:Setstheoperatingclocktofc/23,and16-bitPWMoutputmode(lowerbyte).
LD(TC4CR),056H:SetsTFF4totheinitialvalue0,and16-bitPWMsignalgenerationmode(upperbyte).
LD(TC4CR),05EH:Startsthetimer.
Page1049.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UGFigure9-716-BitPWMModeTimingChart(TC3andTC4)10anan+1FFFF0anan+1FFFF01bmbm+1FFFF0bmcpbc11cpnaanInternalsourceclock16-bitshiftregisterShiftShiftShiftShiftCounterMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectanbmcpanmpTC4CRTC4CRPWREG3(Lowerbyte)TimerF/F4PWM4pinINTTC4interruptrequestPWREG4(Upperbyte)WritetoPWREG4WritetoPWREG4WritetoPWREG3WritetoPWREG3Page105TMP86FS23UG9.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC3and4)Thismodeisusedtogeneratepulseswithupto16-bitsofresolution.
Thetimercounter3and4arecascad-abletoenterthe16-bitPPGmode.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG3,PWREG4)valueisdetected,thelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestateagainwhenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetected,andthecounteriscleared.
TheINTTC4interruptisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/F4byTC4CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F4isclearedto0.
(ThelogicleveloutputfromthePPG4pinistheoppositetothetimerF/F4.
)Setthelowerbyteandupperbyteinthisordertoprogramthetimerregister.
(TTREG3→TTREG4,PWREG3→PWREG4)(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)ForPPGoutput,settheoutputlatchoftheI/Oportto1.
Note1:InthePPGmode,donotchangethePWREGiandTTREGisettingswhilethetimerisrunning.
SincePWREGiandTTREGiarenotintheshiftregisterconfigurationinthePPGmode,thenewvaluespro-grammedinPWREGiandTTREGiareineffectimmediatelyafterprogrammingPWREGiandTTREGi.
Therefore,ifPWREGiandTTREGiarechangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPPGoutput,thePPG4pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC4CRafterthetimerisstopped.
DonotchangeTC4CRuponstoppingofthetimer.
Example:FixingthePPG4pintothehighlevelwhentheTimerCounterisstoppedCLR(TC4CR).
3:StopsthetimerCLR(TC4CR).
7:SetsthePPG4pintothehighlevelNote3:i=3,4Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC3pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1orIDLE1mode,andfc/24tointheSLOW1/2orSLEEP1/2mode.
Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof16.
385ms(fc=16.
0MHz)SettingportsLDW(PWREG3),07D0H:Setsthepulsewidth.
LDW(TTREG3),8002H:Setsthecycleperiod.
LD(TC3CR),33H:Setstheoperatingclocktofc/23,and16-bitPPGmode(lowerbyte).
LD(TC4CR),057H:SetsTFF4totheinitialvalue0,and16-bitPPGmode(upperbyte).
LD(TC4CR),05FH:Startsthetimer.
Page1069.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UGFigure9-816-BitPPGModeTimingChart(TC3andTC40)10mnmn+1qr-1mnqr-11mnmn+1mn+10qr0qr10InternalsourceclockCounterWriteof"0"MatchdetectMatchdetectMatchdetectmnmnmnMatchdetectMatchdetectnmrqHeldatthelevelwhenthetimerstopsF/FclearTC4CRTC4CRPWREG3(Lowerbyte)TimerF/F4PPG4pinINTTC4interruptrequestPWREG4(Upperbyte)TTREG3(Lowerbyte)TTREG4(Upperbyte)Page107TMP86FS23UG9.
3.
9Warm-UpCounterModeInthismode,thewarm-upperiodtimeisobtainedtoassureoscillationstabilitywhenthesystemclockingisswitchedbetweenthehigh-frequencyandlow-frequency.
Thetimercounter3and4arecascadabletoforma16-bitTimerCouter.
Thewarm-upcountermodehastwotypesofmode;switchingfromthehigh-frequencytolow-frequency,andvice-versa.
Note1:Inthewarm-upcountermode,fixTCiCRto0.
Ifnotfixed,thePDOi,PWMiandPPGipinsmayoutputpulses.
Note2:Inthewarm-upcountermode,onlyupper8bitsofthetimerregisterTTREG4and3areusedformatchdetectionandlower8bitsarenotused.
Note3:i=3,49.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)Inthismode,thewarm-upperiodtimefromastopofthelow-frequencyclockfstooscillationstabilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethelow-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG4,3)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,thecounterisclearedbygeneratingtheINTTC4interruptrequest.
AfterstoppingthetimerintheINTTC4interruptserviceroutine,setSYSCR2to1toswitchthesystemclockfromthehigh-frequencytolow-frequency,andthenclearofSYSCR2to0tostopthehigh-frequencyclock.
Table9-8SettingTimeofLow-FrequencyWarm-UpCounterMode(fs=32.
768kHz)MaximumTimeSetting(TTREG4,3=0100H)MaximumTimeSetting(TTREG4,3=FF00H)7.
81ms1.
99sExample:Aftercheckinglow-frequencyclockoscillationstabilitywithTC4and3,switchingtotheSLOW1modeSET(SYSCR2).
6:SYSCR2←1LD(TC3CR),43H:SetsTFF3=0,sourceclockfs,and16-bitmode.
LD(TC4CR),05H:SetsTFF4=0,andwarm-upcountermode.
LD(TTREG3),8000H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRH).
4:EnablestheINTTC4.
EI:IMF←1SET(TC4CR).
3:StartsTC4and3.
::PINTTC4:CLR(TC4CR).
3:StopsTC4and3.
SET(SYSCR2).
5:SYSCR2←1(Switchesthesystemclocktothelow-frequencyclock.
)CLR(SYSCR2).
7:SYSCR2←0(Stopsthehigh-frequencyclock.
)RETI::VINTTC4:DWPINTTC4:INTTC4vectortablePage1089.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86FS23UG9.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)Inthismode,thewarm-upperiodtimefromastopofthehigh-frequencyclockfctotheoscillationsta-bilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethehigh-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG4,3)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,thecounterisclearedbygeneratingtheINTTC4interruptrequest.
AfterstoppingthetimerintheINTTC4interruptserviceroutine,clearSYSCR2to0toswitchthesystemclockfromthelow-frequencytohigh-frequency,andthenSYSCR2to0tostopthelow-frequencyclock.
Table9-9SettingTimeinHigh-FrequencyWarm-UpCounterModeMinimumtime(TTREG4,3=0100H)Maximumtime(TTREG4,3=FF00H)16s4.
08msExample:Aftercheckinghigh-frequencyclockoscillationstabilitywithTC4and3,switchingtotheNORMAL1modeSET(SYSCR2).
7:SYSCR2←1LD(TC3CR),63H:SetsTFF3=0,sourceclockfs,and16-bitmode.
LD(TC4CR),05H:SetsTFF4=0,andwarm-upcountermode.
LD(TTREG3),0F800H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRH).
4:EnablestheINTTC4.
EI:IMF←1SET(TC4CR).
3:StartstheTC4and3.
::PINTTC4:CLR(TC4CR).
3:StopstheTC4and3.
CLR(SYSCR2).
5:SYSCR2←0(Switchesthesystemclocktothehigh-frequencyclock.
)CLR(SYSCR2).
6:SYSCR2←0(Stopsthelow-frequencyclock.
)RETI::VINTTC4:DWPINTTC4:INTTC4vectortablePage109TMP86FS23UG10.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationFigure10-18-BitTimerCouter5,68-bitup-counterDecodeENAYBSABYCDEFGHSAYBSSAYBToggleQSetClear8-bitup-counterABYCDEFGHSDecodeENToggleQSetClearPWMmodePDO,PPGmodePDOmodePWM,PPGmodePWMmodePWMmode16-bitmode16-bitmode16-bitmode16-bitmodeTimer,EventCountermodeOverflowOverflowTimer,EventCoutermode16-bitmodeClearClearfc/27fc/25fc/23fc/2fcfc/27fc/25fc/23fc/2fcPDO,PWM,PPGmodePDO,PWMmode16-bitmodefc/211orfs/23fc/211orfs/23fsfsTC6CRTC5CRTTREG6PWREG6TTREG5PWREG5TC5pinTC6pinTC6STC5SINTTC5interruptrequestINTTC6interruptrequestTFF6TFF5PDO6/PWM6/PPG6pinPDO5/PWM5/pinTC5CKTC6CKTC5MTC5STFF5TC6MTC6STFF6TimerF/F6TimerF/F5Page11010.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UG10.
2TimerCounterControlTheTimerCounter5iscontrolledbytheTimerCounter5controlregister(TC5CR)andtwo8-bittimerregisters(TTREG5,PWREG5).
Note1:Donotchangethetimerregister(TTREG5)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG5)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC5M,TC5CKandTFF5settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC5S=1→0),donotchangetheTC5M,TC5CKandTFF5settings.
Tostartthetimeropera-tion(TC5S=0→1),TC5M,TC5CKandTFF5canbeprogrammed.
Note4:TousetheTimerCounterinthe16-bitmode,settheoperatingmodebyprogrammingTC6CR,whereTC5Mmustbefixedto011.
Note5:TousetheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC5CK.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC6CRandTC6CR,respectively.
Note6:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-1andTable10-2.
TimerCounter5TimerRegisterTTREG5(001EH)R/W76543210(Initialvalue:11111111)PWREG5(002AH)R/W76543210(Initialvalue:11111111)TimerCounter5ControlRegisterTC5CR(001AH)76543210TFF5TC5CKTC5STC5M(Initialvalue:00000000)TFF5TimeF/F5control0:1:ClearSetR/WTC5CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfcfc(Note8)111TC5pininputTC5STC5startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC5MTC5Moperatingmodeselect000:001:010:011:1**:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmode16-bitmode(EachmodeisselectablewithTC6M.
)ReservedR/WPage111TMP86FS23UGNote7:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-3.
Note8:TheoperatingclockfcintheSLOWorSLEEPmodecanbeusedonlyasthehigh-frequencywarm-upmode.
Page11210.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UGTheTimerCounter6iscontrolledbytheTimerCounter6controlregister(TC6CR)andtwo8-bittimerregisters(TTREG6andPWREG6).
Note1:Donotchangethetimerregister(TTREG6)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG6)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC6M,TC6CKandTFF6settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC6S=1→0),donotchangetheTC6M,TC6CKandTFF6settings.
Tostartthetimeroperation(TC6S=0→1),TC6M,TC6CKandTFF6canbeprogrammed.
Note4:WhenTC6M=1**(upperbyteinthe16-bitmode),thesourceclockbecomestheTC6overflowsignalregardlessoftheTC5CKsetting.
Note5:TousetheTimerCounterinthe16-bitmode,selecttheoperatingmodebyprogrammingTC6M,whereTC5CRmustbesetto011.
TimerCounter6TimerRegisterTTREG6(001FH)R/W76543210(Initialvalue:11111111)PWREG6(002BH)R/W76543210(Initialvalue:11111111)TimerCounter6ControlRegisterTC6CR(001BH)76543210TFF6TC6CKTC6STC6M(Initialvalue:00000000)TFF6TimerF/F6control0:1:ClearSetR/WTC6CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfc–111TC6pininputTC6STC6startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC6MTC6Moperatingmodeselect000:001:010:011:100:101:110:111:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmodeReserved16-bittimer/eventcountermodeWarm-upcountermode16-bitpulsewidthmodulation(PWM)outputmode16-bitPPGmodeR/WPage113TMP86FS23UGNote6:TotheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC5CR.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC6SandTFF6,respectively.
Note7:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-1andTable10-2.
Note8:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-3.
Note9:TousethePDO,PWMorPPGmode,apulseisnotoutputfromthetimeroutputpinwhenTC1CR2issetto1.
Tooutputapulsefromthetimeroutputpin,clearTC1CR2to0.
Note1:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC5CK).
Note2:Ο:AvailablesourceclockTable10-1OperatingModeandSelectableSourceClock(NORMAL1/2andIDLE1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC5pininputTC6pininput8-bittimerΟΟΟΟ8-biteventcounterΟΟ8-bitPDOΟΟΟΟ8-bitPWMΟΟΟΟΟΟΟ––16-bittimerΟΟΟΟ16-biteventcounterΟ–Warm-upcounter––––Ο––––16-bitPWMΟΟΟΟΟΟΟΟ–16-bitPPGΟΟΟΟ–––Ο–Table10-2OperatingModeandSelectableSourceClock(SLOW1/2andSLEEP1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC5pininputTC6pininput8-bittimerΟ8-biteventcounterΟΟ8-bitPDOΟ8-bitPWMΟ–––Ο––––16-bittimerΟ16-biteventcounterΟ–Warm-upcounterΟ––16-bitPWMΟ–––Ο––Ο–16-bitPPGΟΟ–Note1:Note2:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC5CK).
Ο:AvailablesourceclockPage11410.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UGNote:n=5to6Table10-3ConstraintsonRegisterValuesBeingComparedOperatingmodeRegisterValue8-bittimer/eventcounter1≤(TTREGn)≤2558-bitPDO1≤(TTREGn)≤2558-bitPWM2≤(PWREGn)≤25416-bittimer/eventcounter1≤(TTREG6,5)≤65535Warm-upcounter256≤(TTREG6,5)≤6553516-bitPWM2≤(PWREG6,5)≤6553416-bitPPG1≤(PWREG6,5)to0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Table10-4SourceClockforTimerCounter5,6(InternalClock)SourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
6ms62.
3msfc/27fc/27–8s–2.
0ms–fc/25fc/25–2s–510s–fc/23fc/23–500ns–127.
5s–Example:Settingthetimermodewithsourceclockfc/27Hzandgeneratinganinterrupt80slater(TimerCounter6,fc=16.
0MHz)LD(TTREG6),0AH:Setsthetimerregister(80s÷27/fc=0AH).
DISET(EIRH).
5:EnablesINTTC6interrupt.
EILD(TC6CR),00010000B:Setstheoperatingcocktofc/27,and8-bittimermode.
LD(TC6CR),00011000B:StartsTC6.
Page11610.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UGFigure10-28-BitTimerModeTimingChart(TC6)10.
3.
28-BitEventCounterMode(TC5,6)Inthe8-biteventcountermode,theup-countercountsupatthefallingedgeoftheinputpulsetotheTCjpin.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,anINTTCjinterruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTCjpin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTCjpin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24HzintheSLOW1/2orSLEEP1/2mode.
Note1:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Figure10-38-BitEventCounterModeTimingChart(TC6)10.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC5,6)Thismodeisusedtogenerateapulsewitha50%dutycyclefromthePDOjpin.
InthePDOmode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,thelogicleveloutputfromthePDOjpinisswitchedtotheoppositestateandtheup-counteriscleared.
TheINTTCjinterruptrequestisgeneratedatthetime.
ThelogicstateoppositetothetimerF/FjlogiclevelisoutputfromthePDOjpin.
AnarbitraryvaluecanbesettothetimerF/FjbyTCjCR.
Uponreset,thetimerF/Fjvalueisinitializedto0.
Tousetheprogrammabledivideroutput,settheoutputlatchoftheI/Oportto1.
123n-1n01n-1n20120nInternalSourceClockCounterMatchdetectCounterclearMatchdetectCounterclearTC6CRTTREG6INTTC6interruptrequest102n-1n0120nCounterMatchdetectCounterclearn-1n201MatchdetectCounterclearTC6CRTTREG6INTTC6interruptrequestTC6pininputPage117TMP86FS23UGNote1:Intheprogrammabledivideroutputmode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheprogrammabledivideroutputmode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPDOoutput,thePDOjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRsettinguponstoppingofthetimer.
Example:FixingthePDOjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePDOjpintothehighlevel.
Note3:j=5,6Example:Generating1024HzpulseusingTC6(fc=16.
0MHz)SettingportLD(TTREG6),3DH:1/1024÷27/fc÷2=3DHLD(TC6CR),00010001B:Setstheoperatingclocktofc/27,and8-bitPDOmode.
LD(TC6CR),00011001B:StartsTC6.
Page11810.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UGFigure10-48-BitPDOModeTimingChart(TC6)120n0n0n0n01221212310nInternalsourceclockCounterMatchdetectMatchdetectMatchdetectMatchdetectHeldatthelevelwhenthetimerisstoppedSetF/FWriteof"1"TC6CRTC6CRTTREG6TimerF/F6PDO6pinINTTC6interruptrequestPage119TMP86FS23UG10.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC5,6)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto8bitsofresolution.
Theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthePWREGjvalueisdetected,thelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestateagainbytheup-counteroverflow,andthecounteriscleared.
TheINTTCjinterruptrequestisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/FjbyTCjCR,positiveandnegativepulsescanbegen-erated.
Uponreset,thetimerF/Fjisclearedto0.
(ThelogicleveloutputfromthePWMjpinistheoppositetothetimerF/Fjlogiclevel.
)SincePWREGjinthePWMmodeisseriallyconnectedtotheshiftregister,thevaluesettoPWREGjcanbechangedwhilethetimerisrunning.
ThevaluesettoPWREGjduringarunofthetimerisshiftedbytheINTTCjinterruptrequestandloadedintoPWREGj.
Whilethetimerisstopped,thevalueisshiftedimmedi-atelyaftertheprogrammingofPWREGj.
IfexecutingthereadinstructiontoPWREGjduringPWMoutput,thevalueintheshiftregisterisread,butnotthevaluesetinPWREGj.
Therefore,afterwritingtoPWREGj,thereadingdataofPWREGjispreviousvalueuntilINTTCjisgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREGjimmediatelyaftertheINTTCjinterruptrequestisgenerated(normallyintheINTTCjinterruptserviceroutine.
)IftheprogrammingofPWREGjandtheinter-ruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofthepulsedifferentfromtheprogrammedvalueuntilthenextINTTCjinterruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWMjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRuponstoppingofthetimer.
Example:FixingthePWMjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePWMjpintothehighlevel.
Note3:ToentertheSTOPmodeduringPWMoutput,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwithoutstoppingthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisout-putfromthePWMjpinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Note4:j=5,6Table10-5PWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
8ms62.
5msfc/27fc/27–8s–2.
05ms–fc/25fc/25–2s–512s–fc/23fc/23–500ns–128s–fsfsfs30.
5s30.
5s7.
81ms7.
81msfc/2fc/2–125ns–32s–fcfc–62.
5ns–16s–Page12010.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UGFigure10-58-BitPWMModeTimingChart(TC6)10nn+1FF0nn+1FF01mm+1FF011pnInternalsourceclockCounterWritetoPWREG4WritetoPWREG4mpmpnShiftregistarShiftShiftShiftShiftMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectnmpnTC6CRTC6CRPWREG6TimerF/F6PWM6pinINTTC6interruptrequestPage121TMP86FS23UG10.
3.
516-BitTimerMode(TC5and6)Inthetimermode,theup-countercountsupusingtheinternalclock.
TheTimerCounter5and6arecascad-abletoforma16-bittimer.
Whenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,anINTTC6interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-countercontinuescounting.
Programtheupperbyteandlowerbyteinthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Inthetimermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMj,andPPGjpinsmayoutputapulse.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogrammingofTTREGj.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Figure10-616-BitTimerModeTimingChart(TC5andTC6)Table10-6SourceClockfor16-BitTimerModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23fs/23128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–Example:Settingthetimermodewithsourceclockfc/27Hz,andgeneratinganinterrupt300mslater(fc=16.
0MHz)LDW(TTREG5),927CH:Setsthetimerregister(300ms÷27/fc=927CH).
DISET(EIRH).
5:EnablesINTTC6interrupt.
EILD(TC5CR),13H:Setstheoperatingcocktofc/27,and16-bittimermode(lowerbyte).
LD(TC6CR),04H:Setsthe16-bittimermode(upperbyte).
LD(TC6CR),0CH:Startsthetimer.
1023mn-1mn01mn-1mn20120nmInternalsourceclockCounterMatchdetectCounterclearMatchdetectCounterclearTC6CRTTREG5(Lowerbyte)INTTC6interruptrequestTTREG6(Upperbyte)Page12210.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UG10.
3.
616-BitEventCounterMode(TC5and6)10.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC5and6)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto16bitsofresolution.
TheTimerCounter5and6arecascadabletoformthe16-bitPWMsignalgenerator.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG5,PWREG6)valueisdetected,thelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestateagainbythecounteroverflow,andthecounteriscleared.
TheINTTC6interruptisgeneratedatthistime.
Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC5pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1orIDLE1mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
SincetheinitialvaluecanbesettothetimerF/F6byTC6CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F6isclearedto0.
(ThelogicleveloutputfromthePWM6pinistheoppositetothetimerF/F6logiclevel.
)SincePWREG6and5inthePWMmodeareseriallyconnectedtotheshiftregister,thevaluessettoPWREG6and5canbechangedwhilethetimerisrunning.
ThevaluessettoPWREG6and5duringarunofthetimerareshiftedbytheINTTCjinterruptrequestandloadedintoPWREG6and5.
Whilethetimerisstopped,thevaluesareshiftedimmediatelyaftertheprogrammingofPWREG6and5.
Setthelowerbyte(PWREG5)andupperbyte(PWREG5)inthisordertoprogramPWREG6and5.
(Programmingonlythelowerorupperbyteoftheregistershouldnotbeattempted.
)IfexecutingthereadinstructiontoPWREG6and5duringPWMoutput,thevaluessetintheshiftregisterisread,butnotthevaluessetinPWREG6and5.
Therefore,afterwritingtothePWREG6and5,readingdataofPWREG6and5ispreviousvalueuntilINTTC6isgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREG6and5immediatelyaftertheINTTC6interruptrequestisgenerated(normallyintheINTTC6interruptserviceroutine.
)IftheprogrammingofPWREGjandtheinterruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofpulsedifferentfromtheprogrammedvalueuntilthenextINTTC6interruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWM6pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC6CRafterthetimerisstopped.
DonotprogramTC6CRuponstoppingofthetimer.
Example:FixingthePWM6pintothehighlevelwhentheTimerCounterisstoppedIntheeventcountermode,theup-countercountsupatthefallingedgetotheTC5pin.
TheTimerCounter5and6arecascadabletoforma16-biteventcounter.
Whenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,anINTTC6interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTC5pin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC5pin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1orIDLE1mode,andfs/24intheSLOW1/2orSLEEP1/2mode.
Programthelowerbyte(TTREG5),andupperbyte(TTREG6)inthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Note2:Note3:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimme-diatelyaftertheprogramming.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
j=5,6Page123TMP86FS23UGCLR(TC6CR).
3:Stopsthetimer.
CLR(TC6CR).
7:SetsthePWM6pintothehighlevel.
Note3:ToentertheSTOPmode,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwith-outstoppingofthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisoutputfromthePWM6pinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Table10-716-BitPWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23[Hz]fs/23[Hz]128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–fsfsfs30.
5s30.
5s2s2sfc/2fc/2–125ns–8.
2ms–fcfc–62.
5ns–4.
1ms–Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof32.
768ms(fc=16.
0MHz)SettingportsLDW(PWREG5),07D0H:Setsthepulsewidth.
LD(TC5CR),33H:Setstheoperatingclocktofc/23,and16-bitPWMoutputmode(lowerbyte).
LD(TC6CR),056H:SetsTFF6totheinitialvalue0,and16-bitPWMsignalgenerationmode(upperbyte).
LD(TC6CR),05EH:Startsthetimer.
Page12410.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UGFigure10-716-BitPWMModeTimingChart(TC5andTC6)10anan+1FFFF0anan+1FFFF01bmbm+1FFFF0bmcpbc11cpnaanInternalsourceclock16-bitshiftregisterShiftShiftShiftShiftCounterMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectanbmcpanmpTC6CRTC6CRPWREG5(Lowerbyte)TimerF/F6PWM6pinINTTC6interruptrequestPWREG6(Upperbyte)WritetoPWREG6WritetoPWREG6WritetoPWREG5WritetoPWREG5Page125TMP86FS23UG10.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC5and6)Thismodeisusedtogeneratepulseswithupto16-bitsofresolution.
Thetimercounter5and6arecascad-abletoenterthe16-bitPPGmode.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG5,PWREG6)valueisdetected,thelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestateagainwhenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetected,andthecounteriscleared.
TheINTTC6interruptisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/F6byTC6CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F6isclearedto0.
(ThelogicleveloutputfromthePPG6pinistheoppositetothetimerF/F6.
)Setthelowerbyteandupperbyteinthisordertoprogramthetimerregister.
(TTREG5→TTREG6,PWREG5→PWREG6)(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)ForPPGoutput,settheoutputlatchoftheI/Oportto1.
Note1:InthePPGmode,donotchangethePWREGiandTTREGisettingswhilethetimerisrunning.
SincePWREGiandTTREGiarenotintheshiftregisterconfigurationinthePPGmode,thenewvaluespro-grammedinPWREGiandTTREGiareineffectimmediatelyafterprogrammingPWREGiandTTREGi.
Therefore,ifPWREGiandTTREGiarechangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPPGoutput,thePPG6pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC6CRafterthetimerisstopped.
DonotchangeTC6CRuponstoppingofthetimer.
Example:FixingthePPG6pintothehighlevelwhentheTimerCounterisstoppedCLR(TC6CR).
3:StopsthetimerCLR(TC6CR).
7:SetsthePPG6pintothehighlevelNote3:i=5,6Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC5pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1orIDLE1mode,andfc/24tointheSLOW1/2orSLEEP1/2mode.
Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof16.
385ms(fc=16.
0MHz)SettingportsLDW(PWREG5),07D0H:Setsthepulsewidth.
LDW(TTREG5),8002H:Setsthecycleperiod.
LD(TC5CR),33H:Setstheoperatingclocktofc/23,and16-bitPPGmode(lowerbyte).
LD(TC6CR),057H:SetsTFF6totheinitialvalue0,and16-bitPPGmode(upperbyte).
LD(TC6CR),05FH:Startsthetimer.
Page12610.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UGFigure10-816-BitPPGModeTimingChart(TC5andTC60)10mnmn+1qr-1mnqr-11mnmn+1mn+10qr0qr10InternalsourceclockCounterWriteof"0"MatchdetectMatchdetectMatchdetectmnmnmnMatchdetectMatchdetectnmrqHeldatthelevelwhenthetimerstopsF/FclearTC6CRTC6CRPWREG5(Lowerbyte)TimerF/F6PPG6pinINTTC6interruptrequestPWREG6(Upperbyte)TTREG5(Lowerbyte)TTREG6(Upperbyte)Page127TMP86FS23UG10.
3.
9Warm-UpCounterModeInthismode,thewarm-upperiodtimeisobtainedtoassureoscillationstabilitywhenthesystemclockingisswitchedbetweenthehigh-frequencyandlow-frequency.
Thetimercounter5and6arecascadabletoforma16-bitTimerCouter.
Thewarm-upcountermodehastwotypesofmode;switchingfromthehigh-frequencytolow-frequency,andvice-versa.
Note1:Inthewarm-upcountermode,fixTCiCRto0.
Ifnotfixed,thePDOi,PWMiandPPGipinsmayoutputpulses.
Note2:Inthewarm-upcountermode,onlyupper8bitsofthetimerregisterTTREG6and5areusedformatchdetectionandlower8bitsarenotused.
Note3:i=5,610.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)Inthismode,thewarm-upperiodtimefromastopofthelow-frequencyclockfstooscillationstabilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethelow-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG6,5)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,thecounterisclearedbygeneratingtheINTTC6interruptrequest.
AfterstoppingthetimerintheINTTC6interruptserviceroutine,setSYSCR2to1toswitchthesystemclockfromthehigh-frequencytolow-frequency,andthenclearofSYSCR2to0tostopthehigh-frequencyclock.
Table10-8SettingTimeofLow-FrequencyWarm-UpCounterMode(fs=32.
768kHz)MaximumTimeSetting(TTREG6,5=0100H)MaximumTimeSetting(TTREG6,5=FF00H)7.
81ms1.
99sExample:Aftercheckinglow-frequencyclockoscillationstabilitywithTC6and5,switchingtotheSLOW1modeSET(SYSCR2).
6:SYSCR2←1LD(TC5CR),43H:SetsTFF5=0,sourceclockfs,and16-bitmode.
LD(TC6CR),05H:SetsTFF6=0,andwarm-upcountermode.
LD(TTREG5),8000H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRH).
5:EnablestheINTTC6.
EI:IMF←1SET(TC6CR).
3:StartsTC6and5.
::PINTTC6:CLR(TC6CR).
3:StopsTC6and5.
SET(SYSCR2).
5:SYSCR2←1(Switchesthesystemclocktothelow-frequencyclock.
)CLR(SYSCR2).
7:SYSCR2←0(Stopsthehigh-frequencyclock.
)RETI::VINTTC6:DWPINTTC6:INTTC6vectortablePage12810.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86FS23UG10.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)Inthismode,thewarm-upperiodtimefromastopofthehigh-frequencyclockfctotheoscillationsta-bilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethehigh-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG6,5)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,thecounterisclearedbygeneratingtheINTTC6interruptrequest.
AfterstoppingthetimerintheINTTC6interruptserviceroutine,clearSYSCR2to0toswitchthesystemclockfromthelow-frequencytohigh-frequency,andthenSYSCR2to0tostopthelow-frequencyclock.
Table10-9SettingTimeinHigh-FrequencyWarm-UpCounterModeMinimumtime(TTREG6,5=0100H)Maximumtime(TTREG6,5=FF00H)16s4.
08msExample:Aftercheckinghigh-frequencyclockoscillationstabilitywithTC6and5,switchingtotheNORMAL1modeSET(SYSCR2).
7:SYSCR2←1LD(TC5CR),63H:SetsTFF5=0,sourceclockfs,and16-bitmode.
LD(TC6CR),05H:SetsTFF6=0,andwarm-upcountermode.
LD(TTREG5),0F800H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRH).
5:EnablestheINTTC6.
EI:IMF←1SET(TC6CR).
3:StartstheTC6and5.
::PINTTC6:CLR(TC6CR).
3:StopstheTC6and5.
CLR(SYSCR2).
5:SYSCR2←0(Switchesthesystemclocktothehigh-frequencyclock.
)CLR(SYSCR2).
6:SYSCR2←0(Stopsthelow-frequencyclock.
)RETI::VINTTC6:DWPINTTC6:INTTC6vectortablePage129TMP86FS23UG11.
AsynchronousSerialinterface(UART)11.
1ConfigurationFigure11-1UART(AsynchronousSerialInterface)CounterYABCSSABCDYEFGHUARTstatusregisterUARTcontrolregister2UARTcontrolregister1TransmitdatabufferReceivedatabufferfc/13fc/26fc/52fc/104fc/208fc/416fc/96StopbitParitybitfc/26fc/27fc/28BaudrategeneratorTransmit/receiveclock243222NoiserejectioncircuitMPXTransmitcontrolcircuitShiftregisterShiftregisterReceivecontrolcircuitMPX:MultiplexerUARTCR1TDBUFRDBUFINTTXDINTRXDUARTSRUARTCR2RXDTXDINTTC5Page13011.
AsynchronousSerialinterface(UART)11.
2ControlTMP86FS23UG11.
2ControlUARTiscontrolledbytheUARTControlRegisters(UARTCR1,UARTCR2).
Theoperatingstatuscanbemoni-toredusingtheUARTstatusregister(UARTSR).
Note1:WhenoperationsaredisabledbysettingTXEandRXEbitto"0",thesettingbecomesvalidwhendatatransmitorreceivecomplete.
Whenthetransmitdataisstoredinthetransmitdatabuffer,thedataarenottransmitted.
Evenifdatatransmitisenabled,untilnewdataarewrittentothetransmitdatabuffer,thecurrentdataarenottransmitted.
Note2:Thetransmitclockandtheparityarecommontotransmitandreceive.
Note3:UARTCR1andUARTCR1shouldbesetto"0"beforeUARTCR1ischanged.
Note:WhenUARTCR2="01",pulseslongerthan96/fc[s]arealwaysregardedassignals;whenUARTCR2="10",longerthan192/fc[s];andwhenUARTCR2="11",longerthan384/fc[s].
UARTControlRegister1UARTCR1(0025H)76543210TXERXESTBTEVENPEBRG(Initialvalue:00000000)TXETransferoperation0:1:DisableEnableWriteonlyRXEReceiveoperation0:1:DisableEnableSTBTTransmitstopbitlength0:1:1bit2bitsEVENEven-numberedparity0:1:Odd-numberedparityEven-numberedparityPEParityaddition0:1:NoparityParityBRGTransmitclockselect000:001:010:011:100:101:110:111:fc/13[Hz]fc/26fc/52fc/104fc/208fc/416TC5(InputINTTC5)fc/96UARTControlRegister2UARTCR2(0026H)76543210RXDNCSTOPBR(Initialvalue:*****000)RXDNCSelectionofRXDinputnoiserejectiotime00:01:10:11:Nonoiserejection(Hysteresisinput)Rejectspulsesshorterthan31/fc[s]asnoiseRejectspulsesshorterthan63/fc[s]asnoiseRejectspulsesshorterthan127/fc[s]asnoiseWriteonlySTOPBRReceivestopbitlength0:1:1bit2bitsPage131TMP86FS23UGNote:WhenanINTTXDisgenerated,TBEPflagissetto"1"automatically.
UARTStatusRegisterUARTSR(0025H)76543210PERRFERROERRRBFLTENDTBEP(Initialvalue:000011**)PERRParityerrorflag0:1:NoparityerrorParityerrorReadonlyFERRFramingerrorflag0:1:NoframingerrorFramingerrorOERROverrunerrorflag0:1:NooverrunerrorOverrunerrorRBFLReceivedatabufferfullflag0:1:ReceivedatabufferemptyReceivedatabufferfullTENDTransmitendflag0:1:OntransmittingTransmitendTBEPTransmitdatabufferemptyflag0:1:Transmitdatabufferfull(Transmitdatawritingisfinished)TransmitdatabufferemptyUARTReceiveDataBufferRDBUF(0F9BH)76543210Readonly(Initialvalue:00000000)UARTTransmitDataBufferTDBUF(0F9BH)76543210Writeonly(Initialvalue:00000000)Page13211.
AsynchronousSerialinterface(UART)11.
3TransferDataFormatTMP86FS23UG11.
3TransferDataFormatInUART,anone-bitstartbit(Lowlevel),stopbit(Bitlengthselectableathighlevel,byUARTCR1),andparity(SelectparityinUARTCR1;even-orodd-numberedparitybyUARTCR1)areaddedtothetransferdata.
Thetransferdataformatsareshownasfollows.
Figure11-2TransferDataFormatFigure11-3CautiononChangingTransferDataFormatNote:Inordertoswitchthetransferdataformat,performtransmitoperationsintheaboveFigure11-3sequenceexceptfortheinitialsetting.
StartBit0Bit1Bit6Bit7Stop1StartBit0Bit1Bit6Bit7Stop1Stop2StartBit0Bit1Bit6Bit7ParityStop1StartBit0Bit1Bit6Bit7ParityStop1Stop2PE0011STBTFrameLength011238910111201Withoutparity/1STOPbitWithparity/1STOPbitWithoutparity/2STOPbitWithparity/2STOPbitPage133TMP86FS23UG11.
4TransferRateThebaudrateofUARTissetofUARTCR1.
Theexampleofthebaudrateareshownasfollows.
WhenTC5isusedastheUARTtransferrate(whenUARTCR1="110"),thetransferclockandtransferratearedeterminedasfollows:Transferclock[Hz]=TC5sourceclock[Hz]/TTREG5settingvalueTransferRate[baud]=Transferclock[Hz]/1611.
5DataSamplingMethodTheUARTreceiverkeepssamplinginputusingtheclockselectedbyUARTCR1untilastartbitisdetectedinRXDpininput.
RTclockstartsdetecting"L"leveloftheRXDpin.
Onceastartbitisdetected,thestartbit,databits,stopbit(s),andparitybitaresampledatthreetimesofRT7,RT8,andRT9duringonereceiverclockinterval(RTclock).
(RT0isthepositionwherethebitsupposedlystarts.
)Bitisdeterminedaccordingtomajorityrule(Thedataarethesametwiceormoreoutofthreesamplings).
Figure11-4DataSamplingMethodTable11-1TransferRate(Example)BRGSourceClock16MHz8MHz4MHz00076800[baud]38400[baud]19200[baud]00138400192009600010192009600480001196004800240010048002400120010124001200600RT012345678910111213141501234567891011Bit0StartbitBit0Startbit(a)WithoutnoiserejectioncircuitRTclockInternalreceivedataRT012345678910111213141501234567891011Bit0StartbitBit0StartbitRTclockInternalreceivedata(b)WithnoiserejectioncircuitRXDpinRXDpinPage13411.
AsynchronousSerialinterface(UART)11.
6STOPBitLengthTMP86FS23UG11.
6STOPBitLengthSelectatransmitstopbitlength(1bitor2bits)byUARTCR1.
11.
7ParitySetparity/noparitybyUARTCR1andsetparitytype(Odd-orEven-numbered)byUARTCR1.
11.
8Transmit/ReceiveOperation11.
8.
1DataTransmitOperationSetUARTCR1to"1".
ReadUARTSRtocheckUARTSR="1",thenwritedatainTDBUF(Transmitdatabuffer).
WritingdatainTDBUFzero-clearsUARTSR,transfersthedatatothetransmitshiftregisterandthedataaresequentiallyoutputfromtheTXDpin.
Thedataoutputincludeaone-bitstartbit,stopbitswhosenumberisspecifiedinUARTCR1andaparitybitifparityadditionisspecified.
SelectthedatatransferbaudrateusingUARTCR1.
Whendatatransmitstarts,transmitbufferemptyflagUARTSRissetto"1"andanINTTXDinterruptisgenerated.
WhileUARTCR1="0"andfromwhen"1"iswrittentoUARTCR1towhensenddataarewrittentoTDBUF,theTXDpinisfixedathighlevel.
Whentransmittingdata,firstreadUARTSR,thenwritedatainTDBUF.
Otherwise,UARTSRisnotzero-clearedandtransmitdoesnotstart.
11.
8.
2DataReceiveOperationSetUARTCR1to"1".
WhendataarereceivedviatheRXDpin,thereceivedataaretransferredtoRDBUF(Receivedatabuffer).
Atthistime,thedatatransmittedincludesastartbitandstopbit(s)andaparitybitifparityadditionisspecified.
Whenstopbit(s)arereceived,dataonlyareextractedandtransferredtoRDBUF(Receivedatabuffer).
ThenthereceivebufferfullflagUARTSRissetandanINTRXDinterruptisgenerated.
SelectthedatatransferbaudrateusingUARTCR1.
Ifanoverrunerror(OERR)occurswhendataarereceived,thedataarenottransferredtoRDBUF(Receivedatabuffer)butdiscarded;dataintheRDBUFarenotaffected.
Note:WhenareceiveoperationisdisabledbysettingUARTCR1bitto"0",thesettingbecomesvalidwhendatareceiveiscompleted.
However,ifaframingerroroccursindatareceive,thereceive-disablingsettingmaynotbecomevalid.
Ifaframingerroroccurs,besuretoperformare-receiveoperation.
Page135TMP86FS23UG11.
9StatusFlag11.
9.
1ParityErrorWhenparitydeterminedusingthereceivedatabitsdiffersfromthereceivedparitybit,theparityerrorflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterread-ingtheUARTSR.
Figure11-5GenerationofParityError11.
9.
2FramingErrorWhen"0"issampledasthestopbitinthereceivedata,framingerrorflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
Figure11-6GenerationofFramingError11.
9.
3OverrunErrorWhenallbitsinthenextdataarereceivedwhileunreaddataarestillinRDBUF,overrunerrorflagUARTSRissetto"1".
Inthiscase,thereceivedataisdiscarded;datainRDBUFarenotaffected.
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
ParityStopShiftregisterpxxxx0*1pxxxx0xxxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsPERR.
FinalbitStopShiftregisterxxxx0*0xxxx0xxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsFERR.
Page13611.
AsynchronousSerialinterface(UART)11.
9StatusFlagTMP86FS23UGFigure11-7GenerationofOverrunErrorNote:ReceiveoperationsaredisableduntiltheoverrunerrorflagUARTSRiscleared.
11.
9.
4ReceiveDataBufferFullLoadingthereceiveddatainRDBUFsetsreceivedatabufferfullflagUARTSRto"1".
TheUARTSRisclearedto"0"whentheRDBUFisreadafterreadingtheUARTSR.
Figure11-8GenerationofReceiveDataBufferFullNote:IftheoverrunerrorflagUARTSRissetduringtheperiodbetweenreadingtheUARTSRandreadingtheRDBUF,itcannotbeclearedbyonlyreadingtheRDBUF.
Therefore,afterreadingtheRDBUF,readtheUARTSRagaintocheckwhetherornottheoverrunerrorflagwhichshouldhavebeenclearedstillremainsset.
11.
9.
5TransmitDataBufferEmptyWhennodataisinthetransmitbufferTDBUF,UARTSRissetto"1",thatis,whendatainTDBUFaretransferredtothetransmitshiftregisteranddatatransmitstarts,transmitdatabufferemptyflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whentheTDBUFiswrittenafterreadingtheUARTSR.
FinalbitStopShiftregisterxxxx0*1xxxx0yyyyxxx0**RXDpinUARTSRINTRXDinterruptAfterreadingUARTSRthenRDBUFclearsOERR.
RDBUFUARTSRFinalbitStopShiftregisterxxxx0*1xxxx0xxxxyyyyxxx0**RXDpinUARTSRINTRXDinterruptRDBUFAfterreadingUARTSRthenRDBUFclearsRBFL.
Page137TMP86FS23UGFigure11-9GenerationofTransmitDataBufferEmpty11.
9.
6TransmitEndFlagWhendataaretransmittedandnodataisinTDBUF(UARTSR="1"),transmitendflagUARTSRissetto"1".
TheUARTSRisclearedto"0"whenthedatatransmitisstatedafterwritingtheTDBUF.
Figure11-10GenerationofTransmitEndFlagandTransmitDataBufferEmptyShiftregisterDatawriteDatawritezzzzxxxxyyyyStartBit0FinalbitStop1xxxx0*****1*1xxxx****1x*****11yyyy0TDBUFTXDpinUARTSRINTTXDinterruptAfterreadingUARTSRwritingTDBUFclearsTBEP.
Shiftregister*1yyyy***1xx****1x*****1StopStart1yyyy0Bit0TXDpinUARTSRUARTSRINTTXDinterruptDatawriteforTDBUFPage13811.
AsynchronousSerialinterface(UART)11.
9StatusFlagTMP86FS23UGPage139TMP86FS23UG12.
SynchronousSerialInterface(SIO)TheTMP86FS23UGhasaclocked-synchronous8-bitserialinterface.
Serialinterfacehasan8-bytetransmitandreceivedatabufferthatcanautomaticallyandcontinuouslytransferupto64bitsofdata.
SerialinterfaceisconnectedtooutsideperipherldevicesviaSO,SI,SCKport.
12.
1ConfigurationFigure12-1SerialInterfaceSIOcontrol/statusregisterSerialclockShiftclockShiftregister32107654Transmitandreceivedatabuffer(8bytesinDBR)ControlcircuitCPUSerialdataoutputSerialdatainput8-bittransfer4-bittransferSerialclockI/OBuffercontrolcircuitSOSISCKSIOCR2SIOCR1SIOSRINTSIOinterruptrequestPage14012.
SynchronousSerialInterface(SIO)12.
2ControlTMP86FS23UG12.
2ControlTheserialinterfaceiscontrolledbySIOcontrolregisters(SIOCR1/SIOCR2).
TheserialinterfacestatuscanbedeterminedbyreadingSIOstatusregister(SIOSR).
ThetransmitandreceivedatabufferiscontrolledbytheSIOCR2.
Thedatabufferisassignedtoaddress0F90Hto0F97HforSIOintheDBRarea,andcancontinuouslytransferupto8words(bytesornibbles)atonetime.
Whenthespecifiednumberofwordshasbeentransferred,abufferempty(inthetransmitmode)orabufferfull(inthereceivemodeortransmit/receivemode)interrupt(INTSIO)isgenerated.
Whentheinternalclockisusedastheserialclockinthe8-bitreceivemodeandthe8-bittransmit/receivemode,afixedintervalwaitcanbeappliedtotheserialclockforeachwordtransferred.
FourdifferentwaittimescanbeselectedwithSIOCR2.
Note1:fc;High-frequencyclock[Hz],fs;Low-frequencyclock[Hz]Note2:SetSIOSto"0"andSIOINHto"1"whensettingthetransfermodeorserialclock.
Note3:SIOCR1iswrite-onlyregister,whichcannotaccessanyofinread-modify-writeinstructionsuchasbitoperate,etc.
SIOControlRegister1SIOCR176543210(0F98H)SIOSSIOINHSIOMSCK(Initialvalue:00000000)SIOSIndicatetransferstart/stop0:StopWriteonly1:StartSIOINHContinue/aborttransfer0:Continuouslytransfer1:Aborttransfer(Automaticallyclearedafterabort)SIOMTransfermodeselect000:8-bittransmitmode010:4-bittransmitmode100:8-bittransmit/receivemode101:8-bitreceivemode110:4-bitreceivemodeExcepttheabove:ReservedSCKSerialclockselectNORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeWriteonlyDV7CK=0DV7CK=1000fc/213fs/25fs/25001fc/28fc/28-010fc/27fc/27-011fc/26fc/26-100fc/25fc/25-101fc/24fc/24-110Reserved111Externalclock(InputfromSCKpin)SIOControlRegister2SIOCR276543210(0F99H)WAITBUF(Initialvalue:***00000)Page141TMP86FS23UGNote1:Thelower4bitsofeachbufferareusedduring4-bittransfers.
Zeros(0)arestoredtotheupper4bitswhenreceiving.
Note2:Transmittingstartsatthelowestaddress.
Receiveddataarealsostoredstartingfromthelowestaddresstothehighestaddress.
(Thefirstbufferaddresstransmittedis0F90H).
Note3:ThevaluetobeloadedtoBUFisheldaftertransferiscompleted.
Note4:SIOCR2mustbesetwhentheserialinterfaceisstopped(SIOF=0).
Note5:*:Don'tcareNote6:SIOCR2iswrite-onlyregister,whichcannotaccessanyofinread-modify-writeinstructionsuchasbitoperate,etc.
Note1:Tf;Frametime,TD;DatatransfertimeNote2:AfterSIOSisclearedto"0",SIOFisclearedto"0"attheterminationoftransferorthesettingofSIOINHto"1".
Figure12-2Frametime(Tf)andDatatransfertime(TD)12.
3Serialclock12.
3.
1ClocksourceInternalclockorexternalclockforthesourceclockisselectedbySIOCR1.
WAITWaitcontrolAlwayssets"00"except8-bittransmit/receivemode.
Writeonly00:Tf=TD(Nonwait)01:Tf=2TD(Wait)10:Tf=4TD(Wait)11:Tf=8TD(Wait)BUFNumberoftransferwords(Bufferaddressinuse)000:1wordtransfer0F90H001:2wordstransfer0F90H~0F91H010:3wordstransfer0F90H~0F92H011:4wordstransfer0F90H~0F93H100:5wordstransfer0F90H~0F94H101:6wordstransfer0F90H~0F95H110:7wordstransfer0F90H~0F96H111:8wordstransfer0F90H~0F97HSIOStatusRegisterSIOSR76543210(0F99H)SIOFSEFSIOFSerialtransferoperatingstatusmoni-tor0:1:TransferterminatedTransferinprocessReadonlySEFShiftoperatingstatusmonitor0:1:ShiftoperationterminatedShiftoperationinprocessTDTf(output)SCKoutputPage14212.
SynchronousSerialInterface(SIO)12.
3SerialclockTMP86FS23UG12.
3.
1.
1InternalclockAnyofsixfrequenciescanbeselected.
TheserialclockisoutputtotheoutsideontheSCKpin.
TheSCKpingoeshighwhentransferstarts.
Whendatawriting(inthetransmitmode)orreading(inthereceivemodeorthetransmit/receivemode)cannotkeepupwiththeserialclockrate,thereisawaitfunctionthatautomaticallystopstheserialclockandholdsthenextshiftoperationuntiltheread/writeprocessingiscompleted.
Note:1Kbit=1024bit(fc=16MHz,fs=32.
768kHz)Figure12-3AutomaticWaitFunction(at4-bittransmitmode)12.
3.
1.
2ExternalclockAnexternalclockconnectedtotheSCKpinisusedastheserialclock.
Inthiscase,outputlatchofthisportshouldbesetto"1".
Toensureshifting,apulsewidthofatleast4machinecyclesisrequired.
Thispulseisneededfortheshiftoperationtoexecutecertainly.
Actually,thereisnecessaryprocessingtimeforinterrupting,writing,andreading.
Theminimumpulseisdeterminedbysettingthemodeandthepro-gram.
Therfore,maximumtransferfrequencywillbe488.
3Kbit/sec(atfc=16MHz).
Figure12-4ExternalclockpulsewidthTable12-1SerialClockRateNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modeDV7CK=0DV7CK=1SCKClockBaudRateClockBaudRateClockBaudRate000fc/2131.
91Kbpsfs/251024bpsfs/251024bps001fc/2861.
04Kbpsfc/2861.
04Kbps--010fc/27122.
07Kbpsfc/27122.
07Kbps--011fc/26244.
14Kbpsfc/26244.
14Kbps--100fc/25488.
28Kbpsfc/25488.
28Kbps--101fc/24976.
56Kbpsfc/24976.
56Kbps--110111ExternalExternalExternalExternalExternalExternala1a2b0b1b2b3c0c1a3acba0pin(output)pin(output)WrittentransmitdataAutomaticallywaitfunctionSCKSOtSCKLtSCKHtcyc=4/fc(IntheNORMAL1/2,IDLE1/2modes)4/fs(IntheSLOW1/2,SLEEP1/2modes)tSCKL,tSCKH>4tcycSCKpin(Output)Page143TMP86FS23UG12.
3.
2ShiftedgeTheleadingedgeisusedtotransmit,andthetrailingedgeisusedtoreceive.
12.
3.
2.
1LeadingedgeTransmitteddataareshiftedontheleadingedgeoftheserialclock(fallingedgeoftheSCKpininput/output).
12.
3.
2.
2TrailingedgeReceiveddataareshiftedonthetrailingedgeoftheserialclock(risingedgeoftheSCKpininput/out-put).
Figure12-5Shiftedge12.
4NumberofbitstotransferEither4-bitor8-bitserialtransfercanbeselected.
When4-bitserialtransferisselected,onlythelower4bitsofthetransmit/receivedatabufferregisterareused.
Theupper4bitsareclearedto"0"whenreceiving.
Thedataistransferredinsequencestartingattheleastsignificantbit(LSB).
12.
5NumberofwordstotransferUpto8wordsconsistingof4bitsofdata(4-bitserialtransfer)or8bits(8-bitserialtransfer)ofdatacanbetrans-ferredcontinuously.
ThenumberofwordstobetransferredcanbeselectedbySIOCR2.
AnINTSIOinterruptisgeneratedwhenthespecifiednumberofwordshasbeentransferred.
Ifthenumberofwordsistobechangedduringtransfer,theserialinterfacemustbestoppedbeforemakingthechange.
Thenumberofwordscanbechangedduringautomatic-waitoperationofaninternalclock.
Inthiscase,theserialinterfaceisnotrequiredtobestopped.
Bit1Bit2Bit3*3213210**32***3Bit0ShiftregisterShiftregisterBit1Bit0Bit2Bit30*******210*10**3210(a)Leadingedge(b)Trailingedge*;Don'tcareSOpinSIpinSCKpinSCKpinPage14412.
SynchronousSerialInterface(SIO)12.
6TransferModeTMP86FS23UGFigure12-6Numberofwordstotransfer(Example:1word=4bit)12.
6TransferModeSIOCR1isusedtoselectthetransmit,receive,ortransmit/receivemode.
12.
6.
14-bitand8-bittransfermodesInthesemodes,firstlysettheSIOcontrolregistertothetransmitmode,andthenwritefirsttransmitdata(numberoftransferwordstobetransferred)tothedatabufferregisters(DBR).
Afterthedataarewritten,thetransmissionisstartedbysettingSIOCR1to"1".
ThedataarethenoutputsequentiallytotheSOpininsynchronouswiththeserialclock,startingwiththeleastsignificantbit(LSB).
AssoonastheLSBhasbeenoutput,thedataaretransferredfromthedatabufferregistertotheshiftregister.
Whenthefinaldatabithasbeentransferredandthedatabufferregisterisempty,anINTSIO(Bufferempty)interruptisgeneratedtorequestthenexttransmitteddata.
Whentheinternalclockisused,theserialclockwillstopandanautomatic-waitwillbeinitiatedifthenexttransmitteddataarenotloadedtothedatabufferregisterbythetimethenumberofdatawordsspecifiedwiththeSIOCR2hasbeentransmitted.
Writingevenonewordofdatacancelstheautomatic-wait;therefore,whentransmittingtwoormorewords,alwayswritethenextwordbeforetransmissionofthepreviouswordiscompleted.
Note:AutomaticwaitsarealsocanceledbywritingtoaDBRnotbeingusedasatransmitdatabufferregister;there-fore,duringSIOdonotusesuchDBRforotherapplications.
Forexample,when3wordsaretransmitted,donotusetheDBRoftheremained5words.
Whenanexternalclockisused,thedatamustbewrittentothedatabufferregisterbeforeshiftingnextdata.
Thus,thetransferspeedisdeterminedbythemaximumdelaytimefromthegenerationoftheinterruptrequesttowritingofthedatatothedatabufferregisterbytheinterruptserviceprogram.
ThetransmissionisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inbufferemptyinterruptserviceprogram.
a1a2a3a0a1a2a3b0b1b2b3c0c1c2c3a0a1a0a2a3b0b1b2b3c0c1c2c3(a)1wordtransmit(b)3wordstransmit(c)3wordsreceiveSOpinINTSIOinterruptINTSIOinterruptINTSIOinterruptSOpinSIpinSCKpinSCKpinSCKpinPage145TMP86FS23UGSIOCR1iscleared,theoperationwillendafterallbitsofwordsaretransmitted.
ThatthetransmissionhasendedcanbedeterminedfromthestatusofSIOSRbecauseSIOSRisclearedto"0"whenatransferiscompleted.
WhenSIOCR1isset,thetransmissionisimmediatelyendedandSIOSRisclearedto"0".
Whenanexternalclockisused,itisalsonecessarytoclearSIOCR1to"0"beforeshiftingthenextdata;IfSIOCR1isnotclearedbeforeshiftout,dummydatawillbetransmittedandtheoperationwillend.
Ifitisnecessarytochangethenumberofwords,SIOCR1shouldbeclearedto"0",thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Figure12-7TransferMode(Example:8bit,1wordtransfer,Internalclock)Figure12-8TransferMode(Example:8bit,1wordtransfer,Externalclock)a1a2a3a4a5a6a7b0b1b2b3b4b5b6b7a0DBRbaClearSIOSWrite(a)Write(b)SCKpin(Output)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRSIOSRa1a2a3a4a5a6a7b0b1b2b3b4b5b6b7a0DBRbaClearSIOSWrite(a)Write(b)SCKpin(Input)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRPage14612.
SynchronousSerialInterface(SIO)12.
6TransferModeTMP86FS23UGFigure12-9TransmiiiedDataHoldTimeatEndofTransfer12.
6.
24-bitand8-bitreceivemodesAftersettingthecontrolregisterstothereceivemode,setSIOCR1to"1"toenablereceiving.
ThedataarethentransferredtotheshiftregisterviatheSIpininsynchronouswiththeserialclock.
Whenonewordofdatahasbeenreceived,itistransferredfromtheshiftregistertothedatabufferregister(DBR).
WhenthenumberofwordsspecifiedwiththeSIOCR2hasbeenreceived,anINTSIO(Bufferfull)interruptisgeneratedtorequestthatthesedatabereadout.
Thedataarethenreadfromthedatabufferregistersbytheinterruptserviceprogram.
Whentheinternalclockisused,andthepreviousdataarenotreadfromthedatabufferregisterbeforethenextdataarereceived,theserialclockwillstopandanautomatic-waitwillbeinitiateduntilthedataareread.
Awaitwillnotbeinitiatedifevenonedatawordhasbeenread.
Note:WaitsarealsocanceledbyreadingaDBRnotbeingusedasareceiveddatabufferregisterisread;therefore,duringSIOdonotusesuchDBRforotherapplications.
Whenanexternalclockisused,theshiftoperationissynchronizedwiththeexternalclock;therefore,thepreviousdataarereadbeforethenextdataaretransferredtothedatabufferregister.
Ifthepreviousdatahavenotbeenread,thenextdatawillnotbetransferredtothedatabufferregisterandthereceivingofanymoredatawillbecanceled.
Whenanexternalclockisused,themaximumtransferspeedisdeterminedbythedelaybetweenthetimewhentheinterruptrequestisgeneratedandwhenthedatareceivedhavebeenread.
ThereceivingisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inbufferfullinterruptserviceprogram.
WhenSIOCR1iscleared,thecurrentdataaretransferredtothebuffer.
AfterSIOCR1cleared,thereceivingisendedatthetimethatthefinalbitofthedatahasbeenreceived.
ThatthereceivinghasendedcanbedeterminedfromthestatusofSIOSR.
SIOSRisclearedto"0"whenthereceiv-ingisended.
Afterconfirmedthereceivingtermination,thefinalreceivingdataisread.
WhenSIOCR1isset,thereceivingisimmediatelyendedandSIOSRisclearedto"0".
(Thereceiveddataisignored,anditisnotrequiredtobereadout.
)Ifitisnecessarytochangethenumberofwordsinexternalclockoperation,SIOCR1shouldbeclearedto"0"thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Ifitisnecessarytochangethenumberofwordsininternalclock,duringautomatic-waitoperationwhichoccursaftercompletionofdatareceiving,SIOCR2mustberewrittenbeforethereceiveddataisreadout.
Note:Thebuffercontentsarelostwhenthetransfermodeisswitched.
Ifitshouldbecomenecessarytoswitchthetransfermode,endreceivingbyclearingSIOCR1to"0",readthelastdataandthenswitchthetrans-fermode.
MSBoflastwordtSODH=min3.
5/fc[s](IntheNORMAL1/2,IDLE1/2modes)tSODH=min3.
5/fs[s](IntheSLOW1/2,SLEEP1/2modes)SCKpinSOpinSIOSRPage147TMP86FS23UGFigure12-10ReceiveMode(Example:8bit,1wordtransfer,Internalclock)12.
6.
38-bittransfer/receivemodeAftersettingtheSIOcontrolregistertothe8-bittransmit/receivemode,writethedatatobetransmittedfirsttothedatabufferregisters(DBR).
Afterthat,enablethetransmit/receivebysettingSIOCR1to"1".
Whentransmitting,thedataareoutputfromtheSOpinatleadingedgesoftheserialclock.
Whenreceiving,thedataareinputtotheSIpinatthetrailingedgesoftheserialclock.
Whentheallreceiveisenabled,8-bitdataaretransferredfromtheshiftregistertothedatabufferregister.
AnINTSIOinterruptisgeneratedwhenthenumberofdatawordsspecifiedwiththeSIOCR2hasbeentransferred.
Usually,readthereceivedatafromthebufferregisterintheinterruptservice.
Thedatabufferregisterisusedforbothtransmittingandreceiving;therefore,alwayswritethedatatobetransmittedafterreadingtheallreceiveddata.
Whentheinternalclockisused,awaitisinitiateduntilthereceiveddataarereadandthenexttransferdataarewritten.
Awaitwillnotbeinitiatedifevenonetransferdatawordhasbeenwritten.
Whenanexternalclockisused,theshiftoperationissynchronizedwiththeexternalclock;therefore,itisnecessarytoreadthereceiveddataandwritethedatatobetransmittednextbeforestartingthenextshiftoper-ation.
Whenanexternalclockisused,thetransferspeedisdeterminedbythemaximumdelaybetweengenera-tionofaninterruptrequestandthereceiveddataarereadandthedatatobetransmittednextarewritten.
Thetransmit/receiveoperationisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inINTSIOinterruptserviceprogram.
WhenSIOCR1iscleared,thecurrentdataaretransferredtothebuffer.
AfterSIOCR1cleared,thetransmitting/receivingisendedatthetimethatthefinalbitofthedatahasbeentransmitted.
Thatthetransmitting/receivinghasendedcanbedeterminedfromthestatusofSIOSR.
SIOSRisclearedto"0"whenthetransmitting/receivingisended.
WhenSIOCR1isset,thetransmit/receiveoperationisimmediatelyendedandSIOSRisclearedto"0".
Ifitisnecessarytochangethenumberofwordsinexternalclockoperation,SIOCR1shouldbeclearedto"0",thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Ifitisnecessarytochangethenumberofwordsininternalclock,duringautomatic-waitoperationwhichoccursaftercompletionoftransmit/receiveoperation,SIOCR2mustberewrittenbeforereadingandwritingofthereceive/transmitdata.
a1a0a2a3a4a5a6a7b0b1b2b3b4b5b6b7DBRbaClearSIOSReadoutReadoutSCKpin(Output)SIpinINTSIOInterruptSIOCR1SIOSRSIOSRPage14812.
SynchronousSerialInterface(SIO)12.
6TransferModeTMP86FS23UGNote:Thebuffercontentsarelostwhenthetransfermodeisswitched.
Ifitshouldbecomenecessarytoswitchthetransfermode,endreceivingbyclearingSIOCR1to"0",readthelastdataandthenswitchthetrans-fermode.
Figure12-11Transfer/ReceiveMode(Example:8bit,1wordtransfer,Internalclock)Figure12-12TransmittedDataHoldTimeatEndofTransfer/Receivea1a0a2a3a4a5a6a7b0b1b2b3b4b5b6b7c1c0c2c3c4c5cbc6c7d0d1d2d3d4d5d6d7ClearSIOSDBRdaReadout(c)Write(a)Readout(d)Write(b)SCKpin(output)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRSIpinBit7oflastwordBit6tSODH=min4/fc[s](IntheNORMAL1/2,IDLE1/2modes)tSODH=min4/fs[s](IntheSLOW1/2,SLEEP1/2modes)SCKpinSOpinSIOSRPage149TMP86FS23UG13.
10-bitADConverter(ADC)TheTMP86FS23UGhavea10-bitsuccessiveapproximationtypeADconverter.
13.
1ConfigurationThecircuitconfigurationofthe10-bitADconverterisshowninFigure13-1.
ItconsistsofcontrolregisterADCCR1andADCCR2,convertedvalueregisterADCDR1andADCDR2,aDAconverter,asample-holdcircuit,acomparator,andasuccessivecomparisoncircuit.
Note:BeforeusingADconverter,setappropriatevaluetoI/Oportregisterconbiningaanaloginputport.
Fordetails,seethesec-tionon"I/Oports".
Figure13-110-bitADConverter24108AINDSADRSR/2R/2RACKAMDIREFONADconversionresultregister1,2ADconvertercontrolregister1,2ADBFEOCFINTADCSAINnSuccessiveapproximatecircuitADCCR2ADCDR1ADCDR2ADCCR1SampleholdcircuitASENShiftclockDAconverterAnaloginputmultiplexerYReferencevoltageAnalogcomparator23ControlcircuitVSSVAREFAVDDAIN0AIN7Page15013.
10-bitADConverter(ADC)13.
2RegisterconfigurationTMP86FS23UG13.
2RegisterconfigurationTheADconverterconsistsofthefollowingfourregisters:1.
ADconvertercontrolregister1(ADCCR1)Thisregisterselectstheanalogchannelsandoperationmode(Softwarestartorrepeat)inwhichtoper-formADconversionandcontrolstheADconverterasitstartsoperating.
2.
ADconvertercontrolregister2(ADCCR2)ThisregisterselectstheADconversiontimeandcontrolstheconnectionoftheDAconverter(Ladderresistornetwork).
3.
ADconvertedvalueregister1(ADCDR1)ThisregisterusedtostorethedigitalvaluefterbeingconvertedbytheADconverter.
4.
ADconvertedvalueregister2(ADCDR2)ThisregistermonitorstheoperatingstatusoftheADconverter.
Note1:SelectanaloginputchannelduringADconverterstops(ADCDR2="0").
Note2:Whentheanaloginputchannelisallusedisabling,theADCCR1shouldbesetto"1".
Note3:Duringconversion,Donotperformportoutputinstructiontomaintainaprecisionforallofthepinsbecauseanaloginputportuseasgeneralinputport.
Andforportneartoanaloginput,Donotinputintensesignalingofchange.
Note4:TheADCCR1isautomaticallyclearedto"0"afterstartingconversion.
Note5:DonotsetADCCR1newlyagainduringADconversion.
BeforesettingADCCR1newlyagain,checkADCDR2toseethattheconversioniscompletedorwaituntiltheinterruptsignal(INTADC)isgenerated(e.
g.
,interrupthandlingroutine).
Note6:AfterSTOPorSLOW/SLEEPmodearestarted,ADconvertercontrolregister1(ADCCR1)isallinitializedandnodatacanbewritteninthisregister.
Therfore,touseADconverteragain,settheADCCR1newlyafterreturningtoNORMAL1orNORMAL2mode.
ADConverterControlRegister1ADCCR1(000EH)76543210ADRSAMDAINDSSAIN(Initialvalue:00010000)ADRSADconversionstart0:1:-ADconversionstartR/WAMDADoperatingmode00:01:10:11:ADoperationdisableSoftwarestartmodeReservedRepeatmodeAINDSAnaloginputcontrol0:1:AnaloginputenableAnaloginputdisableSAINAnaloginputchannelselect0000:0001:0010:0011:0100:0101:0110:0111:1000:1001:1010:1011:1100:1101:1110:1111:AIN0AIN1AIN2AIN3AIN4AIN5AIN6AIN7ReservedReservedReservedReservedReservedReservedReservedReservedPage151TMP86FS23UGNote1:Alwayssetbit0inADCCR2to"0"andsetbit4inADCCR2to"1".
Note2:WhenareadinstructionforADCCR2,bit6to7inADCCR2readinasundefineddata.
Note3:AfterSTOPorSLOW/SLEEPmodearestarted,ADconvertercontrolregister2(ADCCR2)isallinitializedandnodatacanbewritteninthisregister.
Therfore,touseADconverteragain,settheADCCR2newlyafterreturningtoNORMAL1orNORMAL2mode.
Note1:Settingfor""intheabovetableareinhibited.
fc:HighFrequencyoscillationclock[Hz]Note2:SetconversiontimesettingshouldbekeptmorethanthefollowingtimebyAnalogreferencevoltage(VAREF).
ADConverterControlRegister2ADCCR2(000FH)76543210IREFON"1"ACK"0"(Initialvalue:**0*000*)IREFONDAconverter(Ladderresistor)connectioncontrol0:1:ConnectedonlyduringADconversionAlwaysconnectedR/WACKADconversiontimeselect(Refertothefollowingtableaboutthecon-versiontime)000:001:010:011:100:101:110:111:39/fcReserved78/fc156/fc312/fc624/fc1248/fcReservedTable13-1ACKsettingandConversiontimeConditionConversiontime16MHz8MHz4MHz2MHz10MHz5MHz2.
5MHzACK00039/fc---19.
5s--15.
6s001Reserved01078/fc--19.
5s39.
0s-15.
6s31.
2s011156/fc-19.
5s39.
0s78.
0s15.
6s31.
2s62.
4s100312/fc19.
5s39.
0s78.
0s156.
0s31.
2s62.
4s124.
8s101624/fc39.
0s78.
0s156.
0s-62.
4s124.
8s-1101248/fc78.
0s156.
0s--124.
8s--111Reserved-VAREF=4.
5to5.
5V15.
6sandmore-VAREF=2.
7to5.
5V31.
2sandmoreADConvertedvalueRegister1ADCDR1(0021H)76543210AD09AD08AD07AD06AD05AD04AD03AD02(Initialvalue:00000000)ADConvertedvalueRegister2ADCDR2(0020H)76543210AD01AD00EOCFADBF(Initialvalue:0000****)Page15213.
10-bitADConverter(ADC)13.
2RegisterconfigurationTMP86FS23UGNote1:TheADCDR2isclearedto"0"whenreadingtheADCDR1.
Therfore,theADconversionresultshouldbereadtoADCDR2morefirstthanADCDR1.
Note2:TheADCDR2issetto"1"whenADconversionstarts,andclearedto"0"whenADconversionfinished.
ItalsoiscleareduponenteringSTOPmodeorSLOWmode.
Note3:IfareadinstructionisexecutedforADCDR2,readdataofbit3tobit0areunstable.
EOCFADconversionendflag0:1:BeforeorduringconversionConversioncompletedReadonlyADBFADconversionBUSYflag0:1:DuringstopofADconversionDuringADconversionPage153TMP86FS23UG13.
3Function13.
3.
1SoftwareStartModeAftersettingADCCR1to"01"(softwarestartmode),setADCCR1to"1".
ADconver-sionofthevoltageattheanaloginputpinspecifiedbyADCCR1istherebystarted.
AftercompletionoftheADconversion,theconversionresultisstoredinADconvertedvalueregisters(ADCDR1,ADCDR2)andatthesametimeADCDR2issetto1,theADconversionfinishedinter-rupt(INTADC)isgenerated.
ADRSisautomaticallyclearedafterADconversionhasstarted.
DonotsetADCCR1newlyagain(Restart)duringADconversion.
BeforesettingADRSnewlyagain,checkADCDR2toseethattheconversioniscompletedorwaituntiltheinterruptsignal(INTADC)isgenerated(e.
g.
,interrupthandlingrou-tine).
Figure13-2SoftwareStartMode13.
3.
2RepeatModeADconversionofthevoltageattheanaloginputpinspecifiedbyADCCR1isperformedrepeatedly.
Inthismode,ADconversionisstartedbysettingADCCR1to"1"aftersettingADCCR1to"11"(Repeatmode).
AftercompletionoftheADconversion,theconversionresultisstoredinADconvertedvalueregisters(ADCDR1,ADCDR2)andatthesametimeADCDR2issetto1,theADconversionfinishedinter-rupt(INTADC)isgenerated.
Inrepeatmode,eachtimeoneADconversioniscompleted,thenextADconversionisstarted.
TostopADconversion,setADCCR1to"00"(Disablemode)bywriting0s.
TheADconvertoperationisstoppedimmediately.
TheconvertedvalueatthistimeisnotstoredintheADconvertedvalueregister.
ADCDR1statusEOCFclearedbyreadingconversionresultConversionresultreadADCDR2INTADCinterruptrequestADCDR2ADCCR11stconversionresult2ndconversionresultIndeterminateADconversionstartADconversionstartADCDR1ADCDR2ConversionresultreadConversionresultreadConversionresultreadPage15413.
10-bitADConverter(ADC)13.
3FunctionTMP86FS23UGFigure13-3RepeatMode13.
3.
3RegisterSetting1.
SetuptheADconvertercontrolregister1(ADCCR1)asfollows:ChoosethechanneltoADconvertusingADinputchannelselect(SAIN).
Specifyanaloginputenableforanaloginputcontrol(AINDS).
SpecifyAMDfortheADconvertercontroloperationmode(softwareorrepeatmode).
2.
SetuptheADconvertercontrolregister2(ADCCR2)asfollows:SettheADconversiontimeusingADconversiontime(ACK).
Fordetailsonhowtosetthecon-versiontime,refertoFigure13-1andADconvertercontrolregister2.
ChooseIREFONforDAconvertercontrol.
3.
Aftersettingup(1)and(2)above,setADconversionstart(ADRS)ofADconvertercontrolregister1(ADCCR1)to"1".
Ifsoftwarestartmodehasbeenselected,ADconversionstartsimmediately.
4.
AfteranelapseofthespecifiedADconversiontime,theADconvertedvalueisstoredinADcon-vertedvalueregister1(ADCDR1)andtheADconversionfinishedflag(EOCF)ofADconvertedvalueregister2(ADCDR2)issetto"1",uponwhichtimeADconversioninterruptINTADCisgener-ated.
5.
EOCFisclearedto"0"byareadoftheconversionresult.
However,ifreconvertedbeforearegisterread,althoughEOCFisclearedthepreviousconversionresultisretaineduntilthenextconversioniscompleted.
ADCDR1,ADCDR2EOCFclearedbyreadingconversionresultConversionresultreadADCDR2INTADCinterruptrequestConversionoperationADCCR1IndeterminateADconversionstartADCCR1"11""00"1stconversionresultADconvertoperationsuspended.
Conversionresultisnotstored.
2ndconversionresult3rdconversionresultADCDR1ADCDR22ndconversionresult3rdconversionresult1stconversionresultConversionresultreadConversionresultreadConversionresultreadConversionresultreadConversionresultreadPage155TMP86FS23UG13.
4STOP/SLOWModesduringADConversionWhenstandbymode(STOPorSLOWmode)isenteredforciblyduringADconversion,theADconvertoperationissuspendedandtheADconverterisinitialized(ADCCR1andADCCR2areinitializedtoinitialvalue).
Also,theconversionresultisindeterminate.
(Conversionresultsuptothepreviousoperationarecleared,sobesuretoreadtheconversionresultsbeforeenteringstandbymode(STOPorSLOWmode).
)Whenrestoredfromstandbymode(STOPorSLOWmode),ADconversionisnotautomaticallyrestarted,soitisnecessarytorestartADconversion.
Notethatsincetheanalogreferencevoltageisautomaticallydisconnected,thereisnopossibilityofcurrentflowingintotheanalogreferencevoltage.
Example:Afterselectingtheconversiontime19.
5sat16MHzandtheanaloginputchannelAIN3pin,performADcon-versiononce.
AftercheckingEOCF,readtheconvertedvalue,storethelower2bitsinaddress0009EHndstoretheupper8bitsinaddress0009FHinRAM.
Theoperationmodeissoftwarestartmode.
:(portsetting):;SetportregisterapprorriatelybeforesettingADconverterregisters.
::(RefertosectionI/Oportindetails)LD(ADCCR1),00100011B;SelectAIN3LD(ADCCR2),11011000B;Selectconversiontime(312/fc)andoperationmodeSET(ADCCR1).
7;ADRS=1(ADconversionstart)SLOOP:TEST(ADCDR2).
5;EOCF=1JRST,SLOOPLDA,(ADCDR2);ReadresultdataLD(9EH),ALDA,(ADCDR1);ReadresultdataLD(9FH),APage15613.
10-bitADConverter(ADC)13.
5AnalogInputVoltageandADConversionResultTMP86FS23UG13.
5AnalogInputVoltageandADConversionResultTheanaloginputvoltageiscorrespondedtothe10-bitdigitalvalueconvertedbytheADasshowninFigure13-4.
Figure13-4AnalogInputVoltageandADConversionResult(Typ.
)1001H02H03H3FDH3FEH3FFH231021102210231024Analoginputvoltage1024ADconversionresultVAREFVSSPage157TMP86FS23UG13.
6PrecautionsaboutADConverter13.
6.
1RestrictionsforADConversioninterrupt(INTADC)usageWhenanADinterruptisused,itmaynotbeprocesseddependingonprogramcomposition.
Forexample,ifanINTADCinterruptrequestisgeneratedwhileaninterruptwithprioritylowerthantheinterruptlatchIL15(INTADC)isbeingaccepted,theINTADCinterruptlatchmaybeclearedwithouttheINTADCinterruptbeingprocessed.
ThecompletionofADconversioncanbedetectedbythefollowingmethods:(1)MethodnotusingtheADconversionendinterruptWhetherornotADconversioniscompletedcanbedetectedbymonitoringtheADconversionendflag(EOCF)bysoftware.
ThiscanbedonebypollingEOCFormonitoringEOCFatregularintervalsafterstartofADconversion.
(2)MethodfordetectingADconversionendwhilealower-priorityinterruptisbeingprocessedWhileaninterruptwithprioritylowerthanINTADCisbeingprocessed,checktheADconversionendflag(EOCF)andinterruptlatchIL15.
IfIL15=0andEOCF=1,calltheADconversionendinterruptprocessingroutinewithconsiderationgiventoPUSH/POPoperations.
Atthistime,ifaninterruptrequestwithpriorityhigherthanINTADChasbeenset,theADconversionendinterruptprocessingroutinewillbeexecutedfirstagainstthespecifiedpriority.
Ifnecessary,werecommendthattheADconversionendinterruptprocessingrou-tinebecalledaftercheckingwhetherornotaninterruptrequestwithpriorityhigherthanINTADChasbeenset.
13.
6.
2AnaloginputpinvoltagerangeMakesuretheanaloginputpins(AIN0toAIN7)areusedatvoltageswithinVAREFtoVSS.
Ifanyvoltageoutsidethisrangeisappliedtooneoftheanaloginputpins,theconvertedvalueonthatpinbecomesuncertain.
Theotheranaloginputpinsalsoareaffectedbythat.
13.
6.
3AnaloginputsharedpinsTheanaloginputpins(AIN0toAIN7)aresharedwithinput/outputports.
WhenusinganyoftheanaloginputstoexecuteADconversion,donotexecuteinput/outputinstructionsforallotherports.
ThisisnecessarytopreventtheaccuracyofADconversionfromdegrading.
Notonlytheseanaloginputsharedpins,someotherpinsmayalsobeaffectedbynoisearisingfrominput/outputtoandfromadjacentpins.
13.
6.
4NoiseCountermeasureTheinternalequivalentcircuitoftheanaloginputpinsisshowninFigure13-5.
Thehighertheoutputimpedanceoftheanaloginputsource,moreeasilytheyaresusceptibletonoise.
Therefore,makesuretheout-putimpedanceofthesignalsourceinyourdesignis5korless.
Toshibaalsorecommendsattachingacapac-itorexternaltothechip.
Figure13-5AnalogInputEquivalentCircuitandExampleofInputPinProcessingDAconverterAINiAnalogcomparatorInternalresistancePermissiblesignalsourceimpedanceInternalcapacitance5k(typ)C=12pF(typ.
)5k(max)Note)i=7to0Page15813.
10-bitADConverter(ADC)13.
6PrecautionsaboutADConverterTMP86FS23UGPage159TMP86FS23UG14.
Key-onWakeup(KWU)IntheTMP86FS23UG,theSTOPmodeisreleasedbynotonlyP20(INT5/STOP)pinbutalsofour(STOP2toSTOP5)pins.
WhentheSTOPmodeisreleasedbySTOP2toSTOP5pins,theSTOPpinneedstobeused.
Indetails,refertothefollowingsection"14.
2Control".
14.
1ConfigurationFigure14-1Key-onWakeupCircuit14.
2ControlSTOP2toSTOP5pinscancontrolledbyKey-onWakeupControlRegister(STOPCR).
Itcanbeconfiguredasenable/disablein1-bitunit.
WhenthosepinsareusedforSTOPmoderelease,configurecorrespondingI/OpinstoinputmodebyI/Oportregisterbeforehand.
14.
3FunctionStopmodecanbeenteredbysettinguptheSystemControlRegister(SYSCR1),andcanbeexitedbydetectingthe"L"levelonSTOP2toSTOP5pins,whichareenabledbySTOPCR,forreleasingSTOPmode(Note1).
Key-onWakeupControlRegisterSTOPCR76543210(0F9AH)STOP5STOP4STOP3STOP2(Initialvalue:0000****)STOP5STOPmodereleasedbySTOP50:Disable1:EnableWriteonlySTOP4STOPmodereleasedbySTOP40:Disable1:EnableWriteonlySTOP3STOPmodereleasedbySTOP30:Disable1:EnableWriteonlySTOP2STOPmodereleasedbySTOP20:Disable1:EnableWriteonlySTOPCRINT5STOPSTOPmodereleasesignal(1:Release)(0F9AH)STOP2STOP3STOP4STOP5STOP2STOP3STOP4STOP5Page16014.
Key-onWakeup(KWU)14.
3FunctionTMP86FS23UGAlso,eachleveloftheSTOP2toSTOP5pinscanbeconfirmedbyreadingcorrespondingI/Oportdataregister,checkallSTOP2toSTOP5pins"H"thatisenabledbySTOPCRbeforetheSTOPmodeisstartd(Note2,3).
Note1:WhentheSTOPmodereleasedbytheedgereleasemode(SYSCR1="0"),inhibitinputfromSTOP2toSTOP5pinsbyKey-onWakeupControlRegister(STOPCR)ormustbeset"H"levelintoSTOP2toSTOP5pinsthatareavailableinputduringSTOPmode.
Note2:WhentheSTOPpininputishighorSTOP2toSTOP5pinsinputwhichisenabledbySTOPCRislow,executinganinstructionwhichstartsSTOPmodewillnotplaceinSTOPmodebutinsteadwillimmediatelystartthereleasesequence(Warmup).
Note3:TheinputcircuitofKey-onWakeupinputandPortinputisseparatedAsoeachinputvoltagethresholdvalueisdiffrent.
Therefore,avaluecomesfromportinputbeforeSTOPmodestartmaybediffrentfromavaluewhichisdetectedbyKey-onWakeupinput(Figure14-2).
Note4:STOPpindoesn'thavethecontrolregistersuchasSTOPCR,sowhenSTOPmodeisreleasedbySTOP2toSTOP5pins,STOPpinalsoshouldbeusedasSTOPmodereleasefunction.
Note5:InSTOPmode,Key-onWakeuppinwhichisenabledasinputmode(forreleasingSTOPmode)byKey-onWakeupControlRegister(STOPCR)maygenaratethepenetrationcurrent,sothesaidpinmustbedisabledADconversioninput(analogvoltageinput).
Note6:WhentheSTOPmodeisreleasedbySTOP2toSTOP5pins,thelevelofSTOPpinshouldhold"L"level(Figure14-3).
Figure14-2Key-onWakeupInputandPortInputFigure14-3PriorityofSTOPpinandSTOP2toSTOP5pinsTable14-1Releaselevel(edge)ofSTOPmodePinnameReleaselevel(edge)SYSCR1="1"(Note2)SYSCR1="0"STOP"H"levelRisingedgeSTOP2"L"levelDon'tuse(Note1)STOP3"L"levelDon'tuse(Note1)STOP4"L"levelDon'tuse(Note1)STOP5"L"levelDon'tuse(Note1)PortinputExternalpinKey-onwakeupinputSTOPpina)STOPReleaseSTOPmodeSTOPmodeSTOPpin"L"b)ReleaseSTOPmodeSTOPmodeIncaseofSTOP2toSTOP5STOP2pinPage161TMP86FS23UG15.
LCDDriverTheTMP86FS23UGhasadriverandcontrolcircuittodirectlydrivetheliquidcrystaldevice(LCD).
ThepinstobeconnectedtoLCDareasfollows:1.
Segmentoutputport32pins(SEG31toSEG0)2.
Commonoutputport4pins(COM3toCOM0)Inaddition,VLCpinisprovidedfortheLCDpowersupply.
ThedevicesthatcanbedirectlydrivenisselectablefromLCDofthefollowingdrivemethods:1.
1/4Duty(1/3Bias)LCDMax128Segments(8segments*16digits)2.
1/3Duty(1/3Bias)LCDMax96Segments(8segments*12digits)3.
1/3Duty(1/2Bias)LCDMax96Segments(8segments*12digits)4.
1/2Duty(1/2Bias)LCDMax64Segments(8segments*8digits)5.
StaticLCDMax32Segments(8segments*4digits)15.
1ConfigurationFigure15-1LCDDriverCOM3COM0VLCDutycontrolfc/217,fs/29fc/214fc/216,fs/28CommondriverDBRdisplaydataareaDisplaydataselectcontrolTimingcontrolDisplaydatabufferregisterBlankingcontrolSegmentdriverfc/215toLCDCRtoDUTYSLFEDSPLRSEPowerSwitchandBias,Bleederresistance76543210SEG0SEG31Page16215.
LCDDriver15.
1ConfigurationTMP86FS23UG15.
2ControlTheLCDcontrolregister(LCDCR)controlstheLCDdriver.
EDSPspecifieswhethertoenabletheLCDdisplay.
IfEDSPisclearedto"0"forblanking,thepowerswitchfortheVLCpinisturnedoff.
So,theCOMpinandpinout-putselectedwithSEGenterGNDlevel.
Note1:Thebase-frequency(SLF)sourceclockisswitchedbetweenhighandlowfrequenciesbytheSYSCR2pro-gramming.
ThebasefrequencydoesnotdependontheTBTCRprogramming.
Note2:IfthesettingofSYSCR2ischanged,besuretoturnofftheLCD(clearEDSPto"0")toavoidtheoutputofincor-rectwaveform.
Note3:ProgrammingLRSEproperlyaccordingtotheLCDpanelused.
AstheLRSEprogrammingincreases(lengthentheperiodofenablingofthelowresistor),thedrivecapabilitybecomeshigherwhilethepowerdissipationincreases.
Reversely,astheLRSEprogrammingdecreasesshortentheperiodofenablingofthelowresistor,thedrivecapabilitybecomeslowerwhilethepowerconsumptiondecreases.
Note4:IftheIDLE0,SLEEP0,orSTOPmodeisactivatedwhenthedisplayisenabled,LCDCRisautomaticallychangedto"0"toblankthedisplay.
LCDDriverControlRegisterLCDCR(0027H)76543210EDSPLRSELDUTYSLF(Initialvalue:00000000)EDSPLCDdisplaycontrol0:Blanking1:EnablesLCDdisplay(Blankingisreleased)R/WLRSEPeriodselectionofenabling(turnon)ofthelowbleederresistor(forimplementingappropriateLCDpaneldrivecapability)NORMAL1/2,IDLE/1/2modeSLOW1/2,SLEEP1/2modeSLFSettingSLFSetting11100100010000:26/fc27/fc28/fc29/fc1/fs2/fs01:29/fc210/fc211/fc212/fc23/fs24/fs10:Alwaysenabling11:ReservedDUTYSelectionofdrivingmethods000:1/4Duty(1/3Bias)001:1/3Duty(1/3Bias)010:1/3Duty(1/2Bias)011:1/2Duty(1/2Bias)100:Static101:Reserved110:Reserved111:ReservedSLFSelectionofLCDframefre-quencyNORMAL1/2,IDLE0/1/2modeSLOW1/2,SLEEP1/2mode00:01:10:11:fc/217[Hz]fc/216fc/215fc/213fs/29[Hz]fs/28ReservedReservedPage163TMP86FS23UG15.
2.
1LCDdrivingmethodsAsforLCDdrivingmethod,5typescanbeselectedbyLCDCR.
ThedrivingmethodisinitializedintheinitialprogramaccordingtotheLCDused.
Note1:fF:FramefrequencyNote2:VLCD:LCDdrivevoltage(=VDDVLC)Figure15-2LCDDriveWaveform(COM-SEGpins)VLCDVLCD1/fF1/fFVLCDVLCDData"1"Data"0"0Data"1"VLCDData"0"0(b)1/3Duty(1/3Bias)Data"1"Data"0"1/fFVLCD0(c)1/3Duty(1/2Bias)(a)1/4Duty(1/3Bias)VLCDVLCDData"1"Data"0"1/fF0(e)StaticVLCDData"1"Data"0"1/fFVLCD0(d)1/2Duty(1/2Bias)Page16415.
LCDDriver15.
1ConfigurationTMP86FS23UG15.
2.
2FramefrequencyFramefrequency(fF)issetaccordingtodrivingmethodandbasefrequencyasshowninthefollowingTable15-1.
ThebasefrequencyisselectedbyLCDCRaccordingtothefrequencyfcandfsofthebasicclocktobeused.
Note:fc:High-frequencyclock[Hz]Note:fs:Low-frequencyclock[Hz]Table15-1SettingofLCDFrameFrequencyforhighfrequencyclock(a)AttheSYSCR2="0".
SLFBaseFrequency[Hz]FrameFrequency[Hz]1/4Duty1/3Duty1/2DutyStatic00(fc=16MHz)122163244122(fc=8MHz)61811226101(fc=8MHz)122163244122(fc=4MHz)61811226110(fc=4MHz)122163244122(fc=2MHz)61811226111(fc=2MHz)122162244122(fc=1MHz)618112261Table15-2SettingofLCDFrameFrequencyforlowfrequencyclock(b)AttheSYSCR2="1".
SLFBaseFrequency[Hz]FrameFrequency[Hz]1/4Duty1/3Duty1/2DutyStatic00(fs=32.
768kHz)64851286401(fs=32.
768kHz)1281712561281*Reservedfc217--------fc217--------43---fc217--------42---fc217--------fc217--------fc216--------fc216--------43---fc216--------42---fc216--------fc216--------fc215--------fc215--------43---fc215--------42---fc215--------fc215--------fc214--------fc214--------43---fc214--------42---fc214--------fc214--------fs29------fs29------43---fs29------42---fs29------fs29------fs28------fs28------43---fs28------42---fs28------fs28------Page165TMP86FS23UG15.
2.
3LCDdrivevoltageLCDdrivingvoltageVLCDisgivenaspotentialdifferenceVDDVLCbetweenpinsVDDandVLC.
Therefore,whentheCPUvoltageandLCDdrivevoltagearethesame,VLCpinwillbeconnectedtoVSSpin.
TheLCDlightswhenthepotentialdifferencebetweensegmentoutputandcommonoutputis±VLCD.
Other-wiseitturnsoff.
Duringreset,thepowerswitchofLCDdriverisautomaticallyturnedoff,shuttingofftheVLCvoltage.
Afterreset,iftheP*LCRregister(*;PortNo.
)foreachportissetto"1"withLCDCR="0",aGNDlevelisoutputfromthepinwhichcanbeusedassegment.
ThepowerswitchisturnedontosupplyVLCvoltagetoLCDdriverbysettingwithLCDCRto"1".
IftheIDLE0,SLEEP0,orSTOPmodeisactivated,LCDCRisautomaticallychangedto"0"toblankthedisplay.
Toturnthedisplaybackonafterreleasingfromthepreviousmode,setLCDCRto"1"again.
Note:Duringreset,theLCDcommonoutputs(COM3toCOM0)arefixed"0"level.
However,themultiplexport(input/outputportorSEGoutputisselectable)becomeshighimpedance.
Therefore,whentheresetinputislongremarkably,ghostproblemmayappearinLCDdisplay.
15.
2.
4AdjustingtheLCDpaneldrivecapabilityTheLCDpaneldrivecapabilitycanbeadjustedbyprogrammingLCDCR.
Whentheperiodofenablingofthelowbleederresistorislengthened,thedrivecapabilitybecomeshigherwhilethepowercon-sumptionincreases.
Reversely,whentheperiodofenablingofthelowbleederresistorisshortened,thedrivecapabilitybecomeslowerwhilethepowerconsumptiondecreases.
Ifthedrivecapabilityisnotenough,theLCDdisplaymightpresentaghostproblem.
So,implementtheoptimumdrivecapabilityfortheLCDpanelused.
Thefigurebelowshowsthebleederresistancetimingandequivalentcircuitfor1/4dutyand1/3bias.
Figure15-3BleederResistanceSelectionwithLCDCR(for1/4dutyand1/3bias)VDDVM1VM2VLCDFramefrequencyRLtRLtRLtRLtRLtWhenLCDCR"10B"RLtRHtRLtRHtRLtRHtRLtRHtRLtRHtWhenLCDCR="00B"or"01B"(a)ONTimingforLowBleederResistanceVM2VMVDDRLRLRLRHRHRHVLCHigh/lowresistanceswitchingsignalRH:HighresistanceRL:LowresistanceVLC(b)EquivalentCircuitforBleederResistanceRLt:PeriodduringwhichresistanceRLisselected(TimespecifiedwithLCDCR)RHt:PeriodduringwhichresistanceRHisselected(TimespecifiedwithLCDCR÷4TimespecifiedwithLCDCR)Page16615.
LCDDriver15.
3LCDDisplayOperationTMP86FS23UG15.
3LCDDisplayOperation15.
3.
1DisplaydatasettingDisplaydataisstoredtothedisplaydataarea(address0F80Hto0F8FH,16bytes)intheDBR.
ThedisplaydatastoredinthedisplaydataareaisautomaticallyreadoutandsenttotheLCDdriverbythehardware.
TheLCDdrivergeneratesthesegmentsignalandcommonsignalaccordingtothedisplaydataanddrivingmethod.
Therefore,displaypatternscanbechangedbyonlyoverwritingthecontentsofdisplaydataareabythepro-gram.
Table15-4showsthecorrespondencebetweenthedisplaydataareaandSEG/COMpins.
LCDlightwhendisplaydatais"1"andturnoffwhen"0".
AccordingtothedrivingmethodofLCD,thenumberofpixelswhichcanbedrivenbecomesdifferent,andthenumberofbitsinthedisplaydataareawhichisusedtostoredisplaydataalsobecomesdifferent.
Therefore,thebitswhicharenotusedtostoredisplaydataaswellasthedatabufferwhichcorrespondstotheaddressesnotconnectedtoLCDcanbeusedtostoregeneraluserprocessdata(seeTable15-3).
Note:–:Thisbitisnotusedfordisplaydata15.
3.
2BlankingBlankingisenabledwhenLCDCRisclearedto"0".
ToblanktheLCDdisplayandturnitoff,aGND-levelsignalisoutputtotheCOMpinandtheportwhichcanbeusedasthesegmentbysettingofP*LCRregister(*;PortNo.
).
Atthistime,thepowerswitchofVLCpinisturnedoff.
Table15-3DrivingMethodandBitforDisplayDataDrivingmethodsBit7/3Bit6/2Bit5/1Bit4/01/4DutyCOM3COM2COM1COM01/3Duty–COM2COM1COM01/2Duty––COM1COM0Static–––COM0Table15-4LCDDisplayDataArea(DBR)AddressBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit00F80HSEG1SEG00F81HSEG3SEG20F82HSEG5SEG40F83HSEG7SEG60F84HSEG9SEG80F85HSEG11SEG100F86HSEG13SEG120F87HSEG15SEG140F88HSEG17SEG160F89HSEG19SEG180F8AHSEG21SEG200F8BHSEG23SEG220F8CHSEG25SEG240F8DHSEG27SEG260F8EHSEG29SEG280F8FHSEG31SEG30COM3COM2COM1COM0COM3COM2COM1COM0Page167TMP86FS23UG15.
4ControlMethodofLCDDriver15.
4.
1InitialsettingFigure15-4showstheflowchartofinitialization.
Figure15-4InitialSettingofLCDDriver15.
4.
2StoreofdisplaydataGenerally,displaydataarepreparedasfixeddatainprogrammemory(ROM)andstoredindisplaydataareabyloadcommand.
Note:DBisabytedatadefinitioninstruction.
Example:Tooperatea1/4dutyLCDof32segments*4com-monsatframefrequencyfc/216[Hz],Theperiodofenablingofthelowbleederresistor:28/fcLD(LCDCR),00000001B;SetsLCDdrivingmethod,Theperiodofenablingoflowbleederresistorandframefrequency.
LD(P*LCR),0FFH;Setssegmentoutputcontrolregister.
(*;PortNo.
)::::;Setstheinitialvalueofdisplaydata.
LD(LCDCR),10000001B;DisplayenableExample:(1)Todisplayusing1/4dutyLCDanumericalvaluewhichcorrespondstotheLCDdatastoredindatamemoryataddress80H(whenpinsCOMandSEGareconnectedtoLCDasinFigure15-5),displaydatabecomeasshowninTable15-5.
LDA,(80H)ADDA,TABLE-$-7LDHL,0F85HLDW,(PC+A)LD(HL),WRETTABLE:DB11011111B,00000110B,11100011B,10100111B,00110110B,10110101B,11110101B,00010111B,11110111B,10110111BSetsLCDdrivingmethod(DUTY).
Setsframefrequency(SLF).
Selectsperiodofenablingoflowresistor(LRSE).
Setssegmentoutputcontrolregisters(P*LCR(*;PortNo.
))Initializationofdisplaydataarea.
Displayenable(EDSP)(Releasesfromblanking.
)Page16815.
LCDDriver15.
3LCDDisplayOperationTMP86FS23UGFigure15-5ExampleofCOM,SEGPinConnection(1/4duty)Example:(2)Table15-6showsanexampleofdisplaydatawhicharedisplayedusing1/2dutyLCDinthesamewayasTable15-5.
TheconnectionbetweenpinsCOMandSEGarethesameasshowninFigure15-6.
Figure15-6ExampleofCOM,SEGPinConnectionTable15-5ExampleofDisplayData(1/4duty)No.
DisplayDisplaydataNo.
DisplayDisplaydata011011111510110101100000110611110101211100011700000111310100111811110111400110110910110111SEG10SEG11COM0COM1COM2COM3SEG10SEG12SEG11SEG13COM0COM1Page169TMP86FS23UGNote:*:Don'tcare15.
4.
3ExampleofLCDdriveroutputFigure15-71/4Duty(1/3Bias)DriveTable15-6ExampleofDisplayData(1/2duty)NumberDisplaydataNumberDisplaydataHighorderaddressLoworderaddressHighorderaddressLoworderaddress0**01**11**01**115**11**10**01**011**00**10**00**106**11**11**01**012**10**01**01**117**01**10**00**113**10**10**01**118**11**11**01**114**11**10**00**109**11**10**01**11VLC0VLC0VLC0VLC0VLC0VLC0VLCD-VLCDVLCD00-VLCDSEG10SEG11DisplaydataareaAddress0F85HSEG10EDSPSEG11COM0COM1COM2COM3COM0-SEG10(Selected)COM2-SEG11(Nonselected)10110101COM0COM1COM2COM3Page17015.
LCDDriver15.
3LCDDisplayOperationTMP86FS23UGFigure15-81/3Duty(1/3Bias)DriveSEG12Address*:Don'tcareSEG10EDSPSEG11SEG12COM0COM1COM2COM0-SEG11(Selected)COM1-SEG12(Nonselected)SEG11SEG10COM0COM1COM2Displaydataarea0F85H0F86H*111*010*****001VLC0VLC0VLC0VLC0VLC0VLC0VLCD-VLCDVLCD00-VLCDPage171TMP86FS23UGFigure15-91/3Duty(1/2Bias)DriveSEG12Address*:Don'tcareSEG10EDSPSEG11SEG12COM0COM1COM2COM0-SEG11(Selected)COM1-SEG12(Nonselected)SEG11SEG10COM0COM1COM2Displaydataarea0F85H0F86H*111*010*****001VDDVLCVDDVLCVDDVLCVDDVLCVDDVLCVDDVLC00VLCDVLCD-VLCD-VLCDPage17215.
LCDDriver15.
3LCDDisplayOperationTMP86FS23UGFigure15-101/2Duty(1/2Bias)DriveSEG13Address*:Don'tcareSEG10EDSPSEG11SEG12SEG13COM0COM1COM0-SEG11(Selected)COM1-SEG12(Nonselected)SEG10COM0Displaydataarea0F85H0F86H**01**01**11**10VDDVLCVDDVLCVDDVLCVDDVLCVDDVLCVDDVLC0SEG11SEG12COM10VLCDVLCD-VLCD-VLCDPage173TMP86FS23UGFigure15-11StaticDriveSEG12SEG17Address0F85HSEG15SEG14SEG13SEG10SEG11SEG16COM0VDDVDDVLCVDDVLCVDDVLCD-VLCDVLCD0SEG10SEG14SEG17COM0COM0-SEG10(Selected)COM0-SEG14(Nonselected)0EDSP0F86H0F87H0F88H***0***1***1***1***1***0***0***1Displaydataarea*:Don'tcareVLCVLC-VLCDPage17415.
LCDDriver15.
3LCDDisplayOperationTMP86FS23UGPage175TMP86FS23UG16.
Real-TimeClockTheTMP86FS23UGincludearealtimecounter(RTC).
Alow-frequencyclockcanbeusedtoprovideaperiodicinterrupt(0.
0625[s],0.
125[s],0.
25[s],0.
50[s])ataprogrammedinterval,implementtheclockfunction.
TheRTCcanbeusedinthemodeinwhichthelow-frequencyoscillatorisactive(exceptfortheSLEEP0mode).
16.
1ConfigurationFigure16-1ConfigurationoftheRTC16.
2ControloftheRTCTheRTCiscontrolledbytheRTCcontrolregister(RTCCR).
Note1:ProgramtheRTCCRduringlow-frequencyoscillation(whenSYSCR2="1").
Forselectinganinterruptgenera-tionperiod,programtheRTCSELwhenthetimerisinactive(RTCRUN="0").
Duringthetimeroperation,donotchangetheRTCSELprogrammingatthesamemomentthetimerstops.
Note2:Thetimerautomaticallystops,andthisregisterisinitialized(thetimer'sbinarycounterisalsoinitialized)ifoneofthefol-lowingoperationsisperformedwhilethetimerisactive:1.
Stoppingthelow-frequencyoscillation(withSYSCR2="0")2.
WhentheTMP86FS23UGareputinSTOPorSLEEP0modeTherefore,beforeactivatingthetimerafterreleasingfromSTOPorSLEEP0mode,reprogramtheregistersagain.
Note3:IfareadinstructionforRTCCRisexecuted,undefinedvalueissettobits7to3.
Note4:Ifbreakprocessingisperformedonthedebuggerforthedevelopmenttoolduringthetimeroperation,thetimerstopscounting(contentsoftheRTCCRisn'taltered).
Whenthebreakiscancelled,processingisrestartedfromthepointatwhichitwassuspended.
RTCControlRegisterRTCCR(0017H)76543210RTCSELRTCRUN(Initialvalue:*****000)RTCSELInterruptgenerationperiod(fs=32.
768kHz)00:0.
50[s]01:0.
25[s]10:0.
125[s]11:0.
0625[s]R/WRTCRUNRTCcontrol0:Stopsandclearsthebinarycounter.
1:StartscountingSelectorRTCCRRTCSELInterruptrequestINTRTCBinarycounterRTCRUN214/fs213/fs212/fs211/fsfs(32.
768kHz)Page17616.
Real-TimeClock16.
3FunctionTMP86FS23UG16.
3FunctionTheRTCcountsupontheinternallow-frequencyclock.
WhenRTCCRissetto"1",thebinarycounterstartscountingup.
EachtimetheendoftheperiodspecifiedwithRTCCRisdetected,anINTRTCinterruptisgenerated,andthebinarycounteriscleared.
Thetimercontinuescountingupevenafterthebinarycounteriscleared.
Page177TMP86FS23UG17.
Multiply-Accumulate(MAC)UnitTheTMP86FS23UGincludesamultiply-accumulate(MAC)unit.
TheMACunitiscapableofexecuting16-bit*16-bitmultiplicationsand16-bit*16-bit+32-bitmultiply-accumu-lateoperations.
TheMACunitsupportsonlyintegerarithmetic,notfixed-pointorfloating-pointarithmetic.
Bothsignedandunsignedoperationscanbeperformed.
TheMACunitcanonlybeusedinNORMAL1orNORMAL2mode.
AlltheregistersoftheMACunitareinitial-izeduponenteringamodeotherthanNORMALmode.
Withdevelopmenttools,ifbreakmodeisenteredwhiletheMACunitiscalculating,thecalculationiscontinuedbutitsresultisunpredictable.
Inthiscase,thecalculationmustbere-executedafterbreakmodeisexited.
Donotwritetothemultiplicandregisterinbreakmode.
Whenthecalculationiscompleted,itispossibletoenterbreakmodeandreadthecalculationresultinbreakmode.
17.
1ConfigurationFigure17-1MACUnit17.
2RegistersTheMACunitconsistsofthefollowingregisters:17.
2.
1CommandRegisterThecommandregisterisusedtoenableanddisabletheMACunit,specifythearithmeticmode,andcleartheresultregister.
Table17-1RegistersintheMACUnitRegisterAddressNumberofBitsCommandregister(MACCR)0FA4H8bitsStatusregister(MACSR)0FA5H8bitsMultiplierdataregister(MPLDRH,MPLDRL)0FA7H,0FA6H16bitsMultiplicanddataregister(MPCDRH,MPCDRL)0FA9H,0FA8H16bitsResultregister(RCALDR4toRCALDR1)0FAAHto0FADH32bitsAddendregister(MADDR4toMADDR1)0FAAHto0FADH32bitsControlcircuitStatusregisterCommandregisterArithmeticunitTemporaryregister2Temporaryregister3ResultregisterMultiplierregisterMultiplicandregisterTemporaryregister1Page17817.
Multiply-Accumulate(MAC)Unit17.
3ControlTMP86FS23UG17.
2.
2StatusRegisterThestatusregistercontainsflagstoindicatetheoperationstatusoftheMACunitandthecalculationresult.
17.
2.
3MultiplierdataRegisterThedatawrittentothisregisteriscalculatedasamultiplier.
17.
2.
4MultiplicanddataRegisterThedatawrittentothisregisteriscalculatedasamultiplicand.
17.
2.
5ResultRegisterThecalculationresultisstoredinthisregister.
17.
2.
6AddendRegisterThedatawrittentothisregisteriscalculatedasanaddendinamultiply-accumulateoperation.
Anaddendmustbewrittentothisregisterwhilecalculationisnotbeingperformed(CALC="0").
17.
3ControlNote1:SettingRCLRto"1"causestheresult,addend,andstatusregisterstobeinitialized.
Themultiplier,multiplicand,andcom-mandregistersremainthesameasbefore.
(RCLRisautomaticallyclearedto"0"onemachinecycleafteritissetto"1".
)Note2:WritingtoCMOD(includinganoverwrite)makesnochangestothestatus,multiplier,multiplicand,result,andaddendreg-isters.
Note3:Beforechangingthearithmeticmode,besuretocheckthatcalculationisnotbeingperformed(CALC="0").
Note4:ClearingtheresultregisterwithRCLRispossibleonlywhencalculationisnotbeingperformed(CALC="0").
(RCLRcan-notbesetto"1"duringcalculation.
)Note5:Bits6to4arealwaysreadas"1".
("0"cannotbewritten.
)CommandRegisterMACCR(0FA4H)76543210RCLR"1""1""1"CMODEMAC(Initialvalue:01110000)RCLRResultregisterclear0:-(Keepsthevalueoftheresultregister.
)1:Clearstheresultregister.
(Thisbitisautomaticallyclearedto"0"onemachinecycleafteritissetto"1".
)R/WCMODArithmeticmode000:Unsignedmultiply(16bits*16bits)001:Unsignedmultiply-accumulate(16bits*16bits+32bits)010:Signedmultiply(16bits*16bits)011:Signedmultiply-accumulate(16bits*16bits+32bits)1**:ReservedEMACMACunitcontrol0:DisablestheMACunit.
1:EnablestheMACunit.
StatusRegisterMACSR(0FA5H)76543210"1""1""1"CARFZERFSIGNOVRFCALC(Initialvalue:11100000)Page179TMP86FS23UGNote1:Thestatusregisterisinitializedwhentheresultregisteriscleared(RCLR="1").
Note2:CARF,ZERF,SIGN,andOVRFareprogrammedattheendofcalculation.
Theyarenotaffectedbyareadfromthestatusregister.
Note3:ZERFandSIGNarenotaffectedbyawritetotheaddendregister.
Note4:Inmultiplymode,OVRFandCARFarealwaysreadas"0".
Note5:Bit7to5arealwaysreadas"1".
Note:Insignedarithmeticmode,bit15istreatedasthesignbit.
Note1:Insignedarithmeticmode,bit15istreatedasthesignbit.
Note2:Calculationcanonlybestartedbywritingtoboththelowerbyte(MPCDRL)andupperbyte(MPCDRH)ofthemul-tiplicandregisterinthisorder.
Note3:Themultiplicandregistercanonlybeprogrammedwhendataiswrittenintheorderoflowerbyteandupperbyte.
Ifdataisonlywrittentotheupperbyte,thewrittendatacannotbereadout.
(Ifdataisonlywrittentothelowerbyte,thewrittendatacanbereadout.
)Note:Insignedarithmeticmode,bit31containsthesignofthecalculationresult.
CARFCarryflag0:Nocarryoccurredinmultiply-accumulateoperation.
1:Carryoccurredinmultiply-accumulateoperation.
ReadonlyZERFZeroflag0:Calculationresulstisotherthan"00000000H".
1:Calculationresultis"00000000H".
SIGNSignflag0:Resultregistercontentsarepositiveor"00000000H".
1:Resultregistercontentsarenegative.
OVRFOverflowflag0:Overflowoccurred.
1:Nooverflowoccurred.
CALCOperationstatusflag0:Calculationnotinprogress1:CalculationinprogressMultiplierdataRegisterMPLDRH,MPLDRL(0FA7H,0FA6H)1514131211109876543210MPLDRH(0FA7H)MPLDRL(0FA6H)(Initialvalue:0000000000000000)R/WMultiplicanddataRegisterMPCDRH,MPCDRL(0FA9H,0FA8H)1514131211109876543210MPCDRH(0FA9H)MPCDRL(0FA8H)(Initialvalue:0000000000000000)R/WResultRegisterRCALDR4,RCALDR3(0FADH,0FACH)31302928272625242322212019181716RCALDR4(0FADH)RCALDR3(0FACH)(Initialvalue:0000000000000000)ReadonlyRCALDR2,RCALDR1(0FABH,0FAAH)1514131211109876543210RCALDR2(0FABH)RCALDR1(0FAAH)(Initialvalue:0000000000000000)ReadonlyAddendRegisterMADDR4,MADDR3(0FADH,0FACH)31302928272625242322212019181716MADDR4(0FADH)MADDR3(0FACH)(Initialvalue:0000000000000000)WriteonlyMADDR2,MADDR1(0FABH,0FAAH)1514131211109876543210MADDR2(0FABH)MADDR1(0FAAH)(Initialvalue:0000000000000000)WriteonlyPage18017.
Multiply-Accumulate(MAC)Unit17.
4RegisterDescriptionTMP86FS23UGNote1:Insignedarithmeticmode,bit31istreatedasthesignbit.
Note2:Writingtotheaddendregisterchangesthecontentsoftheresultregister.
Thus,readfromtheresultregisterbeforewritingtotheaddendregister.
17.
4RegisterDescription17.
4.
1EMACSettingMACCRto"1"enablestheMACunit.
Onceenabled,theMACunitremainsenableduntilitisdisabled.
17.
4.
2CMODTheMACCRisusedtospecifythearithmeticmode.
Calculationisstartedautomaticallywhendataiswrittentoboththelowerbyte(MPCDRL)andupperbyte(MPCDRH)ofthemultiplicandregisterinthisorder.
Thus,themultiplierregister(MPLDRH,MPLDRL)mustbesetbeforethemultiplicandregister.
Whencalculationiscompleted,theresultisstoredintheresultregister(RCALDR4toRCALDR1).
ThearithmeticmodeisvaliduntiltheCMODfieldischanged.
NotethatiftheoperationmodeischangedtoIDLE0/1/2,SLOW1/2,orSTOPmode,CMODisinitialized.
Duringcalculation,thenextdatacanbewrittentothemultiplierandmultiplicandregistersonlyonce.
Donotwritetotheseregistersmorethanonce.
WhetherornotcalculationisinprogresscanbecheckedbyreadingtheMACSRflag.
Note1:Beforechangingthearithmeticmode,ensurethatcalculationisnotbeingperformed(CALC="0").
Note2:WritingtotheCMODfield(includinganoverwrite)makesnochangestothestatus,multiplier,multiplicand,result,andaddendregisters.
Thus,toclearthestatus,result,andaddendregistersafterachangeofthearithmeticmode,settheRCLRbitto"1".
17.
4.
3RCLRWhencalculationisnotbeingperformed(CALC="0"),settingMACCRto"1"causestheresult,addend,andstatusregisterstobeinitilized.
(Themultiplierandmultiplicandregistersremainthesameasbefore.
)RCLRisautomaticallyclearedto"0"onemachinecycleafteritissetto"1"Note:Whencalculationisinprogress(CALC="1"),RCLRcannotbesetto"1".
(Theinstructiontosetitto"1"isinvalid.
)AsshowninTable17-2,thestateofeachregisterchangeswhen:theMACunitisdisabled(EMAC="0");theresultregisteriscleared(RCLR="1");ortheoperationmodeischanged.
Note1:Themultiplier,multiplicand,andaddendregisterscanbewrittentoonlywhentheMACunitisenabled(EMAC="1").
Note2:Whenwritingtothemultiplicandregister,besuretowritetothelowerbyte(MPCDRL)firstandthentotheupperbyte(MPCDRH).
Note3:RCLRcanbewrittentoonlywhencalculationisnotbeingperformed(CALC="0").
Table17-2EffectsoftheEMACandRCLRBitsontheMACRegistersRegisterEMAC="0"(Disable)RCLR="1"(registerclear)IDLE0/1/2,SLOW1/2,orSTOPModeCommandregister(MACCR)BitsotherthanEMACremainthesameasbeforeBitsotherthanRCLRremainthesameasbefore.
RCLRisclearedto"0"afteronemachinecycle.
InitializedStatusregister(MACSR)InitializedInitializedInitializedMultiplierdataregister(MPLDRH,MPLDRL)InitializedRemainsthesameasbeforeInitializedMultiplicanddataregister(MPCDRH,MPCDRL)InitializedRemainsthesameasbeforeInitializedResultregister(RCALDR4toRCALDR1)InitializedInitializedInitializedAddendregister(MADDR4toMADDR1)InitializedInitializedInitializedPage181TMP86FS23UGNote4:WhentheMACunitisenabled(EMAC="1"),iftheoperationmodeischangedtoIDLE0/1/2,SLOW1/2,orSTOPmode,thecommandregister(MACCR)isinitializedanditscontentsarediscarded.
Thus,programtheMACCRagainaftereachoftheseoperationmodesisexited.
17.
5ArithmeticModesThefollowingfourarithmeticmodesareavailable:1.
Unsignedmultiply(16bits*16bits)2.
Signedmultiply(16bits*16bits)3.
Unsignedmultiply-accumulate(16bits*16bits+32bits)4.
Signedmultiply-accumulate(16bits*16bits+32bits)17.
5.
1UnsignedMultiplyModeSettingtheMACCRfieldinthecommandregisterto"000B"placestheMACunitinunsignedmultiplymode.
Inthismode,thevaluesofthemultiplierandmultiplicandregistersareeachtreatedas16-bitdataforcalculation.
Calculationisstartedautomaticallybywritingamultipliertothemultiplierregister(MPLDRH,MPLDRL)andthenwritingamultiplicandtothelowerbyte(MPCDRL)andupperbyte(MPCDRH)ofthemultiplicandregisterinthisorder.
Thecalculationresultisstoredas32-bitdataintheresultregister(RCALDR4toRCALDR1).
(Thepreviouscalculationresultiscleared.
)17.
5.
2SignedMultiplyModeSettingtheMACCRfieldinthecommandregisterto"010B"placestheMACunitinsignedmul-tiplymode.
Inthismode,bit15inthemultiplierandmultiplicandregistersiseachtreatedasthesignbit.
Calculationisstartedautomaticallybywritingamultipliertothemultiplierregister(MPLDRH,MPLDRL)andthenwritingamultiplicandtothelowerbyte(MPCDRL)andupperbyte(MPCDRH)ofthemultiplicandregisterinthisorder.
Thecalculationresultisstoredas32-bitdataintheresultregister(RCALDR4toRCALDR1).
(Bit31containsthesign,andthepreviouscalculationresultiscleared.
)Thesignofthecalcula-tionresultvariesdependingonthesignsofthemultiplierandmultiplicand,asshowninTable17-3.
17.
5.
3UnsignedMultiply-AccumulateModeSettingtheMACCRfieldinthecommandregisterto"001B"placestheMACunitinunsignedmultiply-accumulatemode.
Inthismode,thevaluesofthemultiplierandmultiplicandregistersareeachtreatedas16-bitdataforcalculation.
Calculationisstartedautomaticallybywritingamultipliertothemultiplierregister(MPLDRH,MPLDRL)andthenwritingamultiplicandtothelowerbyte(MPCDRH)andupperbyte(MPCDRH)ofthemultiplicandregisterinthisorder.
First,themultiplierandmultiplicandaremultiplied.
Then,thecontentsoftheaddendreg-isterareaddedtotheproduct.
Thesumisstoredas32-bitdataintheresultregister.
Inunsignedmultiply-accumulatemode,anyaddendcanbewrittentotheaddendregisterwhencalculationisnotbeingperformed.
If,forexample,A*BisexecutedafterarbitrarydataCiswrittentotheaddendregister,theresultofA*B+Cisstoredintheresultregister(RCALDR4toRCALDR1).
SettingtheRCLRbitto"1"Table17-3SignsUsedinSingedMultiplyModeSignofMultiplierSignofMultiplicandSignofCalculationResult000011101110Page18217.
Multiply-Accumulate(MAC)Unit17.
6StatusFlagsTMP86FS23UGcausestheresultandaddendregisterstobecleared.
Aftercalculationiscompleted,thecontentsoftheresultregisterareautomaticallystoredintheaddendregister.
Thus,ifthecontentsoftheaddendregisterarenotchanged,theresultofthepreviousmultiply-accumulateoperationisusedasanaddendforthenextcalculation.
Note1:Besuretowritetotheaddendregisterwhencalculationisnotbeingperformed(CALC="0").
Note2:Writingtotheaddendregisterchangesthecontentsoftheresultregister.
Thus,readfromtheresultregisterbeforewritingtotheaddendregister.
17.
5.
4SignedMultiply-AccumulateModeSettingtheMACCRfieldinthecommandregisterto"011B"placestheMACunitinsignedmul-tiply-accumulatemode.
Inthismode,bit15inthemultiplierandmultiplicandregisteriseachtreatedasthesignbit.
Calculationisstartedautomaticallybywritingamultipliertothemultiplierregister(MPLDRH,MPLDRL)andthenwritingamultiplicandtothelowerbyte(MPCDRL)andupperbyte(MPCDRH)ofthemultiplicandregisterinthisorder.
First,themultiplicandandmultiplicandaremultiplied.
Then,thecontentsoftheaddendregisterareaddedtotheproduct.
Thesumisstoredassigned32-bitdataintheresultregister(RCALDR4toRCALDR1).
ThesignoftheresultvariesasshowninTable17-4.
Asinthecaseofunsignedmultiply-accumu-latemode,anyaddendcanbewrittentotheaddendregisterwhencalculationisnotbeingperformed.
Note:Insignedmultiply-accumulatemode,bit31intheaddendregisteristreatedasthesignbit.
17.
5.
5ValidNumericalRangesTable17-5showsthenumericalrangethatcanbehandledineacharithmeticmode.
17.
6StatusFlagsThestatusregisterMACSRcontainsthefollowingfiveflags.
OVRF,CARF,SIGN,andZERFareprogrammedwhencalculationiscompleted,andtheseflagsarenotaffectedbyareadfromthestatusregister.
1.
Operationstatusflag(CALC)2.
Overflowflag(OVRF)3.
Carryflag(CARF)4.
Signflag(SIGN)5.
Zeroflag(ZERF)Table17-4SignsUsedinSginedMultiply-AccumulateModeSignofProductSignofAddendSign(bit31)ofCalculationResultWhenOVRF="0"WhenOVRF="1"000101"1"whensum6cycles/3sRET6cycles/3sTotalprocessingtime57sPage185TMP86FS23UG18.
FlashMemoryTMP86FS23UGhas61440byteflashmemory(address:1000HtoFFFFH).
Thewriteanderaseoperationstotheflashmemoryarecontrolledinthefollowingthreetypesofmode.
-MCUmodeTheflashmemoryisaccessedbytheCPUcontrolintheMCUmode.
Thismodeisusedforsoftwarebugcorrectionandfirmwarechangeaftershipmentofthedevicesincethewriteoperationtotheflashmemoryisavailablebyretainingtheapplicationbehavior.
-SerialPROMmodeTheflashmemoryisaccessedbytheCPUcontrolintheserialPROMmode.
Useoftheserialinterface(UART)enablestheflashmemorytobecontrolledbythesmallnumberofpins.
TMP86FS23UGintheserialPROMmodesupportson-boardprogrammingwhichenablesuserstoprogramflashmemoryafterthemicrocontrollerismountedonauserboard.
-ParallelPROMmodeTheparallelPROMmodeallowstheflashmemorytobeaccessedasastand-aloneflashmemorybytheprogramwriterprovidedbythethirdparty.
High-speedaccesstotheflashmemoryisavailablebycontrol-lingaddressanddatasignalsdirectly.
Forthesupportoftheprogramwriter,pleaseaskToshibasalesrep-resentative.
IntheMCUandserialPROMmodes,theflashmemorycontrolregister(FLSCR)isusedforflashmemorycon-trol.
Thischapterdescribeshowtoaccesstheflashmemoryusingtheflashmemorycontrolregister(FLSCR)intheMCUandserialPROMmodes.
Page18618.
FlashMemory18.
1FlashMemoryControlTMP86FS23UG18.
1FlashMemoryControlTheflashmemoryiscontrolledviatheflashmemorycontrolregister(FLSCR)andflashmemorystanbycontrolresister(FLSSTB).
Note1:ThecommandsequenceoftheflashmemorycanbeexecutedonlywhenFLSMD="0011B".
Inothercases,anyattemptstoexecutethecommandsequenceareineffective.
Note2:FLSMDmustbesettoeither"1100B"or"0011B".
Note3:BANKSELiseffectiveonlyintheserialPROMmode.
IntheMCUmode,theflashmemoryisalwaysaccessedwithactualaddresses(1000-FFFFH)regardlessofBANKSEL.
Note4:Bits2through0inFLSCRarealwaysreadasdon'tcare.
Note1:WhenFSTBissetto1,donotexecutetheread/writeinstructiontotheflashmemorybecausethereisapossibilitythattheexpecteddataisnotreadortheprogramisnotoperatedcorrectly.
Ifexecutingtheread/writeinstruction,FSTBisinitial-izedto0automatically.
Note2:IfaninterruptisissuedwhenFSTBissetto1,FSTBisinitializedto0automaticallyandthenthevectorareaoftheflashmemoryisread.
Note3:IftheIDLE0/1/2,SLEEP0/1/2orSTOPmodeisactivatedwhenFSTBissetto1,FSTBisinitializedto0automatically.
IntheIDLE0/1/2,SLEEP0/1/2orSTOPmode,thestandbyfunctionoperatesregardlessofFSTBsetting.
18.
1.
1FlashMemoryCommandSequenceExecutionControl(FLSCR)Theflashmemorycanbeprotectedfrominadvertentwriteduetoprogramerrorormicrocontrollermisoper-ation.
Thiswriteprotectionfeatureisrealizedbydisablingflashmemorycommandsequenceexecutionviatheflashmemorycontrolregister(writeprotect).
Toenablecommandsequenceexecution,setFLSCRto"0011B".
Todisablecommandsequenceexecution,setFLSCRto"1100B".
Afterreset,FLSCRisinitializedto"1100B"todisablecommandsequenceexecution.
Normally,FLSCRshouldbesetto"1100B"exceptwhentheflashmemoryneedstobewrittenorerased.
18.
1.
2FlashMemoryBankSelectControl(FLSCR)IntheserialPROMmode,a2-kbyteBOOTROMismappedtoaddresses7800H-7FFFHandtheflashmem-oryismappedto2banksat8000H-FFFFH.
Flashmemoryaddresses1000H-7FFFHaremappedto9000H-FFFFHasBANK0,andflashmemoryaddresses8000H-FFFFHaremappedto8000H-FFFFHasBANK1.
FLSCRisusedtoswitchbetweenthesebanks.
Forexample,toaccesstheflashmemoryaddress7000H,setFLSCRto"0"andthenaccessF000H.
Toaccesstheflashmemoryaddress9000H,setFLSCRto"1"andthenaccess9000H.
IntheMCUmode,theflashmemoryisaccessedwithactualaddressesat1000H-FFFFH.
Inthiscase,FLSCRisineffective(i.
e.
,itsvaluehasnoeffectonotheroperations).
FlashMemoryControlRegisterFLSCR76543210(0FFFH)FLSMDBANKSEL(Initialvalue:11001***)FLSMDFlashmemorycommandsequenceexe-cutioncontrol1100:Disablecommandsequenceexecution0011:EnablecommandsequenceexecutionOthers:ReservedR/WBANKSELFlashmemorybankselectcontrol(SerialPROMmodeonly)0:SelectBANK01:SelectBANK1R/WFlashMemoryStandbyControlRegisterFLSSTB76543210(0FE9H)FSTB(Initialvalue0)FSTBFlashmemorystandbycontrol0:Disablethestandbyfunction.
1:Enablethestandbyfunction.
WriteonlyPage187TMP86FS23UG18.
1.
3FlashMemoryStandbyControl(FLSSTB)Lowpowerconsumptionisenabledbycuttingoffthesteady-statecurrentoftheflashmemory.
IntheIDLE0/1/2,SLEEP0/1/2orSTOPmode,thesteady-statecurrentoftheflashmemoryiscutoffautomatically.
WhentheprogramisexecutedintheRAMarea(withoutaccessingtheflashmemory)intheNORMAL1/2orSLOW1/2mode,thecurrentcanbecutoffbythecontroloftheregister.
Tocutoffthesteady-statecurrentoftheflashmemory,setFLSSTBto"1"bythecontrolprogramintheRAMarea.
TheproceduresforcontrollingtheFLSSTBregisterareexplainedbelow.
(Steps1and2arecontrolledbytheprogramintheflashmemory,andsteps3through8arecontrolledbythewritecontrolprogramexecutedintheRAMarea.
)1.
TransferthecontrolprogramoftheFLSSTBregistertotheRAMarea.
2.
JumptotheRAMarea.
3.
Disable(DI)theinterruptmasterenableflag(IMF="0").
4.
SetFLSSTBto"1".
5.
Executetheuserprogram.
6.
Repeatstep5untilthereturnrequesttotheflashmemoryisdetected.
7.
SetFLSSTBto"0".
8.
Jumptotheflashmemoryarea.
Note1:ThestandbyfunctionisnotoperatedbysettingFLSSTBwiththeprogramintheflashmemory.
YoumustsetFLSSTBbytheprogramintheRAMarea.
Note2:TousethestandbyfunctionbysettingFLSSTBto"1"withtheprogramintheRAMarea,FLSSTBmustbesetto"0"bytheprogramintheRAMareabeforereturningtheprogramcontroltotheflashmemory.
IftheprogramcontrolisreturnedtotheflashmemorywithFLSSTBsetto"1",theprogrammaymisoperateandrunoutofcontrol.
Table18-1FlashMemoryAccessOperatingModeFLSCRAccessAreaSpecifiedAddressMCUmodeDon'tcare1000H-FFFFHSerialPROMmode0(BANK0)1000H-7FFFH9000H-FFFFH1(BANK1)8000H-FFFFHPage18818.
FlashMemory18.
2CommandSequenceTMP86FS23UG18.
2CommandSequenceThecommandsequenceintheMCUandtheserialPROMmodesconsistsofsixcommands(JEDECcompatible),asshowninTable18-2.
Addressesspecifiedinthecommandsequencearerecognizedwiththelower12bits(excludingBA,SA,andFF7FHusedforreadprotection).
Theupper4bitsareusedtospecifytheflashmemoryarea,asshowninTable18-3.
Note1:Settheaddressanddatatobewritten.
Note2:Theareatobeerasedisspecifiedwiththeupper4bitsoftheaddress.
18.
2.
1ByteProgramThiscommandwritestheflashmemoryforeachbyteunit.
Theaddressesanddatatobewrittenarespecifiedinthe4thbuswritecycle.
Eachbytecanbeprogrammedinamaximumof40s.
Thenextcommandsequencecannotbeexecuteduntilthewriteoperationiscompleted.
Tocheckthecompletionofthewriteoperation,per-formreadoperationsrepeatedlyuntilthesamedataisreadtwicefromthesameaddressintheflashmemory.
Duringthewriteoperation,anyconsecutiveattemptstoreadfromthesameaddressisreversedbit6ofthedata(togglingbetween0and1).
Note:TorewritedatatoFlashmemoryaddressesatwhichdata(includingFFH)isalreadywritten,makesuretoerasetheexistingdataby"sectorerase"or"chiperase"beforerewritingdata.
18.
2.
2SectorErase(4-kbyteErase)Thiscommanderasestheflashmemoryinunitsof4kbytes.
Theflashmemoryareatobeerasedisspecifiedbytheupper4bitsofthe6thbuswritecycleaddress.
Forexample,intheMCUmode,toerase4kbytesfrom7000Hto7FFFH,specifyoneoftheaddressesin7000H-7FFFHasthe6thbuswritecycle.
IntheserialPROMmode,toerase4kbytesfrom7000Hto7FFFH,setFLSCRto"0"andthenspecifyoneoftheaddressesinF000H-FFFFHasthe6thbuswritecycle.
ThesectorerasecommandiseffectiveonlyintheMCUandserialPROMmodes,anditcannotbeusedintheparallelPROMmode.
Table18-2CommandSequenceCommandSequence1stBusWriteCycle2ndBusWriteCycle3rdBusWriteCycle4thBusWriteCycle5thBusWriteCycle6thBusWriteCycleAddressDataAddressDataAddressDataAddressDataAddressDataAddressData1Byteprogram555HAAHAAAH55H555HA0HBA(Note1)Data(Note1)----2SectorErase(4-kbyteErase)555HAAHAAAH55H555H80H555HAAHAAAH55HSA(Note2)30H3ChipErase(AllErase)555HAAHAAAH55H555H80H555HAAHAAAH55H555H10H4ProductIDEntry555HAAHAAAH55H555H90H5ProductIDExitXXHF0HProductIDExit555HAAHAAAH55H555HF0H6ReadProtect555HAAHAAAH55H555HA5HFF7FH00H----Table18-3AddressSpecificationintheCommandSequenceOperatingModeFLSCRSpecifiedAddressMCUmodeDon'tcare1***H-F***HSerialPROMmode0(BANK0)9***H-F***H1(BANK1)8***H-F***HPage189TMP86FS23UGAmaximumof30msisrequiredtoerase4kbytes.
Thenextcommandsequencecannotbeexecuteduntiltheeraseoperationiscompleted.
Tocheckthecompletionoftheeraseoperation,performreadoperationsrepeat-edlyfordatapollinguntilthesamedataisreadtwicefromthesameaddressintheflashmemory.
Duringtheeraseoperation,anyconsecutiveattemptstoreadfromthesameaddressisreversedbit6ofthedata(togglingbetween0and1).
18.
2.
3ChipErase(AllErase)Thiscommanderasestheentireflashmemoryinapproximately30ms.
Thenextcommandsequencecannotbeexecuteduntiltheeraseoperationiscompleted.
Tocheckthecompletionoftheeraseoperation,performreadoperationsrepeatedlyfordatapollinguntilthesamedataisreadtwicefromthesameaddressintheflashmemory.
Duringtheeraseoperation,anyconsecutiveattemptstoreadfromthesameaddressisreversedbit6ofthedata(togglingbetween0and1).
Afterthechipiserased,allbytescontainFFH.
18.
2.
4ProductIDEntryThiscommandactivatestheProductIDmode.
IntheProductIDmode,thevendorID,theflashID,andthereadprotectionstatuscanbereadfromtheflashmemory.
Note:ThevalueataddressF002H(flashsize)dependsonthesizeofflashmemoryincorporatedineachproduct.
Forexample,iftheproducthas60-kbyteflashmemory,"0EH"isreadfromaddressF002H.
18.
2.
5ProductIDExitThiscommandisusedtoexittheProductIDmode.
18.
2.
6ReadProtectThiscommandenablesthereadprotectionsettingintheflashmemory.
Whenthereadprotectionisenabled,theflashmemorycannotbereadintheparallelPROMmode.
IntheserialPROMmode,theflashwriteandRAMloadercommandscannotbeexecuted.
ToenablethereadprotectionsettingintheserialPROMmode,setFLSCRto"1"beforeexe-cutingthereadprotectcommandsequence.
Todisablethereadprotectionsetting,itisnecessarytoexecutethechiperasecommandsequence.
WhetherornotthereadprotectionisenabledcanbecheckedbyreadingFF7FHintheProductIDmode.
Fordetails,seeTable18-4.
Table18-4ValuesToBeReadintheProductIDModeAddressMeaningReadValueF000HVendorID98HF001HFlashmacroID41HF002HFlashsize0EH:60kbytes0BH:48kbytes07H:32kbytes05H:24kbytes03H:16kbytes01H:8kbytes00H:4kbytesFF7FHReadprotectionstatusFFH:ReadprotectiondisabledOtherthanFFH:ReadprotectionenabledPage19018.
FlashMemory18.
3ToggleBit(D6)TMP86FS23UGIttakesamaximumof40stosetreadprotectionintheflashmemory.
Thenextcommandsequencecannotbeexecuteduntilthisoperationiscompleted.
Tocheckthecompletionofthereadprotectoperation,performreadoperationsrepeatedlyfordatapollinguntilthesamedataisreadtwicefromthesameaddressintheflashmemory.
Duringthereadprotectoperation,anyattemptstoreadfromthesameaddressisreversedbit6ofthedata(togglingbetween0and1).
18.
3ToggleBit(D6)Afterthebyteprogram,chiperase,andreadprotectcommandsequenceisexecuted,anyconsecutiveattemptstoreadfromthesameaddressisreversedbit6(D6)ofthedata(togglingbetween0and1)untiltheoperationiscom-pleted.
Therefore,thistogglebitprovidesasoftwaremechanismtocheckthecompletionofeachoperation.
Usuallyperformreadoperationsrepeatedlyfordatapollinguntilthesamedataisreadtwicefromthesameaddressintheflashmemory.
Afterthebyteprogram,chiperase,orreadprotectcommandsequenceisexecuted,theinitialreadofthetogglebitalwaysproducesa"1".
Page191TMP86FS23UG18.
4AccesstotheFlashMemoryAreaWhenthewrite,eraseandreadprotectionsaresetintheflashmemory,readandfetchoperationscannotbeper-formedintheentireflashmemoryarea.
Therefore,toperformtheseoperationsintheentireflashmemoryarea,accesstotheflashmemoryareabythecontrolprogramintheBOOTROMorRAMarea.
(Theflashmemorypro-gramcannotwritetotheflashmemory.
)TheserialPROMorMCUmodeisusedtorunthecontrolprogramintheBOOTROMorRAMarea.
Note1:Theflashmemorycanbewrittenorreadforeachbyteunit.
Eraseoperationscanbeperformedeitherintheentireareaorinunitsof4kbytes,whereasreadoperationscanbeperformedbyanonetransferinstruction.
However,thecommandsequencemethodisadoptedforwriteanderaseoperations,requiringseveral-bytetransferinstruc-tionsforeachoperation.
Note2:TorewritedatatoFlashmemoryaddressesatwhichdata(includingFFH)isalreadywritten,makesuretoerasetheexistingdataby"sectorerase"or"chiperase"beforerewritingdata.
18.
4.
1FlashMemoryControlintheSerialPROMModeTheserialPROMmodeisusedtoaccesstotheflashmemorybythecontrolprogramprovidedintheBOOTROMarea.
Sincealmostofalloperationsrelatingtoaccesstotheflashmemorycanbecontrolledsim-plybythecommunicationdataoftheserialinterface(UART),thesefunctionsaretransparenttotheuser.
ForthedetailsoftheserialPROMmode,see"SerialPROMMode.
"ToaccesstotheflashmemorybyusingperipheralfunctionsintheserialPROMmode,runtheRAMloadercommandtoexecutethecontrolprogramintheRAMarea.
TheprocedurestoexecutethecontrolprogramintheRAMareaisshownin"18.
4.
1.
1HowtowritetotheflashmemorybyexecutingthecontrolprogramintheRAMarea(intheRAMloadermodewithintheserialPROMmode)".
18.
4.
1.
1HowtowritetotheflashmemorybyexecutingthecontrolprogramintheRAMarea(intheRAMloadermodewithintheserialPROMmode)(Steps1and2arecontrolledbytheBOOTROM,andsteps3through10arecontrolledbythecontrolprogramexecutedintheRAMarea.
)1.
TransferthewritecontrolprogramtotheRAMareaintheRAMloadermode.
2.
JumptotheRAMarea.
3.
Disable(DI)theinterruptmasterenableflag(IMF←"0").
4.
SetFLSCRto"0011B"(toenablecommandsequenceexecution).
5.
Executetheerasecommandsequence.
6.
Readthesameflashmemoryaddresstwice.
(Repeatstep6untilthesamedataisreadbytwoconsecutivereadsoperations.
)7.
SpecifythebanktobewritteninFLSCR.
8.
Executethewritecommandsequence.
9.
Readthesameflashmemoryaddresstwice.
(Repeatstep9untilthesamedataisreadbytwoconsecutivereadsoperations.
)10.
SetFLSCRto"1100B"(todisablecommandsequenceexecution).
Note1:BeforewritingtotheflashmemoryintheRAMarea,disableinterruptsbysettingtheinterruptmasterenableflag(IMF)to"0".
UsuallydisableinterruptsbyexecutingtheDIinstructionattheheadofthewritecontrolprogramintheRAMarea.
Note2:SincethewatchdogtimerisdisabledbytheBOOTROMintheRAMloadermode,itisnotrequiredtodisablethewatchdogtimerbytheRAMloaderprogram.
Page19218.
FlashMemory18.
4AccesstotheFlashMemoryAreaTMP86FS23UGExample:Afterchiperasure,theprogramintheRAMareawritesdata3FHtoaddressF000H.
DI:Disableinterrupts(IMF←"0")LD(FLSCR),0011_1000B:Enablecommandsequenceexecution.
LDIX,0F555HLDIY,0FAAAHLDHL,0F000H;####FlashMemoryChiperaseProcess####LD(IX),0AAH:1stbuswritecycleLD(IY),55H:2ndbuswritecycleLD(IX),80H:3rdbuswritecycleLD(IX),0AAH:4thbuswritecycleLD(IY),55H:5thbuswritecycleLD(IX),10H:6thbuswritecyclesLOOP1:LDW,(IX)CMPW,(IX)JRNZ,sLOOP1:Loopuntilthesamevalueisread.
SET(FLSCR).
3:SetBANK1.
;####FlashMemoryWriteProcess####LD(IX),0AAH:1stbuswritecycleLD(IY),55H:2ndbuswritecycleLD(IX),0A0H:3rdbuswritecycleLD(HL),3FH:4thbuswritecycle,(F000H)=3FHsLOOP2:LDW,(HL)CMPW,(HL)JRNZ,sLOOP2:Loopuntilthesamevalueisread.
LD(FLSCR),1100_1000B:Disablecommandsequenceexecution.
sLOOP3:JPsLOOP3Page193TMP86FS23UG18.
4.
2FlashMemoryControlintheMCUmodeIntheMCUmode,writeoperationsareperformedbyexecutingthecontrolprogramintheRAMarea.
Beforeexecutionofthecontrolprogram,copythecontrolprogramintotheRAMareaorobtainitfromtheexternalusingthecommunicationpin.
TheprocedurestoexecutethecontrolprogramintheRAMareaintheMCUmodearedescribedbelow.
18.
4.
2.
1HowtowritetotheflashmemorybyexecutingauserwritecontrolprogramintheRAMarea(intheMCUmode)(Steps1and2arecontrolledbytheprogramintheflashmemory,andsteps3through11arecontrolledbythecontrolprogramintheRAMarea.
)1.
TransferthewritecontrolprogramtotheRAMarea.
2.
JumptotheRAMarea.
3.
Disable(DI)theinterruptmasterenableflag(IMF←"0").
4.
Disablethewatchdogtimer,ifitisused.
5.
SetFLSCRto"0011B"(toenablecommandsequenceexecution).
6.
Executetheerasecommandsequence.
7.
Readthesameflashmemoryaddresstwice.
(Repeatstep7untilthesamedataisreadbytwoconsecutivereadoperations.
)8.
Executethewritecommandsequence.
(Itisnotrequiredtospecifythebanktobewritten.
)9.
Readthesameflashmemoryaddresstwice.
(Repeatstep9untilthesamedataisreadbytwoconsecutivereadoperations.
)10.
SetFLSCRto"1100B"(todisablecommandsequenceexecution).
11.
Jumptotheflashmemoryarea.
Note1:BeforewritingtotheflashmemoryintheRAMarea,disableinterruptsbysettingtheinterruptmasterenableflag(IMF)to"0".
UsuallydisableinterruptsbyexecutingtheDIinstructionattheheadofthewritecontrolprogramintheRAMarea.
Note2:Whenwritingtotheflashmemory,donotintentionallyusenon-maskableinterrupts(thewatchdogtimermustbedisabledifitisused).
Ifanon-maskableinterruptoccurswhiletheflashmemoryisbeingwritten,unexpecteddataisreadfromtheflashmemory(interruptvector),resultinginmalfunc-tionofthemicrocontroller.
Page19418.
FlashMemory18.
4AccesstotheFlashMemoryAreaTMP86FS23UGExample:Aftersectorerasure(E000H-EFFFH),theprogramintheRAMareawritesdata3FHtoaddressE000H.
DI:Disableinterrupts(IMF←"0")LD(WDTCR2),4EH:CleartheWDTbinarycounter.
LDW(WDTCR1),0B101H:DisabletheWDT.
LD(FLSCR),0011_1000B:Enablecommandsequenceexecution.
LDIX,0F555HLDIY,0FAAAHLDHL,0E000H;####FlashMemorySectorEraseProcess####LD(IX),0AAH:1stbuswritecycleLD(IY),55H:2ndbuswritecycleLD(IX),80H:3rdbuswritecycleLD(IX),0AAH:4thbuswritecycleLD(IY),55H:5thbuswritecycleLD(HL),30H:6thbuswritecyclesLOOP1:LDW,(IX)CMPW,(IX)JRNZ,sLOOP1:Loopuntilthesamevalueisread.
;####FlashMemoryWriteProcess####LD(IX),0AAH:1stbuswritecycleLD(IY),55H:2ndbuswritecycleLD(IX),0A0H:3rdbuswritecycleLD(HL),3FH:4thbuswritecycle,(1000H)=3FHsLOOP2:LDW,(HL)CMPW,(HL)JRNZ,sLOOP2:Loopuntilthesamevalueisread.
LD(FLSCR),1100_1000B:Disablecommandsequenceexecution.
JPXXXXH:Jumptotheflashmemoryarea.
Example:ThiswritecontrolprogramreadsdatafromaddressF000Handstoresitto98HintheRAMarea.
LDA,(0F000H):ReaddatafromaddressF000H.
LD(98H),A:Storedatatoaddress98H.
Page195TMP86FS23UG19.
SerialPROMMode19.
1OutlineTheTMP86FS23UGhasa2048byteBOOTROM(MaskROM)forprogrammingtoflashmemory.
TheBOOTROMisavailableintheserialPROMmode,andcontrolledbyTEST,BOOTandRESETpins.
Communica-tionisperformedviaUART.
TheserialPROMmodehasseventypesofoperatingmode:Flashmemorywriting,RAMloader,FlashmemorySUMoutput,ProductIDcodeoutput,Flashmemorystatusoutput,Flashmemoryeras-ingandFlashmemoryreadprotectionsetting.
MemoryaddressmappingintheserialPROMmodediffersfromthatintheMCUmode.
Figure19-1showsmemoryaddressmappingintheserialPROMmode.
Note:Thoughincludedinaboveoperatingrange,someofhighfrequenciesarenotsupportedintheserialPROMmode.
Fordetails,referto"Table19-5".
19.
2MemoryMappingTheFigure19-1showsmemorymappingintheSerialPROMmodeandMCUmode.
IntheserialPROMmode,theBOOTROM(MaskROM)ismappedinaddressesfrom7800Hto7FFFH.
Theflashmemoryisdividedintotwobanksformapping.
Therefore,whentheRAMloadermode(60H)isused,itisrequiredtospecifytheflashmemoryaddressaccordingtoFigure19-1(Fordetailofbanksandcontrolregister,refertothechapterof"FlashMemoryControlRegister".
)Figure19-1MemoryAddressMapsTable19-1OperatingRangeintheSerialPROMModeParameterMinMaxUnitPowersupply4.
55.
5VHighfrequency(Note)216MHzTousetheFlashmemorywritingcommand(30H),specifytheflashmemoryaddressesfrom1000HtoFFFFH,thatisthesameaddressesintheMCUmode,becausetheBOOTROMchangestheflashmemoryaddress.
003FH0000H64bytes2048bytes0040H0FFFH7800H7FFFH8000H8000H7FFFHFFFFHFFFFHSFRRAMDBRSFRRAMDBRBOOTROMFlashmemorySerialPROMmodeMCUmode9000H28672bytes(BANK0)32768bytes(BANK1)61440bytes003FH0000H64bytes0040H0FFFH1000HFlashmemory2048bytes128bytes128bytes083FH0F80H0F80H2048bytes083FHPage19619.
SerialPROMMode19.
3SerialPROMModeSettingTMP86FS23UG19.
3SerialPROMModeSetting19.
3.
1SerialPROMModeControlPinsToexecuteon-boardprogramming,activatetheserialPROMmode.
Table19-2showspinsettingtoactivatetheserialPROMmode.
Note:TheBOOTpinissharedwiththeUARTcommunicationpin(RXDpin)intheserialPROMmode.
ThispinisusedasUARTcommunicationpinafteractivatingserialPROMmode19.
3.
2PinFunctionIntheserialPROMmode,TXD(P11)andRXD(P10)areusedasaserialinterfacepin.
Note1:Duringon-boardprogrammingwithotherpartsmountedonauserboard,becarefulnotoaffectthesecommunicationcontrolpins.
Note2:OperatingrangeofhighfrequencyinserialPROMmodeis2MHzto16MHz.
Table19-2SerialPROMModeSettingPinSettingTESTpinHighBOOT/RXDpinHighRESETpinTable19-3PinFunctionintheSerialPROMModePinName(SerialPROMMode)Input/OutputFunctionPinName(MCUMode)TXDOutputSerialdataoutput(Note1)P11BOOT/RXDInput/InputSerialPROMmodecontrol/SerialdatainputP10RESETInputSerialPROMmodecontrolRESETTESTInputFixedtohighTESTVDD,AVDDPowersupply4.
5to5.
5VVSSPowersupply0VVAREFPowersupplyLeaveopenorapplyinputreferencevoltage.
I/O(Output)portsexceptP11,P10I/O(Output)Theseportsareinthehigh-impedancestateintheserialPROMmode.
Theinputlevelisfixedtotheportinputswithahardwarefeaturetopreventoverlapcurrent.
(Theportinputsareinvalid.
)Tomaketheportinputsvalid,setthepinoftheSPCRregisterto"1"bytheRAMloadercontrolpro-gram.
COM3toCOM0OutputLowoutputintheserialPROMmodeVLCPowersupplyConnecttoGNDorapplyLCDdrivevoltage.
XINInputSelf-oscillatewithanoscillator.
(Note2)XOUTOutputPage197TMP86FS23UGFigure19-2SerialPROMModePinSettingNote1:Forconnectionofotherpins,referto"Table19-3PinFunctionintheSerialPROMMode".
19.
3.
3ExampleConnectionforOn-BoardWritingFigure19-3showsanexampleconnectiontoperformon-boardwring.
Figure19-3ExampleConnectionforOn-BoardWritingNote1:WhenotherpartsontheapplicationboardeffecttheUARTcommunicationintheserialPROMmode,iso-latethesepinsbyajumperorswitch.
Note2:WhentheresetcontrolcircuitontheapplicationboardeffectsactivationoftheserialPROMmode,isolatethepinbyajumperorswitch.
Note3:Forconnectionofotherpins,referto"Table19-3PinFunctionintheSerialPROMMode".
VDD(4.
5Vto5.
5V)SerialPROMmodeMCUmodeVDDTESTRESETExternalcontrolpull-upXINXOUTVSSGNDBOOT/RXD(P10)TXD(P11)TMP86FS23UGVDD(4.
5Vto5.
5V)SerialPROMmodeMCUmodeVDDTESTRESETPCcontrolPull-upLevelconverterXINXOUTVSSGNDExternalcontrolboardApplicationboardRCpower-onresetcircuitRESETcontrolOtherparts(Note1)(Note2)BOOT/RXD(P10)TXD(P11)Page19819.
SerialPROMMode19.
3SerialPROMModeSettingTMP86FS23UG19.
3.
4ActivatingtheSerialPROMModeThefollowingisaproceduretoactivatetheserialPROMmode.
"Figure19-4SerialPROMModeTiming"showsaserialPROMmodetiming.
1.
SupplypowertotheVDDpin.
2.
SettheRESETpintolow.
3.
SettheTESTpinandBOOT/RXDpinstohigh.
4.
Waituntilthepowersupplyandclockoscillationstabilize.
5.
SettheRESETpintohigh.
6.
Inputthematchingdata(5AH)totheBOOT/RXDpinaftersetupsequence.
Fordetailsofthesetuptiming,referto"19.
16UARTTiming".
Figure19-4SerialPROMModeTimingVDDTEST(Input)RESET(Input)PROGRAMSetuptimeforserialPROMmode(Rxsup)HighlevelsettingMatchingdatadon'tcareResetmodeSerialPROMmodeinputBOOT/RXD(Input)Page199TMP86FS23UG19.
4InterfaceSpecificationsforUARTThefollowingshowstheUARTcommunicationformatusedintheserialPROMmode.
Toperformon-boardprogramming,thecommunicationformatofthewritecontrollermustalsobesetinthesamemanner.
Thedefaultbaudrateis9600bpsregardlessofoperatingfrequencyofthemicrocontroller.
ThebaudratecanbemodifiedbytransmittingthebaudratemodificationdatashowninTable1-4toTMP86FS23UG.
TheTable19-5showsanoperatingfrequencyandbaudrate.
ThefrequencieswhicharenotdescribedinTable19-5cannotbeused.
-Baudrate(Default):9600bps-Datalength:8bits-Parityaddition:None-Stopbit:1bitTable19-4BaudRateModificationDataBaudratemodificationdata04H05H06H07H0AH18H28HBaudrate(bps)7680062500576003840031250192009600Page20019.
SerialPROMMode19.
4InterfaceSpecificationsforUARTTMP86FS23UGNote1:"Ref.
Frequency"and"Rating"showfrequenciesavailableintheserialPROMmode.
ThoughthefrequencyissupportedintheserialPROMmode,theserialPROMmodemaynotbeactivatedcorrectlyduetothefrequencydifferenceintheexternalcontroller(suchaspersonalcomputer)andoscillator,andloadcapacitanceofcommunicationpins.
Note2:Itisrecommendedthatthetotalfrequencydifferenceiswithin±3%sothatautodetectionisperformedcorrectlybytheref-erencefrequency.
Note3:Theexternalcontrollermusttransmitthematchingdata(5AH)repeatedlytilltheautodetectionofbaudrateisperformed.
Thisnumberindicatesthenumberoftimesthematchingdataistransmittedforeachfrequency.
Table19-5OperatingFrequencyandBaudRateintheSerialPROMMode(Note3)ReferenceBaudRate(bps)7680062500576003840031250192009600BaudRateModificationData04H05H06H07H0AH18H28HRef.
Fre-quency(MHz)Rating(MHz)Baudrate(bps)(%)(bps)(%)(bps)(%)(bps)(%)(bps)(%)(bps)(%)(bps)(%)121.
91to2.
109615+0.
16243.
82to4.
19312500.
0019231+0.
169615+0.
164.
193.
82to4.
1932734+4.
7520144+4.
9210072+4.
9234.
91524.
70to5.
16384000.
00--192000.
0096000.
0054.
70to5.
1639063+1.
73--19531+1.
739766+1.
73465.
87to6.
459375-2.
346.
1445.
87to6.
4596000.
0057.
37287.
05to7.
74---576000.
00----192000.
0096000.
00687.
64to8.
39--625000.
00--38462+0.
16312500.
0019231+0.
169615+0.
1679.
83049.
40to10.
32768000.
00----384000.
00--192000.
0096000.
00109.
40to10.
3278125+1.
73----39063+1.
73--19531+1.
739766+1.
7381211.
75to12.
90----57692+0.
16--312500.
0018750-2.
349375-2.
3412.
28811.
75to12.
90----59077+2.
56--32000+2.
40192000.
0096000.
0012.
511.
75to12.
90--60096-3.
8560096+4.
33--30048-3.
8519531+1.
739766+1.
73914.
745614.
10to15.
48----576000.
00384000.
00--192000.
0096000.
00101615.
27to16.
7776923+0.
16625000.
00--38462+0.
16312500.
0019231+0.
169615+0.
16Page201TMP86FS23UG19.
5OperationCommandTheeightcommandsshowninTable19-6areusedintheserialPROMmode.
Afterresetrelease,theTMP86FS23UGwaitsforthematchingdata(5AH).
19.
6OperationModeTheserialPROMmodehasseventypesofmodes,thatare(1)Flashmemoryerasing,(2)Flashmemorywriting,(3)RAMloader,(4)FlashmemorySUMoutput,(5)ProductIDcodeoutput,(6)Flashmemorystatusoutputand(7)Flashmemoryreadprotectionsettingmodes.
Descriptionofeachmodeisshownbelow.
1.
FlashmemoryerasingmodeTheflashmemoryiserasedbythechiperase(erasinganentireflasharea)orsectorerase(erasingsectorsin4-kbyteunits).
TheerasedareaisfilledwithFFH.
Whenthereadprotectionisenabled,thesectoreraseintheflasherasingmodecannotbeperformed.
Todisablethereadprotection,performthechiperase.
Beforeerasingtheflashmemory,TMP86FS23UGchecksthepasswordsexceptablankproduct.
Ifthepasswordisnotmatched,theflashmemoryerasingmodeisnotactivated.
2.
FlashmemorywritingmodeDataiswrittentothespecifiedflashmemoryaddressforeachbyteunit.
Theexternalcontrollermusttrans-mitthewritedataintheIntelHexformat(Binary).
Ifnoerrorisencounteredtilltheendrecord,TMP86FS23UGcalculatesthechecksumfortheentireflashmemoryarea(1000HtoFFFFH),andreturnstheobtainedresulttotheexternalcontroller.
Whenthereadprotectionisenabled,theflashmemorywritingmodeisnotactivated.
Inthiscase,performthechiperasecommandbeforehandintheflashmemoryeras-ingmode.
Beforeactivatingtheflashmemorywritingmode,TMP86FS23UGchecksthepasswordexceptablankproduct.
Ifthepasswordisnotmatched,flashmemorywritingmodeisnotactivated.
3.
RAMloadermodeTheRAMloadertransfersthedatainIntelHexformatsentfromtheexternalcontrollertotheinternalRAM.
Whenthetransferiscompletednormally,theRAMloadercalculatesthechecksum.
Aftertransmit-tingtheresults,theRAMloaderjumpstotheRAMaddressspecifiedwiththefirstdatarecordinordertoexecutetheuserprogram.
Whenthereadprotectionisenabled,theRAMloadermodeisnotactivated.
Inthiscase,performthechiperasebeforehandintheflashmemoryerasingmode.
BeforeactivatingtheRAMloadermode,TMP86FS23UGchecksthepasswordexceptablankproduct.
Ifthepasswordisnotmatched,flashRAMloadermodeisnotactivated.
4.
FlashmemorySUMoutputmodeThechecksumiscalculatedfortheentireflashmemoryarea(1000HtoFFFFH),andtheresultisreturnedtotheexternalcontroller.
SincetheBOOTROMdoesnotsupporttheoperationcommandtoreadtheflashmemory,usethischecksumtoidentifyprogramswhenmanagingrevisionsofapplicationprograms.
5.
ProductIDcodeoutputThecodeusedtoidentifytheproductisoutput.
Thecodetobeoutputconsistsof13-bytedata,whichincludestheinformationindicatingtheareaoftheROMincorporatedintheproduct.
Theexternalcontrol-lerreadsthiscode,andrecognizestheproducttowrite.
(InthecaseofTMP86FS23UG,theaddressesfrom1000HtoFFFFHbecometheROMarea.
)Table19-6OperationCommandintheSerialPROMModeCommandDataOperatingModeDescription5AHSetupMatchingdata.
Executethiscommandafterreleasingthereset.
F0HFlashmemoryerasingErasestheflashmemoryarea(address1000HtoFFFFH).
30HFlashmemorywritingWritestotheflashmemoryarea(address1000HtoFFFFH).
60HRAMloaderWritestothespecifiedRAMarea(address0050Hto083FH).
90HFlashmemorySUMoutputOutputsthe2-bytechecksumupperbyteandlowerbyteinthisorderfortheentireareaoftheflashmemory(address1000HtoFFFFH).
C0HProductIDcodeoutputOutputstheproductIDcode(13-bytedata).
C3HFlashmemorystatusoutputOutputsthestatuscode(7-bytedata)suchasthereadprotectioncondition.
FAHFlashmemoryreadprotectionsettingEnablesthereadprotection.
Page20219.
SerialPROMMode19.
6OperationModeTMP86FS23UG6.
FlashmemorystatusoutputmodeThestatusoftheareafromFFE0HtoFFFFH,andthereadprotectionconditionareoutputas7-bytecode.
Theexternalcontrollerreadsthiscodetorecognizetheflashmemorystatus.
7.
FlashmemoryreadprotectionsettingmodeThismodedisablesreadingtheflashmemorydatainparallelPROMmode.
IntheserialPROMmode,theflashmemorywritingandRAMloadermodesaredisabled.
Todisabletheflashmemoryreadprotection,performthechiperaseintheflashmemoryerasingmode.
Page203TMP86FS23UG19.
6.
1FlashMemoryErasingMode(Operatingcommand:F0H)Table19-7showstheflashmemoryerasingmode.
Note1:"xxH*3"indicatesthatthedeviceentersthehaltconditionaftertransmitting3bytesofxxh.
Note2:Referto"19.
13SpecifyingtheErasureArea".
Note3:Referto"19.
8Checksum(SUM)".
Note4:Referto"19.
10Passwords".
Note5:Donottransmitthepasswordstringforablankproduct.
Note6:Whenapassworderroroccurs,TMP86FS23UGstopsUARTcommunicationandentersthehaltmode.
Therefore,whenapassworderroroccurs,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialPROMmode.
Note7:Ifanerroroccursduringtransferofapasswordaddressorapasswordstring,TMP86FS23UGstopsUARTcommunica-tionandentersthehaltcondition.
Therefore,whenapassworderroroccurs,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialPROMmode.
Descriptionoftheflashmemoryerasingmode1.
The1stthrough4thbytesofthetransmittedandreceiveddatacontainthesamedataasintheflashmemorywritingmode.
Table19-7FlashMemoryErasingModeTransferByteTransferDatafromtheExternalControllertoTMP86FS23UGBaudRateTransferDatafromTMP86FS23UGtotheExternalControllerBOOTROM1stbyte2ndbyteMatchingdata(5AH)-9600bps9600bps-(Automaticbaudrateadjustment)OK:Echobackdata(5AH)Error:Nodatatransmitted3rdbyte4thbyteBaudratechangedata(Table19-4)-9600bps9600bps-OK:EchobackdataError:A1H*3,A3H*3,62H*3(Note1)5thbyte6thbyteOperationcommanddata(F0H)-ModifiedbaudrateModifiedbaudrate-OK:Echobackdata(F0H)Error:A1H*3,A3H*3,63H*3(Note1)7thbyte8thbytePasswordcountstorageaddressbit15to08(Note4,5)ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted9thbyte10thbytePasswordcountstorageaddressbit07to00(Note4,5)ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted11thbyte12thbytePasswordcomparisonstartaddressbit15to08(Note4,5)ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted13thbyte14thbytePasswordcomparisonstartaddressbit07to00(Note4,5)ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted)15thbyte:m'thbytePasswordstring(Note4,5)-ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmittedn'th-2byteEraseareaspecification(Note2)Modifiedbaudrate-n'th-1byte-ModifiedbaudrateOK:Checksum(Upperbyte)(Note3)Error:Nothingtransmittedn'thbyte-ModifiedbaudrateOK:Checksum(Lowerbyte)(Note3)Error:Nothingtransmittedn'th+1byte(Waitforthenextoperationcommanddata)Modifiedbaudrate-Page20419.
SerialPROMMode19.
6OperationModeTMP86FS23UG2.
The5thbyteofthereceiveddatacontainsthecommanddataintheflashmemoryerasingmode(F0H).
3.
Whenthe5thbyteofthereceiveddatacontainstheoperationcommanddatashowninTable19-6,thedeviceechoesbackthevaluewhichisthesamedatainthe6thbytepositionofthereceiveddata(inthiscase,F0H).
Ifthe5thbyteofthereceiveddatadoesnotcontaintheoperationcommanddata,thedeviceentersthehaltconditionaftersending3bytesoftheoperationcommanderrorcode(63H).
4.
The7ththoroughm'thbytesofthetransmittedandreceiveddatacontainthesamedataasintheflashmemorywritingmode.
Inthecaseofablankproduct,donottransmitapasswordstring.
(Donottransmitadummypasswordstring.
)5.
Then'th-2bytecontainstheerasureareaspecificationdata.
Theupper4bitsandlower4bitsspecifythestartaddressandendaddressoftheerasurearea,respectively.
Forthedetaileddescription,see"1.
13SpecifyingtheErasureArea".
6.
Then'th-1byteandn'thbytecontaintheupperandlowerbytesofthechecksum,respectively.
Forhowtocalculatethechecksum,referto"1.
8Checksum(SUM)".
ChecksumiscalculatedunlessareceivingerrororIntelHexformaterroroccurs.
Aftersendingtheendrecord,theexternalcontrollerjudgeswhetherthetransmissioniscompletedcorrectlybyreceivingthechecksumsentbythedevice.
7.
Aftersendingthechecksum,thedevicewaitsforthenextoperationcommanddata.
Page205TMP86FS23UG19.
6.
2FlashMemoryWritingMode(Operationcommand:30H)Table19-8showsflashmemorywritingmodeprocess.
Note1:"xxH*3"indicatesthatthedeviceentersthehaltconditionaftersending3bytesofxxH.
Fordetails,referto"19.
7ErrorCode".
Note2:Referto"19.
9IntelHexFormat(Binary)".
Note3:Referto"19.
8Checksum(SUM)".
Note4:Referto"19.
10Passwords".
Note5:IfaddressesfromFFE0HtoFFFFHarefilledwith"FFH",thepasswordsarenotcomparedbecausethedeviceisconsid-eredasablankproduct.
Transmittingapasswordstringisnotrequired.
Eveninthecaseofablankproduct,itisrequiredtospecifythepasswordcountstorageaddressandthepasswordcomparisonstartaddress.
Transmitthesedatafromtheexternalcontroller.
Ifapassworderroroccursduetoincorrectpasswordcountstorageaddressorpasswordcomparisonstartaddress,TMP86FS23UGstopsUARTcommunicationandentersthehaltcondition.
Therefore,whenapassworderroroccurs,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialROMmode.
Note6:Ifthereadprotectionisenabledorapassworderroroccurs,TMP86FS23UGstopsUARTcommunicationandentersthehaltconfition.
Inthiscase,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialROMmode.
Note7:Ifanerroroccursduringthereceptionofapasswordaddressorapasswordstring,TMP86FS23UGstopsUARTcommu-nicationandentersthehaltcondition.
Inthiscase,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialPROMmode.
Table19-8FlashMemoryWritingModeProcessTransferByteTransferDatafromExternalControllertoTMP86FS23UGBaudRateTransferDatafromTMP86FS23UGtoExternalControllerBOOTROM1stbyte2ndbyteMatchingdata(5Ah)-9600bps9600bps-(Automaticbaudrateadjustment)OK:Echobackdata(5AH)Error:Nothingtransmitted3rdbyte4thbyteBaudratemodificationdata(SeeTable19-4)-9600bps9600bps-OK:EchobackdataError:A1H*3,A3H*3,62H*3(Note1)5thbyte6thbyteOperationcommanddata(30H)-ModifiedbaudrateModifiedbaudrate-OK:Echobackdata(30H)Error:A1H*3,A3H*3,63H*3(Note1)7thbyte8thbytePasswordcountstorageaddressbit15to08(Note4)Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted9thbyte10thbytePasswordcountstorageaddressbit07to00(Note4)Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted11thbyte12thbytePasswordcomparisonstartaddressbit15to08(Note4)Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted13thbyte14thbytePasswordcomparisonstartaddressbit07to00(Note4)Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted)15thbyte:m'thbytePasswordstring(Note5)-Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmittedm'th+1byte:n'th-2byteIntelHexformat(binary)(Note2)Modifiedbaudrate--n'th-1byte-ModifiedbaudrateOK:SUM(Upperbyte)(Note3)Error:Nothingtransmittedn'thbyte-ModifiedbaudrateOK:SUM(Lowerbyte)(Note3)Error:Nothingtransmittedn'th+1byte(Waitstateforthenextoperationcom-manddata)Modifiedbaudrate-Page20619.
SerialPROMMode19.
6OperationModeTMP86FS23UGDescriptionoftheflashmemorywritingmode1.
The1stbyteofthereceiveddatacontainsthematchingdata.
WhentheserialPROMmodeisacti-vated,TMP86FS23UG(hereaftercalleddevice),waitstoreceivethematchingdata(5AH).
Uponreceptionofthematchingdata,thedeviceautomaticallyadjuststheUART'sinitialbaudrateto9600bps.
2.
Whenreceivingthematchingdata(5AH),thedevicetransmitsanechobackdata(5AH)asthesecondbytedatatotheexternalcontroller.
Ifthedevicecannotrecognizethematchingdata,itdoesnottransmittheechobackdataandwaitsforthematchingdataagainwithautomaticbaudrateadjust-ment.
Therefore,theexternalcontrollershouldtransmitthematchingdatarepeatedlytillthedevicetransmitsanechobackdata.
Thetransmissionrepetitioncountvariesdependingonthefrequencyofdevice.
Fordetails,refertoTable19-5.
3.
The3rdbyteofthereceiveddatacontainsthebaudratemodificationdata.
ThefivetypesofbaudratemodificationdatashowninTable19-4areavailable.
Evenifbaudrateisnotmodified,theexternalcontrollershouldtransmittheinitialbaudratedata(28H:9600bps).
4.
Onlywhenthe3rdbyteofthereceiveddatacontainsthebaudratemodificationdatacorrespondingtothedevice'soperatingfrequency,thedeviceechoesbackdatathevaluewhichisthesamedatainthe4thbytepositionofthereceiveddata.
Aftertheechobackdataistransmitted,baudratemodificationbecomeseffective.
Ifthe3rdbyteofthereceiveddatadoesnotcontainthebaudratemodificationdata,thedeviceentersthehaltsconditionaftersending3bytesofbaudratemodificationerrorcode(62H).
5.
The5thbyteofthereceiveddatacontainsthecommanddata(30H)towritetheflashmemory.
6.
Whenthe5thbyteofthereceiveddatacontainstheoperationcommanddatashowninTable1-6,thedeviceechoesbackthevaluewhichisthesamedatainthe6thbytepositionofthereceiveddata(inthiscase,30H).
Ifthe5thbyteofthereceiveddatadoesnotcontaintheoperationcommanddata,thedeviceentersthehaltconditionaftersending3bytesoftheoperationcommanderrorcode(63H).
7.
The7thbytecontainsthedatafor15to8bitsofthepasswordcountstorageaddress.
Whenthedatareceivedwiththe7thbytehasnoreceivingerror,thedevicedoesnotsendanydata.
Ifareceivingerrororpassworderroroccurs,thedevicedoesnotsendanydataandentersthehaltcondition.
8.
The9thbytecontainsthedatafor7to0bitsofthepasswordcountstorageaddress.
Whenthedatareceivedwiththe9thbytehasnoreceivingerror,thedevicedoesnotsendanydata.
Ifareceivingerrororpassworderroroccurs,thedevicedoesnotsendanydataandentersthehaltcondition.
9.
The11thbytecontainsthedatafor15to8bitsofthepasswordcomparisonstartaddress.
Whenthedatareceivedwiththe11thbytehasnoreceivingerror,thedevicedoesnotsendanydata.
Ifareceiv-ingerrororpassworderroroccurs,thedevicedoesnotsendanydataandentersthehaltcondition.
10.
The13thbytecontainsthedatafor7to0bitsofthepasswordcomparisonstartaddress.
Whenthedatareceivedwiththe13thbytehasnoreceivingerror,thedevicedoesnotsendanydata.
Ifareceiv-ingerrororpassworderroroccurs,thedevicedoesnotsendanydataandentersthehaltcondition.
11.
The15ththroughm'thbytescontainthepassworddata.
Thenumberofpasswordsbecomesthedata(N)storedinthepasswordcountstorageaddress.
TheexternalpassworddataiscomparedwithN-bytedatafromtheaddressspecifiedbythepasswordcomparisonstartaddress.
Theexternalcontrol-lershouldsendN-bytepassworddatatothedevice.
Ifthepasswordsdonotmatch,thedeviceentersthehaltconditionwithoutreturninganerrorcodetotheexternalcontroller.
IftheaddressesfromFFE0HtoFFFFHarefilledwith"FFH",thepasswordsarenotconparedbecausethedeviceisconsid-eredasablankproduct.
12.
Them'th+1throughn'th-2bytesofthereceiveddatacontainthebinarydataintheIntelHexfor-mat.
Noreceiveddataisechoedbacktotheexternalcontroller.
Afterreceivingthestartmark(3AHfor":")intheIntelHexformat,thedevicestartsdatarecordreception.
Therefore,thereceiveddataexcept3AHisignoreduntilthestartmarkisreceived.
Afterreceivingthestartmark,thedevicereceivesthedatarecord,thatconsistsofdatalength,address,recordtype,writedataandchecksum.
Sincethedevicestartschecksumcalculationafterreceivinganendrecord,theexternalcontrollershouldwaitforthechecksumaftersendingtheendrecord.
IfareceivingerrororIntelHexformaterroroccurs,thedeviceentersthehaltsconditionwithoutreturninganerrorcodetotheexternalcon-troller.
13.
Then'th-1andn'thbytescontainthechecksumupperandlowerbytes.
Fordetailsonhowtocalcu-latetheSUM,referto"19.
8Checksum(SUM)".
ThechecksumiscalculatedonlywhentheendrecordisdetectedandnoreceivingerrororIntelHexformaterroroccurs.
AftersendingtheendPage207TMP86FS23UGrecord,theexternalcontrollerjudgeswhetherthetransmissioniscompletedcorrectlybyreceivingthechecksumsentbythedevice.
14.
Aftertransmittingthechecksum,thedevicewaitsforthenextoperationcommanddata.
Note1:DonotwriteonlytheaddressfromFFE0HtoFFFFHwhenallflashmemorydataisthesame.
Ifonlytheseareaarewritten,thesubsequentoperationcannotbeexecutedduetopassworderror.
Note2:TorewritedatatoFlashmemoryaddressesatwhichdata(includingFFH)isalreadywritten,makesuretoerasetheexistingdataby"sectorerase"or"chiperase"beforerewritingdata.
Page20819.
SerialPROMMode19.
6OperationModeTMP86FS23UG19.
6.
3RAMLoaderMode(OperationCommand:60H)Table19-9showsRAMloadermodeprocess.
Note1:"xxH*3"indicatesthatthedeviceentersthehaltconditionaftersending3bytesofxxH.
Fordetails,referto"19.
7ErrorCode".
Note2:Referto"19.
9IntelHexFormat(Binary)".
Note3:Referto"19.
8Checksum(SUM)".
Note4:Referto"19.
10Passwords".
Note5:IfaddressesfromFFE0HtoFFFFHarefilledwith"FFH",thepasswordsarenotcomparedbecausethedeviceisconsid-eredasablankproduct.
Transmittingapasswordstringisnotrequired.
Eveninthecaseofablankproduct,itisrequiredtospecifythepasswordcountstorageaddressandthepasswordcomparisonstartaddress.
Transmitthesedatafromtheexternalcontroller.
Ifapassworderroroccursduetoincorrectpasswordcountstorageaddressorpasswordcomparisonstartaddress,TMP86FS23UGstopsUARTcommunicationandentersthehaltcondition.
Therefore,whenapassworderroroccurs,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialROMmode.
Note6:Aftertransmittingapasswordstring,theexternalcontrollermustnottransmitonlyanendrecord.
Ifreceivinganendrecordafterapasswordstring,thedevicemaynotoperatecorrectly.
Note7:Ifthereadprotectionisenabledorapassworderroroccurs,TMP86FS23UGstopsUARTcommunicationandentersthehaltcondition.
Inthiscase,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialPROMmode.
Table19-9RAMLoaderModeProcessTransferBytesTransferDatafromExternalControl-lertoTMP86FS23UGBaudRateTransferDatafromTMP86FS23UGtoExternalControllerBOOTROM1stbyte2ndbyteMatchingdata(5AH)-9600bps9600bps-(Automaticbaudrateadjustment)OK:Echobackdata(5AH)Error:Nothingtransmitted3rdbyte4thbyteBaudratemodificationdata(SeeTable19-4)-9600bps9600bps-OK:EchobackdataError:A1H*3,A3H*3,62H*3(Note1)5thbyte6thbyteOperationcommanddata(60H)-ModifiedbaudrateModifiedbaudrate-OK:Echobackdata(60H)Error:A1H*3,A3H*3,63H*3(Note1)7thbyte8thbytePasswordcountstorageaddressbit15to08(Note4)Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted9thbyte10thbytePasswordcountstorageaddressbit07to00(Note4)Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted11thbyte12thbytePasswordcomparisonstartaddressbit15to08(Note4)Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted13thbyte14thbytePasswordcomparisonstartaddressbit07to00(Note4)Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted15thbyte:m'thbytePasswordstring(Note5)-Modifiedbaudrate-OK:NothingtransmittedError:Nothingtransmittedm'th+1byte:n'th-2byteIntelHexformat(Binary)(Note2)ModifiedbaudrateModifiedbaudrate--n'th-1byte-ModifiedbaudrateOK:SUM(Upperbyte)(Note3)Error:Nothingtransmittedn'thbyte-ModifiedbaudrateOK:SUM(Lowerbyte)(Note3)Error:NothingtransmittedRAM-TheprogramjumpstothestartaddressofRAMinwhichthefirsttransferreddataiswritten.
Page209TMP86FS23UGNote8:Ifanerroroccursduringthereceptionofapasswordaddressorapasswordstring,TMP86FS23UGstopsUARTcommu-nicationandentersthehaltcondition.
Inthiscase,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialPROMmode.
DescriptionofRAMloadermode1.
The1stthrough4thbytesofthetransmittedandreceiveddatacontainsthesamedataasintheflashmemorywritingmode.
2.
Inthe5thbyteofthereceiveddatacontainstheRAMloadercommanddata(60H).
3.
Whenth5thbyteofthereceiveddatacontainstheoperationcommanddatashowninTable1-6,thedeviceechoesbackthevaluewhichisthesamedatainthe6thbyteposition(inthiscase,60H).
Ifthe5thbytedoesnotcontaintheoperationcommanddata,thedeviceentersthehaltconditionaftersend-ing3bytesofoperationcommanderrorcode(63H).
4.
The7ththroughm'thbytesofthetransmittedandreceiveddatacontainthesamedataasintheflashmemorywritingmode.
5.
Them'th+1throughn'th-2bytesofthereceiveddatacontainthebinarydataintheIntelHexfor-mat.
Noreceiveddataisechoedbacktotheexternalcontroller.
Afterreceivingthestartmark(3AHfor":")intheIntelHexformat,thedevicestartsdatarecordreception.
Therefore,thereceiveddataexcept3AHisignoreduntilthestartmarkisreceived.
Afterreceivingthestartmark,thedevicereceivesthedatarecord,thatconsistsofdatalength,address,recordtype,writedataandchecksum.
ThewritingdataofthedatarecordiswrittenintoRAMspecifiedbyaddress.
Sincethedevicestartschecksumcalculationafterreceivinganendrecord,theexternalcontrollershouldwaitforthecheck-sumaftersendingtheendrecord.
IfareceivingerrororIntelHexformaterroroccurs,thedeviceentersthehaltsconditionwithoutreturninganerrorcodetotheexternalcontroller.
6.
Then'th-1andn'thbytescontainthechecksumupperandlowerbytes.
Fordetailsonhowtocalcu-latetheSUM,referto"19.
8Checksum(SUM)".
ThechecksumiscalculatedonlywhentheendrecordisdetectedandnoreceivingerrororIntelHexformaterroroccurs.
Aftersendingtheendrecord,theexternalcontrollerjudgeswhetherthetransmissioniscompletedcorrectlybyreceivingthechecksumsentbythedevice.
7.
Aftertransmittingthechecksumtotheexternalcontroller,thebootprogramjumpstotheRAMaddressthatisspecifiedbythefirstreceiveddatarecord.
Note1:TorewritedatatoFlashmemoryaddressesatwhichdata(includingFFH)isalreadywritten,makesuretoerasetheexistingdataby"sectorerase"or"chiperase"beforerewritingdata.
Page21019.
SerialPROMMode19.
6OperationModeTMP86FS23UG19.
6.
4FlashMemorySUMOutputMode(OperationCommand:90H)Table19-10showsflashmemorySUMoutputmodeprocess.
Note1:"xxH*3"indicatesthatthedeviceentersthehaltconditionaftersending3bytesofxxH.
Fordetails,referto"19.
7ErrorCode".
Note2:Referto"19.
8Checksum(SUM)".
DescriptionoftheflashmemorySUMoutputmode1.
The1stthrough4thbytesofthetransmittedandreceiveddatacontainsthesamedataasintheflashmemorywritingmode.
2.
The5thbyteofthereceiveddatacontainsthecommanddataintheflashmemorySUMoutputmode(90H).
3.
Whenthe5thbyteofthereceiveddatacontainstheoperationcommanddatashowninTable1-6,thedeviceechoesbackthevaluewhichisthesamedatainthe6thbytepositionofthereceiveddata(inthiscase,90H).
Ifthe5thbyteofthereceiveddatadoesnotcontaintheoperationcommanddata,thedeviceentersthehaltconditionaftertransmitting3bytesofoperationcommanderrorcode(63H).
4.
The7thandthe8thbytescontaintheupperandlowerbitsofthechecksum,respectively.
Forhowtocalculatethechecksum,referto"19.
8Checksum(SUM)".
5.
Aftersendingthechecksum,thedevicewaitsforthenextoperationcommanddata.
Table19-10FlashMemorySUMOutputProcessTransferBytesTransferDatafromExternalControl-lertoTMP86FS23UGBaudRateTransferDatafromTMP86FS23UGtoExternalControllerBOOTROM1stbyte2ndbyteMatchingdata(5AH)-9600bps9600bps-(Automaticbaudrateadjustment)OK:Echobackdata(5AH)Error:Nothingtransmitted3rdbyte4thbyteBaudratemodificationdata(SeeTable19-4)-9600bps9600bps-OK:EchobackdataError:A1H*3,A3H*3,62H*3(Note1)5thbyte6thbyteOperationcommanddata(90H)-ModifiedbaudrateModifiedbaudrate-OK:Echobackdata(90H)Error:A1H*3,A3H*3,63H*3(Note1)7thbyte-ModifiedbaudrateOK:SUM(Upperbyte)(Note2)Error:Nothingtransmitted8thbyte-ModifiedbaudrateOK:SUM(Lowerbyte)(Note2)Error:Nothingtransmitted9thbyte(Waitforthenextoperationcom-manddata)Modifiedbaudrate-Page211TMP86FS23UG19.
6.
5ProductIDCodeOutputMode(OperationCommand:C0H)Table19-11showsproductIDcodeoutputmodeprocess.
Note:"xxH*3"indicatesthatthedeviceentersthehaltconditionaftersending3bytesofxxH.
Fordetails,referto"19.
7ErrorCode".
DescriptionofProductIDcodeoutputmode1.
The1stthrough4thbytesofthetransmittedandreceiveddatacontainthesamedataasintheflashmemorywritingmode.
2.
The5thbyteofthereceiveddatacontainstheproductIDcodeoutputmodecommanddata(C0H).
3.
Whenthe5thbytecontainstheoperationcommanddatashowninTable19-6,thedeviceechoesbackthevaluewhichisthesamedatainthe6thbytepositionofthereceiveddata(inthiscase,C0H).
Ifthe5thbytedatadoesnotcontaintheoperationcommanddata,thedeviceentersthehaltconditionaftersending3bytesofoperationcommanderrorcode(63H).
4.
The9ththrough19thbytescontaintheproductIDcode.
Fordetails,referto"19.
11ProductIDCode".
Table19-11ProductIDCodeOutputProcessTransferBytesTransferDatafromExternalControllertoTMP86FS23UGBaudRateTransferDatafromTMP86FS23UGtoExternalControllerBOOTROM1stbyte2ndbyteMatchingdata(5AH)-9600bps9600bps-(Automaticbaudrateadjustment)OK:Echobackdata(5AH)Error:Nothingtransmitted3rdbyte4thbyteBaudratemodificationdata(SeeTable19-4)-9600bps9600bps-OK:EchobackdataError:A1H*3,A3H*3,62H*3(Note1)5thbyte6thbyteOperationcommanddata(C0H)-ModifiedbaudrateModifiedbaudrate-OK:Echobackdata(C0H)Error:A1H*3,A3H*3,63H*3(Note1)7thbyteModifiedbaudrate3AHStartmark8thbyteModifiedbaudrate0AHThenumberoftransferdata(from9thto18thbytes)9thbyteModifiedbaudrate02HLengthofaddress(2bytes)10thbyteModifiedbaudrate1DHReserveddata11thbyteModifiedbaudrate00HReserveddata12thbyteModifiedbaudrate00HReserveddata13thbyteModifiedbaudrate00HReserveddata14thbyteModifiedbaudrate01HROMblockcount(1block)15thbyteModifiedbaudrate10HFirstaddressofROM(Upperbyte)16thbyteModifiedbaudrate00HFirstaddressofROM(Lowerbyte)17thbyteModifiedbaudrateFFHEndaddressofROM(Upperbyte)18thbyteModifiedbaudrateFFHEndaddressofROM(Lowerbyte)19thbyteModifiedbaudrateD2HChecksumoftransferreddata(9ththrough18thbyte)20thbyte(Waitforthenextoperationcommanddata)Modifiedbaudrate-Page21219.
SerialPROMMode19.
6OperationModeTMP86FS23UG5.
Aftersendingthechecksum,thedevicewaitsforthenextoperationcommanddata.
Page213TMP86FS23UG19.
6.
6FlashMemoryStatusOutputMode(OperationCommand:C3H)Table19-12showsFlashmemorystatusoutputmodeprocess.
Note1:"xxH*3"indicatesthatthedeviceentersthehaltconditionaftersending3bytesofxxH.
Fordetails,referto"19.
7ErrorCode".
Note2:Forthedetailsonstatuscode1,referto"19.
12FlashMemoryStatusCode".
DescriptionofFlashmemorystatusoutputmode1.
The1stthrough4thbytesofthetransmittedandreceiveddatacontainthesamedataasintheFlashmemorywritingmode.
2.
The5thbyteofthereceiveddatacontainstheflashmemorystatusoutputmodecommanddata(C3H).
3.
Whenthe5thbytecontainstheoperationcommanddatashowninTable19-6,thedeviceechoesbackthevaluewhichisthesamedatainthe6thbytepositionofthereceiveddata(inthiscase,C3H).
Ifthe5thbytedoesnotcontaintheoperationcommanddata,thedeviceentersthehaltconditionaftersend-ing3bytesofoperationcommanderrorcode(63H).
4.
The9ththrough13thbytescontainthestatuscode.
Fordetailsonthestatuscode,referto"19.
12FlashMemoryStatusCode".
5.
Aftersendingthestatuscode,thedevicewaitsforthenextoperationcommanddata.
Table19-12FlashMemoryStatusOutputModeProcessTransferBytesTransferDatafromExternalCon-trollertoTMP86FS23UGBaudRateTransferDatafromTMP86FS23UGtoExter-nalControllerBOOTROM1stbyte2ndbyteMatchingdata(5AH)-9600bps9600bps-(Automaticbaudrateadjustment)OK:Echobackdata(5AH)Error:Nothingtransmitted3rdbyte4thbyteBaudratemodificationdata(SeeTable19-4)-9600bps9600bps-OK:EchobackdataError:A1H*3,A3H*3,62H*3(Note1)5thbyte6thbyteOperationcommanddata(C3H)-ModifiedbaudrateModifiedbaudrate-OK:Echobackdata(C3H)Error:A1H*3,A3H*3,63H*3(Note1)7thbyteModifiedbaudrate3AHStartmark8thbyteModifiedbaudrate04HBytecount(from9thto12thbyte)9thbyteModifiedbaudrate00Hto03HStatuscode110thbyteModifiedbaudrate00HReserveddata11thbyteModifiedbaudrate00HReserveddata12thbyteModifiedbaudrate00HReserveddata13thbyteModifiedbaudrateChecksum2'scomplementforthesumof9ththrough12thbytes9thbyteChecksum00H:00H01H:FFH02H:FEH03H:FDH14thbyte(Waitforthenextoperationcom-manddata)Modifiedbaudrate-Page21419.
SerialPROMMode19.
6OperationModeTMP86FS23UG19.
6.
7FlashMemoryReadProtectionSettingMode(OperationCommand:FAH)Table19-13showsFlashmemoryreadprotectionsettingmodeprocess.
Note1:"xxH*3"indicatesthatthedeviceentersthehaltconditionaftersending3bytesofxxH.
Fordetails,referto"19.
7ErrorCode".
Note2:Referto"19.
10Passwords".
Note3:Ifthereadprotectionisenabledforablankproductorapassworderroroccursforanon-blankproduct,TMP86FS23UGstopsUARTcommunicationandentersthehaltmode.
Inthiscase,initializeTMP86FS23UGbytheRESETpinandreacti-vatetheserialPROMmode.
Note4:Ifanerroroccursduringreceptionofapasswordaddressorapasswordstring,TMP86FS23UGstopsUARTcommunica-tionandentersthehaltmode.
Inthiscase,initializeTMP86FS23UGbytheRESETpinandreactivatetheserialPROMmode.
DescriptionoftheFlashmemoryreadprotectionsettingmode1.
The1stthrough4thbytesofthetransmittedandreceiveddatacontainthesamedataasintheFlashmemorywritingmode.
2.
The5thbyteofthereceiveddatacontainsthecommanddataintheflashmemorystatusoutputmode(FAH).
3.
Whenthe5thbyteofthereceiveddatacontainstheoperationcommanddatashowninTable1-6,thedeviceechoesbackthevaluewhichisthesamedatainthe6thbytepositionofthereceiveddata(inTable19-13FlashMemoryReadProtectionSettingModeProcessTransferBytesTransferDatafromExternalCon-trollertoTMP86FS23UGBaudRateTransferDatafromTMP86FS23UGtoExter-nalControllerBOOTROM1stbyte2ndbyteMatchingdata(5AH)-9600bps9600bps-(Automaticbaudrateadjustment)OK:Echobackdata(5AH)Error:Nothingtransmitted3rdbyte4thbyteBaudratemodificationdata(SeeTable19-4)-9600bps9600bps-OK:EchobackdataError:A1H*3,A3H*3,62H*3(Note1)5thbyte6thbyteOperationcommanddata(FAH)-ModifiedbaudrateModifiedbaudrate-OK:Echobackdata(FAH)Error:A1H*3,A3H*3,63H*3(Note1)7thbyte8thbytePasswordcountstorageaddress15to08(Note2)ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted9thbyte10thbytePasswordcountstorageaddress07to00(Note2)ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted11thbyte12thbytePasswordcomparisonstartaddress15to08(Note2)ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted13thbyte14thbytePasswordcomparisonstartaddress07to00(Note2)ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmitted15thbyte:m'thbytePasswordstring(Note2)-ModifiedbaudrateModifiedbaudrate-OK:NothingtransmittedError:Nothingtransmittedn'thbyte-ModifiedbaudrateOK:FBH(Note3)Error:Nothingtransmittedn'+1thbyte(Waitforthenextoperationcom-manddata)Modifiedbaudrate-Page215TMP86FS23UGthiscase,FAH).
Ifthe5thbytedoesnotcontaintheoperationcommanddata,thedeviceentersthehaltconditionaftertransmitting3bytesofoperationcommanderrorcode(63H).
4.
The7ththroughm'thbytesofthetransmittedandreceiveddatacontainthesamedataasintheflashmemorywritingmode.
5.
Then'thbytecontainsthestatustobetransmittedtotheexternalcontrollerinthecaseofthesuccess-fulreadprotection.
Page21619.
SerialPROMMode19.
7ErrorCodeTMP86FS23UG19.
7ErrorCodeWhendetectinganerror,thedevicetransmitstheerrorcodetotheexternalcontroller,asshowninTable19-14.
Note:Ifapassworderroroccurs,TMP86FS23UGdoesnottransmitanerrorcode.
19.
8Checksum(SUM)19.
8.
1CalculationMethodThechecksum(SUM)iscalculatedwiththesumofallbytes,andtheobtainedresultisreturnedasaword.
Thedataisreadforeachbyteunitandthecalculatedresultisreturnedasaword.
Example:Thechecksumwhichistransmittedbyexecutingtheflashmemorywritecommand,RAMloadercommand,orflashmemorySUMoutputcommandiscalculatedinthemanner,asshownabove.
Table19-14ErrorCodeTransmitDataMeaningofErrorData62H,62H,62HBaudratemodificationerror.
63H,63H,63HOperationcommanderror.
A1H,A1H,A1HFramingerrorinthereceiveddata.
A3H,A3H,A3HOverrunerrorinthereceiveddata.
A1HIfthedatatobecalculatedconsistsofthefourbytes,thechecksumofthedataisasshownbelow.
B2HA1H+B2H+C3H+D4H=02EAHSUM(HIGH)=02HSUM(LOW)=EAHC3HD4HPage217TMP86FS23UG19.
8.
2CalculationdataThedatausedtocalculatethechecksumislistedinTable19-15.
Table19-15ChecksumCalculationDataOperatingModeCalculationDataDescriptionFlashmemorywritingmodeDataintheentireareaoftheflashmemoryEvenwhenapartoftheflashmemoryiswritten,thechecksumoftheentireflashmemoryarea(1000HtoFFFH)iscalculated.
Thedatalength,address,recordtypeandchecksuminIntelHexformatarenotincludedinthechecksum.
FlashmemorySUMoutputmodeRAMloadermodeRAMdatawritteninthefirstreceivedRAMaddressthroughthelastreceivedRAMaddressThelengthofdata,address,recordtypeandchecksuminIntelHexformatarenotincludedinthechecksum.
ProductIDCodeOutputmode9ththrough18thbytesofthetransferreddataFordetails,referto"19.
11ProductIDCode".
FlashMemoryStatusOutputmode9ththrough12thbytesofthetransferreddataFordetails,referto"19.
12FlashMemoryStatusCode"FlashMemoryErasingmodeAlldataintheerasedareaoftheflashmemory(thewholeorpartoftheflashmemory)Whenthesectoreraseisexecuted,onlytheerasedareaisusedtocalculatethechecksum.
Inthecaseofthechiperase,anentireareaoftheflashmemoryisused.
Page21819.
SerialPROMMode19.
9IntelHexFormat(Binary)TMP86FS23UG19.
9IntelHexFormat(Binary)1.
Afterreceivingthechecksumofadatarecord,thedevicewaitsforthestartmark(3AH":")ofthenextdatarecord.
Afterreceivingthechecksumofadatarecord,thedeviceignoresthedataexcept3AHtransmittedbytheexternalcontroller.
2.
Aftertransmittingthechecksumofendrecord,theexternalcontrollermusttransmitnothing,andwaitforthe2-bytereceivedata(upperandlowerbytesofthechecksum).
3.
IfareceivingerrororIntelHexformaterroroccurs,thedeviceentersthehaltconditionwithoutreturninganerrorcodetotheexternalcontroller.
TheIntelHexformaterroroccursinthefollowingcase:Whentherecordtypeisnot00H,01H,or02HWhenachecksumerroroccursWhenthedatalengthofanextendedrecord(recordtype=02H)isnot02HWhenthedevicereceivesthedatarecordafterreceivinganextendedrecord(recordtype=02H)withextendedaddressof1000Horlarger.
Whenthedatalengthoftheendrecord(recordtype=01H)isnot00H19.
10PasswordsTheconsecutiveeightormore-bytedataintheflashmemoryareacanbespecifiedtothepassword.
TMP86FS23UGcomparesthedatastringspecifiedtothepasswordwiththepasswordstringtransmittedfromtheexternalcontroller.
Theareainwhichpasswordscanbespecifiedislocatedataddresses1000HtoFF9FH.
TheareafromFFA0HtoFFFFHcannotbespecifiedasthepasswordsarea.
IfaddressesfromFFE0HthroughFFFFHarefilledwith"FFH",thepasswordsarenotcomparedbecausetheproductisconsideredasablankproduct.
Eveninthiscase,thepasswordcountstorageaddressesandpasswordcomparisonstartaddressmustbespecified.
Table19-16showsthepasswordsettingintheblankproductandnon-blankproduct.
Note1:WhenaddressesfromFFE0HthroughFFFFHarefilledwith"FFH",theproductisrecognizedasablankproduct.
Note2:Thedataincludingthesameconsecutivedata(threeormorebytes)cannotbeusedasapassword.
(Thiscausesapass-worderrordata.
TMP86FS23UGtransmitsnodataandentersthehaltcondition.
)Note3:*:Don'tcare.
Note4:Whentheaboveconditionisnotmet,apassworderroroccurs.
Ifapassworderroroccurs,thedeviceentersthehaltcon-ditionwithoutreturningtheerrorcode.
Note5:IntheflashmemorywritingmodeorRAMloadermode,theblankproductreceivestheIntelHexformatdataimmediatelyafterreceivingPCSAwithoutreceivingpasswordstrings.
Inthiscase,thesubsequentprocessingisperformedcorrectlybecausetheblankproductignoresthedataexceptthestartmark(3AH":")astheIntelHexformatdata,eveniftheexter-nalcontrollertransmitsthedummypasswordstring.
However,ifthedummypasswordstringcontains"3AH",itisdetectedasthestartmarkerroneously.
Themicrocontrollerentersthehaltmode.
Ifthiscausestheproblem,donottransmitthedummypasswordstrings.
Note6:Intheflashmemoryerasingmode,theexternalcontrollermustnottransmitthepasswordstringfortheblankproduct.
Table19-16PasswordSettingintheBlankProductandNon-BlankProductPasswordBlankProduct(Note1)Non-BlankProductPNSA(Passwordcountstorageaddress)1000H≤PNSA≤FF9FH1000H≤PNSA≤FF9FHPCSA(Passwordcomparisonstartaddress)1000H≤PCSA≤FF9FH1000H≤PCSA≤FFA0-NN(Passwordcount)*8≤NPasswordstringsettingNotrequired(Note5)Required(Note2)Page219TMP86FS23UGFigure19-5PasswordComparison19.
10.
1PasswordStringThepasswordstringtransmittedfromtheexternalcontrolleriscomparedwiththespecifieddataintheflashmemory.
Whenthepasswordstringisnotmatchedtothedataintheflashmemory,thedeviceentersthehaltconditionduetothepassworderror.
19.
10.
2HandlingofPasswordErrorIfapassworderroroccurs,thedeviceentersthehaltcondition.
Inthiscase,resetthedevicetoreactivatetheserialPROMmode.
19.
10.
3PasswordManagementduringProgramDevelopmentIfaprogramismodifiedmanytimesinthedevelopmentstage,confusionmayariseastothepassword.
Therefore,itisrecommendedtouseafixedpasswordintheprogramdevelopmentstage.
Example:SpecifyPNSAtoF000H,andthepasswordstringto8bytesfromaddressF001H(PCSAbecomesF001H.
)PasswordSectioncodeabs=0F000HDB08H:PNSAdefinitionDB"CODE1234":Passwordstringdefinition08H01H02H03H04H05H08HF012HF107HF108HFlashmemoryF109HF10AHF10BHF10CHUARTF0H12HF1H07H01H02H03H04H05H06H07H08HPNSAPCSAPasswordstring06H07HF10DHF10EH"08H"becomestheumberofpasswords8bytesCompareExamplePNSA=F012HPCSA=F107HPasswordstring=01H,02H,03H,04H,05H06H,07H,08HRXDpinPage22019.
SerialPROMMode19.
11ProductIDCodeTMP86FS23UG19.
11ProductIDCodeTheproductIDcodeisthe13-bytedatacontainingthestartaddressandtheendaddressofROM.
Table19-17showstheproductIDcodeformat.
19.
12FlashMemoryStatusCodeTheflashmemorystatuscodeisthe7-bytedataincludingthereadprotectionstatusandthestatusofthedatafromFFE0HtoFFFFH.
Table19-18showstheflashmemorystatuscode.
Table19-17ProductIDCodeFormatDataDescriptionIntheCaseofTMP86FS23UG1stStartMark(3AH)3AH2ndThenumberoftransferdata(10bytesfrom3rdto12thbyte)0AH3rdAddresslength(2bytes)02H4thReserveddata1DH5thReserveddata00H6thReserveddata00H7thReserveddata00H8thROMblockcount01H9thThefirstaddressofROM(Upperbyte)10H10thThefirstaddressofROM(Lowerbyte)00H11thTheendaddressofROM(Upperbyte)FFH12thTheendaddressofROM(Lowerbyte)FFH13thChecksumofthetransferreddata(2'scomplimentforthesumof3rdthrough12thbytes)D2HTable19-18FlashMemoryStatusCodeDataDescriptionIntheCaseofTMP86FS23UG1stStartmark3AH2ndTransferreddatacount(3rdthrough6thbyte)04H3rdStatuscode00Hto03H(Seefigurebelow)4thReserveddata00H5thReserveddata00H6thReserveddata00H7thChecksumofthetransferreddata(2'scomplimentforthesumof3rdthrough6thdata)3rdbyte00H01H02H03Hchecksum00HFFHFEHFDHStatusCode176543210RPENABLANK(InitialValue:000000**)Page221TMP86FS23UGSomeoperationcommandsarelimitedbytheflashmemorystatuscode1.
Ifthereadprotectionisenabled,flashmemorywritingmodecommandandRAMloadermodecommandcannotbeexecuted.
Eraseallflashmemorybeforeexecutingthesecommand.
Note:m:Thecommandcanbeexecuted.
Pass:Thecommandcanbeexecutedwithapassword.
*:Thecommandcannotbeexecuted.
(Afterechoingthecommandbacktotheexternalcontroller,TMP86FS23UGstopsUARTcommunicationandentersthehaltcondition.
)RPENAFlashmemoryreadpro-tectionstatus0:1:Readprotectionisdisabled.
Readprotectionisenabled.
BLANKThestatusfromFFE0HtoFFFFH.
0:1:AlldataisFFHintheareafromFFE0HtoFFFFH.
ThevalueexceptFFHisincludedintheareafromFFE0HtoFFFFH.
RPENABLANKFlashMemoryWritingModeRAMLoaderModeFlashmemorySUMOutputModeProductIDCodeOutputModeFlashMemoryStatusOutputModeFlashMemoryErasingModeReadProtec-tionSettingModeChipEraseSec-torErase00mmmmmm*01PassPassmmmPassPass10**mmmm**11**mmmPass*PassPage22219.
SerialPROMMode19.
13SpecifyingtheErasureAreaTMP86FS23UG19.
13SpecifyingtheErasureAreaIntheflashmemoryerasingmode,theerasureareaoftheflashmemoryisspecifiedbyn2bytedata.
ThestartaddressofanerasureareaisspecifiedbyERASTA,andtheendaddressisspecifiedbyERAEND.
IfERASTAisequaltoorsmallerthanERAEND,thesectorerase(erasurein4kbyteunits)isexecuted.
Executingthesectorerasewhilethereadprotectionisenabledresultsinaninfiniteloop.
IfERASTAislargerthanERAEND,thechiperase(erasureofanentireflashmemoryarea)isexecutedandthereadprotectionisdisabled.
Therefore,executethechiperase(notsectorerase)todisablethereadprotection.
Note:Whenthesectoreraseisexecutedfortheareacontainingnoflashcell,TMP86FS23UGstopstheUARTcommuni-cationandentersthehaltcondition.
19.
14PortInputControlRegisterIntheserialPROMmode,theinputlevelisfixedtotheallportsexceptP11andP10portswithahardwarefeaturetopreventoverlapcurrenttounusedports.
(Allportinputsandperipheralfunctioninputssharedwiththeportsbecomeinvalid.
)Therefore,toaccesstotheflashmemoryintheRAMloadermodewithoutUARTcommunication,portinputsmustbevalid.
Tomakeportinputsvalid,setthepinoftheportinputcontrolregister(SPCR)to"1".
TheSPCRregisterisnotoperatedintheMCUmode.
ErasureAreaSpecificationData(n2bytedata)76543210ERASTAERAENDERASTAThestartaddressoftheerasurearea0000:0001:0010:0011:0100:0101:0110:0111:1000:1001:1010:1011:1100:1101:1110:1111:from0000Hfrom1000Hfrom2000Hfrom3000Hfrom4000Hfrom5000Hfrom6000Hfrom7000Hfrom8000Hfrom9000HfromA000HfromB000HfromC000HfromD000HfromE000HfromF000HERAENDTheendaddressoftheerasurearea0000:0001:0010:0011:0100:0101:0110:0111:1000:1001:1010:1011:1100:1101:1110:1111:to0FFFHto1FFFHto2FFFHto3FFFHto4FFFHto5FFFHto6FFFHto7FFFHto8FFFHto9FFFHtoAFFFHtoBFFFHtoCFFFHtoDFFFHtoEFFFHtoFFFFHPage223TMP86FS23UGNote1:TheSPCRregistercanbereadorwrittenonlyintheserialPROMmode.
WhenthewriteinstructionisexecutedtotheSPCRregisterintheMCUmode,theportinputcontrolcannotbeperformed.
WhenthereadinstructionisexecutedfortheSPCRregisterintheMCUmode,readdataofbit7to1areunstable.
Note2:AllI/OportsexceptP11andP10portsarecontrolledbytheSPCRregister.
PortInputControlRegisterSPCR(0FEAH)76543210PIN(Initialvalue:0)PINPortinputcontrolintheserialPROMmode0:Invalidportinputs(Theinputlevelisfixedwithahardwarefeature.
)1:ValidportinputsR/WPage22419.
SerialPROMMode19.
15FlowchartTMP86FS23UG19.
15FlowchartSTARTSetupReceiveUARTdataReceivedata=5AHAdjustthebaudrate(Adjustthesourceclockto9600bps)NoYesTransmitUARTdata(Transmitdata=5AH)ReceiveUARTdataModifythebaudratebasedonthereceivedataReceivedata=30H(Flashmemorywritingmode)Receivedata=60H(RAMloadermode)ReceiveUARTdata(IntelHexformat)TransmitUARTdata(Checksumofanentirearea)ReceiveUARTdataTransmitUARTdata(Transmitdata=60H)ReceiveUARTdata(IntelHexformat)JumptothestartaddressofRAMprogramTransmitUARTdata(Checksumofanentirearea)Receivedata=C0H(ProductIDcodeoutputmode)TransmitUARTdata(Transmitdata=C0H)FlashmemorywriteprocessRAMwriteprocessTransmitUARTdata(ProductIDcode)TransmitUARTdata(Echobackthebaudratemodificationdata)Verifythepassword(Comparethereceivedataandflashmemorydata)ReadprotectioncheckProtectiondisabledReadprotectioncheckProtectiondisabledInfiniteloopInfiniteloopNGProtectionEnableNGReceivedata=C3H(Flashmemorystatusoutputmode)TransmitUARTdata(Transmitdata=C3H)Receivedata=F0H(Flashmemoryerasingmode)TransmitUARTdata(Transmitdata=F0H)InfiniteloopNGChiperase(Eraseonentirearea)TransmitUARTdata(Checksumofanentirearea)Receivedata=FAH(Readprotectionsettingmode)TransmitUARTdata(Transmitdata=FAH)ReadprotectionsettingReadprotectioncheckBlankproductcheckInfiniteloopNGBlankproductcheckBlankproductcheckNon-blankproductNon-blankproductOKBlankproductOKBlankproductcheckNon-blankproductOKOKBlankproductcheckNon-blankproductBlankproductProtectionEnableBlankproductDisablereadprotectionBlankproductReceiveUARTdataReceivedataSectorerase(Blockerase)Upper4bitsx1000HtoLower4bitsx1000HTransmitUARTdata(Checksumoftheerasedarea)Upper4bits>Lower4bitsTransmitUARTdata(Transmitdata=30H)TransmitUARTdata(Transmitdata=90H)Receivedata=90H(Flashmemorysumoutputmode)Verifythepassword(Comparethereceivedataandflashmemorydata)TransmitUARTdata(Checksum)Verifythepassword(Comparethereceivedataandflashmemorydata)Verifythepassword(Comparethereceivedataandflashmemorydata)TransmitUARTdata(Statusofthereadprotectionandblankproduct)TransmitUARTdata(Transmitdata=FBH)ReadprotectioncheckUpper4bits16UARTTimingTable19-19UARTTiming-1(VDD=4.
5to5.
5V,fc=2to16MHz,Topr=-10to40°C)ParameterSymbolClockFrequency(fc)MinimumRequiredTimeAtfc=2MHzAtfc=16MHzTimefrommatchingdatareceptiontotheechobackCMeb1Approx.
930465s58.
1sTimefrombaudratemodificationdatareceptiontotheechobackCMeb2Approx.
980490s61.
3sTimefromoperationcommandreceptiontotheechobackCMeb3Approx.
800400s50sChecksumcalculationtimeCKsmApprox.
78645003.
93s491.
5sErasuretimeofanentireflashmemoryCEall-30ms30msErasuretimeforasectorofaflashmemory(in4-kbyteunits)CEsec-15ms15msTable19-20UARTTiming-2(VDD=4.
5to5.
5V,fc=2to16MHz,Topr=-10to40°C)ParameterSymbolClockFrequency(fc)MinimumRequiredTimeAtfc=2MHzAtfc=16MHzTimefromtheresetreleasetotheacceptanceofstartbitofRXDpinRXsup21001.
05ms131.
3msMatchingdatatransmissionintervalCMtr12850014.
2ms1.
78msTimefromtheechobackofmatchingdatatotheacceptanceofbaudratemodificationdataCMtr2380190s23.
8sTimefromtheechobackofbaudratemodificationdatatotheacceptanceofanoperationcommandCMtr3650325s40.
6sTimefromtheechobackofoperationcommandtotheacceptanceofpasswordcountstorageaddresses(Upperbyte)CMtr4800400s50sRESETpinRXDpinRXsup(5AH)CMeb1(5AH)CMtr2(28H)(28H)CMeb2CMtr3(30H)(30H)CMeb3CMtr4TXDpinRXDpinTXDpin(5AH)(5AH)(5AH)CMtr1Page22619.
SerialPROMMode19.
16UARTTimingTMP86FS23UGPage227TMP86FS23UG20.
Input/OutputCircuitry20.
1ControlPinsTheinput/outputcircuitriesoftheTMP86FS23UGcontrolpinsareshownbelow.
Note:TheTESTpinoftheTMP86FS23doesnothaveapull-downresistor.
FixtheTESTpinatlow-levelinMCUmode.
ControlPinI/OInput/OutputCircuitryRemarksXINXOUTInputOutputResonatorconnectingpins(high-frequency)Rf=1.
2M(typ.
)RO=0.
5k(typ.
)XTINXTOUTInputOutputResonatorconnectingpins(Low-frequency)Rf=6M(typ.
)RO=220k(typ.
)RESETInputHysteresisinputPull-upresistorRIN=220k(typ.
)TESTInputWithoutpull-downresistorR=1k(typ.
)FixtheTESTpinatlow-levelinMCUmode.
fcRfROOsc.
enableXINXOUTVDDVDDfsRfROOsc.
enableXTINXTOUTXTENVDDVDDVDDAddress-trap-resetWatchdog-timerSystem-clock-resetRINVDDRD1Page22820.
Input/OutputCircuitry20.
2Input/OutputPortsTMP86FS23UG20.
2Input/OutputPortsPortI/OInput/OutputCircuitryRemarksP1I/OTri-stateI/OHysteresisinputR=100(typ.
)LCDsegmentoutputP5P7P8I/OTri-stateI/OR=100(typ.
)LCDsegmentoutputP2I/OSinkopendrainoutputHysteresisinputR=100(typ.
)P34toP30I/OSinkopendrainoutputorC-MOSoutputHysteresisinputHighcurrentoutput(Nch)(OnlyP33,P34port)R=100(typ.
)P37toP35OutputSinkopendrainoutputHighcurrentoutput(Nch)P6I/OTri-stateI/OHysteresisinputAINinputR=100(typ.
)Initial"High-Z"DisableSEGoutputDataoutputPininputVDDRInitial"High-Z"DisableSEGoutputDataoutputPininputVDDRInitial"High-Z"DataoutputPininputInputfromoutputlatchVDDRInitial"High-Z"InputfromoutputlatchPchcontrolDataoutputPininputVDDRInitial"High-Z"DataoutputInputfromoutputlatchInitial"High-Z"DisableAINDataoutputPininputVDDRPage229TMP86FS23UG21.
ElectricalCharacteristics21.
1AbsoluteMaximumRatingsTheabsolutemaximumratingsareratedvalueswhichmustnotbeexceededduringoperation,evenforaninstant.
Anyoneoftheratingsmustnotbeexceeded.
Ifanyabsolutemaximumratingisexceeded,adevicemaybreakdownoritsperformancemaybedegraded,causingittocatchfireorexploderesultingininjurytotheuser.
Thus,whendesigningproductswhichincludethisdevice,ensurethatnoabsolutemaximumratingvaluewilleverbeexceeded.
(VSS=0V)ParameterSymbolPinsRatingsUnitSupplyvoltageVDD0.
3to6.
5VInputvoltageVIN0.
3toVDD+0.
3OutputvoltageVOUT0.
3toVDD+0.
3Outputcurrent(Per1pin)IOUT1P1,P30toP34,P5,P6,P7,P8port1.
8mAIOUT2P1,P2,P30toP32,P5,P6,P7,P8port3.
2IOUT3P33toP37port30Outputcurrent(Total)ΣIOUT1P1,P30toP34,P5,P6,P7,P8port30ΣIOUT2P1,P2,P30toP32,P5,P6,P7,P8port60ΣIOUT3P33toP37port80Powerdissipation[Topr=85°C]PD350mWSolderingtemperature(Time)Tsld260(10s)°CStoragetemperatureTstg55to125OperatingtemperatureTopr40to85Page23021.
ElectricalCharacteristics21.
2RecommendedOperatingConditionTMP86FS23UG21.
2RecommendedOperatingConditionTherecommendedoperatingconditionsforadeviceareoperatingconditionsunderwhichitcanbeguaranteedthatthedevicewilloperateasspecified.
Ifthedeviceisusedunderoperatingconditionsotherthantherecommendedoperatingconditions(supplyvoltage,operatingtemperaturerange,specifiedAC/DCvaluesetc.
),malfunctionmayoccur.
Thus,whendesigningproductswhichincludethisdevice,ensurethattherecommendedoperatingconditionsforthedevicearealwaysadheredto.
21.
2.
1WhenProgrammingFlashmemoryinMCUmode21.
2.
2WhenNotProgrammingFlashMemoryinMCUModeNote:WhenthesupplyvoltageVDDislessthan3.
0V,theoperatingtemperatureToprmustbeinarangeof-20to85°C.
(VSS=0V,Topr=10to40°C)ParameterSymbolPinsRatingsMinMaxUnitSupplyvoltageVDDNORMAL1,2modes4.
55.
5VInputhighlevelVIH1ExcepthysteresisinputVDD≥4.
5VVDD*0.
70VDDVIH2HysteresisinputVDD*0.
75InputlowlevelVIL1ExcepthysteresisinputVDD≥4.
5V0VDD*0.
30VIL2HysteresisinputVDD*0.
25ClockfrequencyfcXIN,XOUT1.
016.
0MHz(VSS=0V,Topr=40to85°C)ParameterSymbolPinsRatingsMinMaxUnitSupplyvoltageVDDfc=16MHzNORMAL1,2modesIDLE0,1,2modes3.
55.
5Vfc=8MHzNORMAL1,2modesIDLE0,1,2modes2.
7(Note1)fs=32.
768kHzSLOW1,2modesSLEEP0,1,2modesSTOPmodeInputhighlevelVIH1ExcepthysteresisinputVDD≥4.
5VVDD*0.
70VDDVIH2HysteresisinputVDD*0.
75VIH3VDD<4.
5VVDD*0.
90InputlowlevelVIL1ExcepthysteresisinputVDD≥4.
5V0VDD*0.
30VIL2HysteresisinputVDD*0.
25VIL3VDD<4.
5VVDD*0.
10ClockfrequencyfcXIN,XOUTVDD=2.
7to5.
5V1.
08.
0MHzVDD=3.
5to5.
5V16.
0fsXTIN,XTOUTVDD=2.
7to5.
5V30.
034.
0kHzPage231TMP86FS23UG21.
2.
3SerialPROMmode(VSS=0V,Topr=10to40°C)ParameterSymbolPinsConditionMinMaxUnitSupplyvoltageVDDNORMAL1,2modes4.
55.
5VInputhighvoltageVIH1ExcepthysteresisinputVDD≥4.
5VVDD*0.
70VDDVIH2HysteresisinputVDD*0.
75InputlowvoltageVIL1ExcepthysteresisinputVDD≥4.
5V0VDD*0.
30VIL2HysteresisinputVDD*0.
25ClockfrequencyfcXIN,XOUT2.
016.
0MHzPage23221.
ElectricalCharacteristics21.
3DCCharacteristicsTMP86FS23UG21.
3DCCharacteristicsNote1:TypicalvaluesshowthoseatTopr=25°C,VDD=5VNote2:Inputcurrent(IIN1,IIN2);Thecurrentthroughpull-uporpull-downresistorisnotincluded.
Note3:IDDdoesnotincludeIREFcurrent.
Note4:ThesupplycurrentsofSLOW2andSLEEP2modesareequivalenttoIDLE0,1,2.
Note5:OutputresistorsROSandROCindicate"ON"whenswitchinglevels.
Note6:VO2/3indicatestheoutputvoltageatthe2/3levelwhenoperatinginthe1/4or1/3dutymode.
Note7:VO1/2indicatestheoutputvoltageatthe1/2levelwhenoperatinginthe1/2dutyorstaticmode.
Note8:VO1/3indicatestheoutputvoltageatthe1/3levelwhenoperatinginthe1/4or1/3dutymode.
Note9:WhenusingLCD,itisnecessarytoconsidervaluesofROS1/2andROC1/2.
Note10:Whenaprogramisexecutingintheflashmemoryorwhendataisbeingreadfromtheflashmemory,theflashmemoryoperatesinanintermittentmanner,causingpeakcurrentsintheoperationcurrent,asshowninFigure21-1.
(VSS=0V,Topr=-40to85°C)ParameterSymbolPinsConditionMinTyp.
MaxUnitHysteresisvoltageVHSHysteresisinput–0.
9–VInputcurrentIIN1TESTVDD=5.
5V,VIN=5.
5V/0V––±2AIIN2Sinkopendrain,Tri-stateIIN3RESET,STOPInputresistanceRIN2RESETpull-up100220450kOutputleakagecurrentILOSinkopendrain,Tri-stateVDD=5.
5V,VOUT=5.
5V/0V––±2AOutputhighvoltageVOHC-MOS,Tri–stateportVDD=4.
5V,IOH=–0.
7mA4.
1––VOutputlowvoltageVOLExceptXOUTandP3portVDD=4.
5V,IOL=1.
6mA––0.
4OutputlowcurrentIOLHighcurrentport(P33toP37port)VDD=4.
5V,VOL=1.
0V–20–mASupplycurrentinNORMAL1,2modesIDDVDD=5.
5VVIN=5.
3V/0.
2Vfc=16MHzfs=32.
768kHzWhenaprogramoperatesonflashmemory(Note10,11)–12.
620mASupplycurrentinIDLE0,1,2modes–610SupplycurrentinSLOW1modeVDD=3.
0VVIN=2.
8V/0.
2Vfs=32.
768kHzWhenaprogramoperatesonflashmemory(Note10,11)–40260AWhenaprogramoperatesonRAM–1825SupplycurrentinSLEEP1mode–1018SupplycurrentinSLEEP0mode–816SupplycurrentinSTOPmodeVDD=5.
5VVIN=5.
3V/0.
2V–0.
510SegmentoutputlowresistanceROS1SEGpin–20–kCommonoutputlowresistanceROC1COMpin20SegmentoutputhighresistanceROS2SEGpin200CommonoutputhighresistanceROC2COMpin200Segment/commonoutputvoltageVO2/3SEG/COMpinVDD=5.
0VVLC=2.
0V3.
8–4.
2VVO1/23.
33.
7VO1/32.
83.
2Page233TMP86FS23UGInthiscase,thesupplycurrentIDD(inNORMAL1,NORMAL2andSLOW1modes)isdefinedasthesumoftheaveragepeakcurrentandMCUcurrent.
Note11:Whendesigningthepowersupply,makesurethatpeakcurrentscanbesupplied.
InSLOW1mode,thedifferencebetweenthepeakcurrentandtheaveragecurrentbecomeslarge.
Figure21-1IntermittentOperationofFlashMemorynProgramcoutner(PC)n+1n+2n+31machinecycle(4/fcor4/fs)MCUcurrentI[mA]DDP-PTyp.
currentMomentaryflashcurrentMax.
currentSumofaveragemomentaryflashcurrentandMCUcurrentPage23421.
ElectricalCharacteristics21.
4ADConversionCharacteristicsTMP86FS23UG21.
4ADConversionCharacteristicsNote1:Thetotalerrorincludesallerrorsexceptaquantizationerror,andisdefinedasamaximumdeviationfromtheidealcon-versionline.
Note2:Conversiontimeisdifferentinrecommendedvaluebypowersupplyvoltage.
Aboutconversiontime,pleasereferto"RegisterFraming".
Note3:PleaseuseinputvoltagetoAINinputPininlimitofVAREFtoVSS.
Whenvoltageofrangeoutsideisinput,conversionvaluebecomesunsettledandgivesaffecttootherchannelconversionvalue.
Note4:Analogreferencevoltagerange:VAREF=VAREFVSSNote5:TheAVDDpinshouldbefixedontheVDDleveleventhoughADconverterisnotused.
Note6:WhenthesupplyvoltageVDDislessthan3.
0V,theoperatingtemperatureToprmustbeinarangeof20to85°C.
(VSS=0.
0V,4.
5V≤VDD≤5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitAnalogreferencevoltageVAREFAVDD1.
0AVDDVPowersupplyvoltageofanalogcontrolcircuit(Note5)AVDDVDDAnalogreferencevoltagerange(Note4)VAREF3.
5AnaloginputvoltageVAINVSSVAREFPowersupplycurrentofanalogreferencevoltageIREFVDD=AVDD=VAREF=5.
5VVSS=0.
0V0.
61.
0mANonlinearityerrorVDD=AVDD=5.
0VVSS=0.
0VVAREF=5.
0V±2LSBZeropointerror±2Fullscaleerror±2Totalerror±2(VSS=0.
0V,2.
7V≤VDD<4.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitAnalogreferencevoltageVAREFAVDD1.
0AVDDVPowersupplyvoltageofanalogcontrolcircuit(Note5)AVDDVDDAnalogreferencevoltagerange(Note4)VAREF2.
5AnaloginputvoltageVAINVSSVAREFPowersupplycurrentofanalogreferencevoltageIREFVDD=AVDD=VAREF=4.
5VVSS=0.
0V0.
50.
8mANonlinearityerrorVDD=AVDD=2.
7VVSS=0.
0VVAREF=2.
7V±2LSBZeropointerror±2Fullscaleerror±2Totalerror±2Page235TMP86FS23UG21.
5ACCharacteristicsNote:WhenthesupplyvoltageVDDislessthan3.
0V,theoperatingtemperatureToprmustbeinarangeof20to85°C.
21.
6TimerCounter1input(ECIN)Characteristics21.
7FlashCharacteristics21.
7.
1Write/RetentionCharacteristics(VSS=0V,VDD=3.
5to5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitMachinecycletimetcyNORMAL1,2mode0.
254sIDLE1,2modeSLOW1,2mode117.
6133.
3SLEEP1,2modeHighlevelclockpulsewidthtWCHForexternalclockoperation(XINinput)fc=16MHz31.
25nsLowlevelclockpulsewidthtWCLHighlevelclockpulsewidthtWCHForexternalclockoperation(XTINinput)fs=32.
768kHz15.
26sLowlevelclockpulsewidthtWCL(VSS=0V,VDD=2.
7to5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitMachinecycletimetcyNORMAL1,2mode0.
54sIDLE1,2modeSLOW1,2mode117.
6133.
3SLEEP1,2modeHighlevelclockpulsewidthtWCHForexternalclockoperation(XINinput)fc=8MHz62.
5nsLowlevelclockpulsewidthtWCLHighlevelclockpulsewidthtWCHForexternalclockoperation(XTINinput)fs=32.
768kHz15.
26sLowlevelclockpulsewidthtWCL(VSS=0V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitTC1input(ECINinput)tTC1FrequencymeasurementmodeVDD=3.
5to5.
5VSingleedgecount16MHzBothedgecountFrequencymeasurementmodeVDD=2.
7to5.
5VSingleedgecount8Bothedgecount(VSS=0V)ParameteConditionMinMax.
Typ.
UnitNumberofguaranteedwritestoflashmemoryVSS=0V,Topr=10to40°C100TimesPage23621.
ElectricalCharacteristics21.
8RecommendedOscillatingConditionsTMP86FS23UG21.
8RecommendedOscillatingConditionsNote1:Toensurestableoscillation,theresonatorposition,loadcapacitance,etc.
mustbeappropriate.
Becausethesefactorsaregreatlyaffectedbyboardpatterns,pleasebesuretoevaluateoperationontheboardonwhichthedevicewillactuallybemounted.
Note2:FortheresonatorstobeusedwithToshibamicrocontrollers,werecommendceramicresonatorsmanufacturedbyMurataManufacturingCo.
,Ltd.
Fordetails,pleasevisitthewebsiteofMurataatthefollowingURL:http://www.
murata.
com21.
9HandlingPrecaution-Thesolderabilitytestconditionsforlead-freeproducts(indicatedbythesuffixGinproductname)areshownbelow.
1.
WhenusingtheSn-37PbsolderbathSolderbathtemperature=230°CDippingtime=5secondsNumberoftimes=onceR-typefluxused2.
WhenusingtheSn-3.
0Ag-0.
5CusolderbathSolderbathtemperature=245°CDippingtime=5secondsNumberoftimes=onceR-typefluxusedNote:Thepasscriteronoftheabovetestisasfollows:Solderabilityrateuntilforming≥95%-Whenusingthedevice(oscillator)inplacesexposedtohighelectricfieldssuchascathode-raytubes,werecommendelectricallyshieldingthepackageinordertomaintainnormaloperatingcondition.
(2)Low-frequencyOscillation(1)High-frequencyOscillationXINXOUTC2C1XTINXTOUTC2C1Page237TMP86FS23UG22.
PackageDimensionP-LQFP64-1010-0.
50DUnit:mmPage23822.
PackageDimensionTMP86FS23UGThisisatechnicaldocumentthatdescribestheoperatingfunctionsandelectricalspecificationsofthe8-bitmicrocontrollerseriesTLCS-870/C(LSI).
Toshibaprovidesavarietyofdevelopmenttoolsandbasicsoftwaretoenableefficientsoftwaredevelopment.
Thesedevelopmenttoolshavespecificationsthatsupportadvancesinmicrocomputerhardware(LSI)andcanbeusedextensively.
Boththehardwareandsoftwarearesupportedcontinuouslywithversionupdates.
TherecentadvancesinCMOSLSIproductiontechnologyhavebeenphenomenalandmicrocomputersystemsforLSIdesignareconstantlybeingimproved.
Theproductsdescribedinthisdocumentmayalsoberevisedinthefuture.
Besuretocheckthelatestspecificationsbeforeusing.
Toshibaisdevelopinghighlyintegrated,high-performancemicrocomputersusingadvancedMOSproductiontechnologyandespeciallywellprovenCMOStechnology.
Wearepreparedtomeettherequestsforcustompackagingforavarietyofapplicationareas.
Weareconfidentthatourproductscansatisfyyourapplicationneedsnowandinthefuture.