circuitsncsetting

8BitMicrocontrollerTLCS-870/CSeriesTMP86CS28FGTheinformationcontainedhereinissubjecttochangewithoutnotice.
021023_DTOSHIBAiscontinuallyworkingtoimprovethequalityandreliabilityofitsproducts.
Nevertheless,semiconductordevicesingeneralcanmalfunctionorfailduetotheirinherentelectricalsensitivityandvulnerabilitytophysicalstress.
Itistheresponsibilityofthebuyer,whenutilizingTOSHIBAproducts,tocomplywiththestandardsofsafetyinmakingasafedesignfortheentiresystem,andtoavoidsituationsinwhichamalfunctionorfailureofsuchTOSHIBAproductscouldcauselossofhumanlife,bodilyinjuryordamagetoproperty.
Indevelopingyourdesigns,pleaseensurethatTOSHIBAproductsareusedwithinspecifiedoperatingrangesassetforthinthemostrecentTOSHIBAproductsspecifications.
Also,pleasekeepinmindtheprecautionsandconditionssetforthinthe"HandlingGuideforSemiconductorDevices,"or"TOSHIBASemiconductorReliabilityHandbook"etc.
021023_ATheTOSHIBAproductslistedinthisdocumentareintendedforusageingeneralelectronicsapplications(computer,personalequipment,officeequipment,measuringequipment,industrialrobotics,domesticappliances,etc.
).
TheseTOSHIBAproductsareneitherintendednorwarrantedforusageinequipmentthatrequiresextraordinarilyhighqualityand/orreliabilityoramalfunctionorfailureofwhichmaycauselossofhumanlifeorbodilyinjury("UnintendedUsage").
UnintendedUsageincludeatomicenergycontrolinstruments,airplaneorspaceshipinstruments,transportationinstruments,trafficsignalinstruments,combustioncontrolinstruments,medicalinstruments,alltypesofsafetydevices,etc.
UnintendedUsageofTOSHIBAproductslistedinthisdocumentshallbemadeatthecustomer'sownrisk.
021023_BTheproductsdescribedinthisdocumentshallnotbeusedorembeddedtoanydownstreamproductsofwhichmanufacture,useand/orsaleareprohibitedunderanyapplicablelawsandregulations.
060106_QTheinformationcontainedhereinispresentedonlyasaguidefortheapplicationsofourproducts.
NoresponsibilityisassumedbyTOSHIBAforanyinfringementsofpatentsorotherrightsofthethirdpartieswhichmayresultfromitsuse.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentsorotherrightsofTOSHIBAorthethirdparties.
070122_CTheproductsdescribedinthisdocumentaresubjecttoforeignexchangeandforeigntradecontrollaws.
060925_EForadiscussionofhowthereliabilityofmicrocontrollerscanbepredicted,pleaserefertoSection1.
3ofthechapterentitledQualityandReliabilityAssurance/HandlingPrecautions.
030619_S2007TOSHIBACORPORATIONAllRightsReservedRevisionHistoryDateRevision2006/12/51FirstRelease2006/12/142ContentsRevised2007/7/213ContentsRevised2008/8/294ContentsRevisedCautioninSettingtheUARTNoiseRejectionTimeWhenUARTisused,settingsofRXDNCarelimiteddependingonthetransferclockspecifiedbyBRG.
Thecom-bination"O"isavailablebutpleasedonotselectthecombination"–".
Thetransferclockgeneratedbytimer/counterinterruptiscalculatedbythefollowingequation:Transferclock[Hz]=Timer/countersourceclock[Hz]÷TTREGsetvalueBRGsettingTransferclock[Hz]RXDNCsetting00(Nonoiserejection)01(Rejectpulsesshorterthan31/fc[s]asnoise)10(Rejectpulsesshorterthan63/fc[s]asnoise)11(Rejectpulsesshorterthan127/fc[s]asnoise)000fc/13OOO–110(Whenthetransferclockgen-eratedbytimer/counterinter-ruptisthesameastherightsidecolumn)fc/8O–––fc/16OO––fc/32OOO–ThesettingexcepttheaboveOOOOiTableofContentsTMP86CS28FG1.
1Features11.
2PinAssignment31.
3BlockDiagram41.
4PinNamesandFunctions52.
OperationalDescription2.
1CPUCoreFunctions92.
1.
1MemoryAddressMap.
92.
1.
2ProgramMemory(MaskROM)92.
1.
3DataMemory(RAM)92.
2SystemClockController102.
2.
1ClockGenerator.
102.
2.
2TimingGenerator.
122.
2.
2.
1Configurationoftiminggenerator2.
2.
2.
2Machinecycle2.
2.
3OperationModeControlCircuit132.
2.
3.
1Single-clockmode2.
2.
3.
2Dual-clockmode2.
2.
3.
3STOPmode2.
2.
4OperatingModeControl182.
2.
4.
1STOPmode2.
2.
4.
2IDLE1/2modeandSLEEP1/2mode2.
2.
4.
3IDLE0andSLEEP0modes(IDLE0,SLEEP0)2.
2.
4.
4SLOWmode2.
3ResetCircuit312.
3.
1ExternalResetInput312.
3.
2Addresstrapreset322.
3.
3Watchdogtimerreset.
322.
3.
4Systemclockreset.
323.
InterruptControlCircuit3.
1Interruptlatches(IL30toIL2)363.
2Interruptenableregister(EIR)363.
2.
1Interruptmasterenableflag(IMF)363.
2.
2Individualinterruptenableflags(EF30toEF4)37Note3:383.
3InterruptSequence393.
3.
1Interruptacceptanceprocessingispackagedasfollows.
393.
3.
2Saving/restoringgeneral-purposeregisters.
403.
3.
2.
1UsingPUSHandPOPinstructions3.
3.
2.
2Usingdatatransferinstructions3.
3.
3Interruptreturn413.
4SoftwareInterrupt(INTSW)423.
4.
1Addresserrordetection423.
4.
2Debugging42ii3.
5UndefinedInstructionInterrupt(INTUNDEF)423.
6AddressTrapInterrupt(INTATRAP)423.
7ExternalInterrupts434.
SpecialFunctionRegister(SFR)4.
1SFR454.
2DBR475.
I/OPorts5.
1PortP0(P00toP02)535.
2PortP1(P10toP17)555.
3PortP2(P20toP22)585.
4PortP3(P30toP37)595.
5PortP4(P40toP47)615.
6PortP5(P50toP57)635.
7PortP6(P60toP67)655.
8PortP7(P70toP77)675.
9PortP8(P80toP87)696.
WatchdogTimer(WDT)6.
1WatchdogTimerConfiguration716.
2WatchdogTimerControl726.
2.
1MalfunctionDetectionMethodsUsingtheWatchdogTimer.
726.
2.
2WatchdogTimerEnable736.
2.
3WatchdogTimerDisable746.
2.
4WatchdogTimerInterrupt(INTWDT)746.
2.
5WatchdogTimerReset756.
3AddressTrap766.
3.
1SelectionofAddressTrapinInternalRAM(ATAS)766.
3.
2SelectionofOperationatAddressTrap(ATOUT)766.
3.
3AddressTrapInterrupt(INTATRAP)766.
3.
4AddressTrapReset.
777.
TimeBaseTimer(TBT)7.
1TimeBaseTimer797.
1.
1Configuration797.
1.
2Control797.
1.
3Function807.
2DividerOutput(DVO)817.
2.
1Configuration817.
2.
2Control818.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter1083iii8.
1.
1Configuration838.
1.
2TimerCounterControl848.
1.
3Function858.
1.
3.
1Timermode8.
1.
3.
2ExternalTriggerTimerMode8.
1.
3.
3EventCounterMode8.
1.
3.
4WindowMode8.
1.
3.
5PulseWidthMeasurementMode8.
1.
3.
6ProgrammablePulseGenerate(PPG)OutputMode8.
216-BitTimerCounter11978.
2.
1Configuration978.
2.
2TimerCounterControl988.
2.
3Function998.
2.
3.
1Timermode8.
2.
3.
2ExternalTriggerTimerMode8.
2.
3.
3EventCounterMode8.
2.
3.
4WindowMode8.
2.
3.
5PulseWidthMeasurementMode8.
2.
3.
6ProgrammablePulseGenerate(PPG)OutputMode9.
8-BitTimerCounter(TC3,TC4)9.
1Configuration1119.
2TimerCounterControl1129.
3Function.
1179.
3.
18-BitTimerMode(TC3and4)1179.
3.
28-BitEventCounterMode(TC3,4)1189.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC3,4)1189.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC3,4)1219.
3.
516-BitTimerMode(TC3and4)1239.
3.
616-BitEventCounterMode(TC3and4)1249.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC3and4)1249.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC3and4)1279.
3.
9Warm-UpCounterMode.
1299.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)9.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)10.
8-BitTimerCounter(TC5,TC6)10.
1Configuration13110.
2TimerCounterControl13210.
3Function.
13710.
3.
18-BitTimerMode(TC5and6)13710.
3.
28-BitEventCounterMode(TC5,6)13810.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC5,6)13810.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC5,6)14110.
3.
516-BitTimerMode(TC5and6)14310.
3.
616-BitEventCounterMode(TC5and6)14410.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC5and6)14410.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC5and6)14710.
3.
9Warm-UpCounterMode.
14910.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)10.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)11.
SynchronousSerialInterface(SIO)11.
1Configuration151iv11.
2Control15211.
3Serialclock15311.
3.
1Clocksource15311.
3.
1.
1Internalclock11.
3.
1.
2Externalclock11.
3.
2Shiftedge.
15511.
3.
2.
1Leadingedge11.
3.
2.
2Trailingedge11.
4Numberofbitstotransfer15511.
5Numberofwordstotransfer15511.
6TransferMode15611.
6.
14-bitand8-bittransfermodes.
15611.
6.
24-bitand8-bitreceivemodes15811.
6.
38-bittransfer/receivemode15912.
AsynchronousSerialinterface(UART1)12.
1Configuration16112.
2Control16212.
3TransferDataFormat16412.
4TransferRate.
16512.
5DataSamplingMethod16512.
6STOPBitLength16612.
7Parity16612.
8Transmit/ReceiveOperation16612.
8.
1DataTransmitOperation16612.
8.
2DataReceiveOperation16612.
9StatusFlag16712.
9.
1ParityError.
16712.
9.
2FramingError.
16712.
9.
3OverrunError.
16712.
9.
4ReceiveDataBufferFull.
16812.
9.
5TransmitDataBufferEmpty16812.
9.
6TransmitEndFlag16913.
AsynchronousSerialinterface(UART0)13.
1Configuration17113.
2Control17213.
3TransferDataFormat17413.
4TransferRate.
17513.
5DataSamplingMethod17513.
6STOPBitLength17613.
7Parity17613.
8Transmit/ReceiveOperation17613.
8.
1DataTransmitOperation17613.
8.
2DataReceiveOperation17613.
9StatusFlag17713.
9.
1ParityError.
17713.
9.
2FramingError.
17713.
9.
3OverrunError.
17713.
9.
4ReceiveDataBufferFull.
17813.
9.
5TransmitDataBufferEmpty17813.
9.
6TransmitEndFlag179v14.
10-bitADConverter(ADC)14.
1Configuration18114.
2Registerconfiguration18214.
3Function.
18514.
3.
1SoftwareStartMode18514.
3.
2RepeatMode18514.
3.
3RegisterSetting18614.
4STOP/SLOWModesduringADConversion18714.
5AnalogInputVoltageandADConversionResult18814.
6PrecautionsaboutADConverter.
18914.
6.
1Analoginputpinvoltagerange18914.
6.
2Analoginputsharedpins18914.
6.
3NoiseCountermeasure.
18915.
Key-onWakeup(KWU)15.
1Configuration19115.
2Control19115.
3Function.
19116.
LCDDriver16.
1Configuration19316.
2Control19416.
2.
1LCDdrivingmethods19516.
2.
2Framefrequency.
19616.
2.
3DrivingmethodforLCDdriver19716.
2.
3.
1Whenusingtheboostercircuit(LCDCR="1")16.
2.
3.
2Whenusinganexternalresistordivider(LCDCR="0")16.
3LCDDisplayOperation19916.
3.
1Displaydatasetting19916.
3.
2Blanking20016.
4ControlMethodofLCDDriver20116.
4.
1Initialsetting.
20116.
4.
2Storeofdisplaydata20116.
4.
3ExampleofLCDdriveoutput.
20417.
Input/OutputCircuitry17.
1ControlPins20917.
2Input/OutputPorts21018.
ElectricalCharacteristics18.
1AbsoluteMaximumRatings.
21118.
2OperatingCondition.
21218.
221218.
3DCCharacteristics.
21318.
4ADConversionCharacteristics214vi18.
5ACCharacteristics.
21518.
6RecommendedOscillatingConditions.
21618.
7HandlingPrecaution21619.
PackageDimensionsThisisatechnicaldocumentthatdescribestheoperatingfunctionsandelectricalspecificationsofthe8-bitmicrocontrollerseriesTLCS-870/C(LSI).
Page1TMP86CS28FGCMOS8-BitMicrocontrollerTheinformationcontainedhereinissubjecttochangewithoutnotice.
021023_DTOSHIBAiscontinuallyworkingtoimprovethequalityandreliabilityofitsproducts.
Nevertheless,semiconductordevicesingeneralcanmalfunctionorfailduetotheirinherentelectricalsensitivityandvulnerabilitytophysicalstress.
Itistheresponsibilityofthebuyer,whenutilizingTOSHIBAproducts,tocomplywiththestandardsofsafetyinmakingasafedesignfortheentiresystem,andtoavoidsituationsinwhichamalfunctionorfailureofsuchTOSHIBAproductscouldcauselossofhumanlife,bodilyinjuryordamagetoproperty.
Indevelopingyourdesigns,pleaseensurethatTOSHIBAproductsareusedwithinspecifiedoperatingrangesassetforthinthemostrecentTOSHIBAproductsspecifications.
Also,pleasekeepinmindtheprecautionsandconditionssetforthinthe"HandlingGuideforSemiconductorDevices,"or"TOSHIBASemiconductorReliabilityHandbook"etc.
021023_ATheTOSHIBAproductslistedinthisdocumentareintendedforusageingeneralelectronicsapplications(computer,personalequip-ment,officeequipment,measuringequipment,industrialrobotics,domesticappliances,etc.
).
TheseTOSHIBAproductsareneitherintendednorwarrantedforusageinequipmentthatrequiresextraordinarilyhighqualityand/orreliabilityoramalfunctionorfailureofwhichmaycauselossofhumanlifeorbodilyinjury("UnintendedUsage").
UnintendedUsageincludeatomicenergycontrolinstruments,airplaneorspaceshipinstruments,transportationinstruments,trafficsignalinstruments,combustioncontrolinstruments,medicalinstru-ments,alltypesofsafetydevices,etc.
UnintendedUsageofTOSHIBAproductslistedinthisdocumentshallbemadeatthecustomer'sownrisk.
021023_BTheproductsdescribedinthisdocumentshallnotbeusedorembeddedtoanydownstreamproductsofwhichmanufacture,useand/orsaleareprohibitedunderanyapplicablelawsandregulations.
060106_QTheinformationcontainedhereinispresentedonlyasaguidefortheapplicationsofourproducts.
NoresponsibilityisassumedbyTOSHIBAforanyinfringementsofpatentsorotherrightsofthethirdpartieswhichmayresultfromitsuse.
Nolicenseisgrantedbyimpli-cationorotherwiseunderanypatentsorotherrightsofTOSHIBAorthethirdparties.
070122_CTheproductsdescribedinthisdocumentaresubjecttoforeignexchangeandforeigntradecontrollaws.
060925_EForadiscussionofhowthereliabilityofmicrocontrollerscanbepredicted,pleaserefertoSection1.
3ofthechapterentitledQualityandReliabilityAssurance/HandlingPrecautions.
030619_STMP86CS28FG1.
1Features1.
8-bitsinglechipmicrocomputerTLCS-870/Cseries-Instructionexecutiontime:0.
25s(at16MHz)122s(at32.
768kHz)-132types&731basicinstructions2.
23interruptsources(External:6Internal:17)3.
Input/Outputports(62pins)4.
WatchdogTimer5.
Prescaler-Timebasetimer-Divideroutputfunction6.
16-bittimercounter:2ch-Timer,Externaltrigger,Window,Pulsewidthmeasurement,Eventcounter,Programmablepulsegenerate(PPG)modes7.
8-bittimercounter:4ch-Timer,Eventcounter,Programmabledivideroutput(PDO),Pulsewidthmodulation(PWM)output,Programmablepulsegeneration(PPG)modes8.
8-bitUART/SIO:1ch9.
8-bitUART:1chProductNo.
ROM(MaskROM)RAMPackageFLASHMCUEmulationChipTMP86CS28FG61440bytes2048bytesQFP80-P-1420-0.
80BTMP86FS28FGTMP86C989XBPage21.
1FeaturesTMP86CS28FG10.
10-bitsuccessiveapproximationtypeADconverter-Analoginput:8ch11.
Key-onwakeup:4ch12.
LCDdriver/controllerBuilt-involtageboosterforLCDdriverWithdisplaymemoryLCDdirectdrivecapability(MAX40seg*4com)1/4,1/3,1/2dutiesorstaticdriveareprogrammablyselectable13.
ClockoperationSingleclockmodeDualclockmode14.
LowpowerconsumptionoperationSTOPmode:Oscillationstops.
(Battery/Capacitorback-up.
)SLOW1mode:Lowpowerconsumptionoperationusinglow-frequencyclock.
(High-frequencyclockstop.
)SLOW2mode:Lowpowerconsumptionoperationusinglow-frequencyclock.
(High-frequencyclockoscillate.
)IDLE0mode:CPUstops,andonlytheTime-Based-Timer(TBT)onperipheralsoperateusinghighfre-quencyclock.
ReleasebyfallingedgeofthesourceclockwhichissetbyTBTCR.
IDLE1mode:CPUstopsandperipheralsoperateusinghighfrequencyclock.
Releasebyinterru-puts(CPUrestarts).
IDLE2mode:CPUstopsandperipheralsoperateusinghighandlowfrequencyclock.
Releasebyinter-ruputs.
(CPUrestarts).
SLEEP0mode:CPUstops,andonlytheTime-Based-Timer(TBT)onperipheralsoperateusinglowfre-quencyclock.
ReleasebyfallingedgeofthesourceclockwhichissetbyTBTCR.
SLEEP1mode:CPUstops,andperipheralsoperateusinglowfrequencyclock.
Releasebyinterru-put.
(CPUrestarts).
SLEEP2mode:CPUstopsandperipheralsoperateusinghighandlowfrequencyclock.
Releasebyinterruput.
15.
Wideoperationvoltage:2.
7Vto5.
5Vat8MHz/32.
768kHz4.
0Vto5.
5Vat16MHz/32.
768kHzPage3TMP86CS28FG1.
2PinAssignmentFigure1-1PinAssignment1234567891011121314151617181920212223246463626160595857565554535251504948474645444342414039383736353433323130292827262565666768697071727374757677787980VSSXOUTTESTVDD(XTIN)P21(XTOUT)P22RESET(INT5/STOP)P20P00(INT3/PPG10)P02VAREFAVDD(AIN0)P10(AIN1)P11(STOP2/AIN2)P12(STOP3/AIN3)P13(STOP4/AIN4)P14(STOP5/AIN5)P15(AIN6)P16(INT0)P30AVSSP31(DVO)P33P34(SO/RXD1)P36(SCK)P35(SI/TXD1)P50(SEG31/TXD0)P47(SEG32)P46(SEG33)P45(SEG34)P44(SEG35)P43(SEG36/TC11)P42(SEG37/PPG11)P41(SEG38/INT2)P40(SEG39/INT1)P37(TC10/INT4)P32P62(SEG21)P61(SEG22)P60(SEG23)P57(SEG24)P56(SEG25)P55(SEG26/TC6/PDO6/PWM6/PPG6)P54(SEG27/TC5/PDO5/PWM5)P53(SEG28/TC4/PDO4/PWM4/PPG4)P52(SEG29/TC3/PDO3/PWM3)P51(SEG30/RXD0)P75(SEG10)P80(SEG7)P77(SEG8)P76(SEG9)P74(SEG11)P73(SEG12)P72(SEG13)P71(SEG14)P70(SEG15)P67(SEG16)P66(SEG17)P65(SEG18)P64(SEG19)P63(SEG20)(AIN7)P17P01XIN(SEG6)P81(SEG5)P82(SEG4)P83(SEG3)P84(SEG1)P86(SEG0)P87COM3COM2COM1COM0V3V2V1C1C0(SEG2)P85Page41.
3BlockDiagramTMP86CS28FG1.
3BlockDiagramFigure1-2BlockDiagramPage5TMP86CS28FG1.
4PinNamesandFunctionsTable1-1PinNamesandFunctions(1/4)PinNamePinNumberInput/OutputFunctionsP02PPG10INT312IOOIPORT02PPG10outputExternalinterrupt3inputP0111IOPORT01P0010IOPORT00P17AIN722IOIPORT17AnalogInput7P16AIN621IOIPORT16AnalogInput6P15AIN5STOP520IOIIPORT15AnalogInput5STOP5inputP14AIN4STOP419IOIIPORT14AnalogInput4STOP4inputP13AIN3STOP318IOIIPORT13AnalogInput3STOP3inputP12AIN2STOP217IOIIPORT12AnalogInput2STOP2inputP11AIN116IOIPORT11AnalogInput1P10AIN015IOIPORT10AnalogInput0P22XTOUT7IOOPORT22Resonatorconnectingpins(32.
768kHz)forinputtingexternalclockP21XTIN6IOIPORT21Resonatorconnectingpins(32.
768kHz)forinputtingexternalclockP20STOPINT59IOIIPORT20STOPmodereleasesignalinputExternalinterrupt5inputP37TC10INT431IOIIPORT37TC10inputExternalinterrupt4inputP36SCK30IOIOPORT36SerialClockI/OP35SITXD129IOIOPORT35SerialDataInputUARTdataoutput1P34SORXD128IOOIPORT34SerialDataOutputUARTdatainput1P3327IOPORT33Page61.
4PinNamesandFunctionsTMP86CS28FGP3226IOPORT32P31DVO25IOOPORT31DividerOutputP30INT024IOIPORT30Externalinterrupt0inputP47SEG3239IOOPORT47LCDsegmentoutput32P46SEG3338IOOPORT46LCDsegmentoutput33P45SEG3437IOOPORT45LCDsegmentoutput34P44SEG3536IOOPORT44LCDsegmentoutput35P43SEG36TC1135IOOIPORT43LCDsegmentoutput36TC11inputP42SEG37PPG1134IOOOPORT42LCDsegmentoutput37PPG11outputP41SEG38INT233IOOIPORT41LCDsegmentoutput38Externalinterrupt2inputP40SEG39INT132IOOIPORT40LCDsegmentoutput39Externalinterrupt1inputP57SEG2447IOOPORT57LCDsegmentoutput24P56SEG2546IOOPORT56LCDsegmentoutput25P55SEG26TC6PDO6/PWM6/PPG645IOOIOPORT55LCDsegmentoutput26TC6inputPDO6/PWM6/PPG6outputP54SEG27TC5PDO5/PWM544IOOIOPORT54LCDsegmentoutput27TC5inputPDO5/PWM5outputP53SEG28TC4PDO4/PWM4/PPG443IOOIOPORT53LCDsegmentoutput28TC4inputPDO4/PWM4/PPG4outputP52SEG29TC3PDO3/PWM342IOOIOPORT52LCDsegmentoutput29TC3inputP51SEG30RXD041IOOIPORT51LCDsegmentoutput30UARTdatainput0P50SEG31TXD040IOOOPORT50LCDsegmentoutput31UARTdataoutput0Table1-1PinNamesandFunctions(2/4)PinNamePinNumberInput/OutputFunctionsPage7TMP86CS28FGP67SEG1655IOOPORT67LCDsegmentoutput16P66SEG1754IOOPORT66LCDsegmentoutput17P65SEG1853IOOPORT65LCDsegmentoutput18P64SEG1952IOOPORT64LCDsegmentoutput19P63SEG2051IOOPORT63LCDsegmentoutput20P62SEG2150IOOPORT62LCDsegmentoutput21P61SEG2249IOOPORT61LCDsegmentoutput22P60SEG2348IOOPORT60LCDsegmentoutput23P77SEG863IOOPORT77LCDsegmentoutput8P76SEG962IOOPORT76LCDsegmentoutput9P75SEG1061IOOPORT75LCDsegmentoutput10P74SEG1160IOOPORT74LCDsegmentoutput11P73SEG1259IOOPORT73LCDsegmentoutput12P72SEG1358IOOPORT72LCDsegmentoutput13P71SEG1457IOOPORT71LCDsegmentoutput14P70SEG1556IOOPORT70LCDsegmentoutput15P87SEG071IOOPORT87LCDsegmentoutput0P86SEG170IOOPORT86LCDsegmentoutput1P85SEG269IOOPORT85LCDsegmentoutput2P84SEG368IOOPORT84LCDsegmentoutput3P83SEG467IOOPORT83LCDsegmentoutput4P82SEG566IOOPORT82LCDsegmentoutput5P81SEG665IOOPORT81LCDsegmentoutput6Table1-1PinNamesandFunctions(3/4)PinNamePinNumberInput/OutputFunctionsPage81.
4PinNamesandFunctionsTMP86CS28FGP80SEG764IOOPORT80LCDsegmentoutput7COM372OLCDcommonoutput3COM273OLCDcommonoutput2COM174OLCDcommonoutput1COM075OLCDcommonoutput0V376ILCDvoltageboosterpinV277ILCDvoltageboosterpinV178ILCDvoltageboosterpinC179ILCDvoltageboosterpinC080ILCDvoltageboosterpinXIN2IResonatorconnectingpinsforhigh-frequencyclockXOUT3OResonatorconnectingpinsforhigh-frequencyclockRESET8IResetsignalTEST4ITestpinforout-goingtest.
Normally,befixedtolow.
VAREF14IAnalogBaseVoltageInputPinforA/DConversionAVDD13IAnalogPowerSupplyAVSS23IAnalogPowerSupplyVDD5IPowerSupplyVSS1I0(GND)Table1-1PinNamesandFunctions(4/4)PinNamePinNumberInput/OutputFunctionsPage9TMP86CS28FG2.
OperationalDescription2.
1CPUCoreFunctionsTheCPUcoreconsistsofaCPU,asystemclockcontroller,andaninterruptcontroller.
ThissectionprovidesadescriptionoftheCPUcore,theprogrammemory,thedatamemory,andtheresetcircuit.
2.
1.
1MemoryAddressMapTheTMP86CS28FGmemoryiscomposedMaskROM,RAM,DBR(Databufferregister)andSFR(Specialfunctionregister).
Theyareallmappedin64-Kbyteaddressspace.
Figure2-1showstheTMP86CS28FGmemoryaddressmap.
Figure2-1MemoryAddressMap2.
1.
2ProgramMemory(MaskROM)TheTMP86CS28FGhasa61440bytes(Address1000HtoFFFFH)ofprogrammemory(MaskROM).
2.
1.
3DataMemory(RAM)TheTMP86CS28FGhas2048bytes(Address0040Hto083FH)ofinternalRAM.
Thefirst192bytes(0040Hto00FFH)oftheinternalRAMarelocatedinthedirectarea;instructionswithshortenoperationsareavailableagainstsuchanarea.
SFR0000H64bytesSFR:RAM:Specialfunctionregisterincludes:I/OportsPeripheralcontrolregistersPeripheralstatusregistersSystemcontrolregistersProgramstatuswordRandomaccessmemoryincludes:DatamemoryStack003FHRAM0040H2048bytes083FHDBR0F00H256bytesDBR:Databufferregisterincludes:PeripheralcontrolregistersPeripheralstatusregistersLCDdisplaymemory0FFFH1000HMaskROM:ProgrammemoryMaskROM61440bytesFFA0HVectortableforinterrupts(32bytes)FFBFHFFC0HVectortableforvectorcallinstructions(32bytes)FFDFHFFE0HVectortableforinterrupts(32bytes)FFFFHPage102.
OperationalDescription2.
2SystemClockControllerTMP86CS28FGThedatamemorycontentsbecomeunstablewhenthepowersupplyisturnedon;therefore,thedatamemoryshouldbeinitializedbyaninitializationroutine.
2.
2SystemClockControllerThesystemclockcontrollerconsistsofaclockgenerator,atiminggenerator,andastandbycontroller.
Figure2-2SystemColckControl2.
2.
1ClockGeneratorTheclockgeneratorgeneratesthebasicclockwhichprovidesthesystemclockssuppliedtotheCPUcoreandperipheralhardware.
Itcontainstwooscillationcircuits:Oneforthehigh-frequencyclockandoneforthelow-frequencyclock.
Powerconsumptioncanbereducedbyswitchingofthestandbycontrollertolow-poweroperationbasedonthelow-frequencyclock.
Thehigh-frequency(fc)clockandlow-frequency(fs)clockcaneasilybeobtainedbyconnectingaresonatorbetweentheXIN/XOUTandXTIN/XTOUTpinsrespectively.
Clockinputfromanexternaloscillatorisalsopossible.
Inthiscase,externalclockisappliedtoXIN/XTINpinwithXOUT/XTOUTpinnotconnected.
Example:ClearsRAMto"00H".
(TMP86CS28FG)LDHL,0040H;StartaddresssetupLDA,H;Initialvalue(00H)setupLDBC,07FFHSRAMCLR:LD(HL),AINCHLDECBCJRSF,SRAMCLRTBTCRSYSCR2SYSCR1XINXOUTXTINXTOUTfc0036H0038H0039HfsTiminggeneratorcontrolregisterTiminggeneratorStandbycontrollerSystemclocksClockgeneratorcontrolHigh-frequencyclockoscillatorLow-frequencyclockoscillatorClockgeneratorSystemcontrolregistersPage11TMP86CS28FGFigure2-3ExamplesofResonatorConnectionNote:Thefunctiontomonitorthebasicclockdirectlyatexternalisnotprovidedforhardware,however,withdis-ablingallinterruptsandwatchdogtimers,theoscillationfrequencycanbeadjustedbymonitoringthepulsewhichthefixedfrequencyisoutputtedtotheportbytheprogram.
Thesystemtorequiretheadjustmentoftheoscillationfrequencyshouldcreatetheprogramfortheadjust-mentinadvance.
XOUTXIN(Open)XOUTXINXTOUTXTIN(Open)XTOUTXTIN(a)Crystal/Ceramicresonator(b)Externaloscillator(c)Crystal(d)ExternaloscillatorHigh-frequencyclockLow-frequencyclockPage122.
OperationalDescription2.
2SystemClockControllerTMP86CS28FG2.
2.
2TimingGeneratorThetiminggeneratorgeneratesthevarioussystemclockssuppliedtotheCPUcoreandperipheralhardwarefromthebasicclock(fcorfs).
Thetiminggeneratorprovidesthefollowingfunctions.
1.
Generationofmainsystemclock2.
Generationofdivideroutput(DVO)pulses3.
Generationofsourceclocksfortimebasetimer4.
Generationofsourceclocksforwatchdogtimer5.
Generationofinternalsourceclocksfortimer/counters6.
Generationofwarm-upclocksforreleasingSTOPmode7.
LCD2.
2.
2.
1ConfigurationoftiminggeneratorThetiminggeneratorconsistsofa2-stageprescaler,a21-stagedivider,amainsystemclockgenerator,andmachinecyclecounters.
Aninputclocktothe7thstageofthedividerdependsontheoperatingmode,SYSCR2andTBTCR,thatisshowninFigure2-4.
AsresetandSTOPmodestarted/canceled,theprescalerandthedividerareclearedto"0".
Figure2-4ConfigurationofTimingGeneratorMulti-plexerHigh-frequencyclockfcLow-frequencyclockfsDividerSYSCKfc/4fcorfsMachinecyclecountersMainsystemclockgenerator12143287109121114131615DV7CKMultiplexerWarm-upcontrollerWatchdogtimerASBYSB0A0Y0B1A1Y1561718192021Timercounter,Serialinterface,Time-base-timer,divideroutput,etc.
(Peripheralfunctions)Page13TMP86CS28FGNote1:Insingleclockmode,donotsetDV7CKto"1".
Note2:Donotset"1"onDV7CKwhilethelow-frequencyclockisnotoperatedstably.
Note3:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*:Don'tcareNote4:InSLOW1/2andSLEEP1/2modes,theDV7CKsettingisineffective,andfsisinputtothe7thstageofthedivider.
Note5:WhenSTOPmodeisenteredfromNORMAL1/2mode,theDV7CKsettingisineffectiveduringthewarm-upperiodafterreleaseofSTOPmode,andthe6thstageofthedividerisinputtothe7thstageduringthisperiod.
2.
2.
2.
2MachinecycleInstructionexecutionandperipheralhardwareoperationaresynchronizedwiththemainsystemclock.
Theminimuminstructionexecutionunitiscalledan"machinecycle".
Thereareatotalof10differenttypesofinstructionsfortheTLCS-870/CSeries:Rangingfrom1-cycleinstructionswhichrequireonemachinecycleforexecutionto10-cycleinstructionswhichrequire10machinecyclesforexecution.
Amachinecycleconsistsof4states(S0toS3),andeachstateconsistsofonemainsystemclock.
Figure2-5MachineCycle2.
2.
3OperationModeControlCircuitTheoperationmodecontrolcircuitstartsandstopstheoscillationcircuitsforthehigh-frequencyandlow-frequencyclocks,andswitchesthemainsystemclock.
Therearethreeoperatingmodes:Singleclockmode,dualclockmodeandSTOPmode.
Thesemodesarecontrolledbythesystemcontrolregisters(SYSCR1andSYSCR2).
Figure2-6showstheoperatingmodetransitiondiagram.
2.
2.
3.
1Single-clockmodeOnlytheoscillationcircuitforthehigh-frequencyclockisused,andP21(XTIN)andP22(XTOUT)pinsareusedasinput/outputports.
Themain-systemclockisobtainedfromthehigh-frequencyclock.
Inthesingle-clockmode,themachinecycletimeis4/fc[s].
(1)NORMAL1modeInthismode,boththeCPUcoreandon-chipperipheralsoperateusingthehigh-frequencyclock.
TheTMP86CS28FGisplacedinthismodeafterreset.
TimingGeneratorControlRegisterTBTCR(0036H)76543210(DVOEN)(DVOCK)DV7CK(TBTEN)(TBTCK)(Initialvalue:00000000)DV7CKSelectionofinputtothe7thstageofthedivider0:fc/28[Hz]1:fsR/WMainsystemclockStateMachinecycleS3S2S1S0S3S2S1S01/fcor1/fs[s]Page142.
OperationalDescription2.
2SystemClockControllerTMP86CS28FG(2)IDLE1modeInthismode,theinternaloscillationcircuitremainsactive.
TheCPUandthewatchdogtimerarehalted;howeveron-chipperipheralsremainactive(Operateusingthehigh-frequencyclock).
IDLE1modeisstartedbySYSCR2="1",andIDLE1modeisreleasedtoNORMAL1modebyaninterruptrequestfromtheon-chipperipheralsorexternalinterruptinputs.
WhentheIMF(Interruptmasterenableflag)is"1"(Interruptenable),theexecutionwillresumewiththeacceptanceoftheinterrupt,andtheoperationwillreturntonormalaftertheinterruptserviceiscompleted.
WhentheIMFis"0"(Interruptdisable),theexecutionwillresumewiththeinstructionwhichfollowstheIDLE1modestartinstruction.
(3)IDLE0modeInthismode,allthecircuit,exceptoscillatorandthetimer-base-timer,stopsoperation.
ThismodeisenabledbySYSCR2="1".
WhenIDLE0modestarts,theCPUstopsandthetiminggeneratorstopsfeedingtheclocktotheperipheralcircuitsotherthanTBT.
Then,upondetectingthefallingedgeofthesourceclockselectedwithTBTCR,thetiminggeneratorstartsfeedingtheclocktoallperipheralcircuits.
WhenreturnedfromIDLE0mode,theCPUrestartsoperating,enteringNORMAL1modebackagain.
IDLE0modeisenteredandreturnedregardlessofhowTBTCRisset.
WhenIMF="1",EF6(TBTinterruptindividualenableflag)="1",andTBTCR="1",interruptpro-cessingisperformed.
WhenIDLE0modeisenteredwhileTBTCR="1",theINTTBTinterruptlatchissetafterreturningtoNORMAL1mode.
2.
2.
3.
2Dual-clockmodeBoththehigh-frequencyandlow-frequencyoscillationcircuitsareusedinthismode.
P21(XTIN)andP22(XTOUT)pinscannotbeusedasinput/outputports.
Themainsystemclockisobtainedfromthehigh-frequencyclockinNORMAL2andIDLE2modes,andisobtainedfromthelow-frequencyclockinSLOWandSLEEPmodes.
Themachinecycletimeis4/fc[s]intheNORMAL2andIDLE2modes,and4/fs[s](122satfs=32.
768kHz)intheSLOWandSLEEPmodes.
TheTLCS-870/Cisplacedinthesignal-clockmodeduringreset.
Tousethedual-clockmode,thelow-frequencyoscillatorshouldbeturnedonatthestartofaprogram.
(1)NORMAL2modeInthismode,theCPUcoreoperateswiththehigh-frequencyclock.
On-chipperipheralsoperateusingthehigh-frequencyclockand/orlow-frequencyclock.
(2)SLOW2modeInthismode,theCPUcoreoperateswiththelow-frequencyclock,whileboththehigh-frequencyclockandthelow-frequencyclockareoperated.
AstheSYSCR2becomes"1",thehard-warechangesintoSLOW2mode.
AstheSYSCR2becomes"0",thehardwarechangesintoNORMAL2mode.
AstheSYSCR2becomes"0",thehardwarechangesintoSLOW1mode.
DonotclearSYSCR2to"0"duringSLOW2mode.
(3)SLOW1modeThismodecanbeusedtoreducepower-consumptionbyturningoffoscillationofthehigh-fre-quencyclock.
TheCPUcoreandon-chipperipheralsoperateusingthelow-frequencyclock.
Page15TMP86CS28FGSwitchingbackandforthbetweenSLOW1andSLOW2modesareperformedbySYSCR2.
InSLOW1andSLEEPmodes,theinputclocktothe1ststageofthedividerisstopped;outputfromthe1stto6thstagesisalsostopped.
(4)IDLE2modeInthismode,theinternaloscillationcircuitremainactive.
TheCPUandthewatchdogtimerarehalted;however,on-chipperipheralsremainactive(Operateusingthehigh-frequencyclockand/orthelow-frequencyclock).
StartingandreleasingofIDLE2modearethesameasforIDLE1mode,exceptthatoperationreturnstoNORMAL2mode.
(5)SLEEP1modeInthismode,theinternaloscillationcircuitofthelow-frequencyclockremainsactive.
TheCPU,thewatchdogtimer,andtheinternaloscillationcircuitofthehigh-frequencyclockarehalted;how-ever,on-chipperipheralsremainactive(Operateusingthelow-frequencyclock).
Startingandreleas-ingofSLEEPmodearethesameasforIDLE1mode,exceptthatoperationreturnstoSLOW1mode.
InSLOW1andSLEEP1modes,theinputclocktothe1ststageofthedividerisstopped;outputfromthe1stto6thstagesisalsostopped.
(6)SLEEP2modeTheSLEEP2modeistheidlemodecorrespondingtotheSLOW2mode.
ThestatusundertheSLEEP2modeissameasthatundertheSLEEP1mode,exceptfortheoscillationcircuitofthehigh-frequencyclock.
(7)SLEEP0modeInthismode,allthecircuit,exceptoscillatorandthetimer-base-timer,stopsoperation.
Thismodeisenabledbysetting"1"onbitSYSCR2.
WhenSLEEP0modestarts,theCPUstopsandthetiminggeneratorstopsfeedingtheclocktotheperipheralcircuitsotherthanTBT.
Then,upondetectingthefallingedgeofthesourceclockselectedwithTBTCR,thetiminggeneratorstartsfeedingtheclocktoallperipheralcircuits.
WhenreturnedfromSLEEP0mode,theCPUrestartsoperating,enteringSLOW1modebackagain.
SLEEP0modeisenteredandreturnedregardlessofhowTBTCRisset.
WhenIMF="1",EF6(TBTinterruptindividualenableflag)="1",andTBTCR="1",interruptpro-cessingisperformed.
WhenSLEEP0modeisenteredwhileTBTCR="1",theINTTBTinterruptlatchissetafterreturningtoSLOW1mode.
2.
2.
3.
3STOPmodeInthismode,theinternaloscillationcircuitisturnedoff,causingallsystemoperationstobehalted.
TheinternalstatusimmediatelypriortothehaltisheldwithalowestpowerconsumptionduringSTOPmode.
STOPmodeisstartedbythesystemcontrolregister1(SYSCR1),andSTOPmodeisreleasedbyainputting(Eitherlevel-sensitiveoredge-sensitivecanbeprogrammablyselected)totheSTOPpin.
Afterthewarm-upperiodiscompleted,theexecutionresumeswiththeinstructionwhichfollowstheSTOPmodestartinstruction.
Page162.
OperationalDescription2.
2SystemClockControllerTMP86CS28FGNote1:NORMAL1andNORMAL2modesaregenericallycalledNORMAL;SLOW1andSLOW2arecalledSLOW;IDLE0,IDLE1andIDLE2arecalledIDLE;SLEEP0,SLEEP1andSLEEP2arecalledSLEEP.
Note2:ThemodeisreleasedbyfallingedgeofTBTCRsetting.
Figure2-6OperatingModeTransitionDiagramTable2-1OperatingModeandConditionsOperatingModeOscillatorCPUCoreTBTOtherPeripheralsMachineCycleTimeHighFrequencyLowFrequencySingleclockRESETOscillationStopResetResetReset4/fc[s]NORMAL1OperateOperateOperateIDLE1HaltIDLE0HaltSTOPStopHalt–DualclockNORMAL2OscillationOscillationOperatewithhighfrequencyOperateOperate4/fc[s]IDLE2HaltSLOW2Operatewithlowfrequency4/fs[s]SLEEP2HaltSLOW1StopOperatewithlowfrequencySLEEP1HaltSLEEP0HaltSTOPStopHalt–Note2SYSCR2="1"STOPpininputSTOPpininputSTOPpininputInterruptInterruptSYSCR2="0"SYSCR2="1"SYSCR2="0"SYSCR2="0"SYSCR1="1"SYSCR1="1"SYSCR1="1"SYSCR2="1"SYSCR2="1"InterruptSYSCR2="1"SYSCR2="1"InterruptSYSCR2="1"ResetreleaseNORMAL1modeIDLE0mode(a)Single-clockmodeIDLE1modeNORMAL2modeIDLE2modeSYSCR2="1"SLOW2modeSLEEP2modeSLOW1modeSLEEP1modeSLEEP0modeRESET(b)Dual-clockmodeSTOPSYSCR2="1"Note2Page17TMP86CS28FGNote1:AlwayssetRETMto"0"whentransitingfromNORMALmodetoSTOPmode.
AlwayssetRETMto"1"whentransitingfromSLOWmodetoSTOPmode.
Note2:WhenSTOPmodeisreleasedwithRESETpininput,areturnismadetoNORMAL1regardlessoftheRETMcontents.
Note3:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*;Don'tcareNote4:Bits1and0inSYSCR1arereadasundefineddatawhenareadinstructionisexecuted.
Note5:AsthehardwarebecomesSTOPmodeunderOUTEN="0",inputvalueisfixedto"0";thereforeitmaycauseexternalinterruptrequestonaccountoffallingedge.
Note6:Whenthekey-onwakeupisused,RELMshouldbesetto"1".
Note7:PortP20isusedasSTOPpin.
Therefore,whenstopmodeisstarted,OUTENdoesnotaffecttoP20,andP20becomesHigh-Zmode.
Note8:Thewarmig-uptimeshouldbesetcorrectlyforusingoscillator.
Note1:AresetisappliedifbothXENandXTENareclearedto"0",XENisclearedto"0"whenSYSCK="0",orXTENisclearedto"0"whenSYSCK="1".
Note2:*:Don'tcare,TG:Timinggenerator,*;Don'tcareNote3:Bits3,1and0inSYSCR2arealwaysreadasundefinedvalue.
Note4:DonotsetIDLEandTGHALTto"1"simultaneously.
Note5:BecausereturningfromIDLE0/SLEEP0toNORMAL1/SLOW1isexecutedbytheasynchronousinternalclock,theperiodofIDLE0/SLEEP0modemightbeshorterthantheperiodsettingbyTBTCR.
Note6:WhenIDLE1/2orSLEEP1/2modeisreleased,IDLEisautomaticallyclearedto"0".
Note7:WhenIDLE0orSLEEP0modeisreleased,TGHALTisautomaticallyclearedto"0".
Note8:BeforesettingTGHALTto"1",besuretostopperipherals.
Ifperipheralsarenotstopped,theinterruptlatchofperipheralsmaybesetafterIDLE0orSLEEP0modeisreleased.
SystemControlRegister1SYSCR176543210(0038H)STOPRELMRETMOUTENWUT(Initialvalue:000000**)STOPSTOPmodestart0:CPUcoreandperipheralsremainactive1:CPUcoreandperipheralsarehalted(StartSTOPmode)R/WRELMReleasemethodforSTOPmode0:Edge-sensitiverelease1:Level-sensitivereleaseR/WRETMOperatingmodeafterSTOPmode0:ReturntoNORMAL1/2mode1:ReturntoSLOW1modeR/WOUTENPortoutputduringSTOPmode0:Highimpedance1:OutputkeptR/WWUTWarm-uptimeatreleasingSTOPmodeReturntoNORMALmodeReturntoSLOWmodeR/W000110113x216/fc216/fc3x214/fc214/fc3x213/fs213/fs3x26/fs26/fsSystemControlRegister2SYSCR2(0039H)76543210XENXTENSYSCKIDLETGHALT(Initialvalue:1000*0**)XENHigh-frequencyoscillatorcontrol0:Turnoffoscillation1:TurnonoscillationR/WXTENLow-frequencyoscillatorcontrol0:Turnoffoscillation1:TurnonoscillationSYSCKMainsystemclockselect(Write)/mainsystemclockmoni-tor(Read)0:High-frequencyclock(NORMAL1/NORMAL2/IDLE1/IDLE2)1:Low-frequencyclock(SLOW1/SLOW2/SLEEP1/SLEEP2)IDLECPUandwatchdogtimercontrol(IDLE1/2andSLEEP1/2modes)0:CPUandwatchdogtimerremainactive1:CPUandwatchdogtimerarestopped(StartIDLE1/2andSLEEP1/2modes)R/WTGHALTTGcontrol(IDLE0andSLEEP0modes)0:FeedingclocktoallperipheralsfromTG1:StopfeedingclocktoperipheralsexceptTBTfromTG.
(StartIDLE0andSLEEP0modes)Page182.
OperationalDescription2.
2SystemClockControllerTMP86CS28FG2.
2.
4OperatingModeControl2.
2.
4.
1STOPmodeSTOPmodeiscontrolledbythesystemcontrolregister1,theSTOPpininputandkey-onwakeupinput(STOP5toSTOP2)whichiscontrolledbytheSTOPmodereleasecontrolregister(STOPCR).
TheSTOPpinisalsousedbothasaportP20andanINT5(externalinterruptinput5)pin.
STOPmodeisstartedbysettingSYSCR1to"1".
DuringSTOPmode,thefollowingstatusismaintained.
1.
Oscillationsareturnedoff,andallinternaloperationsarehalted.
2.
Thedatamemory,registers,theprogramstatuswordandportoutputlatchesareallheldinthestatusineffectbeforeSTOPmodewasentered.
3.
Theprescalerandthedividerofthetiminggeneratorareclearedto"0".
4.
Theprogramcounterholdstheaddress2aheadoftheinstruction(e.
g.
,[SET(SYSCR1).
7])whichstartedSTOPmode.
STOPmodeincludesalevel-sensitivemodeandanedge-sensitivemode,eitherofwhichcanbeselectedwiththeSYSCR1.
Donotuseanykey-onwakeupinput(STOP5toSTOP2)forreleas-ingSTOPmodeinedge-sensitivemode.
Note1:TheSTOPmodecanbereleasedbyeithertheSTOPorkey-onwakeuppin(STOP5toSTOP2).
However,becausetheSTOPpinisdifferentfromthekey-onwakeupandcannotinhibitthereleaseinput,theSTOPpinmustbeusedforreleasingSTOPmode.
Note2:DuringSTOPperiod(fromstartofSTOPmodetoendofwarmup),duetochangesintheexternalinterruptpinsignal,interruptlatchesmaybesetto"1"andinterruptsmaybeacceptedimmediatelyafterSTOPmodeisreleased.
BeforestartingSTOPmode,therefore,disableinterrupts.
Also,beforeenablinginterruptsafterSTOPmodeisreleased,clearunnecessaryinterruptlatches.
(1)Level-sensitivereleasemode(RELM="1")Inthismode,STOPmodeisreleasedbysettingtheSTOPpinhighorsettingtheSTOP5toSTOP2pininputwhichisenabledbySTOPCR.
Thismodeisusedforcapacitorbackupwhenthemainpowersupplyiscutoffandlongtermbatterybackup.
EvenifaninstructionforstartingSTOPmodeisexecutedwhileSTOPpininputishighorSTOP5toSTOP2inputislow,STOPmodedoesnotstartbutinsteadthewarm-upsequencestartsimmedi-ately.
Thus,tostartSTOPmodeinthelevel-sensitivereleasemode,itisnecessaryfortheprogramtofirstconfirmthattheSTOPpininputisloworSTOP5toSTOP2inputishigh.
Thefollowingtwomethodscanbeusedforconfirmation.
1.
Testingaport.
2.
UsinganexternalinterruptinputINT5(INT5isafallingedge-sensitiveinput).
Example1:StartingSTOPmodefromNORMALmodebytestingaportP20.
LD(SYSCR1),01010000B;Setsupthelevel-sensitivereleasemodeSSTOPH:TEST(P2PRD).
0;WaituntiltheSTOPpininputgoeslowlevelJRSF,SSTOPHDI;IMF←0SET(SYSCR1).
7;StartsSTOPmodePage19TMP86CS28FGFigure2-7Level-sensitiveReleaseModeNote1:EveniftheSTOPpininputislowafterwarm-upstart,theSTOPmodeisnotrestarted.
Note2:Inthiscaseofchangingtothelevel-sensitivemodefromtheedge-sensitivemode,thereleasemodeisnotswitcheduntilarisingedgeoftheSTOPpininputisdetected.
(2)Edge-sensitivereleasemode(RELM="0")Inthismode,STOPmodeisreleasedbyarisingedgeoftheSTOPpininput.
Thisisusedinappli-cationswherearelativelyshortprogramisexecutedrepeatedlyatperiodicintervals.
Thisperiodicsignal(forexample,aclockfromalow-powerconsumptionoscillator)isinputtotheSTOPpin.
Intheedge-sensitivereleasemode,STOPmodeisstartedevenwhentheSTOPpininputishighlevel.
DonotuseanySTOP5toSTOP2pininputforreleasingSTOPmodeinedge-sensitivereleasemode.
Figure2-8Edge-sensitiveReleaseModeExample2:StartingSTOPmodefromNORMALmodewithanINT5interrupt.
PINT5:TEST(P2PRD).
0;Torejectnoise,STOPmodedoesnotstartifJRSF,SINT5portP20isathighLD(SYSCR1),01010000B;Setsupthelevel-sensitivereleasemode.
DI;IMF←0SET(SYSCR1).
7;StartsSTOPmodeSINT5:RETIExample:StartingSTOPmodefromNORMALmodeDI;IMF←0LD(SYSCR1),10010000B;Startsafterspecifiedtotheedge-sensitivereleasemodeVIHNORMALoperationWarmupSTOPoperationConfirmbyprogramthattheSTOPpininputislowandstartSTOPmode.
AlwaysreleasediftheSTOPpininputishigh.
STOPpinXOUTpinSTOPmodeisreleasedbythehardware.
NORMALoperationNORMALoperationNORMALoperationVIHSTOPmodeisreleasedbythehardwareattherisingedgeofSTOPpininput.
WarmupSTOPmodestartedbytheprogram.
STOPoperationSTOPoperationSTOPpinXOUTpinPage202.
OperationalDescription2.
2SystemClockControllerTMP86CS28FGSTOPmodeisreleasedbythefollowingsequence.
1.
Inthedual-clockmode,whenreturningtoNORMAL2,boththehigh-frequencyandlow-frequencyclockoscillatorsareturnedon;whenreturningtoSLOW1mode,onlythelow-frequencyclockoscillatoristurnedon.
Inthesingle-clockmode,onlythehigh-frequencyclockoscillatoristurnedon.
2.
Awarm-upperiodisinsertedtoallowoscillationtimetostabilize.
Duringwarmup,allinternaloperationsremainhalted.
Fourdifferentwarm-uptimescanbeselectedwiththeSYSCR1inaccordancewiththeresonatorcharacteristics.
3.
Whenthewarm-uptimehaselapsed,normaloperationresumeswiththeinstructionfollow-ingtheSTOPmodestartinstruction.
Note1:WhentheSTOPmodeisreleased,thestartismadeaftertheprescalerandthedividerofthetiminggeneratorareclearedto"0".
Note2:STOPmodecanalsobereleasedbyinputtinglowlevelontheRESETpin,whichimmediatelyperformsthenormalresetoperation.
Note3:WhenSTOPmodeisreleasedwithalowholdvoltage,thefollowingcautionsmustbeobserved.
ThepowersupplyvoltagemustbeattheoperatingvoltagelevelbeforereleasingSTOPmode.
TheRESETpininputmustalsobe"H"level,risingtogetherwiththepowersupplyvoltage.
Inthiscase,ifanexternaltimeconstantcircuithasbeenconnected,theRESETpininputvoltagewillincreaseataslowerpacethanthepowersupplyvoltage.
Atthistime,thereisadangerthataresetmayoccurifinputvoltageleveloftheRESETpindropsbelowthenon-invertinghigh-levelinputvoltage(Hysteresisinput).
Note1:Thewarm-uptimeisobtainedbydividingthebasicclockbythedivider.
Therefore,thewarm-uptimemayincludeacertainamountoferrorifthereisanyfluctuationoftheoscillationfrequencywhenSTOPmodeisreleased.
Thus,thewarm-uptimemustbeconsideredasanapproximatevalue.
Table2-2Warm-upTimeExample(atfc=16.
0MHz,fs=32.
768kHz)WUTWarm-upTime[ms]ReturntoNORMALModeReturntoSLOWMode0001101112.
2884.
0963.
0721.
0247502505.
851.
95Page21TMP86CS28FGFigure2-9STOPModeStart/ReleaseInstructionaddressa+40Instructionaddressa+3TurnonTurnonWarmup0nHaltSET(SYSCR1).
7Turnoff(a)STOPmodestart(Example:StartwithSET(SYSCR1).
7instructionlocatedataddressa)a+6a+5a+4a+3a+2n+2n+3n+4a+3n+1Instructionaddressa+22103(b)STOPmodereleaseCountupTurnoffHaltOscillatorcircuitProgramcounterInstructionexecutionDividerMainsystemclockOscillatorcircuitSTOPpininputProgramcounterInstructionexecutionDividerMainsystemclockPage222.
OperationalDescription2.
2SystemClockControllerTMP86CS28FG2.
2.
4.
2IDLE1/2modeandSLEEP1/2modeIDLE1/2andSLEEP1/2modesarecontrolledbythesystemcontrolregister2(SYSCR2)andmaskableinterrupts.
Thefollowingstatusismaintainedduringthesemodes.
1.
OperationoftheCPUandwatchdogtimer(WDT)ishalted.
On-chipperipheralscontinuetooperate.
2.
Thedatamemory,CPUregisters,programstatuswordandportoutputlatchesareallheldinthestatusineffectbeforethesemodeswereentered.
3.
Theprogramcounterholdstheaddress2aheadoftheinstructionwhichstartsthesemodes.
Figure2-10IDLE1/2andSLEEP1/2ModesResetResetinput"0""1"(Interruptreleasemode)YesNoNoCPUandWDTarehaltedInterruptrequestIMFInterruptprocessingNormalreleasemodeYesStartingIDLE1/2andSLEEP1/2modesbyinstructionExecutionoftheinstruc-tionwhichfollowstheIDLE1/2andSLEEP1/2modesstartinstructionPage23TMP86CS28FGStarttheIDLE1/2andSLEEP1/2modesAfterIMFissetto"0",settheindividualinterruptenableflag(EF)whichreleasesIDLE1/2andSLEEP1/2modes.
TostartIDLE1/2andSLEEP1/2modes,setSYSCR2to"1".
ReleasetheIDLE1/2andSLEEP1/2modesIDLE1/2andSLEEP1/2modesincludeanormalreleasemodeandaninterruptreleasemode.
Thesemodesareselectedbyinterruptmasterenableflag(IMF).
AfterreleasingIDLE1/2andSLEEP1/2modes,theSYSCR2isautomaticallyclearedto"0"andtheoperationmodeisreturnedtothemodeprecedingIDLE1/2andSLEEP1/2modes.
IDLE1/2andSLEEP1/2modescanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
(1)Normalreleasemode(IMF="0")IDLE1/2andSLEEP1/2modesarereleasedbyanyinterruptsourceenabledbytheindividualinterruptenableflag(EF).
Aftertheinterruptisgenerated,theprogramoperationisresumedfromtheinstructionfollowingtheIDLE1/2andSLEEP1/2modesstartinstruction.
Normally,theinterruptlatches(IL)oftheinterruptsourceusedforreleasingmustbeclearedto"0"byloadinstructions.
(2)Interruptreleasemode(IMF="1")IDLE1/2andSLEEP1/2modesarereleasedbyanyinterruptsourceenabledwiththeindividualinterruptenableflag(EF)andtheinterruptprocessingisstarted.
Aftertheinterruptisprocessed,theprogramoperationisresumedfromtheinstructionfollowingtheinstruction,whichstartsIDLE1/2andSLEEP1/2modes.
Note:WhenawatchdogtimerinterruptsisgeneratedimmediatelybeforeIDLE1/2andSLEEP1/2modesarestarted,thewatchdogtimerinterruptwillbeprocessedbutIDLE1/2andSLEEP1/2modeswillnotbestarted.
Page242.
OperationalDescription2.
2SystemClockControllerTMP86CS28FGFigure2-11IDLE1/2andSLEEP1/2ModesStart/ReleaseHaltHaltHaltHaltOperateInstructionaddressa+2a+3a+2a+4a+3a+3HaltSET(SYSCR2).
4OperateOperateOperateAcceptanceofinterruptNormalreleasemodeInterruptreleasemodeMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimer(a)IDLE1/2andSLEEP1/2modesstart(Example:StartingwiththeSETinstructionlocatedataddressa)(b)IDLE1/2andSLEEP1/2modesreleasePage25TMP86CS28FG2.
2.
4.
3IDLE0andSLEEP0modes(IDLE0,SLEEP0)IDLE0andSLEEP0modesarecontrolledbythesystemcontrolregister2(SYSCR2)andthetimebasetimercontrolregister(TBTCR).
ThefollowingstatusismaintainedduringIDLE0andSLEEP0modes.
1.
TiminggeneratorstopsfeedingclocktoperipheralsexceptTBT.
2.
Thedatamemory,CPUregisters,programstatuswordandportoutputlatchesareallheldinthestatusineffectbeforeIDLE0andSLEEP0modeswereentered.
3.
Theprogramcounterholdstheaddress2aheadoftheinstructionwhichstartsIDLE0andSLEEP0modes.
Note:BeforestartingIDLE0orSLEEP0mode,besuretostop(Disable)peripherals.
Figure2-12IDLE0andSLEEP0ModesYes(Normalreleasemode)Yes(Interruptreleasemode)NoYesResetinputCPUandWDTarehaltedResetTBTsourceclockfallingedgeTBTCR="1"InterruptprocessingIMF="1"YesTBTinterruptenableNoNoNoNoStoppingperipheralsbyinstructionYesStartingIDLE0,SLEEP0modesbyinstructionExecutionoftheinstructionwhichfollowstheIDLE0,SLEEP0modesstartinstructionPage262.
OperationalDescription2.
2SystemClockControllerTMP86CS28FGStarttheIDLE0andSLEEP0modesStop(Disable)peripheralssuchasatimercounter.
TostartIDLE0andSLEEP0modes,setSYSCR2to"1".
ReleasetheIDLE0andSLEEP0modesIDLE0andSLEEP0modesincludeanormalreleasemodeandaninterruptreleasemode.
Thesemodesareselectedbyinterruptmasterflag(IMF),theindividualinterruptenableflagofTBTandTBTCR.
AfterreleasingIDLE0andSLEEP0modes,theSYSCR2isautomaticallyclearedto"0"andtheoperationmodeisreturnedtothemodeprecedingIDLE0andSLEEP0modes.
BeforestartingtheIDLE0orSLEEP0mode,whentheTBTCRissetto"1",INTTBTinterruptlatchissetto"1".
IDLE0andSLEEP0modescanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
Note:IDLE0andSLEEP0modesstart/releasewithoutreferencetoTBTCRsetting.
(1)Normalreleasemode(IMFEF6TBTCR="0")IDLE0andSLEEP0modesarereleasedbythesourceclockfallingedge,whichissettingbytheTBTCR.
Afterthefallingedgeisdetected,theprogramoperationisresumedfromtheinstructionfollowingtheIDLE0andSLEEP0modesstartinstruction.
BeforestartingtheIDLE0orSLEEP0mode,whentheTBTCRissetto"1",INTTBTinterruptlatchissetto"1".
(2)Interruptreleasemode(IMFEF6TBTCR="1")IDLE0andSLEEP0modesarereleasedbythesourceclockfallingedge,whichissettingbytheTBTCRandINTTBTinterruptprocessingisstarted.
Note1:BecausereturningfromIDLE0,SLEEP0toNORMAL1,SLOW1isexecutedbytheasynchro-nousinternalclock,theperiodofIDLE0,SLEEP0modemightbetheshorterthantheperiodset-tingbyTBTCR.
Note2:WhenawatchdogtimerinterruptisgeneratedimmediatelybeforeIDLE0/SLEEP0modeisstarted,thewatchdogtimerinterruptwillbeprocessedbutIDLE0/SLEEP0modewillnotbestarted.
Page27TMP86CS28FGFigure2-13IDLE0andSLEEP0ModesStart/ReleaseHaltHaltOperateInstructionaddressa+2HaltOperateSET(SYSCR2).
2HaltOperateAcceptanceofinterruptHaltNormalreleasemodeInterruptreleasemodeMainsystemclockInterruptrequestProgramcounterInstructionexecutionWatchdogtimerMainsystemclockTBTclockTBTclockProgramcounterInstructionexecutionWatchdogtimerMainsystemclockProgramcounterInstructionexecutionWatchdogtimera+3a+2a+4a+3a+3(a)IDLE0andSLEEP0modesstart(Example:StartingwiththeSETinstructionlocatedataddressa(b)IDLEandSLEEP0modesreleasePage282.
OperationalDescription2.
2SystemClockControllerTMP86CS28FG2.
2.
4.
4SLOWmodeSLOWmodeiscontrolledbythesystemcontrolregister2(SYSCR2).
Thefollowingisthemethodstoswitchthemodewiththewarm-upcounter.
(1)SwitchingfromNORMAL2modetoSLOW1modeFirst,setSYSCR2toswitchthemainsystemclocktothelow-frequencyclockforSLOW2mode.
Next,clearSYSCR2toturnoffhigh-frequencyoscillation.
Note:Thehigh-frequencyclockcanbecontinuedoscillationinordertoreturntoNORMAL2modefromSLOWmodequickly.
Alwaysturnoffoscillationofhigh-frequencyclockwhenswitchingfromSLOWmodetostopmode.
Example1:SwitchingfromNORMAL2modetoSLOW1mode.
SET(SYSCR2).
5;SYSCR2←1(Switchesthemainsystemclocktothelow-frequencyclockforSLOW2)CLR(SYSCR2).
7;SYSCR2←0(Turnsoffhigh-frequencyoscillation)Example2:SwitchingtotheSLOW1modeafterlow-frequencyclockhasstabilized.
SET(SYSCR2).
6;SYSCR2←1LD(TC3CR),43H;SetsmodeforTC4,3(16-bitmode,fsforsource)LD(TC4CR),05H;Setswarming-upcountermodeLDW(TTREG3),8000H;Setswarm-uptime(Dependonoscillatoraccompanied)DI;IMF←0SET(EIRE).
5;EnablesINTTC4EI;IMF←1SET(TC4CR).
3;StartsTC4,3:PINTTC4:CLR(TC4CR).
3;StopsTC4,3SET(SYSCR2).
5;SYSCR2←1(Switchesthemainsystemclocktothelow-frequencyclock)CLR(SYSCR2).
7;SYSCR2←0(Turnsoffhigh-frequencyoscillation)RETI:VINTTC4:DWPINTTC4;INTTC4vectortablePage29TMP86CS28FG(2)SwitchingfromSLOW1modetoNORMAL2modeNote:AfterSYSCKisclearedto"0",executingtheinstructionsiscontiniuedbythelow-frequencyclockfortheperiodsynchronizedwithlow-frequencyandhigh-frequencyclocks.
First,setSYSCR2toturnonthehigh-frequencyoscillation.
Whentimeforstabilization(Warmup)hasbeentakenbythetimer/counter(TC4,TC3),clearSYSCR2toswitchthemainsystemclocktothehigh-frequencyclock.
SLOWmodecanalsobereleasedbyinputtinglowlevelontheRESETpin.
Afterreleasingreset,theoperationmodeisstartedfromNORMAL1mode.
Example:SwitchingfromtheSLOW1modetotheNORMAL2mode(fc=16MHz,warm-uptimeis4.
0ms).
SET(SYSCR2).
7;SYSCR2←1(Startshigh-frequencyoscillation)LD(TC3CR),63H;SetsmodeforTC4,3(16-bitmode,fcforsource)LD(TC4CR),05H;Setswarming-upcountermodeLD(TTREG4),0F8H;Setswarm-uptimeDI;IMF←0SET(EIRE).
5;EnablesINTTC4EI;IMF←1SET(TC4CR).
3;StartsTC4,3:PINTTC4:CLR(TC4CR).
3;StopsTC4,3CLR(SYSCR2).
5;SYSCR2←0(Switchesthemainsystemclocktothehigh-frequencyclock)RETI:VINTTC4:DWPINTTC4;INTTC4vectortableHigh-frequencyclockLow-frequencyclockMainsystemclockSYSCKPage302.
OperationalDescription2.
2SystemClockControllerTMP86CS28FGFigure2-14SwitchingbetweentheNORMAL2andSLOWModesSET(SYSCR2).
7NORMAL2modeCLR(SYSCR2).
7SET(SYSCR2).
5NORMAL2modeTurnoff(a)SwitchingtotheSLOWmodeSLOW1modeSLOW2modeCLR(SYSCR2).
5(b)SwitchingtotheNORMAL2modeHigh-frequencyclockLow-frequencyclockMainsystemclockInstructionexecutionSYSCKXENHigh-frequencyclockLow-frequencyclockMainsystemclockInstructionexecutionSYSCKXENSLOW1modeWarmupduringSLOW2modePage31TMP86CS28FG2.
3ResetCircuitTheTMP86CS28FGhasfourtypesofresetgenerationprocedures:Anexternalresetinput,anaddresstrapreset,awatchdogtimerresetandasystemclockreset.
Ofthesereset,theaddresstrapreset,thewatchdogtimerandthesys-temclockresetareamalfunctionreset.
Whenthemalfunctionresetrequestisdetected,resetoccursduringthemax-imum24/fc[s].
Themalfunctionresetcircuitsuchaswatchdogtimerreset,addresstrapresetandsystemclockresetisnotinitial-izedwhenpoweristurnedon.
Therefore,resetmayoccurduringmaximum24/fc[s](1.
5sat16.
0MHz)whenpoweristurnedon.
Table2-3showson-chiphardwareinitializationbyresetaction.
2.
3.
1ExternalResetInputTheRESETpincontainsaSchmitttrigger(Hysteresis)withaninternalpull-upresistor.
WhentheRESETpinisheldat"L"levelforatleast3machinecycles(12/fc[s])withthepowersupplyvolt-agewithintheoperatingvoltagerangeandoscillationstable,aresetisappliedandtheinternalstateisinitial-ized.
WhentheRESETpininputgoeshigh,theresetoperationisreleasedandtheprogramexecutionstartsatthevectoraddressstoredataddressesFFFEHtoFFFFH.
Figure2-15ResetCircuitTable2-3InitializingInternalStatusbyResetActionOn-chipHardwareInitialValueOn-chipHardwareInitialValueProgramcounter(PC)(FFFEH)Prescaleranddivideroftiminggenerator0Stackpointer(SP)NotinitializedGeneral-purposeregisters(W,A,B,C,D,E,H,L,IX,IY)NotinitializedJumpstatusflag(JF)NotinitializedWatchdogtimerEnableZeroflag(ZF)NotinitializedOutputlatchesofI/OportsRefertoI/OportcircuitryCarryflag(CF)NotinitializedHalfcarryflag(HF)NotinitializedSignflag(SF)NotinitializedOverflowflag(VF)NotinitializedInterruptmasterenableflag(IMF)0Interruptindividualenableflags(EF)0ControlregistersRefertoeachofcontrolregisterInterruptlatches(IL)0LCDdatabufferNotinitializedRAMNotinitializedInternalresetRESETVDDMalfunctionresetoutputcircuitWatchdogtimerresetAddresstrapresetSystemclockresetPage322.
OperationalDescription2.
3ResetCircuitTMP86CS28FG2.
3.
2AddresstrapresetIftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whenWDTCR1issetto"1"),DBRortheSFRarea,addresstrapresetwillbegenerated.
Theresettimeismaximum24/fc[s](1.
5sat16.
0MHz).
Note:Theoperatingmodeunderaddresstrappedisalternativeofresetorinterrupt.
Theaddresstrapareaisalter-native.
Note1:Address"a"isintheSFR,DBRoron-chipRAM(WDTCR1="1")space.
Note2:Duringresetrelease,resetvector"r"isreadout,andaninstructionataddress"r"isfetchedanddecoded.
Figure2-16AddressTrapReset2.
3.
3WatchdogtimerresetRefertoSection"WatchdogTimer".
2.
3.
4SystemclockresetIftheconditionasfollowsisdetected,thesystemclockresetoccursautomaticallytopreventdeadlockoftheCPU.
(Theoscillationiscontinuedwithoutstopping.
)-IncaseofclearingSYSCR2andSYSCR2simultaneouslyto"0".
-IncaseofclearingSYSCR2to"0",whentheSYSCR2is"0".
-IncaseofclearingSYSCR2to"0",whentheSYSCR2is"1".
Theresettimeismaximum24/fc(1.
5sat16.
0MHz).
Instructionataddressr16/fc[s]maximum24/fc[s]InstructionexecutionInternalresetJPaResetreleaseAddresstrapisoccurred4/fcto12/fc[s]Page33TMP86CS28FGPage342.
OperationalDescription2.
3ResetCircuitTMP86CS28FGPage35TMP86CS28FG3.
InterruptControlCircuitTheTMP86CS28FGhasatotalof23interruptsourcesexcludingreset.
Interruptscanbenestedwithpriorities.
Fouroftheinternalinterruptsourcesarenon-maskablewhiletherestaremaskable.
Interruptsourcesareprovidedwithinterruptlatches(IL),whichholdinterruptrequests,andindependentvectors.
Theinterruptlatchissetto"1"bythegenerationofitsinterruptrequestwhichrequeststheCPUtoacceptitsinter-rupts.
Interruptsareenabledordisabledbysoftwareusingtheinterruptmasterenableflag(IMF)andinterruptenableflag(EF).
Ifmorethanoneinterruptsaregeneratedsimultaneously,interruptsareacceptedinorderwhichisdomi-natedbyhardware.
However,therearenoprioritizedinterruptfactorsamongnon-maskableinterrupts.
Note1:Tousetheaddresstrapinterrupt(INTATRAP),clearWDTCR1to"0"(Itissetforthe"resetrequest"afterresetiscancelled).
Fordetails,see"AddressTrap".
Note2:Tousethewatchdogtimerinterrupt(INTWDT),clearWDTCR1to"0"(Itissetforthe"Resetrequest"afterresetisreleased).
Fordetails,see"WatchdogTimer".
InterruptFactorsEnableConditionInterruptLatchVectorAddressPriorityInternal/External(Reset)Non-maskable–FFFE1InternalINTSWI(Softwareinterrupt)Non-maskable–FFFC2InternalINTUNDEF(Executedtheundefinedinstructioninterrupt)Non-maskable–FFFC2InternalINTATRAP(Addresstrapinterrupt)Non-maskableIL2FFFA2InternalINTWDT(Watchdogtimerinterrupt)Non-maskableIL3FFF82ExternalINT0IMFEF4=1,INT0EN=1IL4FFF65ExternalINT1IMFEF5=1IL5FFF46InternalINTTBTIMFEF6=1IL6FFF27InternalINTTC10IMFEF7=1IL7FFF08InternalINTRXD0IMFEF8=1IL8FFEE9InternalINTTXD0IMFEF9=1IL9FFEC10InternalINTTC11IMFEF10=1IL10FFEA11ExternalINT2IMFEF11=1IL11FFE812-ReservedIMFEF12=1IL12FFE613InternalINTSIOIMFEF13=1IL13FFE414-ReservedIMFEF14=1IL14FFE215-ReservedIMFEF15=1IL15FFE016-ReservedIMFEF16=1IL16FFBE17-ReservedIMFEF17=1IL17FFBC18-ReservedIMFEF18=1IL18FFBA19-ReservedIMFEF19=1IL19FFB820InternalINTTC3IMFEF20=1IL20FFB621InternalINTTC4IMFEF21=1IL21FFB422ExternalINT3IMFEF22=1IL22FFB223InternalINTTC5IMFEF23=1IL23FFB024InternalINTTC6IMFEF24=1IL24FFAE25ExternalINT4IMFEF25=1IL25FFAC26ExternalINT5IMFEF26=1IL26FFAA27InternalINTRXD1IMFEF27=1IL27FFA828InternalINTTXD1IMFEF28=1IL28FFA629InternalINTADCIMFEF29=1IL29FFA430-ReservedIMFEF30=1IL30FFA231-ReservedIMFEF31=1IL31FFA032Page363.
InterruptControlCircuit3.
1Interruptlatches(IL30toIL2)TMP86CS28FG3.
1Interruptlatches(IL30toIL2)Aninterruptlatchisprovidedforeachinterruptsource,exceptforasoftwareinterruptandanexecutedtheunde-finedinstructioninterrupt.
Wheninterruptrequestisgenerated,thelatchissetto"1",andtheCPUisrequestedtoaccepttheinterruptifitsinterruptisenabled.
Theinterruptlatchisclearedto"0"immediatelyafteracceptinginter-rupt.
Allinterruptlatchesareinitializedto"0"duringreset.
Theinterruptlatchesarelocatedonaddress002EH,002FH,003CHand003DHinSFRarea.
Eachlatchcanbeclearedto"0"individuallybyinstruction.
However,IL2andIL3shouldnotbeclearedto"0"bysoftware.
Forclear-ingtheinterruptlatch,loadinstructionshouldbeusedandthenIL2andIL3shouldbesetto"1".
Iftheread-modify-writeinstructionssuchasbitmanipulationoroperationinstructionsareused,interruptrequestwouldbeclearedinadequatelyifinterruptisrequestedwhilesuchinstructionsareexecuted.
Interruptlatchesarenotsetto"1"byaninstruction.
Sinceinterruptlatchescanberead,thestatusforinterruptrequestscanbemonitoredbysoftware.
Note:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninterruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexecutedbeforesettingIMF="1".
3.
2Interruptenableregister(EIR)Theinterruptenableregister(EIR)enablesanddisablestheacceptanceofinterrupts,exceptforthenon-maskableinterrupts(Softwareinterrupt,undefinedinstructioninterrupt,addresstrapinterruptandwatchdoginterrupt).
Non-maskableinterruptisacceptedregardlessofthecontentsoftheEIR.
TheEIRconsistsofaninterruptmasterenableflag(IMF)andtheindividualinterruptenableflags(EF).
Theseregistersarelocatedonaddress002CH,002DH,003AHand003BHinSFRarea,andtheycanbereadandwrittenbyaninstructions(Includingread-modify-writeinstructionssuchasbitmanipulationoroperationinstructions).
3.
2.
1Interruptmasterenableflag(IMF)Theinterruptenableregister(IMF)enablesanddisablestheacceptanceofthewholemaskableinterrupt.
WhileIMF="0",allmaskableinterruptsarenotacceptedregardlessofthestatusoneachindividualinterruptenableflag(EF).
BysettingIMFto"1",theinterruptbecomesacceptableiftheindividualsareenabled.
Whenaninterruptisaccepted,IMFisclearedto"0"afterthelateststatusonIMFisstacked.
Thusthemaskableinter-ruptswhichfollowaredisabled.
Byexecutingreturninterruptinstruction[RETI/RETN],thestackeddata,whichwasthestatusbeforeinterruptacceptance,isloadedonIMFagain.
TheIMFislocatedonbit0inEIRL(Address:003AHinSFR),andcanbereadandwrittenbyaninstruction.
TheIMFisnormallysetandclearedby[EI]and[DI]instructionrespectively.
Duringreset,theIMFisinitial-izedto"0".
Example1:ClearsinterruptlatchesDI;IMF←0LDW(ILL),1110100000111111B;IL12,IL10toIL6←0EI;IMF←1Example2:ReadsinterruptlatchessLDWA,(ILL);W←ILH,A←ILLExample3:TestsinterruptlatchesTEST(ILL).
7;ifIL7=1thenjumpJRF,SSETPage37TMP86CS28FG3.
2.
2Individualinterruptenableflags(EF30toEF4)Eachoftheseflagsenablesanddisablestheacceptanceofitsmaskableinterrupt.
Settingthecorrespondingbitofanindividualinterruptenableflagto"1"enablesacceptanceofitsinterrupt,andsettingthebitto"0"dis-ablesacceptance.
Duringreset,alltheindividualinterruptenableflags(EF30toEF4)areinitializedto"0"andallmaskableinterruptsarenotaccepteduntiltheyaresetto"1".
Note:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenor-mallyoninterruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulat-ingEForILshouldbeexecutedbeforesettingIMF="1".
Example1:EnablesinterruptsindividuallyandsetsIMFDI;IMF←0LDW:(EIRL),1110100010100000B;EF15toEF13,EF11,EF7,EF5←1Note:IMFshouldnotbeset.
:EI;IMF←1Example2:Ccompilerdescriptionexampleunsignedint_io(3AH)EIRL;/*3AHshowsEIRLaddress*/_DI();EIRL=10100000B;:_EI();Page383.
InterruptControlCircuit3.
2Interruptenableregister(EIR)TMP86CS28FGNote1:ToclearanyoneofbitsIL7toIL4,besuretowrite"1"intoIL2andIL3.
Note2:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninter-ruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexe-cutedbeforesettingIMF="1".
Note3:DonotclearILwithread-modify-writeinstructionssuchasbitoperations.
Note1:*:Don'tcareNote2:DonotsetIMFandtheinterruptenableflag(EF15toEF4)to"1"atthesametime.
Note3:Inmainprogram,beforemanipulatingtheinterruptenableflag(EF)ortheinterruptlatch(IL),besuretoclearIMFto"0"(DisableinterruptbyDIinstruction).
ThensetIMFnewlyagainasrequiredafteroperatingontheEForIL(EnableinterruptbyEIinstruction)Ininterruptserviceroutine,becausetheIMFbecomes"0"automatically,clearingIMFneednotexecutenormallyoninter-ruptserviceroutine.
However,ifusingmultipleinterruptoninterruptserviceroutine,manipulatingEForILshouldbeexe-cutedbeforesettingIMF="1".
InterruptLatches(Initialvalue:**0*0000000000**)ILH,ILL(003DH,003CH)1514131211109876543210IL13IL11IL10IL9IL8IL7IL6IL5IL4IL3IL2ILH(003DH)ILL(003CH)(Initialvalue:**0000000000****)ILD,ILE(002FH,002EH)1514131211109876543210IL29IL28IL27IL26IL25IL24IL23IL22IL21IL20ILD(002FH)ILE(002EH)IL30toIL2InterruptlatchesatRD0:Nointerruptrequest1:InterruptrequestatWR0:Clearstheinterruptrequest1:(Interruptlatchisnotset.
)R/WInterruptEnableRegisters(Initialvalue:**0*00000000***0)EIRH,EIRL(003BH,003AH)1514131211109876543210EF13EF11EF10EF9EF8EF7EF6EF5EF4IMFEIRH(003BH)EIRL(003AH)(Initialvalue:**0000000000****)EIRD,EIRE(002DH,002CH)1514131211109876543210EF29EF28EF27EF26EF25EF24EF23EF22EF21EF20EIRD(002DH)EIRE(002CH)EF30toEF4Individual-interruptenableflag(Specifiedforeachbit)0:1:Disablestheacceptanceofeachmaskableinterrupt.
Enablestheacceptanceofeachmaskableinterrupt.
R/WIMFInterruptmasterenableflag0:1:DisablestheacceptanceofallmaskableinterruptsEnablestheacceptanceofallmaskableinterruptsPage39TMP86CS28FG3.
3InterruptSequenceAninterruptrequest,whichraisedinterruptlatch,isheld,untilinterruptisacceptedorinterruptlatchisclearedto"0"byresettingoraninstruction.
Interruptacceptancesequencerequires8machinecycles(2s@16MHz)afterthecompletionofthecurrentinstruction.
Theinterruptservicetaskterminatesuponexecutionofaninterruptreturninstruction[RETI](formaskableinterrupts)or[RETN](fornon-maskableinterrupts).
Figure3-1showsthetimingchartofinterruptacceptanceprocessing.
3.
3.
1Interruptacceptanceprocessingispackagedasfollows.
a.
Theinterruptmasterenableflag(IMF)isclearedto"0"inordertodisabletheacceptanceofanyfol-lowinginterrupt.
b.
Theinterruptlatch(IL)fortheinterruptsourceacceptedisclearedto"0".
c.
Thecontentsoftheprogramcounter(PC)andtheprogramstatusword,includingtheinterruptmasterenableflag(IMF),aresaved(Pushed)onthestackinsequenceofPSW+IMF,PCH,PCL.
Mean-while,thestackpointer(SP)isdecrementedby3.
d.
Theentryaddress(Interruptvector)ofthecorrespondinginterruptserviceprogram,loadedonthevec-tortable,istransferredtotheprogramcounter.
e.
Theinstructionstoredattheentryaddressoftheinterruptserviceprogramisexecuted.
Note:WhenthecontentsofPSWaresavedonthestack,thecontentsofIMFarealsosaved.
Note1:a:Returnaddressentryaddress,b:Entryaddress,c:AddresswhichRETIinstructionisstoredNote2:Onconditionthatinterruptisenabled,ittakes38/fc[s]or38/fs[s]atmaximum(Iftheinterruptlatchissetatthefirstmachinecycleon10cycleinstruction)tostartinterruptacceptanceprocessingsinceitsinterruptlatchisset.
Figure3-1TimingChartofInterruptAcceptance/ReturnInterruptInstructionExample:CorrespondencebetweenvectortableaddressforINTTBTandtheentryaddressoftheinterruptserviceprogramFigure3-2Vectortableaddress,Entryaddressabac+1ExecuteinstructionSPPCExecuteinstructionnn2n-3n2n1n1na+2a+1c+2b+3b+2b+1a+1aa1ExecuteRETIinstructionInterruptacceptanceExecuteinstructionInterruptservicetask1-machinecycleInterruptrequestInterruptlatch(IL)IMFD2H03HD203HD204H06HVectortableaddressEntryaddress0FHVectorInterruptserviceprogramFFF2HFFF3HPage403.
InterruptControlCircuit3.
3InterruptSequenceTMP86CS28FGAmaskableinterruptisnotaccepteduntiltheIMFissetto"1"evenifthemaskableinterrupthigherthanthelevelofcurrentservicinginterruptisrequested.
Inordertoutilizenestedinterruptservice,theIMFissetto"1"intheinterruptserviceprogram.
Inthiscase,acceptableinterruptsourcesareselectivelyenabledbytheindividualinterruptenableflags.
Toavoidoverloadednesting,cleartheindividualinterruptenableflagwhoseinterruptiscurrentlyserviced,beforesettingIMFto"1".
Asfornon-maskableinterrupt,keepinterruptserviceshortencomparedwithlengthbetweeninterruptrequests;otherwisethestatuscannotberecoveredasnon-maskableinterruptwouldsimplynested.
3.
3.
2Saving/restoringgeneral-purposeregistersDuringinterruptacceptanceprocessing,theprogramcounter(PC)andtheprogramstatusword(PSW,includesIMF)areautomaticallysavedonthestack,buttheaccumulatorandothersarenot.
Theseregistersaresavedbysoftwareifnecessary.
Whenmultipleinterruptservicesarenested,itisalsonecessarytoavoidusingthesamedatamemoryareaforsavingregisters.
Thefollowingmethodsareusedtosave/restorethegeneral-purposeregisters.
3.
3.
2.
1UsingPUSHandPOPinstructionsIfonlyaspecificregisterissavedorinterruptsofthesamesourcearenested,general-purposeregisterscanbesaved/restoredusingthePUSH/POPinstructions.
Figure3-3Save/storeregisterusingPUSHandPOPinstructions3.
3.
2.
2UsingdatatransferinstructionsTosaveonlyaspecificregisterwithoutnestedinterrupts,datatransferinstructionsareavailable.
Example:Save/storeregisterusingPUSHandPOPinstructionsPINTxx:PUSHWA;SaveWAregister(interruptprocessing)POPWA;RestoreWAregisterRETI;RETURNPCLPCHPSWAtacceptanceofaninterruptAtexecutionofPUSHinstructionAtexecutionofRETIinstructionAtexecutionofPOPinstructionb-4b-3b-2b-1bPCLPCHPSWPCLPCHPSWSPAddress(Example)SPSPSPAWb-5Page41TMP86CS28FGFigure3-4Saving/RestoringGeneral-purposeRegistersunderInterruptProcessing3.
3.
3InterruptreturnInterruptreturninstructions[RETI]/[RETN]performasfollows.
Asforaddresstrapinterrupt(INTATRAP),itisrequiredtoalterstackeddataforprogramcounter(PC)torestartingaddress,duringinterruptserviceprogram.
Note:If[RETN]isexecutedwiththeabovedataunaltered,theprogramreturnstotheaddresstrapareaandINTATRAPoccursagain.
Wheninterruptacceptanceprocessinghascompleted,stackeddataforPCLandPCHarelocatedonaddress(SP+1)and(SP+2)respectively.
Example:Save/storeregisterusingdatatransferinstructionsPINTxx:LD(GSAVA),A;SaveAregister(interruptprocessing)LDA,(GSAVA);RestoreAregisterRETI;RETURN[RETI]/[RETN]InterruptReturn1.
Programcounter(PC)andprogramstatusword(PSW,includesIMF)arerestoredfromthestack.
2.
Stackpointer(SP)isincrementedby3.
Example1:Returningfromaddresstrapinterrupt(INTATRAP)serviceprogramPINTxx:POPWA;RecoverSPby2LDWA,ReturnAddress;PUSHWA;Alterstackeddata(interruptprocessing)RETN;RETURNInterruptacceptanceInterruptservicetaskRestoringregistersSavingregistersInterruptreturnSaving/Restoringgeneral-purposeregistersusingPUSH/POPdatatransferinstructionMaintaskPage423.
InterruptControlCircuit3.
4SoftwareInterrupt(INTSW)TMP86CS28FGInterruptrequestsaresampledduringthefinalcycleoftheinstructionbeingexecuted.
Thus,thenextinter-ruptcanbeacceptedimmediatelyaftertheinterruptreturninstructionisexecuted.
Note1:ItisrecommendedthatstackpointerbereturntoratebeforeINTATRAP(Increment3times),ifreturninter-ruptinstruction[RETN]isnotutilizedduringinterruptserviceprogramunderINTATRAP(suchasExample2).
Note2:Whentheinterruptprocessingtimeislongerthantheinterruptrequestgenerationtime,theinterruptservicetaskisperformedbutnotthemaintask.
3.
4SoftwareInterrupt(INTSW)ExecutingtheSWIinstructiongeneratesasoftwareinterruptandimmediatelystartsinterruptprocessing(INTSWishighestprioritizedinterrupt).
UsetheSWIinstructiononlyfordetectionoftheaddresserrororfordebugging.
3.
4.
1AddresserrordetectionFFHisreadifforsomecausesuchasnoisetheCPUattemptstofetchaninstructionfromanon-existentmemoryaddressduringsinglechipmode.
CodeFFHistheSWIinstruction,soasoftwareinterruptisgener-atedandanaddresserrorisdetected.
TheaddresserrordetectionrangecanbefurtherexpandedbywritingFFHtounusedareasoftheprogrammemory.
AddresstrapresetisgeneratedincasethataninstructionisfetchedfromRAM,DBRorSFRareas.
3.
4.
2DebuggingDebuggingefficiencycanbeincreasedbyplacingtheSWIinstructionatthesoftwarebreakpointsettingaddress.
3.
5UndefinedInstructionInterrupt(INTUNDEF)TakingcodewhichisnotdefinedasauthorizedinstructionforinstructioncausesINTUNDEF.
INTUNDEFisgen-eratedwhentheCPUfetchessuchacodeandtriestoexecuteit.
INTUNDEFisacceptedevenifnon-maskableinter-ruptisinprocess.
ContemporaryprocessisbrokenandINTUNDEFinterruptprocessstarts,soonafteritisrequested.
Note:Theundefinedinstructioninterrupt(INTUNDEF)forcesCPUtojumpintovectoraddress,assoftwareinterrupt(SWI)does.
3.
6AddressTrapInterrupt(INTATRAP)Fetchinginstructionfromunauthorizedareaforinstructions(Addresstrappedarea)causesresetoutputoraddresstrapinterrupt(INTATRAP).
INTATRAPisacceptedevenifnon-maskableinterruptisinprocess.
Contemporarypro-cessisbrokenandINTATRAPinterruptprocessstarts,soonafteritisrequested.
Note:Theoperatingmodeunderaddresstrapped,whethertoberesetoutputorinterruptprocessing,isselectedonwatchdogtimercontrolregister(WDTCR).
Example2:Restartingwithoutreturninginterrupt(Inthiscase,PSW(IncludesIMF)beforeinterruptacceptanceisdiscarded.
)PINTxx:INCSP;RecoverSPby3INCSP;INCSP;(interruptprocessing)LDEIRL,data;SetIMFto"1"orclearitto"0"JPRestartAddress;JumpintorestartingaddressPage43TMP86CS28FG3.
7ExternalInterruptsTheTMP86CS28FGhas6externalinterruptinputs.
Theseinputsareequippedwithdigitalnoiserejectcircuits(Pulseinputsoflessthanacertaintimeareeliminatedasnoise).
EdgeselectionisalsopossiblewithINT1toINT4.
TheINT0/P30pincanbeconfiguredaseitheranexternalinter-ruptinputpinoraninput/outputport,andisconfiguredasaninputportduringreset.
Edgeselection,noiserejectcontrolandINT0/P30pinfunctionselectionareperformedbytheexternalinterruptcontrolregister(EINTCR).
Note1:InNORMAL1/2orIDLE1/2mode,ifasignalwithnonoiseisinputonanexternalinterruptpin,ittakesamaximumof"sig-nalestablishmenttime+6/fs[s]"fromtheinputsignal'sedgetosettheinterruptlatch.
Note2:WhenINT0EN="0",IL4isnotsetevenifafallingedgeisdetectedontheINT0pininput.
Note3:Whenapinwithmorethanonefunctionisusedasanoutputandachangeoccursindataorinput/outputstatus,aninter-ruptrequestsignalisgeneratedinapseudomanner.
Inthiscase,itisnecessarytoperformappropriateprocessingsuchasdisablingtheinterruptenableflag.
SourcePinEnableConditionsReleaseEdge(level)DigitalNoiseRejectINT0INT0IMFEF4INT0EN=1FallingedgePulsesoflessthan2/fc[s]areeliminatedasnoise.
Pulsesof7/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT1INT1IMFEF5=1FallingedgeorRisingedgePulsesoflessthan15/fcor63/fc[s]areelimi-natedasnoise.
Pulsesof49/fcor193/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsideredtobesignals.
INT2INT2IMFEF11=1FallingedgeorRisingedgePulsesoflessthan7/fc[s]areeliminatedasnoise.
Pulsesof25/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT3INT3IMFEF22=1FallingedgeorRisingedgePulsesoflessthan7/fc[s]areeliminatedasnoise.
Pulsesof25/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT4INT4IMFEF25=1Fallingedge,Risingedge,FallingandRisingedgeorHlevelPulsesoflessthan7/fc[s]areeliminatedasnoise.
Pulsesof25/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
INT5INT5IMFEF26=1FallingedgePulsesoflessthan2/fc[s]areeliminatedasnoise.
Pulsesof7/fc[s]ormoreareconsideredtobesignals.
IntheSLOWortheSLEEPmode,pulsesoflessthan1/fs[s]areeliminatedasnoise.
Pulsesof3.
5/fs[s]ormoreareconsid-eredtobesignals.
Page443.
InterruptControlCircuit3.
7ExternalInterruptsTMP86CS28FGNote1:fc:High-frequencyclock[Hz],*:Don'tcareNote2:Whenthesystemclockfrequencyisswitchedbetweenhighandloworwhentheexternalinterruptcontrolregister(EINTCR)isoverwritten,thenoisecancellermaynotoperatenormally.
Itisrecommendedthatexternalinterruptsaredis-abledusingtheinterruptenableregister(EIR).
Note3:ThemaximumtimefrommodifyingINT1NCuntilanoiserejecttimeischangedis26/fc.
Note4:IncaseRESETpinisreleasedwhilethestateofINT4pinkeeps"H"level,theexternalinterrupt4requestisnotgeneratedeveniftheINT4edgeselectisspecifiedas"H"level.
TherisingedgeisneededafterRESETpinisreleased.
ExternalInterruptControlRegisterEINTCR76543210(0037H)INT1NCINT0ENINT4ESINT3ESINT2ESINT1ES(Initialvalue:0000000*)INT1NCNoiserejecttimeselect0:Pulsesoflessthan63/fc[s]areeliminatedasnoise1:Pulsesoflessthan15/fc[s]areeliminatedasnoiseR/WINT0ENP30/INT0pinconfiguration0:P30input/outputport1:INT0pin(PortP30shouldbesettoaninputmode)R/WINT4ESINT4edgeselect00:Risingedge01:Fallingedge10:RisingedgeandFallingedge11:HlevelR/WINT3ESINT3edgeselect0:Risingedge1:FallingedgeR/WINT2ESINT2edgeselect0:Risingedge1:FallingedgeR/WINT1ESINT1edgeselect0:Risingedge1:FallingedgeR/WPage45TMP86CS28FG4.
SpecialFunctionRegister(SFR)TheTMP86CS28FGadoptsthememorymappedI/Osystem,andallperipheralcontrolanddatatransfersareper-formedthroughthespecialfunctionregister(SFR)orthedatabufferregister(DBR).
TheSFRismappedonaddress0000Hto003FH,DBRismappedonaddress0F00Hto0FFFH.
Thischaptershowsthearrangementofthespecialfunctionregister(SFR)anddatabufferregister(DBR)forTMP86CS28FG.
4.
1SFRAddressReadWrite0000HP0DR0001HP1DR0002HP2DR0003HP3DR0004HP4DR0005HP5DR0006HP6DR0007HP7DR0008HP8DR0009HTC3CR000AHTC4CR000BHTC5CR000CHTC6CR000DHReserved000EHReserved000FHReserved0010HTC10DRAL0011HTC10DRAH0012HTC10DRBL0013HTC10DRBH0014HTC10CR0015HTTREG30016HTTREG40017HTTREG50018HTTREG60019HPWREG3001AHPWREG4001BHPWREG5001CHPWREG6001DHReserved001EHReserved001FHReserved0020HTC11DRAL0021HTC11DRAH0022HTC11DRBL0023HTC11DRBH0024HTC11CR0025HReservedPage464.
SpecialFunctionRegister(SFR)4.
1SFRTMP86CS28FGNote1:Donotaccessreservedareasbytheprogram.
Note2:;Cannotbeaccessed.
Note3:Write-onlyregistersandinterruptlatchescannotusetheread-modify-writeinstructions(BitmanipulationinstructionssuchasSET,CLR,etc.
andlogicaloperationinstructionssuchasAND,OR,etc.
).
0026HReserved0027HReserved0028HReserved0029HReserved002AHReserved002BHP3OUTCR002CHEIRE002DHEIRD002EHILE002FHILD0030HReserved0031H-STOPCR0032HP0OUTCR0033HReserved0034H-WDTCR10035H-WDTCR20036HTBTCR0037HEINTCR0038HSYSCR10039HSYSCR2003AHEIRL003BHEIRH003CHILL003DHILH003EHReserved003FHPSWAddressReadWritePage47TMP86CS28FG4.
2DBRAddressReadWrite0F00HReserved::::0F5FHReservedAddressReadWrite0F60HSIOBR00F61HSIOBR10F62HSIOBR20F63HSIOBR30F64HSIOBR40F65HSIOBR50F66HSIOBR60F67HSIOBR70F68H-SIOCR10F69HSIOSRSIOCR2AddressReadWrite0F70HReserved::::0F7FHReservedPage484.
SpecialFunctionRegister(SFR)4.
2DBRTMP86CS28FGAddressReadWrite0F80HReserved::::0F9FHReservedAddressReadWrite0FA0HReserved::::0FBFHReservedAddressReadWrite0FC0HSEG1/00FC1HSEG3/20FC2HSEG5/40FC3HSEG7/60FC4HSEG9/80FC5HSEG11/100FC6HSEG13/120FC7HSEG15/140FC8HSEG17/160FC9HSEG19/180FCAHSEG21/200FCBHSEG23/220FCCHSEG25/240FCDHSEG27/260FCEHSEG29/280FCFHSEG31/300FD0HSEG33/320FD1HSEG35/340FD2HSEG37/360FD3HSEG39/380FD4HP4LCR0FD5HP5LCR0FD6HP6LCR0FD7HP7LCR0FD8HP8LCR0FD9HLCDCR0FDAHReserved0FDBHReserved0FDCHReserved0FDDHReserved0FDEHReserved0FDFHReservedPage49TMP86CS28FGNote1:Donotaccessreservedareasbytheprogram.
Note2:;Cannotbeaccessed.
Note3:Write-onlyregistersandinterruptlatchescannotusetheread-modify-writeinstructions(BitmanipulationinstructionssuchasSET,CLR,etc.
andlogicaloperationinstructionssuchasAND,OR,etc.
).
AddressReadWrite0FE0HADCDR2-0FE1HADCDR1-0FE2HADCCR10FE3HADCCR20FE4HReserved0FE5HUART0SRUART0CR10FE6H-UART0CR20FE7HRD0BUFTD0BUF0FE8HUART1SRUART1CR10FE9H-UART1CR20FEAHRD1BUFTD1BUF0FEBHReserved0FECHReserved0FEDHReserved0FEEHReserved0FEFHReserved0FF0HP0PRD-0FF1HReserved0FF2HP2PRD-0FF3HP3PRD-0FF4HP4PRD-0FF5HP5PRD-0FF6HP6PRD-0FF7HP7PRD-0FF8HP8PRD-0FF9HP1CR10FFAHP1CR20FFBHP4OUTCR0FFCHP5OUTCR0FFDHP6OUTCR0FFEHP7OUTCR0FFFHP8OUTCRPage504.
SpecialFunctionRegister(SFR)4.
2DBRTMP86CS28FGPage51TMP86CS28FG5.
I/OPortsTheTMP86CS28FGhas9input/outputports(62pins)asshownbelow.
Table5-1PortFunctionsPrimaryFunctionSecondaryFunctionsPortP03-bitinput/outputportExternalinterruptinput,PPGoutputPortP18-bitinput/outputportAnaloginput,STOPmodereleasesignalinputPortP23-bitinput/outputportExternalinterruptinput,low-frequencyresonatorconnection,STOPmodereleasesignalinputPortP38-bitinput/outputportExternalinterruptinput,timer/counterinput,serialinterfaceinput/output,UARTinput/output,divideroutputPortP48-bitinput/outputportExternalinterruptinput,timer/counterinput,LCDsegmentoutput,PPGoutputPortP58-bitinput/outputportTimer/counterinput/output,LCDsegmentoutput,UARTinput/outputPortP68-bitinput/outputportLCDsegmentoutputPortP78-bitinput/outputportLCDsegmentoutputPortP88-bitinput/outputportLCDsegmentoutputTable5-2RegisterListPortLatchReadPchControlCR1CR2LCDControlP0P0DR(0000H)P0PRD(0FF0H)P0OUTCR(0032H)P1P1DR(0001H)P1CR1(0FF9H)P1CR2(0FFAH)P2P2DR(0002H)P2PRD(0FF2H)P3P3DR(0003H)P3PRD(0FF3H)P3OUTCR(002BH)P4P4DR(0004H)P4PRD(0FF4H)P4OUTCR(0FFBH)P4LCR(0FD4H)P5P5DR(0005H)P5PRD(0FF5H)P5OUTCR(0FFCH)P5LCR(0FD5H)P6P6DR(0006H)P6PRD(0FF6H)P6OUTCR(0FFDH)P6LCR(0FD6H)P7P7DR(0007H)P7PRD(0FF7H)P7OUTCR(0FFEH)P7LCR(0FD7H)P8P8DR(0008H)P8PRD(0FF8H)P8OUTCR(0FFFH)P8LCR(0FD8H)Page525.
I/OPortsTMP86CS28FGEachoutputportcontainsalatchforholdingoutputdata.
Allinputportsdonothavelatches,makingitnecessarytoexternallyholdinputdatauntilitisreadexternallyortoreadinputdatamultipletimesbeforeitisprocessed.
Fig-ure5-1showsinput/outputtimings.
Externaldataisreadfromaninput/outputportintheS1stateofthereadcycleininstructionexecution.
Sincethistimingcannotberecognizedexternally,transientinputsuchaschatteringmustbeprocessedbysoftware.
Dataisout-puttoaninput/outputportintheS2stateofthewritecycleininstructionexecution.
Note:Thepositionsofthereadandwritecyclesmayvarydependingontheinstruction.
Figure5-1Input/OutputTimings(Example)InstructionexecutioncycleInputstrobeDatainputEx:LDA,(x)FetchcycleFetchcycleReadcycleS0S1S2S3S0S1S2S3S0S1S2S3InstructionexecutioncycleOutputlatchpulseDataoutputEx:LD(x),AFetchcycleFetchcycleWritecycleS0S1S2S3S0S1S2S3S0S1S2S3(a)Inputtiming(b)OutputtimingPage53TMP86CS28FG5.
1PortP0(P00toP02)PortP0isa3-bitinput/outputportthatcanalsobeusedforexternalinterruptinputorPPGoutput.
Aresetinitializestheoutputlatch(P0DR)to"1"andthePchcontrol(P0OUTCR)to"0".
TouseapininPortP0asaninputportorexternalinterruptinput,setP0DRto"1"andthensetthecorrespondingbitinP0OUTCRto"0".
TouseapininPortP0asaPPGoutput,setP0DRto"1".
TheoutputcircuitofPortP0canbeseteitherassinkopen-drainoutput("0")orCMOSoutput("1")individuallyforeachbitinP0OUTCR.
PortP0hasaseparatedatainputregister.
TheoutputlatchstatecanbereadfromtheP0DRregister,andthepinstatecanbereadfromtheP0PRDregister.
Figure5-2PortP0Table5-3RegisterProgrammingforPortP0(P00toP02)FunctionProgrammedValueP0DRP0OUTCRPortinput,externalinterruptinput"1""0"Port"0"output"0"Setasappropriate.
Port"1"output,PPGoutput"1"Datainput(P0PRD)Outputlatchread(P0DR)STOPOUTENP0OUTCRiinputDataoutput(P0DR)P0OUTCRiP0iNote)i=2~0DQDQControloutputControlinputOutputlatchPage545.
I/OPorts5.
1PortP0(P00toP02)TMP86CS28FGP0DR(0000H)R/W76543210P02PPG1INT3P01P00(Initialvalue:*****111)P0OUTCR(0032H)R/W76543210(Initialvalue:*****000)P0OUTCRPortP0input/outputcontrol(setforeachbitindividually)0:Sinkopen-drainoutput1:CMOSoutputR/WP0PRD(0FF0H)76543210P02P01P00(Initialvalue:*****000)ReadonlyPage55TMP86CS28FG5.
2PortP1(P10toP17)PortP1isan8-bitinput/outputportthatcanbeconfiguredasaninputoranoutputonabitbasis.
PortP1isalsousedforanaloginputorkey-onwake-upinput.
ThePortP1input/outputcontrolregister(P1CR1)andPortP1inputcontrolregister(P1CR2)areusedtospecifythefunctionofeachpin.
AresetinitializesP1CR1to"0",P1CR2to"1",andtheoutputlatch(P1DR)to"0"sothatPortP1becomesaninputport.
TouseapininPortP1asaninputport,setP1CR1to"0"andthensetP1CR2to"1".
TouseapininPortP1asananaloginputorkey-onwake-upinput,setP1CR1to"0"andthensetP1CR2to"0".
TouseapininPortP1asanoutputport,setthecorrespondingbitinP1CR1to"1".
Toreadtheoutputlatchdata,setP1CR1to"1"andreadP1DR.
Toreadthepinstate,setP1CR1to"0"andP1CR2to"1"andthenreadP1DR.
WhenP1CR1="0"andP1CR2="0",P1DRisreadas"0".
Bitsnotusedasanaloginputsareusedasinput/outputpins.
DuringADconversion,however,outputinstructionsmustnotbeexecutedtoensuretheaccuracyofconversionresults.
Also,duringADconversion,donotinputsignalsthatfluctuatewidelytopinsnearanaloginputpins.
Note:Anasterisk(*)indicatesthateither"1"or"0"canbeset.
Table5-4RegisterProgrammingforPortP1(P10toP17)FunctionProgrammedValueP1DRP1CR1P1CR2Portinput*"0""1"Analoginput,key-onwake-upinput*"0""0"Port"0"output"0""1"*Port"1"output"1""1"*Table5-5ValuesReadfromP1DRaccordingtoRegisterProgrammingConditionsValuesReadfromP1DRP1CR1P1CR2"0""0""0""0""1"Pinstate"1""0"Outputlatchstate"1"Page565.
I/OPorts5.
2PortP1(P10toP17)TMP86CS28FGFigure5-3PortP1Note1:Pinssettoinputmodereadthepininputdata.
Therefore,whenbothinputandoutputmodesareusedinPortP1,thecontentsoftheoutputlatchofapinsettoinputmodemaybeoverwrittenbyabitmanipulationinstruction.
Note2:Forapinusedasananaloginput,besuretoclearthecorrespondingbitinP1CR2to"0"topreventflow-throughcurrent.
Note3:Forapinusedasananaloginput,donotsetP1CR1to"1"(portoutput)topreventthepinfrombecomingshortedwithanexternalsignal.
Note4:Pinsnotusedasanaloginputscanbeusedasinput/outputpins.
DuringADconversion,however,outputinstruc-tionsmustnotbeexecutedtoensuretheaccuracyofconversionresults.
Also,duringADconversion,donotinputsignalsthatfluctuatewidelytopinsnearanaloginputpins.
Dataoutput(P1DR)Datainput(P1DR)STOPOUTENAINDSSAINP1CR2iinputP1CR1iinputPCR2iP1CR1iP1iNote1)i=0,1,6,7:j=2~5:k=2~5Note2)STOP=bit7inSYSCR1Note3)SAIN=ADinputselectsignalNote4)STOPk=inputselectsignalforkey-onwake-upKey-onwake-upDataoutput(P1DR)Datainput(P1DR)STOPSTOPkOUTENAINDSSAINP1CR2jinputP1CR1jinputP1CR2jP1CR1jP1jDQDQDQDQDQDQAnaloginputAnaloginputPage57TMP86CS28FGP1DR(0001H)R/W76543210P17AIN7P16AIN6P15AIN5STOP5P14AIN4STOP4P13AIN3STOP3P12AIN2STOP2P11AIN1P10AIN0(Initialvalue:00000000)P1CR1(0FF9H)76543210(Initialvalue:00000000)P1CR1PortP1input/outputcontrol(setforeachbitindividually)0:Portinput,key-onwake-upinput,analoginput1:PortoutputR/WP1CR2(0FFAH)76543210(Initialvalue:11111111)P1CR2PortP1inputcontrol(setforeachbitindividually)0:Analoginput,key-onwake-upinput1:PortinputR/WPage585.
I/OPorts5.
3PortP2(P20toP22)TMP86CS28FG5.
3PortP2(P20toP22)PortP2isa3-bitinput/outputportthatcanalsobeusedforexternalinterruptinput,STOPmodereleasesignalinput,orlow-frequencyresonatorconnection.
TousePortP2asaninputportorfunctionpins,settheoutputlatch(P2DR)to"1".
AresetinitializesP2DRto"1".
Inthedualclockmode,pinsP21(XTIN)andP22(XOUT)areconnectedwithalow-frequencyresonator(32.
768kHz).
Inthesingleclockmode,pinsP21andP22canbeusedasnormalinput/outputportpins.
ItisrecommendedthatpinP20beusedasanexternalinterruptinput,STOPreleasesignalinput,orinputport.
(WhenP20isusedasanoutputport,theinterruptlatchissetonthefallingedgeoftheoutputpulse.
)PortP2hasaseparatedatainputregister.
TheoutputlatchstatecanbereadfromtheP2DRregister,andthepinstatecanbereadfromtheP2PRDregister.
WhenareadinstructionisexecutedonP2DRorP2PRD,bits7to3arereadasundefined.
Figure5-4PortP2Note:SincepinP20isalsousedasaSTOPpin,theoutputofP20becomeshigh-impedanceinSTOPmoderegardlessoftheOUTENstate.
P2DR(0002H)R/W76543210P22XTOUTP21XTINP20INT5STOP(Initialvalue:*****111)P2PRD(0FF2H)Readonly76543210P22P21P20Datainput(P20PRD)Outputlatchread(P21)Dataoutput(P21)Dataoutput(P20)Datainput(P20)Datainput(P21PRD)Outputlatchread(P22)Datainput(P22PRD)Dataoutput(P22)STOPOUTENXTENfsP22(XTOUT)P21(XTIN)P20(INT5,STOP)ControlinputOutputlatchOutputlatchOutputlatchOsc.
enableDQDQDQPage59TMP86CS28FG5.
4PortP3(P30toP37)PortP3isan8-bitinput/outputportthatcanalsobeusedforexternalinterruptinput,divideroutput,timer/counterinput,serialinterfaceinput/output,orUARTinput/output.
Aresetinitializestheoutputlatch(P3DR)to"1"andthePchcontrol(P3OUTCR)to"0".
TouseapininPortP3asanexternalinterruptinput,timer/counterinput,serialinterfaceinput,orUARTinput,setP3DRto"1"andthensetthecorrespondingbitinP3OUTCRto"0".
TouseapininPortP3asadivideroutput,serialinterfaceoutput,orUARToutput,setP3DRto"1".
Port3canbeusedforeitherSIOorUART,sobesurenottoenablebothofthesefunctionsatthesametime.
TheoutputcircuitofPortP3canbeseteitherassinkopen-drainoutput("0")orCMOSoutput("1")individuallyforeachbitinP3OUTCR.
PortP3hasaseparatedatainputregister.
TheoutputlatchstatecanbereadfromtheP3DRregister,andthepinstatecanbereadfromtheP3PRDregister.
Figure5-5PortP3Table5-6RegisterProgrammingforPortP3(P30toP37)FunctionProgrammedValueP3DRP3OUTCRPortinput,externalinterruptinput,timer/counterinput,serialinterfaceinput,UARTinput"1""0"Port"0"output"0"Setasappropriate.
Port"1"output,serialinterfaceoutput,UARToutput,divideroutput"1"Datainput(P3PRD)Outputlatchread(P3DR)STOPOUTENP3OUTCRiinputDataoutput(P3DR)P3OUTCRiP3iNote)i=7~0ControloutputControlinputOutputlatchDQDQPage605.
I/OPorts5.
4PortP3(P30toP37)TMP86CS28FGP3DR(0003H)R/W76543210P37TC10INT4P36SCKP35SITXD1P34SORXD1P33P32P31DVOP30INT0(Initialvalue:11111111)P3OUTCR(002BH)76543210(Initialvalue:00000000)P3OUTCRPortP3outputcircuitcontrol(setforeachbitindividually)0:Sinkopen-drainoutput1:CMOSoutputR/WP3PRD(0FF3H)Readonly76543210P37P36P35P34P33P32P31P30Page61TMP86CS28FG5.
5PortP4(P40toP47)PortP4isan8-bitinput/outputportthatcanalsobeusedforexternalinterruptinput,PPGoutput,timer/counterinput,orLCDsegmentoutput.
Aresetinitializestheoutputlatch(P4DR)to"1",thePchcontrol(P4OUTCR)to"0",andtheLCDoutputcontrolregister(P4LCR)to"0".
TouseapininPortP4asaninputport,externalinterruptinput,ortimer/counterinput,setP4DRto"1"andthensetthecorrespondingbitinP4LCRandP4OUTCRto"0".
TouseapininPortP4asanLCDsegmentoutput,setthecorrespondingbitinP4LCRto"1".
TouseapininPortP4asaPPGoutput,setP4DRto"1"andthensetthecorrespondingbitinP4LCRto"0".
TheoutputcircuitofPortP4canbeseteitherassinkopen-drainoutut("0")orCMOSoutput("1")individuallyforeachbitinP4OUTCR.
PortP4hasaseparatedatainputregister.
TheoutputlatchstatecanbereadfromtheP4DRregister,andthepinstatecanbereadfromtheP4PRDregister.
Note:Anasterisk(*)indicatesthateither"1"or"0"canbeset.
Figure5-6PortP4Table5-7RegisterProgrammingforPortP4(P40toP47)FunctionProgrammedValueP4DRP4OUTCRP4LCRPortinput,externalinterruptinput,timer/counterinput"1""0""0"Port"0"output"0"Setasappropriate.
"0"Port"1"output"1""0"PPGoutput"1""0"LCDsegmentoutput**"1"Datainput(P4PRD)Outputlatchread(P4DR)STOPOUTENP4OUTCRiinputDataoutput(P4DR)P4OUTCRiP4iNote)i=7~0DQDQLCDdataoutputP4LCRiDQP4LCRiinputControloutputControlinputOutputlatchPage625.
I/OPorts5.
5PortP4(P40toP47)TMP86CS28FGP4DR(0004H)R/W76543210P47SEG32P46SEG31P45SEG30P44SEG29P43SEG28TC11P42SEG27PPG1P41SEG26INT2P40SEG25INT1(Initialvalue:00000000)P4LCR(0FD4H)76543210(Initialvalue:00000000)P4LCRPortP4segmentoutputcontrol(Setforeachbitindividually)0:Input/outputport1:LCDsegmentoutputR/WP4OUTCR(0FFBH)76543210(Initialvalue:00000000)P4OUTCRP4outputcircuitcontrol(Setforeachbitindividually)0:Sinkopen-drainoutput1:CMOSoutputR/WP4PRD(0FF4H)Readonly76543210P47P46P45P44P43P42P41P40Page63TMP86CS28FG5.
6PortP5(P50toP57)PortP5isan8-bitinput/outputportthatcanalsobeusedfortimer/counterinput/output,LCDsegmentoutput,orUARTinput/output.
Aresetinitializestheoutputlatch(P5DR)to"1",thePchcontrol(P5OUTCR)to"0",andtheLCDoutputcontrolregister(P5LCR)to"0".
TouseapininPortP5asaninputport,timer/counterinput,orUARTinput,setP5DRto"1"andthensetthecor-respondingbitinP5LCRandP5OUTCRto"0".
TouseapininPortP5asanLCDsegmentoutput,setthecorrespondingbitinP5LCRto"1".
TouseapininPortP5asaUARToutputortimer/counteroutput,setP5DRto"1"andthensetthecorrespondingbitinP5LCRto"0".
TheoutputcircuitofPortP5canbeseteitherassinkopen-drainoutput("0")orCMOSotuput("1")individuallyforeachbitinP5OUTCR.
PortP5hasaseparatedatainputregister.
TheoutputlatchstatecanbereadfromtheP5DRregister,andthepinstatecanbereadfromtheP5PRDregister.
Note:Anasterisk(*)indicatesthateither"1"or"0"canbeset.
Figure5-7PortP5Table5-8RegisterProgrammingforPortP5(P50toP57)FunctionProgrammedValueP5DRP5OUTCRP5LCRPortinput,UARTinput,timer/counterinput"1""0""0"Port"0"output"0"Setasappropriate.
"0"Port"1"output,UARToutput"1""0"LCDsegmentoutput**"1"Datainput(P5PRD)Outputlatchread(P5DR)STOPOUTENP5OUTCRiinputDataoutput(P5DR)P5OUTCRiP5iNote)i=7~0DQDQLCDdataoutputP5LCRiDQP5LCRiinputControloutputControlinputOutputlatchPage645.
I/OPorts5.
6PortP5(P50toP57)TMP86CS28FGP5DR(0005H)R/W76543210P57SEG24P56SEG25P55SEG26TC6PWM6PDO6P54SEG27TC5PWM5PDO5P53SEG28TC4PWM4PDO4P52SEG29TC3PWM3PDO3P51SEG30RXD0P50SEG31TXD0(Initialvalue:00000000)P5LCR(0FD5H)76543210(Initialvalue:00000000)P5LCRPortP5segmentoutputcontrol(Setforeachbitindividually)0:Input/outputport1:LCDsegmentoutputR/WP5OUTCR(0FFCH)76543210(Initialvalue:00000000)P5OUTCRPortP5input/outputcontrol(Setforeachbitindividually)0:Sinkopen-drainoutput1:CMOSoutputR/WP5PRD(0FF5H)76543210P57P56P55P54P53P52P51P50ReadonlyPage65TMP86CS28FG5.
7PortP6(P60toP67)PortP6isan8-bitinput/outputportthatcanalsobeusedforLCDsegmentoutput.
Aresetinitializestheoutputlatch(P6DR)to"1",thePchcontrol(P6OUTCR)to"0",andtheLCDoutputcontrolregister(P6LCR)to"0".
TouseapininPortP6asaninputport,setP6DRto"1"andthensetthecorrespondingbitinP6LCRandP6OUTCRto"0".
TouseapininPortP6asanLCDsegmentoutput,setthecorrespondingbitinP6LCRto"1".
TheoutputcircuitofPortP6canbeseteitherassinkopen-drainoutput("0")orCMOSoutput("1")individuallyforeachbitinP6OUTCR.
PortP6hasaseparatedatainputregister.
TheoututlatchstatecanbereadfromtheP6DRregister,andthepinstatecanbereadfromtheP6PRDregister.
Note:Anasterisk(*)indicatesthateither"1"or"0"canbeset.
Figure5-8PortP6Table5-9RegisterProgrammingforPortP6(P60toP67)FunctionProgrammedValueP6DRP6OUTCRP6LCRPortinput"1""0""0"Port"0"output"0"Setasappropriate.
"0"Port"1"output"1""0"LCDsegmentoutput**"1"Datainput(P6PRD)Outputlatchread(P6DR)STOPOUTENP6OUTCRiinputDataoutput(P6DR)P6OUTCRiP6iNote)i=7~0DQDQLCDdataoutputP6LCRiDQP6LCRiinputOutputlatchPage665.
I/OPorts5.
7PortP6(P60toP67)TMP86CS28FGP6DR(0006H)R/W76543210P67SEG16P66SEG17P65SEG18P64SEG19P63SEG20P62SEG21P61SEG22P60SEG23(Initialvalue:00000000)P6LCR(0FD6H)76543210(Initialvalue:00000000)P6LCRPortP6segmentoutputcontrol(Setforeachbitindividually)0:Input/outputport1:SegmentoutputR/WP6OUTCR(0FFDH)76543210(Initialvalue:11111111)P6CR2PortP6input/outputcontrol(Setforeachbitindividually)0:Sinkopen-drainoutput1:CMOSoutputR/WP6PRD(0FF6H)76543210P67P66P65P64P63P62P61P60ReadonlyPage67TMP86CS28FG5.
8PortP7(P70toP77)PortP7isan8-bitinput/outputportthatcanalsobeusedforLCDsegmentoutput.
Aresetinitializestheoutputlatch(P7DR)to"1",thePchcontrol(P7OUTCR)to"0",andtheLCDoutputcontrolregister(P7LCR)to"0".
TouseapininPortP7asaninputport,setP7DRto"1"andthensetthecorrespondingbitinP7LCRandP7OUTCRto"0".
TouseapininPortP7asanLCDsegmentoutput,setthecorrespondingbitinP7LCRto"1".
TheoutputcircuitofPortP7canbeseteitherassinkopen-drainoutput("0")orCMOSoutput("1")individuallyforeachbitinP7OUTCR.
PortP7hasaseparatedatainputregister.
TheoutputlatchstatecanbereadfromtheP7DRregister,andthepinstatecanbereadfromtheP7PRDregister.
Note:Anasterisk(*)indicatesthateither"1"or"0"canbeset.
Figure5-9PortP7Table5-10RegisterProgrammingforPortP7(P70toP77)FunctionProgrammedValueP7DRP7OUTCRP7LCRPortinput"1""0""0"Port"0"output"0"Setasappropriate.
"0"Port"1"output"1""0"LCDsegmentoutput**"1"Datainput(P7PRD)Outputlatchread(P7DR)STOPOUTENP7OUTCRiinputDataoutput(P7DR)P7OUTCRiP7iNote)i=7~0DQDQLCDdataoutputP7LCRiDQP7LCRiinputOutputlatchPage685.
I/OPorts5.
8PortP7(P70toP77)TMP86CS28FGP7DR(0007H)R/W76543210P77SEG8P76SEG9P75SEG10P74SEG11P73SEG12P72SEG13P71SEG14P70SEG15(Initialvalue:00000000)P7LCR(0FD7H)76543210(Initialvalue:00000000)P7LCRPortP7segmentoutputcontrol(setforeachbitindividually)0:Input/outputport1:SegmentoutputR/WP7OUTCR(0FFEH)76543210(Initialvalue:00000000)P7OUTCRPortP7input/outputcontrol(setforeachbitindividually)0:Sinkopen-drainoutput1:CMOSoutputR/WP7PRD(0FF7H)76543210P77P76P75P74P73P72P71P70ReadonlyPage69TMP86CS28FG5.
9PortP8(P80toP87)PortP8isan8-bitinput/outputportthatcanalsobeusedforLCDsegmentoutput.
Aresetinitializestheoutputlatch(P8DR)to"1",thePchcontrol(P8OUTCR)to"0",andtheLCDoutputcontrolregister(P8LCR)to"0".
TouseapininPortP8asaninputport,setP8DRto"1"andthensetthecorrespondingbitinP8LCRandP8OUTCRto"0".
TouseapininPortP8asanLCDsegmentoutput,setthecorrespondingbitinP8LCRto"1".
TheoutputcircuitofPortP8canbeseteitherassinkopen-drainoutput("0")orCMOSoutput("1")individuallyforeachbitinP8OUTCR.
PortP8hasaseparatedatainputregister.
TheoutputlatchstatecanbereadfromtheP8DRregister,andthepinstatecanbereadfromtheP8PRDregister.
Note:Anasterisk(*)indicatesthateither"1"or"0"canbeset.
Figure5-10PortP8Table5-11RegisterProgrammingforPortP8(P80toP87)FunctionPortInputP8DRP8OUTCRP8LCRPortinput"1""0""0"Port"0"output"0"Setasappropriate.
"0"Port"1"output"1""0"LCDsegmentoutput**"1"Datainput(P8PRD)Outputlatchread(P8DR)STOPOUTENP8OUTCRiinputDataoutput(P8DR)P8OUTCRiP8iNote)i=7~0DQDQLCDdataoutputP8LCRiDQP8LCRiinputOutputlatchPage705.
I/OPorts5.
9PortP8(P80toP87)TMP86CS28FGP8DR(0008H)R/W76543210P87SEG0P86SEG1P85SEG2P84SEG3P83SEG4P82SEG5P81SEG6P80SEG7(Initialvalue:00000000)P8LCR(0FD8H)76543210(Initialvalue:00000000)P8LCRPortP8segmentoutputcontrol(Setforeachbitindividually)0:Input/outputport1:LCDsegmentoutputR/WP8OUTCR(0FFFH)76543210(Initialvalue:00000000)P8OUTCRPortP8input/outputcontrol(Setforeachbitindividually)0:Sinkopen-drainoutput1:CMOSoutputR/WP8PRD(0FF8H)76543210P87P86P85P84P83P82P81P80ReadonlyPage71TMP86CS28FG6.
WatchdogTimer(WDT)Thewatchdogtimerisafail-safesystemtodetectrapidlytheCPUmalfunctionssuchasendlessloopsduetospu-riousnoisesorthedeadlockconditions,andreturntheCPUtoasystemrecoveryroutine.
Thewatchdogtimersignalfordetectingmalfunctionscanbeprogrammedonlyonceas"resetrequest"or"inter-ruptrequest".
Upontheresetrelease,thissignalisinitializedto"resetrequest".
Whenthewatchdogtimerisnotusedtodetectmalfunctions,itcanbeusedasthetimertoprovideaperiodicinter-rupt.
Note:Caremustbetakeninsystemdesignsincethewatchdogtimerfunctionsarenotbeoperatedcompletelyduetoeffectofdisturbingnoise.
6.
1WatchdogTimerConfigurationFigure6-1WatchdogTimerConfiguration0034HOverflowWDToutputInternalresetBinarycountersWDTOUTWritingclearcodeWritingdisablecodeWDTENWDTT20035HWatchdogtimercontrolregistersWDTCR1WDTCR2INTWDTinterruptrequestInterruptrequestResetrequestResetreleaseClockClear12ControllerQSRSRQSelectorfc/223orfs/215fc/221orfs/213fc/219orfs/211fc/217orfs/29Page726.
WatchdogTimer(WDT)6.
2WatchdogTimerControlTMP86CS28FG6.
2WatchdogTimerControlThewatchdogtimeriscontrolledbythewatchdogtimercontrolregisters(WDTCR1andWDTCR2).
Thewatch-dogtimerisautomaticallyenabledaftertheresetrelease.
6.
2.
1MalfunctionDetectionMethodsUsingtheWatchdogTimerTheCPUmalfunctionisdetected,asshownbelow.
1.
Setthedetectiontime,selecttheoutput,andclearthebinarycounter.
2.
Clearthebinarycounterrepeatedlywithinthespecifieddetectiontime.
IftheCPUmalfunctionssuchasendlessloopsorthedeadlockconditionsoccurforsomereason,thewatch-dogtimeroutputisactivatedbythebinary-counteroverflowunlessthebinarycountersarecleared.
WhenWDTCR1issetto"1"atthistime,theresetrequestisgeneratedandtheninternalhardwareisinitialized.
WhenWDTCR1issetto"0",awatchdogtimerinterrupt(INTWDT)isgenerated.
ThewatchdogtimertemporarilystopscountingintheSTOPmodeincludingthewarm-uporIDLE/SLEEPmode,andautomaticallyrestarts(continuescounting)whentheSTOP/IDLE/SLEEPmodeisinactivated.
Note:Thewatchdogtimerconsistsofaninternaldividerandatwo-stagebinarycounter.
Whentheclearcode4EHiswritten,onlythebinarycounteriscleared,butnottheinternaldivider.
Theminimumbinary-counteroverflowtime,thatdependsonthetimingatwhichtheclearcode(4EH)iswrittentotheWDTCR2register,maybe3/4ofthetimesetinWDTCR1.
Therefore,writetheclearcodeusingacycleshorterthan3/4ofthetimesettoWDTCR1.
Example:Settingthewatchdogtimerdetectiontimeto221/fc[s],andresettingtheCPUmalfunctiondetectionLD(WDTCR2),4EH:Clearsthebinarycounters.
LD(WDTCR1),00001101B:WDTT←10,WDTOUT←1LD(WDTCR2),4EH:Clearsthebinarycounters(alwaysclearsimmediatelybeforeandafterchangingWDTT).
Within3/4ofWDTdetectiontime::LD(WDTCR2),4EH:Clearsthebinarycounters.
Within3/4ofWDTdetectiontime::LD(WDTCR2),4EH:Clearsthebinarycounters.
Page73TMP86CS28FGNote1:AfterclearingWDTOUTto"0",theprogramcannotsetitto"1".
Note2:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz],*:Don'tcareNote3:WDTCR1isawrite-onlyregisterandmustnotbeusedwithanyofread-modify-writeinstructions.
IfWDTCR1isread,adon'tcareisread.
Note4:ToactivatetheSTOPmode,disablethewatchdogtimerorclearthecounterimmediatelybeforeenteringtheSTOPmode.
Afterclearingthecounter,clearthecounteragainimmediatelyaftertheSTOPmodeisinactivated.
Note5:ToclearWDTEN,settheregisterinaccordancewiththeproceduresshownin"6.
2.
3WatchdogTimerDisable".
Note1:ThedisablecodeisvalidonlywhenWDTCR1=0.
Note2:*:Don'tcareNote3:Thebinarycounterofthewatchdogtimermustnotbeclearedbytheinterrupttask.
Note4:Writetheclearcode4EHusingacycleshorterthan3/4ofthetimesetinWDTCR1.
6.
2.
2WatchdogTimerEnableSettingWDTCR1to"1"enablesthewatchdogtimer.
SinceWDTCR1isinitializedto"1"duringreset,thewatchdogtimerisenabledautomaticallyaftertheresetrelease.
WatchdogTimerControlRegister1WDTCR1(0034H)76543210(ATAS)(ATOUT)WDTENWDTTWDTOUT(Initialvalue:**111001)WDTENWatchdogtimerenable/disable0:Disable(WritingthedisablecodetoWDTCR2isrequired.
)1:EnableWriteonlyWDTTWatchdogtimerdetectiontime[s]NORMAL1/2modeSLOW1/2modeWriteonlyDV7CK=0DV7CK=100225/fc217/fs217/fs01223/fc215/fs215fs10221fc213/fs213fs11219/fc211/fs211/fsWDTOUTWatchdogtimeroutputselect0:Interruptrequest1:ResetrequestWriteonlyWatchdogTimerControlRegister2WDTCR2(0035H)76543210(Initialvalue:WDTCR2WriteWatchdogtimercontrolcode4EH:Clearthewatchdogtimerbinarycounter(Clearcode)B1H:Disablethewatchdogtimer(Disablecode)D2H:EnableassigningaddresstrapareaOthers:InvalidWriteonlyPage746.
WatchdogTimer(WDT)6.
2WatchdogTimerControlTMP86CS28FG6.
2.
3WatchdogTimerDisableTodisablethewatchdogtimer,settheregisterinaccordancewiththefollowingprocedures.
Settingthereg-isterinotherprocedurescausesamalfunctionofthemicrocontroller.
1.
Settheinterruptmasterflag(IMF)to"0".
2.
SetWDTCR2totheclearcode(4EH).
3.
SetWDTCR1to"0".
4.
SetWDTCR2tothedisablecode(B1H).
Note:Whilethewatchdogtimerisdisabled,thebinarycountersofthewatchdogtimerarecleared.
6.
2.
4WatchdogTimerInterrupt(INTWDT)WhenWDTCR1isclearedto"0",awatchdogtimerinterruptrequest(INTWDT)isgeneratedbythebinary-counteroverflow.
Awatchdogtimerinterruptisthenon-maskableinterruptwhichcanbeacceptedregardlessoftheinterruptmasterflag(IMF).
Whenawatchdogtimerinterruptisgeneratedwhiletheotherinterruptincludingawatchdogtimerinterruptisalreadyaccepted,thenewwatchdogtimerinterruptisprocessedimmediatelyandthepreviousinterruptisheldpending.
Therefore,ifwatchdogtimerinterruptsaregeneratedcontinuouslywithoutexecutionoftheRETNinstruction,toomanylevelsofnestingmaycauseamalfunctionofthemicrocontroller.
Togenerateawatchdogtimerinterrupt,setthestackpointerbeforesettingWDTCR1.
Example:DisablingthewatchdogtimerDI:IMF←0LD(WDTCR2),04EH:ClearsthebinarycounterLDW(WDTCR1),0B101H:WDTEN←0,WDTCR2←DisablecodeTable6-1WatchdogTimerDetectionTime(Example:fc=16.
0MHz,fs=32.
768kHz)WDTTWatchdogTimerDetectionTime[s]NORMAL1/2modeSLOWmodeDV7CK=0DV7CK=1002.
0974401524.
288m1110131.
072m250m250m1132.
768m62.
5m62.
5mExample:SettingwatchdogtimerinterruptLDSP,083FH:SetsthestackpointerLD(WDTCR1),00001000B:WDTOUT←0Page75TMP86CS28FG6.
2.
5WatchdogTimerResetWhenabinary-counteroverflowoccurswhileWDTCR1issetto"1",awatchdogtimerresetrequestisgenerated.
Whenawatchdogtimerresetrequestisgenerated,theinternalhardwareisreset.
Theresettimeismaximum24/fc[s](1.
5s@fc=16.
0MHz).
Note:WhenawatchdogtimerresetisgeneratedintheSLOW1mode,theresettimeismaximum24/fc(high-fre-quencyclock)sincethehigh-frequencyclockoscillatorisrestarted.
However,whencrystalshaveinaccura-ciesuponstartofthehigh-frequencyclockoscillator,theresettimeshouldbeconsideredasanapproximatevaluebecauseithasslighterrors.
Figure6-2WatchdogTimerInterruptClockBinarycounterOverflowINTWDTinterruptrequest(WDTCR1="0")217/fc219/fc[s](WDTT=11)Write4EHtoWDTCR212301230Internalreset(WDTCR1="1")AresetoccursPage766.
WatchdogTimer(WDT)6.
3AddressTrapTMP86CS28FG6.
3AddressTrapTheWatchdogTimerControlRegister1and2sharetheaddresseswiththecontrolregisterstogenerateaddresstraps.
6.
3.
1SelectionofAddressTrapinInternalRAM(ATAS)WDTCR1specifieswhetherornottogenerateaddresstrapsintheinternalRAMarea.
ToexecuteaninstructionintheinternalRAMarea,clearWDTCR1to"0".
ToenabletheWDTCR1set-ting,setWDTCR1andthenwriteD2HtoWDTCR2.
ExecutinganinstructionintheSFRorDBRareageneratesanaddresstrapunconditionallyregardlessofthesettinginWDTCR1.
6.
3.
2SelectionofOperationatAddressTrap(ATOUT)Whenanaddresstrapisgenerated,eithertheinterruptrequestortheresetrequestcanbeselectedbyWDTCR1.
6.
3.
3AddressTrapInterrupt(INTATRAP)WhileWDTCR1is"0",iftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whileWDTCR1is"1"),DBRortheSFRarea,addresstrapinterrupt(INTATRAP)willbegenerated.
Anaddresstrapinterruptisanon-maskableinterruptwhichcanbeacceptedregardlessoftheinterruptmas-terflag(IMF).
Whenanaddresstrapinterruptisgeneratedwhiletheotherinterruptincludinganaddresstrapinterruptisalreadyaccepted,thenewaddresstrapisprocessedimmediatelyandthepreviousinterruptisheldpending.
Therefore,ifaddresstrapinterruptsaregeneratedcontinuouslywithoutexecutionoftheRETNinstruction,toomanylevelsofnestingmaycauseamalfunctionofthemicrocontroller.
Togenerateaddresstrapinterrupts,setthestackpointerbeforehand.
WatchdogTimerControlRegister1WDTCR1(0034H)76543210ATASATOUT(WDTEN)(WDTT)(WDTOUT)(Initialvalue:**111001)ATASSelectaddresstrapgenerationintheinternalRAMarea0:Generatenoaddresstrap1:Generateaddresstraps(AftersettingATASto"1",writingthecontrolcodeD2HtoWDTCR2isrequired)WriteonlyATOUTSelectoperationataddresstrap0:Interruptrequest1:ResetrequestWatchdogTimerControlRegister2WDTCR2(0035H)76543210(Initialvalue:WDTCR2WriteWatchdogtimercontrolcodeandaddresstrapareacontrolcodeD2H:Enableaddresstrapareaselection(ATRAPcontrolcode)4EH:Clearthewatchdogtimerbinarycounter(WDTclearcode)B1H:Disablethewatchdogtimer(WDTdisablecode)Others:InvalidWriteonlyPage77TMP86CS28FG6.
3.
4AddressTrapResetWhileWDTCR1is"1",iftheCPUshouldstartloopingforsomecausesuchasnoiseandanattemptbemadetofetchaninstructionfromtheon-chipRAM(whileWDTCR1is"1"),DBRortheSFRarea,addresstrapresetwillbegenerated.
Whenanaddresstrapresetrequestisgenerated,theinternalhardwareisreset.
Theresettimeismaximum24/fc[s](1.
5s@fc=16.
0MHz).
Note:WhenanaddresstrapresetisgeneratedintheSLOW1mode,theresettimeismaximum24/fc(high-fre-quencyclock)sincethehigh-frequencyclockoscillatorisrestarted.
However,whencrystalshaveinaccura-ciesuponstartofthehigh-frequencyclockoscillator,theresettimeshouldbeconsideredasanapproximatevaluebecauseithasslighterrors.
Page786.
WatchdogTimer(WDT)6.
3AddressTrapTMP86CS28FGPage79TMP86CS28FG7.
TimeBaseTimer(TBT)Thetimebasetimergeneratestimebaseforkeyscanning,dynamicdisplaying,etc.
Italsoprovidesatimebasetimerinterrupt(INTTBT).
7.
1TimeBaseTimer7.
1.
1ConfigurationFigure7-1TimeBaseTimerconfiguration7.
1.
2ControlTimeBaseTimeriscontrolledbyTimeBaseTimercontrolregister(TBTCR).
Note1:fc;High-frequencyclock[Hz],fs;Low-frequencyclock[Hz],*;Don'tcareTimeBaseTimerControlRegister76543210TBTCR(0036H)(DVOEN)(DVOCK)(DV7CK)TBTENTBTCK(InitialValue:00000000)TBTENTimeBaseTimerenable/disable0:Disable1:EnableTBTCKTimeBaseTimerinterruptFrequencyselect:[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2SLEEP1/2ModeR/WDV7CK=0DV7CK=1000fc/223fs/215fs/215001fc/221fs/213fs/213010fc/216fs/28–011fc/214fs/26–100fc/213fs/25–101fc/212fs/24–110fc/211fs/23–111fc/29fs/2–fc/223orfs/215fc/221orfs/213fc/216orfs/28fc/214orfs/26fc/213orfs/25fc/212orfs/24fc/211orfs/23fc/29orfs/2TBTCRTBTENTBTCK3MPXSourceclockFallingedgedetectorTimebasetimercontrolregisterINTTBTinterruptrequestIDLE0,SLEEP0releaserequestPage807.
TimeBaseTimer(TBT)7.
1TimeBaseTimerTMP86CS28FGNote2:Theinterruptfrequency(TBTCK)mustbeselectedwiththetimebasetimerdisabled(TBTEN="0").
(Theinterruptfre-quencymustnotbechangedwiththedisablefromtheenablestate.
)Bothfrequencyselectionandenablingcanbeper-formedsimultaneously.
7.
1.
3FunctionAnINTTBT(TimeBaseTimerInterrupt)isgeneratedonthefirstfallingedgeofsourceclock(ThedivideroutputofthetiminggeneratorwhichisselectedbyTBTCK.
)aftertimebasetimerhasbeenenabled.
Thedividerisnotclearedbytheprogram;therefore,onlythefirstinterruptmaybegeneratedaheadofthesetinterruptperiod(Figure7-2).
Figure7-2TimeBaseTimerInterruptExample:Setthetimebasetimerfrequencytofc/216[Hz]andenableanINTTBTinterrupt.
LD(TBTCR),00000010B;TBTCK←010LD(TBTCR),00001010B;TBTEN←1DI;IMF←0SET(EIRL).
6Table7-1TimeBaseTimerInterruptFrequency(Example:fc=16.
0MHz,fs=32.
768kHz)TBTCKTimeBaseTimerInterruptFrequency[Hz]NORMAL1/2,IDLE1/2ModeNORMAL1/2,IDLE1/2ModeSLOW1/2,SLEEP1/2ModeDV7CK=0DV7CK=10001.
91110017.
6344010244.
14128–011976.
56512–1001953.
131024–1013906.
252048–1107812.
54096–1113125016384–SourceclockEnableTBTInterruptperiodTBTCRINTTBTPage81TMP86CS28FG7.
2DividerOutput(DVO)Approximately50%dutypulsecanbeoutputusingthedivideroutputcircuit,whichisusefulforpiezoelectricbuzzerdrive.
DivideroutputisfromDVOpin.
7.
2.
1ConfigurationFigure7-3DividerOutput7.
2.
2ControlTheDividerOutputiscontrolledbytheTimeBaseTimerControlRegister.
Note:Selectionofdivideroutputfrequency(DVOCK)mustbemadewhiledivideroutputisdisabled(DVOEN="0").
Also,inotherwords,whenchangingthestateofthedivideroutputfrequencyfromenabled(DVOEN="1")todisable(DVOEN="0"),donotchangethesettingofthedivideroutputfrequency.
TimeBaseTimerControlRegister76543210TBTCR(0036H)DVOENDVOCK(DV7CK)(TBTEN)(TBTCK)(Initialvalue:00000000)DVOENDivideroutputenable/disable0:Disable1:EnableR/WDVOCKDividerOutput(DVO)frequencyselection:[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2SLEEP1/2ModeR/WDV7CK=0DV7CK=100fc/213fs/25fs/2501fc/212fs/24fs/2410fc/211fs/23fs/2311fc/210fs/22fs/22TBTCROutputlatchPortoutputlatchMPXDVOENTBTCRDVOpinoutputDVOCKDivideroutputcontrolregister(a)configuration(b)TimingchartDataoutput2ABCYDSDQDVOpinfc/213orfs/25fc/212orfs/24fc/211orfs/23fc/210orfs/22Page827.
TimeBaseTimer(TBT)7.
2DividerOutput(DVO)TMP86CS28FGExample:1.
95kHzpulseoutput(fc=16.
0MHz)LD(TBTCR),00000000B;DVOCK←"00"LD(TBTCR),10000000B;DVOEN←"1"Table7-2DividerOutputFrequency(Example:fc=16.
0MHz,fs=32.
768kHz)DVOCKDividerOutputFrequency[Hz]NORMAL1/2,IDLE1/2ModeSLOW1/2,SLEEP1/2ModeDV7CK=0DV7CK=1001.
953k1.
024k1.
024k013.
906k2.
048k2.
048k107.
813k4.
096k4.
096k1115.
625k8.
192k8.
192kPage83TMP86CS28FG8.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter108.
1.
1ConfigurationFigure8-1TimerCounter10(TC10)pinTC1METT10StartCaptureClearSourceclockPPGoutputmodeWritetoTC10CR16-bitup-counterClearTC10DRBSelectorTC10DRATC10CRTC10controlregisterMatchINTTC10interriptTFF10ACAP10TC10CKWindowmodeSetToggleQ2ToggleSetClearQYADBCSBAYSTC10SclearMPPG10PPGoutputmodeInternalresetSEnableMCAP10SYABTC10S2SetClearCommandstartDecoderExternaltriggerstartEdgedetectorNote:FunctionI/OmaynotoperatedependingonI/Oportsetting.
Formoredetails,seethechapter"I/OPort".
Port(Note)QPulsewidthmeasurementmodeFallingRisingtriggerExternalCMP16-bittimerregisterA,BPulsewidthmeasurementmodePort(Note)fc/211,fs/23fc/27fc/23Page848.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter10TMP86CS28FG8.
1.
2TimerCounterControlTheTimerCounter10iscontrolledbytheTimerCounter10controlregister(TC10CR)andtwo16-bittimerregisters(TC10DRAandTC10DRB).
Note1:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz]Note2:Thetimerregisterconsistsoftwoshiftregisters.
Avaluesetinthetimerregisterbecomesvalidattherisingedgeofthefirstsourceclockpulsethatoccursaftertheupperbyte(TC10DRAHandTC10DRBH)iswritten.
Therefore,writethelowerbyteandtheupperbyteinthisorder(itisrecommendedtowritetheregisterwitha16-bitaccessinstruction).
Writingonlythelowerbyte(TC10DRALandTC10DRBL)doesnotenablethesettingofthetimerregister.
Note3:Tosetthemode,sourceclock,PPGoutputcontrolandtimerF/Fcontrol,writetoTC10CR1duringTC10S=00.
SetthetimerF/F10controluntilthefirsttimerstartaftersettingthePPGmode.
TimerRegister1514131211109876543210TC10DRA(0011H,0010H)TC10DRAH(0011H)TC10DRAL(0010H)(Initialvalue:1111111111111111)Read/WriteTC10DRB(0013H,0012H)TC10DRBH(0013H)TC10DRBL(0012H)(Initialvalue:1111111111111111)Read/Write(WriteenabledonlyinthePPGoutputmode)TimerCounter10ControlRegisterTC10CR(0014H)76543210TFF10ACAP10MCAP10METT10MPPG10TC10STC10CKTC10MRead/Write(Initialvalue:00000000)TFF10TimerF/F10control0:Clear1:SetR/WACAP10Autocapturecontrol0:Auto-capturedisable1:Auto-captureenableR/WMCAP10Pulsewidthmeasure-mentmodecontrol0:Doubleedgecapture1:SingleedgecaptureMETT10Externaltriggertimermodecontrol0:Triggerstart1:TriggerstartandstopMPPG10PPGoutputcontrol0:Continuouspulsegeneration1:One-shotTC10STC10startcontrolTimerExtrig-gerEventWin-dowPulsePPGR/W00:StopandcounterclearOOOOOO01:CommandstartO––––O10:Risingedgestart(Ex-trigger/Pulse/PPG)Risingedgecount(Event)Positivelogiccount(Window)–OOOOO11:Fallingedgestart(Ex-trigger/Pulse/PPG)Fallingedgecount(Event)Negativelogiccount(Window)–OOOOOTC10CKTC10sourceclockselect[Hz]NORMAL1/2,IDLE1/2modeDividerSLOW,SLEEPmodeR/WDV7CK=0DV7CK=100fc/211fs/23DV9fs/2301fc/27fc/27DV5–10fc/23fc/23DV1–11Externalclock(TC10pininput)TC10MTC10operatingmodeselect00:Timer/externaltriggertimer/eventcountermode01:Windowmode10:Pulsewidthmeasurementmode11:PPG(Programmablepulsegenerate)outputmodeR/WPage85TMP86CS28FGNote4:Auto-capturecanbeusedonlyinthetimer,eventcounter,andwindowmodes.
Note5:Tosetthetimerregisters,thefollowingrelationshipmustbesatisfied.
TC10DRA>TC10DRB>1(PPGoutputmode),TC10DRA>1(othermodes)Note6:SetTFF10to"0"inthemodeexceptPPGoutputmode.
Note7:SetTC10DRBaftersettingTC10MtothePPGoutputmode.
Note8:WhentheSTOPmodeisentered,thestartcontrol(TC10S)isclearedto"00"automatically,andthetimerstops.
AftertheSTOPmodeisexited,settheTC10Stousethetimercounteragain.
Note9:Usetheauto-capturefunctionintheoperativeconditionofTC10.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondition.
Note10:Sincetheup-countervalueiscapturedintoTC10DRBbythesourceclockofup-counteraftersettingTC10CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC10DRBforthefirsttime.
8.
1.
3FunctionTimerCounter10hassixtypesofoperatingmodes:timer,externaltriggertimer,eventcounter,window,pulsewidthmeasurement,programmablepulsegeneratoroutputmodes.
8.
1.
3.
1TimermodeInthetimermode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthetimerregister1A(TC10DRA)valueisdetected,anINTTC10interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscounting.
SettingTC10CRto"1"capturestheup-countervalueintothetimerregister1B(TC10DRB)withtheauto-capturefunction.
Usetheauto-capturefunctionintheoperativeconditionofTC10.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondition.
Sincetheup-countervalueiscapturedintoTC10DRBbythesourceclockofup-counteraftersettingTC10CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC10DRBforthefirsttime.
Table8-1InternalSourceClockforTimerCounter10(Example:fc=16MHz,fs=32.
768kHz)TC10CKNORMAL1/2,IDLE1/2modeSLOW,SLEEPmodeDV7CK=0DV7CK=1Resolution[s]MaximumTimeSetting[s]Resolution[s]MaximumTimeSetting[s]Resolution[s]MaximumTimeSet-ting[s]001288.
39244.
1416.
0244.
1416.
0018.
00.
5248.
00.
524––100.
532.
77m0.
532.
77m––Example1:Settingthetimermodewithsourceclockfc/211[Hz]andgeneratinganinterrupt1secondlater(fc=16MHz,TBTCR="0")LDW(TC10DRA),1E84H;Setsthetimerregister(1s÷211/fc=1E84H)DI;IMF="0"SET(EIRL).
7;EnablesINTTC10EI;IMF="1"LD(TC10CR),00000000B;SelectsthesourceclockandmodeLD(TC10CR),00010000B;StartsTC10Page868.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter10TMP86CS28FGNote:Sincetheup-countervalueiscapturedintoTC10DRBbythesourceclockofup-counteraftersettingTC10CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC10DRBforthefirsttime.
Figure8-2TimerModeTimingChartExample2:Auto-captureLD(TC10CR),01010000B;ACAP10←1::LDWA,(TC10DRB);ReadsthecapturevalueMatchdetectACAP10TC10DRBTC10DRAINTTC10interruputrequestSourceclockCounterSourceclockCounter(a)Timermode(b)Auto-capture763450Timerstart1232140CounterclearCapturen+1nnnm+2m+1mmCapturem+2m+1n+1nm-1m-1m-2n-1n-1n-1Page87TMP86CS28FG8.
1.
3.
2ExternalTriggerTimerModeIntheexternaltriggertimermode,theup-counterstartscountingbytheinputpulsetriggeringoftheTC10pin,andcountsupattheedgeoftheinternalclock.
Forthetriggeredgeusedtostartcounting,eithertherisingorfallingedgeisdefinedinTC10CR.
WhenTC10CRissetto"1"(triggerstartandstop)Whenamatchbetweentheup-counterandtheTC10DRAvalueisdetectedafterthetimerstarts,theup-counterisclearedandhaltedandanINTTC10interruptrequestisgenerated.
Iftheedgeoppositetotriggeredgeisdetectedbeforedetectingamatchbetweentheup-counterandtheTC10DRA,theup-counterisclearedandhaltedwithoutgeneratinganinterruptrequest.
Therefore,thismodecanbeusedtodetectexceedingthespecifiedpulsebyinterrupt.
Afterbeinghalted,theup-counterrestartscountingwhenthetriggeredgeisdetected.
WhenTC10CRissetto"0"(triggerstart)Whenamatchbetweentheup-counterandtheTC10DRAvalueisdetectedafterthetimerstarts,theup-counterisclearedandhaltedandanINTTC10interruptrequestisgenerated.
Theedgeoppositetothetriggeredgehasnoeffectincountup.
Thetriggeredgeforthenextcountingisignoredifdetectingitbeforedetectingamatchbetweentheup-counterandtheTC10DRA.
SincetheTC10pininputhasthenoiserejection,pulsesof4/fc[s]orlessarerejectedasnoise.
Apulsewidthof12/fc[s]ormoreisrequiredtoensureedgedetection.
TherejectioncircuitisturnedoffintheSLOW1/2orSLEEP1/2mode,butapulsewidthofonemachinecycleormoreisrequired.
Example1:Generatinganinterrupt1msaftertherisingedgeoftheinputpulsetotheTC10pin(fc=16MHz)LDW(TC10DRA),007DH;1ms÷27/fc=7DHDI;IMF="0"SET(EIRL).
7;EnablesINTTC10interruptEI;IMF="1"LD(TC10CR),00000100B;SelectsthesourceclockandmodeLD(TC10CR),00100100B;StartsTC10externaltrigger,METT10=0Example2:Generatinganinterruptwhenthelow-levelpulsewith4msormorewidthisinputtotheTC10pin(fc=16MHz)LDW(TC10DRA),01F4H;4ms÷27/fc=1F4HDI;IMF="0"SET(EIRL).
7;EnablesINTTC10interruptEI;IMF="1"LD(TC10CR),00000100B;SelectsthesourceclockandmodeLD(TC10CR),01110100B;StartsTC10externaltrigger,METT10=0Page888.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter10TMP86CS28FGFigure8-3ExternalTriggerTimerModeTimingChartINTTC10interruptrequestSourceclockUp-counterTC10DRATC10pininputINTTC10interruptrequestSourceclockUp-counterTC10DRATC10pininput0Attherisingedge(TC10S=10)Attherisingedge(TC10S=10)(a)Triggerstart(METT10=0)CountstartMatchdetectCountstart0123423n(b)Triggerstartandstop(METT10=1)CountstartCountstart0123m0nn0CountclearNote:m.
Whenamatchbetweentheup-counterandtheTC10DRAvalueisdetected,anINTTC10interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingateachedgeoftheinputpulsetotheTC10pin.
Sinceamatchbetweentheup-counterandthevaluesettoTC10DRAisdetectedattheedgeoppositetotheselectededge,anINTTC10interruptrequestisgeneratedafteramatchofthevalueattheedgeoppositetotheselectededge.
Twoormoremachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC10pin.
SettingTC10CRto"1"capturestheup-countervalueintoTC10DRBwiththeautocapturefunction.
Usetheauto-capturefunctionintheoperativeconditionofTC10.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondition.
Sincetheup-countervalueiscapturedintoTC10DRBbythesourceclockofup-counteraftersettingTC10CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC10DRBforthefirsttime.
Figure8-4EventCounterModeTimingChartTable8-2InputPulseWidthtoTC10PinMinimumPulseWidth[s]NORMAL1/2,IDLE1/2ModeSLOW1/2,SLEEP1/2ModeHigh-going23/fc23/fsLow-going23/fc23/fsAttherisingedge(TC10S=10)INTTC10interrputrequestTC10pinInputUp-counterTC10DRA210nTimerstart210nMatchdetectCounterclearn-1Page908.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter10TMP86CS28FG8.
1.
3.
4WindowModeInthewindowmode,theup-countercountsupattherisingedgeofthepulsethatislogicalANDedproductoftheinputpulsetotheTC10pin(windowpulse)andtheinternalsourceclock.
Eithertheposi-tivelogic(countupduringhigh-goingpulse)ornegativelogic(countupduringlow-goingpulse)canbeselected.
Whenamatchbetweentheup-counterandtheTC10DRAvalueisdetected,anINTTC10interruptisgeneratedandtheup-counteriscleared.
Definethewindowpulsetothefrequencywhichissufficientlylowerthantheinternalsourceclockpro-grammedwithTC10CR.
Figure8-5WindowModeTimingChartMatchdetectTC10DRAINTTC10interrputrequestinterrputrequestInternalclockCounterTC10DRATC10pininputInternalclockCounterTC10pininputINTTC10(a)Positivelogic(TC10S=10)(b)Negativelogic(TC10S=11)Matchdetect107475463121075362023CounterclearTimerstart89019TimerstartCounterclearCountstartCountstopCountstartCountstartCountstopCountstartPage91TMP86CS28FG8.
1.
3.
5PulseWidthMeasurementModeInthepulsewidthmeasurementmode,theup-counterstartscountingbytheinputpulsetriggeringoftheTC10pin,andcountsupattheedgeoftheinternalclock.
EithertherisingorfallingedgeoftheinternalclockisselectedasthetriggeredgeinTC10CR.
Eitherthesingle-ordouble-edgecaptureisselectedasthetriggeredgeinTC10CR.
WhenTC10CRissetto"1"(single-edgecapture)Eitherhigh-orlow-levelinputpulsewidthcanbemeasured.
Tomeasurethehigh-levelinputpulsewidth,settherisingedgetoTC10CR.
Tomeasurethelow-levelinputpulsewidth,setthefallingedgetoTC10CR.
Whendetectingtheedgeoppositetothetriggeredgeusedtostartcountingafterthetimerstarts,theup-countercapturestheup-countervalueintoTC10DRBandgeneratesanINTTC10interruptrequest.
Theup-counterisclearedatthistime,andthenrestartscountingwhendetect-ingthetriggeredgeusedtostartcounting.
WhenTC10CRissetto"0"(double-edgecapture)Thecyclestartingwitheitherthehigh-orlow-goinginputpulsecanbemeasured.
Tomea-surethecyclestartingwiththehigh-goingpulse,settherisingedgetoTC10CR.
Tomeasurethecyclestartingwiththelow-goingpulse,setthefallingedgetoTC10CR.
Whendetectingtheedgeoppositetothetriggeredgeusedtostartcountingafterthetimerstarts,theup-countercapturestheup-countervalueintoTC10DRBandgeneratesanINTTC10interruptrequest.
Theup-countercontinuescountingup,andcapturestheup-countervalueintoTC10DRBandgeneratesanINTTC10interruptrequestwhendetectingthetriggeredgeusedtostartcounting.
Theup-counterisclearedatthistime,andthencontinuescounting.
Note1:ThecapturedvaluemustbereadfromTC10DRBuntilthenexttriggeredgeisdetected.
Ifnotread,thecapturedvaluebecomesadon'tcare.
Itisrecommendedtousea16-bitaccessinstructiontoreadthecapturedvaluefromTC10DRB.
Note2:Forthesingle-edgecapture,thecounteraftercapturingthevaluestopsat"1"untildetectingthenextedge.
Therefore,thesecondcapturedvalueis"1"largerthanthecapturedvalueimmediatelyaftercountingstarts.
Note3:Thefirstcapturedvalueafterthetimerstartsmaybereadincorrectively,therefore,ignorethefirstcapturedvalue.
Page928.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter10TMP86CS28FGExample:Dutymeasurement(resolutionfc/27[Hz])CLR(INTTC10SW).
0;INTTC10serviceswitchinitialsettingAddresssettoconvertINTTC10SWateachINTTC10LD(TC10CR),00000110B;SetstheTC10modeandsourceclockDI;IMF="0"SET(EIRL).
7;EnablesINTTC10EI;IMF="1"LD(TC10CR),00100110B;StartsTC10withanexternaltriggeratMCAP10=0:PINTTC10:CPL(INTTC10SW).
0;INTTC10interrupt,invertsandtestsINTTC10serviceswitchJRSF,SINTTC10LDA,(TC10DRBL);ReadsTC10DRB(High-levelpulsewidth)LDW,(TC10DRBH)LD(HPULSE),WA;Storeshigh-levelpulsewidthinRAMRETISINTTC10:LDA,(TC10DRBL);ReadsTC10DRB(Cycle)LDW,(TC10DRBH)LD(WIDTH),WA;StorescycleinRAM:RETI;Dutycalculation:VINTTC10:DWPINTTC10;INTTC10InterruptvectorWIDTHHPULSETC10pinINTTC10interruptrequestINTTC10SWPage93TMP86CS28FGFigure8-6PulseWidthMeasurementModeTC10DRBINTTC10interruptrequestinterruptrequestTC10pininputCounterInternalclock(MCAP10="1")23nCountstartCountstartTrigger(TC10S="10")132140n0Capturen-1TC10DRBINTTC10TC10pininputCounterInternalclock(MCAP10="0")12nCountstartCountstart(TC10S="10")32140nCaptureCapturen+1m-2n+3n+2n+1m-1m0m[Application]High-orlow-levelpulsewidthmeasurement[Application](1)Cycle/frequencymeasurement(2)Dutymeasurement(a)Single-edgecapture(b)Double-edgecapturePage948.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter10TMP86CS28FG8.
1.
3.
6ProgrammablePulseGenerate(PPG)OutputModeIntheprogrammablepulsegeneration(PPG)mode,anarbitrarydutypulseisgeneratedbycountingperformedintheinternalclock.
Tostartthetimer,TC10CRspecifieseithertheedgeoftheinputpulsetotheTC10pinorthecommandstart.
TC10CRspecifieswhetheradutypulseispro-ducedcontinuouslyornot(one-shotpulse).
WhenTC10CRissetto"0"(Continuouspulsegeneration)Whenamatchbetweentheup-counterandtheTC10DRBvalueisdetectedafterthetimerstarts,thelevelofthePPGpinisinvertedandanINTTC10interruptrequestisgenerated.
Theup-countercontinuescounting.
Whenamatchbetweentheup-counterandtheTC10DRAvalueisdetected,thelevelofthePPGpinisinvertedandanINTTC10interruptrequestisgenerated.
Theup-counterisclearedatthistime,andthencontinuescountingandpulsegeneration.
WhenTC10Sisclearedto"00"duringPPGoutput,thePPGpinretainsthelevelimmediatelybeforethecounterstops.
WhenTC10CRissetto"1"(One-shotpulsegeneration)Whenamatchbetweentheup-counterandtheTC10DRBvalueisdetectedafterthetimerstarts,thelevelofthePPGpinisinvertedandanINTTC10interruptrequestisgenerated.
Theup-countercontinuescounting.
Whenamatchbetweentheup-counterandtheTC10DRAvalueisdetected,thelevelofthePPGpinisinvertedandanINTTC10interruptrequestisgenerated.
TC10CRisclearedto"00"automaticallyatthistime,andthetimerstops.
ThepulsegeneratedbyPPGretainsthesamelevelasthatwhenthetimerstops.
SincetheoutputlevelofthePPGpincanbesetwithTC10CRwhenthetimerstarts,apositiveornegativepulsecanbegenerated.
SincetheinvertedlevelofthetimerF/F1outputlevelisoutputtothePPGpin,specifyTC10CRto"0"tosetthehighleveltothePPGpin,and"1"tosetthelowleveltothePPGpin.
Uponreset,thetimerF/F1isinitializedto"0".
Note1:TochangeTC10DRAorTC10DRBduringarunofthetimer,setavaluesufficientlylargerthanthecountvalueofthecounter.
Settingavaluesmallerthanthecountvalueofthecounterduringarunofthetimermaygenerateapulsedifferentfromthatspecified.
Note2:DonotchangeTC10CRduringarunofthetimer.
TC10CRcanbesetcorrectlyonlyatinitialization(afterreset).
WhenthetimerstopsduringPPG,TC10CRcannotbesetcorrectlyfromthispointonwardifthePPGoutputhasthelevelwhichisinvertedofthelevelwhenthetimerstarts.
(SettingTC10CRspecifiesthetimerF/F1tothelevelinvertedofthepro-grammedvalue.
)Therefore,thetimerF/F1needstobeinitializedtoensureanarbitrarylevelofthePPGoutput.
ToinitializethetimerF/F1,changeTC10CRtothetimermode(itisnotrequiredtostartthetimermode),andthensetthePPGmode.
SetTC10CRatthistime.
Note3:InthePPGmode,thefollowingrelationshipmustbesatisfied.
TC10DRA>TC10DRBNote4:SetTC10DRBafterchangingthemodeofTC10MtothePPGmode.
Page95TMP86CS28FGFigure8-7PPGOutputExample:Generatingapulsewhichishigh-goingfor800sandlow-goingfor200s(fc=16MHz)SettingportLD(TC10CR),10000111B;SetsthePPGmode,selectsthesourceclockLDW(TC10DRA),007DH;Setsthecycle(1ms÷27/fcms=007DH)LDW(TC10DRB),0019H;Setsthelow-levelpulsewidth(200s÷27/fc=0019H)LD(TC10CR),10010111B;StartsthetimerExample:AfterstoppingPPG,settingthePPGpintoahigh-leveltorestartPPG(fc=16MHz)SettingportLD(TC10CR),10000111B;SetsthePPGmode,selectsthesourceclockLDW(TC10DRA),007DH;Setsthecycle(1ms÷27/fcs=007DH)LDW(TC10DRB),0019H;Setsthelow-levelpulsewidth(200s÷27/fc=0019H)LD(TC10CR),10010111B;Startsthetimer::LD(TC10CR),10000111B;StopsthetimerLD(TC10CR),10000100B;SetsthetimermodeLD(TC10CR),00000111B;SetsthePPGmode,TFF10=0LD(TC10CR),00010111B;StartsthetimerQRDPPGpinFunctionoutputPortoutputenableI/OportoutputlatchsharedwithPPGoutputDataoutputToggleSetClearQTC10CRWritetoTC10CRInternalresetMatchtoTC10DRBMatchtoTC10DRATC10CRclearTimerF/F10INTTC10interruptrequestPage968.
16-BitTimerCounter(TC10,TC11)8.
116-BitTimerCounter10TMP86CS28FGFigure8-8PPGModeTimingChartINTTC10TC10DRAInternalclockCounterTC10DRBTC10DRAPPGpinoutput0INTTC10interruptrequestinterruptrequest12m012nm01n2nn+1n+1m(a)Continuouspulsegeneration(TC10S=01)TC10DRBTriggerCountstartTimerstartCounterInternalclockTC10pininputPPGpinoutput01mnnn+1m0(b)One-shotpulsegeneration(TC10S=10)MatchdetectNote:m>nNote:m>n[Application]One-shotpulseoutputPage97TMP86CS28FG8.
216-BitTimerCounter118.
2.
1ConfigurationFigure8-9TimerCounter11(TC11)pinTC1METT11StartCaptureClearSourceclockPPGoutputmodeWritetoTC11CR16-bitup-counterClearTC11DRBSelectorTC11DRATC11CRTC11controlregisterMatchINTTC11interriptTFF11ACAP11TC11CKWindowmodeSetToggleQ2ToggleSetClearQYADBCSBAYSTC11SclearMPPG11PPGoutputmodeInternalresetSEnableMCAP11SYABTC11S2SetClearCommandstartDecoderExternaltriggerstartEdgedetectorNote:FunctionI/OmaynotoperatedependingonI/Oportsetting.
Formoredetails,seethechapter"I/OPort".
Port(Note)QPulsewidthmeasurementmodeFallingRisingtriggerExternalCMP16-bittimerregisterA,BPulsewidthmeasurementmodePort(Note)fc/211,fs/23fc/27fc/23Page988.
16-BitTimerCounter(TC10,TC11)8.
216-BitTimerCounter11TMP86CS28FG8.
2.
2TimerCounterControlTheTimerCounter11iscontrolledbytheTimerCounter11controlregister(TC11CR)andtwo16-bittimerregisters(TC11DRAandTC11DRB).
Note1:fc:High-frequencyclock[Hz],fs:Low-frequencyclock[Hz]Note2:Thetimerregisterconsistsoftwoshiftregisters.
Avaluesetinthetimerregisterbecomesvalidattherisingedgeofthefirstsourceclockpulsethatoccursaftertheupperbyte(TC11DRAHandTC11DRBH)iswritten.
Therefore,writethelowerTimerRegister1514131211109876543210TC11DRA(0021H,0020H)TC11DRAH(0021H)TC11DRAL(0020H)(Initialvalue:1111111111111111)Read/WriteTC11DRB(0023H,0022H)TC11DRBH(0023H)TC11DRBL(0022H)(Initialvalue:1111111111111111)Read/Write(WriteenabledonlyinthePPGoutputmode)TimerCounter11ControlRegisterTC11CR(0024H)76543210TFF11ACAP11MCAP11METT11MPPG11TC11STC11CKTC11MRead/Write(Initialvalue:00000000)TFF11TimerF/F11control0:Clear1:SetR/WACAP11Autocapturecontrol0:Auto-capturedisable1:Auto-captureenableR/WMCAP11Pulsewidthmeasure-mentmodecontrol0:Doubleedgecapture1:SingleedgecaptureMETT11Externaltriggertimermodecontrol0:Triggerstart1:TriggerstartandstopMPPG11PPGoutputcontrol0:Continuouspulsegeneration1:One-shotTC11STC11startcontrolTimerExtrig-gerEventWin-dowPulsePPGR/W00:StopandcounterclearOOOOOO01:CommandstartO––––O10:Risingedgestart(Ex-trigger/Pulse/PPG)Risingedgecount(Event)Positivelogiccount(Window)–OOOOO11:Fallingedgestart(Ex-trigger/Pulse/PPG)Fallingedgecount(Event)Negativelogiccount(Window)–OOOOOTC11CKTC11sourceclockselect[Hz]NORMAL1/2,IDLE1/2modeDividerSLOW,SLEEPmodeR/WDV7CK=0DV7CK=100fc/211fs/23DV9fs/2301fc/27fc/27DV5–10fc/23fc/23DV1–11Externalclock(TC11pininput)TC11MTC11operatingmodeselect00:Timer/externaltriggertimer/eventcountermode01:Windowmode10:Pulsewidthmeasurementmode11:PPG(Programmablepulsegenerate)outputmodeR/WPage99TMP86CS28FGbyteandtheupperbyteinthisorder(itisrecommendedtowritetheregisterwitha16-bitaccessinstruction).
Writingonlythelowerbyte(TC11DRALandTC11DRBL)doesnotenablethesettingofthetimerregister.
Note3:Tosetthemode,sourceclock,PPGoutputcontrolandtimerF/Fcontrol,writetoTC11CR1duringTC11S=00.
SetthetimerF/F10controluntilthefirsttimerstartaftersettingthePPGmode.
Note4:Auto-capturecanbeusedonlyinthetimer,eventcounter,andwindowmodes.
Note5:Tosetthetimerregisters,thefollowingrelationshipmustbesatisfied.
TC11DRA>TC11DRB>1(PPGoutputmode),TC11DRA>1(othermodes)Note6:SetTFF11to"0"inthemodeexceptPPGoutputmode.
Note7:SetTC11DRBaftersettingTC11MtothePPGoutputmode.
Note8:WhentheSTOPmodeisentered,thestartcontrol(TC11S)isclearedto"00"automatically,andthetimerstops.
AftertheSTOPmodeisexited,settheTC11Stousethetimercounteragain.
Note9:Usetheauto-capturefunctionintheoperativeconditionofTC11.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondition.
Note10:Sincetheup-countervalueiscapturedintoTC11DRBbythesourceclockofup-counteraftersettingTC11CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC11DRBforthefirsttime.
8.
2.
3FunctionTimerCounter11hassixtypesofoperatingmodes:timer,externaltriggertimer,eventcounter,window,pulsewidthmeasurement,programmablepulsegeneratoroutputmodes.
8.
2.
3.
1TimermodeInthetimermode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthetimerregister1A(TC11DRA)valueisdetected,anINTTC11interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscounting.
SettingTC11CRto"1"capturestheup-countervalueintothetimerregister1B(TC11DRB)withtheauto-capturefunction.
Usetheauto-capturefunctionintheoperativeconditionofTC11.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondition.
Sincetheup-countervalueiscapturedintoTC11DRBbythesourceclockofup-counteraftersettingTC11CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC11DRBforthefirsttime.
Table8-3InternalSourceClockforTimerCounter11(Example:fc=16MHz,fs=32.
768kHz)TC11CKNORMAL1/2,IDLE1/2modeSLOW,SLEEPmodeDV7CK=0DV7CK=1Resolution[s]MaximumTimeSetting[s]Resolution[s]MaximumTimeSetting[s]Resolution[s]MaximumTimeSet-ting[s]001288.
39244.
1416.
0244.
1416.
0018.
00.
5248.
00.
524––100.
532.
77m0.
532.
77m––Page1008.
16-BitTimerCounter(TC10,TC11)8.
216-BitTimerCounter11TMP86CS28FGNote:Sincetheup-countervalueiscapturedintoTC11DRBbythesourceclockofup-counteraftersettingTC11CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC11DRBforthefirsttime.
Figure8-10TimerModeTimingChartExample1:Settingthetimermodewithsourceclockfc/211[Hz]andgeneratinganinterrupt1secondlater(fc=16MHz,TBTCR="0")LDW(TC11DRA),1E84H;Setsthetimerregister(1s÷211/fc=1E84H)DI;IMF="0"SET(EIRL).
2;EnablesINTTC11EI;IMF="1"LD(TC11CR),00000000B;SelectsthesourceclockandmodeLD(TC11CR),00010000B;StartsTC11Example2:Auto-captureLD(TC11CR),01010000B;ACAP11←1::LDWA,(TC11DRB);ReadsthecapturevalueMatchdetectACAP11TC11DRBTC11DRAINTTC11interruputrequestSourceclockCounterSourceclockCounter(a)Timermode(b)Auto-capture763450Timerstart1232140CounterclearCapturen+1nnnm+2m+1mmCapturem+2m+1n+1nm-1m-1m-2n-1n-1n-1Page101TMP86CS28FG8.
2.
3.
2ExternalTriggerTimerModeIntheexternaltriggertimermode,theup-counterstartscountingbytheinputpulsetriggeringoftheTC11pin,andcountsupattheedgeoftheinternalclock.
Forthetriggeredgeusedtostartcounting,eithertherisingorfallingedgeisdefinedinTC11CR.
WhenTC11CRissetto"1"(triggerstartandstop)Whenamatchbetweentheup-counterandtheTC11DRAvalueisdetectedafterthetimerstarts,theup-counterisclearedandhaltedandanINTTC11interruptrequestisgenerated.
Iftheedgeoppositetotriggeredgeisdetectedbeforedetectingamatchbetweentheup-counterandtheTC11DRA,theup-counterisclearedandhaltedwithoutgeneratinganinterruptrequest.
Therefore,thismodecanbeusedtodetectexceedingthespecifiedpulsebyinterrupt.
Afterbeinghalted,theup-counterrestartscountingwhenthetriggeredgeisdetected.
WhenTC11CRissetto"0"(triggerstart)Whenamatchbetweentheup-counterandtheTC11DRAvalueisdetectedafterthetimerstarts,theup-counterisclearedandhaltedandanINTTC11interruptrequestisgenerated.
Theedgeoppositetothetriggeredgehasnoeffectincountup.
Thetriggeredgeforthenextcountingisignoredifdetectingitbeforedetectingamatchbetweentheup-counterandtheTC11DRA.
SincetheTC11pininputhasthenoiserejection,pulsesof4/fc[s]orlessarerejectedasnoise.
Apulsewidthof12/fc[s]ormoreisrequiredtoensureedgedetection.
TherejectioncircuitisturnedoffintheSLOW1/2orSLEEP1/2mode,butapulsewidthofonemachinecycleormoreisrequired.
Example1:Generatinganinterrupt1msaftertherisingedgeoftheinputpulsetotheTC11pin(fc=16MHz)LDW(TC11DRA),007DH;1ms÷27/fc=7DHDI;IMF="0"SET(EIRL).
2;EnablesINTTC11interruptEI;IMF="1"LD(TC11CR),00000100B;SelectsthesourceclockandmodeLD(TC11CR),00100100B;StartsTC11externaltrigger,METT11=0Example2:Generatinganinterruptwhenthelow-levelpulsewith4msormorewidthisinputtotheTC11pin(fc=16MHz)LDW(TC11DRA),01F4H;4ms÷27/fc=1F4HDI;IMF="0"SET(EIRL).
2;EnablesINTTC11interruptEI;IMF="1"LD(TC11CR),00000100B;SelectsthesourceclockandmodeLD(TC11CR),01110100B;StartsTC11externaltrigger,METT11=0Page1028.
16-BitTimerCounter(TC10,TC11)8.
216-BitTimerCounter11TMP86CS28FGFigure8-11ExternalTriggerTimerModeTimingChartINTTC11interruptrequestSourceclockUp-counterTC11DRATC11pininputINTTC11interruptrequestSourceclockUp-counterTC11DRATC11pininput0Attherisingedge(TC11S=10)Attherisingedge(TC11S=10)(a)Triggerstart(METT11=0)CountstartMatchdetectCountstart0123423n(b)Triggerstartandstop(METT11=1)CountstartCountstart0123m0nn0CountclearNote:m.
Whenamatchbetweentheup-counterandtheTC11DRAvalueisdetected,anINTTC11interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingateachedgeoftheinputpulsetotheTC11pin.
Sinceamatchbetweentheup-counterandthevaluesettoTC11DRAisdetectedattheedgeoppositetotheselectededge,anINTTC11interruptrequestisgeneratedafteramatchofthevalueattheedgeoppositetotheselectededge.
Twoormoremachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC11pin.
SettingTC11CRto"1"capturestheup-countervalueintoTC11DRBwiththeautocapturefunction.
Usetheauto-capturefunctionintheoperativeconditionofTC11.
Acapturedvaluemaynotbefixedifit'sreadaftertheexecutionofthetimerstoporauto-capturedisable.
Readthecapturevalueinacaptureenabledcondition.
Sincetheup-countervalueiscapturedintoTC11DRBbythesourceclockofup-counteraftersettingTC11CRto"1".
Therefore,toreadthecapturedvalue,waitatleastonecycleoftheinternalsourceclockbeforereadingTC11DRBforthefirsttime.
Figure8-12EventCounterModeTimingChartTable8-4InputPulseWidthtoTC11PinMinimumPulseWidth[s]NORMAL1/2,IDLE1/2ModeSLOW1/2,SLEEP1/2ModeHigh-going23/fc23/fsLow-going23/fc23/fsAttherisingedge(TC11S=10)INTTC11interrputrequestTC11pinInputUp-counterTC11DRA210nTimerstart210nMatchdetectCounterclearn-1Page1048.
16-BitTimerCounter(TC10,TC11)8.
216-BitTimerCounter11TMP86CS28FG8.
2.
3.
4WindowModeInthewindowmode,theup-countercountsupattherisingedgeofthepulsethatislogicalANDedproductoftheinputpulsetotheTC11pin(windowpulse)andtheinternalsourceclock.
Eithertheposi-tivelogic(countupduringhigh-goingpulse)ornegativelogic(countupduringlow-goingpulse)canbeselected.
Whenamatchbetweentheup-counterandtheTC11DRAvalueisdetected,anINTTC11interruptisgeneratedandtheup-counteriscleared.
Definethewindowpulsetothefrequencywhichissufficientlylowerthantheinternalsourceclockpro-grammedwithTC11CR.
Figure8-13WindowModeTimingChartMatchdetectTC11DRAINTTC11interrputrequestinterrputrequestInternalclockCounterTC11DRATC11pininputInternalclockCounterTC11pininputINTTC11(a)Positivelogic(TC11S=10)(b)Negativelogic(TC11S=11)Matchdetect107475463121075362023CounterclearTimerstart89019TimerstartCounterclearCountstartCountstopCountstartCountstartCountstopCountstartPage105TMP86CS28FG8.
2.
3.
5PulseWidthMeasurementModeInthepulsewidthmeasurementmode,theup-counterstartscountingbytheinputpulsetriggeringoftheTC11pin,andcountsupattheedgeoftheinternalclock.
EithertherisingorfallingedgeoftheinternalclockisselectedasthetriggeredgeinTC11CR.
Eitherthesingle-ordouble-edgecaptureisselectedasthetriggeredgeinTC11CR.
WhenTC11CRissetto"1"(single-edgecapture)Eitherhigh-orlow-levelinputpulsewidthcanbemeasured.
Tomeasurethehigh-levelinputpulsewidth,settherisingedgetoTC11CR.
Tomeasurethelow-levelinputpulsewidth,setthefallingedgetoTC11CR.
Whendetectingtheedgeoppositetothetriggeredgeusedtostartcountingafterthetimerstarts,theup-countercapturestheup-countervalueintoTC11DRBandgeneratesanINTTC11interruptrequest.
Theup-counterisclearedatthistime,andthenrestartscountingwhendetect-ingthetriggeredgeusedtostartcounting.
WhenTC11CRissetto"0"(double-edgecapture)Thecyclestartingwitheitherthehigh-orlow-goinginputpulsecanbemeasured.
Tomea-surethecyclestartingwiththehigh-goingpulse,settherisingedgetoTC11CR.
Tomeasurethecyclestartingwiththelow-goingpulse,setthefallingedgetoTC11CR.
Whendetectingtheedgeoppositetothetriggeredgeusedtostartcountingafterthetimerstarts,theup-countercapturestheup-countervalueintoTC11DRBandgeneratesanINTTC11interruptrequest.
Theup-countercontinuescountingup,andcapturestheup-countervalueintoTC11DRBandgeneratesanINTTC11interruptrequestwhendetectingthetriggeredgeusedtostartcounting.
Theup-counterisclearedatthistime,andthencontinuescounting.
Note1:ThecapturedvaluemustbereadfromTC11DRBuntilthenexttriggeredgeisdetected.
Ifnotread,thecapturedvaluebecomesadon'tcare.
Itisrecommendedtousea16-bitaccessinstructiontoreadthecapturedvaluefromTC11DRB.
Note2:Forthesingle-edgecapture,thecounteraftercapturingthevaluestopsat"1"untildetectingthenextedge.
Therefore,thesecondcapturedvalueis"1"largerthanthecapturedvalueimmediatelyaftercountingstarts.
Note3:Thefirstcapturedvalueafterthetimerstartsmaybereadincorrectively,therefore,ignorethefirstcapturedvalue.
Page1068.
16-BitTimerCounter(TC10,TC11)8.
216-BitTimerCounter11TMP86CS28FGExample:Dutymeasurement(resolutionfc/27[Hz])CLR(INTTC11SW).
0;INTTC11serviceswitchinitialsettingAddresssettoconvertINTTC11SWateachINTTC11LD(TC11CR),00000110B;SetstheTC11modeandsourceclockDI;IMF="0"SET(EIRH).
7;EnablesINTTC11EI;IMF="1"LD(TC11CR),00100110B;StartsTC11withanexternaltriggeratMCAP11=0:PINTTC11:CPL(INTTC11SW).
0;INTTC11interrupt,invertsandtestsINTTC11serviceswitchJRSF,SINTTC11LDA,(TC11DRBL);ReadsTC11DRB(High-levelpulsewidth)LDW,(TC11DRBH)LD(HPULSE),WA;Storeshigh-levelpulsewidthinRAMRETISINTTC11:LDA,(TC11DRBL);ReadsTC11DRB(Cycle)LDW,(TC11DRBH)LD(WIDTH),WA;StorescycleinRAM:RETI;Dutycalculation:VINTTC11:DWPINTTC11;INTTC11InterruptvectorWIDTHHPULSETC11pinINTTC11interruptrequestINTTC11SWPage107TMP86CS28FGFigure8-14PulseWidthMeasurementModeTC11DRBINTTC11interruptrequestinterruptrequestTC11pininputCounterInternalclock(MCAP11="1")23nCountstartCountstartTrigger(TC11S="10")132140n0Capturen-1TC11DRBINTTC11TC11pininputCounterInternalclock(MCAP11="0")12nCountstartCountstart(TC11S="10")32140nCaptureCapturen+1m-2n+3n+2n+1m-1m0m[Application]High-orlow-levelpulsewidthmeasurement[Application](1)Cycle/frequencymeasurement(2)Dutymeasurement(a)Single-edgecapture(b)Double-edgecapturePage1088.
16-BitTimerCounter(TC10,TC11)8.
216-BitTimerCounter11TMP86CS28FG8.
2.
3.
6ProgrammablePulseGenerate(PPG)OutputModeIntheprogrammablepulsegeneration(PPG)mode,anarbitrarydutypulseisgeneratedbycountingperformedintheinternalclock.
Tostartthetimer,TC11CRspecifieseithertheedgeoftheinputpulsetotheTC11pinorthecommandstart.
TC11CRspecifieswhetheradutypulseispro-ducedcontinuouslyornot(one-shotpulse).
WhenTC11CRissetto"0"(Continuouspulsegeneration)Whenamatchbetweentheup-counterandtheTC11DRBvalueisdetectedafterthetimerstarts,thelevelofthePPGpinisinvertedandanINTTC11interruptrequestisgenerated.
Theup-countercontinuescounting.
Whenamatchbetweentheup-counterandtheTC11DRAvalueisdetected,thelevelofthePPGpinisinvertedandanINTTC11interruptrequestisgenerated.
Theup-counterisclearedatthistime,andthencontinuescountingandpulsegeneration.
WhenTC11Sisclearedto"00"duringPPGoutput,thePPGpinretainsthelevelimmediatelybeforethecounterstops.
WhenTC11CRissetto"1"(One-shotpulsegeneration)Whenamatchbetweentheup-counterandtheTC11DRBvalueisdetectedafterthetimerstarts,thelevelofthePPGpinisinvertedandanINTTC11interruptrequestisgenerated.
Theup-countercontinuescounting.
Whenamatchbetweentheup-counterandtheTC11DRAvalueisdetected,thelevelofthePPGpinisinvertedandanINTTC11interruptrequestisgenerated.
TC11CRisclearedto"00"automaticallyatthistime,andthetimerstops.
ThepulsegeneratedbyPPGretainsthesamelevelasthatwhenthetimerstops.
SincetheoutputlevelofthePPGpincanbesetwithTC11CRwhenthetimerstarts,apositiveornegativepulsecanbegenerated.
SincetheinvertedlevelofthetimerF/F1outputlevelisoutputtothePPGpin,specifyTC11CRto"0"tosetthehighleveltothePPGpin,and"1"tosetthelowleveltothePPGpin.
Uponreset,thetimerF/F1isinitializedto"0".
Note1:TochangeTC11DRAorTC11DRBduringarunofthetimer,setavaluesufficientlylargerthanthecountvalueofthecounter.
Settingavaluesmallerthanthecountvalueofthecounterduringarunofthetimermaygenerateapulsedifferentfromthatspecified.
Note2:DonotchangeTC11CRduringarunofthetimer.
TC11CRcanbesetcorrectlyonlyatinitialization(afterreset).
WhenthetimerstopsduringPPG,TC11CRcannotbesetcor-rectlyfromthispointonwardifthePPGoutputhasthelevelwhichisinvertedofthelevelwhenthetimerstarts.
(SettingTC11CRspecifiesthetimerF/F1tothelevelinvertedofthepro-grammedvalue.
)Therefore,thetimerF/F1needstobeinitializedtoensureanarbitrarylevelofthePPGoutput.
ToinitializethetimerF/F1,changeTC11CRtothetimermode(itisnotrequiredtostartthetimermode),andthensetthePPGmode.
SetTC11CRatthistime.
Note3:InthePPGmode,thefollowingrelationshipmustbesatisfied.
TC11DRA>TC11DRBNote4:SetTC11DRBafterchangingthemodeofTC11MtothePPGmode.
Page109TMP86CS28FGFigure8-15PPGOutputExample:Generatingapulsewhichishigh-goingfor800sandlow-goingfor200s(fc=16MHz)SettingportLD(TC11CR),10000111B;SetsthePPGmode,selectsthesourceclockLDW(TC11DRA),007DH;Setsthecycle(1ms÷27/fcms=007DH)LDW(TC11DRB),0019H;Setsthelow-levelpulsewidth(200s÷27/fc=0019H)LD(TC11CR),10010111B;StartsthetimerExample:AfterstoppingPPG,settingthePPGpintoahigh-leveltorestartPPG(fc=16MHz)SettingportLD(TC11CR),10000111B;SetsthePPGmode,selectsthesourceclockLDW(TC11DRA),007DH;Setsthecycle(1ms÷27/fcs=007DH)LDW(TC11DRB),0019H;Setsthelow-levelpulsewidth(200s÷27/fc=0019H)LD(TC11CR),10010111B;Startsthetimer::LD(TC11CR),10000111B;StopsthetimerLD(TC11CR),10000100B;SetsthetimermodeLD(TC11CR),00000111B;SetsthePPGmode,TFF11=0LD(TC11CR),00010111B;StartsthetimerQRDPPGpinFunctionoutputPortoutputenableI/OportoutputlatchsharedwithPPGoutputDataoutputToggleSetClearQTC11CRWritetoTC11CRInternalresetMatchtoTC11DRBMatchtoTC11DRATC11CRclearTimerF/F11INTTC11interruptrequestPage1108.
16-BitTimerCounter(TC10,TC11)8.
216-BitTimerCounter11TMP86CS28FGFigure8-16PPGModeTimingChartINTTC11TC11DRAInternalclockCounterTC11DRBTC11DRAPPGpinoutput0INTTC11interruptrequestinterruptrequest12m012nm01n2nn+1n+1m(a)Continuouspulsegeneration(TC11S=01)TC11DRBTriggerCountstartTimerstartCounterInternalclockTC11pininputPPGpinoutput01mnnn+1m0(b)One-shotpulsegeneration(TC11S=10)MatchdetectNote:m>nNote:m>n[Application]One-shotpulseoutputPage111TMP86CS28FG9.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationFigure9-18-BitTimerCounter3,48-bitup-counterDecodeENAYBSABYCDEFGHSAYBSSAYBToggleQSetClear8-bitup-counterABYCDEFGHSDecodeENToggleQSetClearPWMmodePDO,PPGmodePDOmodePWM,PPGmodePWMmodePWMmode16-bitmode16-bitmode16-bitmode16-bitmodeTimer,EventCountermodeOverflowOverflowTimer,EventCoutermode16-bitmodeClearClearfc/27fc/25fc/23fc/2fcfc/27fc/25fc/23fc/2fcPDO,PWM,PPGmodePDO,PWMmode16-bitmodefc/211orfs/23fc/211orfs/23fsfsTC4CRTC3CRTTREG4PWREG4TTREG3PWREG3TC3pinTC4pinTC4STC3SINTTC3interruptrequestINTTC4interruptrequestTFF4TFF3PDO4/PWM4/PPG4pinPDO3/PWM3/pinTC3CKTC4CKTC3MTC3STFF3TC4MTC4STFF4TimerF/F4TimerF/F3Page1129.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FG9.
2TimerCounterControlTheTimerCounter3iscontrolledbytheTimerCounter3controlregister(TC3CR)andtwo8-bittimerregisters(TTREG3,PWREG3).
Note1:Donotchangethetimerregister(TTREG3)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG3)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC3M,TC3CKandTFF3settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC3S=1→0),donotchangetheTC3M,TC3CKandTFF3settings.
Tostartthetimeropera-tion(TC3S=0→1),TC3M,TC3CKandTFF3canbeprogrammed.
Note4:TousetheTimerCounterinthe16-bitmode,settheoperatingmodebyprogrammingTC4CR,whereTC3Mmustbefixedto011.
Note5:TousetheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC3CK.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC4CRandTC4CR,respectively.
Note6:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-1andTable9-2.
TimerCounter3TimerRegisterTTREG3(0015H)R/W76543210(Initialvalue:11111111)PWREG3(0019H)R/W76543210(Initialvalue:11111111)TimerCounter3ControlRegisterTC3CR(0009H)76543210TFF3TC3CKTC3STC3M(Initialvalue:00000000)TFF3TimeF/F3control0:1:ClearSetR/WTC3CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfcfc(Note8)111TC3pininputTC3STC3startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC3MTC3Moperatingmodeselect000:001:010:011:1**:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmode16-bitmode(EachmodeisselectablewithTC4M.
)ReservedR/WPage113TMP86CS28FGNote7:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-3.
Note8:TheoperatingclockfcintheSLOWorSLEEPmodecanbeusedonlyasthehigh-frequencywarm-upmode.
Page1149.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FGTheTimerCounter4iscontrolledbytheTimerCounter4controlregister(TC4CR)andtwo8-bittimerregisters(TTREG4andPWREG4).
Note1:Donotchangethetimerregister(TTREG4)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG4)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC4M,TC4CKandTFF4settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC4S=1→0),donotchangetheTC4M,TC4CKandTFF4settings.
Tostartthetimeroperation(TC4S=0→1),TC4M,TC4CKandTFF4canbeprogrammed.
Note4:WhenTC4M=1**(upperbyteinthe16-bitmode),thesourceclockbecomestheTC3overflowsignalregardlessoftheTC4CKsetting.
Note5:TousetheTimerCounterinthe16-bitmode,selecttheoperatingmodebyprogrammingTC4M,whereTC3CRmustbesetto011.
TimerCounter4TimerRegisterTTREG4(0016H)R/W76543210(Initialvalue:11111111)PWREG4(001AH)R/W76543210(Initialvalue:11111111)TimerCounter4ControlRegisterTC4CR(000AH)76543210TFF4TC4CKTC4STC4M(Initialvalue:00000000)TFF4TimerF/F4control0:1:ClearSetR/WTC4CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfc–111TC4pininputTC4STC4startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC4MTC4Moperatingmodeselect000:001:010:011:100:101:110:111:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmodeReserved16-bittimer/eventcountermodeWarm-upcountermode16-bitpulsewidthmodulation(PWM)outputmode16-bitPPGmodeR/WPage115TMP86CS28FGNote6:TotheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC3CR.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC4SandTFF4,respectively.
Note7:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-1andTable9-2.
Note8:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable9-3.
Note1:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC3CK).
Note2:Ο:AvailablesourceclockTable9-1OperatingModeandSelectableSourceClock(NORMAL1/2andIDLE1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC3pininputTC4pininput8-bittimerΟΟΟΟ8-biteventcounterΟΟ8-bitPDOΟΟΟΟ8-bitPWMΟΟΟΟΟΟΟ––16-bittimerΟΟΟΟ16-biteventcounterΟ–Warm-upcounter––––Ο––––16-bitPWMΟΟΟΟΟΟΟΟ–16-bitPPGΟΟΟΟ–––Ο–Table9-2OperatingModeandSelectableSourceClock(SLOW1/2andSLEEP1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC3pininputTC4pininput8-bittimerΟ8-biteventcounterΟΟ8-bitPDOΟ8-bitPWMΟ–––Ο––––16-bittimerΟ16-biteventcounterΟ–Warm-upcounterΟ––16-bitPWMΟ–––Ο––Ο–16-bitPPGΟΟ–Note1:Note2:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC3CK).
Ο:AvailablesourceclockPage1169.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FGNote:n=3to4Table9-3ConstraintsonRegisterValuesBeingComparedOperatingmodeRegisterValue8-bittimer/eventcounter1≤(TTREGn)≤2558-bitPDO1≤(TTREGn)≤2558-bitPWM2≤(PWREGn)≤25416-bittimer/eventcounter1≤(TTREG4,3)≤65535Warm-upcounter256≤(TTREG4,3)≤6553516-bitPWM2≤(PWREG4,3)≤6553416-bitPPG1≤(PWREG4,3)to0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Table9-4SourceClockforTimerCounter3,4(InternalClock)SourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
6ms62.
3msfc/27fc/27–8s–2.
0ms–fc/25fc/25–2s–510s–fc/23fc/23–500ns–127.
5s–Example:Settingthetimermodewithsourceclockfc/27Hzandgeneratinganinterrupt80slater(TimerCounter4,fc=16.
0MHz)LD(TTREG4),0AH:Setsthetimerregister(80s÷27/fc=0AH).
DISET(EIRE).
5:EnablesINTTC4interrupt.
EILD(TC4CR),00010000B:Setstheoperatingclocktofc/27,and8-bittimermode.
LD(TC4CR),00011000B:StartsTC4.
Page1189.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FGFigure9-28-BitTimerModeTimingChart(TC4)9.
3.
28-BitEventCounterMode(TC3,4)Inthe8-biteventcountermode,theup-countercountsupatthefallingedgeoftheinputpulsetotheTCjpin.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,anINTTCjinterruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTCjpin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTCjpin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24HzintheSLOW1/2orSLEEP1/2mode.
Note1:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Figure9-38-BitEventCounterModeTimingChart(TC4)9.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC3,4)Thismodeisusedtogenerateapulsewitha50%dutycyclefromthePDOjpin.
InthePDOmode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,thelogicleveloutputfromthePDOjpinisswitchedtotheoppositestateandtheup-counteriscleared.
TheINTTCjinterruptrequestisgeneratedatthetime.
ThelogicstateoppositetothetimerF/FjlogiclevelisoutputfromthePDOjpin.
AnarbitraryvaluecanbesettothetimerF/FjbyTCjCR.
Uponreset,thetimerF/Fjvalueisinitializedto0.
Tousetheprogrammabledivideroutput,settheoutputlatchoftheI/Oportto1.
123n-1n01n-1n20120nInternalSourceClockCounterMatchdetectCounterclearMatchdetectCounterclearTC4CRTTREG4INTTC4interruptrequest102n-1n0120nCounterMatchdetectCounterclearn-1n201MatchdetectCounterclearTC4CRTTREG4INTTC4interruptrequestTC4pininputPage119TMP86CS28FGNote1:Intheprogrammabledivideroutputmode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheprogrammabledivideroutputmode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPDOoutput,thePDOjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRsettinguponstoppingofthetimer.
Example:FixingthePDOjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePDOjpintothehighlevel.
Note3:j=3,4Example:Generating1024HzpulseusingTC4(fc=16.
0MHz)SettingportLD(TTREG4),3DH:1/1024÷27/fc÷2=3DHLD(TC4CR),00010001B:Setstheoperatingclocktofc/27,and8-bitPDOmode.
LD(TC4CR),00011001B:StartsTC4.
Page1209.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FGFigure9-48-BitPDOModeTimingChart(TC4)120n0n0n0n01221212310nInternalsourceclockCounterMatchdetectMatchdetectMatchdetectMatchdetectHeldatthelevelwhenthetimerisstoppedSetF/FWriteof"1"TC4CRTC4CRTTREG4TimerF/F4PDO4pinINTTC4interruptrequestPage121TMP86CS28FG9.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC3,4)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto8bitsofresolution.
Theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthePWREGjvalueisdetected,thelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestateagainbytheup-counteroverflow,andthecounteriscleared.
TheINTTCjinterruptrequestisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/FjbyTCjCR,positiveandnegativepulsescanbegen-erated.
Uponreset,thetimerF/Fjisclearedto0.
(ThelogicleveloutputfromthePWMjpinistheoppositetothetimerF/Fjlogiclevel.
)SincePWREGjinthePWMmodeisseriallyconnectedtotheshiftregister,thevaluesettoPWREGjcanbechangedwhilethetimerisrunning.
ThevaluesettoPWREGjduringarunofthetimerisshiftedbytheINTTCjinterruptrequestandloadedintoPWREGj.
Whilethetimerisstopped,thevalueisshiftedimmedi-atelyaftertheprogrammingofPWREGj.
IfexecutingthereadinstructiontoPWREGjduringPWMoutput,thevalueintheshiftregisterisread,butnotthevaluesetinPWREGj.
Therefore,afterwritingtoPWREGj,thereadingdataofPWREGjispreviousvalueuntilINTTCjisgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREGjimmediatelyaftertheINTTCjinterruptrequestisgenerated(normallyintheINTTCjinterruptserviceroutine.
)IftheprogrammingofPWREGjandtheinter-ruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofthepulsedifferentfromtheprogrammedvalueuntilthenextINTTCjinterruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWMjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRuponstoppingofthetimer.
Example:FixingthePWMjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePWMjpintothehighlevel.
Note3:ToentertheSTOPmodeduringPWMoutput,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwithoutstoppingthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisout-putfromthePWMjpinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Note4:j=3,4Table9-5PWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
8ms62.
5msfc/27fc/27–8s–2.
05ms–fc/25fc/25–2s–512s–fc/23fc/23–500ns–128s–fsfsfs30.
5s30.
5s7.
81ms7.
81msfc/2fc/2–125ns–32s–fcfc–62.
5ns–16s–Page1229.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FGFigure9-58-BitPWMModeTimingChart(TC4)10nn+1FF0nn+1FF01mm+1FF011pnInternalsourceclockCountermpmpnShiftregistarShiftShiftShiftShiftMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectnmpnTC4CRTC4CRPWREG4TimerF/F4PWM4pinINTTC4interruptrequestWritetoPWREG4WritetoPWREG4Page123TMP86CS28FG9.
3.
516-BitTimerMode(TC3and4)Inthetimermode,theup-countercountsupusingtheinternalclock.
TheTimerCounter3and4arecascad-abletoforma16-bittimer.
Whenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,anINTTC4interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-countercontinuescounting.
Programthelowerbyteandupperbyteinthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Inthetimermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMj,andPPGjpinsmayoutputapulse.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogrammingofTTREGj.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=3,4Figure9-616-BitTimerModeTimingChart(TC3andTC4)Table9-6SourceClockfor16-BitTimerModeSourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23fs/23128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–Example:Settingthetimermodewithsourceclockfc/27Hz,andgeneratinganinterrupt300mslater(fc=16.
0MHz)LDW(TTREG3),927CH:Setsthetimerregister(300ms÷27/fc=927CH).
DISET(EIRE).
5:EnablesINTTC4interrupt.
EILD(TC3CR),13H:Setstheoperatingclocktofc/27,and16-bittimermode(lowerbyte).
LD(TC4CR),04H:Setsthe16-bittimermode(upperbyte).
LD(TC4CR),0CH:Startsthetimer.
1023mn-1mn01mn-1mn20120nmInternalsourceclockCounterMatchdetectCounterclearMatchdetectCounterclearTC4CRTTREG3(Lowerbyte)INTTC4interruptrequestTTREG4(Upperbyte)Page1249.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FG9.
3.
616-BitEventCounterMode(TC3and4)9.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC3and4)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto16bitsofresolution.
TheTimerCounter3and4arecascadabletoformthe16-bitPWMsignalgenerator.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG3,PWREG4)valueisdetected,thelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestateagainbythecounteroverflow,andthecounteriscleared.
TheINTTC4interruptisgeneratedatthistime.
Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC3pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
SincetheinitialvaluecanbesettothetimerF/F4byTC4CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F4isclearedto0.
(ThelogicleveloutputfromthePWM4pinistheoppositetothetimerF/F4logiclevel.
)SincePWREG4and3inthePWMmodeareseriallyconnectedtotheshiftregister,thevaluessettoPWREG4and3canbechangedwhilethetimerisrunning.
ThevaluessettoPWREG4and3duringarunofthetimerareshiftedbytheINTTCjinterruptrequestandloadedintoPWREG4and3.
Whilethetimerisstopped,thevaluesareshiftedimmediatelyaftertheprogrammingofPWREG4and3.
Setthelowerbyte(PWREG3)andupperbyte(PWREG4)inthisordertoprogramPWREG4and3.
(Programmingonlythelowerorupperbyteoftheregistershouldnotbeattempted.
)IfexecutingthereadinstructiontoPWREG4and3duringPWMoutput,thevaluessetintheshiftregisterisread,butnotthevaluessetinPWREG4and3.
Therefore,afterwritingtothePWREG4and3,readingdataofPWREG4and3ispreviousvalueuntilINTTC4isgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREG4and3immediatelyaftertheINTTC4interruptrequestisgenerated(normallyintheINTTC4interruptserviceroutine.
)IftheprogrammingofPWREGjandtheinterruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofpulsedifferentfromtheprogrammedvalueuntilthenextINTTC4interruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWM4pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC4CRafterthetimerisstopped.
DonotprogramTC4CRuponstoppingofthetimer.
Example:FixingthePWM4pintothehighlevelwhentheTimerCounterisstoppedIntheeventcountermode,theup-countercountsupatthefallingedgetotheTC3pin.
TheTimerCounter3and4arecascadabletoforma16-biteventcounter.
Whenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,anINTTC4interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTC3pin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC3pin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24intheSLOW1/2orSLEEP1/2mode.
Programthelowerbyte(TTREG3),andupperbyte(TTREG4)inthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Note2:Note3:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimme-diatelyaftertheprogramming.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
j=3,4Page125TMP86CS28FGCLR(TC4CR).
3:Stopsthetimer.
CLR(TC4CR).
7:SetsthePWM4pintothehighlevel.
Note3:ToentertheSTOPmode,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwith-outstoppingofthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisoutputfromthePWM4pinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Table9-716-BitPWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23[Hz]fs/23[Hz]128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–fsfsfs30.
5s30.
5s2s2sfc/2fc/2–125ns–8.
2ms–fcfc–62.
5ns–4.
1ms–Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof32.
768ms(fc=16.
0MHz)SettingportsLDW(PWREG3),07D0H:Setsthepulsewidth.
LD(TC3CR),33H:Setstheoperatingclocktofc/23,and16-bitPWMoutputmode(lowerbyte).
LD(TC4CR),056H:SetsTFF4totheinitialvalue0,and16-bitPWMsignalgenerationmode(upperbyte).
LD(TC4CR),05EH:Startsthetimer.
Page1269.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FGFigure9-716-BitPWMModeTimingChart(TC3andTC4)10anan+1FFFF0anan+1FFFF01bmbm+1FFFF0bmcpbc11cpnaanInternalsourceclock16-bitshiftregisterShiftShiftShiftShiftCounterMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectanbmcpanmpTC4CRTC4CRPWREG3(Lowerbyte)TimerF/F4PWM4pinINTTC4interruptrequestPWREG4(Upperbyte)WritetoPWREG4WritetoPWREG4WritetoPWREG3WritetoPWREG3Page127TMP86CS28FG9.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC3and4)Thismodeisusedtogeneratepulseswithupto16-bitsofresolution.
Thetimercounter3and4arecascad-abletoenterthe16-bitPPGmode.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG3,PWREG4)valueisdetected,thelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F4isswitchedtotheoppositestateagainwhenamatchbetweentheup-counterandthetimerregister(TTREG3,TTREG4)valueisdetected,andthecounteriscleared.
TheINTTC4interruptisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/F4byTC4CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F4isclearedto0.
(ThelogicleveloutputfromthePPG4pinistheoppositetothetimerF/F4.
)Setthelowerbyteandupperbyteinthisordertoprogramthetimerregister.
(TTREG3→TTREG4,PWREG3→PWREG4)(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)ForPPGoutput,settheoutputlatchoftheI/Oportto1.
Note1:InthePPGmode,donotchangethePWREGiandTTREGisettingswhilethetimerisrunning.
SincePWREGiandTTREGiarenotintheshiftregisterconfigurationinthePPGmode,thenewvaluespro-grammedinPWREGiandTTREGiareineffectimmediatelyafterprogrammingPWREGiandTTREGi.
Therefore,ifPWREGiandTTREGiarechangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPPGoutput,thePPG4pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC4CRafterthetimerisstopped.
DonotchangeTC4CRuponstoppingofthetimer.
Example:FixingthePPG4pintothehighlevelwhentheTimerCounterisstoppedCLR(TC4CR).
3:StopsthetimerCLR(TC4CR).
7:SetsthePPG4pintothehighlevelNote3:i=3,4Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC3pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof16.
385ms(fc=16.
0MHz)SettingportsLDW(PWREG3),07D0H:Setsthepulsewidth.
LDW(TTREG3),8002H:Setsthecycleperiod.
LD(TC3CR),33H:Setstheoperatingclocktofc/23,and16-bitPPGmode(lowerbyte).
LD(TC4CR),057H:SetsTFF4totheinitialvalue0,and16-bitPPGmode(upperbyte).
LD(TC4CR),05FH:Startsthetimer.
Page1289.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FGFigure9-816-BitPPGModeTimingChart(TC3andTC4)10mnmn+1qr-1mnqr-11mnmn+1mn+10qr0qr10InternalsourceclockCounterWriteof"0"MatchdetectMatchdetectMatchdetectmnmnmnMatchdetectMatchdetectnmrqHeldatthelevelwhenthetimerstopsF/FclearTC4CRTC4CRPWREG3(Lowerbyte)TimerF/F4PPG4pinINTTC4interruptrequestPWREG4(Upperbyte)TTREG3(Lowerbyte)TTREG4(Upperbyte)Page129TMP86CS28FG9.
3.
9Warm-UpCounterModeInthismode,thewarm-upperiodtimeisobtainedtoassureoscillationstabilitywhenthesystemclockingisswitchedbetweenthehigh-frequencyandlow-frequency.
Thetimercounter3and4arecascadabletoforma16-bitTimerCounter.
Thewarm-upcountermodehastwotypesofmode;switchingfromthehigh-frequencytolow-frequency,andvice-versa.
Note1:Inthewarm-upcountermode,fixTCiCRto0.
Ifnotfixed,thePDOi,PWMiandPPGipinsmayoutputpulses.
Note2:Inthewarm-upcountermode,onlyupper8bitsofthetimerregisterTTREG4and3areusedformatchdetectionandlower8bitsarenotused.
Note3:i=3,49.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)Inthismode,thewarm-upperiodtimefromastopofthelow-frequencyclockfstooscillationstabilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethelow-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG4,3)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,thecounterisclearedbygeneratingtheINTTC4interruptrequest.
AfterstoppingthetimerintheINTTC4interruptserviceroutine,setSYSCR2to1toswitchthesystemclockfromthehigh-frequencytolow-frequency,andthenclearofSYSCR2to0tostopthehigh-frequencyclock.
Table9-8SettingTimeofLow-FrequencyWarm-UpCounterMode(fs=32.
768kHz)MinimumTimeSetting(TTREG4,3=0100H)MaximumTimeSetting(TTREG4,3=FF00H)7.
81ms1.
99sExample:Aftercheckinglow-frequencyclockoscillationstabilitywithTC4and3,switchingtotheSLOW1modeSET(SYSCR2).
6:SYSCR2←1LD(TC3CR),43H:SetsTFF3=0,sourceclockfs,and16-bitmode.
LD(TC4CR),05H:SetsTFF4=0,andwarm-upcountermode.
LD(TTREG3),8000H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRE).
5:EnablestheINTTC4.
EI:IMF←1SET(TC4CR).
3:StartsTC4and3.
::PINTTC4:CLR(TC4CR).
3:StopsTC4and3.
SET(SYSCR2).
5:SYSCR2←1(Switchesthesystemclocktothelow-frequencyclock.
)CLR(SYSCR2).
7:SYSCR2←0(Stopsthehigh-frequencyclock.
)RETI::VINTTC4:DWPINTTC4:INTTC4vectortablePage1309.
8-BitTimerCounter(TC3,TC4)9.
1ConfigurationTMP86CS28FG9.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)Inthismode,thewarm-upperiodtimefromastopofthehigh-frequencyclockfctotheoscillationsta-bilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethehigh-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG4,3)valueisdetectedafterthetimerisstartedbysettingTC4CRto1,thecounterisclearedbygeneratingtheINTTC4interruptrequest.
AfterstoppingthetimerintheINTTC4interruptserviceroutine,clearSYSCR2to0toswitchthesystemclockfromthelow-frequencytohigh-frequency,andthenSYSCR2to0tostopthelow-frequencyclock.
Table9-9SettingTimeinHigh-FrequencyWarm-UpCounterModeMinimumtimeSetting(TTREG4,3=0100H)MaximumtimeSetting(TTREG4,3=FF00H)16s4.
08msExample:Aftercheckinghigh-frequencyclockoscillationstabilitywithTC4and3,switchingtotheNORMAL1modeSET(SYSCR2).
7:SYSCR2←1LD(TC3CR),63H:SetsTFF3=0,sourceclockfc,and16-bitmode.
LD(TC4CR),05H:SetsTFF4=0,andwarm-upcountermode.
LD(TTREG3),0F800H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRE).
5:EnablestheINTTC4.
EI:IMF←1SET(TC4CR).
3:StartstheTC4and3.
::PINTTC4:CLR(TC4CR).
3:StopstheTC4and3.
CLR(SYSCR2).
5:SYSCR2←0(Switchesthesystemclocktothehigh-frequencyclock.
)CLR(SYSCR2).
6:SYSCR2←0(Stopsthelow-frequencyclock.
)RETI::VINTTC4:DWPINTTC4:INTTC4vectortablePage131TMP86CS28FG10.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationFigure10-18-BitTimerCounter5,68-bitup-counterDecodeENAYBSABYCDEFGHSAYBSSAYBToggleQSetClear8-bitup-counterABYCDEFGHSDecodeENToggleQSetClearPWMmodePDO,PPGmodePDOmodePWM,PPGmodePWMmodePWMmode16-bitmode16-bitmode16-bitmode16-bitmodeTimer,EventCountermodeOverflowOverflowTimer,EventCoutermode16-bitmodeClearClearfc/27fc/25fc/23fc/2fcfc/27fc/25fc/23fc/2fcPDO,PWM,PPGmodePDO,PWMmode16-bitmodefc/211orfs/23fc/211orfs/23fsfsTC6CRTC5CRTTREG6PWREG6TTREG5PWREG5TC5pinTC6pinTC6STC5SINTTC5interruptrequestINTTC6interruptrequestTFF6TFF5PDO6/PWM6/PPG6pinPDO5/PWM5/pinTC5CKTC6CKTC5MTC5STFF5TC6MTC6STFF6TimerF/F6TimerF/F5Page13210.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FG10.
2TimerCounterControlTheTimerCounter5iscontrolledbytheTimerCounter5controlregister(TC5CR)andtwo8-bittimerregisters(TTREG5,PWREG5).
Note1:Donotchangethetimerregister(TTREG5)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG5)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC5M,TC5CKandTFF5settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC5S=1→0),donotchangetheTC5M,TC5CKandTFF5settings.
Tostartthetimeropera-tion(TC5S=0→1),TC5M,TC5CKandTFF5canbeprogrammed.
Note4:TousetheTimerCounterinthe16-bitmode,settheoperatingmodebyprogrammingTC6CR,whereTC5Mmustbefixedto011.
Note5:TousetheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC5CK.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC6CRandTC6CR,respectively.
Note6:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-1andTable10-2.
TimerCounter5TimerRegisterTTREG5(0017H)R/W76543210(Initialvalue:11111111)PWREG5(001BH)R/W76543210(Initialvalue:11111111)TimerCounter5ControlRegisterTC5CR(000BH)76543210TFF5TC5CKTC5STC5M(Initialvalue:00000000)TFF5TimeF/F5control0:1:ClearSetR/WTC5CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfcfc(Note8)111TC5pininputTC5STC5startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC5MTC5Moperatingmodeselect000:001:010:011:1**:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmode16-bitmode(EachmodeisselectablewithTC6M.
)ReservedR/WPage133TMP86CS28FGNote7:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-3.
Note8:TheoperatingclockfcintheSLOWorSLEEPmodecanbeusedonlyasthehigh-frequencywarm-upmode.
Page13410.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FGTheTimerCounter6iscontrolledbytheTimerCounter6controlregister(TC6CR)andtwo8-bittimerregisters(TTREG6andPWREG6).
Note1:Donotchangethetimerregister(TTREG6)settingwhilethetimerisrunning.
Note2:Donotchangethetimerregister(PWREG6)settingintheoperatingmodeexceptthe8-bitand16-bitPWMmodeswhilethetimerisrunning.
Note1:fc:High-frequencyclock[Hz]fs:Low-frequencyclock[Hz]Note2:DonotchangetheTC6M,TC6CKandTFF6settingswhilethetimerisrunning.
Note3:Tostopthetimeroperation(TC6S=1→0),donotchangetheTC6M,TC6CKandTFF6settings.
Tostartthetimeroperation(TC6S=0→1),TC6M,TC6CKandTFF6canbeprogrammed.
Note4:WhenTC6M=1**(upperbyteinthe16-bitmode),thesourceclockbecomestheTC5overflowsignalregardlessoftheTC6CKsetting.
Note5:TousetheTimerCounterinthe16-bitmode,selecttheoperatingmodebyprogrammingTC6M,whereTC5CRmustbesetto011.
TimerCounter6TimerRegisterTTREG6(0018H)R/W76543210(Initialvalue:11111111)PWREG6(001CH)R/W76543210(Initialvalue:11111111)TimerCounter6ControlRegisterTC6CR(000CH)76543210TFF6TC6CKTC6STC6M(Initialvalue:00000000)TFF6TimerF/F6control0:1:ClearSetR/WTC6CKOperatingclockselection[Hz]NORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeR/WDV7CK=0DV7CK=1000fc/211fs/23fs/23001fc/27fc/27–010fc/25fc/25–011fc/23fc/23–100fsfsfs101fc/2fc/2–110fcfc–111TC6pininputTC6STC6startcontrol0:1:OperationstopandcounterclearOperationstartR/WTC6MTC6Moperatingmodeselect000:001:010:011:100:101:110:111:8-bittimer/eventcountermode8-bitprogrammabledivideroutput(PDO)mode8-bitpulsewidthmodulation(PWM)outputmodeReserved16-bittimer/eventcountermodeWarm-upcountermode16-bitpulsewidthmodulation(PWM)outputmode16-bitPPGmodeR/WPage135TMP86CS28FGNote6:TotheTimerCounterinthe16-bitmode,selectthesourceclockbyprogrammingTC5CR.
SetthetimerstartcontrolandtimerF/FcontrolbyprogrammingTC6SandTFF6,respectively.
Note7:Theoperatingclocksettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-1andTable10-2.
Note8:Thetimerregistersettingsarelimiteddependingonthetimeroperatingmode.
Forthedetaileddescriptions,seeTable10-3.
Note1:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC5CK).
Note2:Ο:AvailablesourceclockTable10-1OperatingModeandSelectableSourceClock(NORMAL1/2andIDLE1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC5pininputTC6pininput8-bittimerΟΟΟΟ8-biteventcounterΟΟ8-bitPDOΟΟΟΟ8-bitPWMΟΟΟΟΟΟΟ––16-bittimerΟΟΟΟ16-biteventcounterΟ–Warm-upcounter––––Ο––––16-bitPWMΟΟΟΟΟΟΟΟ–16-bitPPGΟΟΟΟ–––Ο–Table10-2OperatingModeandSelectableSourceClock(SLOW1/2andSLEEP1/2Modes)Operatingmodefc/211orfs/23fc/27fc/25fc/23fsfc/2fcTC5pininputTC6pininput8-bittimerΟ8-biteventcounterΟΟ8-bitPDOΟ8-bitPWMΟ–––Ο––––16-bittimerΟ16-biteventcounterΟ–Warm-upcounterΟ––16-bitPWMΟ–––Ο––Ο–16-bitPPGΟΟ–Note1:Note2:For16-bitoperations(16-bittimer/eventcounter,warm-upcounter,16-bitPWMand16-bitPPG),setitssourceclockonlowerbit(TC5CK).
Ο:AvailablesourceclockPage13610.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FGNote:n=5to6Table10-3ConstraintsonRegisterValuesBeingComparedOperatingmodeRegisterValue8-bittimer/eventcounter1≤(TTREGn)≤2558-bitPDO1≤(TTREGn)≤2558-bitPWM2≤(PWREGn)≤25416-bittimer/eventcounter1≤(TTREG6,5)≤65535Warm-upcounter256≤(TTREG6,5)≤6553516-bitPWM2≤(PWREG6,5)≤6553416-bitPPG1≤(PWREG6,5)to0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Table10-4SourceClockforTimerCounter5,6(InternalClock)SourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
6ms62.
3msfc/27fc/27–8s–2.
0ms–fc/25fc/25–2s–510s–fc/23fc/23–500ns–127.
5s–Example:Settingthetimermodewithsourceclockfc/27Hzandgeneratinganinterrupt80slater(TimerCounter6,fc=16.
0MHz)LD(TTREG6),0AH:Setsthetimerregister(80s÷27/fc=0AH).
DISET(EIRD).
0:EnablesINTTC6interrupt.
EILD(TC6CR),00010000B:Setstheoperatingclocktofc/27,and8-bittimermode.
LD(TC6CR),00011000B:StartsTC6.
Page13810.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FGFigure10-28-BitTimerModeTimingChart(TC6)10.
3.
28-BitEventCounterMode(TC5,6)Inthe8-biteventcountermode,theup-countercountsupatthefallingedgeoftheinputpulsetotheTCjpin.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,anINTTCjinterruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTCjpin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTCjpin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24HzintheSLOW1/2orSLEEP1/2mode.
Note1:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Note2:Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyaftertheprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Figure10-38-BitEventCounterModeTimingChart(TC6)10.
3.
38-BitProgrammableDividerOutput(PDO)Mode(TC5,6)Thismodeisusedtogenerateapulsewitha50%dutycyclefromthePDOjpin.
InthePDOmode,theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandtheTTREGjvalueisdetected,thelogicleveloutputfromthePDOjpinisswitchedtotheoppositestateandtheup-counteriscleared.
TheINTTCjinterruptrequestisgeneratedatthetime.
ThelogicstateoppositetothetimerF/FjlogiclevelisoutputfromthePDOjpin.
AnarbitraryvaluecanbesettothetimerF/FjbyTCjCR.
Uponreset,thetimerF/Fjvalueisinitializedto0.
Tousetheprogrammabledivideroutput,settheoutputlatchoftheI/Oportto1.
123n-1n01n-1n20120nInternalSourceClockCounterMatchdetectCounterclearMatchdetectCounterclearTC6CRTTREG6INTTC6interruptrequest102n-1n0120nCounterMatchdetectCounterclearn-1n201MatchdetectCounterclearTC6CRTTREG6INTTC6interruptrequestTC6pininputPage139TMP86CS28FGNote1:Intheprogrammabledivideroutputmode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheprogrammabledivideroutputmode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogramming.
Therefore,ifTTREGiischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPDOoutput,thePDOjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRsettinguponstoppingofthetimer.
Example:FixingthePDOjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePDOjpintothehighlevel.
Note3:j=5,6Example:Generating1024HzpulseusingTC6(fc=16.
0MHz)SettingportLD(TTREG6),3DH:1/1024÷27/fc÷2=3DHLD(TC6CR),00010001B:Setstheoperatingclocktofc/27,and8-bitPDOmode.
LD(TC6CR),00011001B:StartsTC6.
Page14010.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FGFigure10-48-BitPDOModeTimingChart(TC6)120n0n0n0n01221212310nInternalsourceclockCounterMatchdetectMatchdetectMatchdetectMatchdetectHeldatthelevelwhenthetimerisstoppedSetF/FWriteof"1"TC6CRTC6CRTTREG6TimerF/F6PDO6pinINTTC6interruptrequestPage141TMP86CS28FG10.
3.
48-BitPulseWidthModulation(PWM)OutputMode(TC5,6)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto8bitsofresolution.
Theup-countercountsupusingtheinternalclock.
Whenamatchbetweentheup-counterandthePWREGjvalueisdetected,thelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/Fjisswitchedtotheoppositestateagainbytheup-counteroverflow,andthecounteriscleared.
TheINTTCjinterruptrequestisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/FjbyTCjCR,positiveandnegativepulsescanbegen-erated.
Uponreset,thetimerF/Fjisclearedto0.
(ThelogicleveloutputfromthePWMjpinistheoppositetothetimerF/Fjlogiclevel.
)SincePWREGjinthePWMmodeisseriallyconnectedtotheshiftregister,thevaluesettoPWREGjcanbechangedwhilethetimerisrunning.
ThevaluesettoPWREGjduringarunofthetimerisshiftedbytheINTTCjinterruptrequestandloadedintoPWREGj.
Whilethetimerisstopped,thevalueisshiftedimmedi-atelyaftertheprogrammingofPWREGj.
IfexecutingthereadinstructiontoPWREGjduringPWMoutput,thevalueintheshiftregisterisread,butnotthevaluesetinPWREGj.
Therefore,afterwritingtoPWREGj,thereadingdataofPWREGjispreviousvalueuntilINTTCjisgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREGjimmediatelyaftertheINTTCjinterruptrequestisgenerated(normallyintheINTTCjinterruptserviceroutine.
)IftheprogrammingofPWREGjandtheinter-ruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofthepulsedifferentfromtheprogrammedvalueuntilthenextINTTCjinterruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWMjpinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTCjCRafterthetimerisstopped.
DonotchangetheTCjCRuponstoppingofthetimer.
Example:FixingthePWMjpintothehighlevelwhentheTimerCounterisstoppedCLR(TCjCR).
3:Stopsthetimer.
CLR(TCjCR).
7:SetsthePWMjpintothehighlevel.
Note3:ToentertheSTOPmodeduringPWMoutput,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwithoutstoppingthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisout-putfromthePWMjpinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Note4:j=5,6Table10-5PWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211[Hz]fs/23[Hz]fs/23[Hz]128s244.
14s32.
8ms62.
5msfc/27fc/27–8s–2.
05ms–fc/25fc/25–2s–512s–fc/23fc/23–500ns–128s–fsfsfs30.
5s30.
5s7.
81ms7.
81msfc/2fc/2–125ns–32s–fcfc–62.
5ns–16s–Page14210.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FGFigure10-58-BitPWMModeTimingChart(TC6)10nn+1FF0nn+1FF01mm+1FF011pnInternalsourceclockCountermpmpnShiftregistarShiftShiftShiftShiftMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectnmpnTC6CRTC6CRPWREG6TimerF/F6PWM6pinINTTC6interruptrequestWritetoPWREG6WritetoPWREG6Page143TMP86CS28FG10.
3.
516-BitTimerMode(TC5and6)Inthetimermode,theup-countercountsupusingtheinternalclock.
TheTimerCounter5and6arecascad-abletoforma16-bittimer.
Whenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,anINTTC6interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-countercontinuescounting.
Programthelowerbyteandupperbyteinthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Inthetimermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMj,andPPGjpinsmayoutputapulse.
Note2:Inthetimermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationinthetimermode,thenewvalueprogrammedinTTREGjisineffectimmediatelyafterprogrammingofTTREGj.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note3:j=5,6Figure10-616-BitTimerModeTimingChart(TC5andTC6)Table10-6SourceClockfor16-BitTimerModeSourceClockResolutionMaximumTimeSettingNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23fs/23128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–Example:Settingthetimermodewithsourceclockfc/27Hz,andgeneratinganinterrupt300mslater(fc=16.
0MHz)LDW(TTREG5),927CH:Setsthetimerregister(300ms÷27/fc=927CH).
DISET(EIRD).
0:EnablesINTTC6interrupt.
EILD(TC5CR),13H:Setstheoperatingclocktofc/27,and16-bittimermode(lowerbyte).
LD(TC6CR),04H:Setsthe16-bittimermode(upperbyte).
LD(TC6CR),0CH:Startsthetimer.
1023mn-1mn01mn-1mn20120nmInternalsourceclockCounterMatchdetectCounterclearMatchdetectCounterclearTC6CRTTREG5(Lowerbyte)INTTC6interruptrequestTTREG6(Upperbyte)Page14410.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FG10.
3.
616-BitEventCounterMode(TC5and6)10.
3.
716-BitPulseWidthModulation(PWM)OutputMode(TC5and6)Thismodeisusedtogenerateapulse-widthmodulated(PWM)signalswithupto16bitsofresolution.
TheTimerCounter5and6arecascadabletoformthe16-bitPWMsignalgenerator.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG5,PWREG6)valueisdetected,thelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestateagainbythecounteroverflow,andthecounteriscleared.
TheINTTC6interruptisgeneratedatthistime.
Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC5pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
SincetheinitialvaluecanbesettothetimerF/F6byTC6CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F6isclearedto0.
(ThelogicleveloutputfromthePWM6pinistheoppositetothetimerF/F6logiclevel.
)SincePWREG6and5inthePWMmodeareseriallyconnectedtotheshiftregister,thevaluessettoPWREG6and5canbechangedwhilethetimerisrunning.
ThevaluessettoPWREG6and5duringarunofthetimerareshiftedbytheINTTCjinterruptrequestandloadedintoPWREG6and5.
Whilethetimerisstopped,thevaluesareshiftedimmediatelyaftertheprogrammingofPWREG6and5.
Setthelowerbyte(PWREG5)andupperbyte(PWREG6)inthisordertoprogramPWREG6and5.
(Programmingonlythelowerorupperbyteoftheregistershouldnotbeattempted.
)IfexecutingthereadinstructiontoPWREG6and5duringPWMoutput,thevaluessetintheshiftregisterisread,butnotthevaluessetinPWREG6and5.
Therefore,afterwritingtothePWREG6and5,readingdataofPWREG6and5ispreviousvalueuntilINTTC6isgenerated.
ForthepinusedforPWMoutput,theoutputlatchoftheI/Oportmustbesetto1.
Note1:InthePWMmode,programthetimerregisterPWREG6and5immediatelyaftertheINTTC6interruptrequestisgenerated(normallyintheINTTC6interruptserviceroutine.
)IftheprogrammingofPWREGjandtheinterruptrequestoccuratthesametime,anunstablevalueisshifted,thatmayresultingenerationofpulsedifferentfromtheprogrammedvalueuntilthenextINTTC6interruptrequestisgenerated.
Note2:WhenthetimerisstoppedduringPWMoutput,thePWM6pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC6CRafterthetimerisstopped.
DonotprogramTC6CRuponstoppingofthetimer.
Example:FixingthePWM6pintothehighlevelwhentheTimerCounterisstoppedIntheeventcountermode,theup-countercountsupatthefallingedgetotheTC5pin.
TheTimerCounter5and6arecascadabletoforma16-biteventcounter.
Whenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,anINTTC6interruptisgeneratedandtheup-counteriscleared.
Afterbeingcleared,theup-counterrestartscountingatthefallingedgeoftheinputpulsetotheTC5pin.
Twomachinecyclesarerequiredforthelow-orhigh-levelpulseinputtotheTC5pin.
Therefore,amaximumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24intheSLOW1/2orSLEEP1/2mode.
Programthelowerbyte(TTREG5),andupperbyte(TTREG6)inthisorderinthetimerregister.
(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)Note1:Note2:Note3:Intheeventcountermode,fixTCjCRto0.
Ifnotfixed,thePDOj,PWMjandPPGjpinsmayoutputpulses.
Intheeventcountermode,donotchangetheTTREGjsettingwhilethetimerisrunning.
SinceTTREGjisnotintheshiftregisterconfigurationintheeventcountermode,thenewvalueprogrammedinTTREGjisineffectimme-diatelyaftertheprogramming.
Therefore,ifTTREGjischangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
j=5,6Page145TMP86CS28FGCLR(TC6CR).
3:Stopsthetimer.
CLR(TC6CR).
7:SetsthePWM6pintothehighlevel.
Note3:ToentertheSTOPmode,stopthetimerandthenentertheSTOPmode.
IftheSTOPmodeisenteredwith-outstoppingofthetimerwhenfc,fc/2orfsisselectedasthesourceclock,apulseisoutputfromthePWM6pinduringthewarm-upperiodtimeafterexitingtheSTOPmode.
Table10-716-BitPWMOutputModeSourceClockResolutionRepeatedCycleNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modefc=16MHzfs=32.
768kHzfc=16MHzfs=32.
768kHzDV7CK=0DV7CK=1fc/211fs/23[Hz]fs/23[Hz]128s244.
14s8.
39s16sfc/27fc/27–8s–524.
3ms–fc/25fc/25–2s–131.
1ms–fc/23fc/23–500ns–32.
8ms–fsfsfs30.
5s30.
5s2s2sfc/2fc/2–125ns–8.
2ms–fcfc–62.
5ns–4.
1ms–Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof32.
768ms(fc=16.
0MHz)SettingportsLDW(PWREG5),07D0H:Setsthepulsewidth.
LD(TC5CR),33H:Setstheoperatingclocktofc/23,and16-bitPWMoutputmode(lowerbyte).
LD(TC6CR),056H:SetsTFF6totheinitialvalue0,and16-bitPWMsignalgenerationmode(upperbyte).
LD(TC6CR),05EH:Startsthetimer.
Page14610.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FGFigure10-716-BitPWMModeTimingChart(TC5andTC6)10anan+1FFFF0anan+1FFFF01bmbm+1FFFF0bmcpbc11cpnaanInternalsourceclock16-bitshiftregisterShiftShiftShiftShiftCounterMatchdetectMatchdetectOnecycleperiodMatchdetectMatchdetectanbmcpanmpTC6CRTC6CRPWREG5(Lowerbyte)TimerF/F6PWM6pinINTTC6interruptrequestPWREG6(Upperbyte)WritetoPWREG6WritetoPWREG6WritetoPWREG5WritetoPWREG5Page147TMP86CS28FG10.
3.
816-BitProgrammablePulseGenerate(PPG)OutputMode(TC5and6)Thismodeisusedtogeneratepulseswithupto16-bitsofresolution.
Thetimercounter5and6arecascad-abletoenterthe16-bitPPGmode.
Thecountercountsupusingtheinternalclockorexternalclock.
Whenamatchbetweentheup-counterandthetimerregister(PWREG5,PWREG6)valueisdetected,thelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestate.
Thecountercontinuescounting.
ThelogicleveloutputfromthetimerF/F6isswitchedtotheoppositestateagainwhenamatchbetweentheup-counterandthetimerregister(TTREG5,TTREG6)valueisdetected,andthecounteriscleared.
TheINTTC6interruptisgeneratedatthistime.
SincetheinitialvaluecanbesettothetimerF/F6byTC6CR,positiveandnegativepulsescanbegenerated.
Uponreset,thetimerF/F6isclearedto0.
(ThelogicleveloutputfromthePPG6pinistheoppositetothetimerF/F6.
)Setthelowerbyteandupperbyteinthisordertoprogramthetimerregister.
(TTREG5→TTREG6,PWREG5→PWREG6)(Programmingonlytheupperorlowerbyteshouldnotbeattempted.
)ForPPGoutput,settheoutputlatchoftheI/Oportto1.
Note1:InthePPGmode,donotchangethePWREGiandTTREGisettingswhilethetimerisrunning.
SincePWREGiandTTREGiarenotintheshiftregisterconfigurationinthePPGmode,thenewvaluespro-grammedinPWREGiandTTREGiareineffectimmediatelyafterprogrammingPWREGiandTTREGi.
Therefore,ifPWREGiandTTREGiarechangedwhilethetimerisrunning,anexpectedoperationmaynotbeobtained.
Note2:WhenthetimerisstoppedduringPPGoutput,thePPG6pinholdstheoutputstatuswhenthetimerisstopped.
Tochangetheoutputstatus,programTC6CRafterthetimerisstopped.
DonotchangeTC6CRuponstoppingofthetimer.
Example:FixingthePPG6pintothehighlevelwhentheTimerCounterisstoppedCLR(TC6CR).
3:StopsthetimerCLR(TC6CR).
7:SetsthePPG6pintothehighlevelNote3:i=5,6Twomachinecyclesarerequiredforthehigh-orlow-levelpulseinputtotheTC5pin.
Therefore,amaxi-mumfrequencytobesuppliedisfc/24HzintheNORMAL1/2orIDLE1/2mode,andfs/24tointheSLOW1/2orSLEEP1/2mode.
Example:Generatingapulsewith1-mshigh-levelwidthandaperiodof16.
385ms(fc=16.
0MHz)SettingportsLDW(PWREG5),07D0H:Setsthepulsewidth.
LDW(TTREG5),8002H:Setsthecycleperiod.
LD(TC5CR),33H:Setstheoperatingclocktofc/23,and16-bitPPGmode(lowerbyte).
LD(TC6CR),057H:SetsTFF6totheinitialvalue0,and16-bitPPGmode(upperbyte).
LD(TC6CR),05FH:Startsthetimer.
Page14810.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FGFigure10-816-BitPPGModeTimingChart(TC5andTC6)10mnmn+1qr-1mnqr-11mnmn+1mn+10qr0qr10InternalsourceclockCounterWriteof"0"MatchdetectMatchdetectMatchdetectmnmnmnMatchdetectMatchdetectnmrqHeldatthelevelwhenthetimerstopsF/FclearTC6CRTC6CRPWREG5(Lowerbyte)TimerF/F6PPG6pinINTTC6interruptrequestPWREG6(Upperbyte)TTREG5(Lowerbyte)TTREG6(Upperbyte)Page149TMP86CS28FG10.
3.
9Warm-UpCounterModeInthismode,thewarm-upperiodtimeisobtainedtoassureoscillationstabilitywhenthesystemclockingisswitchedbetweenthehigh-frequencyandlow-frequency.
Thetimercounter5and6arecascadabletoforma16-bitTimerCounter.
Thewarm-upcountermodehastwotypesofmode;switchingfromthehigh-frequencytolow-frequency,andvice-versa.
Note1:Inthewarm-upcountermode,fixTCiCRto0.
Ifnotfixed,thePDOi,PWMiandPPGipinsmayoutputpulses.
Note2:Inthewarm-upcountermode,onlyupper8bitsofthetimerregisterTTREG6and5areusedformatchdetectionandlower8bitsarenotused.
Note3:i=5,610.
3.
9.
1Low-FrequencyWarm-upCounterMode(NORMAL1→NORMAL2→SLOW2→SLOW1)Inthismode,thewarm-upperiodtimefromastopofthelow-frequencyclockfstooscillationstabilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethelow-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG6,5)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,thecounterisclearedbygeneratingtheINTTC6interruptrequest.
AfterstoppingthetimerintheINTTC6interruptserviceroutine,setSYSCR2to1toswitchthesystemclockfromthehigh-frequencytolow-frequency,andthenclearofSYSCR2to0tostopthehigh-frequencyclock.
Table10-8SettingTimeofLow-FrequencyWarm-UpCounterMode(fs=32.
768kHz)MinimumTimeSetting(TTREG6,5=0100H)MaximumTimeSetting(TTREG6,5=FF00H)7.
81ms1.
99sExample:Aftercheckinglow-frequencyclockoscillationstabilitywithTC6and5,switchingtotheSLOW1modeSET(SYSCR2).
6:SYSCR2←1LD(TC5CR),43H:SetsTFF5=0,sourceclockfs,and16-bitmode.
LD(TC6CR),05H:SetsTFF6=0,andwarm-upcountermode.
LD(TTREG5),8000H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRD).
0:EnablestheINTTC6.
EI:IMF←1SET(TC6CR).
3:StartsTC6and5.
::PINTTC6:CLR(TC6CR).
3:StopsTC6and5.
SET(SYSCR2).
5:SYSCR2←1(Switchesthesystemclocktothelow-frequencyclock.
)CLR(SYSCR2).
7:SYSCR2←0(Stopsthehigh-frequencyclock.
)RETI::VINTTC6:DWPINTTC6:INTTC6vectortablePage15010.
8-BitTimerCounter(TC5,TC6)10.
1ConfigurationTMP86CS28FG10.
3.
9.
2High-FrequencyWarm-UpCounterMode(SLOW1→SLOW2→NORMAL2→NORMAL1)Inthismode,thewarm-upperiodtimefromastopofthehigh-frequencyclockfctotheoscillationsta-bilityisobtained.
Beforestartingthetimer,setSYSCR2to1tooscillatethehigh-frequencyclock.
Whenamatchbetweentheup-counterandthetimerregister(TTREG6,5)valueisdetectedafterthetimerisstartedbysettingTC6CRto1,thecounterisclearedbygeneratingtheINTTC6interruptrequest.
AfterstoppingthetimerintheINTTC6interruptserviceroutine,clearSYSCR2to0toswitchthesystemclockfromthelow-frequencytohigh-frequency,andthenSYSCR2to0tostopthelow-frequencyclock.
Table10-9SettingTimeinHigh-FrequencyWarm-UpCounterModeMinimumtimeSetting(TTREG6,5=0100H)MaximumtimeSetting(TTREG6,5=FF00H)16s4.
08msExample:Aftercheckinghigh-frequencyclockoscillationstabilitywithTC6and5,switchingtotheNORMAL1modeSET(SYSCR2).
7:SYSCR2←1LD(TC5CR),63H:SetsTFF5=0,sourceclockfc,and16-bitmode.
LD(TC6CR),05H:SetsTFF6=0,andwarm-upcountermode.
LD(TTREG5),0F800H:Setsthewarm-uptime.
(Thewarm-uptimedependsontheoscillatorcharacteristic.
)DI:IMF←0SET(EIRD).
0:EnablestheINTTC6.
EI:IMF←1SET(TC6CR).
3:StartstheTC6and5.
::PINTTC6:CLR(TC6CR).
3:StopstheTC6and5.
CLR(SYSCR2).
5:SYSCR2←0(Switchesthesystemclocktothehigh-frequencyclock.
)CLR(SYSCR2).
6:SYSCR2←0(Stopsthelow-frequencyclock.
)RETI::VINTTC6:DWPINTTC6:INTTC6vectortablePage151TMP86CS28FG11.
SynchronousSerialInterface(SIO)TheTMP86CS28FGhasaclocked-synchronous8-bitserialinterface.
Serialinterfacehasan8-bytetransmitandreceivedatabufferthatcanautomaticallyandcontinuouslytransferupto64bitsofdata.
SerialinterfaceisconnectedtooutsideperipherldevicesviaSO,SI,SCKport.
11.
1ConfigurationFigure11-1SerialInterfaceSIOcontrol/statusregisterSerialclockShiftclockShiftregister32107654Transmitandreceivedatabuffer(8bytesinDBR)ControlcircuitCPUSerialdataoutputSerialdatainput8-bittransfer4-bittransferSerialclockI/OBuffercontrolcircuitSOSISCKSIOCR2SIOCR1SIOSRINTSIOinterruptrequestPage15211.
SynchronousSerialInterface(SIO)11.
2ControlTMP86CS28FG11.
2ControlTheserialinterfaceiscontrolledbySIOcontrolregisters(SIOCR1/SIOCR2).
TheserialinterfacestatuscanbedeterminedbyreadingSIOstatusregister(SIOSR).
ThetransmitandreceivedatabufferiscontrolledbytheSIOCR2.
Thedatabufferisassignedtoaddress0F60Hto0F67HforSIOintheDBRarea,andcancontinuouslytransferupto8words(bytesornibbles)atonetime.
Whenthespecifiednumberofwordshasbeentransferred,abufferempty(inthetransmitmode)orabufferfull(inthereceivemodeortransmit/receivemode)interrupt(INTSIO)isgenerated.
Whentheinternalclockisusedastheserialclockinthe8-bitreceivemodeandthe8-bittransmit/receivemode,afixedintervalwaitcanbeappliedtotheserialclockforeachwordtransferred.
FourdifferentwaittimescanbeselectedwithSIOCR2.
Note1:fc;High-frequencyclock[Hz],fs;Low-frequencyclock[Hz]Note2:SetSIOSto"0"andSIOINHto"1"whensettingthetransfermodeorserialclock.
Note3:SIOCR1iswrite-onlyregister,whichcannotaccessanyofinread-modify-writeinstructionsuchasbitoperate,etc.
SIOControlRegister1SIOCR176543210(0F68H)SIOSSIOINHSIOMSCK(Initialvalue:00000000)SIOSIndicatetransferstart/stop0:StopWriteonly1:StartSIOINHContinue/aborttransfer0:Continuouslytransfer1:Aborttransfer(Automaticallyclearedafterabort)SIOMTransfermodeselect000:8-bittransmitmode010:4-bittransmitmode100:8-bittransmit/receivemode101:8-bitreceivemode110:4-bitreceivemodeExcepttheabove:ReservedSCKSerialclockselectNORMAL1/2,IDLE1/2modeSLOW1/2SLEEP1/2modeWriteonlyDV7CK=0DV7CK=1000fc/213fs/25fs/25001fc/28fc/28-010fc/27fc/27-011fc/26fc/26-100fc/25fc/25-101fc/24fc/24-110Reserved111Externalclock(InputfromSCKpin)SIOControlRegister2SIOCR276543210(0F69H)WAITBUF(Initialvalue:***00000)Page153TMP86CS28FGNote1:Thelower4bitsofeachbufferareusedduring4-bittransfers.
Zeros(0)arestoredtotheupper4bitswhenreceiving.
Note2:Transmittingstartsatthelowestaddress.
Receiveddataarealsostoredstartingfromthelowestaddresstothehighestaddress.
(Thefirstbufferaddresstransmittedis0F60H).
Note3:ThevaluetobeloadedtoBUFisheldaftertransferiscompleted.
Note4:SIOCR2mustbesetwhentheserialinterfaceisstopped(SIOF=0).
Note5:*:Don'tcareNote6:SIOCR2iswrite-onlyregister,whichcannotaccessanyofinread-modify-writeinstructionsuchasbitoperate,etc.
Note1:Tf;Frametime,TD;DatatransfertimeNote2:AfterSIOSisclearedto"0",SIOFisclearedto"0"attheterminationoftransferorthesettingofSIOINHto"1".
Figure11-2Frametime(Tf)andDatatransfertime(TD)11.
3Serialclock11.
3.
1ClocksourceInternalclockorexternalclockforthesourceclockisselectedbySIOCR1.
WAITWaitcontrolAlwayssets"00"except8-bittransmit/receivemode.
Writeonly00:Tf=TD(Nonwait)01:Tf=2TD(Wait)10:Tf=4TD(Wait)11:Tf=8TD(Wait)BUFNumberoftransferwords(Bufferaddressinuse)000:1wordtransfer0F60H001:2wordstransfer0F60H~0F61H010:3wordstransfer0F60H~0F62H011:4wordstransfer0F60H~0F63H100:5wordstransfer0F60H~0F64H101:6wordstransfer0F60H~0F65H110:7wordstransfer0F60H~0F66H111:8wordstransfer0F60H~0F67HSIOStatusRegisterSIOSR76543210(0F69H)SIOFSEFSIOFSerialtransferoperatingstatusmoni-tor0:1:TransferterminatedTransferinprocessReadonlySEFShiftoperatingstatusmonitor0:1:ShiftoperationterminatedShiftoperationinprocessTDTf(output)SCKoutputPage15411.
SynchronousSerialInterface(SIO)11.
3SerialclockTMP86CS28FG11.
3.
1.
1InternalclockAnyofsixfrequenciescanbeselected.
TheserialclockisoutputtotheoutsideontheSCKpin.
TheSCKpingoeshighwhentransferstarts.
Whendatawriting(inthetransmitmode)orreading(inthereceivemodeorthetransmit/receivemode)cannotkeepupwiththeserialclockrate,thereisawaitfunctionthatautomaticallystopstheserialclockandholdsthenextshiftoperationuntiltheread/writeprocessingiscompleted.
Note:1Kbit=1024bit(fc=16MHz,fs=32.
768kHz)Figure11-3AutomaticWaitFunction(at4-bittransmitmode)11.
3.
1.
2ExternalclockAnexternalclockconnectedtotheSCKpinisusedastheserialclock.
Inthiscase,outputlatchofthisportshouldbesetto"1".
Toensureshifting,apulsewidthofatleast4machinecyclesisrequired.
Thispulseisneededfortheshiftoperationtoexecutecertainly.
Actually,thereisnecessaryprocessingtimeforinterrupting,writing,andreading.
Theminimumpulseisdeterminedbysettingthemodeandthepro-gram.
Therfore,maximumtransferfrequencywillbe488.
3Kbit/sec(atfc=16MHz).
Figure11-4ExternalclockpulsewidthTable11-1SerialClockRateNORMAL1/2,IDLE1/2modeSLOW1/2,SLEEP1/2modeDV7CK=0DV7CK=1SCKClockBaudRateClockBaudRateClockBaudRate000fc/2131.
91Kbpsfs/251024bpsfs/251024bps001fc/2861.
04Kbpsfc/2861.
04Kbps--010fc/27122.
07Kbpsfc/27122.
07Kbps--011fc/26244.
14Kbpsfc/26244.
14Kbps--100fc/25488.
28Kbpsfc/25488.
28Kbps--101fc/24976.
56Kbpsfc/24976.
56Kbps--110111ExternalExternalExternalExternalExternalExternala1a2b0b1b2b3c0c1a3acba0pin(output)pin(output)WrittentransmitdataAutomaticallywaitfunctionSCKSOtSCKLtSCKHtcyc=4/fc(IntheNORMAL1/2,IDLE1/2modes)4/fs(IntheSLOW1/2,SLEEP1/2modes)tSCKL,tSCKH>4tcycSCKpin(Output)Page155TMP86CS28FG11.
3.
2ShiftedgeTheleadingedgeisusedtotransmit,andthetrailingedgeisusedtoreceive.
11.
3.
2.
1LeadingedgeTransmitteddataareshiftedontheleadingedgeoftheserialclock(fallingedgeoftheSCKpininput/output).
11.
3.
2.
2TrailingedgeReceiveddataareshiftedonthetrailingedgeoftheserialclock(risingedgeoftheSCKpininput/out-put).
Figure11-5Shiftedge11.
4NumberofbitstotransferEither4-bitor8-bitserialtransfercanbeselected.
When4-bitserialtransferisselected,onlythelower4bitsofthetransmit/receivedatabufferregisterareused.
Theupper4bitsareclearedto"0"whenreceiving.
Thedataistransferredinsequencestartingattheleastsignificantbit(LSB).
11.
5NumberofwordstotransferUpto8wordsconsistingof4bitsofdata(4-bitserialtransfer)or8bits(8-bitserialtransfer)ofdatacanbetrans-ferredcontinuously.
ThenumberofwordstobetransferredcanbeselectedbySIOCR2.
AnINTSIOinterruptisgeneratedwhenthespecifiednumberofwordshasbeentransferred.
Ifthenumberofwordsistobechangedduringtransfer,theserialinterfacemustbestoppedbeforemakingthechange.
Thenumberofwordscanbechangedduringautomatic-waitoperationofaninternalclock.
Inthiscase,theserialinterfaceisnotrequiredtobestopped.
Bit1Bit2Bit3*3213210**32***3Bit0ShiftregisterShiftregisterBit1Bit0Bit2Bit30*******210*10**3210(a)Leadingedge(b)Trailingedge*;Don'tcareSOpinSIpinSCKpinSCKpinPage15611.
SynchronousSerialInterface(SIO)11.
6TransferModeTMP86CS28FGFigure11-6Numberofwordstotransfer(Example:1word=4bit)11.
6TransferModeSIOCR1isusedtoselectthetransmit,receive,ortransmit/receivemode.
11.
6.
14-bitand8-bittransfermodesInthesemodes,firstlysettheSIOcontrolregistertothetransmitmode,andthenwritefirsttransmitdata(numberoftransferwordstobetransferred)tothedatabufferregisters(DBR).
Afterthedataarewritten,thetransmissionisstartedbysettingSIOCR1to"1".
ThedataarethenoutputsequentiallytotheSOpininsynchronouswiththeserialclock,startingwiththeleastsignificantbit(LSB).
AssoonastheLSBhasbeenoutput,thedataaretransferredfromthedatabufferregistertotheshiftregister.
Whenthefinaldatabithasbeentransferredandthedatabufferregisterisempty,anINTSIO(Bufferempty)interruptisgeneratedtorequestthenexttransmitteddata.
Whentheinternalclockisused,theserialclockwillstopandanautomatic-waitwillbeinitiatedifthenexttransmitteddataarenotloadedtothedatabufferregisterbythetimethenumberofdatawordsspecifiedwiththeSIOCR2hasbeentransmitted.
Writingevenonewordofdatacancelstheautomatic-wait;therefore,whentransmittingtwoormorewords,alwayswritethenextwordbeforetransmissionofthepreviouswordiscompleted.
Note:AutomaticwaitsarealsocanceledbywritingtoaDBRnotbeingusedasatransmitdatabufferregister;there-fore,duringSIOdonotusesuchDBRforotherapplications.
Forexample,when3wordsaretransmitted,donotusetheDBRoftheremained5words.
Whenanexternalclockisused,thedatamustbewrittentothedatabufferregisterbeforeshiftingnextdata.
Thus,thetransferspeedisdeterminedbythemaximumdelaytimefromthegenerationoftheinterruptrequesttowritingofthedatatothedatabufferregisterbytheinterruptserviceprogram.
ThetransmissionisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inbufferemptyinterruptserviceprogram.
a1a2a3a0a1a2a3b0b1b2b3c0c1c2c3a0a1a0a2a3b0b1b2b3c0c1c2c3(a)1wordtransmit(b)3wordstransmit(c)3wordsreceiveSOpinINTSIOinterruptINTSIOinterruptINTSIOinterruptSOpinSIpinSCKpinSCKpinSCKpinPage157TMP86CS28FGSIOCR1iscleared,theoperationwillendafterallbitsofwordsaretransmitted.
ThatthetransmissionhasendedcanbedeterminedfromthestatusofSIOSRbecauseSIOSRisclearedto"0"whenatransferiscompleted.
WhenSIOCR1isset,thetransmissionisimmediatelyendedandSIOSRisclearedto"0".
Whenanexternalclockisused,itisalsonecessarytoclearSIOCR1to"0"beforeshiftingthenextdata;IfSIOCR1isnotclearedbeforeshiftout,dummydatawillbetransmittedandtheoperationwillend.
Ifitisnecessarytochangethenumberofwords,SIOCR1shouldbeclearedto"0",thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Figure11-7TransferMode(Example:8bit,1wordtransfer,Internalclock)Figure11-8TransferMode(Example:8bit,1wordtransfer,Externalclock)a1a2a3a4a5a6a7b0b1b2b3b4b5b6b7a0DBRbaClearSIOSWrite(a)Write(b)SCKpin(Output)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRSIOSRa1a2a3a4a5a6a7b0b1b2b3b4b5b6b7a0DBRbaClearSIOSWrite(a)Write(b)SCKpin(Input)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRPage15811.
SynchronousSerialInterface(SIO)11.
6TransferModeTMP86CS28FGFigure11-9TransmiiiedDataHoldTimeatEndofTransfer11.
6.
24-bitand8-bitreceivemodesAftersettingthecontrolregisterstothereceivemode,setSIOCR1to"1"toenablereceiving.
ThedataarethentransferredtotheshiftregisterviatheSIpininsynchronouswiththeserialclock.
Whenonewordofdatahasbeenreceived,itistransferredfromtheshiftregistertothedatabufferregister(DBR).
WhenthenumberofwordsspecifiedwiththeSIOCR2hasbeenreceived,anINTSIO(Bufferfull)interruptisgeneratedtorequestthatthesedatabereadout.
Thedataarethenreadfromthedatabufferregistersbytheinterruptserviceprogram.
Whentheinternalclockisused,andthepreviousdataarenotreadfromthedatabufferregisterbeforethenextdataarereceived,theserialclockwillstopandanautomatic-waitwillbeinitiateduntilthedataareread.
Awaitwillnotbeinitiatedifevenonedatawordhasbeenread.
Note:WaitsarealsocanceledbyreadingaDBRnotbeingusedasareceiveddatabufferregisterisread;therefore,duringSIOdonotusesuchDBRforotherapplications.
Whenanexternalclockisused,theshiftoperationissynchronizedwiththeexternalclock;therefore,thepreviousdataarereadbeforethenextdataaretransferredtothedatabufferregister.
Ifthepreviousdatahavenotbeenread,thenextdatawillnotbetransferredtothedatabufferregisterandthereceivingofanymoredatawillbecanceled.
Whenanexternalclockisused,themaximumtransferspeedisdeterminedbythedelaybetweenthetimewhentheinterruptrequestisgeneratedandwhenthedatareceivedhavebeenread.
ThereceivingisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inbufferfullinterruptserviceprogram.
WhenSIOCR1iscleared,thecurrentdataaretransferredtothebuffer.
AfterSIOCR1cleared,thereceivingisendedatthetimethatthefinalbitofthedatahasbeenreceived.
ThatthereceivinghasendedcanbedeterminedfromthestatusofSIOSR.
SIOSRisclearedto"0"whenthereceiv-ingisended.
Afterconfirmedthereceivingtermination,thefinalreceivingdataisread.
WhenSIOCR1isset,thereceivingisimmediatelyendedandSIOSRisclearedto"0".
(Thereceiveddataisignored,anditisnotrequiredtobereadout.
)Ifitisnecessarytochangethenumberofwordsinexternalclockoperation,SIOCR1shouldbeclearedto"0"thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Ifitisnecessarytochangethenumberofwordsininternalclock,duringautomatic-waitoperationwhichoccursaftercompletionofdatareceiving,SIOCR2mustberewrittenbeforethereceiveddataisreadout.
Note:Thebuffercontentsarelostwhenthetransfermodeisswitched.
Ifitshouldbecomenecessarytoswitchthetransfermode,endreceivingbyclearingSIOCR1to"0",readthelastdataandthenswitchthetrans-fermode.
MSBoflastwordtSODH=min3.
5/fc[s](IntheNORMAL1/2,IDLE1/2modes)tSODH=min3.
5/fs[s](IntheSLOW1/2,SLEEP1/2modes)SCKpinSOpinSIOSRPage159TMP86CS28FGFigure11-10ReceiveMode(Example:8bit,1wordtransfer,Internalclock)11.
6.
38-bittransfer/receivemodeAftersettingtheSIOcontrolregistertothe8-bittransmit/receivemode,writethedatatobetransmittedfirsttothedatabufferregisters(DBR).
Afterthat,enablethetransmit/receivebysettingSIOCR1to"1".
Whentransmitting,thedataareoutputfromtheSOpinatleadingedgesoftheserialclock.
Whenreceiving,thedataareinputtotheSIpinatthetrailingedgesoftheserialclock.
Whentheallreceiveisenabled,8-bitdataaretransferredfromtheshiftregistertothedatabufferregister.
AnINTSIOinterruptisgeneratedwhenthenumberofdatawordsspecifiedwiththeSIOCR2hasbeentransferred.
Usually,readthereceivedatafromthebufferregisterintheinterruptservice.
Thedatabufferregisterisusedforbothtransmittingandreceiving;therefore,alwayswritethedatatobetransmittedafterreadingtheallreceiveddata.
Whentheinternalclockisused,awaitisinitiateduntilthereceiveddataarereadandthenexttransferdataarewritten.
Awaitwillnotbeinitiatedifevenonetransferdatawordhasbeenwritten.
Whenanexternalclockisused,theshiftoperationissynchronizedwiththeexternalclock;therefore,itisnecessarytoreadthereceiveddataandwritethedatatobetransmittednextbeforestartingthenextshiftoper-ation.
Whenanexternalclockisused,thetransferspeedisdeterminedbythemaximumdelaybetweengenera-tionofaninterruptrequestandthereceiveddataarereadandthedatatobetransmittednextarewritten.
Thetransmit/receiveoperationisendedbyclearingSIOCR1to"0"orsettingSIOCR1to"1"inINTSIOinterruptserviceprogram.
WhenSIOCR1iscleared,thecurrentdataaretransferredtothebuffer.
AfterSIOCR1cleared,thetransmitting/receivingisendedatthetimethatthefinalbitofthedatahasbeentransmitted.
Thatthetransmitting/receivinghasendedcanbedeterminedfromthestatusofSIOSR.
SIOSRisclearedto"0"whenthetransmitting/receivingisended.
WhenSIOCR1isset,thetransmit/receiveoperationisimmediatelyendedandSIOSRisclearedto"0".
Ifitisnecessarytochangethenumberofwordsinexternalclockoperation,SIOCR1shouldbeclearedto"0",thenSIOCR2mustberewrittenafterconfirmingthatSIOSRhasbeenclearedto"0".
Ifitisnecessarytochangethenumberofwordsininternalclock,duringautomatic-waitoperationwhichoccursaftercompletionoftransmit/receiveoperation,SIOCR2mustberewrittenbeforereadingandwritingofthereceive/transmitdata.
a1a0a2a3a4a5a6a7b0b1b2b3b4b5b6b7DBRbaClearSIOSReadoutReadoutSCKpin(Output)SIpinINTSIOInterruptSIOCR1SIOSRSIOSRPage16011.
SynchronousSerialInterface(SIO)11.
6TransferModeTMP86CS28FGNote:Thebuffercontentsarelostwhenthetransfermodeisswitched.
Ifitshouldbecomenecessarytoswitchthetransfermode,endreceivingbyclearingSIOCR1to"0",readthelastdataandthenswitchthetrans-fermode.
Figure11-11Transfer/ReceiveMode(Example:8bit,1wordtransfer,Internalclock)Figure11-12TransmittedDataHoldTimeatEndofTransfer/Receivea1a0a2a3a4a5a6a7b0b1b2b3b4b5b6b7c1c0c2c3c4c5cbc6c7d0d1d2d3d4d5d6d7ClearSIOSDBRdaReadout(c)Write(a)Readout(d)Write(b)SCKpin(output)SOpinINTSIOinterruptSIOCR1SIOSRSIOSRSIpinBit7oflastwordBit6tSODH=min4/fc[s](IntheNORMAL1/2,IDLE1/2modes)tSODH=min4/fs[s](IntheSLOW1/2,SLEEP1/2modes)SCKpinSOpinSIOSRPage161TMP86CS28FG12.
AsynchronousSerialinterface(UART1)12.
1ConfigurationFigure12-1UART1(AsynchronousSerialInterface)CounterYABCSSABCDYEFGHUARTstatusregisterUARTcontrolregister2UARTcontrolregister1TransmitdatabufferReceivedatabufferfc/13fc/26fc/52fc/104fc/208fc/416fc/96StopbitParitybitfc/26fc/27fc/28BaudrategeneratorTransmit/receiveclock243222NoiserejectioncircuitMPXTransmitcontrolcircuitShiftregisterShiftregisterReceivecontrolcircuitMPX:MultiplexerUART1CR1TD1BUFRD1BUFINTTXD1INTRXD1UART1SRUART1CR2RXD1TXD1INTTC5Page16212.
AsynchronousSerialinterface(UART1)12.
2ControlTMP86CS28FG12.
2ControlUART1iscontrolledbytheUART1ControlRegisters(UART1CR1,UART1CR2).
TheoperatingstatuscanbemonitoredusingtheUARTstatusregister(UART1SR).
Note1:WhenoperationsaredisabledbysettingTXEandRXEbitto"0",thesettingbecomesvalidwhendatatransmitorreceivecomplete.
Whenthetransmitdataisstoredinthetransmitdatabuffer,thedataarenottransmitted.
Evenifdatatransmitisenabled,untilnewdataarewrittentothetransmitdatabuffer,thecurrentdataarenottransmitted.
Note2:Thetransmitclockandtheparityarecommontotransmitandreceive.
Note3:UART1CR1andUART1CR1shouldbesetto"0"beforeUART1CR1ischanged.
Note:WhenUART1CR2="01",pulseslongerthan96/fc[s]arealwaysregardedassignals;whenUART1CR2="10",longerthan192/fc[s];andwhenUART1CR2="11",longerthan384/fc[s].
UART1ControlRegister1UART1CR1(0FE8H)76543210TXERXESTBTEVENPEBRG(Initialvalue:00000000)TXETransferoperation0:1:DisableEnableWriteonlyRXEReceiveoperation0:1:DisableEnableSTBTTransmitstopbitlength0:1:1bit2bitsEVENEven-numberedparity0:1:Odd-numberedparityEven-numberedparityPEParityaddition0:1:NoparityParityBRGTransmitclockselect000:001:010:011:100:101:110:111:fc/13[Hz]fc/26fc/52fc/104fc/208fc/416TC5(InputINTTC5)fc/96UART1ControlRegister2UART1CR2(0FE9H)76543210RXDNCSTOPBR(Initialvalue:*****000)RXDNCSelectionofRXDinputnoiserejectiontime00:01:10:11:Nonoiserejection(Hysteresisinput)Rejectspulsesshorterthan31/fc[s]asnoiseRejectspulsesshorterthan63/fc[s]asnoiseRejectspulsesshorterthan127/fc[s]asnoiseWriteonlySTOPBRReceivestopbitlength0:1:1bit2bitsPage163TMP86CS28FGNote:WhenanINTTXDisgenerated,TBEPflagissetto"1"automatically.
UART1StatusRegisterUART1SR(0FE8H)76543210PERRFERROERRRBFLTENDTBEP(Initialvalue:000011**)PERRParityerrorflag0:1:NoparityerrorParityerrorReadonlyFERRFramingerrorflag0:1:NoframingerrorFramingerrorOERROverrunerrorflag0:1:NooverrunerrorOverrunerrorRBFLReceivedatabufferfullflag0:1:ReceivedatabufferemptyReceivedatabufferfullTENDTransmitendflag0:1:OntransmittingTransmitendTBEPTransmitdatabufferemptyflag0:1:Transmitdatabufferfull(Transmitdatawritingisfinished)TransmitdatabufferemptyUART1ReceiveDataBufferRD1BUF(0FEAH)76543210Readonly(Initialvalue:00000000)UART1TransmitDataBufferTD1BUF(0FEAH)76543210Writeonly(Initialvalue:00000000)Page16412.
AsynchronousSerialinterface(UART1)12.
3TransferDataFormatTMP86CS28FG12.
3TransferDataFormatInUART1,anone-bitstartbit(Lowlevel),stopbit(Bitlengthselectableathighlevel,byUART1CR1),andparity(SelectparityinUART1CR1;even-orodd-numberedparitybyUART1CR1)areaddedtothetransferdata.
Thetransferdataformatsareshownasfollows.
Figure12-2TransferDataFormatFigure12-3CautiononChangingTransferDataFormatNote:Inordertoswitchthetransferdataformat,performtransmitoperationsintheaboveFigure12-3sequenceexceptfortheinitialsetting.
StartBit0Bit1Bit6Bit7Stop1StartBit0Bit1Bit6Bit7Stop1Stop2StartBit0Bit1Bit6Bit7ParityStop1StartBit0Bit1Bit6Bit7ParityStop1Stop2PE0011STBTFrameLength011238910111201Withoutparity/1STOPbitWithparity/1STOPbitWithoutparity/2STOPbitWithparity/2STOPbitPage165TMP86CS28FG12.
4TransferRateThebaudrateofUART1issetofUART1CR1.
Theexampleofthebaudrateareshownasfollows.
WhenTC5isusedastheUART1transferrate(whenUART1CR1="110"),thetransferclockandtransferratearedeterminedasfollows:Transferclock[Hz]=TC5sourceclock[Hz]/TTREG5settingvalueTransferRate[baud]=Transferclock[Hz]/1612.
5DataSamplingMethodTheUART1receiverkeepssamplinginputusingtheclockselectedbyUART1CR1untilastartbitisdetectedinRXD1pininput.
RTclockstartsdetecting"L"leveloftheRXD1pin.
Onceastartbitisdetected,thestartbit,databits,stopbit(s),andparitybitaresampledatthreetimesofRT7,RT8,andRT9duringonereceiverclockinterval(RTclock).
(RT0isthepositionwherethebitsupposedlystarts.
)Bitisdeterminedaccordingtomajor-ityrule(Thedataarethesametwiceormoreoutofthreesamplings).
Figure12-4DataSamplingMethodTable12-1TransferRate(Example)BRGSourceClock16MHz8MHz4MHz00076800[baud]38400[baud]19200[baud]00138400192009600010192009600480001196004800240010048002400120010124001200600RT012345678910111213141501234567891011Bit0StartbitBit0Startbit(a)WithoutnoiserejectioncircuitRTclockInternalreceivedataRT012345678910111213141501234567891011Bit0StartbitBit0StartbitRTclockInternalreceivedata(b)WithnoiserejectioncircuitRXD1pinRXD1pinPage16612.
AsynchronousSerialinterface(UART1)12.
6STOPBitLengthTMP86CS28FG12.
6STOPBitLengthSelectatransmitstopbitlength(1bitor2bits)byUART1CR1.
12.
7ParitySetparity/noparitybyUART1CR1andsetparitytype(Odd-orEven-numbered)byUART1CR1.
12.
8Transmit/ReceiveOperation12.
8.
1DataTransmitOperationSetUART1CR1to"1".
ReadUART1SRtocheckUART1SR="1",thenwritedatainTD1BUF(Transmitdatabuffer).
WritingdatainTD1BUFzero-clearsUART1SR,transfersthedatatothetransmitshiftregisterandthedataaresequentiallyoutputfromtheTXD1pin.
Thedataoutputincludeaone-bitstartbit,stopbitswhosenumberisspecifiedinUART1CR1andaparitybitifparityadditionisspecified.
SelectthedatatransferbaudrateusingUART1CR1.
Whendatatransmitstarts,transmitbufferemptyflagUART1SRissetto"1"andanINTTXD1interruptisgenerated.
WhileUART1CR1="0"andfromwhen"1"iswrittentoUART1CR1towhensenddataarewrittentoTD1BUF,theTXD1pinisfixedathighlevel.
Whentransmittingdata,firstreadUART1SR,thenwritedatainTD1BUF.
Otherwise,UART1SRisnotzero-clearedandtransmitdoesnotstart.
12.
8.
2DataReceiveOperationSetUART1CR1to"1".
WhendataarereceivedviatheRXD1pin,thereceivedataaretransferredtoRD1BUF(Receivedatabuffer).
Atthistime,thedatatransmittedincludesastartbitandstopbit(s)andaparitybitifparityadditionisspecified.
Whenstopbit(s)arereceived,dataonlyareextractedandtransferredtoRD1BUF(Receivedatabuffer).
ThenthereceivebufferfullflagUART1SRissetandanINTRXD1interruptisgenerated.
SelectthedatatransferbaudrateusingUART1CR1.
Ifanoverrunerror(OERR)occurswhendataarereceived,thedataarenottransferredtoRD1BUF(Receivedatabuffer)butdiscarded;dataintheRD1BUFarenotaffected.
Note:WhenareceiveoperationisdisabledbysettingUART1CR1bitto"0",thesettingbecomesvalidwhendatareceiveiscompleted.
However,ifaframingerroroccursindatareceive,thereceive-disablingsettingmaynotbecomevalid.
Ifaframingerroroccurs,besuretoperformare-receiveoperation.
Page167TMP86CS28FG12.
9StatusFlag12.
9.
1ParityErrorWhenparitydeterminedusingthereceivedatabitsdiffersfromthereceivedparitybit,theparityerrorflagUART1SRissetto"1".
TheUART1SRisclearedto"0"whentheRD1BUFisreadafterreadingtheUART1SR.
Figure12-5GenerationofParityError12.
9.
2FramingErrorWhen"0"issampledasthestopbitinthereceivedata,framingerrorflagUART1SRissetto"1".
TheUART1SRisclearedto"0"whentheRD1BUFisreadafterreadingtheUART1SR.
Figure12-6GenerationofFramingError12.
9.
3OverrunErrorWhenallbitsinthenextdataarereceivedwhileunreaddataarestillinRD1BUF,overrunerrorflagUART1SRissetto"1".
Inthiscase,thereceivedataisdiscarded;datainRD1BUFarenotaffected.
TheUART1SRisclearedto"0"whentheRD1BUFisreadafterreadingtheUART1SR.
ParityStopShiftregisterpxxxx0*1pxxxx0xxxx0**RXD1pinUART1SRINTRXD1interruptAfterreadingUART1SRthenRD1BUFclearsPERR.
FinalbitStopShiftregisterxxxx0*0xxxx0xxx0**RXD1pinUART1SRINTRXD1interruptAfterreadingUART1SRthenRD1BUFclearsFERR.
Page16812.
AsynchronousSerialinterface(UART1)12.
9StatusFlagTMP86CS28FGFigure12-7GenerationofOverrunErrorNote:ReceiveoperationsaredisableduntiltheoverrunerrorflagUART1SRiscleared.
12.
9.
4ReceiveDataBufferFullLoadingthereceiveddatainRD1BUFsetsreceivedatabufferfullflagUART1SRto"1".
TheUART1SRisclearedto"0"whentheRD1BUFisreadafterreadingtheUART1SR.
Figure12-8GenerationofReceiveDataBufferFullNote:IftheoverrunerrorflagUART1SRissetduringtheperiodbetweenreadingtheUART1SRandread-ingtheRD1BUF,itcannotbeclearedbyonlyreadingtheRD1BUF.
Therefore,afterreadingtheRD1BUF,readtheUART1SRagaintocheckwhetherornottheoverrunerrorflagwhichshouldhavebeenclearedstillremainsset.
12.
9.
5TransmitDataBufferEmptyWhennodataisinthetransmitbufferTD1BUF,thatis,whendatainTD1BUFaretransferredtothetransmitshiftregisteranddatatransmitstarts,transmitdatabufferemptyflagUART1SRissetto"1".
TheUART1SRisclearedto"0"whentheTD1BUFiswrittenafterreadingtheUART1SR.
FinalbitStopShiftregisterxxxx0*1xxxx0yyyyxxx0**RXD1pinUART1SRINTRXD1interruptAfterreadingUART1SRthenRD1BUFclearsOERR.
RD1BUFUART1SRFinalbitStopShiftregisterxxxx0*1xxxx0xxxxyyyyxxx0**RXD1pinUART1SRINTRXD1interruptRD1BUFAfterreadingUART1SRthenRD1BUFclearsRBFL.
Page169TMP86CS28FGFigure12-9GenerationofTransmitDataBufferEmpty12.
9.
6TransmitEndFlagWhendataaretransmittedandnodataisinTD1BUF(UART1SR="1"),transmitendflagUART1SRissetto"1".
TheUART1SRisclearedto"0"whenthedatatransmitisstartedafterwritingtheTD1BUF.
Figure12-10GenerationofTransmitEndFlagandTransmitDataBufferEmptyShiftregisterDatawriteDatawritezzzzxxxxyyyyStartBit0FinalbitStop1xxxx0*****1*1xxxx****1x*****11yyyy0TD1BUFTXD1pinUART1SRINTTXD1interruptAfterreadingUART1SRwritingTD1BUFclearsTBEP.
Shiftregister*1yyyy***1xx****1x*****1StopStart1yyyy0Bit0TXD1pinUART1SRUART1SRINTTXD1interruptDatawriteforTD1BUFPage17012.
AsynchronousSerialinterface(UART1)12.
9StatusFlagTMP86CS28FGPage171TMP86CS28FG13.
AsynchronousSerialinterface(UART0)13.
1ConfigurationFigure13-1UART0(AsynchronousSerialInterface)CounterYABCSSABCDYEFGHUARTstatusregisterUARTcontrolregister2UARTcontrolregister1TransmitdatabufferReceivedatabufferfc/13fc/26fc/52fc/104fc/208fc/416fc/96StopbitParitybitfc/26fc/27fc/28BaudrategeneratorTransmit/receiveclock243222NoiserejectioncircuitMPXTransmitcontrolcircuitShiftregisterShiftregisterReceivecontrolcircuitMPX:MultiplexerUART0CR1TD0BUFRD0BUFINTTXD0INTRXD0UART0SRUART0CR2RXD0TXD0INTTC3Page17213.
AsynchronousSerialinterface(UART0)13.
2ControlTMP86CS28FG13.
2ControlUART0iscontrolledbytheUART0ControlRegisters(UART0CR1,UART0CR2).
TheoperatingstatuscanbemonitoredusingtheUARTstatusregister(UART0SR).
Note1:WhenoperationsaredisabledbysettingTXEandRXEbitto"0",thesettingbecomesvalidwhendatatransmitorreceivecomplete.
Whenthetransmitdataisstoredinthetransmitdatabuffer,thedataarenottransmitted.
Evenifdatatransmitisenabled,untilnewdataarewrittentothetransmitdatabuffer,thecurrentdataarenottransmitted.
Note2:Thetransmitclockandtheparityarecommontotransmitandreceive.
Note3:UART0CR1andUART0CR1shouldbesetto"0"beforeUART0CR1ischanged.
Note:WhenUART0CR2="01",pulseslongerthan96/fc[s]arealwaysregardedassignals;whenUART0CR2="10",longerthan192/fc[s];andwhenUART0CR2="11",longerthan384/fc[s].
UART0ControlRegister1UART0CR1(0FE5H)76543210TXERXESTBTEVENPEBRG(Initialvalue:00000000)TXETransferoperation0:1:DisableEnableWriteonlyRXEReceiveoperation0:1:DisableEnableSTBTTransmitstopbitlength0:1:1bit2bitsEVENEven-numberedparity0:1:Odd-numberedparityEven-numberedparityPEParityaddition0:1:NoparityParityBRGTransmitclockselect000:001:010:011:100:101:110:111:fc/13[Hz]fc/26fc/52fc/104fc/208fc/416TC3(InputINTTC3)fc/96UART0ControlRegister2UART0CR2(0FE6H)76543210RXDNCSTOPBR(Initialvalue:*****000)RXDNCSelectionofRXDinputnoiserejectiontime00:01:10:11:Nonoiserejection(Hysteresisinput)Rejectspulsesshorterthan31/fc[s]asnoiseRejectspulsesshorterthan63/fc[s]asnoiseRejectspulsesshorterthan127/fc[s]asnoiseWriteonlySTOPBRReceivestopbitlength0:1:1bit2bitsPage173TMP86CS28FGNote:WhenanINTTXDisgenerated,TBEPflagissetto"1"automatically.
UART0StatusRegisterUART0SR(0FE5H)76543210PERRFERROERRRBFLTENDTBEP(Initialvalue:000011**)PERRParityerrorflag0:1:NoparityerrorParityerrorReadonlyFERRFramingerrorflag0:1:NoframingerrorFramingerrorOERROverrunerrorflag0:1:NooverrunerrorOverrunerrorRBFLReceivedatabufferfullflag0:1:ReceivedatabufferemptyReceivedatabufferfullTENDTransmitendflag0:1:OntransmittingTransmitendTBEPTransmitdatabufferemptyflag0:1:Transmitdatabufferfull(Transmitdatawritingisfinished)TransmitdatabufferemptyUART0ReceiveDataBufferRD0BUF(0FE7H)76543210Readonly(Initialvalue:00000000)UART0TransmitDataBufferTD0BUF(0FE7H)76543210Writeonly(Initialvalue:00000000)Page17413.
AsynchronousSerialinterface(UART0)13.
3TransferDataFormatTMP86CS28FG13.
3TransferDataFormatInUART0,anone-bitstartbit(Lowlevel),stopbit(Bitlengthselectableathighlevel,byUART0CR1),andparity(SelectparityinUART0CR1;even-orodd-numberedparitybyUART0CR1)areaddedtothetransferdata.
Thetransferdataformatsareshownasfollows.
Figure13-2TransferDataFormatFigure13-3CautiononChangingTransferDataFormatNote:Inordertoswitchthetransferdataformat,performtransmitoperationsintheaboveFigure13-3sequenceexceptfortheinitialsetting.
StartBit0Bit1Bit6Bit7Stop1StartBit0Bit1Bit6Bit7Stop1Stop2StartBit0Bit1Bit6Bit7ParityStop1StartBit0Bit1Bit6Bit7ParityStop1Stop2PE0011STBTFrameLength011238910111201Withoutparity/1STOPbitWithparity/1STOPbitWithoutparity/2STOPbitWithparity/2STOPbitPage175TMP86CS28FG13.
4TransferRateThebaudrateofUART0issetofUART0CR1.
Theexampleofthebaudrateareshownasfollows.
WhenTC3isusedastheUART0transferrate(whenUART0CR1="110"),thetransferclockandtransferratearedeterminedasfollows:Transferclock[Hz]=TC3sourceclock[Hz]/TTREG3settingvalueTransferRate[baud]=Transferclock[Hz]/1613.
5DataSamplingMethodTheUART0receiverkeepssamplinginputusingtheclockselectedbyUART0CR1untilastartbitisdetectedinRXD0pininput.
RTclockstartsdetecting"L"leveloftheRXD0pin.
Onceastartbitisdetected,thestartbit,databits,stopbit(s),andparitybitaresampledatthreetimesofRT7,RT8,andRT9duringonereceiverclockinterval(RTclock).
(RT0isthepositionwherethebitsupposedlystarts.
)Bitisdeterminedaccordingtomajor-ityrule(Thedataarethesametwiceormoreoutofthreesamplings).
Figure13-4DataSamplingMethodTable13-1TransferRate(Example)BRGSourceClock16MHz8MHz4MHz00076800[baud]38400[baud]19200[baud]00138400192009600010192009600480001196004800240010048002400120010124001200600RT012345678910111213141501234567891011Bit0StartbitBit0Startbit(a)WithoutnoiserejectioncircuitRTclockInternalreceivedataRT012345678910111213141501234567891011Bit0StartbitBit0StartbitRTclockInternalreceivedata(b)WithnoiserejectioncircuitRXD0pinRXD0pinPage17613.
AsynchronousSerialinterface(UART0)13.
6STOPBitLengthTMP86CS28FG13.
6STOPBitLengthSelectatransmitstopbitlength(1bitor2bits)byUART0CR1.
13.
7ParitySetparity/noparitybyUART0CR1andsetparitytype(Odd-orEven-numbered)byUART0CR1.
13.
8Transmit/ReceiveOperation13.
8.
1DataTransmitOperationSetUART0CR1to"1".
ReadUART0SRtocheckUART0SR="1",thenwritedatainTD0BUF(Transmitdatabuffer).
WritingdatainTD0BUFzero-clearsUART0SR,transfersthedatatothetransmitshiftregisterandthedataaresequentiallyoutputfromtheTXD0pin.
Thedataoutputincludeaone-bitstartbit,stopbitswhosenumberisspecifiedinUART0CR1andaparitybitifparityadditionisspecified.
SelectthedatatransferbaudrateusingUART0CR1.
Whendatatransmitstarts,transmitbufferemptyflagUART0SRissetto"1"andanINTTXD0interruptisgenerated.
WhileUART0CR1="0"andfromwhen"1"iswrittentoUART0CR1towhensenddataarewrittentoTD0BUF,theTXD0pinisfixedathighlevel.
Whentransmittingdata,firstreadUART0SR,thenwritedatainTD0BUF.
Otherwise,UART0SRisnotzero-clearedandtransmitdoesnotstart.
13.
8.
2DataReceiveOperationSetUART0CR1to"1".
WhendataarereceivedviatheRXD0pin,thereceivedataaretransferredtoRD0BUF(Receivedatabuffer).
Atthistime,thedatatransmittedincludesastartbitandstopbit(s)andaparitybitifparityadditionisspecified.
Whenstopbit(s)arereceived,dataonlyareextractedandtransferredtoRD0BUF(Receivedatabuffer).
ThenthereceivebufferfullflagUART0SRissetandanINTRXD0interruptisgenerated.
SelectthedatatransferbaudrateusingUART0CR1.
Ifanoverrunerror(OERR)occurswhendataarereceived,thedataarenottransferredtoRD0BUF(Receivedatabuffer)butdiscarded;dataintheRD0BUFarenotaffected.
Note:WhenareceiveoperationisdisabledbysettingUART0CR1bitto"0",thesettingbecomesvalidwhendatareceiveiscompleted.
However,ifaframingerroroccursindatareceive,thereceive-disablingsettingmaynotbecomevalid.
Ifaframingerroroccurs,besuretoperformare-receiveoperation.
Page177TMP86CS28FG13.
9StatusFlag13.
9.
1ParityErrorWhenparitydeterminedusingthereceivedatabitsdiffersfromthereceivedparitybit,theparityerrorflagUART0SRissetto"1".
TheUART0SRisclearedto"0"whentheRD0BUFisreadafterreadingtheUART0SR.
Figure13-5GenerationofParityError13.
9.
2FramingErrorWhen"0"issampledasthestopbitinthereceivedata,framingerrorflagUART0SRissetto"1".
TheUART0SRisclearedto"0"whentheRD0BUFisreadafterreadingtheUART0SR.
Figure13-6GenerationofFramingError13.
9.
3OverrunErrorWhenallbitsinthenextdataarereceivedwhileunreaddataarestillinRD0BUF,overrunerrorflagUART0SRissetto"1".
Inthiscase,thereceivedataisdiscarded;datainRD0BUFarenotaffected.
TheUART0SRisclearedto"0"whentheRD0BUFisreadafterreadingtheUART0SR.
ParityStopShiftregisterpxxxx0*1pxxxx0xxxx0**RXD0pinUART0SRINTRXD0interruptAfterreadingUART0SRthenRD0BUFclearsPERR.
FinalbitStopShiftregisterxxxx0*0xxxx0xxx0**RXD0pinUART0SRINTRXD0interruptAfterreadingUART0SRthenRD0BUFclearsFERR.
Page17813.
AsynchronousSerialinterface(UART0)13.
9StatusFlagTMP86CS28FGFigure13-7GenerationofOverrunErrorNote:ReceiveoperationsaredisableduntiltheoverrunerrorflagUART0SRiscleared.
13.
9.
4ReceiveDataBufferFullLoadingthereceiveddatainRD0BUFsetsreceivedatabufferfullflagUART0SRto"1".
TheUART0SRisclearedto"0"whentheRD0BUFisreadafterreadingtheUART0SR.
Figure13-8GenerationofReceiveDataBufferFullNote:IftheoverrunerrorflagUART0SRissetduringtheperiodbetweenreadingtheUART0SRandread-ingtheRD0BUF,itcannotbeclearedbyonlyreadingtheRD0BUF.
Therefore,afterreadingtheRD0BUF,readtheUART0SRagaintocheckwhetherornottheoverrunerrorflagwhichshouldhavebeenclearedstillremainsset.
13.
9.
5TransmitDataBufferEmptyWhennodataisinthetransmitbufferTD0BUF,thatis,whendatainTD0BUFaretransferredtothetransmitshiftregisteranddatatransmitstarts,transmitdatabufferemptyflagUART0SRissetto"1".
TheUART0SRisclearedto"0"whentheTD0BUFiswrittenafterreadingtheUART0SR.
FinalbitStopShiftregisterxxxx0*1xxxx0yyyyxxx0**RXD0pinUART0SRINTRXD0interruptAfterreadingUART0SRthenRD0BUFclearsOERR.
RD0BUFUART0SRFinalbitStopShiftregisterxxxx0*1xxxx0xxxxyyyyxxx0**RXD0pinUART0SRINTRXD0interruptRD0BUFAfterreadingUART0SRthenRD0BUFclearsRBFL.
Page179TMP86CS28FGFigure13-9GenerationofTransmitDataBufferEmpty13.
9.
6TransmitEndFlagWhendataaretransmittedandnodataisinTD0BUF(UART0SR="1"),transmitendflagUART0SRissetto"1".
TheUART0SRisclearedto"0"whenthedatatransmitisstartedafterwritingtheTD0BUF.
Figure13-10GenerationofTransmitEndFlagandTransmitDataBufferEmptyShiftregisterDatawriteDatawritezzzzxxxxyyyyStartBit0FinalbitStop1xxxx0*****1*1xxxx****1x*****11yyyy0TD0BUFTXD0pinUART0SRINTTXD0interruptAfterreadingUART0SRwritingTD0BUFclearsTBEP.
Shiftregister*1yyyy***1xx****1x*****1StopStart1yyyy0Bit0TXD0pinUART0SRUART0SRINTTXD0interruptDatawriteforTD0BUFPage18013.
AsynchronousSerialinterface(UART0)13.
9StatusFlagTMP86CS28FGPage181TMP86CS28FG14.
10-bitADConverter(ADC)TheTMP86CS28FGhavea10-bitsuccessiveapproximationtypeADconverter.
14.
1ConfigurationThecircuitconfigurationofthe10-bitADconverterisshowninFigure14-1.
ItconsistsofcontrolregisterADCCR1andADCCR2,convertedvalueregisterADCDR1andADCDR2,aDAconverter,asample-holdcircuit,acomparator,andasuccessivecomparisoncircuit.
Note:BeforeusingADconverter,setappropriatevaluetoI/Oportregisterconbiningaanaloginputport.
Fordetails,seethesec-tionon"I/Oports".
Figure14-110-bitADConverter24108AINDSADRSR/2R/2RACKAMDIREFONADconversionresultregister1,2ADconvertercontrolregister1,2ADBFEOCFINTADCSAINnSuccessiveapproximatecircuitADCCR2ADCDR1ADCDR2ADCCR1SampleholdcircuitASENShiftclockDAconverterAnaloginputmultiplexerYReferencevoltageAnalogcomparator23ControlcircuitAVSSVAREFAVDDAIN0AIN7Page18214.
10-bitADConverter(ADC)14.
2RegisterconfigurationTMP86CS28FG14.
2RegisterconfigurationTheADconverterconsistsofthefollowingfourregisters:1.
ADconvertercontrolregister1(ADCCR1)Thisregisterselectstheanalogchannelsandoperationmode(Softwarestartorrepeat)inwhichtoper-formADconversionandcontrolstheADconverterasitstartsoperating.
2.
ADconvertercontrolregister2(ADCCR2)ThisregisterselectstheADconversiontimeandcontrolstheconnectionoftheDAconverter(Ladderresistornetwork).
3.
ADconvertedvalueregister1(ADCDR1)ThisregisterusedtostorethedigitalvaluefterbeingconvertedbytheADconverter.
4.
ADconvertedvalueregister2(ADCDR2)ThisregistermonitorstheoperatingstatusoftheADconverter.
Note1:SelectanaloginputchannelduringADconverterstops(ADCDR2="0").
Note2:Whentheanaloginputchannelisallusedisabling,theADCCR1shouldbesetto"1".
Note3:Duringconversion,Donotperformportoutputinstructiontomaintainaprecisionforallofthepinsbecauseanaloginputportuseasgeneralinputport.
Andforportneartoanaloginput,Donotinputintensesignalingofchange.
Note4:TheADCCR1isautomaticallyclearedto"0"afterstartingconversion.
Note5:DonotsetADCCR1newlyagainduringADconversion.
BeforesettingADCCR1newlyagain,checkADCDR2toseethattheconversioniscompletedorwaituntiltheinterruptsignal(INTADC)isgenerated(e.
g.
,interrupthandlingroutine).
Note6:AfterSTOPorSLOW/SLEEPmodearestarted,ADconvertercontrolregister1(ADCCR1)isallinitializedandnodatacanbewritteninthisregister.
Therfore,touseADconverteragain,settheADCCR1newlyafterreturningtoNORMAL1orNORMAL2mode.
ADConverterControlRegister1ADCCR1(0FE2H)76543210ADRSAMDAINDSSAIN(Initialvalue:00010000)ADRSADconversionstart0:1:-ADconversionstartR/WAMDADoperatingmode00:01:10:11:ADoperationdisableSoftwarestartmodeReservedRepeatmodeAINDSAnaloginputcontrol0:1:AnaloginputenableAnaloginputdisableSAINAnaloginputchannelselect0000:0001:0010:0011:0100:0101:0110:0111:1000:1001:1010:1011:1100:1101:1110:1111:AIN0AIN1AIN2AIN3AIN4AIN5AIN6AIN7ReservedReservedReservedReservedReservedReservedReservedReservedPage183TMP86CS28FGNote1:Alwayssetbit0inADCCR2to"0"andsetbit4inADCCR2to"1".
Note2:WhenareadinstructionforADCCR2,bit6to7inADCCR2readinasundefineddata.
Note3:AfterSTOPorSLOW/SLEEPmodearestarted,ADconvertercontrolregister2(ADCCR2)isallinitializedandnodatacanbewritteninthisregister.
Therfore,touseADconverteragain,settheADCCR2newlyafterreturningtoNORMAL1orNORMAL2mode.
Note1:Settingfor""intheabovetableareinhibited.
fc:HighFrequencyoscillationclock[Hz]Note2:SetconversiontimesettingshouldbekeptmorethanthefollowingtimebyAnalogreferencevoltage(VAREF).
ADConverterControlRegister2ADCCR2(0FE3H)76543210IREFON"1"ACK"0"(Initialvalue:**0*000*)IREFONDAconverter(Ladderresistor)connectioncontrol0:1:ConnectedonlyduringADconversionAlwaysconnectedR/WACKADconversiontimeselect(Refertothefollowingtableaboutthecon-versiontime)000:001:010:011:100:101:110:111:39/fcReserved78/fc156/fc312/fc624/fc1248/fcReservedTable14-1ACKsettingandConversiontimeConditionConversiontime16MHz8MHz4MHz2MHz10MHz5MHz2.
5MHzACK00039/fc---19.
5s--15.
6s001Reserved01078/fc--19.
5s39.
0s-15.
6s31.
2s011156/fc-19.
5s39.
0s78.
0s15.
6s31.
2s62.
4s100312/fc19.
5s39.
0s78.
0s156.
0s31.
2s62.
4s124.
8s101624/fc39.
0s78.
0s156.
0s-62.
4s124.
8s-1101248/fc78.
0s156.
0s--124.
8s--111Reserved-VAREF=4.
5to5.
5V15.
6sandmore-VAREF=2.
7to5.
5V31.
2sandmoreADConvertedvalueRegister1ADCDR1(0FE1H)76543210AD09AD08AD07AD06AD05AD04AD03AD02(Initialvalue:00000000)ADConvertedvalueRegister2ADCDR2(0FE0H)76543210AD01AD00EOCFADBF(Initialvalue:0000****)Page18414.
10-bitADConverter(ADC)14.
2RegisterconfigurationTMP86CS28FGNote1:TheADCDR2isclearedto"0"whenreadingtheADCDR1.
Therfore,theADconversionresultshouldbereadtoADCDR2morefirstthanADCDR1.
Note2:TheADCDR2issetto"1"whenADconversionstarts,andclearedto"0"whenADconversionfinished.
ItalsoiscleareduponenteringSTOPmodeorSLOWmode.
Note3:IfareadinstructionisexecutedforADCDR2,readdataofbit3tobit0areunstable.
EOCFADconversionendflag0:1:BeforeorduringconversionConversioncompletedReadonlyADBFADconversionBUSYflag0:1:DuringstopofADconversionDuringADconversionPage185TMP86CS28FG14.
3Function14.
3.
1SoftwareStartModeAftersettingADCCR1to"01"(softwarestartmode),setADCCR1to"1".
ADconver-sionofthevoltageattheanaloginputpinspecifiedbyADCCR1istherebystarted.
AftercompletionoftheADconversion,theconversionresultisstoredinADconvertedvalueregisters(ADCDR1,ADCDR2)andatthesametimeADCDR2issetto1,theADconversionfinishedinter-rupt(INTADC)isgenerated.
ADRSisautomaticallyclearedafterADconversionhasstarted.
DonotsetADCCR1newlyagain(Restart)duringADconversion.
BeforesettingADRSnewlyagain,checkADCDR2toseethattheconversioniscompletedorwaituntiltheinterruptsignal(INTADC)isgenerated(e.
g.
,interrupthandlingrou-tine).
Figure14-2SoftwareStartMode14.
3.
2RepeatModeADconversionofthevoltageattheanaloginputpinspecifiedbyADCCR1isperformedrepeatedly.
Inthismode,ADconversionisstartedbysettingADCCR1to"1"aftersettingADCCR1to"11"(Repeatmode).
AftercompletionoftheADconversion,theconversionresultisstoredinADconvertedvalueregisters(ADCDR1,ADCDR2)andatthesametimeADCDR2issetto1,theADconversionfinishedinter-rupt(INTADC)isgenerated.
Inrepeatmode,eachtimeoneADconversioniscompleted,thenextADconversionisstarted.
TostopADconversion,setADCCR1to"00"(Disablemode)bywriting0s.
TheADconvertoperationisstoppedimmediately.
TheconvertedvalueatthistimeisnotstoredintheADconvertedvalueregister.
ADCDR1statusEOCFclearedbyreadingconversionresultConversionresultreadADCDR2INTADCinterruptrequestADCDR2ADCCR11stconversionresult2ndconversionresultIndeterminateADconversionstartADconversionstartADCDR1ADCDR2ConversionresultreadConversionresultreadConversionresultreadPage18614.
10-bitADConverter(ADC)14.
3FunctionTMP86CS28FGFigure14-3RepeatMode14.
3.
3RegisterSetting1.
SetuptheADconvertercontrolregister1(ADCCR1)asfollows:ChoosethechanneltoADconvertusingADinputchannelselect(SAIN).
Specifyanaloginputenableforanaloginputcontrol(AINDS).
SpecifyAMDfortheADconvertercontroloperationmode(softwareorrepeatmode).
2.
SetuptheADconvertercontrolregister2(ADCCR2)asfollows:SettheADconversiontimeusingADconversiontime(ACK).
Fordetailsonhowtosetthecon-versiontime,refertoFigure14-1andADconvertercontrolregister2.
ChooseIREFONforDAconvertercontrol.
3.
Aftersettingup(1)and(2)above,setADconversionstart(ADRS)ofADconvertercontrolregister1(ADCCR1)to"1".
Ifsoftwarestartmodehasbeenselected,ADconversionstartsimmediately.
4.
AfteranelapseofthespecifiedADconversiontime,theADconvertedvalueisstoredinADcon-vertedvalueregister1(ADCDR1)andtheADconversionfinishedflag(EOCF)ofADconvertedvalueregister2(ADCDR2)issetto"1",uponwhichtimeADconversioninterruptINTADCisgener-ated.
5.
EOCFisclearedto"0"byareadoftheconversionresult.
However,ifreconvertedbeforearegisterread,althoughEOCFisclearedthepreviousconversionresultisretaineduntilthenextconversioniscompleted.
ADCDR1,ADCDR2EOCFclearedbyreadingconversionresultConversionresultreadADCDR2INTADCinterruptrequestConversionoperationADCCR1IndeterminateADconversionstartADCCR1"11""00"1stconversionresultADconvertoperationsuspended.
Conversionresultisnotstored.
2ndconversionresult3rdconversionresultADCDR1ADCDR22ndconversionresult3rdconversionresult1stconversionresultConversionresultreadConversionresultreadConversionresultreadConversionresultreadConversionresultreadPage187TMP86CS28FG14.
4STOP/SLOWModesduringADConversionWhenstandbymode(STOPorSLOWmode)isenteredforciblyduringADconversion,theADconvertoperationissuspendedandtheADconverterisinitialized(ADCCR1andADCCR2areinitializedtoinitialvalue).
Also,theconversionresultisindeterminate.
(Conversionresultsuptothepreviousoperationarecleared,sobesuretoreadtheconversionresultsbeforeenteringstandbymode(STOPorSLOWmode).
)Whenrestoredfromstandbymode(STOPorSLOWmode),ADconversionisnotautomaticallyrestarted,soitisnecessarytorestartADconversion.
Notethatsincetheanalogreferencevoltageisautomaticallydisconnected,thereisnopossibilityofcurrentflowingintotheanalogreferencevoltage.
Example:Afterselectingtheconversiontime19.
5sat16MHzandtheanaloginputchannelAIN3pin,performADcon-versiononce.
AftercheckingEOCF,readtheconvertedvalue,storethelower2bitsinaddress0009EHndstoretheupper8bitsinaddress0009FHinRAM.
Theoperationmodeissoftwarestartmode.
:(portsetting):;SetportregisterapprorriatelybeforesettingADconverterregisters.
::(RefertosectionI/Oportindetails)LD(ADCCR1),00100011B;SelectAIN3LD(ADCCR2),11011000B;Selectconversiontime(312/fc)andoperationmodeSET(ADCCR1).
7;ADRS=1(ADconversionstart)SLOOP:TEST(ADCDR2).
5;EOCF=1JRST,SLOOPLDA,(ADCDR2);ReadresultdataLD(9EH),ALDA,(ADCDR1);ReadresultdataLD(9FH),APage18814.
10-bitADConverter(ADC)14.
5AnalogInputVoltageandADConversionResultTMP86CS28FG14.
5AnalogInputVoltageandADConversionResultTheanaloginputvoltageiscorrespondedtothe10-bitdigitalvalueconvertedbytheADasshowninFigure14-4.
Figure14-4AnalogInputVoltageandADConversionResult(Typ.
)1001H02H03H3FDH3FEH3FFH231021102210231024Analoginputvoltage1024ADconversionresultVAREFAVSSPage189TMP86CS28FG14.
6PrecautionsaboutADConverter14.
6.
1AnaloginputpinvoltagerangeMakesuretheanaloginputpins(AIN0toAIN7)areusedatvoltageswithinVAREFtoAVSS.
Ifanyvoltageoutsidethisrangeisappliedtooneoftheanaloginputpins,theconvertedvalueonthatpinbecomesuncertain.
Theotheranaloginputpinsalsoareaffectedbythat.
14.
6.
2AnaloginputsharedpinsTheanaloginputpins(AIN0toAIN7)aresharedwithinput/outputports.
WhenusinganyoftheanaloginputstoexecuteADconversion,donotexecuteinput/outputinstructionsforallotherports.
ThisisnecessarytopreventtheaccuracyofADconversionfromdegrading.
Notonlytheseanaloginputsharedpins,someotherpinsmayalsobeaffectedbynoisearisingfrominput/outputtoandfromadjacentpins.
14.
6.
3NoiseCountermeasureTheinternalequivalentcircuitoftheanaloginputpinsisshowninFigure14-5.
Thehighertheoutputimpedanceoftheanaloginputsource,moreeasilytheyaresusceptibletonoise.
Therefore,makesuretheout-putimpedanceofthesignalsourceinyourdesignis5korless.
Toshibaalsorecommendsattachingacapac-itorexternaltothechip.
Figure14-5AnalogInputEquivalentCircuitandExampleofInputPinProcessingDAconverterAINiAnalogcomparatorInternalresistancePermissiblesignalsourceimpedanceInternalcapacitance5k(typ)C=22pF(typ.
)5k(max)Note)i=7to0Page19014.
10-bitADConverter(ADC)14.
6PrecautionsaboutADConverterTMP86CS28FGPage191TMP86CS28FG15.
Key-onWakeup(KWU)IntheTMP86CS28FG,theSTOPmodeisreleasedbynotonlyP20(INT5/STOP)pinbutalsofour(STOP2toSTOP5)pins.
WhentheSTOPmodeisreleasedbySTOP2toSTOP5pins,theSTOPpinneedstobeused.
Indetails,refertothefollowingsection"15.
2Control".
15.
1ConfigurationFigure15-1Key-onWakeupCircuit15.
2ControlSTOP2toSTOP5pinscancontrolledbyKey-onWakeupControlRegister(STOPCR).
Itcanbeconfiguredasenable/disablein1-bitunit.
WhenthosepinsareusedforSTOPmoderelease,configurecorrespondingI/OpinstoinputmodebyI/Oportregisterbeforehand.
15.
3FunctionStopmodecanbeenteredbysettinguptheSystemControlRegister(SYSCR1),andcanbeexitedbydetectingthe"L"levelonSTOP2toSTOP5pins,whichareenabledbySTOPCR,forreleasingSTOPmode(Note1).
Key-onWakeupControlRegisterSTOPCR76543210(0031H)STOP5STOP4STOP3STOP2(Initialvalue:0000****)STOP5STOPmodereleasedbySTOP50:Disable1:EnableWriteonlySTOP4STOPmodereleasedbySTOP40:Disable1:EnableWriteonlySTOP3STOPmodereleasedbySTOP30:Disable1:EnableWriteonlySTOP2STOPmodereleasedbySTOP20:Disable1:EnableWriteonlySTOPCRINT5STOPSTOPmodereleasesignal(1:Release)(0031H)STOP2STOP3STOP4STOP5STOP2STOP3STOP4STOP5Page19215.
Key-onWakeup(KWU)15.
3FunctionTMP86CS28FGAlso,eachleveloftheSTOP2toSTOP5pinscanbeconfirmedbyreadingcorrespondingI/Oportdataregister,checkallSTOP2toSTOP5pins"H"thatisenabledbySTOPCRbeforetheSTOPmodeisstarted(Note2,3).
Note1:WhentheSTOPmodereleasedbytheedgereleasemode(SYSCR1="0"),inhibitinputfromSTOP2toSTOP5pinsbyKey-onWakeupControlRegister(STOPCR)ormustbeset"H"levelintoSTOP2toSTOP5pinsthatareavailableinputduringSTOPmode.
Note2:WhentheSTOPpininputishighorSTOP2toSTOP5pinsinputwhichisenabledbySTOPCRislow,executinganinstructionwhichstartsSTOPmodewillnotplaceinSTOPmodebutinsteadwillimmediatelystartthereleasesequence(Warmup).
Note3:TheinputcircuitofKey-onWakeupinputandPortinputisseparated,soeachinputvoltagethresholdvalueisdif-ferent.
Therefore,avaluecomesfromportinputbeforeSTOPmodestartmaybedifferentfromavaluewhichisdetectedbyKey-onWakeupinput(Figure15-2).
Note4:STOPpindoesn'thavethecontrolregistersuchasSTOPCR,sowhenSTOPmodeisreleasedbySTOP2toSTOP5pins,STOPpinalsoshouldbeusedasSTOPmodereleasefunction.
Note5:InSTOPmode,Key-onWakeuppinwhichisenabledasinputmode(forreleasingSTOPmode)byKey-onWakeupControlRegister(STOPCR)maygeneratethepenetrationcurrent,sothesaidpinmustbedisabledADconversioninput(analogvoltageinput).
Note6:WhentheSTOPmodeisreleasedbySTOP2toSTOP5pins,thelevelofSTOPpinshouldhold"L"level(Figure15-3).
Figure15-2Key-onWakeupInputandPortInputFigure15-3PriorityofSTOPpinandSTOP2toSTOP5pinsTable15-1Releaselevel(edge)ofSTOPmodePinnameReleaselevel(edge)SYSCR1="1"(Note2)SYSCR1="0"STOP"H"levelRisingedgeSTOP2"L"levelDon'tuse(Note1)STOP3"L"levelDon'tuse(Note1)STOP4"L"levelDon'tuse(Note1)STOP5"L"levelDon'tuse(Note1)PortinputExternalpinKey-onwakeupinputSTOPpina)STOPReleaseSTOPmodeSTOPmodeSTOPpin"L"b)ReleaseSTOPmodeSTOPmodeIncaseofSTOP2toSTOP5STOP2pinPage193TMP86CS28FG16.
LCDDriverTheTMP86CS28FGhasadriverandcontrolcircuittodirectlydrivetheliquidcrystaldevice(LCD).
ThepinstobeconnectedtoLCDareasfollows:1.
Segmentoutputport40pins(SEG39toSEG0)2.
Commonoutputport4pins(COM3toCOM0)Inaddition,C0,C1,V1,V2,V3pinareprovidedfortheLCDdriver'sboostercircuit.
ThedevicesthatcanbedirectlydrivenisselectablefromLCDofthefollowingdrivemethods:1.
1/4Duty(1/3Bias)LCDMax160Segments(8segments*20digits)2.
1/3Duty(1/3Bias)LCDMax120Segments(8segments*15digits)3.
1/2Duty(1/2Bias)LCDMax80Segments(8segments*10digits)4.
StaticLCDMax40Segments(8segments*5digits)16.
1ConfigurationFigure16-1LCDDriverNote:TheLCDdriverincorporatesadedicateddividercircuit.
Therefore,thebreakfunctionofadebugger(developmenttool)willnotstopLCDdriveroutput.
COM3COM0V1Dutycontrolfc/217,fs/29fc/213fc/216,fs/28CommondriverDBRdisplaydataareaDisplaydataselectcontrolTimingcontrolDisplaydatabufferregisterBlankingcontrolSegmentdriverfc/215LCDCRto76543210DUTYSLFEDSPVFSELConstantvoltageboostercircuitBRESfc/213,fs/25fc/29fc/211,fs/23V2V3C0C1fc/210,fs/22SEG0SEG39Page19416.
LCDDriver16.
2ControlTMP86CS28FG16.
2ControlTheLCDdriveriscontrolledusingtheLCDcontrolregister(LCDCR).
TheLCDdriver'sdisplayisenabledusingtheEDSP.
Note1:When(Boostercircuitcontrol)issetto"0",VDD≥V3≥V2≥V1≥VSSshouldbesatisfied.
Whenissetto"1",5.
5[V]≥V3≥VDDshouldbesatisfied.
Iftheseconditionsarenotsatisfied,itnotonlyaffectsthequalityofLCDdisplaybutalsomaydamagethedeviceduetoovervoltageoftheport.
Note2:Whenusedastheboostercircuit,biasshouldbecomposedto1/3.
Therefore,donotsetLCDCRto"10"or"11"whentheboostercircuitisenable.
Note3:DonotsetSLFto"10"or"11"inSLOW1/2modes.
Note4:DonotsetVFSELto"11"SLOW1/2modes.
LCDDriverControlRegisterLCDCR(0FD9H)76543210EDSPBRESVFSELDUTYSLF(Initialvalue:00000000)EDSPLCDDisplayControl0:Blanking1:EnablesLCDdisplay(Blankingisreleased)R/WBRESBoostercircuitcontrol0:Disable(usedividerresistance)1:EnableVFSELSelectionofboostfrequencyNORMAL1/2,IDLE/1/2modeSLOW1/2,SLEEP0/1/2modeDV7CK=0DV7CK=100fc/213fs/25fs/2501fc/211fs/23fs/2310fc/210fs/22fs/2211fc/29fc/29–DUTYSelectionofdrivingmethods00:1/4Duty(1/3Bias)01:1/3Duty(1/3Bias)10:1/2Duty(1/2Bias)11:StaticSLFSelectionofLCDframefre-quencyNORMAL1/2,IDLE/1/2modeSLOW1/2,SLEEP0/1/2modeDV7CK=0DV7CK=100fc/217fs/29fs/2901fc/216fs/28fs/2810fc/215fc/215–11fc/213fc/213–Page195TMP86CS28FG16.
2.
1LCDdrivingmethodsAsforLCDdrivingmethod,4typescanbeselectedbyLCDCR.
ThedrivingmethodisinitializedintheinitialprogramaccordingtotheLCDused.
Note1:fF:FramefrequencyNote2:VLCD3:LCDdrivevoltageFigure16-2LCDDriveWaveform(COM-SEGpins)VLCD31/fF1/fFVLCD3VLCD3Data"1"Data"0"0Data"1"VLCD3Data"0"0(b)1/3Duty(1/3Bias)(a)1/4Duty(1/3Bias)VLCD3VLCD3Data"1"Data"0"1/fF0(d)StaticVLCD3Data"1"Data"0"1/fFVLCD30(c)1/2Duty(1/2Bias)Page19616.
LCDDriver16.
2ControlTMP86CS28FG16.
2.
2FramefrequencyFramefrequency(fF)issetaccordingtodrivingmethodandbasefrequencyasshowninthefollowingTable16-1.
ThebasefrequencyisselectedbyLCDCRaccordingtothefrequencyfcandfsofthebasicclocktobeused.
Note:fc:High-frequencyclock[Hz]Note:fs:Low-frequencyclock[Hz]Table16-1SettingofLCDFrameFrequency(a)Atthesingleclockmode.
Atthedualclockmode(DV7CK=0).
SLFBasefrequency[Hz]Framefrequency[Hz]1/4Duty1/3Duty1/2DutyStatic00(fc=16MHz)122163244122(fc=8MHz)61811226101(fc=8MHz)122163244122(fc=4MHz)61811226110(fc=4MHz)122163244122(fc=2MHz)61811226111(fc=1MHz)122163244122Table16-2(b)Atthedualclockmode(DV7CK=1orSYSCK=1)SLFBasefrequency[Hz]Framefrequency[Hz]1/4Duty1/3Duty1/2DutyStatic00(fs=32.
768kHz)64851286401(fs=32.
768kHz)128171256128fc217--------fc217--------43---fc217--------42---fc217--------fc217--------fc216--------fc216--------43---fc216--------42---fc216--------fc216--------fc215--------fc215--------43---fc215--------42---fc215--------fc215--------fc213--------fc213--------43---fc213--------42---fc213--------fc213--------fs29------fs29------43---fs29------42---fs29------fs29------fs28------fs28------43---fs28------42---fs28------fs28------Page197TMP86CS28FG16.
2.
3DrivingmethodforLCDdriverIntheTMP86CS28FG,LCDdrivingvoltagescanbegeneratedusingeitheraninternalboostercircuitoranexternalresistordivider.
ThisselectionismadeinLCDCR.
16.
2.
3.
1Whenusingtheboostercircuit(LCDCR="1")WhenthereferencevoltageisconnectedtotheV1pin,theboostercircuitbooststhereferencevoltagetwofold(V2)orthreefold(V3)togeneratetheoutputvoltagesforsegment/commonsignals.
WhenthereferencevoltageisconnectedtotheV2pin,itisreducedto1/2(V1)orboostedto3/2(V3).
WhenthereferencevoltageisconnectedtotheV3pin,itisreducedto1/3(V1)or2/3(V2).
LCDCRisusedtoselectthereferencefrequencyintheboostercircuit.
Thefastertheboost-ingfrequency,thehigherthesegment/commondrivecapability,butpowerconsumptionisincreased.
Conversely,theslowertheboostingfrequency,thelowerthesegment/commondrivecapability,butpowerconsumptionisreduced.
Ifthedrivecapabilityisinsufficient,theLCDmaynotbedisplayedclearly.
Therefore,selectanoptimumboostingfrequencyfortheLCDpaneltobeused.
Table16-3showstheV3pincurrentcapacityandboostingfrequency.
Note:Whenusedastheboostercircuit,biasshouldbecomposedto1/3.
Therefore,donotsetLCDCRto"10"or"11"whentheboostercircuitisenable(LCDCR="1").
V3V2V1C1C0VDDVSSKeepthefollowingcondition.
V1=V3ReferencevoltageCCCC=0.
1to0.
47F1/3xV3a)Referencepin=V1V3V2V1C1C0VDDVSSKeepthefollowingcondition.
V2=V3ReferencevoltageCCCC=0.
1to0.
47Fb)Referencepin=V2C2/3xV3Page19816.
LCDDriver16.
2ControlTMP86CS28FGNote1:WhentheTMP86CS28FGusestheboostercircuittodrivetheLCD,thepowersupplyandcapacitorfortheboostercircuitshouldbeconnectedasshownabove.
Note2:WhenthereferencevoltageisconnectedtoapinotherthanV1,addacapacitorbetweenV1andGND.
Note3:Theconnectionexamplesshownabovearedifferentfromthoseshowninthedatasheetsofthepreviousversion.
Sincetheaboveconnectionmethodenhancestheboostingcharacteristics,itisrecommendedthatnewboardsbedesignedusingtheaboveconnectionmethod.
(UsingtheexistingconnectionmethoddoesnotaffectLCDdisplay.
)Figure16-3ConnectionExamplesWhenUsingtheBoosterCircuit(LCDCR="1")Note1:Thecurrentcapacityistheamountofvoltagethatfallsper1A.
Note2:TheboostingfrequencyshouldbeselecteddependingonyourLCDpanel.
Note3:ForthereferencepinV1orV2,acurrentcapacitytentimeslargerthantheaboveisrecommendedtoensurestableoper-ation.
Forexample,whentheboostingfrequencyisfc/29(atfc=8MHz),1.
7mV/AormoreisrecommendedforthecurrentcapacityofthereferencepinV1.
16.
2.
3.
2Whenusinganexternalresistordivider(LCDCR="0")Whenanexternalresistordividerisused,thevoltageofanexternalpowersupplyisdividedandinputonV1,V2,andV3togeneratetheoutputvoltagesforsegment/commonsignals.
Table16-3V3PinCurrentCapacityandBoostingFrequency(typ.
)VFSELBoostingfrequencyfc=16MHzfc=8MHzfc=4MHzfc=32.
768MHz00fc/213orfs/2537mV/A80mV/A138mV/A76mV/A01fc/211orfs/2319mV/A24mV/A37mV/A23mV/A10fc/210orfs/2217mV/A19mV/A24mV/A18mV/A11fc/2916mV/A17mV/A19mV/A–V3V2V1C1C0VDDVSSKeepthefollowingcondition.
V3CCCC=0.
1to0.
47Fc)Referencepin=V3CReferencevoltageV3V2V1C1C0VDDVSSKeepthefollowingcondition.
CCCC=0.
1to0.
47Fd)Referencepin=V3CV3=Page199TMP86CS28FGThesmallertheexternalresistorvalue,thehigherthesegment/commondrivecapability,butpowercon-sumptionisincreased.
Conversely,thelargertheexternalresistorvalue,thelowerthesegment/commondrivecapability,butpowerconsumptionisreduced.
Ifthedrivecapabilityisinsufficient,theLCDmaynotbedisplayedclearly.
Therefore,selectanoptimumresistorvaluefortheLCDpaneltobeused.
Figure16-4ConnectionExamplesWhenUsinganExternalResistorDivider(LCDCR="0")16.
3LCDDisplayOperation16.
3.
1DisplaydatasettingDisplaydataisstoredtothedisplaydataarea(assignedtoaddress0FC0Hto0FD3H,20bytes)intheDBR.
ThedisplaydatawhicharestoredinthedisplaydataareaisautomaticallyreadoutandsenttotheLCDdriverbythehardware.
TheLCDdrivergeneratesthesegmentsignalandcommonsignalaccordingtothedisplaydataanddrivingmethod.
Therefore,displaypatternscanbechangedbyonlyoverwritingthecontentsofdis-playdataareabytheprogram.
Table16-5showsthecorrespondencebetweenthedisplaydataareaandSEG/COMpins.
LCDlightwhendisplaydatais"1"andturnoffwhen"0".
AccordingtothedrivingmethodofLCD,thenumberofpixelswhichcanbedrivenbecomesdifferent,andthenumberofbitsinthedisplaydataareawhichisusedtostoredisplaydataalsobecomesdifferent.
Therefore,thebitswhicharenotusedtostoredisplaydataaswellasthedatabufferwhichcorrespondstotheaddressesnotconnectedtoLCDcanbeusedtostoregeneraluserprocessdata(seeTable16-4).
Note:Thedisplaydatamemorycontentsbecomeunstablewhenthepowersupplyisturnedon;therefore,thedis-playdatamemoryshouldbeinitializedbyaninitiationroutine.
Table16-4DrivingMethodandBitforDisplayDataDrivingmethodsBit7/3Bit6/2Bit5/1Bit4/01/4DutyCOM3COM2COM1COM01/3Duty–COM2COM1COM01/2Duty––COM1COM0Static–––COM0AdjustmentofcontrastAdjustmentofcontrastAdjustmentofcontrastR3R2R1OpenV3V2C0C1V1VDDVSSOpen1/3Bias(R1=R2=R3)R2R1OpenV3V2C0C1V1VDDVSSOpenR1OpenV3V2C0C1V1VDDVSSOpenStaticKeepthefollowingconditon.
VDDV3V2V1VSS1/2Bias(R1=R2)Page20016.
LCDDriver16.
3LCDDisplayOperationTMP86CS28FGNote:–:Thisbitisnotusedfordisplaydata16.
3.
2BlankingBlankingisenabledwhenEDSPisclearedto"0".
BlankingturnsoffLCDthroughoutputtingaGNDleveltoSEG/COMpin.
WheninSTOPmode,EDSPisclearedto"0"andautomaticallyblanked.
ToredisplayICDafterexitingSTOPmode,itisnecessarytosetEDSPbackto"1".
Note:Duringreset,theLCDcommonoutputsarefixed"0"level.
Butthemultiplexterminalofinput/outputportandLCDsegmentoutputbecomeshighimpedance.
Therefore,whentheresetinputislongremarkably,ghostproblemmayappearinLCDdisplay.
Table16-5LCDDisplayDataArea(DBR)AddressBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit00FC0HSEG1SEG00FC1HSEG3SEG20FC2HSEG5SEG40FC3HSEG7SEG60FC4HSEG9SEG80FC5HSEG11SEG100FC6HSEG13SEG120FC7HSEG15SEG140FC8HSEG17SEG160FC9HSEG19SEG180FCAHSEG21SEG200FCBHSEG23SEG220FCCHSEG25SEG240FCDHSEG27SEG260FCEHSEG29SEG280FCFHSEG31SEG300FD0HSEG33SEG320FD1HSEG35SEG340FD2HSEG37SEG360FD3HSEG39SEG38COM3COM2COM1COM0COM3COM2COM1COM0Page201TMP86CS28FG16.
4ControlMethodofLCDDriver16.
4.
1InitialsettingFigure16-5showstheflowchartofinitialization.
Figure16-5InitialSettingofLCDDriver16.
4.
2StoreofdisplaydataGenerally,displaydataarepreparedasfixeddatainprogrammemory(ROM)andstoredindisplaydataareabyloadcommand.
Example:Tooperatea1/4dutyLCDof40segments*4com-monsatframefrequencyfc/216[Hz],andboosterfre-quencyfc/213[Hz]LD(LCDCR),01000001B;SetsLCDdrivingmethodandframefrequency.
BoostfrequencyLD(P*LCR),0FFH;Setssegmentoutputcontrolregister.
(*;PortNo.
)::::;Setstheinitialvalueofdisplaydata.
LD(LCDCR),11000001B;DisplayenableSetsLCDdrivingmethod(DUTY).
Setsframefrequency(SLF).
Setssegmentoutputcontrolregisters(P*LCR(*;PortNo.
))Initializationofdisplaydataarea.
Displayenable(EDSP)(Releasesfromblanking.
)Setsboostfrequency(VFSEL).
Enablesboostercircuit(BRES)Page20216.
LCDDriver16.
4ControlMethodofLCDDriverTMP86CS28FGNote:DBisabytedatadifinitioninstruction.
Figure16-6ExampleofCOM,SEGPinConnection(1/4Duty)Example:Todisplayusing1/4dutyLCDanumericalvaluewhichcorrespondstotheLCDdatastoredindatamem-oryataddress80H(whenpinsCOMandSEGareconnectedtoLCDasinFigure16-6),displaydatabecomeasshowninTable16-6.
LDA,(80H)ADDA,TABLE-$-7LDHL,0F80HLDW,(PC+A)LD(HL),WRETTABLE:DB11011111B,00000110B,11100011B,10100111B,00110110B,10110101B,11110101B,00010111B,11110111B,10110111BTable16-6ExampleofDisplayData(1/4Duty)No.
displayDisplaydataNo.
displayDisplaydata011011111510110101100000110611110101211100011700000111310100111811110111400110110910110111SEG0SEG1COM0COM1COM2COM3Page203TMP86CS28FGExample2:Table16-6showsanexampleofdisplaydatawhicharedisplayedusing1/2dutyLCDinthesamewayasTable16-7.
TheconnectionbetweenpinsCOMandSEGarethesameasshowninFigure16-7.
Figure16-7ExampleofCOM,SEGPinConnectionNote:*:Don'tcareTable16-7ExampleofDisplayData(1/2Duty)NumberDisplaydataNumberDisplaydataHighorderaddressLoworderaddressHighorderaddressLoworderaddress0**01**11**01**115**11**10**01**011**00**10**00**106**11**11**01**012**10**01**01**117**01**10**00**113**10**10**01**118**11**11**01**114**11**10**00**109**11**10**01**11SEG0SEG2SEG1SEG3COM0COM1Page20416.
LCDDriver16.
4ControlMethodofLCDDriverTMP86CS28FG16.
4.
3ExampleofLCDdriveoutputFigure16-81/4Duty(1/3bias)DriveVLCD30VLCD30VLCD30VLCD30VLCD30VLCD30VLCD3VLCD3VLCD300VLCD3SEG0SEG1DisplaydataareaAddressSEG0EDSPSEG1COM0COM1COM2COM3COM0-SEG0(Selected)COM2-SEG1(Nonselected)10110101COM0COM1COM2COM30FC0HPage205TMP86CS28FGFigure16-91/3Duty(1/3bias)DriveSEG2Address*:Don'tcareSEG0EDSPSEG1SEG2COM0COM1COM2COM0-SEG1(Selected)COM1-SEG2(Nonselected)SEG1SEG0COM0COM1COM2Displaydataarea*111*010*****001VLCD30VLCD30VLCD30VLCD30VLCD30VLCD30VLCD3VLCD3VLCD300VLCD30FC0H0FC1HPage20616.
LCDDriver16.
4ControlMethodofLCDDriverTMP86CS28FGFigure16-101/2Duty(1/2bias)DriveAddress*:Don'tcareSEG0EDSPSEG1SEG2COM0COM1COM0-SEG1(Selected)COM1-SEG2(Nonselected)Displaydataarea**01**01**11**10VLCD30VLCD30VLCD30VLCD30VLCD30VLCD30VLCD30VLCD3SEG3VLCD30COM0COM2COM1SEG3COM0COM1VLCD30FC0H0FC1HPage207TMP86CS28FGFigure16-11StaticDriveSEG2SEG7AddressSEG5SEG4SEG3SEG0SEG1SEG6COM0VLCD3VLCD30VLCD30VLCD3VLCD3VLCD3VLCD30SEG0SEG4SEG7COM0COM0-SEG0(Selected)COM0-SEG4(Nonselected)0VLCD3EDSP***0***1***1***1***1***0***0***1Displaydataarea*:Don'tcare000FC0H0FC1H0FC2H0FC3HPage20816.
LCDDriver16.
4ControlMethodofLCDDriverTMP86CS28FGPage209TMP86CS28FG17.
Input/OutputCircuitry17.
1ControlPinsTheinput/outputcircuitriesoftheTMP86CS28FGcontrolpinsareshownbelow.
ControlPinI/OInput/OutputCircuitryRemarksXINXOUTInputOutputResonatorconnectingpins(high-frequency)Rf=1.
2M(typ.
)RO=0.
5k(typ.
)XTINXTOUTInputOutputResonatorconnectingpins(Low-frequency)Rf=6M(typ.
)RO=220k(typ.
)RESETInputHysteresisinputPull-upresistorRIN=220k(typ.
)TESTInputPull-downresistorRIN=70k(typ.
)R=1k(typ.
)fcRfROOsc.
enableXINXOUTVDDVDDfsRfROOsc.
enableXTINXTOUTXTENVDDVDDVDDAddress-trap-resetWatchdog-timerSystem-clock-resetRINVDDRINRD1Page21017.
Input/OutputCircuitry17.
2Input/OutputPortsTMP86CS28FG17.
2Input/OutputPortsPortI/OInput/OutputCircuitryRemarksP0,P3InputOutputSinkopendrainoutputorC-MOSoutputHysteresisinputR=100(typ.
)P1InputOutputTri-stateI/OHysteresisinputAINinputR=100W(typ.
)P2InputOutputSinkopendrainoutputHysteresisinputR=100(typ.
)P4,P5,P6,P7,P8InputOutputSinkopendrainoutputorC-MOSoutputHysteresisinputR=100(typ.
)LCDsegmentoutputInitial"High-Z"InputfromoutputlatchPchcontrolDataoutputPininputVDDRInitial"High-Z"DisableAINDataoutputPininputVDDRInitial"High-Z"DataoutputPininputInputfromoutputlatchVDDRInitial"High-Z"InputfromoutputlatchPchcontrolDataoutputPininputVDDRSEGoutputPage211TMP86CS28FG18.
ElectricalCharacteristics18.
1AbsoluteMaximumRatingsTheabsolutemaximumratingsareratedvalueswhichmustnotbeexceededduringoperation,evenforaninstant.
Anyoneoftheratingsmustnotbeexceeded.
Ifanyabsolutemaximumratingisexceeded,adevicemaybreakdownoritsperformancemaybedegraded,causingittocatchfireorexploderesultingininjurytotheuser.
Thus,whendesigningproductswhichincludethisdevice,ensurethatnoabsolutemaximumratingvaluewilleverbeexceeded.
(VSS=0V)ParameterSymbolPinsRatingsUnitSupplyvoltageVDD0.
3to6.
5VInputvoltageVIN0.
3toVDD+0.
3OutputvoltageVOUT0.
3toVDD+0.
3Outputcurrent(Per1pin)IOL1P0,P1,P2,P3,P4,P5,P6,P7,P8ports3.
2mAIOH1P0,P1,P3,P4,P5,P6,P7,P8ports1.
8Outputcurrent(Total)ΣIOL1P0,P1,P2,P3,P4,P5,P6,P7,P8ports80ΣIOH1P0,P1,P3,P4,P5,P6,P7,P8ports30Powerdissipation[Topr=85°C]PD350mWSolderingtemperature(Time)Tsld260(10s)°CStoragetemperatureTstg55to125OperatingtemperatureTopr40to85Page21218.
ElectricalCharacteristics18.
2OperatingConditionTMP86CS28FG18.
2OperatingConditionTheOperatingConditionsshowtheconditionsunderwhichthedevicebeusedinorderforittooperatenormallywhilemaintainingitsquality.
IfthedeviceisusedoutsidetherangeofOperatingConditions(powersupplyvoltage,operatingtemperaturerange,orAC/DCratedvalues),itmayoperateerratically.
Therefore,whendesigningyourapplicationequipment,alwaysmakesureitsintendedworkingconditionswillnotexceedtherangeofOperatingConditions.
(VSS=0V,Topr=40to85°C)ParameterSymbolPinsConditionMinMaxUnitSupplyvoltageVDDfc=16MHzNORMAL1,2mode4.
05.
5VIDLE0,1,2modefc=8MHzNORMAL1,2mode2.
7IDLE0,1,2modefs=32.
768kHzSLOW1,2modeSLEEP0,1,2modeSTOPmodeInputhighlevelVIH1ExcepthysteresisinputVDD≥4.
5VVDD*0.
70VDDVIH2HysteresisinputVDD*0.
75VIH3VDD<4.
5VVDD*0.
90InputlowlevelVIL1ExcepthysteresisinputVDD≥4.
5V0VDD*0.
30VIL2HysteresisinputVDD*0.
25VIL3VDD<4.
5VVDD*0.
10ClockfrequencyfcXIN,XOUTVDD=2.
7Vto5.
5V1.
08.
0MHzVDD=4.
0Vto5.
5V16.
0fsXTIN,XTOUTVDD=2.
7Vto5.
5V30.
034.
0kHzLCDreferencevoltagerangeV1LCDboostercircuitenable(V3≥VDD)0.
91.
8VCapacityforLCDboostercircuitCLCD0.
10.
47uFPage213TMP86CS28FG18.
3DCCharacteristicsNote1:TypicalvaluesshowthoseatTopr=25°C,VDD=5VNote2:Inputcurrent(IIN1,IIN2);Thecurrentthroughpull-uporpull-downresistorisnotincluded.
Note3:IDDdoesnotincludeIREFcurrent.
Note4:ThesupplycurrentsofSLOW2andSLEEP2modesareequivalenttoIDLE0,1,2.
(VSS=0V,Topr=40to85°C)ParameterSymbolPinsConditionMinTyp.
MaxUnitHysteresisvoltageVHSHysteresisinput–0.
9–VInputcurrentIIN1Sinkopendrain,Tri-stateVDD=5.
5V,VIN=5.
5V/0V––±2AIIN2RESET,STOPInputresistanceRIN1TESTpull-dwon–70–kRIN2RESETpull-up100220450OutputleakagecurrentILOSinkopendrain,Tri-stateVDD=5.
5V,VOUT=5.
5V/0V––±2AOutputhighvoltageVOHC-MOS,Tri-stportVDD=4.
5V,IOH=0.
7mA4.
1––VOutputlowvoltageVOLExceptXOUTVDD=4.
5V,IOL=1.
6mA––0.
4LCDoutputvoltageuseLCDdriver'sboosteV2-3OUTV2terminalV3≥VDDReferencesupplyterminal:V1SEG/COMterminalnoload–V1x2–VV3terminal–V1x3–SupplycurrentinNORMAL1,2modeIDDVDD=5.
5VVIN=5.
3V/0.
2Vfc=16MHzfs=32.
768kHz–8.
511.
5mASupplycurrentinIDLE0,1,2mode–68.
5SupplycurrentinSLOW1modeVDD=3.
0VVIN=2.
8V/0.
2Vfs=32.
768kHz–8.
520ASupplycurrentinSLEEP1mode–6.
115SupplycurrentinSLEEP0mode–511SupplycurrentinSTOPmodeVDD=5.
5VVIN=5.
3V/0.
2V–0.
510Page21418.
ElectricalCharacteristics18.
4ADConversionCharacteristicsTMP86CS28FG18.
4ADConversionCharacteristicsNote1:Thetotalerrorincludesallerrorsexceptaquantizationerror,andisdefinedasamaximumdeviationfromtheidealcon-versionline.
Note2:Conversiontimeisdifferentinrecommendedvaluebypowersupplyvoltage.
Aboutconversiontime,pleasereferto"RegisterConfiguration".
Note3:PleaseuseinputvoltagetoAINinputPininlimitofVAREFtoVSS.
Whenvoltageofrangeoutsideisinput,conversionvaluebecomesunsettledandgivesaffecttootherchannelconversionvalue.
Note4:Analogreferencevoltagerange:VAREF=VAREFVSSNote5:TheAVDDpinshouldbefixedontheVDDleveleventhoughADconverterisnotused.
(VSS=0.
0V,4.
5V≤VDD≤5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitAnalogreferencevoltageVAREFAVDD1.
0–AVDDVPowersupplyvoltageofanalogcontrolcircuit(Note6)AVDDVDDAVSSVSSAnalogreferencevoltagerange(Note4)VAREF3.
5––AnaloginputvoltageVAINAVSS–VAREFPowersupplycurrentofanalogreferencevoltageIREFVDD=AVDD=VAREF=5.
5VVSS=AVSS=0.
0V–0.
61.
0mANonlinearityerrorVDD=AVDD=5.
0VVSS=AVSS=0.
0VVAREF=5.
0V––±2LSBZeropointerror––±2Fullscaleerror––±2Totalerror––±2(VSS=0.
0V,2.
7V≤VDD<4.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitAnalogreferencevoltageVAREFAVDD1.
0–AVDDVPowersupplyvoltageofanalogcontrolcircuit(Note6)AVDDVDDAVSSVSSAnalogreferencevoltagerange(Note4)VAREF2.
5––AnaloginputvoltageVAINVSS–VAREFPowersupplycurrentofanalogreferencevoltageIREFVDD=AVDD=VAREF=4.
5VVSS=AVSS=0.
0V–0.
50.
8mANonlinearityerrorVDD=AVDD=2.
7VVSS=AVSS=0.
0VVAREF=2.
7V––±2LSBZeropointerror––±2Fullscaleerror––±2Totalerror––±2Page215TMP86CS28FG18.
5ACCharacteristics(VSS=0V,VDD=4.
0to5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitMachinecycletimetcyNORMAL1,2mode0.
25–4sIDLE1,2modeSLOW1,2mode117.
6–133.
3SLEEP1,2modeHighlevelclockpulsewidthtWCHForexternalclockoperation(XINinput)fc=16MHz–31.
25–nsLowlevelclockpulsewidthtWCLHighlevelclockpulsewidthtWCHForexternalclockoperation(XTINinput)fs=32.
768kHz–15.
26–sLowlevelclockpulsewidthtWCL(VSS=0V,VDD=2.
7to5.
5V,Topr=40to85°C)ParameterSymbolConditionMinTyp.
MaxUnitMachinecycletimetcyNORMAL1,2mode0.
5–4sIDLE1,2modeSLOW1,2mode117.
6–133.
3SLEEP1,2modeHighlevelclockpulsewidthtWCHForexternalclockoperation(XINinput)fc=8MHz–62.
5–nsLowlevelclockpulsewidthtWCLHighlevelclockpulsewidthtWCHForexternalclockoperation(XTINinput)fs=32.
768kHz–15.
26–sLowlevelclockpulsewidthtWCLPage21618.
ElectricalCharacteristics18.
6RecommendedOscillatingConditionsTMP86CS28FG18.
6RecommendedOscillatingConditionsNote1:Toensurestableoscillation,theresonatorposition,loadcapacitance,etc.
mustbeappropriate.
Becausethesefactorsaregreatlyaffectedbyboardpatterns,pleasebesuretoevaluateoperationontheboardonwhichthedevicewillactuallybemounted.
Note2:FortheresonatorstobeusedwithToshibamicrocontrollers,werecommendceramicresonatorsmanufacturedbyMurataManufacturingCo.
,Ltd.
Fordetails,pleasevisitthewebsiteofMurataatthefollowingURL:http://www.
murata.
com18.
7HandlingPrecaution-Thesolderabilitytestconditionsforlead-freeproducts(indicatedbythesuffixGinproductname)areshownbelow.
1.
WhenusingtheSn-37PbsolderbathSolderbathtemperature=230°CDippingtime=5secondsNumberoftimes=onceR-typefluxused2.
WhenusingtheSn-3.
0Ag-0.
5CusolderbathSolderbathtemperature=245°CDippingtime=5secondsNumberoftimes=onceR-typefluxusedNote:Thepasscriteronoftheabovetestisasfollows:Solderabilityrateuntilforming≥95%-Whenusingthedevice(oscillator)inplacesexposedtohighelectricfieldssuchascathode-raytubes,werecommendelectricallyshieldingthepackageinordertomaintainnormaloperatingcondition.
(2)Low-frequencyOscillation(1)High-frequencyOscillationXINXOUTC2C1XTINXTOUTC2C1Page217TMP86CS28FG19.
PackageDimensionsQFP80-P-1420-0.
80BRev01Unit:mmPage21819.
PackageDimensionsTMP86CS28FGThisisatechnicaldocumentthatdescribestheoperatingfunctionsandelectricalspecificationsofthe8-bitmicrocontrollerseriesTLCS-870/C(LSI).
Toshibaprovidesavarietyofdevelopmenttoolsandbasicsoftwaretoenableefficientsoftwaredevelopment.
Thesedevelopmenttoolshavespecificationsthatsupportadvancesinmicrocomputerhardware(LSI)andcanbeusedextensively.
Boththehardwareandsoftwarearesupportedcontinuouslywithversionupdates.
TherecentadvancesinCMOSLSIproductiontechnologyhavebeenphenomenalandmicrocomputersystemsforLSIdesignareconstantlybeingimproved.
Theproductsdescribedinthisdocumentmayalsoberevisedinthefuture.
Besuretocheckthelatestspecificationsbeforeusing.
Toshibaisdevelopinghighlyintegrated,high-performancemicrocomputersusingadvancedMOSproductiontechnologyandespeciallywellprovenCMOStechnology.
Wearepreparedtomeettherequestsforcustompackagingforavarietyofapplicationareas.
Weareconfidentthatourproductscansatisfyyourapplicationneedsnowandinthefuture.