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SN65LVDS311www.
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comSLLSE31B–MAY2010–REVISEDMARCH2013PROGRAMMABLE27-BITDISPLAYSERIALINTERFACETRANSMITTERCheckforSamples:SN65LVDS311Whentransmitting,thePLLlockstotheincoming1FEATURESpixelclockPCLKandgeneratesaninternalhigh-2.
8*2.
8mmpackagesizespeedclockatthelinerateofthedatalines.
The1.
8VinputsignalswingparalleldataislatchedontherisingedgeofPCLK.
Theserializeddataispresentedontheserialoutputs24-BitRGBData,3ControlBits,1ParityBitD0,D1,D2witharecreationofthePixelclockPCLKand2ReservedBitsTransmittedover1,2or3generatedfromtheinternalhigh-speedclockandDifferentialLinesoutputontheCLKoutput.
IftheinputclockPCLKSubLVDSDifferentialVoltageLevelsstops,thedeviceentersastandbymodetoconserveThreeOperatingModestoConservePowerpower.
–Active-ModeQVGA17.
4mW(typ)TwoLink-SelectlinesLS0andLS1controlwhether1,2or3seriallinksareused.
TheTXENinputmaybe–Active-ModeVGA28.
8mW(typ)usedtoputtheSN65LVDS311inashutdownmode.
–ShutdownMode≈0.
5μA(typ)TheSN65LVDS311entersanactiveStandbymodeif–StandbyMode≈0.
5μA(typ)theinputclockPCLKstops.
ThisminimizespowerESDRating>3kV(HBM)consumptionwithouttheneedforcontrollinganexternalpin.
TheSN65LVDS311ischaracterizedforPixelClockRangeof4MHz–65MHzoperationoverambientairtemperaturesof-40°CtoFailsafeonallCMOSInputs85°C.
AllCMOSinputsofferfailsafetoprotecttheTypicalApplication:Cameras,Embeddedinputfromdamageduringpower-upandtoavoidComputerscurrentflowintothedeviceinputsduringpower-up.
DESCRIPTIONTheSN65LVDS311serializertransmits27parallelinputdataover1,2,or3serialoutputlinks.
ThedevicepinoutisoptimizedtointerfacewiththeOMAP3630applicationprocessor.
Thedeviceloadsashiftregisterwiththe24pixelbitsand3controlbitsfromtheparallelCMOSinputinterface.
Thedataarelatchedintothedevicebythepixelclock,PCLK.
Inadditiontothe27bits,thedeviceaddsaparitybitandtworeservedbitsforatotalnumberof30serialbits.
Theparitybitallowsareceivertodetectsingle-biterrors.
Oddparityisimplemented.
Theserialshiftregisterisuploadedthrough1,2,or3serialoutputsat30,15,or10timesthepixelclockdatarate.
Acopyofthepixelclockisoutputonanadditionaldifferentialoutput.
TheserialdataandclockaretransmittedviaSubLow-VoltageDifferentialSignaling(SubLVDS)lines.
TheSN65LVDS311supportsthreepowermodes(Shutdown,StandbyandActive)toconservepower.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2010–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
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comThisintegratedcircuitcanbedamagedbyESD.
TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.
Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.
Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
FunctionalBlockDiagramPINOUT2SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
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comSLLSE31B–MAY2010–REVISEDMARCH2013Table1.
SIGNALLISTSIGNALPINSIGNALPINSIGNALPINSIGNALPINR0B3G0B4B0C1PCLKA7R1B2G1A3B1D1HSB7R2A2G2E2B2E3VSB6R3A1G3C3B3F3DEA6R4A5G4G1B4E1TXENE5R5B1G5F1B5F2LS0C6R6D2G6C2B6B5LS1C5R7D3G7G2B7A4D0PG4D1PE7D2PC7CLKPG6D0NG3D1NF7D2ND7CLKNG5VDDD4VDDPLLDD5VDDPLLAF6VDDLVDSG7GNDC4,D6,E6,E4,F4,F5Table2.
TERMINALFUNCTIONSNAMEI/ODESCRIPTIOND0+,D0–SubLVDSDataLink(activeduringnormaloperation)SubLVDSDataLink(activeduringnormaloperationwhenLS0=highandLS1=low,orD1+,D1–LS0=lowandLS1=high;highimpedanceifLS0=LS1=low)SubLVDSOutSubLVDSDataLink(activeduringnormaloperationwhenLS0=lowandLS1=high,D2+,D2–high-impedancewhenLS1=low)CLK+,CLK–SubLVDSoutputClock;clockpolarityisfixedR0–R7RedPixelData(8);pinassignmentdependsonSWAPpinsettingG0–G7GreenPixelData(8);pinassignmentdependsonSWAPpinsettingB0–B7BluePixelData(8);pinassignmentdependsonSWAPpinsettingHSHorizontalSyncVSVerticalSyncDEDataEnablePCLKInputPixelClock;dataarelatchedonrisinginputclockedgeLS0,LS1LinkSelect(DeterminesactiveSubLVDSDataLinksandPLLRange)SeeTable3CMOSINDisablestheCMOSDriversandTurnsOffthePLL,puttingdeviceinshutdownmode1–Transmitterenabled0–Transmitterdisabled(Shutdown)TXENNote:TheTXENinputincorporatesglitch-suppressionlogictoavoiddevicemalfunctiononshortinputspikes.
ItisnecessarytopullTXENhighforlongerthan10μstoenablethetransmitter.
ItisnecessarytopulltheTXENinputlowforlongerthan10μstodisablethetransmitter.
Atpowerup,thetransmitterisenabledimmediatelyifTXEN=1anddisabledifTXEN=0VDDSupplyVoltageGNDSupplyGroundVDDLVDSSubLVDSI/OsupplyVoltageGNDLVDSSubLVDSGroundPowerSupply(1)VDDPLLAPLLanalogsupplyVoltageGNDPLLAPLLanalogGNDVDDPLLDPLLdigitalsupplyVoltageGNDPLLDPLLdigitalGND(1)Foramultilayerpcb,itisrecommendedtokeeponecommonGNDlayerunderneaththedeviceandconnectallgroundterminalsdirectlytothisplane.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
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comFUNCTIONALDESCRIPTIONSerializationModesTheSN65LVDS311transmitterhasthreemodesofoperationcontrolledbylink-selectpinsLS0andLS1.
Table3showstheserializermodesofoperation.
Table3.
LogicTable:LinkSelectOperatingModesLS1LS0ModeofOperationDataLinksStatus001ChM1-channelmode(30-bitserializationrate)D0active;D1,D2high-impedance012ChM2-channelmode(15-bitserializationrate)D0,D1active;D2high-impedance103ChM3-channelmode(10-bitserializationrate)D0,D1,D2active11ReservedReserved1-ChannelModeWhileLS0andLS1areheldlow,theSN65LVDS311transmitspayloaddataoverasingleSubLVDSdatapair,D0.
ThePLLlockstoPCLKandinternallymultipliestheclockbyafactorof30.
Theinternalhigh-speedclockisusedtoserialize(shiftout)thedatapayloadonD0.
Tworeservedbitsandtheparitybitareaddedtothedataframe.
Figure1illustratesthetimingandthemappingofthedatapayloadintothe30-bitframe.
Theinternalhigh-speedclockisdividedbyafactorof30torecreatethepixelclock,andpresentedontheSubLVDSCLKoutput.
Whileinthismode,thePLLcanlocktoaclockthatisintherangeof4MHzthrough15MHz.
Thismodeisintendedforsmallervideodisplayformats(e.
g.
QVGAtoHVGA)thatdonotrequirethefullbandwidthcapabilitiesoftheSN65LVDS311.
Figure1.
DataandClockOutputin1-ChannelMode(LS0andLS1=low).
2-ChannelModeWhileLS0isheldhighandLS1isheldlow,theSN65LVDS311transmitspayloaddataovertwoSubLVDSdatapairs,D0andD1.
ThePLLlockstoPCLKandinternallymultipliesitbyafactorof15.
Theinternalhigh-speedclockisusedtoserializethedatapayloadonD0,andD1.
Tworeservedbitsandtheparitybitareaddedtothedataframe.
Figure2illustratesthetimingandthemappingofthedatapayloadintothe30-bitframeandhowtheframebecomessplitintothetwooutputchannels.
Theinternalhigh-speedclockisdividedby15torecreatethepixelclock,andpresentedonSubLVDSCLK.
ThePLLcanlocktoaclockthatisintherangeof8MHzthrough30MHzinthismode.
Typicalapplicationsforusingthe2-channelmodeareHVGAandVGAdisplays.
Figure2.
DataandClockOutputin2-ChannelMode(LS0=high;LS1=low).
4SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
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comSLLSE31B–MAY2010–REVISEDMARCH20133-ChannelModeWhileLS0isheldlowandLS1isheldhigh,theSN65LVDS311transmitspayloaddataoverthreeSubLVDSdatapairsD0,D1,andD2.
ThePLLlockstoPCLK,andinternallymultipliesitby10.
Theinternalhigh-speedclockisusedtoserializethedatapayloadonD0,D1,andD2.
Tworeservedbitsandtheparitybitareaddedtothedataframe.
Figure3illustratesthetimingandthemappingofthedatapayloadintothe30-bitframeandhowtheframebecomessplitoverthethreeoutputchannels.
Theinternalhighspeedclockisdividedbackdownbyafactorof10torecreatethepixelclockandpresentedonSubLVDSCLKoutput.
Whileinthismode,thePLLcanlocktoaclockintherangeof20MHzthrough65MHz.
The3-channelmodesupportsapplicationswithverylargedisplayresolutionssuchasVGAorXGA.
Figure3.
DataandClockOutputin3-ChannelMode(LS0=low;LS1=high).
PowerdownModesTheSN65LVDS311Transmitterhastwopowerdownmodestofacilitateefficientpowermanagement.
ShutdownModeTheSN65LVDS311entersShutdownmodewhentheTXENpinisassertedlow.
Thisturnsoffalltransmittercircuitry,includingtheCMOSinput,PLL,serializer,andSubLVDStransmitteroutputstage.
Alloutputsarehigh-impedance.
CurrentconsumptioninShutdownmodeisnearlyzero.
StandbyModeTheSN65LVDS311enterstheStandbymodeifTXENishighandthePCLKinputfrequencyislessthan500kHz.
AllcircuitryexceptthePCLKinputmonitorisshutdown,andalloutputsenterhigh-impedancemode.
ThecurrentconsumptioninStandbymodeisverylow.
WhenthePCLKinputsignaliscompletelystopped,theIDDcurrentconsumptionislessthan10μA.
ThePCLKinputmustnotbeleftfloating.
NOTEAfloating(leftopen)CMOSinputallowsleakagecurrentstoflowfromVDDtoGND.
Topreventlargeleakagecurrent,aCMOSgatemustbekeptatavalidlogiclevel,eitherVIHorVIL.
ThiscanbeachievedbyapplyinganexternalvoltageofVIHorVILtoallSN65LVDS311inputs.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
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comActiveModesWhenTXENishighandthePCLKinputclocksignalisfasterthan3MHz,theSN65LVDS311entersActivemode.
CurrentconsumptioninActivemodedependsonoperatingfrequencyandthenumberofdatatransitionsinthedatapayload.
AcquireMode(PLLapproacheslock)ThePLLisenabledandattemptstolocktotheinputClock.
Alloutputsremaininhigh-impedancemode.
WhenthePLLmonitordetectsstablePLLoperation,thedeviceswitchesfromAcquiretoTransmitmode.
Forproperdeviceoperation,thepixelclockfrequencymustfallwithinthevalidfPCLKrangespecifiedunderrecommendedoperatingconditions.
Ifthepixelclockfrequencyislargerthan3MHzbutsmallerthanfPCLK(min),theSN65LVDS311PLLisenabled.
Undersuchconditions,itispossibleforthePLLtolocktemporarilytothepixelclock,causingthePLLmonitortoreleasethedeviceintotransmitmode.
Ifthishappens,thePLLmayormaynotbeproperlylockedtothepixelclockinput,potentiallycausingdataerrors,frequencyoscillation,andPLLdeadlock(lossofVCOoscillation).
TransmitModeAfterthePLLachieveslock,thedeviceentersthenormaltransmitmode.
TheCLKpinoutputsacopyofPCLK.
Basedontheselectedmodeofoperation,theD0,D1,andD2outputscarrytheserializeddata.
In1-channelmode,outputsD1andD2remainhigh-impedance.
Inthe2-channelmode,outputD2remainshigh-impedance.
ParityBitGenerationTheSN65LVDS311transmittercalculatestheparityofthetransmitdatawordandsetstheparitybitaccordingly.
Theparitybitcoversthe27bitdatapayloadconsistingof24bitsofpixeldataplusVS,HSandDE.
Thetworeservedbitsarenotincludedintheparitygeneration.
ODDParitybitsignalingisused.
ThetransmittersetstheParitybitifthesumofthe27databitsresultinanevennumberofones.
TheParitybitisclearedotherwise.
ThisallowsthereceivertoverifyParityanddetectsinglebiterrors.
StatusDetectandOperatingModesFlowdiagramTheSN65LVDS311switchesbetweenthepowersavingandactivemodesinthefollowingway:Figure4.
StatusDetectandOperatingModesFlowDiagram6SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
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comSLLSE31B–MAY2010–REVISEDMARCH2013Table4.
StatusDetectandOperatingModesDescriptionsModeCharacteristicsConditionsShutdownModeLeastamountofpowerconsumption(1)(mostcircuitryturnedTXENislow(1)(2)off);Alloutputsarehigh-impedanceStandbyModeLowpowerconsumption(onlyclockactivitycircuitactive;PLLTXENishigh;PCLKinputsignalismissingorisdisabledtoconservepower);Alloutputsarehigh-inactive(2)impedanceAcquireModePLLtriestoachievelock;Alloutputsarehigh-impedanceTXENishigh;PCLKinputmonitordetectedinputactivityTransmitModeDatatransfer(normaloperation);TransmitterserializesdataTXENishighandPLLislockedtoincomingclockandtransmitsdataonserialoutput;unusedoutputsremainhigh-impedance(1)InShutdownMode,allSN65LVDS311internalswitchingcircuits(e.
g.
,PLL,serializer,etc.
)areturnedofftominimizepowerconsumption.
Theinputstageofanyinputpinremainsactive.
(2)Leavinginputsunconnectedcancauserandomnoisetotoggletheinputstageandpotentiallyharmthedevice.
AllinputsmustbetiedtoavalidlogiclevelVILorVIHduringShutdownorStandmbyMode.
Table5.
OperatingModeTransitionsMODETRANSITIONUSECASETRANSITIONSPECIFICSShutdown→StandbyDriveTXENhightoenable1.
TXENhigh>10μstransmitter2.
Transmitterentersstandbymodea.
Alloutputsarehigh-impedanceb.
TransmitterturnsonclockinputmonitorStandby→AcquireTransmitteractivitydetected1.
PCLKinputmonitordetectsclockinputactivity;2.
Outputsremainhigh-impedance;3.
PLLcircuitisenabledAcquire→TransmitLinkisreadytotransferdata1.
PLLisactiveandapproacheslock2.
PLLachievedlockwithin2ms3.
ParallelDatainputlatchesintoshiftregister4.
CLKoutputturnson5.
selectedDataoutputsturnonandsendoutfirstserialdatabitTransmit→StandbyRequestTransmittertoenter1.
PCLKInputmonitordetectsmissingPCLKStandbymodebystopping2.
Transmitterindicatesstandby,puttingalloutputsintohigh-impedance;PCLK3.
PLLshutsdown;4.
PCLKactivityinputmonitorremainsactiveTransmit/Standby→TurnoffTransmitter1.
TXENpulledlowforlongerthan10usShutdown2.
Transmitterindicatesstandby,puttingoutputCLK+andCLK–intohigh-impedancestate;3.
Transmitterputsallotheroutputsintohigh-impedancestate4.
MostICcircuitryisshutdownforleastpowerconsumptionCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
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comORDERINGINFORMATION(1)PARTNUMBERPACKAGESHIPPINGMETHODSN65LVDS311YFFTrayYFFSN65LVDS311YFFRReel(1)Updatedoderinginformationisfoundintheorderableaddendumattheendofthisdocument.
ABSOLUTEMAXIMUMRATINGS(1)overoperatingfree-airtemperaturerange(unlessotherwisenoted)VALUEUNITSupplyvoltagerange,VDD(2),VDDPLLA,VDDPLLD,VDDLVDS-0.
3to2.
175VVoltagerangeatanyinputWhenVDDx>0V-0.
5to2.
175VoroutputterminalWhenVDDx≤0V-0.
5toVDD+2.
175VHumanBodyModel(3)(allPins)±3kVElectrostaticdischargeCharged-DeviceMode(4)l(allPins)±500VMachineModel(5)(allpins)±200ContinuouspowerdissipationSeeDissipationRatingTable(1)Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.
Exposuretoabsolutemaximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)AllvoltagevaluesarewithrespecttotheGNDterminals.
(3)InaccordancewithJEDECStandard22,TestMethodA114-A.
(4)InaccordancewithJEDECStandard22,TestMethodC101.
(5)InaccordancewithJEDECStandard22,TestMethodA115-ADISSIPATIONRATINGSCIRCUITDERATINGFACTOR(1)TA=85°CPACKAGEθJA50MHz;f(noise)=1Hzto1MHz100f(PCLK)>50MHz;f(noise)>1MHz401-Channeltransmitmode,seeFigure14152-Channeltransmitmode,seeFigure2830fPCLKPixelclockfrequencyMHz3-Channeltransmitmode,seeFigure32065FrequencythresholdStandbymodetoactive0.
53mode(2),seeFigure14tHxfPCLKPCLKinputdutycycle0.
330.
67TAOperatingfree-air–4085°Ctemperaturetjit(per)PCLKPCLKRMSperiodjitter(3)5ps-rmstjit(TJ)PCLKPCLKtotaljitter0.
05/fPCLKsMeasuredonPCLKinputtjit(CC)PCLKPCLKpeak0.
02/fPCLKscycle-to-cyclejitter(4)PCLK,R[0:7],G[0:7],B[0:7],VS,HS,DE,PCLK,LS[1:0],TXEN,SWAPVIHHigh-levelinputvoltage0.
7*VDDVDDVVILLow-levelinputvoltage0.
3*VDDVtDSDatasetuptimepriorto2.
0nsPCLKtransitionf(PCLK)=65MHz;seeFigure6tDHDataholdtimeafterPCLK2.
0nstransition(1)Unusedsingle-endedinputsmustbeheldhighorlowtopreventthemfromfloating.
(2)PCLKinputfrequencieslowerthan500kHzforcetheSN65LVDS311intostandbymode.
Inputfrequenciesbetween500kHzand3MHzmayormaynotactivatetheSN65LVDS311.
Inputfrequenciesbeyond3MHzactivatetheSN65LVDS311.
(3)Periodjitteristhedeviationincycletimeofasignalwithrespecttotheidealperiodoverarandomsampleof100,000cycles.
(4)Cycle-to-cyclejitteristhevariationincycletimeofasignalbetweenadjacentcycles;overarandomsampleof1,000adjacentcyclepairs.
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comDEVICEELECTRICALCHARACTERISTICSoverrecommendedoperatingconditions(unlessotherwisenoted)PARAMTESTCONDITIONSMINTYP(1)MAXUNITETERVDD=VDDPLLA=VDDPLLD=VDDLVDS,fPCLK=4MHz9.
011.
4RL(PCLK)=RL(D0)=100,VIH=VDD,VIL=0V,fPCLK=6MHz10.
612.
6mATXENatVDD,fPCLK=15MHz1618.
8alternating1010serialbitpattern1ChMVDD=VDDPLLA=VDDPLLD=VDDLVDS,fPCLK=4MHz8.
0RL(PCLK)=RL(D0)=100,VIH=VDD,VIL=0V,fPCLK=6MHz8.
9mATXENatVDD,fPCLK=15MHz14.
0typicalpowertestpattern(seeTable7)VDD=VDDPLLA=VDDPLLD=VDDLVDS,fPCLK=8MHz13.
715.
9RL(PCLK)=RL(Dx)=100,VIH=VDD,VIL=0V,fPCLK=22MHz18.
422.
0mATXENatVDD,fPCLK=30MHz21.
425.
8alternating1010serialbitpattern;2ChMVDD=VDDPLLA=VDDPLLD=VDDLVDS,fPCLK=8MHz11.
5RL(PCLK)=RL(D0)=100,VIH=VDD,VIL=0V,fPCLK=22MHz16.
0mATXENatVDD,IDDfPCLK=30MHz19.
1typicalpowertestpattern(seeTable8)VDD=VDDPLLA=VDDPLLD=VDDLVDS,fPCLK=20MHz20.
022.
5RL(PCLK)=RL(D0)=100,VIH=VDD,VIL=0V,fPCLK=65MHzmATXENatVDD,29.
136.
8alternating1010serialbitpattern3ChMVDD=VDDPLLA=VDDPLLD=VDDLVDS,fPCLK=20MHz15.
9RL(PCLK)=RL(D0)=100,VIH=VDD,VIL=0V,fPCLK=65MHzmATXENatVDD,24.
7typicalpowertestpattern(seeTable9)StandbyModeVDD=VDDPLLA=VDDPLLD0.
6110μA=VDDLVDS,RL(PCLK)=RL(D0)=100,VIH=VDD,VIL=0V,allShutdownMode0.
5510μAinputsheldstatichighorstaticlow(1)Alltypicalvaluesareat25°Candwith1.
8Vsupplyunlessotherwisenoted.
OUTPUTELECTRICALCHARACTERISTICSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYP(1)MAXUNITsubLVDSoutput(D0+,D0–,D1+,D1–,D2+,D1–,CLK+,andCLK–)VOCM(SS)Steady-statecommon-modeoutputvoltageOutputloadseeFigure80.
80.
91.
0VVOCM(SS)Changeinsteady-statecommon-modeoutputvoltage–1010mVVOCM(PP)Peak-to-peakcommonmodeoutputvoltage75mV|VOD|Differentialoutputvoltagemagnitude100150200mV|VDx+–VDx–|,|VCLK+–VCLK–|Δ|VOD|Changeindifferentialoutputvoltagebetweenlogicstates–1010mVZOD(CLK)Differentialsmall-signaloutputimpedanceTXENatVDD210IOSDDifferentialshort-circuitoutputcurrentVOD=0V,fPCLK=28MHz10mAIOSShortcircuitoutputcurrent(2)VO=0VorVDD5IOZHigh-impedancestateoutputcurrentVO=0VorVDD(max),–33μATXENatGND(1)Alltypicalvaluesareat25°Candwith1.
8Vsupplyunlessotherwisenoted.
(2)AllSN65LVDS311outputstolerateshortstoGNDorVDDwithoutpermanentdevicedamage.
10SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
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comSLLSE31B–MAY2010–REVISEDMARCH2013INPUTELECTRICALCHARACTERISTICSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYP(1)MAXUNITPCLK,R[0:7],G[0:7],B[0:7],VS,HS,DE,PCLK,LS[1:0],TXEN,SWAPIIHHigh-levelinputcurrentVIN=0.
7*VDD–200200nAIILLow-levelinputcurrentVIN=0.
3*VDD–200200CINInputcapacitance1.
5pF(1)Alltypicalvaluesareat25°Candwith1.
8Vsupplyunlessotherwisenoted.
SWITCHINGCHARACTERISTICSoverrecommendedoperatingconditions(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYP(1)MAXUNITtr20%-to-80%differentialSeeFigure7andFigure8250500outputsignalrisetimepstf20%-to-80%differentialSeeFigure7andFigure8250500outputsignalfalltimeTestedfromPCLKinputtofPCLK=22MHz0.
082*fPCLKPLLbandwidth(3dBcutofffBWMHzCLKoutput,SeeFigure5(2)frequency)fPCLK=65MHz0.
07*fPCLKtpd(L)Propagationdelaytime,TXENatVDD,VIH=VDD,1-channelmode0.
8/fPCLK1/fPCLK1.
2/fPCLKinputtoserialoutput(dataVIL=GND,RL=1002-channelmode1.
0/fPCLK1.
21/fPCLK1.
5/fPCLKslatencyFigure9)3-channelmode1.
1/fPCLK1.
31/fPCLK1.
6/fPCLKtH*fCLK0OutputCLKdutycycle1-channeland3-channel0.
450.
500.
55mode2-channelmode0.
490.
530.
58tGSTXENGlitchsuppressionVIH=VDD,VIL=GND,TXENtogglesbetweenVILandVIH,3.
810μspulsewidth(3)seeFigure12andFigure13tpwrupEnabletimefrompowerTimefromTXENpulledhightoCLKandDxoutputs0.
242msdown(↑TXEN)enabledandtransmitvaliddata;seeFigure13tpwrdnDisabletimefromactiveTXENispulledlowduringtransmitmode;time0.
511mode(↓TXEN)measurementuntiloutputisdisabledandPLLisShutdown;μsseeFigure13twakupEnabletimefromStandbyTXENatVDD;deviceinstandby;timemeasurementfrom0.
232(PCLK)PCLKstartsswitchingtoCLKandDxoutputsenabledandmstransmitvaliddata;seeFigure13tsleepDisabletimefromActiveTXENatVDD;deviceistransmitting;timemeasurement0.
4100mode(PCLKstopping)fromPCLKinputsignalstopsuntilCLK+DxoutputsareμsdisabledandPLLisdisabled;seeFigure13(1)Alltypicalvaluesareat25°Candwith1.
8Vsupplyunlessotherwisenoted.
(2)TheMaximumLimitisbasedonstatisticalanalysisofthedeviceperformanceoverprocess,voltage,andtempranges.
ThisparameterisfunctionalitytestedonlyonAutomaticTestEquipment(ATE).
(3)TheTXENinputincorporatesglitch-suppressioncircuitrytodisregardshortinputpulses.
tGSisthedurationofeitherahigh-to-loworlow-to-hightransitionthatissuppressed.
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comFigure5.
LVDS311PLLBandwidth(alsoshowingtheLVDS302PLLbandwidth)TIMINGCHARACTERISTICSPARAMETERTESTCONDITIONSMINTYPMAXUNIT1ChM:x=0.
.
29,fPCLK=15MHz;TXENatVDD,VIH=VDD,VIL=GND,RL=100,testpatternasinTable12(3)1ChM:x=0.
.
29,fPCLK=4MHzto15MHz(4)2ChM:x=0.
.
14,fPCLK=30MHzTXENatVDD,VIH=VDD,VIL=GND,OutputPulsePosition,RL=100,testpatternasinTable13(3)tPPOSXserialdatato↑CLK;seeps2ChM:x=0.
.
14,(1)(2)andFigure11fPCLK=8MHzto30MHz(4)3ChM:x=0.
.
9,fPCLK=65MHz,TXENatVDD,VIH=VDD,VIL=GND,RL=100,testpatternasinTable14(3)3ChM:x=0.
.
9,fPCLK=20MHzto65MHz(4)(1)Thisnumberalsoincludesthehigh-frequencyrandomanddeterministicPLLclockjitterthatisnottraceablebytheSN65LVDS302receiverPLL;tPPosxrepresentsthetotaltiminguncertaintyofthetransmitternecessarytocalculatethejitterbudgetwhencombinedwiththeSN65LVDS302receiver;(2)Thepulsepositionmin/maxvariationisgivenwithabiterrorratetargetof10–12;ThemeasurementestimatestherandomjittercontributiontothetotaljittercontributionbymultiplyingtherandomRMSjitterbythefactor14;Measurementsofthetotaljitteraretakenoverasampleamountof>10–12samples.
(3)TheMinimumandMaximumLimitsarebasedonstatisticalanalysisofthedeviceperformanceoverprocess,voltage,andtempranges.
ThisparameterisfunctionalitytestedonlyonAutomaticTestEquipment(ATE).
(4)TheseMinimumandMaximumLimitsaresimulatedonly.
12SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
ti.
comSLLSE31B–MAY2010–REVISEDMARCH2013PARAMETERMEASUREMENTINFORMATIONFigure6.
Setup/HoldTimeFigure7.
RiseandFallTimeDefinitionsFigure8.
DriverOutputVoltageTestCircuitandDefinitionsCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
ti.
comFigure9.
tpd(L)PropagationDelayInputtoOutput(LS0=LS1=0)Figure10.
PowerSupplyNoiseTestSet-UpFigure11.
tSK(0)SubLVDSOutputPulsePositionMeasurement14SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
ti.
comSLLSE31B–MAY2010–REVISEDMARCH2013Figure12.
TransmitterBehaviorWhileApproachingSyncFigure13.
TransmitterEnableGlitchSuppressionTimeFigure14.
StandbyDetectionPowerConsumptionTestsTable6showsanexampletestpatternword.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
ti.
comTable6.
ExampleTestPatternWordWordR[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10x7C3E1E77C3E1E7R7R6R5R4R3R2R1R0G7G6G5G4G3G2G1G0B7B6B5B4B3B2B1B00VSHSDE0111110000111110000111100111TypicalICPowerConsumptionTestPatternThetypicalpowerconsumptiontestpatternsconsistsofsixteen30-bittransmitwordsin1-channelmode,eight30-bittransmitwordsin2-channelmodeandfive30-bittransmitwordsin3-channelmode.
Thepatternrepeatsitselfthroughouttheentiremeasurement.
ItisassumedthateverypossibletransmitcodeonRGBinputshasthesameprobabilitytooccurduringtypicaldeviceoperation.
Table7.
TypicalICPowerConsumptionTestPattern,1-ChannelModeWordTestPattern:R[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10x000000720xFFF000730x01FFF4740xF0E07F750x7C3E1E760xE707C3770xE1CE6C780xF1B923790x91BB347100xD4CCC67110xAD53377120xACB2207130xAAB2697140x5556957150xAAAAAB3160xAAAAAA516SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
ti.
comSLLSE31B–MAY2010–REVISEDMARCH2013Table8.
TypicalICPowerConsumptionTestPattern,2-ChannelModeWordTestPattern:R[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10x000000120x03F03F130xBFFBFF140x1D71D7150x4C74C7160xC45C45170xA3aA3A580x5555553Table9.
TypicalICPowerConsumptionTestPattern,3-ChannelModeWordTestPattern:R[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10xFFFFFF120x000000130xF0F0F0140xCCCCCC150xAAAAAA7MaximumPowerConsumptionTestPatternThemaximum(orworst-case)powerconsumptionoftheSN65LVDS311istestedusingthetwodifferenttestpatternsshowninTable10andTable11.
Thetestpatternsconsistofsixteen30-bittransmitwordsin1-channelmode,eight30-bittransmitwordsin2-channelmodeandfive30-bittransmitwordsin3-channelmode.
Thepatternrepeatsitselfthroughouttheentiremeasurement.
ItisassumedthateverypossibletransmitcodeonRGBinputshasthesameprobabilitytooccurduringtypicaldeviceoperation.
Table10.
Worst-CasePowerConsumptionTestPatternWordTestPattern:R[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10xAAAAAA520x5555555Table11.
Worst-CasePowerConsumptionTestPatternWordTestPattern:R[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10x000000020xFFFFFF7Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
ti.
comOutputSkewPulsePosition&JitterPerformanceThefollowingtestpatternsareusedtomeasuretheoutput-skewpulsepositionandthejitterperformanceoftheSN65LVDS311.
Thejittertestpatternstressestheinterconnect,particularlytotestforISI.
Verylongrun-lengthsofconsecutivebitsincorporateveryhighandlowdatarates,maximingesswitchingnoise.
Eachpatternisself-repeatingforthedurationofthetest.
Table12.
TransmitJitterTestPattern,1-ChannelModeWordTestPattern:R[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10x000000120x000003130x00000F140x00003F150x0000FF160x0003FF170x000FFF180x0F0F0F190x0C30C31100x0842111110x1C71C71120x18C6311130x1111111140x3333331150x2452413160x22A2A25170x5555553180xDB6DB65190xCCCCCC1200xEEEEEE1210xE739CE1220xE38E381230xF7BDEE1240xF3CF3C1250xF0F0F01260xFFF0001270xFFFC001280xFFFF001290xFFFFC01300xFFFFF01310xFFFFFC1320xFFFFFF118SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
ti.
comSLLSE31B–MAY2010–REVISEDMARCH2013Table13.
TransmitJitterTestPattern,2-ChannelModeWordTestPattern:R[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10x000000120x000FFF330x800800140x003003750xE00E00160x00FF00170x007E00180x003C00190x0018001100x1C7E381110x3333331120x555AAA5130x6DBDB61140x7777771150x555AAA3160xAAAAAA5170x5555553180xAAA5555190x8888881200x9242491210xAAA5571220xCCCCCC1230xE3E1C71240xFFE7FF1250xFFC3FF1260xFF81FF1270xFE00FF1280x1FF1FF1290xFFCFFC3300x7FF7FF1310xFFF0007320xFFFFFF1Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
ti.
comTable14.
TransmitJitterTestPattern,3-ChannelModeWordTestPattern:R[7:4],R[3:0],G[7:4],G[3:0],B[7-4],B[3-0],0,VS,HS,DE10x000000120x000000130x000000340x010101350x030303360x070707370x181818380xE7E7E7190x3535351100x0202021110x5454543120xA5A5A51130xADADAD1140x5555551150xA6A2AA3160xA6A2AA5170x5555553180x5555555190xAAAAAA1200x5252521210x5A5A5A1220xABABAB1230xFDFCFD1240xCAAACA1250x1818181260xE7E7E71270xF8F8F81280xFCFCFC1290xFEFEFE1300xFFFFFF1310xFFFFFF5320xFFFFFF520SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
ti.
comSLLSE31B–MAY2010–REVISEDMARCH2013TYPICALCHARACTERISTICSPOWERDOWN,STANDBYSUPPLYCURRENTSUPPLYCURRENTIDDvsvsTEMPERATURETEMPERATUREFigure15.
Figure16.
SUPPLYCURRENTDIFFERENTIALOUTPUTSWINGvsvsPCLKFREQUENCYPCLKFREQUENCYFigure17.
Figure18.
CYCLE-TO-CYCLEOUTPUTJITTERvsPLLBANDWIDTHPCLKFREQUENCYFigure19.
Figure20.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
ti.
comTYPICALCHARACTERISTICS(continued)CYCLE-TO-CYCLEOUTPUTJITTEROUTPUTPULSEPOSITIONvsvsTEMPERATURETEMPERATUREFigure21.
Figure22.
DATAEYEPATTERN,2-CHANNELMODEDATAEYEPATTERN,3-CHANNELMODEFigure23.
Figure24.
QVGAOUTPUTWAVEFORMVGA2-CHANNELOUTPUTWAVEFORMFigure25.
Figure26.
22SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
ti.
comSLLSE31B–MAY2010–REVISEDMARCH2013TYPICALCHARACTERISTICS(continued)VGA2-CHANNELOUTPUTWAVEFORMVGA3-CHANNELOUTPUTWAVEFORMFigure27.
Figure28.
XGA3-CHANNELOUTPUTWAVEFORMONTHEXGA3-CHANNELOUTPUTWAVEFORMSN65LVDS302WHENDRIVENBYTHESN65LVDS311Figure29.
Figure30.
PLLPHASENOISEOUTPUTRETURNLOSSFigure31.
Figure32.
Copyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
ti.
comTYPICALCHARACTERISTICS(continued)OUTPUTCOMMONMODENOISEREJECTIONCROSSTALKFigure33.
Figure34.
GTEMSAEJ1752/3EMITESTFigure35.
A.
Figure35showsasuperimposedimageofthreeEMImeasurementswiththedeviceoperatingatf(PCLK)=5MHz,f(PCLK)=22MHz,andf(PCLK)=65MHz.
ThisexcellentEMIperformancemeetsthesystemrequirementsofdense,mobiledesignswithanoisefloorof~2dBV(-105dBm)andallspursbeingsmallerthan16dBV(-101dBm).
ThetestwasperformedincompliancewiththeSAEJ1752/3EMItestguidelines.
24SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
ti.
comSLLSE31B–MAY2010–REVISEDMARCH2013APPLICATIONINFORMATIONPreventingIncreasedLeakageCurrentsinControlInputsAfloating(leftopen)CMOSinputallowsleakagecurrentstoflowfromVDDtoGND.
DonotleaveanyCMOSInputunconnectedorfloating.
EveryinputmustbeconnectedtoavalidlogiclevelVIHorVOLwhilepowerissuppliedtoVDD.
Thisalsominimizesthepowerconsumptionofstandbyandpowerdownmode.
PowerSupplyDesignRecommendationForamultilayerpcb,itisrecommendedtokeeponecommonGNDlayerunderneaththedeviceandconnectallgroundterminalsdirectlytothisplane.
DecouplingRecommendationTheSN65LVDS311wasdesignedtooperatereliablyinaconstrictedenvironmentwithotherdigitalswitchingICs.
Inmanydesigns,theSN65LVDS311oftensharesapowersupplywiththeapplicationprocessor.
TheSN65LVDS311canoperatewithpowersupplynoiseasspecifiedinRecommendDeviceOperatingConditions.
Tominimizethepowersupplynoisefloor,providegooddecouplingneartheSN65LVDS311powerpins.
Theuseoffourceramiccapacitors(2*0.
01μFand2*0.
1μF)providesgoodperformance.
Attheveryleast,itisrecommendedtoinstallone0.
1μFandone0.
01μFcapacitorneartheSN65LVDS311.
Toavoidlargecurrentloopsandtraceinductance,thetracelengthbetweendecouplingcapacitorandICpowerinputspinsmustbeminimized.
PlacingthecapacitorunderneaththeSN65LVDS311onthebottomofthepcbisoftenagoodchoice.
VGAApplicationFigure36showsapossibleimplementationofaVGAdisplay.
TheLVDS311interfacesdirectlytoaLCDdriverwithintegratedFlatLink3Greceiver.
TheSPIinterfaceisusedtoconfigurethedisplay.
Thepixelclockrateof22MHzassumes≈10%blankingoverheadand60Hzdisplayrefreshrate.
Theapplicationassumes24-bitcolorresolution.
Figure36.
TypicalVGADisplayApplicationCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25ProductFolderLinks:SN65LVDS311SN65LVDS311SLLSE31B–MAY2010–REVISEDMARCH2013www.
ti.
comDualLCD-DisplayApplicationTheexampleinFigure37showsapossibleapplicationsetupdrivingtwovideomodedisplaysfromoneapplicationprocessor.
Thedatarateof330Mbpsatapixelclockrateof5.
5MHzcorrespondstoQVGAresolutionat60Hzrefreshrateand10%blankingoverhead.
Figure37.
ExampleDual-QVGADisplayApplicationTypicalApplicationFrequenciesTheSN65LVDS311supportspixelclockfrequenciesfrom4MHzto65MHzover1,2,or3datalanes.
Table15providesafewtypicaldisplayresolutionexamplesandshowsthenumberofdatalanesnecessarytoconnecttheLVDS311withthedisplay.
Theblankingoverheadisassumedtobe20%.
Often,blankingoverheadissmaller,resultinginalowerdatarate.
Furthermore,theexamplesinthetableassumesadisplayframerefreshrateof60Hzor90Hz.
Theactualrefreshratemaydifferdependingontheapplication-processorclockimplementation.
Table15.
TypicalApplicationDataRates&SerialLaneUsageDisplayScreenVisibleBlankingDisplayPixelClockFrequencySerialDataRatePerLaneResolutionPixelCountOverheadRefresh[MHz]1-ChM2-ChM3-ChMRate176x220(QCIF+)38,72020%90Hz4.
2MHz125Mbps240x320(QVGA)76,80060Hz5.
5MHz166Mbps640x200128,0009.
2MHz276Mbps138Mbps352x416(CIF+)146,43210.
5MHz316Mbps158Mbps352x440154,88011.
2MHz335Mbps167Mbps320x480(HVGA)153,60011.
1MHz332Mbps166Mbps800x250200,00014.
4MHz432Mbps216Mbps640x320204,80014.
7MHz442Mbps221Mbps640x480(VGA)307,20022.
1MHz332Mbps221Mbps1024x320327,68023.
6MHz354Mbps236Mbps854x480(WVGA)409,92029.
5MHz443Mbps295Mbps800x600(SVGA)480,00034.
6MHz346Mbps1024x768(XGA)786,43256.
6MHz566Mbps26SubmitDocumentationFeedbackCopyright2010–2013,TexasInstrumentsIncorporatedProductFolderLinks:SN65LVDS311SN65LVDS311www.
ti.
comSLLSE31B–MAY2010–REVISEDMARCH2013CalculationExample:HVGADisplayThisexamplecalculationshowsatypicalHalf-VGAdisplaywiththeseparameters:DisplayResolution:480x320FrameRefreshRate:58.
4HzHorizontalVisiblePixel:480columnsHorizontalFrontPorch:20columnsHorizontalSync:5columnsHorizontalBackPorch:3columnsVerticalVisiblePixel:320linesVerticalFrontPorch:10linesVerticalSync:5linesVerticalBackPorch:3linesFigure38.
HVGADisplayParametersCalculationofthetotalnumberofpixelandBlankingoverhead:VisibleAreaPixelCount:480*320=153600pixelTotalFramePixelCount:(480+20+5+3)*(320+10+5+3)=171704pixelBlankingOverhead:(171704-153600)÷153600=11.
8%Theapplicationrequiresfollowingserial-linkparameters:PixelClkFrequency:171704*58.
4Hz=10.
0MHzSerialDataRate:1-channelmode:10.
0MHz*30bit/channel=300Mbps2-channelmode:10.
0MHz*15bit/channel=150MbpsCopyright2010–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback27ProductFolderLinks:SN65LVDS311PACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesSN65LVDS311YFFRACTIVEDSBGAYFF493000RoHS&GreenSNAGCULevel-1-260C-UNLIM-40to85LVDS311SN65LVDS311YFFTACTIVEDSBGAYFF49250RoHS&GreenSNAGCULevel-1-260C-UNLIM-40to85LVDS311(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
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42.
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930.
814.
08.
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0182.
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