extrapoz8nrd12

REV.
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AD7866Dual1MSPS,12-Bit,2-ChannelSARADCwithSerialInterfaceFEATURESDual12-Bit,2-ChannelADCFastThroughputRate:1MSPSSpecifiedforVDDof2.
7Vto5.
25VLowPower11.
4mWMaxat1MSPSwith3VSupplies24mWMaxat1MSPSwith5VSuppliesWideInputBandwidth70dBSNRat300kHzInputFrequencyOn-BoardReference2.
5V–40Cto+125COperationFlexiblePower/ThroughputRateManagementSimultaneousConversion/ReadNoPipelineDelaysHighSpeedSerialInterfaceSPITM/QSPITM/MICROWIRETM/DSPCompatibleShutdownMode:1AMax20-LeadTSSOPPackageFUNCTIONALBLOCKDIAGRAMVA2VA1DGNDDOUTAREFSELECTVREFA012-BITSUCCESSIVEAPPROXIMATIONADCAD78662.
5VREFT/HMUXBUFOUTPUTDRIVERSRANGESCLKCSCONTROLLOGICVB2VB1DOUTB12-BITSUCCESSIVEAPPROXIMATIONADCT/HMUXOUTPUTDRIVERSBUFDCAPAAVDDDVDDDCAPBAGNDAGNDVDRIVEGENERALDESCRIPTIONTheAD7866isadual12-bithighspeed,lowpower,successiveapproximationADC.
Thepartoperatesfromasingle2.
7Vto5.
25Vpowersupplyandfeaturesthroughputratesupto1MSPS.
ThedevicecontainstwoADCs,eachprecededbyalownoise,widebandwidthtrack-and-holdamplifierthatcanhandleinputfrequenciesinexcessof10MHz.
Theconversionprocessanddataacquisitionarecontrolledusingstandardcontrolinputs,allowingeasyinterfacingtomicroprocessorsorDSPs.
TheinputsignalissampledonthefallingedgeofCS;conversionisalsoinitiatedatthispoint.
TheconversiontimeisdeterminedbytheSCLKfrequency.
Therearenopipelineddelaysassociatedwiththepart.
TheAD7866usesadvanceddesigntechniquestoachieveverylowpowerdissipationathighthroughputrates.
With3Vsuppliesand1MSPSthroughputrate,thepartconsumesamaximumof3.
8mA.
With5Vsuppliesand1MSPS,thecurrentconsumptionisamaximumof4.
8mA.
Thepartalsooffersflexiblepower/throughputratemanagementwhenoperatinginsleepmode.
Theanaloginputrangeforthepartcanbeselectedtobea0VtoVREFrangeora2VREFrangewitheitherstraightbinaryortwoscomplementoutputcoding.
TheAD7866hasanon-chip2.
5Vreferencethatcanbeoverdrivenifanexternalreferenceispreferred.
Eachon-boardADCcanalsobesuppliedwithaseparateindividualexternalreference.
TheAD7866isavailableina20-leadthinshrinksmalloutline(TSSOP)package.
PRODUCTHIGHLIGHTS1.
TheAD7866featurestwocompleteADCfunctions,allowingsimultaneoussamplingandconversionoftwochannels.
EachADChasa2-channelinputmultiplexer.
Theconversionresultofbothchannelsisavailablesimultaneouslyonseparatedatalines,ormaybetakenononedatalineifonlyoneserialportisavailable.
2.
HighThroughputwithLowPowerConsumption—TheAD7866offersa1MSPSthroughputratewith11.
4mWmaximumpowerconsumptionwhenoperatingat3V.
3.
FlexiblePower/ThroughputRateManagement—Theconver-sionrateisdeterminedbytheserialclock,allowingthepowerconsumptiontobereducedastheconversiontimeisreducedthroughaSCLKfrequencyincrease.
Powerefficiencycanbemaximizedatlowerthroughputratesifthepartenterssleepduringconversions.
4.
NoPipelineDelay—ThepartfeaturestwostandardsuccessiveapproximationADCswithaccuratecontrolofthesamplinginstantviaaCSinputandonceoffconversioncontrol.
AD7866*PRODUCTPAGEQUICKLINKSLastContentUpdate:02/23/2017COMPARABLEPARTSViewaparametricsearchofcomparableparts.
EVALUATIONKITSAD7866EvaluationBoardDOCUMENTATIONDataSheetAD7866:Dual1MSPS,12-Bit,2-ChannelSARADCwithSerialInterfaceDataSheetTOOLSANDSIMULATIONSAD7866IBISModelREFERENCEDESIGNSCN0323CN0341CN0368REFERENCEMATERIALSTechnicalArticlesMS-2210:DesigningPowerSuppliesforHighSpeedADCDESIGNRESOURCESAD7866MaterialDeclarationPCN-PDNInformationQualityAndReliabilitySymbolsandFootprintsDISCUSSIONSViewallAD7866EngineerZoneDiscussions.
SAMPLEANDBUYVisittheproductpagetoseepricingoptions.
TECHNICALSUPPORTSubmitatechnicalquestionorfindyourregionalsupportnumber.
DOCUMENTFEEDBACKSubmitfeedbackforthisdatasheet.
ThispageisdynamicallygeneratedbyAnalogDevices,Inc.
,andinsertedintothisdatasheet.
Adynamicchangetothecontentonthispagewillnottriggerachangetoeithertherevisionnumberorthecontentoftheproductdatasheet.
Thisdynamicpagemaybefrequentlymodified.
REV.
A–2–AD7866–SPECIFICATIONS(TA=TMINtoTMAX,VDD=2.
7Vto5.
25V,VDRIVE=2.
7Vto5.
25V,Reference=2.
5VExternalonDCAPAandDCAPB,fSCLK=20MHz,unlessotherwisenoted.
)ParameterAVersion1BVersion1UnitTestConditions/CommentsDYNAMICPERFORMANCESignaltoNoise+Distortion(SINAD)26868dBminfIN=300kHzSineWave,fS=1MSPSTotalHarmonicDistortion(THD)2–75–75dBmaxfIN=300kHzSineWave,fS=1MSPSPeakHarmonicorSpuriousNoise(SFDR)2–76–76dBmaxfIN=300kHzSineWave,fS=1MSPSIntermodulationDistortion(IMD)2SecondOrderTerms–88–88dBtypThirdOrderTerms–88–88dBtypChannel-to-ChannelIsolation–88–88dBtypSAMPLEANDHOLDApertureDelay31010nsmaxApertureJitter35050pstypApertureDelayMatching3200200psmaxFullPowerBandwidth1212MHztyp@3dB22MHztyp@0.
1dBDCACCURACYResolution1212BitsIntegralNonlinearity±1.
5±1LSBmaxBGrade,0VtoVREFRangeOnly;±0.
5LSBtyp±1.
5LSBmax0Vto2VREFRange;±0.
5LSBtypDifferentialNonlinearity–0.
95/+1.
25–0.
95/+1.
25LSBmaxGuaranteedNoMissedCodesto12Bits0VtoVREFInputRangeStraightBinaryOutputCodingOffsetError±8±8LSBmaxOffsetErrorMatch±1.
2±1.
2LSBtypGainError±2.
5±2.
5LSBmaxGainErrorMatch±0.
2±0.
2LSBtyp2VREFInputRange–VREFto+VREFBiasedaboutVREFwithPositiveGainError±2.
5±2.
5LSBmaxTwosComplementOutputCodingZeroCodeError±8±8LSBmaxZeroCodeErrorMatch±0.
2±0.
2LSBtypNegativeGainError±2.
5±2.
5LSBmaxANALOGINPUTInputVoltageRanges0toVREF0toVREFVRANGEPinLowuponCSFallingEdge0to2VREF0to2VREFVRANGEPinHighuponCSFallingEdgeDCLeakageCurrent±500±500nAmaxTA=–40Cto+85C11Amax85C52.
5V±1%forSpecifiedPerformanceReferenceInputVoltageRange42/32/3Vmin/VmaxREFSELECTPinTiedHighDCLeakageCurrent±30±30AmaxVREFPin±160±160AmaxDCAPA,DCAPBPinsInputCapacitance2020pFtypReferenceOutputVoltage52.
45/2.
552.
45/2.
55Vmin/VmaxVREFOutputImpedance62525typVDD=5V4545typVDD=3VReferenceTemperatureCoefficient5050ppm/°CtypREFOUTError(TMINtoTMAX)±15±15mVtypLOGICINPUTSInputHighVoltage,VINH0.
7VDRIVE0.
7VDRIVEVminInputLowVoltage,VINL0.
3VDRIVE0.
3VDRIVEVmaxInputCurrent,IIN±1±1AmaxTypically15nA,VIN=0VorVDRIVEInputCapacitance,CIN31010pFmaxLOGICOUTPUTSOutputHighVoltage,VOHVDRIVE–0.
2VDRIVE–0.
2VminISOURCE=200AOutputLowVoltage,VOL0.
40.
4VmaxISINK=200AFloating-StateLeakageCurrent±1±1AmaxVDD=2.
7Vto5.
25VFloating-StateOutputCapacitance31010pFmaxOutputCodingStraight(Natural)BinarySelectablewithEitherInputRangeTwosComplementREV.
AAD7866–3–ParameterAVersion1BVersion1UnitTestConditions/CommentsCONVERSIONRATEConversionTime1616SCLKcycles800nswithSCLK=20MHzTrack/HoldAcquisitionTime3300300nsmaxThroughputRate11MSPSmaxSeeSerialInterfaceSectionPOWERREQUIREMENTSVDD2.
7/5.
252.
7/5.
25Vmin/maxVDRIVE2.
7/5.
252.
7/5.
25Vmin/maxIDD7DigitalI/Ps=0VorVDRIVENormalMode(Static)3.
13.
1mAmaxVDD=4.
75Vto5.
25V.
Add0.
5mATypicalifUsingInternalReference.
2.
82.
8mAmaxVDD=2.
7Vto3.
6V.
Add0.
35mATypicalifUsingInternalReference.
Operational,fS=1MSPS4.
84.
8mAmaxVDD=4.
75Vto5.
25V.
Add0.
5mATypicalifUsingInternalReference.
3.
83.
8mAmaxVDD=2.
7Vto3.
6V.
Add0.
5mATypicalifUsingInternalReference.
PartialPower-DownMode1.
61.
6mAmaxfS=100kSPS,fSCLK=20MHzAdd0.
2mATypifUsingInternalReference.
PartialPower-DownMode560560Amax(Static)Add100ATypicalifUsingInternalReference.
FullPower-DownMode11AmaxSCLKOnorOff.
TA=–40Cto+85C22AmaxSCLKOnorOff.
85C411.
4mWmaxVDD=3VPartialPower-Down(Static)2.
82.
8mWmaxVDD=5V.
SCLKOnorOff.
1.
681.
68mWmaxVDD=3V.
SCLKOnorOff.
FullPower-Down(Static)55WmaxVDD=5V.
SCLKOnorOff.
33WmaxVDD=3V.
SCLKOnorOff.
NOTES1Temperaturerangesasfollows:A,BVersions:–40°Cto+125°C.
2SeeTerminologysection.
3Sampletested@25°Ctoensurecompliance.
4ExternalreferencerangethatmaybeappliedatVREF,DCAPA,orDCAPB.
5RelatestopinsVREF,DCAPA,orDCAPB.
6SeeReferencesectionforDCAPA,DCAPBoutputimpedances.
7SeePowervs.
ThroughputRatesection.
Specificationssubjecttochangewithoutnotice.
REV.
A–4–AD7866TIMINGSPECIFICATIONS1(VDD=2.
7Vto5.
25V,VDRIVE=2.
7Vto5.
25V,VREF=2.
5V;TA=TMINtoTMAX,unlessotherwisenoted.
)LimitatParameterTMIN,TMAXUnitDescriptionfSCLK210kHzmin20MHzmaxtCONVERT16tSCLKnsmaxtSCLK=1/fSCLK800nsmaxfSCLK=20MHztQUIET50nsmaxMinimumTimebetweenEndofSerialReadandNextFallingEdgeofCSt210nsminCStoSCLKSetupTimet3325nsmaxDelayfromCSuntilDOUTAandDOUTBThree-StateDisabledt4340nsmaxDataAccessTimeafterSCLKFallingEdge.
VDRIVE3V,CL=50pF;VDRIVE<3V,CL=25pFt50.
4tSCLKnsminSCLKLowPulsewidtht60.
4tSCLKnsminSCLKHighPulsewidtht710nsminSCLKtoDataValidHoldTimet8425nsmaxCSRisingEdgetoDOUTA,DOUTB,HighImpedancet9410nsminSCLKFallingEdgetoDOUTA,DOUTB,HighImpedance50nsmaxSCLKFallingEdgetoDOUTA,DOUTB,HighImpedanceNOTES1Sampletestedat25°Ctoensurecompliance.
AllinputsignalsarespecifiedwithtR=tF=5ns(10%to90%ofVDRIVE)andtimedfromavoltagelevelof1.
6V.
2Mark/SpaceratiofortheCLKinputis40/60to60/40.
3MeasuredwiththeloadcircuitofFigure1anddefinedasthetimerequiredfortheoutputtocross0.
8Vor2.
0V.
4t8,t9arederivedfromthemeasuredtimetakenbythedataoutputstochange0.
5VwhenloadedwiththecircuitofFigure1.
Themeasurednumberisthenextrapo-latedbacktoremovetheeffectsofchargingordischargingthe50pFcapacitor.
Thismeansthatthetimest8andt9quotedinthetimingcharacteristicsarethetruebusrelinquishtimesofthepartandareindependentofthebusloading.
Specificationssubjecttochangewithoutnotice.
1.
6V200AIOL200AIOHCL50pFTOOUTPUTPINFigure1.
LoadCircuitforDigitalOutputTimingSpecificationsREV.
AAD7866–5–ORDERINGGUIDEResolutionPackageModelTemperatureRange(Bits)PackageDescriptionOptionAD7866ARU–40°Cto+125°C12ThinShrinkSOC(TSSOP)RU-20AD7866BRU–40°Cto+125°C12ThinShrinkSOC(TSSOP)RU-20EVAL-AD7866CB1EvaluationBoardEVAL-CONTROLBRD22ControllerBoardNOTES1Thiscanbeusedasastandaloneevaluationboardorinconjunctionwiththeevaluationboardcontrollerforevaluation/demonstrationpurposes.
2Thisevaluationboardcontrollerisacompleteunit,allowingaPCtocontrolandcommunicatewithallAnalogDevicesevaluationboardsendingintheCBdesignators.
Toorderacompleteevaluationkit,theparticularADCevaluationboard,e.
g.
,EVAL-AD7866CB,theEVAL-CONTROLBRD2,anda12Vtransformermustbeordered.
SeerelevantEvaluationBoardTechnicalnoteformoreinformation.
ABSOLUTEMAXIMUMRATINGS1(TA=25oC,unlessotherwisenoted.
)AVDDtoAGND0.
3Vto+7VDVDDtoDGND0.
3Vto+7VVDRIVEtoDGND0.
3VtoDVDD+0.
3VVDRIVEtoAGND0.
3VtoAVDD+0.
3VAVDDtoDVDD0.
3Vto+0.
3VAGNDtoDGND0.
3Vto+0.
3VAnalogInputVoltagetoAGND0.
3VtoAVDD+0.
3VDigitalInputVoltagetoDGND0.
3Vto+7VVREFtoAGND0.
3VtoAVDD+0.
3VDigitalOutputVoltagetoDGND.
.
.
–0.
3VtoVDRIVE+0.
3VInputCurrenttoAnyPinExceptSupplies210mAOperatingTemperatureRangeCommercial(A,BVersions)40Cto+125CStorageTemperatureRange65Cto+150CJunctionTemperature150CTSSOPPackage,PowerDissipation450mWJAThermalImpedance(TSSOP)143C/WJCThermalImpedance(TSSOP)45C/WLeadTemperature,SolderingVaporPhase(60sec)215CInfrared(15sec)220CESD1.
5kVNOTES1StressesabovethoselistedunderAbsoluteMaximumRatingsmaycauseperma-nentdamagetothedevice.
Thisisastressratingonly;functionaloperationofthedeviceattheseoranyotherconditionsabovethoselistedintheoperationalsectionsofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
2Transientcurrentsofupto100mAwillnotcauseSCRlatchup.
CAUTIONESD(electrostaticdischarge)sensitivedevice.
Electrostaticchargesashighas4000Vreadilyaccumulateonthehumanbodyandtestequipmentandcandischargewithoutdetection.
AlthoughtheAD7866featuresproprietaryESDprotectioncircuitry,permanentdamagemayoccurondevicessubjectedtohighenergyelectrostaticdischarges.
Therefore,properESDprecautionsarerecommendedtoavoidperformancedegradationorlossoffunctionality.
REV.
A–6–AD7866PINCONFIGURATIONTOPVIEW(NottoScale)2019181716151413121112345678910AD7866REFSELECTA0DCAPBAGNDVB2VB1VA2VA1AGNDDCAPAVREFCSSCLKVDRIVEDOUTBDOUTADGNDDVDDAVDDRANGEPINFUNCTIONDESCRIPTIONSPinNo.
MnemonicFunction1REFSELECTInternal/ExternalReferenceSelection.
Logicinput.
IfthispinistiedtoGND,theon-chip2.
5VreferenceisusedasthereferencesourceforbothADCAandADCB.
Inaddition,pinsVREF,DCAPA,andDCAPBmustbetiedtodecouplingcapacitors.
IftheREFSELECTpinistiedtoalogichigh,anexternalrefer-encecanbesuppliedtotheAD7866throughtheVREFpin,inwhichcasedecouplingcapacitorsarerequiredonDCAPAandDCAPB.
However,iftheVREFpinistiedtoAGNDwhileREFSELECTistiedtoalogiclow,anindividualexternalreferencecanbeappliedtobothADCAandADCBthroughpinsDCAPAandDCAPB,respectively.
SeetheReferenceConfigurationOptionssection.
2,9DCAPB,DCAPADecouplingcapacitorsareconnectedtothesepinstodecouplethereferencebufferforeachrespectiveADC.
Theon-chipreferencecanbetakenfromthesepinsandappliedexternallytotherestofasystem.
DependingonthepolarityoftheREFSELECTpinandtheconfigurationoftheVREFpin,thesepinscanalsobeusedtoinputaseparateexternalreferencetoeachADC.
Therangeoftheexternalreferenceisdependentontheanaloginputrangeselected.
SeetheReferenceConfigurationOptionssection.
3,8AGNDAnalogGround.
GroundreferencepointforallanalogcircuitryontheAD7866.
AllanaloginputsignalsandanyexternalreferencesignalshouldbereferredtothisAGNDvoltage.
BothofthesepinsshouldconnecttotheAGNDplaneofasystem.
TheAGNDandDGNDvoltagesideallyshouldbeatthesamepotentialandmustnotbemorethan0.
3Vapart,evenonatransientbasis.
4,5VB2,VB1AnalogInputsofADCB.
Single-endedanaloginputchannels.
Theinputrangeoneachchannelis0VtoVREFora2VREFrangedependingonthepolarityoftheRANGEpinuponthefallingedgeofCS.
6,7VA2,VA1AnalogInputsofADCA.
Single-endedanaloginputchannels.
Theinputrangeoneachchannelis0VtoVREFora2VREFrangedependingonthepolarityoftheRANGEpinuponthefallingedgeofCS.
10VREFReferenceDecouplingandExternalReferenceSelection.
Thispinisconnectedtotheinternalreferenceandrequiresadecouplingcapacitor.
Thenominalreferencevoltageis2.
5V,whichappearsatthepin;however,iftheinternalreferenceistobeusedexternallyinasystem,itmustbetakenfromeithertheDCAPAorDCAPBpins.
ThispinisalsousedinconjunctionwiththeREFSELECTpinwhenapplyinganexternalreferencetotheAD7866.
SeetheREFSELECTpindescription.
REV.
AAD7866–7–PINFUNCTIONDESCRIPTIONS(continued)PinNo.
MnemonicFunction11RANGEAnalogInputRangeandOutputCodingSelection.
Logicinput.
ThepolarityonthispinwilldeterminewhatinputrangetheanaloginputchannelsontheAD7866willhave,andwillalsoselectthetypeofoutputcodingtheADCwillusefortheconversionresult.
OnthefallingedgeofCS,thepolarityofthispinischeckedtodeterminetheanaloginputrangeofthenextconversion.
Ifthispinistiedtoalogiclow,theanaloginputrangeis0VtoVREFandtheoutputcodingfromthepartwillbestraightbinary(forthenextconversion).
IfthispinistiedtoalogichighwhenCSgoeslow,theanaloginputrangeis2VREFandtheoutputcodingforthepartwillbetwoscomplement.
How-ever,ifafterthefallingedgeofCSthelogicleveloftheRANGEpinhaschangedupontheeighthSCLKfallingedge,theoutputcodingwillchangetotheotheroptionwithoutanychangeintheanaloginputrange.
(SeetheAnalogInputandADCTransferFunctionsections.
)12AVDDAnalogSupplyVoltage,2.
7Vto5.
25V.
ThisistheonlysupplyvoltageforallanalogcircuitryontheAD7866.
TheAVDDandDVDDvoltagesideallyshouldbeatthesamepotentialandmustnotbemorethan0.
3Vapartevenonatransientbasis.
ThissupplyshouldbedecoupledtoAGND.
13DVDDDigitalSupplyVoltage,2.
7Vto5.
25V.
ThisisthesupplyvoltageforalldigitalcircuitryontheAD7866.
TheDVDDandAVDDvoltagesshouldideallybeatthesamepotentialandmustnotbemorethan0.
3Vapartevenonatransientbasis.
ThissupplyshouldbedecoupledtoDGND.
14DGNDDigitalGround.
ThisisthegroundreferencepointforalldigitalcircuitryontheAD7866.
TheDGNDandAGNDvoltagesideallyshouldbeatthesamepotentialandmustnotbemorethan0.
3Vapartevenonatransientbasis.
15,16DOUTA,DOUTBSerialDataOutputs.
Thedataoutputissuppliedtothispinasaserialdatastream.
ThebitsareclockedoutonthefallingedgeoftheSCLKinput.
ThedataappearsonbothpinssimultaneouslyfromthesimultaneousconversionsofbothADCs.
ThedatastreamconsistsofoneleadingzerofollowedbythreeSTATUSbits,followedbythe12bitsofconversiondata.
ThedataisprovidedMSBfirst.
IfCSisheldlowforanother16SCLKcyclesaftertheconversiondatahasbeenoutputoneitherDOUTAorDOUTB,thedatafromtheotherADCfollowsontheDOUTpin.
ThisallowsdatafromasimultaneousconversiononbothADCstobegatheredinserialformatoneitherDOUTAorDOUTBaloneusingonlyoneserialport.
SeetheSerialInterfacesection.
17VDRIVELogicPowerSupplyInput.
Thevoltagesuppliedatthispindeterminesatwhatvoltagetheinterfacewilloperate.
ThispinshouldbedecoupledtoDGND.
18SCLKSerialClock.
LogicInput.
AserialclockinputprovidestheSCLKforaccessingthedatafromtheAD7866.
Thisclockisalsousedastheclocksourcefortheconversionprocess.
19CSChipSelect.
Activelowlogicinput.
ThisinputprovidesthedualfunctionofinitiatingconversionsontheAD7866andframestheserialdatatransfer.
20A0MultiplexerSelect.
Logicinput.
Thisinputisusedtoselectthepairofchannelstobeconvertedsimultaneously,i.
e.
,Channel1ofbothADCAandADCB,orChannel2ofbothADCAandADCB.
ThelogicstateofthispinischeckeduponthefallingedgeofCS,andthemultiplexerissetupforthenextconversion.
Ifitislow,thefollowingconversionwillbeperformedonChannel1ofeachADC;ifitishigh,thefollowingconversionwillbeperformedonChannel2ofeachADC.
REV.
A–8–AD7866TERMINOLOGYIntegralNonlinearityThisisthemaximumdeviationfromastraightlinepassingthroughtheendpointsoftheADCtransferfunction.
Theendpointsofthetransferfunctionarezeroscale,apoint1LSBbelowthefirstcodetransition,andfullscale,apoint1LSBabovethelastcodetransition.
DifferentialNonlinearityThisisthedifferencebetweenthemeasuredandtheideal1LSBchangebetweenanytwoadjacentcodesintheADC.
OffsetErrorThisappliestoStraightBinaryoutputcoding.
Itisthedeviationofthefirstcodetransition(00.
.
.
000)to(00.
.
.
001)fromtheideal,i.
e.
,AGND+1LSB.
OffsetErrorMatchThisisthedifferenceinOffsetErrorbetweenthetwochannels.
GainErrorThisappliestoStraightBinaryoutputcoding.
Itisthedeviationofthelastcodetransition(111.
.
.
110)to(111.
.
.
111)fromtheideal(i.
e.
,VREF–1LSB)aftertheoffseterrorhasbeenadjustedout.
GainErrorMatchThisisthedifferenceinGainErrorbetweenthetwochannels.
ZeroCodeErrorThisapplieswhenusingthetwoscomplementoutputcodingoption,inparticularwiththe2VREFinputrangeas–VREFto+VREFbiasedabouttheVREFpoint.
Itisthedeviationofthemidscaletransition(all1stoall0s)fromtheidealVINvoltage,i.
e.
,VREF–1LSB.
ZeroCodeErrorMatchThisreferstothedifferenceinZeroCodeErrorbetweenthetwochannels.
PositiveGainErrorThisapplieswhenusingthetwoscomplementoutputcodingoption,inparticularwiththe2VREFinputrangeas–VREFto+VREFbiasedabouttheVREFpoint.
Itisthedeviationofthelastcodetransition(011.
.
.
110)to(011.
.
.
111)fromtheideal(i.
e.
,+VREF–1LSB)aftertheZeroCodeErrorhasbeenadjustedout.
NegativeGainErrorThisapplieswhenusingthetwoscomplementoutputcodingoption,inparticularwiththe2VREFinputrangeas–VREFto+VREFbiasedabouttheVREFpoint.
Itisthedeviationofthefirstcodetransition(100.
.
.
000)to(100.
.
.
001)fromtheideal(i.
e.
,–VREF+1LSB)aftertheZeroCodeErrorhasbeenadjustedout.
Track-and-HoldAcquisitionTimeThetrack-and-holdamplifierreturnsintotrackmodeaftertheendofconversion.
Track-and-holdacquisitiontimeisthetimerequiredfortheoutputofthetrack-and-holdamplifiertoreachitsfinalvalue,within±1/2LSB,aftertheendofconversion.
Signal-to-(Noise+Distortion)Ratio(SNDR)Thisisthemeasuredratioofsignal-to-(noise+distortion)attheoutputoftheA/Dconverter.
Thesignalisthermsamplitudeofthefundamental.
Noiseisthesumofallnonfundamentalsig-nalsuptohalfthesamplingfrequency(fS/2),excludingdc.
Theratioisdependentonthenumberofquantizationlevelsinthedigitizationprocess;themorelevels,thesmallerthequantiza-tionnoise.
Thetheoreticalsignal-to-(noise+distortion)ratioforanidealN-bitconverterwithasinewaveinputisgivenby:Signal-to-(Noise+Distortion)=(6.
02N+1.
76)dBThus,fora12-bitconverter,thisis74dB.
TotalHarmonicDistortion(THD)Totalharmonicdistortionistheratioofthermssumofhar-monicstothefundamental.
FortheAD7866,itisdefinedas:THDdbVVVVVV()=++++2022324252621logwhereV1isthermsamplitudeofthefundamentalandV2,V3,V4,V5,andV6arethermsamplitudesofthesecondthroughthesixthharmonics.
PeakHarmonicorSpuriousNoisePeakharmonic,orspuriousnoise,isdefinedastheratioofthermsvalueofthenextlargestcomponentintheADCoutputspectrum(uptofS/2andexcludingdc)tothermsvalueofthefundamental.
Normally,thevalueofthisspecificationisdeter-minedbythelargestharmonicinthespectrum.
ButforADCswheretheharmonicsareburiedinthenoisefloor,itwillbeanoisepeak.
IntermodulationDistortionWithinputsconsistingofsinewavesattwofrequencies,faandfb,anyactivedevicewithnonlinearitieswillcreatedistortionproductsatsumanddifferencefrequenciesofmfa±nfbwherem,n=0,1,2,3,andsoon.
Intermodulationdistortiontermsarethoseforwhichneithermnornareequaltozero.
Forexample,thesecondordertermsinclude(fa+fb)and(fa–fb),whilethethirdordertermsinclude(2fa+fb),(2fa–fb),(fa+2fb),and(fa–2fb).
TheAD7866istestedusingtheCCIFstandardwheretwoinputfrequenciesnearthetopendoftheinputbandwidthareused.
Inthiscase,thesecondordertermsareusuallydistancedinfrequencyfromtheoriginalsinewaveswhilethethirdordertermsareusuallyatafrequencyclosetotheinputfrequencies.
Asaresult,thesecondandthirdordertermsarespecifiedsepa-rately.
ThecalculationoftheintermodulationdistortionisaspertheTHDspecificationwhereitistheratioofthermssumoftheindividualdistortionproductstothermsamplitudeofthesumofthefundamentalsexpressedindB.
Channel-to-ChannelIsolationChannel-to-channelisolationisameasureofthelevelofcrosstalkbetweenchannels.
Itismeasuredbyapplyingafull-scale(2VREF),455kHzsinewavesignaltoallunselectedinputchannelsanddetermininghowmuchthatsignalisattenuatedintheselectedchannelwitha10kHzsignal(0VtoVREF).
Thefiguregivenistheworst-caseacrossallfourchannelsfortheAD7866.
PSR(PowerSupplyRejection)SeethePerformanceCurvessection.
REV.
AAD7866–9–TypicalPerformanceCharacteristicsFREQUENCY–kHz0–35–1150500100SNR–dB200300400–55–75–95501502503504504098POINTFFTfSAMPLE=1MSPSfIN=300kHzSNR=70.
31dBTHD=–85.
47dBSFDR=–86.
64dB–15TPC1.
DynamicPerformanceINPUTFREQUENCY–Hz–61–7510k1M100kSINAD–dB–73–63–67–69–71–65TA=25CVDD=VDRIVE=2.
7VVDD=VDRIVE=3.
6VVDD=VDRIVE=5.
25VVDD=VDRIVE=4.
75VTPC2.
SINADvs.
InputFrequencyAVDDRIPPLEFREQUENCY–Hz0–1001kPSRR–dB10k–90–80–70–60–50–40–30–20–10100k1M100mVp-pSINEWAVEONAVDD2.
5VEXTREFERENCEONVREFTA=25CVDD=2.
7VVDD=5.
25VVDD=4.
75VVDD=3.
6VTPC3a.
PSRRvs.
SupplyRippleFrequency,withoutSupplyDecouplingAVDDRIPPLEFREQUENCY–Hz0–1001kPSRR–dB10k–90–80–70–60–50–40–30–20–10100k1M100mVp-pSINEWAVEONAVDD2.
5VEXTREFERENCEONDCAPA,DCAPBTA=25CVDD=2.
7VVDD=5.
25VVDD=4.
75VVDD=3.
6VTPC3b.
PSRRvs.
SupplyRippleFrequency,withoutSupplyDecouplingPERFORMANCECURVESTPC1showsatypicalFFTplotfortheAD7866at1MHzsamplerateand300kHzinputfrequency.
TPC2showsthesignal-to-(noise+distortion)ratioperformanceversusinputfrequencyforvarioussupplyvoltageswhilesamplingat1MSPSwithanSCLKof20MHz.
TPCs3ato4bshowthepowersupplyrejectionratioversusAVDDsupplyripplefrequencyfortheAD7866underdifferentconditions.
Thepowersupplyrejectionratio(PSRR)isdefinedastheratioofthepowerintheADCoutputatfull-scalefre-quencyf,tothepowerofa100mVsinewaveappliedtotheADCAVDDsupplyoffrequencyfS:PSRRdBPfPfS10logPf=poweratfrequencyfinADCoutput,andPfS=poweratfrequencyfScoupledontotheADCAVDDsupply.
Here,a100mVpeak-to-peaksinewaveiscoupledontotheAVDDsupplywhilethedigitalsupplyisleftunaltered.
TPCs3aand3bshowthePSRRoftheAD7866whenthereisnodecouplingonthesupply,whileTPCs4aand4bshowthePSRRwithdecouplingcapacitorsof10Fand0.
1Fonthesupply.
TPCs5and6showtypicalDNLandINLplotsfortheAD7866.
TPC7showsagraphofthetotalharmonicdistortionversusanaloginputfrequencyforvarioussourceimpedances.
TPC8showsagraphoftotalharmonicdistortionversusanaloginputfrequencyforvarioussupplyvoltages.
SeetheAnalogInputsection.
REV.
A–10–AD7866AVDDRIPPLEFREQUENCY–Hz0–1001kPSRR–dB10k–90–80–70–60–50–40–30–20–10100k1M100mVp-pSINEWAVEONAVDD2.
5VEXTREFERENCEONVREFTA=25CVDD=2.
7VVDD=3.
6VTPC4a.
PSRRvs.
SupplyRippleFrequency,withSupplyDecouplingAVDDRIPPLEFREQUENCY–Hz0–1001kPSRR–dB10k–90–80–70–60–50–40–30–20–10100k1M100mVp-pSINEWAVEONAVDD2.
5VEXTREFERENCEONDCAPA,DCAPBTA=25CVDD=2.
7VVDD=4.
75VVDD=3.
6VTPC4b.
PSRRvs.
SupplyRippleFrequency,withSupplyDecouplingADC–Code1.
00DNL–LSB0.
80.
60.
40.
20–0.
2–0.
4–0.
6–0.
8–1.
05001000150020002500300035004000TPC5.
DCDNLPlotADC–Code1.
00INL–LSB0.
00.
80.
60.
40.
2–0.
2–0.
4–0.
6–0.
8–1.
05001000150020002500300035004000TPC6.
DCINLPlotINPUTFREQUENCY–Hz–6010kTHD–dB–65–70–75–80–85–90100k1000kTA=25CVDD=4.
75VRIN=100RIN=50RIN=10TPC7.
THDvs.
AnalogInputFrequencyforVariousSourceImpedancesINPUTFREQUENCY–Hz–7010kTHD–dB–72–74–76–78–80–82100k1000kTA=25C–84–86–88–90VDD=VDRIVE=2.
7VVDD=VDRIVE=3.
6VVDD=VDRIVE=4.
75VVDD=VDRIVE=5.
25VTPC8.
THDvs.
AnalogInputFrequencyforVariousSupplyVoltagesREV.
AAD7866–11–CIRCUITINFORMATIONTheAD7866isafast,micropower,dual12-bit,singlesupply,A/Dconverterthatoperatesfroma2.
7Vto5.
25Vsupply.
Whenoperatedfromeithera5Vsupplyora3Vsupply,theAD7866iscapableofthroughputratesof1MSPSwhenprovidedwitha20MHzclock.
TheAD7866containstwoon-chiptrack-and-holdamplifiers,twosuccessiveapproximationA/Dconverters,andaserialinter-facewithtwoseparatedataoutputpins,andishousedina20-leadTSSOPpackage,whichofferstheuserconsiderablespace-savingadvantagesoveralternativesolutions.
TheserialclockinputaccessesdatafromthepartbutalsoprovidestheclocksourceforeachsuccessiveapproximationADC.
Theana-loginputrangeforthepartcanbeselectedtobea0VtoVREFinputora2VREFinputwitheitherstraightbinaryortwoscomplementoutputcoding.
TheAD7866hasanon-chip2.
5Vreferencethatcanbeoverdrivenifanexternalreferenceispre-ferred.
Inaddition,eachADCcanbesuppliedwithanindividualseparateexternalreference.
TheAD7866alsofeaturespower-downoptionstoallowpowersavingbetweenconversions.
Thepower-downfeatureisimple-mentedacrossthestandardserialinterface,asdescribedintheModesofOperationsection.
CONVERTEROPERATIONTheAD7866hastwosuccessiveapproximationanalog-to-digitalconverters,eachbasedaroundacapacitiveDAC.
Figures2and3showsimplifiedschematicsofoneoftheseADCs.
TheADCiscomprisedofcontrollogic,aSAR,andacapacitiveDAC,allofwhichareusedtoaddandsubtractfixedamountsofchargefromthesamplingcapacitortobringthecomparatorbackintoabalancedcondition.
Figure2showstheADCduringitsacquisitionphase.
SW2isclosedandSW1isinpositionA,thecomparatorisheldinabalancedcondition,andthesamplingcapacitoracquiresthesignalonVA1,forexample.
CAPACITIVEDACCONTROLLOGICCOMPARATORSW2SW1ABAGNDVINFigure2.
ADCAcquisitionPhaseWhentheADCstartsaconversion(seeFigure3),SW2willopenandSW1willmovetopositionB,causingthecomparatortobecomeunbalanced.
TheControlLogicandthecapacitiveDACareusedtoaddandsubtractfixedamountsofchargefromthesamplingcapacitortobringthecomparatorbackintoabalancedcondition.
Whenthecomparatorisrebalanced,theconversioniscomplete.
TheControlLogicgeneratestheADCoutputcode.
Figures10and11showtheADCtransferfunctions.
CAPACITIVEDACCONTROLLOGICCOMPARATORSW2SW1ABAGNDVINFigure3.
ADCConversionPhaseANALOGINPUTFigure4showsanequivalentcircuitoftheanaloginputstructureoftheAD7866.
Thetwodiodes,D1andD2,provideESDprotectionfortheanaloginputs.
Caremustbetakentoensurethattheanaloginputsignalneverexceedsthesupplyrailsbymorethan300mV.
Thiswillcausethesediodestobecomeforward-biasedandstartconductingcurrentintothesubstrate.
10mAisthemaximumcurrentthesediodescanconductwithoutcausingirreversibledamagetothepart.
ThecapacitorC1inFigure4istypicallyabout10pFandcanprimarilybeattributedtopincapacitance.
TheresistorR1isalumpedcomponentmadeupoftheonresistanceofaswitch.
Thisresistoristypicallyabout100.
ThecapacitorC2istheADCsamplingcapacitorandhasacapacitanceof20pFtypically.
Foracapplications,removinghighfrequencycomponentsfromtheanaloginputsignalisrecommendedbyuseofanRClow-passfilterontherelevantanaloginputpin.
Inapplicationswhereharmonicdistortionandsignal-to-noiseratioarecritical,theanaloginputshouldbedrivenfromalowimpedancesource.
LargesourceimpedanceswillsignificantlyaffecttheacperformanceoftheADC.
Thismaynecessitatetheuseofaninputbufferamplifier.
Thechoiceoftheopampwillbeafunctionoftheparticularapplication.
VDDVINC1D1D2R1CONVERTPHASE–SWITCHOPENTRACKPHASE–SWITCHCLOSEDC2Figure4.
EquivalentAnalogInputCircuitWhennoamplifierisusedtodrivetheanaloginput,thesourceimpedanceshouldbelimitedtolowvalues.
Themaximumsourceimpedancewilldependontheamountoftotalharmonicdistortion(THD)thatcanbetolerated.
TheTHDwillincreaseasthesourceimpedanceincreases,andperformancewilldegrade(seeTPC7).
REV.
A–12–AD7866AnalogInputRangesTheanaloginputrangefortheAD7866canbeselectedtobe0VtoVREFor2VREFwitheitherstraightbinaryortwoscomplementoutputcoding.
TheRANGEpinisusedtoselectboththeanaloginputrangeandtheoutputcoding,asshowninFigures5to8.
OnthefallingedgeofCS,pointA,thelogicleveloftheRANGEpinischeckedtodeterminetheanaloginputrangeofthenextconversion.
Ifthispinistiedtoalogiclow,theanaloginputrangewillbe0VtoVREFandtheoutputcodingfromthepartwillbestraightbinary(forthenextconversion).
IfthispinisatalogichighwhenCSgoeslow,theanaloginputrangewillbe2VREFandtheoutputcodingforthepartwillbetwoscomplement.
How-ever,ifafterthefallingedgeofCS,thelogicleveloftheRANGEpinhaschangedupontheeighthfallingSCLKedge,pointB,theoutputcodingwillchangetotheotheroptionwithoutanychangeintheanaloginputrange.
Soforthenextconversion,twoscomplementoutputcodingcouldbeselectedwitha0VtoVREFinputrange,forexample,iftheRANGEpinislowuponthefallingedgeofCSandhighupontheeighthfallingSCLKedge,asshowninFigure7.
Figures5to8showexamplesoftimingdiagramsforselectionsofdifferentanaloginputrangeswithvariousoutputcodingformats.
TableIsummarizestherequiredlogicleveloftheRANGEpinforeachselection.
NotethattheanaloginputrangeselectedmustnotexceedVDD.
ThelogicinputA0isusedtoselectthepairofchannelstobeconvertedsimultaneously.
ThelogicstateofthispinisalsocheckeduponthefallingedgeofCS,andthemultiplexersaresetupforthenextconversion.
Ifitislow,thefollowingconversionwillbeperformedonChannel1ofeachADC;ifitishigh,thefollowingconversionwillbeperformedonChannel2ofeachADC.
HandlingBipolarInputSignalsFigure9showshowusefulthecombinationofthe2VREFinputrangeandthetwoscomplementoutputcodingschemeisforhandlingbipolarinputsignals.
IfthebipolarinputsignalisbiasedaboutVREFandtwoscomplementoutputcodingisselected,thenVREFbecomesthezerocodepoint,–VREFisnegativefull-scale,and+VREFbecomespositivefull-scalewithadynamicrangeof2VREF.
TransferFunctionsThedesignedcodetransitionsoccuratsuccessiveintegerLSBvalues(i.
e.
,1LSB,2LSB,andsoon).
TheLSBsizeisVREF/4096.
TheidealtransfercharacteristicfortheAD7866whenstraightbinarycodingisselectedisshowninFigure10,andtheidealtransfercharacteristicfortheAD7866whentwoscomplementcodingisselectedisshowninFigure11.
TableI.
AnalogInputandOutputCodingSelectionRangeLevelRangeLevel@PointA1@PointB2InputRange3OutputCoding3LowLow0VtoVREFStraightBinaryHighHighVREF±VREFTwosComplementLowHighVREF/2±VREF/2TwosComplementHighLow0Vto2VREFStraightBinaryNOTES1PointA=FallingedgeofCS.
2PointB=EighthfallingedgeofSCLK.
3Selectedfornextconversion.
STRAIGHTBINARY0VTOVREFINPUTRANGECSSCLKRANGEDOUTADOUTB1816161ABFigure5.
Selecting0VtoVREFInputRangewithStraightBinaryOutputCodingCSSCLKRANGEDOUTADOUTB1816161ABVREFVREFINPUTRANGETWOSCOMPLEMENTFigure6.
SelectingVREF±VREFInputRangewithTwosComplementOutputCodingREV.
AAD7866–13–CSSCLKRANGEDOUTADOUTB1816161ABVREF/2VREF/2INPUTRANGETWOSCOMPLEMENTFigure7.
SelectingVREF/2±VREF/2InputRangewithTwosComplementOutputCodingCSSCLKRANGEDOUTADOUTB1816161AB0VTO2VREFINPUTRANGESTRAIGHTBINARYFigure8.
Selecting0Vto2VREFInputRangewithStraightBinaryOutputCodingREFSELECTVREFAD7866DOUTDCAPADCAPBVDRIVEVIN470nF470nF100nFVREFR4R3R2VR1V0VTWOSCOMPLEMENT011111+VREFVREF–VREF(=2VREF)000000100000(=0V)R1=R2=R3=R4VDDVDDDSP/PFigure9.
HandlingBipolarSignalswiththeAD7866000.
.
.
0000VANALOGINPUT111.
.
.
111000.
.
.
001000.
.
.
010111.
.
.
110111.
.
.
000011.
.
.
1111LSBVREF–1LSB1LSB=VREF/4096ADCCODEFigure10.
StraightBinaryTransferCharacteristicwith0VtoVREFInputRange100.
.
.
000ANALOGINPUT011.
.
.
110100.
.
.
001100.
.
.
010000.
.
.
001111.
.
.
1111LSB=2VREF/4096ADCCODE011.
.
.
111000.
.
.
000+VREF–1LSB–VREF+1LSBVREF–1LSBFigure11.
TwosComplementTransferCharacteristicwithVREF±VREFInputRangeREV.
A–14–AD7866DigitalInputsThedigitalinputsappliedtotheAD7866arenotlimitedbythemaximumratingsthatlimittheanaloginputs.
Instead,thedigitalinputsappliedcangoto7VandarenotrestrictedbytheVDD+0.
3Vlimitasontheanaloginputs.
Seemaximumratings.
AnotheradvantageofSCLK,RANGE,REFSELECT,A0,andCSnotbeingrestrictedbytheVDD+0.
3Vlimitisthatpowersupplysequencingissuesareavoided.
IfoneofthesedigitalinputsisappliedbeforeVDD,thereisnoriskoflatch-up,astherewouldbeontheanaloginputsifasignalgreaterthan0.
3VwereappliedpriortoVDD.
VDRIVETheAD7866alsohastheVDRIVEfeature,whichcontrolsthevoltageatwhichtheserialinterfaceoperates.
VDRIVEallowstheADCtoeasilyinterfacetoboth3Vand5Vprocessors.
Forexample,iftheAD7866wasoperatedwithaVDDof5V,theVDRIVEpincouldbepoweredfroma3Vsupply,allowingalargedynamicrangewithlowvoltagedigitalprocessors.
Forexample,theAD7866couldbeusedwiththe2VREFinputrange,withaVDDof5Vwhilestillbeingabletointerfaceto3Vdigitalparts.
REFERENCECONFIGURATIONOPTIONSTheAD7866hasvariousreferenceconfigurationoptions.
TheREFSELECTpinallowsthechoiceofusinganinternal2.
5Vreferenceorapplyinganexternalreference,orevenanindividualexternalreferenceforeachon-chipADCifdesired.
IftheREFSELECTpinistiedtoAGND,thentheon-chip2.
5VreferenceisusedasthereferencesourceforbothADCAandADCB.
Inaddition,pinsVREF,DCAPA,andDCAPBmustbetiedtodecouplingcapacitors(100nF,470nF,and470nFrecommended,respectively).
IftheREFSELECTpinistiedtoalogichigh,anexternalreferencecanbesuppliedtotheAD7866throughtheVREFpintooverdrivetheon-chipreference,inwhichcasedecouplingcapacitorsarerequiredonDCAPAandDCAPBagain.
However,iftheVREFpinistiedtoAGNDwhileREFSELECTistiedtoalogiclow,anindividualexternalreferencecanbeappliedtobothADCAandADCBthroughpinsDCAPAandDCAPB,respectively.
TableIIsummarizesthesereferenceoptions.
Forspecifiedperformance,thelastconfigurationwasusedwiththesamereferencevoltageappliedtobothDCAPAandDCAPB.
Theconnectionsfortherelevantreferencepinsareshowninthetypicalconnectiondiagrams.
Iftheinternalreferenceisbeingused,theVREFpinshouldhavea100nFcapacitorconnectedtoAGNDveryclosetotheVREFpin.
TheseconnectionsareshowninFigure12.
DCAPBDCAPAVREF470nFAD7866470nF100nFFigure12.
RelevantConnectionswhenUsinganInternalReferenceDCAPBDCAPAVREFAD7866VREFREFSELECTFigure13.
RelevantConnectionswhenApplyinganExternalReferenceatDCAPAand/orDCAPBDCAPBDCAPAVREF470nFAD7866470nFVREFREFSELECTVDRIVEFigure14.
RelevantConnectionswhenApplyinganExternalReferenceatVREFFigure13showstheconnectionsrequiredwhenanexternalreferenceisappliedtoDCAPAandDCAPB.
Inthisexample,thesamereferencevoltageisappliedateachpin;however,adifferentvoltagemaybeappliedateachofthesepinsforeachon-chipADC.
Anexternalreferenceappliedatthesepinsmayhavearangefrom2Vto3V,butforspecifiedperformanceitmustbewithin±1%of2.
5V.
Figure14showsthethirdoption,whichistooverdrivetheinternalreferencethroughtheVREFpin.
ThisispossibleduetotheseriesresistancefromtheVREFpintotheinternalreference.
Thisexternalreferencecanhavearangefrom2Vto3V;butagain,togetascloseaspossibletothespecifiedperformance,a2.
5Vreferenceisdesirable.
DCAPAandDCAPBdecoupleeachon-chipreferencebuffer,asshowninFigure15.
TableII.
ReferenceSelectionReferenceOptionREFSELECTVREF1DCAPAandDCAPB2InternalLowDecouplingCapacitorDecouplingCapacitorExternallythroughVREFHighExternalReferenceDecouplingCapacitorExternallythroughDCAPAand/orDCAPBLowAGNDExternalReferenceAand/orReferenceBNOTES1Recommendedvalueofdecouplingcapacitor=100nF.
2Recommendedvalueofdecouplingcapacitor=470nF.
REV.
AAD7866–15–100nF2.
5VREFADCBEXTREFEXTREF470nFDCAPBDCAPAVREFEXTREF470nFBUFBADCABUFAFigure15.
ReferenceCircuitIftheon-chip2.
5Vreferenceisbeingused,andistobeappliedexternallytotherestofthesystem,itmaybetakenfromeithertheVREFpinoroneoftheDCAPAorDCAPBpins.
IfitistakenfromtheVREFpin,itmustbebufferedbeforebeingappliedelsewhereasitwillnotbecapableofsourcingmorethanafewmicroamps.
IfthereferencevoltageistakenfromeithertheDCAPApinorDCAPBpin,abufferisnotstrictlynecessary.
Eitherpiniscapableofsourcingcurrentintheregionof100A;how-ever,thelargerthesourcecurrentrequirement,thegreaterthevoltagedropseenatthepin.
Theoutputimpedanceofeachofthesepinsistypically50.
Inaddition,thispointrepresentstheactualvoltageappliedtotheADCinternallysoanyvoltagedropduetothecurrentloadordisturbanceduetoadynamicloadwilldirectlyaffecttheADCconversion.
Forthisreason,ifalargecurrentsourceisnecessaryoradynamicloadispresent,itisrecommendedtouseabufferontheoutputtodriveadevice.
Examplesofsuitableexternalreferencedevicesthatmaybeap-pliedatpinsVREF,DCAPA,orDCAPBaretheAD780,REF192,REF43,andAD1582.
MODESOFOPERATIONThemodeofoperationoftheAD7866isselectedbycontrollingthe(logic)stateoftheCSsignalduringaconversion.
Therearethreepossiblemodesofoperation:normalmode,partialpower-downmode,andfullpower-downmode.
ThepointatwhichCSispulledhighaftertheconversionhasbeeninitiatedwilldeterminewhichpower-downmode,ifany,thedevicewillenter.
Similarly,ifalreadyinapower-downmode,CScancontrolwhetherthedevicewillreturntonormaloperationorremaininpower-down.
Thesemodesofoperationaredesignedtoprovideflexiblepowermanagementoptions.
Theseoptionscanbechosentooptimizethepowerdissipation/throughputrateratiofordifferingapplicationrequirements.
NormalModeThismodeisintendedforfastestthroughputrateperformancesincetheuserdoesnothavetoworryaboutanypower-uptimeswiththeAD7866remainingfullypoweredallthetime.
Figure16showsthegeneraldiagramoftheoperationoftheAD7866inthismode.
TheconversionisinitiatedonthefallingedgeofCS,asdescribedintheSerialInterfacesection.
Toensurethatthepartremainsfullypoweredupatalltimes,CSmustremainlowuntilatleast10SCLKfallingedgeshaveelapsedafterthefallingedgeofCS.
IfCSisbroughthighanytimeafterthe10thSCLKfallingedge,butbeforethe16thSCLKfallingedge,thepartwillremainpoweredupbuttheconversionwillbeterminatedandDOUTAandDOUTBwillgobackintothree-state.
Sixteenserialclockcyclesarerequiredtocompletetheconversionandaccesstheconversionresult.
TheDOUTlinewillnotreturntothree-stateafter16SCLKcycleshaveelapsed,butinsteadwhenCSisbroughthighagain.
IfCSisleftlowforanother16SCLKcycles,theresultfromtheotherADConboardwillalsobeaccessedonthesameDOUTline,asshowninFigure22(seealsotheSerialInterfacesection).
TheSTATUSbitsprovidedpriortoeachconversionresultwillidentifywhichADCthefollowingresultwillbefrom.
Once32SCLKcycleshaveelapsed,theDOUTlinewillreturntothree-stateonthe32ndSCLKfallingedge.
IfCSisbroughthighpriortothis,theDOUTlinewillreturntothree-stateatthatpoint.
Thus,CSmayidlelowafter32SCLKcycles,untilitisbroughthighagainsometimepriortothenextconversion(effectivelyidlingCSlow),ifsodesired,sincethebuswillstillreturntothree-stateuponcompletionofthedualresultread.
OnceadatatransferiscompleteandDOUTAandDOUTBhavereturnedtothree-state,anotherconversioncanbeinitiatedafterthequiettime,tQUIET,haselapsedbybringingCSlowagain.
PartialPower-DownModeThismodeisintendedforuseinapplicationswhereslowerthroughputratesarerequired.
EithertheADCispowereddownbetweeneachconversion,oraseriesofconversionsmaybeperformedatahighthroughputrateandtheADCisthenpowereddownforarelativelylongdurationbetweentheseburstsofseveralconversions.
WhentheAD7866isinpartialpower-down,allanalogcircuitryispowereddownexceptfortheon-chipreferenceandreferencebuffer.
Toenterpartialpower-down,theconversionprocessmustbeinterruptedbybringingCShighanywhereafterthesecondfallingedgeofSCLKandbeforethetenthfallingedgeofSCLKasshowninFigure17.
OnceCShasbeenbroughthighinthiswindowofSCLKs,thepartwillenterpartialpower-down,theconversionthatwasinitiatedbythefallingedgeofCSwillbeSCLKDOUTADOUTBCSSTATUSBITSANDCONVERSIONRESULT11610Figure16.
NormalModeOperationREV.
A–16–AD7866terminated,andDOUTAandDOUTBwillgobackintothree-state.
IfCSisbroughthighbeforethesecondSCLKfallingedge,thepartwillremaininnormalmodeandwillnotpowerdown.
Thiswillavoidaccidentalpower-downduetoglitchesontheCSline.
ToexitthismodeofoperationandpoweruptheAD7866again,adummyconversionisperformed.
OnthefallingedgeofCS,thedevicewillbegintopowerup,andwillcontinuetopowerupaslongasCSisheldlowuntilafterthefallingedgeofthetenthSCLK.
Inthecaseofanexternalreference,thedevicewillbefullypowereduponce16SCLKshaveelapsed,andvaliddatawillresultfromthenextconversion,asshowninFigure18.
IfCSisbroughthighbeforethesecondfallingedgeofSCLK,theAD7866willagaingointopartialpower-down.
Thisavoidsaccidentalpower-upduetoglitchesontheCSline;althoughthedevicemaybegintopoweruponthefallingedgeofCS,itwillpowerdownagainontherisingedgeofCS.
IftheAD7866isalreadyinpartialpower-downmodeandCSisbroughthighbetweenthesecondandtenthfallingedgesofSCLK,thedevicewillenterfullpower-downmode.
Formoreinformationonthepower-uptimesassociatedwithpartialpower-downinvariousconfigurations,seethePower-UpTimessection.
FullPower-DownModeThismodeisintendedforuseinapplicationswherethroughputratesslowerthanthoseinthepartialpower-downmodearerequired,aspower-upfromafullpower-downtakessubstantiallylongerthanthatfrompartialpower-down.
Thismodeismoresuitedtoapplicationswhereaseriesofconversionsperformedatarela-tivelyhighthroughputratewouldbefollowedbyalongperiodofinactivityandthuspower-down.
WhentheAD7866isinfullpower-down,allanalogcircuitryispowereddown.
Fullpower-downisenteredinasimilarwayaspartialpower-down,exceptthetimingsequenceshowninFigure17mustbeexecutedtwice.
TheconversionprocessmustbeinterruptedinasimilarfashionbybringingCShighanywhereafterthesecondfallingedgeofSCLKandbeforethetenthfallingedgeofSCLK.
Thedevicewillenterpartialpower-downatthispoint.
Toreachfullpower-down,thenextconversioncyclemustbeinterruptedinthesameway,asshowninFigure19.
OnceCShasbeenbroughthighinthiswindowofSCLKs,thepartwillpowerdowncompletely.
Notethatitisnotnecessarytocompletethe16SCLKsonceCShasbeenbroughthightoenterapower-downmode.
Toexitfullpower-downandpowertheAD7866upagain,adummyconversionisperformed,aswhenpoweringupfrompartialpower-down.
OnthefallingedgeofCS,thedevicewillbegintopowerupandwillcontinuetopowerupaslongasCSisheldlowuntilafterthefallingedgeofthetenthSCLK.
Thepower-uptimerequiredmustelapsebeforeaconversioncanbeinitiated,asshowninFigure20.
SeethePower-UpTimessec-tionforthepower-uptimesassociatedwiththeAD7866.
POWER-UPTIMESTheAD7866hastwopower-downmodes,partialpower-downandfullpower-down,whicharedescribedindetailintheModesofOperationsection.
Thissectiondealswiththepower-uptimerequiredwhencomingoutofeitherofthesemodes.
Itshouldbenotedthatthepower-uptimesquotedapplywiththerecommendedcapacitorsontheVREF,DCAPA,andDCAPBpinsinplace.
Topowerupfromfullpower-down,approximately4msshouldbeallowedfromthefallingedgeofCS,showninFigure20astPOWERUP.
Poweringupfrompartialpower-downrequiresmuchlesstime.
Iftheinternalreferenceisbeingused,thepower-uptimeistypically4s;butifanexternalreferenceisbeingused,thepower-uptimeistypically1s.
ThismeansthatwithanyfrequencyofSCLKupto20MHz,onedummycyclewillalwaysbesufficienttoallowthedevicetopowerupfrompartialpower-downwhenusinganexternalreference(seeFigure18).
Oncethedummycycleiscomplete,theADCwillbefullypoweredupandtheinputsignalwillbeacquiredproperly.
Adummycyclemaywellbesufficienttopowerupthepartwhenusinganinternalreferencealso,providedtheSCLKisslowenoughtoallowtherequiredpower-uptimetoelapsebeforeavalidconversionisrequested.
Inaddition,itshouldbeensuredthatthequiettime,tQUIET,hasstillbeenallowedfromthepointwherethebusgoesbackintothree-stateafterthedummyconversiontothenextfallingedgeofCS.
Alternatively,insteadofslowingtheSCLKtomakethedummycyclelongenough,theCShightimecouldjustbeextendedtoincludetherequiredpower-uptime(asinFigure20)whenpoweringupfromfullpower-down.
Differentpower-uptimeisneededwhencomingoutofpartialpower-downfortwocaseswhereaninternalorexternalrefer-enceisbeingused,primarilybecauseoftheon-chipreferencebuffers.
Theypowerdowninpartialpower-downmodeandmustbepoweredupagainiftheinternalreferenceisbeingused,buttheydonotneedtobepoweredupagainifanexternalreferenceisbeingused.
Thetimeneededtopowerupthesebuffersisnotjusttheirownpower-uptimebutalsothetimerequiredtochargeupthedecouplingcapacitorspresentonpinsVREF,DCAPA,andDCAPB.
Itshouldalsobenotedthatduringpower-upfrompartialpower-down,thetrack-and-hold,whichwasinholdmodewhilethepartwaspowereddown,returnstotrackmodeafterthefirstSCLKedgethepartreceivesafterthefallingedgeofCS.
ThisisshownaspointAinFigure18.
WhenpowersuppliesarefirstappliedtotheAD7866,theADCmaypowerupineitherofthepower-downmodesorthenormalmode.
Becauseofthis,itisbesttoallowadummycycletoelapsetoensurethatthepartisfullypoweredupbeforeattemptingavalidconversion.
Likewise,ifthepartistobekeptinthepartialpower-downmodeimmediatelyafterthesuppliesareapplied,twodummycyclesmustbeinitiated.
ThefirstdummycyclemustholdCSlowuntilafterthetenthSCLKfallingedge(seeFigure16);inthesecondcycle,CSmustbebroughthighbeforethetenthSCLKedgebutafterthesecondSCLKfallingedge(seeFigure17).
Alternatively,ifthepartistobeplacedinfullpower-downmodewhenthesupplieshavebeenapplied,threedummycyclesmustbeinitiated.
ThefirstdummycyclemustholdCSlowuntilafterthetenthSCLKfallingedge(seeFigure16);thesec-ondandthirddummycyclesplacethepartinfullpower-down(seeFigure19).
SeealsotheModesofOperationsection.
OncesuppliesareappliedtotheAD7866,enoughtimemustbeallowedforanyexternalreferencetopowerupandchargeanyreferencecapacitortoitsfinalvalue,orenoughtimemustbeallowedfortheinternalreferencebuffertochargethevariousreferencebufferdecouplingcapacitorstotheirfinalvalues.
REV.
AAD7866–17–CS116102THREE-STATESCLKDOUTADOUTBFigure17.
EnteringPartialPower-DownMode11610116INVALIDDATAVALIDDATACSSCLKDOUTADOUTBTHEPARTBEGINSTOPOWERUPTHEPARTMAYBEFULLYPOWEREDUP;SEEPOWER-UPTIMESSECTIONAFigure18.
ExitingPartialPower-DownMode11610116INVALIDDATAINVALIDDATATHREE-STATETHREE-STATE2210CSSCLKDOUTADOUTBTHEPARTENTERSPARTIALPOWER-DOWNTHEPARTBEGINSTOPOWERUPTHEPARTENTERSFULLPOWER-DOWNFigure19.
EnteringFullPower-DownMode11610116INVALIDDATAVALIDDATACSSCLKDOUTADOUTBTHEPARTBEGINSTOPOWERUPTHEPARTISFULLYPOWEREDUPtPOWERUPFigure20.
ExitingFullPower-DownModeThen,toplacetheAD7866innormalmode,adummycycle(1sto4sapproximately)shouldbeinitiated.
Ifthefirstvalidconversionisperformeddirectlyafterthedummyconversion,caremustbetakentoensurethatadequateacquisitiontimehasbeenallowed.
Asmentionedearlier,whenpoweringupfromthepower-downmode,thepartwillreturntotrackuponthefirstSCLKedgeappliedafterthefallingedgeofCS.
HoweverwhentheADCinitiallypowersupaftersuppliesareapplied,thetrack-and-holdwillalreadybeintrack.
Thismeansthat(assumingonehasthefacilitytomonitortheADCsupplycurrentandthusdeterminewhichmodetheAD7866isin)iftheADCpowersupinthedesiredmodeofoperationandthusadummycycleisnotrequiredtochangemode,thenneitherisadummycyclerequiredtoplacethetrack-and-holdintotrack.
Ifnocurrentmonitoringfacilityisavailable,therelevantdummycycle(s)shouldbeperformedtoensurethepartisintherequiredmode.
REV.
A–18–AD7866POWERVS.
THROUGHPUTRATEWhentheAD7866isinpartialpower-downmodeandnotconverting,theaveragepowerconsumptionoftheADCdecreasesatlowerthroughputrates.
Figure21showsthatasthethrough-putrateisreduced,thepartremainsinitspartialpower-downstatelonger,andtheaveragepowerconsumptionovertimedropsaccordingly.
THROUGHPUT–kSPS0.
010POWER–mW50100VDD=5VSCLK=20MHz1502002503003500.
1110100VDD=3VSCLK=20MHzFigure21.
Powervs.
ThroughputforPartialPower-DownForexample,iftheAD7866isoperatedinacontinuoussamplingmodewithathroughputrateof100kSPSandanSCLKof20MHz(VDD=5V),andthedeviceisplacedinpartialpower-downmodebetweenconversions,thepowerconsumptioniscalculatedasfollows.
Themaximumpowerdissipationduringnormaloperationis24mW(VDD=5V).
Ifthepower-uptimeallowedfrompartialpower-downisonedummycycle,i.
e.
,1s,(assuminguseofanexternalreference)andtheremainingconversiontimeisanothercycle,i.
e.
,1s,thentheAD7866canbesaidtodissipate24mWfor2sduringeachconversioncycle.
Fortheremainderoftheconversioncycle,8s,thepartremainsinpartialpower-downmode.
TheAD7866canbesaidtodissipate2.
8mWfortheremaining8softheconversioncycle.
Ifthethroughputrateis100kSPS,thecycletimeis10sandtheaveragepowerdissipatedduringeachcycleis(2/10)(24mW)+(8/10)(2.
8mW)=7.
04mW.
IfVDD=3V,SCLK=20MHz,andthedeviceisagaininpartialpower-downmodebetweenconversions,thepowerdissipatedduringnormaloperationis11.
4mW.
TheAD7866canbesaidtodissipate11.
4mWfor2sduringeachconversioncycleand1.
68mWfortheremaining8swhenthepartisinpartialpower-down.
Withathroughputrateof100kSPS,theaveragepowerdissipatedduringeachconversioncycleis(2/10)(11.
4mW)+(8/10)(1.
68mW)=3.
624mW.
Figure21showsthemaximumpowerversusthroughputratewhenusingthepartialpower-downmodebetweenconversionswithboth5Vand3VsuppliesfortheAD7866.
SERIALINTERFACEFigure22showsthedetailedtimingdiagramforserialinterfacingtotheAD7866.
TheserialclockprovidestheconversionclockandcontrolsthetransferofinformationfromtheAD7866duringconversion.
TheCSsignalinitiatesthedatatransferandconversionprocess.
ThefallingedgeofCSputsthetrack-and-holdintoholdmodeandtakesthebusoutofthree-state;theanaloginputissampledatthispoint.
Theconversionisalsoinitiatedatthispointandrequires16SCLKcyclestocomplete.
Once13SCLKfallingedgeshaveelapsed,thetrack-and-holdwillgobackintotrackonthenextSCLKrisingedge,asshowninFigure22atpointB.
OntherisingedgeofCS,theconversionwillbeterminatedandDOUTAandDOUTBwillgobackintothree-state.
IfCSisnotbroughthighbutisinsteadheldlowforafurther16SCLKcyclesonDOUTA,thedatafromconversionBwillbeoutputonCSSCLKDOUTADOUTBt21234513141516t3t4t7t5t8tQUIET0RANGEA0A/BDB11DB2DB1DB0THREE-STATE1LEADINGZERO3STATUSBITSDB10THREE-STATEt6BFigure22.
SerialInterfaceTimingDiagramCSSCLKDOUTAt2t4t7t50RANGEDB11AA0/A0ZERODB1ADB0AZERORANGEA0/A0ONEDB11BDB1BDB0BTHREE-STATEt6t91LEADINGZERO3STATUSBITS1LEADINGZERO3STATUSBITSTHREE-STATEt3123451415161732Figure23.
ReadingDatafromBothADCsonOneDOUTLineREV.
AAD7866–19–DOUTA.
Likewise,ifCSisheldlowforafurther16SCLKcyclesonDOUTB,thedatafromconversionAwillbeoutputonDOUTB.
ThisisillustratedinFigure23wherethecaseforDOUTAisshown.
Notethatinthiscase,theDOUTlineinusewillgobackintothree-stateonthe32ndSCLKrisingedgeortherisingedgeofCS,whicheveroccursfirst.
SixteenserialclockcyclesarerequiredtoperformtheconversionprocessandtoaccessdatafromoneconversiononeitherdatalineoftheAD7866.
CSgoinglowprovidestheleadingzerotobereadinbythemicrocontrollerorDSP.
TheremainingdataisthenclockedoutbysubsequentSCLKfallingedges,beginningwiththefirstofthreedataSTATUSbits.
ThusthefirstfallingclockedgeontheserialclockhastheleadingzeroprovidedandalsoclocksoutthefirstofthreeSTATUSbits.
Thefinalbitinthedatatransferisvalidonthesixteenthfallingedge,havingbeingclockedoutontheprevious(fifteenth)fallingedge.
InapplicationswithaslowerSCLK,itispossibletoreadindataoneachSCLKrisingedge,i.
e.
,thefirstrisingedgeofSCLKaftertheCSfallingedgewouldhavetheleadingzeroprovidedandthefifteenthrisingSCLKedgewouldhaveDB0provided.
ThethreeSTATUSbitsthatfollowtheleadingzeroprovideinfor-mationwithrespecttotheconversionresultthatfollowsthemontheDOUTlineinuse.
TableIIIshowshowtheseidentifica-tionbitscanbeinterpreted.
MICROPROCESSORINTERFACINGTheserialinterfaceontheAD7866allowsthepartstobedirectlyconnectedtoarangeofmanydifferentmicroprocessors.
ThissectionexplainshowtointerfacetheAD7866withsomeofthemorecommonmicrocontrollerandDSPserialinterfaceprotocols.
AD7866toADSP-218xTheADSP-218xfamilyofDSPsisdirectlyinterfacedtotheAD7866withoutanygluelogicrequired.
TheVDRIVEpinoftheAD7866takesthesamesupplyvoltageasthatoftheADSP-218x.
ThisallowstheADCtooperateatahighersupplyvoltagethantheserialinterface,i.
e.
,ADSP-218x,ifnecessary.
ThisexampleshowsbothDOUTAandDOUTBoftheAD7866connectedtobothserialportsoftheADSP-218x.
TableIII.
STATUSBitDescriptionBitBitNameComment15ZEROLeadingZero.
Thisbitwillalwaysbeazerooutput.
14RANGEThepolarityofthisbitreflectstheanaloginputrangethathasbeenselectedwiththeRANGEpin.
Ifitisa0,itmeansthatintheprevioustransferuponthefallingedgeoftheCS,therangepinwasatalogiclow,providingananaloginputrangefrom0VtoVREFforthisconversion.
Ifitisa1,itmeansthatintheprevioustransferuponthefallingedgeofCS,theRANGEpinwasatalogichigh,resultinginananaloginputrangeof2VREFselectedforthisconversion.
SeeAnalogInputsection.
13A0Thisbitindicatesonwhichchanneltheconversionisbeingperformed,Channel1orChannel2oftheADCinquestion.
Ifthisbitisa0,theconversionresultwillbefromChannel1oftheADC;ifitisa1,theresultwillbefromChannel2oftheADCinquestion.
12A/BThisbitindicatesfromwhichADCtheconversionresultcomes.
Ifthisbitisa0,theresultisfromADCA;ifitisa1,theresultisfromADCB.
ThisisespeciallyusefulifonlyoneserialportisavailableforuseandoneDOUTlineisused,asshowninFigure23.
TheSPORT0controlregistershouldbesetupasfollows:TFSW=RFSW=1,AlternateFramingINVRFS=INVTFS=1,ActiveLowFrameSignalDTYPE=00,RightJustifyDataSLEN=1111,16-BitData-WordsISCLK=1,InternalSerialClockTFSR=RFSR=1,FrameEveryWordIRFS=0ITFS=1TheSPORT1controlregistershouldbesetupasfollows:TFSW=RFSW=1,AlternateFramingINVRFS=INVTFS=1,ActiveLowFrameSignalDTYPE=00,RightJustifyDataSLEN=1111,16-BitData-WordsISCLK=0,ExternalSerialClockTFSR=RFSR=1,FrameEveryWordIRFS=0ITFS=1Toimplementthepower-downmodesontheAD7866,SLENshouldbesetto1001toissuean8-bitSCLKburst.
TheconnectiondiagramisshowninFigure24.
TheADSP-218xhastheTFS0andRFS0oftheSPORT0andtheRFS1ofSPORT1tiedtogether,withTFS0setasanoutputandbothRFS0andRFS1setasinputs.
TheDSPoperatesinalternateframingmodeandtheSPORTcontrolregisterissetupasdescribed.
TheframesynchronizationsignalgeneratedontheTFSistiedtoCSand,aswithallsignalprocessingapplications,equidistantsamplingisnecessary.
However,inthisexample,thetimerinterruptisusedtocontrolthesamplingrateoftheADCandundercertainconditions,equidistantsamplingmaynotbeachieved.
Thetimerandotherregistersareloadedwithavaluethatwillprovideaninterruptattherequiredsampleinterval.
Whenaninterruptisreceived,avalueistransmittedwithTFS/DT(ADCcontrolword).
TheTFSisusedtocontroltheRFSandthere-forethereadingofdata.
ThefrequencyoftheserialclockissetintheSCLKDIVregister.
WhentheinstructiontotransmitwithTFSisgiven(i.
e.
,AX0=TX0),thestateoftheSCLKischecked.
TheDSPwillwaituntiltheSCLKhasgonehigh,low,andhighbeforetransmissionwillstart.
IfthetimerandSCLKvaluesarechosensuchthattheinstructiontotransmitoccursonorneartherisingedgeofSCLK,thedatamaybetransmittedoritmaywaituntilthenextclockedge.
REV.
A–20–AD7866Forexample,iftheADSP-2189hada20MHzcrystalsuchthatithadamasterclockfrequencyof40MHz,thenthemastercycletimewouldbe25ns.
IftheSCLKDIVregisterisloadedwiththevalue3,anSCLKof5MHzisobtainedandeightmasterclockperiodswillelapseforevery1SCLKperiod.
Dependingonthethroughputrateselected,ifthetimerregisterwereloadedwiththevalue,803,(803+1=804),forexample,100.
5SCLKswouldoccurbetweeninterruptsandsubsequentlybetweentransmitinstructions.
ThissituationwouldresultinnonequidistantsamplingasthetransmitinstructionisoccurringonanSCLKedge.
IfthenumberofSCLKsbetweeninterruptswereawholeintegerfigureofN,equidistantsamplingwouldbeimplementedbytheDSP.
AD7866*VDRIVEDOUTADOUTBCSSCLKADSP-218x*DR0DR1TFS0SCLK0RFS0RSF1SCLK1*ADDITIONALPINSOMITTEDFORCLARITYVDDFigure24.
InterfacingtheAD7866totheADSP-218xAD7866*VDRIVEDOUTADOUTBCSSCLKTMS320C541*DR0DR1CLKX0CLKR0CLKX1CLKR1*ADDITIONALPINSOMITTEDFORCLARITYVDDFSX0FSR0FSR1Figure25.
InterfacingtheAD7866totheTMS320C541AD7866toTMS320C541TheserialinterfaceontheTMS320C541usesacontinuousserialclockandframesynchronizationsignalstosynchronizethedatatransferoperationswithperipheraldevicesliketheAD7866.
TheCSinputallowseasyinterfacingbetweentheTMS320C541andtheAD7866withnogluelogicrequired.
TheserialportsoftheTMS320C541aresetuptooperateinburstmodewithinternalCLKX(Txserialclockonserialport0)andFSX0(Txframesyncfromserialport0).
Theserialportcontrol(SPC)registersmusthavethefollowingsetup:SPC0:FO=0,FSM=1,MCM=1andTxM=1SPC1:FO=0,FSM=1,MCM=0andTxM=0Theformatbit,FO,maybesetto1tosetthewordlengthtoeightbits,inordertoimplementthepower-downmodesontheAD7866.
TheconnectiondiagramisshowninFigure25.
Itshouldbenotedthatforsignalprocessingapplications,itisimperativethattheframesynchronizationsignalfromtheTMS320C541willprovideequidistantsampling.
TheVDRIVEpinoftheAD7866takesthesamesupplyvoltageasthatoftheTMS320C541.
ThisallowstheADCtooperateatahighervoltagethantheserialinterface,i.
e.
,TMS320C541,ifnecessary.
AD7866toDSP-563xxTheconnectiondiagraminFigure26showshowtheAD7866canbeconnectedtotheESSI(synchronousserialinterface)oftheDSP-563xxfamilyofDSPsfromMotorola.
EachESSI(therearetwoon-board)isoperatedinsynchronousmode(bitSYN=1inCRBregister)withinternallygeneratedwordlengthframesyncforbothTxandRx(bitsFSL1=0andFSL0=0inCRB).
NormaloperationoftheESSIisselectedbymakingMOD=0intheCRB.
Setthewordlengthto16bysettingbitsWL1=1andWL0=0inCRA.
Toimplementthepower-downmodesontheAD7866,thewordlengthcanbechangedtoeightbitsbysettingbitsWL1=0andWL0=0inCRA.
TheFSPbitintheCRBshouldbesetto1tomaketheframesyncnegative.
Itshouldbenotedthatforsignalprocessingapplications,itisimperativethattheframesynchronizationsignalfromtheDSP-563xxprovideequidistantsampling.
IntheexampleshowninFigure26,theserialclockistakenfromtheESSI0,sotheSCK0pinmustbesetasanoutput,SCKD=1,whiletheSCK1pinissetupasaninput,SCKD=0.
TheframesyncsignalistakenfromSC02onESSI0,soSCD2=1,whileonESSI1,SCD2=0,soSC12isconfiguredasaninput.
TheVDRIVEpinoftheAD7866takesthesamesupplyvoltageasthatoftheDSP-563xx.
ThisallowstheADCtooperateatahighervoltagethantheserialinterface,i.
e.
,DSP-563xx,ifnecessary.
AD7866*VDRIVEDOUTADOUTBCSSCLKDSP-563xx*SC02SC12SCK0SRD0SRD1SCK1*ADDITIONALPINSOMITTEDFORCLARITYVDDFigure26.
InterfacingtotheDSP-563xxAPPLICATIONHINTSGroundingandLayoutTheanaloganddigitalsuppliestotheAD7866areindependentandseparatelypinnedouttominimizecouplingbetweentheanaloganddigitalsectionsofthedevice.
TheAD7866hasverygoodimmunitytonoiseonthepowersuppliesascanbeshownbythePSRRvs.
SupplyRippleFrequencyplots,TPC3atoTPC4b.
However,careshouldbetakenwithregardtogroundingandlayout.
TheprintedcircuitboardthathousestheAD7866shouldbedesignedsuchthattheanaloganddigitalsectionsareseparatedandconfinedtocertainareasoftheboard.
Thisfacilitatestheuseofgroundplanesthatcanbeeasilyseparated.
AminimumREV.
AAD7866–21–etchtechniqueisgenerallybestforgroundplanesbecauseitgivesthebestshielding.
BothAGNDpinsoftheAD7866shouldbesunkintheAGNDplane.
Digitalandanaloggroundplanesshouldbejoinedatonlyoneplace.
IftheAD7866isinasystemwheremultipledevicesrequireanAGNDtoDGNDconnec-tion,theconnectionshouldstillbemadeatonepointonly,astargroundpointthatshouldbeestablishedascloseaspossibletotheAD7866.
Avoidrunningdigitallinesunderthedevicesincethesewillcouplenoiseontothedie.
TheanaloggroundplaneshouldbeallowedtorunundertheAD7866toavoidnoisecoupling.
ThepowersupplylinestotheAD7866shouldusethelargesttracepossibletoprovidelowimpedancepathsandtoreducetheeffectsofglitchesonthepowersupplyline.
Fastswitchingsignalslikeclocksshouldbeshieldedwithdigitalgroundtoavoidradiatingnoisetoothersectionsoftheboard,andclocksignalsshouldneverberunneartheanaloginputs.
Avoidcrossoverofdigitalandanalogsignals.
Tracesonoppositesidesoftheboardshouldrunatrightanglestoeachother.
Thiswillreducetheeffectsoffeedthroughthroughtheboard.
Amicrostriptechniqueisbyfarthebestbutisnotalwayspossiblewithadouble-sidedboard.
Forthistechnique,thecomponentsideoftheboardisdedicatedtogroundplaneswhilesignalsareplacedonthesolderside.
Gooddecouplingisalsoimportant.
Allanalogsuppliesshouldbedecoupledwith10Ftantaluminparallelwith0.
1FcapacitorstoAGND.
Alldigitalsuppliesshouldhaveatleasta0.
1FdiskceramiccapacitortoDGND.
VDRIVEshouldhavea0.
1FceramiccapacitortoDGND.
Toachievethebestresultsfromthesedecouplingcomponents,placethemascloseaspossibletothedevice,ideallyrightupagainstit.
The0.
1Fcapacitorsshouldbecommonceramicorsurface-mounttypes,whichhavelowEffectiveSeriesResistance(ESR)andEffectiveSeriesInductance(ESI),andprovidealowimpedancepathtogroundathighfrequenciesforhandlingtransientcurrentsduetointernallogicswitching.
Figure27showstherecommendedsupplydecouplingscheme.
Forinformationonthedecouplingrequirementsofeachreferenceconfiguration,seetheReferenceConfigurationOptionssection.
AGNDDGNDAD7866DVDDAVDD0.
1F10FAGND0.
1F10FVDRIVE0.
1FFigure27.
RecommendedSupplyDecouplingSchemeEvaluatingtheAD7866PerformanceTherecommendedlayoutfortheAD7866isoutlinedintheevaluationboardfortheAD7866.
Theevaluationboardpackageincludesafullyassembledandtestedevaluationboard,documen-tation,andsoftwareforcontrollingtheboardfromthePCviatheeval-controllerboard.
Theeval-controllerboardcanbeusedinconjunctionwiththeAD7866evaluationboard,aswellasmanyotherAnalogDevicesevaluationboardsendingintheCBdesig-nator,todemonstrate/evaluatetheacanddcperformanceoftheAD7866.
Thesoftwareallowstheusertoperformac(fastFouriertransform)anddc(histogramofcodes)testsontheAD7866.
REV.
A–22–AD7866OUTLINEDIMENSIONS20-LeadThinShrinkSmallOutlinePackage[TSSOP](RU-20)Dimensionsshowninmillimeters20111106.
40BSC4.
504.
404.
30PIN16.
606.
506.
40SEATINGPLANE0.
150.
050.
300.
190.
65BSC1.
20MAX0.
200.
090.
750.
600.
4580COMPLIANTTOJEDECSTANDARDSMO-153ACCOPLANARITY0.
10REV.
AAD7866–23–RevisionHistoryLocationPage2/03—DataSheetchangedfromREV.
0toREV.
A.
AdditiontoFEATURES1AdditiontoSPECIFICATIONS2ChangestoABSOLUTEMAXIMUMRATINGS5ChangestoORDERINGGUIDE5AddedtexttoAnalogInputRangessection12ChangestoFigure913ChangestoPOWERVS.
THROUGHPUTRATEsection18ReplacedFigure2118UpdatedOUTLINEDIMENSIONS22C02672–0–2/03(A)PRINTEDINU.
S.
A.
–24–