Masterz8nrd12

LC2MOS8-Channel,12-BitSerialDataAcquisitionSystemAD7890Rev.
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O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:781.
329.
4700www.
analog.
comFax:781.
461.
31132006AnalogDevices,Inc.
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FEATURESFast12-bitADCwith5.
9μsconversiontimeEightsingle-endedanaloginputchannelsSelectionofinputranges:±10VforAD7890-100Vto4.
096VforAD7890-40Vto2.
5VforAD7890-2AllowsseparateaccesstomultiplexerandADCOn-chiptrack/holdamplifierOn-chipreferenceHigh-speed,flexible,serialinterfaceSinglesupply,low-poweroperation(50mWmaximum)Power-downmode(75μWtyp)GENERALDESCRIPTIONTheAD7890isan8-channel12-bitdataacquisitionsystem.
Thepartcontainsaninputmultiplexer,anon-chiptrack/holdamplifier,ahighspeed12-bitADC,a2.
5Vreference,andahighspeed,serialinterface.
Thepartoperatesfromasingle5Vsupplyandacceptsananaloginputrangeof±10V(AD7890-10),0Vto4.
096V(AD7890-4),and0Vto2.
5V(AD7890-2).
Themultiplexeronthepartisindependentlyaccessible.
Thisallowstheusertoinsertanantialiasingfilterorsignalconditioning,ifrequired,betweenthemultiplexerandtheADC.
Thismeansthatoneantialiasingfiltercanbeusedforalleightchannels.
Connectionofanexternalcapacitorallowstheusertoadjustthetimegiventothemultiplexersettlingtoincludeanyexternaldelaysinthefilterorsignalconditioningcircuitry.
OutputdatafromtheAD7890isprovidedviaahighspeedbidirectionalserialinterfaceport.
Thepartcontainsanon-chipcontrolregister,allowingcontrolofchannelselection,conversionstart,andpower-downviatheserialport.
Versatile,highspeedlogicensureseasyinterfacingtoserialportsonmicrocontrollersanddigitalsignalprocessors.
Inadditiontothetraditionaldcaccuracyspecificationssuchaslinearity,full-scale,andoffseterrors,theAD7890isalsospecifiedfordynamicperformanceparametersincludingharmonicdistortionandsignal-to-noiseratio.
FUNCTIONALBLOCKDIAGRAMTRACK/HOLD2kAD7890CEXTCONVSTMUXOUTSHAINREFOUT/REFINAGNDAGNDDGNDSCLKTFSRFSDATAOUTDATAINSMODEVIN1VDDVIN2VIN3VIN4VIN5VIN6VIN7VIN81NOSCALINGONAD7890-2CLOCKOUTPUT/CONTROLREGISTER12-BITADCMUX2.
5VREFERENCESIGNALSCALING1SIGNALSCALING1SIGNALSCALING1SIGNALSCALING1SIGNALSCALING1SIGNALSCALING1SIGNALSCALING1SIGNALSCALING1CLKIN01357-001Figure1.
Powerdissipationinnormalmodeislowat30mWtypicalandthepartcanbeplacedinastandby(power-down)modeifitisnotrequiredtoperformconversions.
TheAD7890isfabricatedinAnalogDevices,Inc.
'sLinearCompatibleCMOS(LC2MOS)process,amixedtechnologyprocessthatcombinesprecisionbipolarcircuitswithlowpowerCMOSlogic.
Thepartisavailableina24-lead,0.
3"wide,plasticorceramicdual-in-linepackageorina24-leadsmalloutlinepackage(SOIC_W).
PRODUCTHIGHLIGHTS1.
Complete12-BitDataAcquisitionSystem-on-a-Chip.
TheAD7890isacompletemonolithicADCcombiningan8-channelmultiplexer,12-bitADC,2.
5Vreference,andatrack/holdamplifieronasinglechip.
2.
SeparateAccesstoMultiplexerandADC.
TheAD7890providesaccesstotheoutputofthemultiplexerallowingoneantialiasingfilterfor8channels—aconsiderablesavingsoverthe8antialiasingfiltersrequiredifthemultiplexerisinternallyconnectedtotheADC.
3.
HighSpeedSerialInterface.
ThepartprovidesahighspeedserialinterfaceforeasyconnectiontoserialportsofmicrocontrollersandDSPprocessors.
AD7890*PRODUCTPAGEQUICKLINKSLastContentUpdate:02/23/2017COMPARABLEPARTSViewaparametricsearchofcomparableparts.
DOCUMENTATIONApplicationNotesAN-413:EvaluationBoardfortheAD7890,12-BitSerial,DataAcquisitionSystemDataSheetAD7890:LC2MOS8-Channel,12-BitSerial,DataAcquisitionSystemDataSheetAD7890:MilitaryDataSheetProductHighlight8-to18-BitSARADCs.
.
.
FromtheLeaderinHighPerformanceAnalogREFERENCEMATERIALSTechnicalArticlesMS-2210:DesigningPowerSuppliesforHighSpeedADCDESIGNRESOURCESAD7890MaterialDeclarationPCN-PDNInformationQualityAndReliabilitySymbolsandFootprintsDISCUSSIONSViewallAD7890EngineerZoneDiscussions.
SAMPLEANDBUYVisittheproductpagetoseepricingoptions.
TECHNICALSUPPORTSubmitatechnicalquestionorfindyourregionalsupportnumber.
DOCUMENTFEEDBACKSubmitfeedbackforthisdatasheet.
ThispageisdynamicallygeneratedbyAnalogDevices,Inc.
,andinsertedintothisdatasheet.
Adynamicchangetothecontentonthispagewillnottriggerachangetoeithertherevisionnumberorthecontentoftheproductdatasheet.
Thisdynamicpagemaybefrequentlymodified.
AD7890Rev.
C|Page2of28TABLEOFCONTENTSFeatures1GeneralDescription.
1FunctionalBlockDiagram1ProductHighlights1RevisionHistory2Specifications.
3TimingSpecifications5AbsoluteMaximumRatings.
6ESDCaution.
6PinConfigurationandFunctionDescriptions.
7Terminology.
9ControlRegister.
10TheoryofOperation11ConverterDetails.
11CircuitDescription.
11Track/HoldAmplifier12Reference13TimingandControl13CEXTFunctioning.
16SerialInterface17Self-ClockingMode17ExternalClockingMode18SimplifyingtheInterface.
19Microprocessor/MicrocontrollerInterface.
20AD7890to8051Interface20AD7890to68HC11Interface.
20AD7890toADSP-2101Interface.
21AD7890toDSP56000Interface21AD7890toTMS320C25/30Interface.
21AntialiasingFilter.
22Performance.
23Linearity.
23Noise23DynamicPerformance.
24EffectiveNumberofBits24OutlineDimensions.
25OrderingGuide27REVISIONHISTORY9/06—Rev.
BtoRev.
CUpdatedFormat.
UniversalChangestoTable1.
3UpdatedOutlineDimensions.
25ChangestoOrderingGuide272/01—Rev.
AtoRev.
BAD7890Rev.
C|Page3of28SPECIFICATIONSVDD=5V,AGND=DGND=0V,REFIN=2.
5V,fCLKIN=2.
5MHzexternal,MUXOUTconnecttoSHAIN.
AllspecificationsTMINtoTMAX,unlessotherwisenoted.
Table1.
ParameterAVersions1BVersionsSVersionUnitTestConditions/CommentsDYNAMICPERFORMANCEUsingexternalCONVST,anychannelSignalto(Noise+Distortion)Ratio2707070dBminfIN=10kHzsinewave,fSAMPLE=100kHz3TotalHarmonicDistortion(THD)2777777dBmaxfIN=10kHzsinewave,fSAMPLE=100kHz3PeakHarmonicorSpuriousNoise2787878dBmaxfIN=10kHzsinewave,fSAMPLE=100kHz3IntermodulationDistortionfa=9kHz,fb=9.
5kHz,fSAMPLE=100kHz32ndOrderTerms808080dBtyp3rdOrderTerms808080dBtypChannel-to-ChannelIsolation2808080dBmaxfIN=1kHzsinewaveDCACCURACYResolution121212BitsMin.
ResolutionforWhichNoMissingCodesAreGuaranteed121212BitsRelativeAccuracy2±1±0.
5±1LSBmaxDifferentialNonlinearity2±1±1±1LSBmaxPositiveFull-ScaleError2±2.
5±2.
5±2.
5LSBmaxFull-ScaleErrorMatch4222LSBmaxAD7890-2,AD7890-4UnipolarOffsetError2±2±2±2LSBmaxUnipolarOffsetErrorMatch222LSBmaxAD7890-10OnlyNegativeFull-ScaleError2±2±2±2LSBmaxBipolarZeroError2±5±5±5LSBmaxBipolarZeroErrorMatch222LSBmaxANALOGINPUTSAD7890-10InputVoltageRange±10±10±10VoltsInputResistance202020kΩminAD7890-4InputVoltageRange0to4.
0960to4.
0960to4.
096VoltsInputResistance111111kΩminAD7890-2InputVoltageRange0to2.
50to2.
50to2.
5VoltsInputCurrent5050200nAmaxMUXOUTOUTPUTOutputVoltageRange0to2.
50to2.
50to2.
5VoltsOutputResistanceAD7890-10,AD7890-43/53/53/5kΩmin/kΩmaxAD7890-2222kΩmaxAssumingVINisdrivenfromlowimpedanceSHAININPUTInputVoltageRange0to2.
50to2.
50to2.
5VoltsInputCurrent±50±50±50nAmaxREFERENCEOUTPUT/INPUTREFINInputVoltageRange2.
375/2.
6252.
375/2.
6252.
375/2.
625Vmin/Vmax2.
5V±5%InputImpedance1.
61.
61.
6kΩminResistorconnectedtointernalreferencenodeInputCapacitance5101010pFmaxREFOUTOutputVoltage2.
52.
52.
5VnomREFOUTError@25°C±10±10±10mVmaxTMINtoTMAX±20±20±25mVmaxREFOUTTemperatureCoefficient252525ppm/°CtypREFOUTOutputImpedance222kΩnomAD7890Rev.
C|Page4of28ParameterAVersions1BVersionsSVersionUnitTestConditions/CommentsLOGICINPUTSInputHighVoltage,VINH2.
42.
42.
4VminVDD=5V±5%InputLowVoltage,VINL0.
80.
80.
8VmaxVDD=5V±5%InputCurrent,IIN±10±10±10μAmaxVIN=0VtoVDDInputCapacitance,CIN5101010pFmaxLOGICOUTPUTSOutputHighVoltage,VOH4.
04.
04.
0VminISOURCE=200μAOutputLowVoltage,VOL0.
40.
40.
4VmaxISINK=1.
6mASerialDataOutputCodingAD7890-10TwosComplementAD7890-4Straight(Natural)BinaryAD7890-2Straight(Natural)BinaryCONVERSIONRATEConversionTime5.
95.
95.
9μsmaxfCLKIN=2.
5MHz,MUXOUT,connectedtoSHAINTrack/HoldAcquisitionTime2,5222μsmaxPOWERREQUIREMENTSVDD555Vnom±5%forspecifiedperformanceIDD(NormalMode)101010mAmaxLogicinputs=0VorVDDIDD(StandbyMode)6@25°C151515μAtypLogicinputs=0VorVDDPowerDissipationNormalMode505050mWmaxTypically30mWStandbyMode@25°C757575μWtyp1Temperaturerangesareasfollows:A,BVersions:40°Cto+85°C;SVersion:55°Cto+125°C.
2SeetheTerminologysection.
3Thissamplerateisonlyachievablewhenusingthepartinexternalclockingmode.
4Full-scaleerrormatchappliestopositivefullscalefortheAD7890-2andAD7890-4.
ItappliestobothpositiveandnegativefullscalefortheAD7890-10.
5Sampletested@25°Ctoensurecompliance.
6AnaloginputsonAD7890-10mustbeat0Vtoachievecorrectpower-downcurrent.
AD7890Rev.
C|Page5of28TIMINGSPECIFICATIONSVDD=5V±5%,AGND=DGND=0V,REFIN=2.
5V,fCLKIN=2.
5MHzexternal,MUXOUTconnectedtoSHAIN.
Parameter1,2LimitatTMIN,TMAX(A,B,SVersions)UnitConditions/CommentsfCLKIN3100kHzminMasterClockFrequency.
Forspecifiedperformance.
2.
5MHzmaxtCLKININLO0.
3*tCLKINnsminMasterClockInputLowTime.
tCLKINHI03*tCLKINnsminMasterClockInputHighTime.
tr425nsmaxDigitalOutputRiseTime.
Typically10ns.
tf425nsmaxDigitalOutputFallTime.
Typically10ns.
tCONVERT5.
9μsmaxConversionTime.
tCST100nsminCONVSTPulseWidth.
Self-ClockingModet1tCLKINHI+50nsmaxRFSLowtoSCLKFallingEdge.
t2525nsmaxRFSLowtoDataValidDelay.
t3tCLKINHInsnomSCLKHighPulseWidth.
t4tCLKINLOnsnomSCLKLowPulseWidth.
t5520nsmaxSCLKRisingEdgetoDataValidDelay.
t640nsmaxSCLKRisingEdgetoRFSDelay.
t7650nsmaxBusRelinquishTimeafterRisingEdgeofSCLK.
t80nsminTFSLowtoSCLKFallingEdge.
tCLKIN+50nsmaxt90nsminDataValidtoTFSFallingEdgeSetupTime(A2AddressBit).
t1020nsminDataValidtoSCLKFallingEdgeSetupTime.
t1110nsminDataValidtoSCLKFallingEdgeHoldTime.
t1220nsminTFStoSCLKFallingEdgeHoldTime.
ExternalClockingModet1320nsminRFSLowtoSCLKFallingEdgeSetupTime.
t14540nsmaxRFSLowtoDataValidDelay.
t1550nsminSCLKHighPulseWidth.
t1650nsminSCLKLowPulseWidth.
t17535nsmaxSCLKRisingEdgetoDataValidDelay.
t1820nsminRFStoSCLKFallingEdgeHoldTime.
t19650nsmaxBusRelinquishTimeafterRisingEdgeofRFS.
t19A690nsmaxBusRelinquishTimeafterRisingEdgeofSCLK.
t2020nsminTFSLowtoSCLKFallingEdgeSetupTime.
t2110nsminDataValidtoSCLKFallingEdgeSetupTime.
t2215nsminDataValidtoSCLKFallingEdgeHoldTime.
t2340nsminTFStoSCLKFallingEdgeHoldTime.
1Sampletestedat25°Ctoensurecompliance.
Allinputsignalsarespecifiedwithtr=tf=5ns(10%to90%of5V)andtimedfromavoltagelevelof1.
6V.
2SeeFigure10toFigure13.
3TheAD7890isproductiontestedwithfCLKINat2.
5MHz.
Itisguaranteedbycharacterizationtooperateat100kHz.
4Specifiedusing10%and90%pointsonwaveformofinterest.
5ThesenumbersaremeasuredwiththeloadcircuitofFigure2anddefinedasthetimerequiredfortheoutputtocross0.
8Vor2.
4V.
6Thesenumbersarederivedfromthemeasuredtimetakenbythedataoutputtochange0.
5VwhenloadedwiththecircuitofFigure2.
Themeasurednumberisthenextrapolatedbacktoremoveeffectsofchargingordischargingthe50pFcapacitor.
Thismeansthatthetimesquotedinthetimingcharacteristicsarethetruebusrelinquishtimesofthepartandassuchareindependentofexternalbusloadingcapacitances.
TOOUTPUTPIN2.
1V1.
6mA200A50pF01357-002Figure2.
LoadCircuitforAccessTimeandBusRelinquishTimeAD7890Rev.
C|Page6of28ABSOLUTEMAXIMUMRATINGSTA=25°C,unlessotherwisenoted.
ParameterRatingVDDtoAGND0.
3Vto+7VVDDtoDGND0.
3Vto+7VAnalogInputVoltagetoAGNDAD7890-10,AD7890-4±17VAD7890-25V,+10VReferenceInputVoltagetoAGND0.
3VtoVDD+0.
3VDigitalInputVoltagetoDGND0.
3VtoVDD+0.
3VDigitalOutputVoltagetoDGND0.
3VtoVDD+0.
3VOperatingTemperatureRangeCommercial(A,BVersions)40°Cto+85°CExtended(SVersion)55°Cto+125°CStorageTemperatureRange65°Cto+150°CJunctionTemperature150°CPDIPPackage,PowerDissipation450mWθJAThermalImpedance105°C/WLeadTemperature(Soldering,10sec)260°CCERDIPPackage,PowerDissipation450mWθJAThermalImpedance70°C/WLeadTemperature(Soldering,10sec)300°CSOIC_WPackage,PowerDissipation450mWθJAThermalImpedance75°C/WLeadTemperature,SolderingVaporPhase(60sec)215°CInfrared(15sec)220°CStressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thisisastressratingonly;functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
ESDCAUTIONAD7890Rev.
C|Page7of28PINCONFIGURATIONANDFUNCTIONDESCRIPTIONS242322212019181716151413123456789101112REFOUT/REFINCONVSTTFSRFSDATAOUTDATAINVDDVIN8VIN7VIN6VIN5VIN4VIN3VIN2VIN1AD7890TOPVIEW(NottoScale)AGNDAGNDSHAINMUXOUTDGNDCLKINSCLKCEXTSMODE01357-003Figure3.
PinConfigurationTable2.
PinFunctionDescriptionsPinNo.
MnemonicDescription1AGNDAnalogGround.
Groundreferencefortrack/hold,comparator,andDAC.
2SMODEControlInput.
Determineswhetherthepartoperatesinitsexternalclocking(slave)orself-clocking(master)serialmode.
WithSMODEatalogiclow,thepartisinitsself-clockingserialmodewithRFSandSCLKasoutputs.
Thisself-clockingmodeisusefulforconnectiontoshiftregistersortoserialportsofDSPprocessors.
WithSMODEatalogichigh,thepartisinitsexternalclockingserialmodewithSCLKandRFSasinputs.
Thisexternalclockingmodeisusefulforconnectiontotheserialportofmicrocontrollers,suchasthe8xC51andthe68HCxx,andforconnectiontotheserialportsofDSPprocessors.
3DGNDDigitalGround.
Groundreferencefordigitalcircuitry.
4CEXTExternalCapacitor.
Anexternalcapacitorisconnectedtothispintodeterminethelengthoftheinternalpulse(seetheControlRegistersection).
Largercapacitancesonthispinextendthepulsetoallowforsettlingtimedelaysthroughanexternalantialiasingfilterorsignalconditioningcircuitry.
5CONVSTConvertStart.
Edge-triggeredlogicinput.
Alow-to-hightransitiononthisinputputsthetrack/holdintoholdandinitiatesconversioniftheinternalpulsehastimedout(seetheControlRegistersection).
IftheinternalpulseisactivewhentheCONVSTgoeshigh,thetrack/holddoesnotproceedtoholduntilthepulsetimesout.
IftheinternalpulsetimesoutwhenCONVSTgoeshigh,therisingedgeofCONVSTdrivesthetrack/holdintoholdandinitiatesconversion.
6CLKINClockInput.
AnexternalTTL-compatibleclockisappliedtothisinputpintoprovidetheclocksourcefortheconversionsequence.
Intheself-clockingserialmode,theSCLKoutputisderivedfromthisCLKINpin.
7SCLKSerialClockInput.
Intheexternalclocking(slave)mode(seetheSerialInterfacesection),thisisanexternallyappliedserialclockusedtoloadserialdatatothecontrolregisterandtoaccessdatafromtheoutputregister.
Intheself-clocking(master)mode,theinternalserialclock,whichisderivedfromtheclockinput(CLKIN),appearsonthispin.
Onceagain,itisusedtoloadserialdatatothecontrolregisterandtoaccessdatafromtheoutputregister.
8TFSTransmitFrameSynchronizationPulse.
Activelowlogicinputwithserialdataexpectedafterthefallingedgeofthissignal.
9RFSReceiveFrameSynchronizationPulse.
Intheexternalclockingmode,thispinisanactivelowlogicinputwithRFSprovidedexternallyasastrobeorframingpulsetoaccessserialdatafromtheoutputregister.
Intheself-clockingmode,itisanactivelowoutput,whichisinternallygeneratedandprovidesastrobeorframingpulseforserialdatafromtheoutputregister.
Forapplicationswhichrequirethatdatabetransmittedandreceivedatthesametime,RFSandTFSshouldbeconnectedtogether.
10DATAOUTSerialDataOutput.
Sixteenbitsofserialdataareprovidedwithoneleadingzero,precedingthethreeaddressbitsofthecontrolregisterandthe12bitsofconversiondata.
SerialdataisvalidonthefallingedgeofSCLKforsixteenedgesafterRFSgoeslow.
OutputcodingfromtheADCistwoscomplementfortheAD7890-10andstraightbinaryfortheAD7890-4andAD7890-2.
11DATAINSerialDataInput.
Serialdatatobeloadedtothecontrolregisterisprovidedatthisinput.
ThefirstfivebitsofserialdataareloadedtothecontrolregisteronthefirstfivefallingedgesofSCLKafterTFSgoeslow.
SerialdataonsubsequentSCLKedgesisignoredwhileTFSremainslow.
12VDDPositiveSupplyVoltage,5V±5%.
13MUXOUTMultiplexerOutput.
Theoutputofthemultiplexerappearsatthispin.
Theoutputvoltagerangefromthisoutputis0Vto2.
5Vforthenominalanaloginputrangetotheselectedchannel.
Theoutputimpedanceofthisoutputisnominally3.
5kΩ.
Ifnoexternalantialiasingfilterisrequired,MUXOUTshouldbeconnectedtoSHAIN.
AD7890Rev.
C|Page8of28PinNo.
MnemonicDescription14SHAINTrack/HoldInput.
Theinputtotheon-chiptrack/holdisappliedtothispin.
Itisahighimpedanceinputandtheinputvoltagerangeis0Vto2.
5V.
15AGNDAnalogGround.
Groundreferencefortrack/hold,comparator,andDAC.
16VIN1AnalogInputChannel1.
Single-endedanaloginput.
Theanaloginputrangeonis±10V(AD7890-10),0Vto4.
096V(AD7890-4),and0Vto2.
5V(AD7890-2).
ThechanneltobeconvertedisselectedusingtheA0,A1,andA2bitsinthecontrolregister.
Themultiplexerhasguaranteedbreak-before-makeoperation.
17VIN2AnalogInputChannel2.
Single-endedanaloginput.
Theanaloginputrangeonis±10V(AD7890-10),0Vto4.
096V(AD7890-4),and0Vto2.
5V(AD7890-2).
ThechanneltobeconvertedisselectedusingtheA0,A1,andA2bitsinthecontrolregister.
Themultiplexerhasguaranteedbreak-before-makeoperation.
18VIN3AnalogInputChannel3.
Single-endedanaloginput.
Theanaloginputrangeonis±10V(AD7890-10),0Vto4.
096V(AD7890-4),and0Vto2.
5V(AD7890-2).
ThechanneltobeconvertedisselectedusingtheA0,A1,andA2bitsinthecontrolregister.
Themultiplexerhasguaranteedbreak-before-makeoperation.
19VIN4AnalogInputChannel4.
Single-endedanaloginput.
Theanaloginputrangeonis±10V(AD7890-10),0Vto4.
096V(AD7890-4),and0Vto2.
5V(AD7890-2).
ThechanneltobeconvertedisselectedusingtheA0,A1,andA2bitsinthecontrolregister.
Themultiplexerhasguaranteedbreak-before-makeoperation.
20VIN5AnalogInputChannel5.
Single-endedanaloginput.
Theanaloginputrangeonis±10V(AD7890-10),0Vto4.
096V(AD7890-4),and0Vto2.
5V(AD7890-2).
ThechanneltobeconvertedisselectedusingtheA0,A1,andA2bitsinthecontrolregister.
Themultiplexerhasguaranteedbreak-before-makeoperation.
21VIN6AnalogInputChannel6.
Single-endedanaloginput.
Theanaloginputrangeonis±10V(AD7890-10),0Vto4.
096V(AD7890-4),and0Vto2.
5V(AD7890-2).
ThechanneltobeconvertedisselectedusingtheA0,A1,andA2bitsinthecontrolregister.
Themultiplexerhasguaranteedbreak-before-makeoperation.
22VIN7AnalogInputChannel7.
Single-endedanaloginput.
Theanaloginputrangeonis±10V(AD7890-10),0Vto4.
096V(AD7890-4),and0Vto2.
5V(AD7890-2).
ThechanneltobeconvertedisselectedusingtheA0,A1,andA2bitsinthecontrolregister.
Themultiplexerhasguaranteedbreak-before-makeoperation.
23VIN8AnalogInputChannel8.
Single-endedanaloginput.
Theanaloginputrangeonis±10V(AD7890-10),0Vto4.
096V(AD7890-4)and0Vto2.
5V(AD7890-2).
ThechanneltobeconvertedisselectedusingtheA0,A1,andA2bitsinthecontrolregister.
Themultiplexerhasguaranteedbreak-before-makeoperation.
24REFOUT/REFINVoltageReferenceOutput/Input.
Thepartcanbeusedwitheitheritsowninternalreferenceorwithanexternalreferencesource.
Theon-chip2.
5Vreferencevoltageisprovidedatthispin.
Whenusingthisinternalreferenceasthereferencesourceforthepart,REFOUTshoulddecoupledtoAGNDwitha0.
1μFdiscceramiccapacitor.
Theoutputimpedanceofthisreferencesourceistypically2kΩ.
Whenusinganexternalreferencesourceasthereferencevoltageforthepart,thereferencesourceshouldbeconnectedtothispin.
Thisoverdrivestheinternalreferenceandprovidesthereferencesourceforthepart.
TheREFINinputisbufferedon-chip.
ThenominalreferencevoltageforcorrectoperationoftheAD7890is2.
5V.
AD7890Rev.
C|Page9of28TERMINOLOGYSignalto(Noise+Distortion)RatioThisisthemeasuredratioofsignalto(noise+distortion)attheoutputoftheA/Dconverter.
Thesignalisthermsamplitudeofthefundamental.
Noiseisthermssumofallnonfundamentalsignalsuptohalfthesamplingfrequency(fS/2),excludingdc.
Theratioisdependentuponthenumberofquantizationlevelsinthedigitizationprocess;themorelevels,thesmallerthequantizationnoise.
Thetheoreticalsignalto(noise+distortion)ratioforanidealN-bitconverterwithasinewaveinputisgivenby:Signalto(Noise+Distortion)=(6.
02N+1.
76)dBThus,fora12-bitconverter,thisis74dB.
TotalHarmonicDistortionTotalharmonicdistortion(THD)istheratioofthermssumofharmonicstothefundamental.
FortheAD7890,itisdefinedas12625242322log20)dB(VVVVVVTHD++++=where:V1isthermsamplitudeofthefundamentalandV2,V3,V4,V5,andV6arethermsamplitudesofthesecondthroughthesixthharmonics.
PeakHarmonicorSpuriousNoisePeakharmonicorspuriousnoiseisdefinedastheratioofthermsvalueofthenextlargestcomponentintheADCoutputspectrum(uptofS/2andexcludingdc)tothermsvalueofthefundamental.
Normally,thevalueofthisspecificationisdeterminedbythelargestharmonicinthespectrum,butforpartswheretheharmonicsareburiedinthenoisefloor,itisdeterminedbyanoisepeak.
IntermodulationDistortionWithinputsconsistingofsinewavesattwofrequencies,faandfb,anyactivedevicewithnonlinearitiescreatesdistortionproductsatsumanddifferencefrequenciesofmfa±nfbwherem,n=0,1,2,3,andsoon.
Intermodulationtermsarethoseforwhichneithermnornareequaltozero.
Forexample,thesecond-ordertermsinclude(fa+fb)and(fafb),whilethethird-ordertermsinclude(2fa+fb),(2fafb),(fa+2fb),and(fa2fb).
TheAD7890istestedusingtheCCIFstandardwheretwoinputfrequenciesnearthetopendoftheinputbandwidthareused.
Inthiscase,thesecondandthirdordertermsareofdifferentsignificance.
Thesecond-ordertermsareusuallydistancedinfrequencyfromtheoriginalsinewaveswhilethethird-ordertermsareusuallyatafrequencyclosetotheinputfrequencies.
Asaresult,thesecond-andthird-ordertermsarespecifiedseparately.
ThecalculationoftheintermodulationdistortionisaspertheTHDspecificationwhereitistheratioofthermssumoftheindividualdistortionproductstothermsamplitudeofthefundamentalexpressedindBs.
Channel-to-ChannelIsolationChannel-to-channelisolationisameasureofthelevelofcrosstalkbetweenchannels.
Itismeasuredbyapplyingafull-scale1kHzsignaltoanyoneoftheotherseveninputsanddetermininghowmuchthatsignalisattenuatedinthechannelofinterest.
Thefiguregivenistheworstcaseacrossalleightchannels.
RelativeAccuracyRelativeaccuracyorendpointnonlinearityisthemaximumdeviationfromastraightlinepassingthroughtheendpointsoftheADCtransferfunction.
DifferentialNonlinearityThisisthedifferencebetweenthemeasuredandtheideal1LSBchangebetweenanytwoadjacentcodesintheADC.
PositiveFull-ScaleError(AD7890-10)Thisisthedeviationofthelastcodetransition(01.
.
.
110to01.
.
.
111)fromtheideal(4*REFIN1LSB)afterthebipolarzeroerrorhasbeenadjustedout.
PositiveFull-ScaleError(AD7890-4)Thisisthedeviationofthelastcodetransition(11.
.
.
110to11.
.
.
111)fromtheideal(1.
638*REFIN1LSB)aftertheunipolaroffseterrorhasbeenadjustedout.
PositiveFull-ScaleError(AD7890-2)Thisisthedeviationofthelastcodetransition(11.
.
.
110to11.
.
.
111)fromtheideal(REFIN1LSB)aftertheunipolaroffseterrorhasbeenadjustedout.
BipolarZeroError(AD7890-10)Thisisthedeviationofthemidscaletransition(all0stoall1s)fromtheideal0V(AGND).
UnipolarOffsetError(AD7890-2,AD7890-4)Thisisthedeviationofthefirstcodetransition(00.
.
.
000to00.
.
.
001)fromtheideal0V(AGND).
NegativeFull-ScaleError(AD7890-10)Thisisthedeviationofthefirstcodetransition(10.
.
.
000to10.
.
.
001)fromtheideal(4*REFIN+1LSB)afterbipolarzeroerrorhasbeenadjustedout.
Track/HoldAcquisitionTimeTrack/holdacquisitiontimeisthetimerequiredfortheoutputofthetrack/holdamplifiertoreachitsfinalvalue,within±1/2LSB,aftertheendofconversion(thepointatwhichthetrack/holdreturnstotrackmode).
ItalsoappliestosituationswhereachangeintheselectedinputchanneltakesplaceorwherethereisastepinputchangeontheinputvoltageappliedtotheselectedVINinputoftheAD7890.
Itmeansthattheusermustwaitforthedurationofthetrack/holdacquisitiontimeaftertheendofconversionorafterachannelchange/stepinputchangetoVINbeforestartinganotherconversion,toensurethatthepartoperatestospecification.
AD7890Rev.
C|Page10of28CONTROLREGISTERThecontrolregisterfortheAD7890contains5bitsofinformation.
Sixserialclockpulsesmustbeprovidedtothepartinordertowritedatatothecontrolregister(sevenifthewriteisrequiredtoputthepartinstandbymode).
IfTFSreturnshighbeforesixserialclockcycles,thennodatatransfertakesplacetothecontrolregisterandthewritecyclehastoberestartedtowritethedatatothecontrolregister.
If,however,theCONVbitoftheregisterissettoaLogic1,thenaconversionisinitiatedwheneveracontrolregisterwritetakesplaceregardlessofhowmanyserialclockcyclestheTFSremainslowfor.
Thedefault(power-on)conditionofallbitsinthecontrolregisteris0.
MSBLSBA2A1A0CONVSTBYTable3.
BitNameDescriptionA2AddressInput.
Thisinputisthemostsignificantaddressinputformultiplexerchannelselection.
A1AddressInput.
Thisisthe2ndmostsignificantaddressinputformultiplexerchannelselection.
A0AddressInput.
Leastsignificantaddressinputformultiplexerchannelselection.
Whentheaddressiswrittentothecontrolregister,aninternalpulseisinitiated,thepulsewidthofwhichisdeterminedbythevalueofcapacitanceontheCEXTpin.
Whenthispulseisactive,itensurestheconversionprocesscannotbeactivated.
Thisallowsforthemultiplexersettlingtime,track/holdacquisitiontimebeforethetrack/holdgoesintohold,andtheconversionisinitiated.
InapplicationswherethereisanantialiasingfilterbetweentheMUXOUTpinandtheSHAINpin,thefiltersettlingtimecanbetakenintoaccountbeforetheinputontheSHAINpinissampled.
Whentheinternalpulsetimesout,thetrack/holdgoesintoholdandconversionisinitiated.
CONVConversionStart.
Writinga1tothisbitinitiatesaconversioninasimilarmannertotheCONVSTinput.
Continuousconversionstartsdonottakeplacewhenthereisa1inthislocation.
Theinternalpulseandtheconversionprocessareinitiatedafterthesixthserialclockcycleofthewriteoperationifa1iswrittentothisbit.
Witha1inthisbit,thehardwareconversionstart(theCONVSTinput)isdisabled.
Writinga0tothisbitenablesthehardwareCONVSTinput.
STBYStandbyModeInput.
Writinga1tothisbitplacesthedeviceinitsstandby,orpower-down,mode.
Writinga0tothisbitplacesthedeviceinitsnormaloperatingmode.
ThepartdoesnotenteritsstandbymodeuntiltheseventhfallingedgeofSCLKinawriteoperation.
Therefore,thepartrequiressevenserialclockpulsesinitsserialwriteoperationifitisrequiredtoputthepartintostandby.
AD7890Rev.
C|Page11of28THEORYOFOPERATIONCONVERTERDETAILSTheAD7890isan8-channel,12-bit,singlesupply,serialdataacquisitionsystem.
Itprovidestheuserwithsignalscaling,multiplexer,track/hold,reference,ADC,andversatileseriallogicfunctionsonasinglechip.
Thesignalscalingallowstheparttohandle±10Vinputsignals(AD7890-10)and0Vto4.
096Vinputsignals(AD7890-4)whileoperatingfromasingle5Vsupply.
TheAD7890-2containsnosignalscalingandacceptsananaloginputrangeof0Vto2.
5V.
Thepartoperatesfroma2.
5Vreference,whichcanbeprovidedfromthepart'sowninternalreferenceorfromanexternalreferencesource.
Unlikeothersinglechipdataacquisitionsolutions,theAD7890providestheuserwithseparateaccesstothemultiplexerandtheADC.
ThismeansthattheflexibilityofseparatemultiplexerandADCsolutionsisnotsacrificedwiththeone-chipsolution.
Withaccesstothemultiplexeroutput,theusercanimplementexternalsignalconditioningbetweenthemultiplexerandthetrack/hold.
Itmeansthatoneantialiasingfiltercanbeusedontheoutputofthemultiplexertoprovidetheantialiasingfunctionforalleightchannels.
ConversionisinitiatedontheAD7890eitherbypulsingtheCONVSTinputorbywritingaLogic1totheCONVbitofthecontrolregister.
WhenusingthehardwareCONVSTinput,ontherisingedgeoftheCONVSTsignal,theon-chiptrack/holdgoesfromtracktoholdmodeandtheconversionsequenceisstarted,providedtheinternalpulsehastimedout.
Thisinternalpulse(whichappearsattheCEXTpin)isinitiatedwheneverthemultiplexeraddressisloadedtotheAD7890controlregister.
Thispulsegoesfromhightolowwhenaserialwritetothepartisinitiated.
ItstartstodischargeonthesixthfallingclockedgeofSCLKinaserialwriteoperationtothepart.
Thetrack/holdcannotgointoholdandconversioncannotbeinitiateduntiltheCEXTpinhascrosseditstriggerpointof2.
5V.
ThedischargetimeofthevoltageonCEXTdependsuponthevalueofcapacitorconnectedtotheCEXTpin(seetheCEXTFunctioningsection).
Thefactthatthepulseisinitiatedeverytimeawritetothecontrolregistertakesplacemeansthatthesoftwareconversionstartandtrack/holdsignalisalwaysdelayedbytheinternalpulse.
TheconversionclockforthepartisgeneratedfromtheclocksignalappliedtotheCLKINpinofthepart.
ConversiontimefortheAD7890is5.
9μsfromtherisingedgeofthehardwareCONVSTsignalandthetrack/holdacquisitiontimeis2μs.
Toobtainoptimumperformancefromthepart,thedatareadoperationorcontrolregisterwriteoperationshouldnotoccurduringtheconversionorduring500nspriortothenextconversion.
Thisallowstheparttooperateatthroughputratesupto117kHzintheexternalclockingmodeandachievedatasheetspecifications.
Thepartcanoperateatslightlyhigherthroughputrates(upto127kHz),againinexternalclockingmodewithdegradedperformance(seetheTimingandControlsection).
Thethroughputrateforself-clockingmodeislimitedbytheserialclockrateto78kHz.
Allunusedinputsshouldbeconnectedtoavoltagewithinthenominalanaloginputrangetoavoidnoisepickup.
OntheAD7890-10,ifanyoneoftheinputchannelswhicharenotbeingconvertedgoesmorenegativethan12V,itcaninterferewiththeconversionontheselectedchannel.
CIRCUITDESCRIPTIONTheAD7890isofferedasthreeparttypes:theAD7890-10handlesa±10Vinputvoltagerange,theAD7890-4handlesa0Vto4.
096Vinputrange,whiletheAD7890-2handlesa0Vto2.
5Vinputvoltagerange.
AD7890-10AnalogInputFigure4showstheanaloginputsectionfortheAD7890-10.
Theanaloginputrangeforeachoftheanaloginputsis±10Vintoaninputresistanceoftypically33kΩ.
Thisinputisbenignwithnodynamicchargingcurrentswiththeresistorattenuatorstagefollowedbythemultiplexerand,incaseswhereMUXOUTisconnectedtoSHAIN,thisisfollowedbythehighinputimpedancestageofthetrack/holdamplifier.
ThedesignedcodetransitionsoccuronsuccessiveintegerLSBvalues(suchas:1LSB,2LSBs,3LSBs.
.
.
).
Outputcodingistwoscomplementbinarywith1LSBFSR/4096=20V/4096=4.
88mV.
Theidealinput/outputtransferfunctionisshowninTable4.
2.
5VREFERENCE30k2k7.
5k200110kAD7890-10REFOUT/REFINAGNDVINX1EQUIVALENTON-RESISTANCEOFMULTIPLEXERMUXOUTTOADCREFERENCECIRCUITRY01357-004Figure4.
AD7890-10AnalogInputStructureAD7890Rev.
C|Page12of28Table4.
IdealInput/OutputCodeTablefortheAD7890-10AnalogInput1DigitalOutputCodeTransition+FSR/21LSB2(9.
995117V)011.
.
.
110to011.
.
.
111+FSR/22LSBs(9.
990234V)011.
.
.
101to011.
.
.
110+FSR/23LSBs(9.
985352V)011.
.
.
100to011.
.
.
101AGND+1LSB(0.
004883V)000.
.
.
000to000.
.
.
001AGND(0.
000000V)111.
.
.
111to000.
.
.
000AGND1LSB(0.
004883V)111.
.
.
110to111.
.
.
111FSR/2+3LSBs(9.
985352V)100.
.
.
010to100.
.
.
011FSR/2+2LSBs(9.
990234V)100.
.
.
001to100.
.
.
010FSR/2+1LSB(9.
995117V)100.
.
.
000to100.
.
.
0011FSRisfull-scalerangeandis20VwithREFIN=2.
5V.
21LSB=FSR/4096=4.
883mVwithREFIN=2.
5V.
AD7890-4AnalogInputFigure5showstheanaloginputsectionfortheAD7890-4.
Theanaloginputrangeforeachoftheanaloginputsis0to4.
096Vintoaninputresistanceoftypically15kΩ.
ThisinputisbenignwithnodynamicchargingcurrentswiththeresistorattenuatorstagefollowedbythemultiplexerandincaseswhereMUXOUTisconnectedtoSHAINthisisfollowedbythehighinputimpedancestageofthetrack/holdamplifier.
ThedesignedcodetransitionsoccuronsuccessiveintegerLSBvalues(suchas:1LSB,2LSBs,3LSBsOutputcodingisstraight(natural)binarywith1LSB=FSR/4096=4.
096V/4096=1mV.
Theidealinput/outputtransferfunctionisshowninTable5.
2.
5VREFERENCE6k2k20019.
38kAD7890-4REFOUT/REFINAGNDVINX1EQUIVALENTON-RESISTANCEOFMULTIPLEXERMUXOUTTOADCREFERENCECIRCUITRY01357-005Figure5.
AD7890-4AnalogInputStructureTable5.
IdealInput/OutputCodeTablefortheAD7890-4AnalogInput1DigitalOutputCodeTransition+FSR1LSB2(4.
095V)111.
.
.
110to111.
.
.
111+FSR2LSBs(4.
094V)111.
.
.
101to111.
.
.
110+FSR3LSBs(4.
093V)111.
.
.
100to111.
.
.
101AGND+3LSBs(0.
003V)000.
.
.
010to000.
.
.
011AGND+2LSBs(0.
002V)000.
.
.
001to000.
.
.
010AGND+1LSB(0.
001V)000.
.
.
000to000.
.
.
0011FSRisfull-scalerangeandis4.
096VwithREFIN=2.
5V.
21LSB=FSR/4096=1mVwithREFIN=2.
5V.
AD7890-2AnalogInputTheanaloginputsectionfortheAD7890-2containsnobiasingresistorsandtheselectedanaloginputconnectstothemulti-plexerand,incaseswhereMUXOUTisconnectedtoSHAIN,thisisfollowedbythehighinputimpedancestageofthetrack/holdamplifier.
Theanaloginputrangeis,therefore,0Vto2.
5Vintoahighimpedancestagewithaninputcurrentoflessthan50nA.
ThedesignedcodetransitionsoccuronsuccessiveintegerLSBvalues(suchas:lLSB,2LSBs,3LSBs.
.
.
FS-1LSBs).
Outputcodingisstraight(natural)binarywith1LSB=FSR/4096=2.
5V/4096=0.
61mV.
Theidealinput/outputtransferfunctionisshowninTable6.
Table6.
IdealInput/OutputCodeTablefortheAD7890-2AnalogInput1DigitalOutputCodeTransition+FSR1LSB2(2.
499390V)111.
.
.
110to111.
.
.
111+FSR2LSBs(2.
498779V)111.
.
.
101to111.
.
.
110+FSR3LSBs(2.
498169V)111.
.
.
100to111.
.
.
101AGND+3LSBs(0.
001831V)000.
.
.
010to010.
.
.
011AGND+2LSBs(0.
001221V)000.
.
.
001to001.
.
.
010AGND+1LSB(0.
000610V)000.
.
.
000to000.
.
.
0011FSRisfull-scalerangeandis2.
5VwithREFIN=2.
5V.
21LSB=FSR/4096=0.
61mVwithREFIN=2.
5V.
TRACK/HOLDAMPLIFIERTheSHAINinputontheAD7890connectsdirectlytotheinputstageofthetrack/holdamplifier.
Thisisahighimpedanceinputwithinputleakagecurrentsoflessthan50nA.
ConnectingtheMUXOUTpindirectlytotheSHAINpinconnectsthemultiplexeroutputdirectlytothetrack/holdamplifier.
Theinputvoltagerangeforthisinputis0Vto2.
5V.
IfexternalcircuitryisconnectedbetweenMUXOUTandSHAIN,thentheusermustensurethattheinputvoltagerangetotheSHAINinputis0Vto2.
5Vtoensurethatthefulldynamicrangeoftheconverterisutilized.
Thetrack/holdamplifierontheAD7890allowstheADCtoaccuratelyconvertaninputsinewaveoffull-scaleamplitudeto12-bitaccuracy.
Theinputbandwidthofthetrack/holdisgreaterthantheNyquistrateoftheADCevenwhentheADCisoperatedatitsmaximumthroughputrateof117kHz(forexample,thetrack/holdcanhandleinputfrequenciesinexcessof58kHz).
Thetrack/holdamplifieracquiresaninputsignalto12-bitaccuracyinlessthan2μs.
Theoperationofthetrack/holdisessentiallytransparenttotheuser.
Thetrack/holdamplifiergoesfromitstrackingmodetoitsholdmodeatthestartofconversion.
ThestartofconversionistherisingedgeofCONVST(assumingtheinternalpulsehastimedout)forhardwareconversionstartsandforsoftwareconversionstartsisthepointwheretheinternalpulseistimedout.
Theaperturetimeforthetrack/hold(forexample,thedelaytimebetweentheexternalCONVSTsignalandthetrack/holdactuallygoingintohold)istypically15ns.
Forsoftwareconversionstarts,thetimedependsontheinternalpulsewidths.
Therefore,forsoftwareconversionstarts,thesamplinginstantisnotverywelldefined.
Forsamplingsystemswhichrequirewelldefined,equidistantsampling,itmaynotbepossibletoachieveoptimumperformancefromthepartusingthesoftwareconversionstart.
AttheendofAD7890Rev.
C|Page13of28conversion,thepartreturnstoitstrackingmode.
Theacquisitiontimeofthetrack/holdamplifierbeginsatthispoint.
REFERENCETheAD7890containsasinglereferencepin,labeledREFOUT/REFIN,whicheitherprovidesaccesstothepart'sown2.
5Vreferenceortowhichanexternal2.
5Vreferencecanbeconnectedtoprovidethereferencesourceforthepart.
Thepartisspecifiedwitha2.
5Vreferencevoltage.
ErrorsinthereferencesourceresultsingainerrorsintheAD7890'stransferfunctionandaddstothespecifiedfull-scaleerrorsonthepart.
OntheAD7893-10,italsoresultsinanoffseterrorinjectedintheattenuatorstage.
TheAD7890containsanon-chip2.
5Vreference.
TousethisreferenceasthereferencesourcefortheAD7890,simplyconnecta0.
1μFdiscceramiccapacitorfromtheREFOUT/REFINpintoAGND.
ThevoltagewhichappearsatthispinisinternallybufferedbeforebeingappliedtotheADC.
IfthisreferenceisrequiredforuseexternaltotheAD7890,itshouldbebufferedasthesourceimpedanceofthisoutputis2kΩnominal.
Thetoleranceontheinternalreferenceis±10mVat25°Cwithatypicaltemperaturecoefficientof25ppm/°Candamaximumerrorovertemperatureof±25mV.
IftheapplicationrequiresareferencewithatightertoleranceortheAD7890needstobeusedwithasystemreference,thentheuserhastheoptionofconnectinganexternalreferencetothisREFOUT/REFINpin.
TheexternalreferenceeffectivelyoverdrivestheinternalreferenceandthusprovidesthereferencesourcefortheADC.
Thereferenceinputisbuffered,buthasanominal2kΩresistorconnectedtotheAD7890'sinternalreference.
SuitablereferencesourcesfortheAD7890includetheAD680,AD780,andREF-43precision2.
5Vreferences.
TIMINGANDCONTROLTheAD7890iscapableoftwointerfacemodes,selectedbytheSMODEinput.
Thefirstoftheseisaself-clockingmodewherethepartprovidestheframesync,serialclock,andserialdataattheendofconversion.
Inthismodetheserialclockrateisdeterminedbythemasterclockrateofthepart(attheCLKINinput).
Thesecondmodeisanexternalclockingmodewheretheuserprovidestheframesyncandserialclocksignalstoobtaintheserialdatafromthepart.
Inthissecondmode,theuserhascontroloftheserialclockrateuptoamaximumof10MHz.
ThetwomodesarediscussedintheSerialInterfacesection.
Thepartalsoprovideshardwareandsoftwareconversionstartfeatures.
Theformerprovidesawell-definedsamplinginstantwiththetrack/holdgoingintoholdontherisingedgeoftheCONVSTsignal.
Forthesoftwareconversionstart,awritetotheCONVbittothecontrolregisterinitiatestheconversionsequence.
However,forthesoftwareconversionstartaninternalpulsehastotimeoutbeforetheinputsignalissampled.
Thispulse,plusthedifficultyinmaintainingexactlyequaldelaysbetweeneachsoftwareconversionstartcommand,meansthatthedynamicperformanceoftheAD7890mayhavedifficultymeetingspecificationswhenusedinsoftwareconversionstartmode.
TheAD7890providesseparatechannelselectandconversionstartcontrol.
Thisallowstheusertooptimizethethroughputrateofthesystem.
Oncethetrack/holdhasgoneintoholdmode,theinputchannelcanbeupdatedandtheinputvoltagecansettletothenewvaluewhilethepresentconversionisinprogress.
AssumingtheinternalpulsehastimedoutbeforetheCONVSTpulseisexercised,theconversionconsistsof14.
5masterclockcycles.
Intheself-clockingmode,theconversiontimeisdefinedasthetimefromtherisingedgeofCONVSTtothefallingedgeofRFS(forexample,whenthedevicestartstotransmititsconversionresult).
Thistimeincludesthe14.
5masterclockcyclesplustheupdatingoftheoutputregisteranddelaytimeinoutputtingtheRFSsignal,resultinginatotalconversiontimeof5.
9μsmaximum.
Figure6showstheconversiontimingfortheAD7890whenusedintheself-clocking(master)modewithhardwareCONVST.
ThetimingdiagramassumesthattheinternalpulseisnotactivewhentheCONVSTsignalgoeshigh.
Toensurethis,thechanneladdresstobeconvertedshouldbeselectedbywritingtothecontrolregisterpriortotheCONVSTpulse.
SufficientsetuptimeshouldbeallowedbetweenthecontrolregisterwriteandtheCONVSTtoensurethattheinternalpulsehastimedout.
Thedurationoftheinternalpulse(andhencethedurationofsetuptime)dependsonthevalueofCEXT.
TRACK/HOLDGOESINTOTHEHOLDTHREE-STATENOTES:1.
(I)SIGNIFIESANINPUT.
2.
(O)SIGNIFIESANOUTPUT.
PULL-UPRESISTORONSCLK.
DATAOUT(O)1SCLK(O)RFS(O)CONVST(I)tCONVERT01357-006Figure6.
Self-Clocking(Master)ModeConversionSequenceAD7890Rev.
C|Page14of28Whenusingthedeviceintheexternal-clockingmode,theoutputregistercanbereadatanytimeandthemostup-to-dateconversionresultisobtained.
However,readingdatafromtheoutputregisterorwritingdatatothecontrolregisterduringconversionorduringthe500nspriortothenextCONVSTresultsinreducedperformancefromthepart.
Areadoperationtotheoutputregisterhasthemosteffectonperformancewiththesignal-to-noiseratiolikelytodegrade,especiallywhenhigherserialclockratesareusedwhilethecodeflickerfromthepartalsoincreases(seethePerformancesection).
Figure7showsthetimingandcontrolsequencerequiredtoobtainoptimumperformancefromthepartintheexternalclockingmode.
Inthesequenceshown,conversionisinitiatedontherisingedgeofCONVSTandnewdataisavailableintheoutputregisteroftheAD78905.
9μslater.
Oncethereadoperationhastakenplace,afurther500nsshouldbeallowedbeforethenextrisingedgeofCONVSTtooptimizethesettlingofthetrack/holdbeforethenextconversionisinitiated.
Thediagramshowsthereadoperationandthewriteoperationtakingplaceinparallel.
OnthesixthfallingedgeofSCLKinthewritesequencetheinternalpulseisinitiated.
AssumingMUXOUTisconnectedtoSHAIN,2μsarerequiredbetweenthissixthfallingedgeofSCLKandtherisingedgeofCONVSTtoallowforthefullacquisitiontimeofthetrack/holdamplifier.
Withtheserialclockrateatitsmaximumof10MHz,theachievablethroughputrateforthepartis5.
9μs(conversiontime)plus0.
6μs(sixserialclockpulsesbeforeinternalpulseisinitiated)plus2μs(acquisitiontime).
Thisresultsinaminimumthroughputtimeof8.
5μs(equivalenttoathroughputrateof117kHz).
Ifthepartisoperatedwithaslowerserialclock,itaffectstheachievablethroughputrateforoptimumperformance.
RFSTFS500nsMINCONVSTSCLKNEXTCONVERSIONSTARTCOMMANDCONVERSIONISINITIATEDANDTRACK/HOLDGOESINTOHOLDCONVERSIONENDS5.
9sLATERSERIALREADANDWRITEOPERATIONSREADANDWRITEOPERATIONSSHOULDEND500nsPRIORTONEXTRISINGEDGEOFCONVSTtCONVERT01357-007Figure7.
ExternalClocking(Slave)ModeTimingSequenceforOptimumPerformanceAD7890Rev.
C|Page15of28Intheself-clockingmode,theAD7890indicateswhenconversioniscompletebybringingtheRFSlinelowandinitiatingaserialdatatransfer.
Intheexternalclockingmode,thereisnoindicationofwhenconversioniscomplete.
Inmanyapplications,thisisnotaproblemasthedatacanbereadfromthepartduringconversionorafterconversion.
However,applicationsthatseektoachieveoptimumperformancefromtheAD7890hastoensurethatthedatareaddoesnotoccurduringconversionorduring500nspriortotherisingedgeofCONVST.
Thiscanbeachievedineitheroftwoways.
Thefirstistoensureinsoftwarethatthereadoperationisnotinitiateduntil5.
9μsaftertherisingedgeofCONVST.
ThisisonlypossibleifthesoftwareknowswhentheCONVSTcommandisissued.
ThesecondschemewouldbetousetheCONVSTsignalasboththeconversionstartsignalandaninterruptsignal.
ThesimplestwaytodothisistogenerateasquarewavesignalforCONVSTwithhighandlowtimesof5.
9μs(seeFigure8).
ConversionisinitiatedontherisingedgeofCONVST.
ThefallingedgeofCONVSToccurs5.
9μslaterandcanbeusedaseitheranactiveloworfallingedge-triggeredinterruptsignaltotelltheprocessortoreadthedatafromtheAD7890.
Providedthereadoperationiscompleted500nsbeforetherisingedgeofCONVST,theAD7890operatestospecification.
Thisschemelimitsthethroughputrateto11.
8μsminimum.
However,dependingupontheresponsetimeofthemicroprocessortotheinterruptsignalandthetimetakenbytheprocessortoreadthedata,thismaybethefastestwhichthesystemcouldhaveoperated.
Inanycase,theCONVSTsignaldoesnothavetohavea50:50dutycycle.
Thiscanbetailoredtooptimizethethroughputrateofthepartforagivensystem.
Alternatively,theCONVSTsignalcanbeusedasanormalnarrowpulsewidth.
TherisingedgeofCONVSTcanbeusedasanactivehighorrisingedge-triggeredinterrupt.
Asoftwaredelayof5.
9μscanthenbeimplementedbeforedataisreadfromthepart.
NEXTCONVSTRISINGEDGECONVERSIONISINITIATEDANDTRACK/HOLDGOESINTOHOLDCONVERSIONENDS5.
9sLATERMICROPROCESSORINTSERVICEORPOLLINGROUTINESERIALREADANDWRITEOPERATIONSREADANDWRITEOPERATIONSSHOULDEND500nsPRIORTONEXTRISINGEDGEOFCONVSTtCONVERT500nsMINRFSTFSCONVSTSCLK01357-008Figure8.
CONVSTUsedasStatusSignalinExternalClockingModeAD7890Rev.
C|Page16of28CEXTFUNCTIONINGTheCEXTinputontheAD7890providesameansofdetermininghowlongafteranewchanneladdressiswrittentothepartthataconversioncantakeplace.
Thereasonbehindthisistwo-fold.
First,whentheinputchanneltotheAD7890ischanged,theinputvoltageonthisnewchannelislikelytobeverydifferentfromthepreviouschannelvoltage.
Therefore,thepart'strack/holdhastoacquirethenewvoltagebeforeanaccurateconversioncantakeplace.
Aninternalpulsedelaysanyconversionstartcommand(aswellasthesignaltosendthetrack/holdintohold)untilafterthispulsehastimedout.
ThesecondreasonistoallowtheusertoconnectexternalantialiasingorsignalconditioningcircuitrybetweentheMUXOUTpinandtheSHAINpin.
Thisexternalcircuitryintroducesextrasettlingtimeintothesystem.
TheCEXTpinprovidesameansfortheusertoextendtheinternalpulsetotakethisextrasettlingtimeintoaccount.
EffectivelyvaryingthevalueofthecapacitorontheCEXTpinvariesthedurationoftheinternalpulse.
Figure9showstherelationshipbetweenthevalueoftheCEXTcapacitorandtheinternaldelay.
645648403224168002505007501000125015001750200001357-009INTERNALPULSEWIDTH(s)CEXTCAPACITANCE(pF)TA=+85°CTA=–40°CTA=+25°CFigure9.
InternalPulseWidthvs.
CEXTThedurationoftheinternalpulsecanbeseenontheCEXTpin.
TheCEXTpingoesfromalowtoahighwhenaserialwritetothepartisinitiated(onthefallingedgeofTFS).
ItstartstodischargeonthesixthfallingedgeofSCLKintheserialwriteoperation.
OncetheCEXTpinhasdischargedtocrossingitsnominaltriggerpointof2.
5V,theinternalpulseistimedout.
Theinternalpulseisinitiatedeachtimeawriteoperationtothecontrolregistertakesplace.
Asaresult,thepulseisinitiatedandtheconversionprocessdelayedforallsoftwareconversionstartcommands.
Forhardwareconversionstart,itispossibletoseparatetheconversionstartcommandfromtheinternalpulse.
Ifthemultiplexeroutput(MUXOUT)isconnecteddirectlytothetrack/holdinput(SHAIN),thennoexternalsettlinghastobetakenintoaccountbytheinternalpulsewidth.
Inapplicationswherethemultiplexerisswitchedandconversionisnotinitiateduntilmorethan2μsafterthechannelischanged(asispossiblewithahardwareconversionstart),theuserdoesnothavetoworryaboutconnectinganycapacitancetotheCEXTpin.
The2μsequatestothetrack/holdacquisitiontimeoftheAD7890.
Inapplicationswherethemultiplexerisswitchedandconversionisinitiatedatthesametime(suchaswithasoftwareconversionstart),a120pFcapacitorshouldbeconnectedtoCEXTtoallowfortheacquisitiontimeofthetrack/holdbeforeconversionisinitiated.
IfexternalcircuitryisconnectedbetweentheMUXOUTpinandSHAINpin,thentheextrasettlingtimeintroducedbythiscircuitrymustbetakenintoaccount.
Inthecasewherethemultiplexerchangecommandandtheconversionstartcommandareseparated,theyneedtobeseparatedbygreaterthantheacquisitiontimeoftheAD7890plusthesettlingtimeoftheexternalcircuitryiftheuserdoesnothavetoworryabouttheCEXTcapacitance.
Inapplicationswherethemultiplexerisswitchedandconversionisinitiatedatthesametime(suchaswithasoftwareconversionstart),thecapacitoronCEXTneedstoallowfortheacquisitiontimeofthetrack/holdandthesettlingtimeoftheexternalcircuitrybeforeconversionisinitiated.
AD7890Rev.
C|Page17of28SERIALINTERFACETheAD7890'sserialcommunicationsportprovidesaflexiblearrangementtoalloweasyinterfacingtoindustry-standardmicroprocessors,microcontrollers,anddigitalsignalprocessors.
AserialreadtotheAD7890accessesdatafromtheoutputregisterviatheDATAOUTline.
AserialwritetotheAD7890writesdatatothecontrolregisterviatheDATAINline.
Twodifferentmodesofoperationareavailable,optimizedfordifferenttypesofinterfacewheretheAD7890canacteitherasmasterinthesystem(itprovidestheserialclockanddataframingsignal)oractsasslave(anexternalserialclockandframingsignalcanbeprovidedtotheAD7890).
Theformerisself-clockingmodewhilethelatterisexternalclockingmode.
SELF-CLOCKINGMODETheAD7890isconfiguredforitsself-clockingmodebytyingtheSMODEpinofthedevicetoalogiclow.
Inthismode,theAD7890providestheserialclocksignalandtheserialdataframingsignalusedforthetransferofdatafromtheAD7890.
Thisself-clockingmodecanbeusedwithprocessorsthatallowanexternaldevicetoclocktheirserialport,includingmostdigitalsignalprocessors.
ReadOperationFigure10showsatimingdiagramforreadingfromtheAD7890intheself-clockingmode.
Attheendofconversion,RFSgoeslowandtheserialclock(SCLK)andserialdata(DATAOUT)outputsbecomeactive.
Sixteenbitsofdataaretransmittedwithoneleadingzero,followedbythethreeaddressbitsofthecontrolregister,followedbythe12-bitconversionresultstartingwiththeMSB.
SerialdataisclockedoutofthedeviceontherisingedgeofSCLKandisvalidonthefallingedgeofSCLK.
TheRFSoutputremainslowforthedurationofthe16clockcycles.
Onthe16thrisingedgeofSCLK,theRFSoutputisdrivenhighandDATAOUTisdisabled.
RFS(O)SCLK(O)DATAOUT(O)THREE-STATEt2t1t3t4t5t7t6THREE-STATELEADINGZERODB0DB10DB11A2A1A0NOTES:1.
(I)SIGNIFIESANINPUT.
2.
(O)SIGNIFIESANOUTPUT.
PULL-UPRESISTORONSCLK.
01357-010Figure10.
Self-Clocking(Master)ModeOutputRegisterReadTFS(I)SCLK(O)DATAIN(I)NOTES:1.
(I)SIGNIFIESANINPUT.
2.
(O)SIGNIFIESANOUTPUT.
PULL-UPRESISTORONSCLK.
t8t9t10t11t3t4t12A2A1A0CONVSTBYDON'TCAREDON'TCAREDON'TCARE01357-011Figure11.
Self-Clocking(Master)ModeControlRegisterWriteAD7890Rev.
C|Page18of28WriteOperationFigure11showsawriteoperationtothecontrolregisteroftheAD7890.
TheTFSinputistakenlowtoindicatetothepartthataserialwriteisabouttooccur.
TFSgoinglowinitiatestheSCLKoutputandthisisusedtoclockdataoutoftheprocessorsserialportandintothecontrolregisteroftheAD7890.
TheAD7890controlregisterrequiresonlyfivebitsofdata.
Theseareloadedonthefirstfiveclockcyclesoftheserialclockwithdataonallsubsequentclockcyclesbeingignored.
However,thepartrequiressixserialclockcyclestoloaddatatothecontrolregister.
SerialdatatobewrittentotheAD7890mustbevalidonthefallingedgeofSCLK.
EXTERNALCLOCKINGMODETheAD7890isconfiguredforitsexternalclockingmodebytyingtheSMODEpinofthedevicetoalogichigh.
Inthismode,SCLKandRFSoftheAD7890areconfiguredasinputs.
Thisexternal-clockingmodeisdesignedfordirectinterfacetosystems,whichprovideaserialclockoutputwhichissynchronizedtotheserialdataoutputincludingmicrocontrollerssuchasthe80C51,87C51,68HC11,and68HC05,andmostdigitalsignalprocessors.
ReadOperationFigure12showsthetimingdiagramforreadingfromtheAD7890intheexternalclockingmode.
RFSgoeslowtoaccessdatafromtheAD7890.
Theserialclockinputdoesnothavetobecontinuous.
Theserialdatacanbeaccessedinanumberofbytes.
However,RFSmustremainlowforthedurationofthedatatransferoperation.
Onceagain,16thbitsofdataaretransmittedwithoneleadingzero,followedbythethreeaddressbitsinthecontrolregister,followedbythe12-bitconversionresultstartingwiththeMSB.
IfRFSgoeslowduringthehightimeofSCLK,theleadingzeroisclockedoutfromthefallingedgeofRFS(asperFigure12).
IfRFSgoeslowduringthelowtimeofSCLK,theleadingzeroisclockedoutonthenextrisingedgeofSCLK.
Thisensuresthat,regardlessofwhetherRFSgoeslowduringahightimeorlowtimeofSCLK,theleadingzeroisvalidonthefirstfallingedgeofSCLKafterRFSgoeslow,providedt14andt17areadheredto.
SerialdataisclockedoutofthedeviceontherisingedgeofSCLKandisvalidonthefallingedgeofSCLK.
Attheendofthereadoperation,theDATAOUTlineisthree-statedbyarisingedgeoneithertheSCLKorRFSinputs,whicheveroccursfirst.
Ifaserialreadfromtheoutputregisterisinprogresswhenconversioniscomplete,theupdatingoftheoutputregisterisdeferreduntiltheserialdatareadiscompleteandRFSreturnshigh.
WriteOperationFigure13showsawriteoperationtothecontrolregisteroftheAD7890.
Aswithself-clockingmode,theTFSinputgoeslowtoindicatetothepartthataserialwriteisabouttooccur.
Asbefore,theAD7890controlregisterrequiresonlyfivebitsofdata.
Theseareloadedonthefirstfiveclockcyclesoftheserialclock;dataonallsubsequentclockcyclesareignored.
However,thepartrequiressixserialclockstoloaddatatothecontrolregister.
SerialdatatobewrittentotheAD7890mustbevalidonthefallingedgeofSCLK.
RFS(I)SCLK(I)DATAOUT(O)NOTES:1.
(I)SIGNIFIESANINPUT.
2.
(O)SIGNIFIESANOUTPUT.
THREE-STATELEADINGZERODB10DB0DB11A2A1A0t14t13t15t16t17t19t19At1801357-012Figure12.
ExternalClocking(Slave)ModeOutputRegisterReadTFS(I)SCLK(I)DATAIN(I)NOTES:1.
(I)SIGNIFIESANINPUT.
2.
(O)SIGNIFIESANOUTPUT.
PULL-UPRESISTORONSCLK.
A2A1A0CONVSTBYDON'TCAREDON'TCAREDON'TCAREt20t22t21t2301357-013Figure13.
ExternalClocking(Slave)ModeControlRegisterWriteAD7890Rev.
C|Page19of28SIMPLIFYINGTHEINTERFACETominimizethenumberofinterconnectlinestotheAD7890,theusercanconnecttheRFSandTFSlinesoftheAD7890togetherandreadandwritefromthepartsimultaneously.
Inthiscase,newcontrolregisterdatashouldbeprovidedontheDATAINlineselectingtheinputchannelandpossiblyprovidingaconversionstartcommandwhilethepartprovidestheresultfromtheconversionjustcompletedontheDATAOUTline.
Intheself-clockingmode,thismeansthatthepartprovidesallthesignalsfortheserialinterface.
ItdoesrequirethatthemicroprocessorhasthedatatobewrittentothecontrolregisteravailableinitsoutputregisterwhenthepartbringstheTFSlinelow.
Intheexternalclockingmode,itmeansthattheuseronlyhastosupplyasingleframesynchronizationsignaltocontrolboththereadandwriteoperations.
Caremustbetakenwiththisschemethatthereadoperationiscompletedbeforethenextconversionstarts,iftheuserwantstoobtainoptimumperformancefromthepart.
Inthecaseofthesoftwareconversionstart,theconversioncommandiswrittentothecontrolregisteronthesixthserialclockedge.
However,thereadoperationcontinuesforanother10serialclockcycles.
Toavoidreadingduringthesamplinginstantorduringconversion,theusershouldensurethattheinternalpulsewidthissufficientlylong(bychoosingCEXT)sothatthereadoperationiscompletedbeforethenextconversionsequencebegins.
Failuretodothisresultsinsignificantlydegradedperformancefromthepart,bothintermsofsignal-to-noiseratioanddcparameters.
Inthecaseofahardwareconversionstart,theusershouldensurethatthedelaybetweenthesixthfallingedgeoftheserialclockinthewriteoperationandthenextrisingedgeofCONVSTisgreaterthantheinternalpulsewidth.
AD7890Rev.
C|Page20of28MICROPROCESSOR/MICROCONTROLLERINTERFACETheAD7890'sflexibleserialinterfaceallowsforeasyconnectiontotheserialportsofDSPprocessorsandmicrocontrollers.
Figure14throughFigure17showtheAD7890interfacedtoanumberofdifferentmicrocontrollersandDSPprocessors.
Insomeoftheinterfacesshown,theAD7890isconfiguredasthemasterinthesystem,providingtheserialclockandframesyncforthereadoperationwhileinothersitactsasaslavewiththesesignalsprovidedbythemicroprocessor.
AD7890TO8051INTERFACEFigure14showsaninterfacebetweentheAD7890andthe8xC51microcontroller.
TheAD7890isconfiguredforitsexternalclockingmodewhilethe8xC51isconfiguredforitsMode0serialinterfacemode.
ThediagramshowninFigure14makesnoprovisionsformonitoringwhenconversioniscompleteontheAD7890(assuminghardwareconversionstartisused).
TomonitortheconversiontimeontheAD7890,ascheme,suchastheschemeoutlinedwithCONVSTintheSimplifyingtheInterfacesection,canbeused.
Thiscanbeimplementedintwoways.
OneistoconnecttheCONVSTlinetoanotherparallelportbit,whichisconfiguredasaninput.
Thisportbitcanthenbepolledtodeterminewhenconversioniscomplete.
AnalternativeistouseaninterruptdrivensystemwheretheCONVSTlineisconnectedtotheINT1inputofthe8xC51.
Sincethe8xC51containsonlyoneserialdataline,theDATAOUTandDATAINlinesoftheAD7890mustbeconnectedtogether.
Thismeansthatthe8xC51cannotcommunicatewiththeoutputregisterandcontrolregisteroftheAD7890atthesametime.
The8xC51outputstheLSBfirstinawriteoperationsocareshouldbetakeninarrangingthedata,whichistobetransmittedtotheAD7890.
Similarly,theAD7890outputstheMSBfirstduringareadoperationwhilethe8xC51expectstheLSBfirst.
Therefore,thedatathatistobereadintotheserialportneedstoberearrangedbeforethecorrectdatawordfromtheAD7890isavailableinthemicrocontroller.
Theserialclockratefromthe8xC51islimitedtosignificantlylessthantheallowableinputserialclockfrequencywithwhichtheAD7890canoperate.
Asaresult,thetimetoreaddatafromthepartisactuallylongerthantheconversiontimeofthepart.
ThismeansthattheAD7890cannotrunatitsmaximumthroughputratewhenusedwiththe8xC51.
VDDSMODERFSTFSDATAOUTDATAINSCLKP1.
0P1.
1P3.
0P3.
1AD78908xC5101357-014Figure14.
AD7890to8xC51InterfaceAD7890TO68HC11INTERFACEAninterfacecircuitbetweentheAD7890andthe68HC11microcontrollerisshowninFigure15.
Fortheinterfaceshown,theAD7890isconfiguredforitsexternalclockingmodewhilethe68HC11'sSPIportisusedandthe68HC11isconfiguredinitssingle-chipmode.
The68HC11isconfiguredinthemastermodewithitsCPOLbitsettoaLogic0anditsCPHAbitsettoaLogic1.
Aswiththepreviousinterface,therearenoprovisionsformonitoringwhenconversioniscompleteontheAD7890.
TomonitortheconversiontimeontheAD7890,ascheme,suchastheschemeoutlinedwithCONVSTintheSimplifyingtheInterfacesection,canbeused.
Thiscanbeimplementedintwoways.
OneistoconnecttheCONVSTlinetoanotherparallelportbit,whichisconfiguredasaninput.
Thisportbitcanthenbepolledtodeterminewhenconversioniscomplete.
AnalternativeistouseaninterruptdrivensysteminwhichcasetheCONVSTlineshouldbeconnectedtotheIRQinputofthe68HC11.
DVDDDVDDSMODERFSTFSDATAOUTDATAINSCLKSSPC0PC1SCKMISOMOSI68HC11AD789001357-015Figure15.
AD7890to68HC11InterfaceAD7890Rev.
C|Page21of28Theserialclockratefromthe68HC11islimitedtosignificantlylessthantheallowableinputserialclockfrequencywithwhichtheAD7890canoperate.
Asaresult,thetimetoreaddatafromthepartisactuallylongerthantheconversiontimeofthepart.
ThismeansthattheAD7890cannotrunatitsmaximumthroughputratewhenusedwiththe68HC11.
AD7890TOADSP-2101INTERFACEAninterfacecircuitbetweentheAD7890andtheADSP-2101DSPprocessorisshowninFigure16.
TheAD7890isconfiguredforitsexternalclockingmodewiththeADSP-2101providingtheserialclockandframesynchronizationsignals.
TheRFS1andTFS1inputsandoutputsareconfiguredforactivelowoperation.
DVDDSMODERFSTFSDATAOUTDATAINSCLKRFS1TFS1SCLK1DR1DT1AD7890ADSP-210101357-016Figure16.
AD7890toADSP-2101InterfaceIntheschemeshown,themaximumserialclockfrequencytheADSP-2101canprovideis6.
25MHz.
ThisallowstheAD7890tobeoperatedatasamplerateof111kHz.
IfitisdesirabletooperatetheAD7890atitsmaximumthroughputrateof117kHz,anexternalserialclockof10MHzcanbeprovidedtodrivetheserialclockinputofboththeAD7890andtheADSP-2101.
TomonitortheconversiontimeontheAD7890,ascheme,suchastheschemeoutlinedwithCONVSTintheSimplifyingtheInterfacesection,canbeused.
ThiscanbeimplementedbyconnectingtheCONVSTlinedirectlytotheIRQ2inputoftheADSP-2101.
Analternativetothis,wheretheuserdoesnothavetoworryaboutmonitoringtheconversionstatus,istooperatetheAD7890initsself-clockingmode.
Inthisscheme,theactualinterfaceconnectionswouldremainthesameasinFigure16,butnowtheAD7890providestheserialclockandreceiveframesynchronizationsignals.
UsingtheAD7890initsself-clockingmodelimitsthethroughputrateofthesystemastheserialclockrateislimitedto2.
5MHz.
AD7890TODSP56000INTERFACEFigure17showsaninterfacecircuitbetweentheAD7890andtheDSP56000DSPprocessor.
TheAD7890isconfiguredforitsexternalclockingmode.
TheDSP56000isconfiguredfornormalmode,synchronousoperationwithcontinuousclock.
Itisalsosetupfora16-bitwordwithSCKandSC2asoutputs.
TheFSLbitoftheDSP56000shouldbesetto0.
TheRFSandTFSinputsoftheAD7890areconnectedtogethersodataistransmittedtoandfromtheAD7890atthesametime.
WiththeDSP56000insynchronousmode,itprovidesacommonframesynchronizationpulseforreadandwriteoperationsonitsSC2output.
ThisisinvertedbeforebeingappliedtotheRFSandTFSinputsoftheAD7890.
TomonitortheconversiontimeontheAD7890,ascheme,suchastheschemeoutlinedwithCONVSTintheSimplifyingtheInterfacesection,canbeused.
ThiscanbeimplementedbyconnectingtheCONVSTlinedirectlytotheIRQAinputoftheDSP56000.
DVDDSMODERFSTFSDATAOUTDATAINSCLKSC2SCKSRDSTDAD7890DSP5600001357-017Figure17.
AD7890toDSP56000InterfaceAD7890TOTMS320C25/30INTERFACEFigure18showsaninterfacecircuitbetweentheAD7890andtheTMS320C25/30DSPprocessor.
TheAD7890isconfiguredforitsself-clockingmodewhereitprovidestheserialclockandframesynchronizationsignals.
However,theTMS320C25/30requiresacontinuousserialclock.
Intheschemeoutlinedhere,theAD7890'smasterclocksignal,CLKIN,isusedtoprovidetheserialclockfortheprocessor.
TheAD7890outputSCLK,towhichtheserialdataisreferenced,isadelayedversionoftheCLKINsignal.
ThetypicaldelaybetweentheCLKINandSCLKis20nsandisnomorethan50nsoversuppliesandtemperature.
Therefore,thereisstillsufficientsetuptimeforDATAOUTtobeclockedintotheDSPontheedgesoftheCLKINsignal.
WhenwritingdatatotheAD7890,theprocessor'sdataholdtimeissufficientlylongtocaterforthedelaybetweenthetwoclocks.
TheAD7890'sRFSsignalconnectstoboththeFSXandFSRinputsoftheprocessor.
TheprocessorcangenerateitsownFSXsignal,soifrequired,theinterfacecanbemodifiedsothattheRFSandTFSsignalsareseparatedandtheprocessorgeneratestheFSXsignalwhichisconnectedtotheTFSinputoftheAD7890.
AD7890Rev.
C|Page22of28Intheschemeoutlinedhere,theuserdoesnothavetoworryaboutmonitoringtheendofconversion.
Onceconversioniscomplete,theAD7890takescareoftransmittingbackitsconversionresulttotheprocessor.
Oncethe16bitsofdatahavebeenreceivedbytheprocessorintoitsserialshiftregister,itgeneratesaninternalinterrupt.
SincetheRFSpinandtheTFSpinareconnectedtogether,dataistransmittedtothecontrolregisteroftheAD7890whenevertheAD7890transmitsitsconversionresult.
TheuserjusthastoensurethatthewordtobewrittentotheAD7890controlregisterissetuppriortotheendofconversion.
Aspartoftheinterruptroutine,whichrecognizesthatdatahasbeenreadin,theprocessorcansetupthedataitisgoingtowritetothecontrolregisternexttimearound.
AD7890SMODERFSTFSDATAOUTDATAINSCLKTMS320C25/C30FSRFSXCLKXCLKRDRDXCLKINCLKINPUT01357-018Figure18.
AD7890toTMS320C25/30InterfaceANTIALIASINGFILTERTheAD7890providesseparateaccesstothemultiplexerandADCviatheMUXOUTpinandtheSHAINpin.
OneofthereasonsforthisistoallowtheusertoimplementanantialiasingfilterbetweenthemultiplexerandtheADC.
Insertingtheantialiasingfilteratthispointhastheadvantagethatoneantialiasingfiltercansufficeforalleightchannelsratherthanaseparateantialiasingfilterforeachchanneliftheyweretobeplacedpriortothemultiplexer.
TheantialiasingfilterinsertedbetweentheMUXOUTpinandtheSHAINpinisgenerallyalow-passfiltertoremovehighfrequencysignalswhichcouldpossiblybealiasedbackin-bandduringthesamplingprocess.
Itisrecommendedthatthisfilterisanactivefilter,ideallywiththeMUXOUTpinoftheAD7890drivingahighimpedancestageandtheSHAINpinofthepartbeingdrivenfromalowimpedancestage.
Thisremovesanyeffectsfromthevariationofthepart'smultiplexeron-resistancewithinputsignalvoltage,andremovesanyeffectsofahighsourceimpedanceatthesamplinginputofthetrack/hold.
Withanexternalantialiasingfilterinplace,theadditionalsettlingtimeassociatedwiththefiltershouldbeaccountedforbyusingalargercapacitanceonCEXT.
AD7890Rev.
C|Page23of28PERFORMANCELINEARITYThelinearityoftheAD7890isprimarilydeterminedbytheon-chip12-bitD/Aconverter.
ThisisasegmentedDACthatislasertrimmedfor12-bitintegrallinearityanddifferentiallinearity.
Typicalrelativenumbersforthepartare±1/4LSBwhilethetypicalDNLerrorsare±1/2LSB.
NOISEInanADC,noiseexhibitsitselfascodeuncertaintyindcapplicationsandasthenoisefloor(inanFFT,forexample)inacapplications.
InasamplingADCliketheAD7890,allinformationabouttheanaloginputappearsinthebasebandfromdcto1/2thesamplingfrequency.
Theinputbandwidthofthetrack/holdexceedstheNyquistbandwidthand,therefore,anantialiasingfiltershouldbeusedtoremoveunwantedsignalsabovefS/2intheinputsignalinapplicationswheresuchsignalsexist.
Figure19showsahistogramplotfor8192conversionsofadcinputusingtheAD7890.
Theanaloginputwassetatthecenterofacodetransition.
ThetimingandcontrolsequenceusedwasasperFigure7wheretheoptimumperformanceoftheADCisachieved.
Thesameperformancecanbeachievedinself-clockingmodewheretheparttransmitsitsdataafterconversioniscomplete.
AlmostallofthecodesappearintheoneoutputbinindicatingverygoodnoiseperformancefromtheADC.
ThermsnoiseperformancefortheAD7890-2fortheplotinFigure19was81μV.
Sincetheanaloginputrange,andhenceLSBsize,ontheAD7893-4is1.
638timeswhatitisfortheAD7893-2,thesameoutputcodedistributionresultsinanoutputrmsnoiseof143μVfortheAD7893-4.
FortheAD7890-10,withanLSBsizeeighttimesthatoftheAD7890-2,thecodedistributionrepresentsanoutputrmsnoiseof648μV.
9000800070006000500040003000200010000SAMPLINGFREQUENCY=102.
4kHzTA=25°C(X–4)(X–3)(X–2)(X–1)X(X+1)(X+2)(X+3)(X+4)OCCURRENCESOFCODECODE01357-019Figure19.
Histogramof8192ConversionsofaDCInputIntheexternalclockingmode,itispossibletowritedatatothecontrolregisterorreaddatafromtheoutputregisterwhileaconversionisinprogress.
ThesamedataispresentedinFigure20asinFigure19,exceptthatinFigure20,theoutputdatareadforthedeviceoccursduringconversion.
Theseresultsareachievedwithaserialclockrateof2.
5MHz.
Ifahigherserialclockrateisused,thecodetransitionnoisedegradesfromthatshownintheplotinFigure20.
Thishastheeffectofinjectingnoiseontothediewhilebitdecisionsarebeingmade,increasingthenoisegeneratedbytheAD7890.
Thehistogramplotfor8192conversionsofthesamedcinputnowshowsalargerspreadofcodeswiththermsnoisefortheAD7890-2increasingto170μV.
Thiseffectvariesdependingonwheretheserialclockedgesappearwithrespecttothebittrialsoftheconversionprocess.
Itispossibletoachievethesamelevelofperformancewhenreadingduringconversionaswhenreadingafterconversion,dependingontherelationshipoftheserialclockedgestothebittrialpoints(forexample,therelationshipoftheserialclockedgestotheCLKINedges).
ThebitdecisionpointsontheAD7890areonthefallingedgesofthemasterclock(CLKIN)duringtheconversionprocess.
Clockingoutnewdatabitsatthesepoints(forexample,therisingedgeofSCLK)isthemostcriticalfromanoisestandpoint.
ThemostcriticalbitdecisionsaretheMSBs,sotoachievethelevelofperformanceoutlinedinFigure20,readingwithin1μsaftertherisingedgeofCONVSTshouldbeavoided.
800070006000500040003000200010000(X–4)(X–3)(X–2)(X–1)X(X+1)(X+2)(X+3)(X+4)OCCURRENCESOFCODECODESAMPLINGFREQUENCY=102.
4kHzTA=25°C01357-020Figure20.
Histogramof8192ConversionswithReadDuringConversionWritingdatatothecontrolregisteralsohastheeffectofintroducingdigitalactivityontothepartwhileconversionisinprogress.
However,sincetherearenooutputdriversactiveduringawriteoperation,theamountofcurrentflowingonthedieislessthanforareadoperation.
Therefore,theamountofnoiseinjectedintothedieislessthanforareadoperation.
Figure21showstheeffectofawriteoperationduringconversion.
Thehistogramplotfor8192conversionsofthesamedcinputnowshowsalargerspreadofcodesthanforidealconditionsbutsmallerthanforareadoperation.
TheresultingrmsnoisefortheAD7890-2is110μV.
Inthiscase,theserialclockfrequencyis10MHz.
AD7890Rev.
C|Page24of28800070006000500040003000200010000(X–4)(X–3)(X–2)(X–1)X(X+1)(X+2)(X+3)(X+4)OCCURRENCESOFCODECODESAMPLINGFREQUENCY=102.
4kHzTA=25°C01357-021Figure21.
Histogramof8192ConversionswithWriteDuringConversionDYNAMICPERFORMANCETheAD7890containsanon-chiptrack/hold,allowingtheparttosampleinputsignalsupto50kHzonanyofitsinputchannels.
ManyAD7890applicationssimplyrequireittosequencethroughlowfrequencyinputsignalsacrossitseightchannels.
Theremaybesomeapplications,however,forwhichthedynamicperformanceoftheconverteroutto40kHzinputfrequencyisofinterest.
Forthesewiderbandsamplingapplications,itisrecommendedthatthehardwareconversionstartmethodisused.
TheseapplicationsrequireinformationontheADC'seffectonthespectralcontentoftheinputsignal.
Signalto(noise+distortion),totalharmonicdistortion,peakharmonicorspuriousandintermodulationdistortionareallspecified.
Figure22showsatypicalFFTplotofa10kHz,0Vto2.
5VinputafterbeingdigitizedbytheAD7890-2operatingata102.
4kHzsamplingrate.
Thesignalto(noise+distortion)is71.
5dBandthetotalharmonicdistortionis85dB.
Notethatreadingdatafromthepartduringconversionat10MHzserialclockdoeshaveasignificantimpactondynamicperformance.
Forsamplingapplications,itisthereforerecommendednottoreaddataduringconversion.
025.
651.
2SIGNALAMPLITUDE(dB)FREQUENCY(kHz)1209060300SAMPLERATE=102.
4kHzINPUTFREQUENCY=10kHzSNR=71.
5dBTA=25°C01357-022Figure22.
AD7890FFTPlotEFFECTIVENUMBEROFBITSTheformulaforsignalto(noise+distortion)ratio(seetheTerminologysection)isrelatedtotheresolutionornumberofbitsintheconverter.
Rewritingtheformulaprovidesameasureofperformanceexpressedineffectivenumberofbits(N):N=(SNR—1.
76)/6.
02whereSNRissignalto(noise+distortion)ratio.
Theeffectivenumberofbitsforadevicecanbecalculatedfromitsmeasuredsignalto(noise+distortion)ratio.
Figure23showsatypicalplotofeffectivenumberofbitsversusfrequencyfortheAD7890-2fromdcto40kHz.
Thesamplingfrequencyis102.
4kHz.
TheplotshowsthattheAD7890convertsaninputsinewaveof40kHztoaneffectivenumbersofbitsof11whichequatestoasignalto(noise+distortion)levelof68dB.
INPUTFREQUENCY(kHz)0EFFECTIVENUMBEROFBITS12.
011.
511.
010.
510.
0402001357-023Figure23.
EffectiveNumberofBitsvs.
FrequencyAD7890Rev.
C|Page25of28OUTLINEDIMENSIONSCONTROLLINGDIMENSIONSAREININCHES;MILLIMETERDIMENSIONS(INPARENTHESES)AREROUNDED-OFFINCHEQUIVALENTSFORREFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.
CORNERLEADSMAYBECONFIGUREDASWHOLEORHALFLEADS.
COMPLIANTTOJEDECSTANDARDSMS-001071006-A0.
022(0.
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100(2.
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250(31.
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38)MIN0.
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015(0.
38)GAUGEPLANE0.
195(4.
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130(3.
30)0.
115(2.
92)Figure24.
24-LeadPlasticDualIn-LinePackage[PDIP]NarrowBody(N-24-1)Dimensionsshownininchesand(millimeters)CONTROLLINGDIMENSIONSAREININCHES;MILLIMETERDIMENSIONS(INPARENTHESES)AREROUNDED-OFFINCHEQUIVALENTSFORREFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.
24112130.
310(7.
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220(5.
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005(0.
13)MIN0.
098(2.
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320(8.
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290(7.
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015(0.
38)0.
008(0.
20)SEATINGPLANE0.
200(5.
08)MAX1.
280(32.
51)MAX0.
150(3.
81)MIN0.
200(5.
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125(3.
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023(0.
58)0.
014(0.
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100(2.
54)BSC0.
070(1.
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030(0.
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060(1.
52)0.
015(0.
38)PIN1Figure25.
24-LeadCeramicDualIn-LinePackage[CERDIP](Q-24)Dimensionsshownininchesand(millimeters)AD7890Rev.
C|Page26of28COMPLIANTTOJEDECSTANDARDSMS-013-ADCONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS(INPARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFORREFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.
15.
60(0.
6142)15.
20(0.
5984)0.
30(0.
0118)0.
10(0.
0039)2.
65(0.
1043)2.
35(0.
0925)10.
65(0.
4193)10.
00(0.
3937)7.
60(0.
2992)7.
40(0.
2913)0.
75(0.
0295)0.
25(0.
0098)45°1.
27(0.
0500)0.
40(0.
0157)COPLANARITY0.
100.
33(0.
0130)0.
20(0.
0079)0.
51(0.
0201)0.
31(0.
0122)SEATINGPLANE8°0°24131211.
27(0.
0500)BSC060706-AFigure26.
24-LeadStandardSmallOutlinePackage[SOIC_W]WideBody(RW-24)Dimensionsshowninmillimetersand(inches)AD7890Rev.
C|Page27of28ORDERINGGUIDEModelTemperatureRangePackageDescriptionLinearityErrorPackageOptionAD7890AN-240°Cto+85°C24-LeadPDIP±1LSBN-24-1AD7890ANZ-2140°Cto+85°C24-LeadPDIP±1LSBN-24-1AD7890BN-240°Cto+85°C24-LeadPDIP±1/2LSBN-24-1AD7890BNZ-2140°Cto+85°C24-LeadPDIP±1/2LSBN-24-1AD7890AR-240°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890AR-2REEL40°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890ARZ-2140°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890ARZ-2REEL140°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890BR-240°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BR-2REEL40°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BRZ-2140°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BRZ-2REEL140°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890SQ-255°Cto+125°C24-LeadCERDIP±1LSBQ-24AD7890AN-440°Cto+85°C24-LeadPDIP±1LSBN-24AD7890ANZ-4140°Cto+85°C24-LeadPDIP±1LSBN-24AD7890BN-440°Cto+85°C24-LeadPDIP±1/2LSBN-24AD7890BNZ-4140°Cto+85°C24-LeadPDIP±1/2LSBN-24AD7890AR-440°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890AR-4REEL40°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890ARZ-4140°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890ARZ-4REEL140°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890BR-440°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BR-4REEL40°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BRZ-4140°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BRZ-4REEL140°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890SQ-455°Cto+125°C24-LeadCERDIP±1LSBQ-24AD7890AN-1040°Cto+85°C24-LeadPDIP±1LSBN-24-1AD7890ANZ-10140°Cto+85°C24-LeadPDIP±1LSBN-24-1AD7890BN-1040°Cto+85°C24-LeadPDIP±1/2LSBN-24-1AD7890BNZ-10140°Cto+85°C24-LeadPDIP±1/2LSBN-24-1AD7890AR-1040°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890AR-10REEL40°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890ARZ-10140°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890ARZ-10REEL140°Cto+85°C24-LeadSOIC_W±1LSBRW-24AD7890BR-1040°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BR-10REEL40°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BRZ-10140°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890BRZ-10REEL140°Cto+85°C24-LeadSOIC_W±1/2LSBRW-24AD7890SQ-1055°Cto+125°C24-LeadCERDIP±1LSBQ-241Z=Pb-freepart.
AD7890Rev.
C|Page28of28NOTES2006AnalogDevices,Inc.
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