90.66z8nrd12

Dual12-/14-/16-Bit,1GSPS,Digital-to-AnalogConvertersAD9776/AD9778/AD9779Rev.
AInformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.
However,noresponsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorotherrightsofthirdpartiesthatmayresultfromitsuse.
Specificationssubjecttochangewithoutnotice.
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Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
OneTechnologyWay,P.
O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:781.
329.
4700www.
analog.
comFax:781.
461.
31132005–2007AnalogDevices,Inc.
Allrightsreserved.
FEATURESLowpower:1.
0W@1GSPS,600mW@500MSPS,fulloperatingconditionsSFDR=78dBctofOUT=100MHzSinglecarrierWCDMAACLR=79dBc@80MHzIFAnalogoutput:adjustable8.
7mAto31.
7mA,RL=25Ωto50ΩNovel2*,4*,and8*interpolator/coarsecomplexmodulatorallowscarrierplacementanywhereinDACbandwidthAuxiliaryDACsallowcontrolofexternalVGAandoffsetcontrolMultiplechipsynchronizationinterfaceHighperformance,lownoisePLLclockmultiplierDigitalinversesincfilter100-lead,exposedpaddleTQFPpackageAPPLICATIONSWirelessinfrastructureWCDMA,CDMA2000,TD-SCDMA,WiMax,GSMDigitalhighorlowIFsynthesisInternaldigitalupconversioncapabilityTransmitdiversityWidebandcommunications:LMDS/MMDS,point-to-pointGENERALDESCRIPTIONTheAD9776/AD9778/AD9779aredual,12-/14-/16-bit,highdynamicrange,digital-to-analogconverters(DACs)thatpro-videasamplerateof1GSPS,permittingmulticarriergenerationuptotheNyquistfrequency.
Theyincludefeaturesoptimizedfordirectconversiontransmitapplications,includingcomplexdigitalmodulation,andgainandoffsetcompensation.
TheDACoutputsareoptimizedtointerfaceseamlesslywithanalogquad-raturemodulatorssuchastheAD8349.
Aserialperipheralinterface(SPI)providesforprogramming/readbackofmanyinternalparameters.
Full-scaleoutputcurrentcanbeprogrammedoverarangeof10mAto30mA.
Thedevicesaremanufacturedonanadvanced0.
18μmCMOSprocessandoperateon1.
8Vand3.
3Vsuppliesforatotalpowerconsumptionof1.
0W.
Theyareenclosedin100-leadTQFPpackages.
PRODUCTHIGHLIGHTS1.
Ultralownoiseandintermodulationdistortion(IMD)enablehighqualitysynthesisofwidebandsignalsfrombasebandtohighintermediatefrequencies.
2.
AproprietaryDACoutputswitchingtechniqueenhancesdynamicperformance.
3.
Thecurrentoutputsareeasilyconfiguredforvarioussingle-endedordifferentialcircuittopologies.
4.
CMOSdatainputinterfacewithadjustablesetupandhold.
5.
Novel2*,4*,and8*interpolator/coarsecomplexmodulatorallowscarrierplacementanywhereinDACbandwidth.
TYPICALSIGNALCHAIN05361-114FPGA/ASIC/DSPDCCOMPLEXIANDQDCLOQUADRATUREMODULATOR/MIXER/AMPLIFIERIDACQDACDIGITALINTERPOLATIONFILTERSAD9779POSTDACANALOGFILTERAFigure1.
AD9776/AD9778/AD9779Rev.
A|Page2of56TABLEOFCONTENTSFeatures1Applications.
1GeneralDescription.
1ProductHighlights1TypicalSignalChain.
1RevisionHistory2FunctionalBlockDiagram3Specifications.
4DCSpecifications4DigitalSpecifications6DigitalInputDataTimingSpecifications7ACSpecifications.
7AbsoluteMaximumRatings.
8ThermalResistance.
8ESDCaution.
8PinConfigurationsandFunctionDescriptions9TypicalPerformanceCharacteristics15Terminology.
24TheoryofOperation25SerialPeripheralInterface.
25MSB/LSBTransfers.
26SPIRegisterMap27InterpolationFilterArchitecture.
31InterpolationFilterMinimumandMaximumBandwidthSpecifications35DrivingtheREFCLKInput.
35InternalPLLClockMultiplier/ClockDistribution.
36Full-ScaleCurrentGeneration38PowerDissipation.
39Power-DownandSleepModes.
41InterleavedDataMode41TimingInformation.
41SynchronizationofInputDatatoDATACLKOutput(Pin37)43SynchronizationofInputDatatotheREFCLKInput(Pin5andPin6)withPLLEnabledorDisabled.
43EvaluationBoardOperation.
46ModifyingtheEvaluationBoardtoUsetheAD8349On-BoardQuadratureModulator.
48EvaluationBoardSchematics49OutlineDimensions.
56OrderingGuide56REVISIONHISTORY3/07—Rev.
0toRev.
AChangestoFeatures.
1ChangestoApplications1ChangestoGeneralProductHighlights.
1AddedFigure1,RenumberedFiguresSequentially.
1ChangestoTable1.
4ChangestoTable2.
5ChangestoTable3.
5ChangestoFigure53andFigure54.
26ChangestoTable12.
29ChangestoPowerDissipationSection39AddedTable19,RenumberedTablesSequentially.
41ChangestoFigure92andFigure93.
42ChangestoFigure94.
42AddedNewFigure95,RenumberedFiguresSequentially.
.
.
.
.
.
.
42ChangestoSynchronizationofInputDatatotheREFCLKInput(Pin5andPin6)withPLLEnabledorDisabledSection.
43AddedNewFigure96,RenumberedFiguresSequentially.
.
.
.
.
.
.
43ChangestoFigure106517/05—Revision0:InitialVersionAD9776/AD9778/AD9779Rev.
A|Page3of56FUNCTIONALBLOCKDIAGRAM10101010CLOCKGENERATION/DISTRIBUTIONDATAASSEMBLERDIGITALCONTROLLER2*2*SYNC1CLOCKMULTIPLIER2*/4*/8*16-BITIDACCLK+CLK–IOUT1_PIOUT1_NAUX1_PAUX1_NAUX2_PAUX2_NIOUT2_PIOUT2_NGAINGAINGAINGAIN16-BITQDAC2*SYNC1ILATCHDELAYLINEQLATCHP2D(15:0)P1D(15:0)SYNC_OSYNC_IDATACLK_OUT2*2*2*n*fDAC/8n=0,1,2.
.
.
7POWER-ONRESETSDOSDIOSCLKCSBSERIALPERIPHERALINTERFACECOMPLEXMODULATORREFERENCEANDBIASVREFI120DELAYLINE05361-001Figure2.
FunctionalBlockDiagramAD9776/AD9778/AD9779Rev.
A|Page4of56SPECIFICATIONSDCSPECIFICATIONSTMINtoTMAX,AVDD33=3.
3V,DVDD33=3.
3V,DVDD18=1.
8V,CVDD18=1.
8V,=20mA,maximumsamplerate,unlessotherwisenoted.
SOUTFITable1.
AD9776,AD9778,andAD9779DCSpecificationsAD9776AD9778AD9779ParameterMinTypMaxMinTypMaxMinTypMaxUnitRESOLUTION121416BitsACCURACYDifferentialNonlinearity(DNL)±0.
1±0.
65±2.
1LSBIntegralNonlinearity(INL)±0.
6±1±3.
7LSBMAINDACOUTPUTSOffsetError0.
0010+0.
0010.
0010+0.
0010.
0010+0.
001%FSRGainError(withInternalReference)±2±2±2%FSRFull-ScaleOutputCurrent18.
6620.
231.
668.
6620.
231.
668.
6620.
231.
66mAOutputComplianceRange1.
0+1.
01.
0+1.
01.
0+1.
0VOutputResistance101010MΩGainDACMonotonicityGuaranteedGuaranteedGuaranteedMAINDACTEMPERATUREDRIFTOffset0.
040.
040.
04ppm/°CGain100100100ppm/°CReferenceVoltage303030ppm/°CAUXDACOUTPUTSResolution101010BitsFull-ScaleOutputCurrent11.
998+1.
9981.
998+1.
9981.
998+1.
998mAOutputComplianceRange(Source)01.
601.
601.
6VOutputComplianceRange(Sink)0.
81.
60.
81.
60.
81.
6VOutputResistance111MΩAuxDACMonotonicityGuaranteedREFERENCEInternalReferenceVoltage1.
21.
21.
2VOutputResistance555kΩANALOGSUPPLYVOLTAGESAVDD333.
133.
33.
473.
133.
33.
473.
133.
33.
47VCVDD181.
701.
81.
901.
701.
81.
901.
701.
81.
90VDIGITALSUPPLYVOLTAGESDVDD333.
133.
33.
473.
133.
33.
473.
133.
33.
47VDVDD181.
701.
81.
901.
701.
81.
901.
701.
81.
90VPOWERCONSUMPTION1*Mode,fDAC=100MSPS,IF=1MHz250300250300250300mW2*Mode,fDAC=320MSPS,IF=16MHz,PLLOff498498498mW2*Mode,fDAC=320MSPS,IF=16MHz,PLLOn588588588mW4*Mode,fDAC/4Modulation,fDAC=500MSPS,IF=137.
5MHz,QDACOff572572572mWAD9776/AD9778/AD9779Rev.
A|Page5of56AD9776AD9778AD9779ParameterMinTypMaxMinTypMaxMinTypMaxUnit8*Mode,fDAC/4Modulation,fDAC=1GSPS,IF=262.
5MHz980980980mWPower-DownMode23.
723.
723.
7mWPowerSupplyRejectionRatio,AVDD330.
3+0.
30.
3+0.
30.
3+0.
3%FSR/VOPERATINGRANGE40+25+8540+25+8540+25+85°C1Basedona10kΩexternalresistor.
AD9776/AD9778/AD9779Rev.
A|Page6of56DIGITALSPECIFICATIONSTMINtoTMAX,AVDD33=3.
3V,DVDD33=3.
3V,DVDD18=1.
8V,CVDD18=1.
8V,=20mA,maximumsamplerate,unlessotherwisenoted.
LVDSdriverandreceiverarecomplianttotheIEEE-1596reducedrangelink,unlessotherwisenoted.
SOUTFITable2.
AD9776,AD9778,andAD9779DigitalSpecificationsParameterConditionsMinTypMaxUnitCMOSINPUTLOGICLEVELInputVINLogicHigh2.
0VInputVINLogicLow0.
8VMaximumInputDataRateatInterpolation1*300MSPS2*250MSPS4*200MSPS8*125MSPSCMOSOUTPUTLOGICLEVEL(DATACLK,PIN37)1OutputVOUTLogicHigh2.
4VOutputVOUTLogicLow0.
4VLVDSRECEIVERINPUTS(SYNC_I+,SYNC_I)SYNC_I+=VIA,SYNC_I=VIBInputVoltageRange,VIAorVIB8251575mVInputDifferentialThreshold,VIDTH100+100mVInputDifferentialHysteresis,VIDTHHVIDTHL20mVReceiverDifferentialInputImpedance,RIN280120ΩLVDSInputRate125MSPSSet-UpTime,SYNC_ItoDACClock0.
2nsHoldTime,SYNC_ItoDACClock1nsLVDSDRIVEROUTPUTS(SYNC_O+,SYNC_O)SYNC_O+=VOA,SYNC_O=VOB,100ΩterminationOutputVoltageHigh,VOAorVOB8251575mVOutputVoltageLow,VOAorVOB1025mVOutputDifferentialVoltage,|VOD|150200250mVOutputOffsetVoltage,VOS11501250mVOutputImpedance,ROSingle-ended80100120ΩMaximumClockRate1GHzDACCLOCKINPUT(CLK+,CLK)DifferentialPeak-to-PeakVoltage(CLK+,CLK)34008002000mVCommon-ModeVoltage300400500mVMaximumClockRate41GSPSSERIALPERIPHERALINTERFACEMaximumClockRate(SCLK)40MHzMinimumPulseWidthHigh12.
5nsMinimumPulseWidthLow12.
5ns1SpecificationisataDATACLKfrequencyof100MHzintoa1kΩload;maximumdrivecapabilityof8mA.
Athigherspeedsorgreaterloads,bestpracticesuggestsusinganexternalbufferforthissignal.
2Guaranteedat25°C.
Candriftabove120Ωattemperaturesabove25°C.
3WhenusingthePLL,adifferentialswingof2Vp-pisrecommended.
4TypicalmaximumclockratewhenDVDD18=CVDD18=1.
9V.
AD9776/AD9778/AD9779Rev.
A|Page7of56DIGITALINPUTDATATIMINGSPECIFICATIONSTable3.
AD9776,AD9778,andAD9779DigitalInputDataTimingSpecificationsParameterMinTypMaxUnitINPUTDATA(ALLMODES,40°Cto+85°C)1Set-UpTime,InputDatatoDATACLK+2.
5nsHoldTime,InputDatatoDATACLK0.
4nsSet-UpTime,InputDatatoREFCLK0.
8nsHoldTime,InputDatatoREFCLK+2.
9ns1Timingvs.
temperatureanddatavalidkeepoutwindowsaredelineatedinTable19.
ACSPECIFICATIONSTMINtoTMAX,AVDD33=3.
3V,DVDD33=3.
3V,DVDD18=1.
8V,CVDD18=1.
8V,=20mA,maximumsamplerate,unlessotherwisenoted.
SOUTFITable4.
AD9776,AD9778,andAD9779ACSpecificationsAD9776AD9778AD9779ParameterMinTypMaxMinTypMaxMinTypMaxUnitSPURIOUSFREEDYNAMICRANGE(SFDR)fDAC=100MSPS,fOUT=20MHz828282dBcfDAC=200MSPS,fOUT=50MHz818182dBcfDAC=400MSPS,fOUT=70MHz808080dBcfDAC=800MSPS,fOUT=70MHz858587dBcTWO-TONEINTERMODULATIONDISTORTION(IMD)fDAC=200MSPS,fOUT=50MHz878791dBcfDAC=400MSPS,fOUT=60MHz808585dBcfDAC=400MSPS,fOUT=80MHz758181dBcfDAC=800MSPS,fOUT=100MHz758081dBcNOISESPECTRALDENSITY(NSD)EIGHT-TONE,500kHzTONESPACINGfDAC=200MSPS,fOUT=80MHz152155158dBm/HzfDAC=400MSPS,fOUT=80MHz155159160dBm/HzfDAC=800MSPS,fOUT=80MHz157.
5160161dBm/HzWCDMAADJACENTCHANNELLEAKAGERATIO(ACLR),SINGLECARRIERfDAC=491.
52MSPS,fOUT=100MHz767879dBcfDAC=491.
52MSPS,fOUT=200MHz697374dBcWCDMASECONDADJACENTCHANNELLEAKAGERATIO(ACLR),SINGLECARRIERfDAC=491.
52MSPS,fOUT=100MHz77.
58081dBcfDAC=491.
52MSPS,fOUT=200MHz767878dBcAD9776/AD9778/AD9779Rev.
A|Page8of56ABSOLUTEMAXIMUMRATINGSTable5.
ParameterWithRespectToRatingAVDD33,DVDD33AGND,DGND,CGND0.
3Vto+3.
6VDVDD18,CVDD18AGND,DGND,CGND0.
3Vto+1.
98VAGNDDGND,CGND0.
3Vto+0.
3VDGNDAGND,CGND0.
3Vto+0.
3VCGNDAGND,DGND0.
3Vto+0.
3VI120,VREF,IPTATAGND0.
3VtoAVDD33+0.
3VIOUT1-P,IOUT1-N,IOUT2-P,IOUT2-N,Aux1-P,Aux1-N,Aux2-P,Aux2-NAGND1.
0VtoAVDD33+0.
3VP1D15toP1D0,P2D15toP2D0DGND0.
3VtoDVDD33+0.
3VDATACLK,TXENABLEDGND0.
3VtoDVDD33+0.
3VCLK+,CLKCGND0.
3VtoCVDD18+0.
3VRESET,IRQ,PLL_LOCK,SYNC_O+,SYNC_O,SYNC_I+,SYNC_I,CSB,SCLK,SDIO,SDODGND0.
3VtoDVDD33+0.
3VJunctionTemperature+125°CStorageTemperatureRange65°Cto+150°CStressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thisisastressratingonly;functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
THERMALRESISTANCE100-lead,thermallyenhancedTQFP_EPpackage,θJA=19.
1°C/WwiththebottomEPADsolderedtothePCB.
WiththebottomEPADnotsolderedtothePCB,θJA=27.
4°C/W.
Thesespecificationsarevalidwithnoairflowmovement.
ESDCAUTIONAD9776/AD9778/AD9779Rev.
A|Page9of56PINCONFIGURATIONSANDFUNCTIONDESCRIPTIONS74VREF73IPTAT72AGND69CSB70RESET71IRQ75I12068SCLK67SDIO66SDO64DGND63SYNC_O+62SYNC_O–61DVDD3360DVDD1859NC58NC57NC56NC55P2D54DGND53DVDD1852P2D51P2D65PLL_LOCKPIN1100AVDD3399AGND98AVDD3397AGND96AVDD3395AGND94AGND93OUT1_P92OUT1_N91AGND90AUX1_P89AUX1_N88AGND87AUX2_N86AUX2_P85AGND84OUT2_N83OUT2_P82AGND81AGND80AVDD3379AGND78AVDD3377AGND76AVDD3326P1D27P1D28P1D29P1D30P1D31NC32DGND33DVDD1834NC35NC36NC37DATACLK38DVDD3339TXENABLE40P2D41P2D42P2D43DVDD1844DGND45P2D46P2D47P2D48P2D49P2D50P2D2CVDD183CGND4CGND7CGND6CLK–5CLK+1CVDD188CGND9CVDD1810CVDD1812AGND13SYNC_I+14SYNC_I–15DGND16DVDD1817P1D18P1D19P1D20P1D21P1D22DGND23DVDD1824P1D25P1D11CGNDAD9776TOPVIEW(NottoScale)ANALOGDOMAINDIGITALDOMAINNC=NOCONNECT05361-002Figure3.
AD9776PinConfigurationTable6.
AD9776PinFunctionDescriptionsPinNo.
MnemonicDescription1CVDD181.
8VClockSupply.
2CVDD181.
8VClockSupply.
3CGNDClockCommon.
4CGNDClockCommon.
5CLK+1DifferentialClockInput.
6CLK1DifferentialClockInput.
7CGNDClockCommon.
8CGNDClockCommon.
9CVDD181.
8VClockSupply.
10CVDD181.
8VClockSupply.
11CGNDClockCommon.
12AGNDAnalogCommon.
13SYNC_I+DifferentialSynchronizationInput.
14SYNC_IDifferentialSynchronizationInput.
15DGNDDigitalCommon.
16DVDD181.
8VDigitalSupply.
17P1DPort1,DataInputD11(MSB).
18P1DPort1,DataInputD10.
19P1DPort1,DataInputD9.
PinNo.
MnemonicDescription20P1DPort1,DataInputD8.
21P1DPort1,DataInputD7.
22DGNDDigitalCommon.
23DVDD181.
8VDigitalSupply.
24P1DPort1,DataInputD6.
25P1DPort1,DataInputD5.
26P1DPort1,DataInputD4.
27P1DPort1,DataInputD3.
28P1DPort1,DataInputD2.
29P1DPort1,DataInputD1.
30P1DPort1,DataInputD0(LSB).
31NCNoConnect.
32DGNDDigitalCommon.
33DVDD181.
8VDigitalSupply.
34NCNoConnect.
35NCNoConnect.
36NCNoConnect.
37DATACLKDataClockOutput.
38DVDD333.
3VDigitalSupply.
AD9776/AD9778/AD9779Rev.
A|Page10of56PinNo.
MnemonicDescription39TXENABLETransmitEnable.
40P2DPort2,DataInputD11(MSB).
41P2DPort2,DataInputD10.
42P2DPort2,DataInputD9.
43DVDD181.
8VDigitalSupply.
44DGNDDigitalCommon.
45P2DPort2,DataInputD8.
46P2DPort2,DataInputD7.
47P2DPort2,DataInputD6.
48P2DPort2,DataInputD5.
49P2DPort2,DataInputD4.
50P2DPort2,DataInputD3.
51P2DPort2,DataInputD2.
52P2DPort2,DataInputD1.
53DVDD181.
8VDigitalSupply.
54DGNDDigitalCommon.
55P2DPort2,DataInputD0(LSB).
56NCNoConnect.
57NCNoConnect.
58NCNoConnect.
59NCNoConnect.
60DVDD181.
8VDigitalSupply.
61DVDD333.
3VDigitalSupply.
62SYNC_ODifferentialSynchronizationOutput.
63SYNC_O+DifferentialSynchronizationOutput64DGNDDigitalCommon65PLL_LOCKPLLLockIndicator66SDOSPIPortDataOutput67SDIOSPIPortDataInput/Output68SCLKSPIPortClock69CSBSPIPortChipSelectBar.
70RESETReset,ActiveHigh.
71IRQInterruptRequest.
72AGNDAnalogCommon.
PinNo.
MnemonicDescription73IPTATFactoryTestPin.
Outputcurrentisproportionaltoabsolutetemperature,approximately10μAat25°Cwithapproximately20nA/°Cslope.
Thispinshouldremainfloating.
74VREFVoltageReferenceOutput.
75I120120μAReferenceCurrent.
76AVDD333.
3VAnalogSupply.
77AGNDAnalogCommon.
78AVDD333.
3VAnalogSupply.
79AGNDAnalogCommon.
80AVDD333.
3VAnalogSupply.
81AGNDAnalogCommon.
82AGNDAnalogCommon.
83OUT2_PDifferentialDACCurrentOutput,Channel2.
84OUT2_NDifferentialDACCurrentOutput,Channel2.
85AGNDAnalogCommon.
86AUX2_PAuxiliaryDACCurrentOutput,Channel2.
87AUX2_NAuxiliaryDACCurrentOutput,Channel2.
88AGNDAnalogCommon.
89AUX1_NAuxiliaryDACCurrentOutput,Channel1.
90AUX1_PAuxiliaryDACCurrentOutput,Channel1.
91AGNDAnalogCommon.
92OUT1_NDifferentialDACCurrentOutput,Channel1.
93OUT1_PDifferentialDACCurrentOutput,Channel1.
94AGNDAnalogCommon.
95AGNDAnalogCommon.
96AVDD333.
3VAnalogSupply.
97AGNDAnalogCommon.
98AVDD333.
3VAnalogSupply.
99AGNDAnalogCommon.
100AVDD333.
3VAnalogSupply.
1ThecombineddifferentialclockinputattheCLK+andCLK–pinsarereferredtoasREFCLK.
AD9776/AD9778/AD9779Rev.
A|Page11of5674VREF73IPTAT72AGND69CSB70RESET71IRQ75I12068SCLK67SDIO66SDO64DGND63SYNC_O+62SYNC_O–61DVDD3360DVDD1859NC58NC57P2D56P2D55P2D54DGND53DVDD1852P2D51P2D65PLL_LOCKPIN1100AVDD3399AGND98AVDD3397AGND96AVDD3395AGND94AGND93OUT1_P92OUT1_N91AGND90AUX1_P89AUX1_N88AGND87AUX2_N86AUX2_P85AGND84OUT2_N83OUT2_P82AGND81AGND80AVDD3379AGND78AVDD3377AGND76AVDD3326P1D27P1D28P1D29P1D30P1D31P1D32DGND33DVDD1834P1D35NC36NC37DATACLK38DVDD3339TXENABLE40P2D41P2D42P2D43DVDD1844DGND45P2D46P2D47P2D48P2D49P2D50P2D2CVDD183CGND4CGND7CGND6CLK–5CLK+1CVDD188CGND9CVDD1810CVDD1812AGND13SYNC_I+14SYNC_I–15DGND16DVDD1817P1D18P1D19P1D20P1D21P1D22DGND23DVDD1824P1D25P1D11CGNDAD9778TOPVIEW(NottoScale)ANALOGDOMAINDIGITALDOMAINNC=NOCONNECT05361-003Figure4.
AD9778PinConfigurationTable7.
AD9778PinFunctionDescriptionPinNo.
MnemonicDescription1CVDD181.
8VClockSupply.
2CVDD181.
8VClockSupply.
3CGNDClockCommon.
4CGNDClockCommon.
5CLK+1DifferentialClockInput.
6CLK1DifferentialClockInput.
7CGNDClockCommon.
8CGNDClockCommon.
9CVDD181.
8VClockSupply.
10CVDD181.
8VClockSupply.
11CGNDClockCommon.
12AGNDAnalogCommon.
13SYNC_I+DifferentialSynchronizationInput.
14SYNC_IDifferentialSynchronizationInput.
15DGNDDigitalCommon.
16DVDD181.
8VDigitalSupply.
17P1DPort1,DataInputD13(MSB).
18P1DPort1,DataInputD12.
19P1DPort1,DataInputD11.
20P1DPort1,DataInputD10.
PinNo.
MnemonicDescription21P1DPort1,DataInputD9.
22DGNDDigitalCommon.
23DVDD181.
8VDigitalSupply.
24P1DPort1,DataInputD8.
25P1DPort1,DataInputD7.
26P1DPort1,DataInputD6.
27P1DPort1,DataInputD5.
28P1DPort1,DataInputD4.
29P1DPort1,DataInputD3.
30P1DPort1,DataInputD2.
31P1DPort1,DataInputD1.
32DGNDDigitalCommon.
33DVDD181.
8VDigitalSupply.
34P1DPort1,DataInputD0(LSB).
35NCNoConnect.
36NCNoConnect.
37DATACLKDataClockOutput.
38DVDD333.
3VDigitalSupply.
39TXENABLETransmitEnable.
40P2DPort2,DataInputD13(MSB).
AD9776/AD9778/AD9779Rev.
A|Page12of56PinNo.
MnemonicDescription41P2DPort2,DataInputD12.
42P2DPort2,DataInputD11.
43DVDD181.
8VDigitalSupply.
44DGNDDigitalCommon.
45P2DPort2,DataInputD10.
46P2DPort2,DataInputD9.
47P2DPort2,DataInputD8.
48P2DPort2,DataInputD7.
49P2DPort2,DataInputD6.
50P2DPort2,DataInputD5.
51P2DPort2,DataInputD4.
52P2DPort2,DataInputD3.
53DVDD181.
8VDigitalSupply.
54DGNDDigitalCommon.
55P2DPort2,DataInputD2.
56P2DPort2,DataInputD1.
57P2DPort2,DataInputD0(LSB).
58NCNoConnect.
59NCNoConnect.
60DVDD181.
8VDigitalSupply.
61DVDD333.
3VDigitalSupply.
62SYNC_ODifferentialSynchronizationOutput.
63SYNC_O+DifferentialSynchronizationOutput.
64DGNDDigitalCommon.
65PLL_LOCKPLLLockIndicator.
66SDOSPIPortDataOutput.
67SDIOSPIPortDataInput/Output.
68SCLKSPIPortClock.
69CSBSPIPortChipSelectBar.
70RESETReset,ActiveHigh.
71IRQInterruptRequest.
72AGNDAnalogCommon.
73IPTATFactoryTestPin.
Outputcurrentisproportionaltoabsolutetemperature,approximately10μAat25°Cwithapproximately20nA/°Cslope.
Thispinshouldremainfloating.
PinNo.
MnemonicDescription74VREFVoltageReferenceOutput.
75I120120μAReferenceCurrent.
76AVDD333.
3VAnalogSupply.
77AGNDAnalogCommon.
78AVDD333.
3VAnalogSupply.
79AGNDAnalogCommon.
80AVDD333.
3VAnalogSupply.
81AGNDAnalogCommon.
82AGNDAnalogCommon.
83OUT2_PDifferentialDACCurrentOutput,Channel2.
84OUT2_NDifferentialDACCurrentOutput,Channel2.
85AGNDAnalogCommon.
86AUX2_PAuxiliaryDACCurrentOutput,Channel2.
87AUX2_NAuxiliaryDACCurrentOutput,Channel2.
88AGNDAnalogCommon.
89AUX1_NAuxiliaryDACCurrentOutput,Channel1.
90AUX1_PAuxiliaryDACCurrentOutput,Channel1.
91AGNDAnalogCommon.
92OUT1_NDifferentialDACCurrentOutput,Channel1.
93OUT1_PDifferentialDACCurrentOutput,Channel1.
94AGNDAnalogCommon.
95AGNDAnalogCommon.
96AVDD333.
3VAnalogSupply.
97AGNDAnalogCommon.
98AVDD333.
3VAnalogSupply.
99AGNDAnalogCommon.
100AVDD333.
3VAnalogSupply.
1ThecombineddifferentialclockinputattheCLK+andCLK–pinsarereferredtoasREFCLK.
AD9776/AD9778/AD9779Rev.
A|Page13of5674VREF73IPTAT72AGND69CSB70RESET71IRQ75I12068SCLK67SDIO66SDO64DGND63SYNC_O+62SYNC_O–61DVDD3360DVDD1859P2D58P2D57P2D56P2D55P2D54DGND53DVDD1852P2D51P2D65PLL_LOCKPIN1100AVDD3399AGND98AVDD3397AGND96AVDD3395AGND94AGND93OUT1_P92OUT1_N91AGND90AUX1_P89AUX1_N88AGND87AUX2_N86AUX2_P85AGND84OUT2_N83OUT2_P82AGND81AGND80AVDD3379AGND78AVDD3377AGND76AVDD3326P1D27P1D28P1D29P1D30P1D31P1D32DGND33DVDD1834P1D35P1D36P1D37DATACLK38DVDD3339TXENABLE40P2D41P2D42P2D43DVDD1844DGND45P2D46P2D47P2D48P2D49P2D50P2D2CVDD183CGND4CGND7CGND6CLK–5CLK+1CVDD188CGND9CVDD1810CVDD1812AGND13SYNC_I+14SYNC_I–15DGND16DVDD1817P1D18P1D19P1D20P1D21P1D22DGND23DVDD1824P1D25P1D11CGNDAD9779TOPVIEW(NottoScale)ANALOGDOMAINDIGITALDOMAIN05361-004Figure5.
AD9779PinConfigurationTable8.
AD9779PinFunctionDescriptionsPinNo.
MnemonicDescription1CVDD181.
8VClockSupply.
2CVDD181.
8VClockSupply.
3CGNDClockCommon.
4CGNDClockCommon.
5CLK+1DifferentialClockInput.
6CLK1DifferentialClockInput.
7CGNDClockCommon.
8CGNDClockCommon.
9CVDD181.
8VClockSupply.
10CVDD181.
8VClockSupply.
11CGNDClockCommon.
12AGNDAnalogCommon.
13SYNC_I+DifferentialSynchronizationInput.
14SYNC_IDifferentialSynchronizationInput.
15DGNDDigitalCommon.
16DVDD181.
8VDigitalSupply.
17P1DPort1,DataInputD15(MSB).
18P1DPort1,DataInputD14.
19P1DPort1,DataInputD13.
20P1DPort1,DataInputD12.
21P1DPort1,DataInputD11.
PinNo.
MnemonicDescription22DGNDDigitalCommon.
23DVDD181.
8VDigitalSupply.
24P1DPort1,DataInputD10.
25P1DPort1,DataInputD9.
26P1DPort1,DataInputD8.
27P1DPort1,DataInputD7.
28P1DPort1,DataInputD6.
29P1DPort1,DataInputD5.
30P1DPort1,DataInputD4.
31P1DPort1,DataInputD3.
32DGNDDigitalCommon.
33DVDD181.
8VDigitalSupply.
34P1DPort1,DataInputD2.
35P1DPort1,DataInputD1.
36P1DPort1,DataInputD0(LSB).
37DATACLKDataClockOutput.
38DVDD333.
3VDigitalSupply.
39TXENABLETransmitEnable.
40P2DPort2,DataInputD15(MSB).
41P2DPort2,DataInputD14.
42P2DPort2,DataInputD13.
AD9776/AD9778/AD9779Rev.
A|Page14of56PinNo.
MnemonicDescription43DVDD181.
8VDigitalSupply.
44DGNDDigitalCommon.
45P2DPort2,DataInputD12.
46P2DPort2,DataInputD11.
47P2DPort2,DataInputD10.
48P2DPort2,DataInputD9.
49P2DPort2,DataInputD8.
50P2DPort2,DataInputD7.
51P2DPort2,DataInputD6.
52P2DPort2,DataInputD5.
53DVDD181.
8VDigitalSupply.
54DGNDDigitalCommon.
55P2DPort2,DataInputD4.
56P2DPort2,DataInputD3.
57P2DPort2,DataInputD2.
58P2DPort2,DataInputD1.
59P2DPort2,DataInputD0(LSB).
60DVDD181.
8VDigitalSupply.
61DVDD333.
3VDigitalSupply.
62SYNC_ODifferentialSynchronizationOutput.
63SYNC_O+DifferentialSynchronizationOutput.
64DGNDDigitalCommon.
65PLL_LOCKPLLLockIndicator.
66SPI_SDOSPIPortDataOutput.
67SPI_SDIOSPIPortDataInput/Output.
68SCLKSPIPortClock.
69SPI_CSBSPIPortChipSelectBar.
70RESETReset,ActiveHigh.
71IRQInterruptRequest.
72AGNDAnalogCommon.
73IPTATFactoryTestPin.
Outputcurrentisproportionaltoabsolutetemperature,approximately10μAat25°Cwithapproximately20nA/°Cslope.
Thispinshouldremainfloating.
PinNo.
MnemonicDescription74VREFVoltageReferenceOutput.
75I120120μAReferenceCurrent.
76AVDD333.
3VAnalogSupply.
77AGNDAnalogCommon.
78AVDD333.
3VAnalogSupply.
79AGNDAnalogCommon.
80AVDD333.
3VAnalogSupply.
81AGNDAnalogCommon.
82AGNDAnalogCommon.
83OUT2_PDifferentialDACCurrentOutput,Channel2.
84OUT2_NDifferentialDACCurrentOutput,Channel2.
85AGNDAnalogCommon.
86AUX2_PAuxiliaryDACCurrentOutput,Channel2.
87AUX2_NAuxiliaryDACCurrentOutput,Channel2.
88AGNDAnalogCommon.
89AUX1_NAuxiliaryDACCurrentOutput,Channel1.
90AUX1_PAuxiliaryDACCurrentOutput,Channel1.
91AGNDAnalogCommon.
92OUT1_NDifferentialDACCurrentOutput,Channel1.
93OUT1_PDifferentialDACCurrentOutput,Channel1.
94AGNDAnalogCommon.
95AGNDAnalogCommon.
96AVDD333.
3VAnalogSupply.
97AGNDAnalogCommon.
98AVDD333.
3VAnalogSupply.
99AGNDAnalogCommon.
100AVDD333.
3VAnalogSupply.
1ThecombineddifferentialclockinputattheCLK+andCLK–pinsarereferredtoasREFCLK.
AD9776/AD9778/AD9779Rev.
A|Page15of56TYPICALPERFORMANCECHARACTERISTICS4–60CODEINL(16-BITLSB)3210–1–2–3–4–510k20k30k60k50k40k05361-005Figure6.
AD9779TypicalINL1.
5–2.
0–1.
5–1.
0–0.
500.
51.
0060k50k40k30k20k10kCODEDNL(16-BITLSB)05361-006Figure7.
AD9779TypicalDNL100500100fOUT(MHz)SFDR(dBc)9080706020406080fDATA=160MSPSfDATA=200MSPSfDATA=250MSPS05361-007Figure8.
AD9779In-BandSFDRvs.
fOUT,1xInterpolation100500100fOUT(MHz)SFDR(dBc)9080706020406080fDATA=160MSPSfDATA=200MSPSfDATA=250MSPS05361-008Figure9.
AD9779In-BandSFDRvs.
fOUT,2*Interpolation100500100fOUT(MHz)SFDR(dBc)9080706020406080fDATA=100MSPSfDATA=200MSPSfDATA=150MSPS05361-009Figure10.
AD9779In-BandSFDRvs.
fOUT,4*Interpolation10050050fOUT(MHz)SFDR(dBc)9080706010203040fDATA=50MSPSfDATA=100MSPSfDATA=125MSPS05361-010Figure11.
AD9779In-BandSFDRvs.
fOUT,8*InterpolationAD9776/AD9778/AD9779Rev.
A|Page16of56100500100fOUT(MHz)SFDR(dBc)9080706020406080fDATA=200MSPSfDATA=160MSPSfDATA=250MSPS05361-011Figure12.
AD9779Out-of-BandSFDRvs.
fOUT,2*Interpolation100500100fOUT(MHz)SFDR(dBc)9080706020406080fDATA=150MSPSfDATA=100MSPSfDATA=200MSPS05361-012Figure13.
AD9779Out-of-BandSFDRvs.
fOUT,4*Interpolation10050050fOUT(MHz)SFDR(dBc)9080706010203040fDATA=50MSPSfDATA=100MSPSfDATA=125MSPS05361-013Figure14.
AD9779Out-of-BandSFDRvs.
fOUT,8*Interpolation1005004fOUT(MHz)SFDR(dBc)090807060102030PLLOFFPLLON05361-014Figure15.
AD9779In-BandSFDR,4*Interpolation,fDATA=100MSPS,PLLOn/Off1005008fOUT(MHz)SFDR(dBc)090807060204060–3dBFS0dBFS–6dBFS05361-015Figure16.
AD9779In-BandSFDRvs.
DigitalFull-ScaleInput1005008fOUT(MHz)SFDR(dBc)09080706020406010mA20mA30mA05361-016Figure17.
AD9779In-BandSFDRvs.
OutputFull-ScaleCurrentAD9776/AD9778/AD9779Rev.
A|Page17of56100500120fOUT(MHz)IMD(dBc)9080706020406080100fDATA=200MSPSfDATA=250MSPSfDATA=160MSPS05361-017Figure18.
AD9779Third-OrderIMDvs.
fOUT,1*Interpolation10050020406080100120140160180200220fOUT(MHz)IMD(dBc)90807060fDATA=160MSPSfDATA=250MSPSfDATA=200MSPS05361-018Figure19.
AD9779Third-OrderIMDvs.
fOUT,2*Interpolation100500400fOUT(MHz)IMD(dBc)908070604080120160200240280320360fDATA=150MSPSfDATA=200MSPSfDATA=100MSPS05361-019Figure20.
AD9779Third-OrderIMDvs.
fOUT,4*InterpolationfOUT(MHz)IMD(dBc)fDATA=75MSPSfDATA=125MSPSfDATA=100MSPS90100807060504504254003753503253002752502252001751501251007550250fDATA=50MSPS05361-020Figure21.
AD9779Third-OrderIMDvs.
fOUT,8*Interpolation100500200fOUT(MHz)IMD(dBc)9080706010020406080120140160180PLLOFFPLLON05361-021Figure22.
AD9779Third-OrderIMDvs.
fOUT,4*Interpolation,fDATA=100MSPS,PLLOnvs.
PLLOff1009550550400360fOUT(MHz)IMD(dBc)90808570756065408012016020024028032005361-022Figure23.
AD9779Third-OrderIMDvs.
fOUT,over50Parts,4*Interpolation,fDATA=200MSPSAD9776/AD9778/AD9779Rev.
A|Page18of56100505560657075808590950400fOUT(MHz)IMD(dBc)801602403603204012020028005361-1170dBFS–3dBFS–6dBFSFigure24.
IMDPerformancevs.
DigitalFull-ScaleInput,4*Interpolation,fDATA=200MSPS100505560657075808590950400fOUT(MHz)IMD(dBc)801602403603204012020028005361-11820mA10mA30mAFigure25.
IMDPerformancevs.
Full-ScaleOutputCurrent,4*Interpolation,fDATA=200MSPSSTOP400.
0MHzSWEEP1.
203s(601pts)VBW20kHzSTART1.
0MHz*RESBW20kHzREF0dBm*PEAKLog10dB/LGAV51W1S3(f):FTUNSWPS2FCAA*ATTEN20dBEXTREFDCCOUPLED05361-023Figure26.
AD9779SingleTone,4*Interpolation,fDATA=100MSPS,fOUT=30MHzSTOP400.
0MHzSWEEP1.
203s(601pts)VBW20kHzSTART1.
0MHz*RESBW20kHzREF0dBm*PEAKLog10dB/LGAV51W1S3(f):FTUNSWPS2FCAA*ATTEN20dBEXTREFDCCOUPLED05361-024Figure27.
AD9779Two-ToneSpectrum,4*Interpolation,fDATA=100MSPS,fOUT=30MHz,35MHz–142–146–150–154–158–162–166–1700fOUT(MHz)NSD(dBm/Hz)204060800dBFS–3dBFS–6dBFS05361-025Figure28.
AD9779NoiseSpectralDensityvs.
DigitalFull-ScaleofSingle-ToneInput,fDATA=200MSPS,2*Interpolation–150–1700100fOUT(MHz)NSD(dBm/Hz)–154–158–162–16620406080fDAC=800MSPSfDAC=400MSPSfDAC=200MSPS05361-026Figure29.
AD9779NoiseSpectralDensityvs.
fDAC,Eight-ToneInputwith500kHzSpacing,fDATA=200MSPSAD9776/AD9778/AD9779Rev.
A|Page19of56–150–1700100fOUT(MHz)NSD(dBm/Hz)–154–158–162–16620406080fDAC=800MSPSfDAC=400MSPSfDAC=200MSPS05361-027Figure30.
AD9779NoiseSpectralDensityvs.
fDAC,Single-ToneInputat6dBFS–55–900260fOUT(MHz)ACLR(dBc)–60–65–70–75–80–8520406080100120140160180200220240–6dBFS–3dBFS0dBFS–PLLON0dBFS05361-028Figure31.
AD9779ACLRforFirstAdjacentBandWCDMA,4*Interpolation,fDATA=122.
88MSPS,On-ChipModulationTranslatesBasebandSignaltoIF–55–900260fOUT(MHz)ACLR(dBc)–60–65–70–75–80–8520406080100120140160180200220240–6dBFS–3dBFS0dBFS–PLLON0dBFS05361-029Figure32.
AD9779ACLRforSecondAdjacentBandWCDMA,4*Interpolation,fDATA=122.
88MSPS.
On-ChipModulationTranslatesBasebandSignaltoIF–55–900260fOUT(MHz)ACLR(dBc)–60–65–70–75–80–8520406080100120140160180200220240–6dBFS–3dBFS0dBFS–PLLON0dBFS05361-030Figure33.
AD9779ACLRforThirdAdjacentBandWCDMA,4*Interpolation,fDATA=122.
88MSPS,On-ChipModulationTranslatesBasebandSignaltoIFAD9776/AD9778/AD9779Rev.
A|Page20of56SPAN50MHzSWEEP162.
2ms(601pts)VBW300kHzCENTER143.
88MHz*RESBW30kHzRMSRESULTSCARRIERPOWER–12.
49dBm/3.
84000MHzFREQOFFSET5.
000MHz10.
00MHz15.
00MHzREFBW3.
840MHz3.
840MHz3.
840MHzdBc–76.
75–80.
94–79.
95dBm–89.
23–93.
43–92.
44LOWERdBc–77.
42–80.
47–78.
96dBm–89.
91–92.
96–91.
45UPPERREF–25.
28dBm*AVGLog10dB/PAVG10W1S2*ATTEN4dBEXTREF05361-031Figure34.
AD9779WCDMASignal,4*Interpolation,fDATA=122.
88MSPS,fDAC/4ModulationSPAN50MHzSWEEP162.
2ms(601pts)VBW300kHzCENTER151.
38MHz*RESBW30kHz1–17.
87dBm2–20.
65dBm3–18.
26dBm4–18.
23dBmTOTALCARRIERPOWER–12.
61dBm/15.
3600MHzREFCARRIERPOWER–17.
87dBm/3.
84000MHzFREQOFFSET5.
000MHz10.
00MHz15.
00MHzINTEGBW3.
840MHz3.
840MHz3.
840MHzdBc–67.
70–70.
00–71.
65dBm–85.
57–97.
87–99.
52LOWERdBc–67.
70–69.
32–71.
00dBm–85.
57–87.
19–88.
88UPPERREF–30.
28dBm*AVGLog10dB/PAVG10W1S2*ATTEN4dBEXTREF05361-032Figure35.
AD9779MulticarrierWCDMASignal,4*Interpolation,fDAC=122.
88MSPS,fDAC/4Modulation1.
50CODEINL(14-BITLSB)10k1.
00.
50–0.
5–1.
0–1.
52k4k6k8k05361-033Figure36.
AD9778TypicalINL0.
60CODEDNL(14-BITLSB)–0.
2–1.
016k14k12k10k8k6k4k2k0.
40.
20–0.
4–0.
6–0.
805361-034Figure37.
AD9778TypicalDNLAD9776/AD9778/AD9779Rev.
A|Page21of56100500400fOUT(MHz)IMD(dBc)9080706040801201602002402803203604*200MSPS4*150MSPS4*100MSPS05361-035Figure38.
AD9778IMD,4*Interpolation100500100fOUT(MHz)SFDR(dBc)9080706020406080fDATA=250MSPSfDATA=200MSPSfDATA=160MSPS05361-036Figure39.
AD9778In-BandSFDR,2*Interpolation–900250fOUT(MHz)ACLR(dBc)–70–80–602550751001251501752002251STADJCHAN2NDADJCHAN3RDADJCHAN05361-037Figure40.
AD9778ACLR,Single-CarrierWCDMA,4*Interpolation,fDATA=122.
88MSPS,Amplitude=3dBFSSPAN50MHzSWEEP162.
2ms(601pts)VBW300kHzCENTER143.
88MHz*RESBW30kHzRMSRESULTSCARRIERPOWER–12.
74dBm/3.
84000MHzFREQOFFSET5.
000MHz10.
00MHz15.
00MHzREFBW3.
884MHz3.
840MHz3.
840MHzdBc–76.
49–80.
13–80.
90dBm–89.
23–92.
87–93.
64LOWERdBc–76.
89–80.
02–79.
53dBm–89.
63–92.
76–92.
27UPPERREF–25.
39dBm*AVGLog10dB/PAVG10W1S2*ATTEN4dB05361-038Figure41.
AD9778ACLR,fDATA=122.
88MSPS,4*Interpolation,fDAC/4Modulation–150–1700100fOUT(MHz)NSD(dBm/Hz)–154–158–162–16620406080fDAC=800MSPSfDAC=400MSPSfDAC=200MSPS05361-039Figure42.
AD9778NoiseSpectralDensityvs.
fDACEight-ToneInputwith500kHzSpacing,fDATA=200MSPS–150–1700100fOUT(MHz)NSD(dBm/Hz)–154–158–162–16620406080fDAC=800MSPSfDAC=400MSPSfDAC=200MSPS05361-040Figure43.
AD9778NoiseSpectralDensityvs.
fDACSingle-ToneInputat6dBFS,fDATA=200MSPSAD9776/AD9778/AD9779Rev.
A|Page22of560.
404096CODEINL(12-BITLSB)–0.
45121024256020481536307235840.
30.
20.
10–0.
1–0.
2–0.
305361-041Figure44.
AD9776TypicalINL0.
2004096CODEDNL(12-BITLSB)2048–0.
20512102415362560307235840.
150.
100.
050–0.
05–0.
10–0.
1505361-042Figure45.
AD9776TypicalDNL100500400fOUT(MHz)IMD(dBc)40801201602002402803203604*200MSPS4*100MSPS4*150MSPS95908580757065605505361-043Figure46.
AD9776IMD,4*Interpolation100500100fOUT(MHz)SFDR(dBc)9080706020406080fDATA=250MSPSfDATA=200MSPSfDATA=160MSPS05361-044Figure47.
AD9776In-BandSFDR,2*Interpolation–900250FOUT(MHz)ACLR(dBc)–552550751001251501752002251STADJCHAN2NDADJCHAN3RDADJCHAN–60–65–70–75–80–8505361-045Figure48.
AD9776ACLR,fDATA=122.
88MSPS,4*Interpolation,fDAC/4ModulationSPAN50MHzSWEEP162.
2ms(601pts)VBW300kHzCENTER143.
88MHz*RESBW30kHzRMSRESULTSCARRIERPOWER–12.
67dBm/3.
84000MHzFREQOFFSET5.
000MHz10.
00MHz15.
00MHzREFBW3.
884MHz3.
840MHz3.
840MHzdBc–75.
00–78.
05–77.
73dBm–87.
67–90.
73–90.
41LOWERdBc–75.
30–77.
99–77.
50dBm–87.
97–90.
66–90.
17UPPERREF–25.
29dBm*AVGLog10dB/PAVG10W1S2*ATTEN4dB05361-046Figure49.
AD9776,SingleCarrierWCDMA,4*Interpolation,fDATA=122.
88MSPS,Amplitude=3dBFSAD9776/AD9778/AD9779Rev.
A|Page23of56–150–1700100fOUT(MHz)NSD(dBm/Hz)–154–158–162–16620406080fDAC=800MSPSfDAC=400MSPSfDAC=200MSPS103050709005361-047Figure50.
AD9776NoiseSpectralDensityvs.
fDAC,Eight-ToneInputwith500kHzSpacing,fDATA=200MSPS–150–1700100fOUT(MHz)NSD(dBm/Hz)–154–158–162–16620406080fDAC=800MSPSfDAC=400MSPSfDAC=200MSPS103050709005361-048Figure51.
AD9776NoiseSpectralDensityvs.
fDAC,Single-ToneInputat6dBFS,fDATA=200MSPSAD9776/AD9778/AD9779Rev.
A|Page24of56TERMINOLOGYIntegralNonlinearity(INL)INLisdefinedasthemaximumdeviationoftheactualanalogoutputfromtheidealoutput,determinedbyastraightlinedrawnfromzeroscaletofullscale.
DifferentialNonlinearity(DNL)DNListhemeasureofthevariationinanalogvalue,normalizedtofullscale,associatedwitha1LSBchangeindigitalinputcode.
MonotonicityADACismonotoniciftheoutputeitherincreasesorremainsconstantasthedigitalinputincreases.
OffsetErrorThedeviationoftheoutputcurrentfromtheidealofzeroiscalledoffseterror.
ForIOUTA,0mAoutputisexpectedwhentheinputsareall0s.
ForIOUTB,0mAoutputisexpectedwhenallinputsaresetto1.
BGainErrorThedifferencebetweentheactualandidealoutputspan.
Theactualspanisdeterminedbythedifferencebetweentheoutputwhenallinputsaresetto1andtheoutputwhenallinputsaresetto0.
OutputComplianceRangeTherangeofallowablevoltageattheoutputofacurrent-outputDAC.
Operationbeyondthemaximumcompliancelimitscancauseeitheroutputstagesaturationorbreakdown,resultinginnonlinearperformance.
TemperatureDriftTemperaturedriftisspecifiedasthemaximumchangefromtheambient(25°C)valuetothevalueateitherTMINorTMAX.
Foroffsetandgaindrift,thedriftisreportedinppmoffull-scalerange(FSR)perdegreeCelsius.
Forreferencedrift,thedriftisreportedinppmperdegreeCelsius.
PowerSupplyRejection(PSR)Themaximumchangeinthefull-scaleoutputasthesuppliesarevariedfromminimumtomaximumspecifiedvoltages.
SettlingTimeThetimerequiredfortheoutputtoreachandremainwithinaspecifiederrorbandarounditsfinalvalue,measuredfromthestartoftheoutputtransition.
In-BandSpuriousFreeDynamicRange(SFDR)Thedifference,indecibels,betweenthepeakamplitudeoftheoutputsignalandthepeakspurioussignalbetweendcandthefrequencyequaltohalftheinputdatarate.
Out-of-BandSpuriousFreeDynamicRange(SFDR)Thedifference,indecibels,betweenthepeakamplitudeoftheoutputsignalandthepeakspurioussignalwithinthebandthatstartsatthefrequencyoftheinputdatarateandendsattheNyquistfrequencyoftheDACoutputsamplerate.
Normally,energyinthisbandisrejectedbytheinterpolationfilters.
Thisspecification,therefore,defineshowwelltheinterpolationfiltersworkandtheeffectofotherparasiticcouplingpathstotheDACoutput.
TotalHarmonicDistortion(THD)THDistheratioofthermssumofthefirstsixharmoniccom-ponentstothermsvalueofthemeasuredfundamental.
Itisexpressedasapercentageorindecibels.
Signal-to-NoiseRatio(SNR)SNRistheratioofthermsvalueofthemeasuredoutputsignaltothermssumofallotherspectralcomponentsbelowtheNyquistfrequency,excludingthefirstsixharmonicsanddc.
ThevalueforSNRisexpressedindecibels.
InterpolationFilterIfthedigitalinputstotheDACaresampledatamultiplerateoffDATA(interpolationrate),adigitalfiltercanbeconstructedthathasasharptransitionbandnearfDATA/2.
ImagesthattypicallyappeararoundfDAC(outputdatarate)canbegreatlysuppressed.
AdjacentChannelLeakageRatio(ACLR)TheratioindBcbetweenthemeasuredpowerwithinachannelrelativetoitsadjacentchannel.
ComplexImageRejectionInatraditionaltwo-partupconversion,twoimagesarecreatedaroundthesecondIFfrequency.
Theseimageshavetheeffectofwastingtransmitterpowerandsystembandwidth.
Byplacingtherealpartofasecondcomplexmodulatorinserieswiththefirstcomplexmodulator,eithertheupperorlowerfrequencyimagenearthesecondIFcanberejected.
AD9776/AD9778/AD9779Rev.
A|Page25of56THEORYOFOPERATIONTheAD9776/AD9778/AD9779combinemanyfeaturesthatmakethemveryattractiveDACsforwiredandwirelesscommunicationssystems.
ThedualdigitalsignalpathanddualDACstructureallowaneasyinterfacewithcommonquadraturemodulatorswhendesigningsinglesidebandtransmitters.
ThespeedandperformanceofthepartsallowwiderbandwidthsandmorecarrierstobesynthesizedthaninpreviouslyavailableDACs.
Thedigitalengineusesabreak-throughfilterarchitecturethatcombinestheinterpolationwithadigitalquadraturemodulator.
Thisallowsthepartstoconductdigitalquadraturefrequencyupconversion.
Theyalsohavefeaturesthatallowsimplifiedsynchronizationwithincomingdataandbetweenmultipleparts.
TheserialportconfigurationiscontrolledbyRegister0x00,Bits.
Itisimportanttonotethattheconfigurationchangesimmediatelyuponwritingtothelastbitofthebyte.
Formulti-bytetransfers,writingtothisregistercanoccurduringthemiddleofacommunicationcycle.
Caremustbetakentocompensateforthisnewconfigurationfortheremainingbytesofthecurrentcommunicationcycle.
Thesameconsiderationsapplytosettingthesoftwarereset,RESET(Register0x00,Bit5)orpullingtheRESETpin(Pin70)high.
Allregistersaresettotheirdefaultvalues,exceptRegister0x00andRegister0x04,whichremainunchanged.
Useofonlysingle-bytetransferswhenchangingserialportconfigurationsorinitiatingasoftwareresetisrecommendedtopreventunexpecteddevicebehavior.
Asdescribedinthissection,allserialportdataistransferredto/fromthedeviceinsynchronizationtotheSCLKpin.
Ifsynchronizationislost,thedevicehastheabilitytoasynchro-nouslyterminateanI/Ooperation,puttingtheserialportcontrollerintoaknownstateand,thereby,regainingsynchronization.
SERIALPERIPHERALINTERFACESPI_SDOSPIPORT66SPI_SDI67SPI_SCLK68SPI_CSB6905361-049Figure52.
SPIPortTheserialportisaflexible,synchronousserialcommunicationsportallowingeasyinterfacetomanyindustry-standardmicro-controllersandmicroprocessors.
TheserialI/Oiscompatiblewithmostsynchronoustransferformats,includingboththeMotorolaSPIandIntelSSRprotocols.
Theinterfaceallowsread/writeaccesstoallregistersthatconfiguretheAD9776/AD9778/AD9779.
Singleormultiplebytetransfersaresup-ported,aswellasMSB-firstorLSB-firsttransferformats.
TheserialinterfaceportscanbeconfiguredasasinglepinI/O(SDIO)ortwounidirectionalpinsforinput/output(SDIO/SDO).
GeneralOperationoftheSerialInterfaceTherearetwophasestoacommunicationcyclewiththeAD977x.
Phase1istheinstructioncycle(thewritingofaninstructionbyteintothedevice),coincidentwiththefirsteightSCLKrisingedges.
Theinstructionbyteprovidestheserialportcontrollerwithinformationregardingthedatatransfercycle,Phase2ofthecommunicationcycle.
ThePhase1instructionbytedefineswhethertheupcomingdatatransferisareadorwrite,thenumberofbytesinthedatatransfer,andthestartingregisteraddressforthefirstbyteofthedatatransfer.
ThefirsteightSCLKrisingedgesofeachcommunicationcycleareusedtowritetheinstructionbyteintothedevice.
AlogichighontheCSBpinfollowedbyalogiclowresetstheSPIporttimingtotheinitialstateoftheinstructioncycle.
Fromthisstate,thenexteightrisingSCLKedgesrepresenttheinstructionbitsofthecurrentI/Ooperation,regardlessofthestateoftheinternalregistersortheothersignallevelsattheinputstotheSPIport.
IftheSPIportisinaninstructioncycleoradatatransfercycle,noneofthepresentdataiswritten.
TheremainingSCLKedgesareforPhase2ofthecommunica-tioncycle.
Phase2istheactualdatatransferbetweenthedeviceandthesystemcontroller.
Phase2ofthecommunicationcycleisatransferofone,two,three,orfourdatabytesasdeterminedbytheinstructionbyte.
Usingonemultibytetransferispreferred.
Single-bytedatatransfersareusefulinreducingCPUoverheadwhenregisteraccessrequiresonlyonebyte.
Registerschangeimmediatelyuponwritingtothelastbitofeachtransferbyte.
InstructionByteTheinstructionbytecontainstheinformationshowninTable9.
Table9.
SPIInstructionByteMSBLSBI7I6I5I4I3I2I1I0R/WN1N0A4A3A2A1A0R/W,Bit7oftheinstructionbyte,determineswhetherareadorawritedatatransferoccursaftertheinstructionbytewrite.
Logichighindicatesareadoperation.
Logic0indicatesawriteoperation.
N1andN0,Bit6andBit5oftheinstructionbyte,determinethenumberofbytestobetransferredduringthedatatransfercycle.
ThebitdecodesarelistedinTable10.
A4,A3,A2,A1,andA0—Bit4,Bit3,Bit2,Bit1,andBit0,respec-tively,oftheinstructionbytedeterminetheregisterthatisaccessedduringthedatatransferportionofthecommunicationcycle.
AD9776/AD9778/AD9779Rev.
A|Page26of56Formultibytetransfers,thisaddressisthestartingbyteaddress.
TheremainingregisteraddressesaregeneratedbythedevicebasedontheLSB-firstbit(Register0x00,Bit6).
Table10.
ByteTransferCountN1N0Description00Transferonebyte01Transferthreebytes10Transfertwobytes11TransferfourbytesSerialInterfacePortPinDescriptionsSerialClock(SCLK)Theserialclockpinsynchronizesdatatoandfromthedeviceandtoruntheinternalstatemachines.
ThemaximumfrequencyofSCLKis40MHz.
AlldatainputisregisteredontherisingedgeofSCLK.
AlldataisdrivenoutonthefallingedgeofSCLK.
ChipSelect(CSB)Activelowinputstartsandgatesacommunicationcycle.
Itallowsmorethanonedevicetobeusedonthesameserialcommunicationslines.
TheSDOandSDIOpinsgotoahighimpedancestatewhenthisinputishigh.
Chipselectshouldstaylowduringtheentirecommunicationcycle.
SerialDataI/O(SDIO)Dataisalwayswrittenintothedeviceonthispin.
However,thispincanbeusedasabidirectionaldataline.
TheconfigurationofthispiniscontrolledbyRegister0x00,Bit7.
ThedefaultisLogic0,configuringtheSDIOpinasunidirectional.
SerialDataOut(SDO)Dataisreadfromthispinforprotocolsthatuseseparatelinesfortransmittingandreceivingdata.
InthecasewherethedeviceoperatesinasinglebidirectionalI/Omode,thispindoesnotoutputdataandissettoahighimpedancestate.
MSB/LSBTRANSFERSTheserialportcansupportbothMSB-firstandLSB-firstdataformats.
ThisfunctionalityiscontrolledbyRegisterBitLSB_FIRST(Register0x00,Bit6).
ThedefaultisMSB-first(LSB-first=0).
WhenLSB-first=0(MSB-first)theinstructionanddatabitmustbewrittenfromMSBtoLSB.
MultibytedatatransfersinMSB-firstformatstartwithaninstructionbytethatincludestheregisteraddressofthemostsignificantdatabyte.
Subsequentdatabytesshouldfollowfromhighaddresstolowaddress.
InMSB-firstmode,theserialportinternalbyteaddressgeneratordecrementsforeachdatabyteofthemultibytecommunicationcycle.
WhenLSB-first=1(LSB-first)theinstructionanddatabitmustbewrittenfromLSBtoMSB.
MultibytedatatransfersinLSB-firstformatstartwithaninstructionbytethatincludestheregisteraddressoftheleastsignificantdatabytefollowedbymul-tipledatabytes.
Theserialportinternalbyteaddressgeneratorincrementsforeachbyteofthemultibytecommunicationcycle.
Theserialportcontrollerdataaddressdecrementsfromthedataaddresswrittentoward0x00formultibyteI/OoperationsiftheMSB-firstmodeisactive.
Theserialportcontrolleraddressincrementsfromthedataaddresswrittentoward0x1FformultibyteI/OoperationsiftheLSB-firstmodeisactive.
R/WN1N0A4A3A2A1A0D7D6ND5ND00D10D20D30D7D6ND5ND00D10D20D30INSTRUCTIONCYCLEDATATRANSFERCYCLECSBSCLKSDIOSDO05361-050Figure53.
SerialRegisterInterfaceTimingMSB-FirstA0A1A2A3A4N0N1R/WD00D10D20D7ND6ND5ND4ND00D10D20D7ND6ND5ND4NINSTRUCTIONCYCLEDATATRANSFERCYCLECSBSCLKSDIOSDO05361-051Figure54.
SerialRegisterInterfaceTimingLSB-FirstINSTRUCTIONBIT6INSTRUCTIONBIT7CSBSCLKSDIOtDStDStDHtPWHtPWLtSCLK05361-052Figure55.
TimingDiagramforSPIRegisterWriteDATABITn–1DATABITnCSBSCLKSDIOSDOtDV05361-053Figure56.
TimingDiagramforSPIRegisterReadAD9776/AD9778/AD9779Rev.
A|Page27of56SPIREGISTERMAPTable11.
RegisterNameAddressBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Def.
Comm0x0000SDIOBidirectionalLSB/MSBFirstSoftwareResetPower-DownModeAutoPower-DownEnablePLLLockIndicator(ReadOnly)0x000x0101FilterInterpolationFactorFilterModulationModeZeroStuffingEnable0x00DigitalControl0x0202DataFormatDual/InterleavedDataBusModeRealModeDataClockDelayEnableInverseSincEnableDATACLKInvertTxEnableInvertQFirst0x00SyncControl0x0303DataClockDelayModeDataClockDivideRatioReserved0x000x0404DataClockDelayOutputSyncPulseDivideSyncOutDelay0x000x0505SyncOutDelayInputSyncPulseFrequencyRatioSyncInputDelay0x000x0606SyncInputDelayInputSyncPulseTimingErrorTolerance0x000x0707SyncReceiverEnableSyncDriverEnableSyncTriggeringEdgeDACClockOffset0x00PLLControl0x0808PLLBandSelectPLLVCOAGCGain0xCF0x0909PLLEnablePLLVCODividerRatioPLLLoopDivideRatioPLLBiasSetting0x37MiscControl0x0A10PLLControlVoltageRange(ReadOnly)PLLLoopBandwidthAdjustment0x380x0B11IDACGainAdjustment0xF9IDACControlRegister0x0C12IDACSleepIDACPowerDownIDACGainAdjustment0x010x0D13AuxiliaryDAC1Data0x00AuxDAC1ControlRegister0x0E14AuxiliaryDAC1SignAuxiliaryDAC1CurrentDirectionAuxiliaryDAC1Power-DownAuxiliaryDAC1Data0x000x0F15QDACGainAdjustment0xF9QDACControlRegister0x1016QDACSleepQDACPower-DownQDACGainAdjustment0x010x1117AuxiliaryDAC2Data0x000x1218AuxiliaryDAC2SignAuxiliaryDAC2CurrentDirectionAuxiliaryDAC2Power-DownAuxiliaryDAC2Data0x00AuxDAC2ControlRegister0x13to0x1819to24Reserved0x1925SyncDelayIRQSyncDelayIRQEnableInternalSyncLoopback0x00InterruptRegister0x1Ato0x1F26to31ReservedAD9776/AD9778/AD9779Rev.
A|Page28of56Table12.
SPIRegisterDescriptionAddressRegisterNameReg.
No.
BitsDescriptionFunctionDefaultCommRegister007SDIObidirectional0:useSDIOpinasinputdataonly01:useSDIOasbothinputandoutputdata006LSB/MSBfirst0:firstbitofserialdataisMSBofdatabyte01:firstbitofserialdataisLSBofdatabyte005SoftwareresetBitmustbewrittenwitha1,then0tosoftresetSPIregistermap0004Power-downmode0:allcircuitryisactive1:disablealldigitalandanalogcircuitry,onlySPIportisactive003Autopower-downenableControlsautopower-downmode,seethePower-DownandSleepModessection0001PLLlock(readonly)0:PLLisnotlocked1:PLLislocked0DigitalControlRegister017:6Filterinterpolationfactor00:1*interpolation0001:2*interpolation10:4*interpolation11:8*interpolation015:2FiltermodulationmodeSeeTable21forfiltermodes0000010Zerostuffing0:zerostuffingoff01:zerostuffingon027Dataformat0:signedbinary01:unsignedbinary026Dual/interleaveddatabusmode0:bothinputdataportsreceivedata01:DataPort1onlyreceivesdata025Realmode0:enableQpathforsignalprocessing01:disableQpathdata(internalQchannelclocksdisabled,IandQmodulatorsdisabled)024DATACLKdelayenableSeetheUsingDataDelaytoMeetTimingRequirementssection.
023Inversesincenable0:inversesincfilterdisabled01:inversesincfilterenabled022DATACLKinvert0:outputDATACLKsamephaseasinternalcaptureclock01:outputDATACLKoppositephaseasinternalcaptureclock021TxEnableinvertInvertsthefunctionofTxEnablePin39,seetheInterleavedDataModesection0020Qfirst0:firstbyteofdataisalwaysIdataatbeginningoftransmit1:firstbyteofdataisalwaysQdataatbeginningoftransmitSyncControlRegister037:6Dataclockdelaymode00:manual00035:4ExtradataclockdivideratioDataclockoutputdivider(seeTable22fordividerratio)00033:0Reserved000047:4DataclockdelaySetsdelayofREFCLKintoDATACLKout0000043:1OutputsyncpulsedivideSetsfrequencyofSYNC_Opulses000040SyncoutdelaySyncoutputdelay,Bit4057:4SyncoutdelaySyncoutputdelay,Bits0053:1InputsyncpulsefrequencyInputsyncpulsefrequencydivider,seetheAN-822applicationnote000050SyncinputdelaySyncinputdelay,Bit40AD9776/AD9778/AD9779Rev.
A|Page29of56AddressRegisterNameReg.
No.
BitsDescriptionFunctionDefaultSyncControlRegister067:4SyncinputdelaySeetheMultipleDACSynchronizationsectionfordetailsonusingtheseregisterstosynchronizemultipleDACs0063:0Inputsyncpulsetimingerrortolerance0077Syncreceiverenable0076Syncdriverenable0075Synctriggeringedge0074:0SYNC_Itoinputdatasamplingclockoffset0PLLControl087:2PLLbandselectVCOfrequencyrangevs.
PLLbandselectvalue(seeTable18)111001081:0VCOAGCgaincontrolLowernumber(lowgain)isgenerallybetterforperformance11097PLLenable0:PLLoff,DACrateclocksuppliedbyoutsidesource01:PLLon,DACrateclocksynthesizedinternallyfromexternalreferenceclockviaPLLclockmultiplier096:5PLLVCOdivideratioFVCO/fDAC00*101*210*411*8094:3PLLloopdivideratiofDAC/fREF00*201*410*811*16092:0PLLbiassettingAlwayssetto0100100A7:5PLLcontrolvoltagerange000to111,proportionaltovoltageatPLLloopfilteroutput,readbackonlyMiscControl0A4:0PLLloopbandwidthadjustmentSeePLLLoopFilterBandwidthsectionfordetailsIDACControlRegister0B7:0IDACgainadjustment(7:0)LSBsliceof10-bitgainsettingwordforIDAC111110010C7IDACsleep0:IDACon01:IDACoff0C6IDACpower-down0:IDACon01:IDACoff0C1:0IDACgainadjustment(9:8)MSBsliceof10-bitgainsettingwordforIDAC010D7:0AuxDAC1gainadjustment(7:0)LSBsliceof10-bitgainsettingwordforAuxDAC1000000000E7AuxDAC1sign0:positive1:negative0E6AuxDAC1currentdirection0:source01:sink0E5AuxDAC1power-down0:AuxDAC1on01:AuxDAC1offAuxDAC1ControlRegister0E1:0AuxDAC1gainadjustment(9:8)MSBsliceof10-bitgainsettingwordforAuxDAC100AD9776/AD9778/AD9779Rev.
A|Page30of56AddressRegisterNameReg.
No.
BitsDescriptionFunctionDefaultQDACControlRegister0F7:0QDACgainadjustment(7:0)LSBsliceof10-bitgainsettingwordforQDAC11111001107QDACsleep0:QDACon01:QDACoff106QDACpower-down0:QDACon01:QDACoff101:0QDACgainadjustment(9:8)MSBsliceof10-bitgainsettingwordforQDAC117:0AuxDAC2gainadjustment(7:0)LSBsliceof10-bitgainsettingwordforAuxDAC200000000127AuxDAC2sign0:positive1:negative126AuxDAC2currentdirection0:source01:sink125AuxDAC2power-down0:AuxDAC2on01:AuxDAC2offAuxDAC2ControlRegister121:0AuxDAC2gainadjustment(9:8)MSBsliceof10-bitgainsettingwordforAuxDAC200InterruptRegister1970196SyncdelayIRQReadback,mustwrite0toclear019501930192SyncdelayIRQenable01910190Internalsyncloopback0AD9776/AD9778/AD9779Rev.
A|Page31of56INTERPOLATIONFILTERARCHITECTURETheAD9776/AD9778/AD9779canprovideupto8*interpola-tion,ortheinterpolationfilterscanbeentirelydisabled.
Itisimportanttonotethattheinputsignalshouldbebackedoffbyapproximately0.
01dBfromfullscaletoavoidoverflowingtheinterpolationfilters.
Thecoefficientsofthelow-passfiltersandtheinversesincfilteraregiveninTable13,Table14,Table15,andTable16.
SpectralplotsforthefilterresponsesareshowninFigure57,Figure58,andFigure59.
Table13.
Half-BandFilter1LowerCoefficientUpperCoefficientIntegerValueH(1)H(55)4H(2)H(54)0H(3)H(53)+13H(4)H(52)0H(5)H(51)34H(6)H(50)0H(7)H(49)+72H(8)H(48)0H(9)H(47)138H(10)H(46)0H(11)H(45)+245H(12)H(44)0H(13)H(43)408H(14)H(42)0H(15)H(41)+650H(16)H(40)0H(17)H(39)1003H(18)H(38)0H(19)H(37)+1521H(20)H(36)0H(21)H(35)2315H(22)H(34)0H(23)H(33)+3671H(24)H(32)0H(25)H(31)6642H(26)H(30)0H(27)H(29)+20,755H(28)+32,768Table14.
Half-BandFilter2LowerCoefficientUpperCoefficientIntegerValueH(1)H(23)2H(2)H(22)0H(3)H(21)+17H(4)H(20)0H(5)H(19)75H(6)H(18)0H(7)H(17)+238H(8)H(16)0H(9)H(15)660H(10)H(14)0H(11)H(13)+2530H(12)+4096Table15.
Half-BandFilter3LowerCoefficientUpperCoefficientIntegerValueH(1)H(15)39H(2)H(14)0H(3)H(13)+273H(4)H(12)0H(5)H(11)1102H(6)H(10)0H(7)H(9)+4964H(8)+8192Table16.
InverseSincFilterLowerCoefficientUpperCoefficientIntegerValueH(1)H(9)+2H(2)H(8)4H(3)H(7)+10H(4)H(6)35H(5)+40110–100–44fOUT(*InputDataRate)ATTENUATION(dB)–3–2–101230–10–20–30–40–50–60–70–80–9005361-054Figure57.
2*Interpolation,Low-PassResponseto±4*InputDataRate(DottedLinesIndicate1dBRoll-Off)10–100–44fOUT(*InputDataRate)ATTENUATION(dB)–3–2–101230–10–20–30–40–50–60–70–80–9005361-055Figure58.
4*Interpolation,Low-PassResponseto±4*InputDataRate(DottedLinesIndicate1dBRoll-Off)AD9776/AD9778/AD9779Rev.
A|Page32of5610–100–44fOUT(*InputDataRate)ATTENUATION(dB)–3–2–101230–10–20–30–40–50–60–70–80–9005361-056Figure59.
8*Interpolation,Low-PassResponseto±4*InputDataRate(DottedLinesIndicate1dBRoll-Off)Withtheinterpolationfilterandmodulatorcombined,theincomingsignalcanbeplacedanywherewithintheNyquistregionoftheDACoutputsamplerate.
Whentheinputsignaliscomplex,thisarchitectureallowsmodulationoftheinputsignaltopositiveornegativeNyquistregions(seeTable17).
TheNyquistregionsofupto4*theinputdataratecanbeseeninFigure60.
–4*–8–3*–6–2*–4–1*–2DC11*32*53*7–7–5–3–124684*05361-057Figure60.
NyquistZonesFigure57,Figure58,andFigure59showthelow-passresponseofthedigitalfilterswithnomodulation.
Byturningonthemodulationfeature,theresponseofthedigitalfilterscanbetunedtoanywherewithintheDACbandwidth.
Asanexample,Figure61toFigure67showthenonshiftedmodefilterresponses(refertoTable17forshifted/nonshiftedmodefilterresponses).
10–100–44–3–2–101230–10–20–30–40–50–60–70–80–90fOUT(*InputDataRate)ATTENUATION(dB)05361-058Figure61.
Interpolation/ModulationCombinationof4fDAC/8Filter10–100–44–3–2–101230–10–20–30–40–50–60–70–80–90fOUT(*InputDataRate)ATTENUATION(dB)05361-059Figure62.
Interpolation/ModulationCombinationof3fDAC/8Filter10–100–44–3–2–101230–10–20–30–40–50–60–70–80–90fOUT(*InputDataRate)ATTENUATION(dB)05361-060Figure63.
Interpolation/ModulationCombinationof2fDAC/8Filter10–100–44–3–2–101230–10–20–30–40–50–60–70–80–90fOUT(*InputDataRate)ATTENUATION(dB)05361-061Figure64.
Interpolation/ModulationCombinationof1fDAC/8FilterAD9776/AD9778/AD9779Rev.
A|Page33of5610–100–44–3–2–101230–10–20–30–40–50–60–70–80–90fOUT(*InputDataRate)ATTENUATION(dB)05361-062Figure65.
Interpolation/ModulationCombinationoffDAC/8Filter10–100–44–3–2–101230–10–20–30–40–50–60–70–80–90fOUT(*InputDataRate)ATTENUATION(dB)05361-063Figure66.
Interpolation/ModulationCombinationof2fDAC/8FilterinShiftedMode10–100–44–3–2–101230–10–20–30–40–50–60–70–80–90fOUT(*InputDataRate)ATTENUATION(dB)05361-064Figure67.
Interpolation/ModulationCombinationof3fDAC/8FilterinShiftedModeShiftedmodefilterresponsesallowthepassbandtobecenteredaround±0.
5fDATA,±1.
5fDATA,±2.
5fDATA,and±3.
5fDATA.
Switchingtotheshiftedmoderesponsedoesnotmodulatethesignal.
Instead,thepassbandissimplyshifted.
Forexample,picturetheresponseshowninFigure67andassumethesignalin-bandisacomplexsignaloverthebandwidth3.
2fDATAto3.
3fDATA.
Iftheevenmodefilterresponseisthenselected,thepassbandbecomescenteredat3.
5fDATA.
However,thesignalremainsatthesameplaceinthespectrum.
TheshiftedmodecapabilityallowsthefilterpassbandtobeplacedanywhereintheDACNyquistbandwidth.
TheAD9776/AD9778/AD9779aredualDACswithinternalcomplexmodulatorsbuiltintotheinterpolatingfilterresponse.
Indualchannelmode,thedevicesexpecttherealandtheimaginarycomponentsofacomplexsignalatDigitalInputPort1andDigitalInputPort2(IandQ,respectively).
TheDACoutputsthenrepresenttherealandimaginarycomponentsoftheinputsignal,modulatedbythecomplexcarrierfDAC/2,fDAC/4,orfDAC/8.
WithRegister2,Bit6set,thedeviceacceptsinterleaveddataonPort1intheI,Q,I,Q.
.
.
sequence.
Notethatininterleavedmode,thechanneldatarateatthebeginningoftheIandtheQdatapathsarenowhalftheinputdataratebecauseoftheinter-leaving.
Themaximuminputdatarateisstillsubjecttothemaximumspecificationofthedevice.
Thislimitsthesynthesisbandwidthavailableattheinputininterleavedmode.
WithRegister0x02,Bit5(realmode)set,theQchannelandtheinternalIandQdigitalmodulationareturnedoff.
TheoutputspectrumattheIDACthenrepresentsthesignalatDigitalInputPort1,interpolatedby1*,2*,4*,or8*.
Thegeneralrecommendationisthatifthedesiredsignaliswithin±0.
4*fDATA,theoddfiltermodeshouldbeused.
Outsideofthis,theevenfiltermodeshouldbeused.
Inanysituation,thetotalbandwidthofthesignalshouldbelessthan0.
8*fDATA.
AD9776/AD9778/AD9779Rev.
A|Page34of56Table17.
InterpolationFilterModes,(Register0x01,Bits)InterpolationFactorFilterModeModulationNyquistZonePassBandF_Low1Center1F_High1Comments80x00DC10.
050+0.
0580x01DCshifted20.
01250.
06250.
112580x02F/830.
0750.
1250.
17580x03F/8shifted40.
13750.
18750.
237580x04F/450.
20.
250.
380x05F/4shifted60.
26250.
31250.
362580x063F/870.
3250.
3750.
42580x073F/8shifted80.
38750.
43750.
487580x08F/280.
550.
50.
4580x09F/2shifted70.
48750.
43750.
387580x0A3F/860.
4250.
3750.
34380x0B3F/8shifted50.
36250.
31250.
262580x0CF/440.
30.
250.
280x0DF/4shifted30.
23750.
18750.
137580x0EF/820.
1750.
1250.
07580x0FF/8shifted10.
11250.
06250.
0125In8*interpolation;BW(min)=0.
0375*fDACBW(max)=0.
1*fDAC40x00DC10.
10+0.
140x01DCshifted20.
0250.
1250.
22540x02F/430.
150.
250.
3540x03F/4shifted40.
2750.
3750.
47540x04F/240.
60.
50.
440x05F/2shifted30.
4750.
3750.
27540x06F/420.
350.
250.
1540x07F/4shifted10.
2250.
1250.
025In4*interpolation;BW(min)=0.
075*fDACBW(max)=0.
2*fDAC20x00DC10.
20+0.
220x01DCshifted20.
050.
250.
4520x02F/220.
70.
50.
320x03F/2shifted10.
450.
250.
05In2*interpolation;BW(min)=0.
15*fDACBW(max)=0.
4*fDAC1FrequencynormalizedtofDAC.
AD9776/AD9778/AD9779Rev.
A|Page35of56INTERPOLATIONFILTERMINIMUMANDMAXIMUMBANDWIDTHSPECIFICATIONSTheAD977xusesanovelinterpolationfilterarchitecturethatallowsDACIFfrequenciestobegeneratedanywhereinthespectrum.
Figure68showsthetraditionalchoiceofDACIFoutputbandwidthplacement.
Notethattherearenopossiblefiltermodesinwhichthecarriercanbeplacednear0.
5*fDATA,1.
5*fDATA,2.
5*fDATA,andsoon.
10–80–44fOUT(*InputDataRate),ASSUMING8*INTERPOLATIONATTENUATION(dB)0–10–20–30–40–50–60–70–3–2–10123+fDAC/2+fDAC/4+fDAC/8BASEBAND–fDAC/8–fDAC/4–fDAC/205361-065Figure68.
TraditionalBandwidthOptionsforTxDACOutputIFThefilterarchitecturenotonlyallowstheinterpolationfilterpassbandstobecenteredinthemiddleoftheinputNyquistzones(asexplainedinthissection),butalsoallowsthepossi-bilityofa3*fDAC/8modulationmode.
Withallofthesefiltercombinations,acarrierofgivenbandwidthcanbeplacedanywhereinthespectrumandfallintoapossiblepassbandoftheinterpolationfilters.
ThepossiblebandwidthsaccessiblewiththefilterarchitectureareshowninFigure69andFigure70.
Notethattheshiftedandnonshiftedfiltermodesareallaccessiblebyprogrammingthefiltermodefortheparticularinterpolationrate.
10–80–44fOUT(*InputDataRate),ASSUMING8*INTERPOLATIONATTENUATION(dB)0–10–20–30–40–50–60–70–3–2–10123–fDAC/2–3*fDAC/8–fDAC/4–fDAC/8BASEBAND+fDAC/8+fDAC/4+3*fDAC/8+fDAC/205361-066Figure69.
NonshiftedBandwidthsAccessiblewiththeFilterArchitecture10–80–44fOUT(*InputDataRate),ASSUMING8*INTERPOLATIONATTENUATION(dB)0–10–20–30–40–50–60–70–3–2–10123SHIFTED–3*fDAC/8SHIFTED–fDAC/4SHIFTED–fDAC/8SHIFTED–DCSHIFTED–DCSHIFTED–fDAC/8SHIFTED–fDAC/4SHIFTED–3*fDAC/805361-067Figure70.
ShiftedBandwidthsAccessiblewiththeFilterArchitectureWiththisfilterarchitecture,asignalplacedanywhereinthespectrumispossible.
However,thesignalbandwidthislimitedbytheinputsamplerateoftheDACandthespecificplacementofthecarrierinthespectrum.
Thebandwidthrestrictionresultingfromthecombinationoffilterresponseandinputsamplerateisoftenreferredtoasthesynthesisbandwidth,sincethisisthelargestbandwidththattheDACcansynthesize.
Themaximumbandwidthconditionexistsifthecarrierisplaceddirectlyinthecenterofoneofthefilterpassbands.
Inthiscase,thetotal0.
1dBbandwidthoftheinterpolationfiltersisequalto0.
8*fDATA.
AsTable17shows,thesynthesisband-widthasafractionofDACoutputsampleratedropsbyafactorof2foreverydoublingofinterpolationrate.
Theminimumbandwidthconditionexists,forexample,ifacarrierisplacedat0.
25*fDATA.
Inthissituation,ifthenonshiftedfilterresponseisenabled,thehighendofthefilterresponsecutsoffat0.
4*fDATA,thuslimitingthehighendofthesignalbandwidth.
Iftheshiftedfilterresponseisenabledinstead,thenthelowendofthefilterresponsecutsoffat0.
1*fDATA,thuslimitingthelowendofthesignalbandwidth.
Theminimumbandwidthspecificationthatappliesforacarrierat0.
25*fDATAistherefore0.
3*fDATA.
Theminimumbandwidthbehaviorisrepeatedoverthespectrumforcarriersplacedat(±n±0.
25)*fDATA,wherenisanyinteger.
DRIVINGTHEREFCLKINPUTTheREFCLKinputrequiresalowjitterdifferentialdrivesignal.
ItisaPMOSinputdifferentialpairpoweredfromthe1.
8Vsupply,therefore,itisimportanttomaintainthespecified400mVinputcommon-modevoltage.
Eachinputpincansafelyswingfrom200mVp-pto1Vp-paboutthe400mVcommon-modevoltage.
WhiletheseinputlevelsarenotdirectlyLVDS-compatible,REFCLKcanbedrivenbyanoffsetac-coupledLVDSsignal,asshowninFigure71.
AD9776/AD9778/AD9779Rev.
A|Page36of56LVDS_P_INCLK+50Ω50Ω0.
1μF0.
1μFLVDS_N_INCLK–VCM=400mV05361-068Figure71.
LVDSREFCLKDriveCircuitIfacleansineclockisavailable,itcanbetransformer-coupledtoREFCLK,asshowninFigure71.
UseofaCMOSorTTLclockisalsoacceptableforlowersamplerates.
ItcanberoutedthroughaCMOStoLVDStranslator,thenac-coupled,asdescribedinthissection.
Alternatively,itcanbetransformer-coupledandclamped,asshowninFigure72.
50Ω50ΩTTLORCMOSCLKINPUTCLK+CLK–VCM=400mVBAV99ZXCTHIGHSPEEDDUALDIODE0.
1μF05361-069Figure72.
TTLorCMOSREFCLKDriveCircuitAsimplebiasnetworkforgeneratingVCMisshowninFigure73.
ItisimportanttouseCVDD18andCGNDfortheclockbiascircuit.
AnynoiseorothersignalthatiscoupledontotheclockismultipliedbytheDACdigitalinputsignalandcandegradeDACperformance.
0.
1μF1nF1nFVCM=400mVCVDD18CGND1kΩ287Ω05361-070Figure73.
REFCLKVCMGeneratorCircuitINTERNALPLLCLOCKMULTIPLIER/CLOCKDISTRIBUTIONTheinternalclockstructureonthedevicesallowstheusertodrivethedifferentialclockinputswithaclockat1*oranintegermultipleoftheinputdatarateorattheDACoutputsamplerate.
AninternalPLLprovidesinputclockmultiplicationandprovidesalltheinternalclocksrequiredfortheinterpolationfiltersanddatasynchronization.
TheinternalclockarchitectureisshowninFigure74.
ThereferenceclockisthedifferentialclockatPin5andPin6.
Thisclockinputcanberundifferentiallyorsingled-endedbydrivingPin5withaclocksignalandbiasingPin6tothemidswingpointofthesignalatPin5.
Theclockarchitecturecanberuninthefollowingconfigurations:PLLEnabled(Register0x09,Bit7=1)ThePLLenableswitchshowninFigure74isconnectedtothejunctionoftheN1dividers(PLLVCOdivideratio)andN2dividers(PLLloopdivideratio).
DividerN3determinestheinterpolationrateoftheDAC,andtheratioN3/N2determinestheratioofreferenceclock/inputdatarate.
TheVCOrunsoptimallyovertherangeof1.
0GHzto2.
0GHz,sothatN1keepsthespeedoftheVCOwithinthisrange,althoughtheDACsampleratecanbelower.
Theloopfiltercomponentsareentirelyinternalandnoexternalcompensationisnecessary.
PLLDisabled(Register0x09,Bit7=0)ThePLLenableswitchshowninFigure74isconnectedtothereferenceclockinput.
ThedifferentialreferenceclockinputisthesameastheDACoutputsamplerate.
N3determinestheinterpolationrate.
ADCPHASEDETECTIONVCODACINTERPOLATIONRATEINTERNALLOOPFILTER0x0A(4:0)LOOPFILTERBANDWIDTHREFERENCECLOCK(PINS5AND6)0x0A(7:5)PLLCONTROLVOLTAGERANGE0x08(7:2)VCORANGE0x09(7)PLLENABLEINTERNALDACSAMPLERATECLOCKDATACLKOUT(PIN37)0x01(7:6)0x09(6:5)PLLVCODIVIDERATIO0x09(4:3)PLLLOOPDIVIDERATIO÷N3÷N2÷N105361-071Figure74.
InternalClockArchitectureAD9776/AD9778/AD9779Rev.
A|Page37of56Table18.
VCOFrequencyRangevs.
PLLBandSelectValueTypicalPLLLockRangesVCOFrequencyRangeinMHzTypat25°CTypoverTempPLLBandSelectfLOWfHIGHfLOWfHIGH111111(63)AutomodeAutomode111110(62)2056217021052138111101(61)2002211320482081111100(60)1982209320292061111011(59)196420752010204311101058)1947205719922026111001(57)1927203719712006111000(56)1907201619511986110111(55)1894200319361972110110(54)1872198119131952110101(53)1852196018921931110100(52)1841194818811920110011(51)1816192318551895110010(50)1796190318351874110001(49)1789189518281867110000(48)1764187118031844101111(47)1746185317841826101110(46)1738184217761815101101(45)1714182017521794101100(44)1700180417371779101011(43)1689179017261764101010(42)1657175716951734101001(41)1641173816791714101000(40)1610170716491684100111(39)1597168916351666100110(38)1568166116071639100101(37)1553164115921617100100(36)1525161315621592100011(35)1511159515481572100010(34)1484157015191549100001(33)1470155215061528100000(32)1441152514741504011111(31)1429150914631487011110(30)1403148514331464011101(29)1390146914221447011100(28)1362144313911423011011(27)1352142913801407011010(26)1325140513521385011001(25)1314139013401369011000(24)1290136813151350010111(23)1276135113021332010110(22)1253133112771313010101(21)1239131312641295010100(20)1183125512051240010011(19)1204127512271259010010(18)1151122111721207010001(17)1171124011931224010000(16)1148121811701204001111(15)1137120411591189TypicalPLLLockRangesVCOFrequencyRangeinMHzTypat25°CTypoverTempPLLBandSelectfLOWfHIGHfLOWfHIGH001110(14)1116118411371170001101(13)1106117111271157001100(12)1086115211061138001011(11)1075113810951124001010(10)1055111910751106001001(9)1045110710651093001000(8)1027109010471076000111(7)1016107610341062000110(6)998105910161046000101(5)987104610051032000100(4)96010179771004000011(3)933989949976000010(2)908962923950000001(1)883936898925000000(0)859911873899VCOFrequencyRangesBecausethePLLbandcoversgreaterthana2*frequencyrange,therecanbetwooptionsforthePLLbandselect:oneatthelowendoftherangeandoneatthehighendoftherange.
Undertheseconditions,theVCOphasenoiseisoptimalwhentheuserselectsthebandselectvaluecorrespondingtothehighendofthefrequencyrange.
Figure75showshowtheVCObandwidthandtheoptimalVCOfrequencyvarieswiththebandselectvalue.
VCOFrequencyRangesoverTemperatureThespecificationsgivenovertemperatureinTable18areforasinglepartinasinglelot.
Part-to-part,andlot-to-lot,thesespecificationscanexhibitameanshiftofseveralregistersettings.
SystemsshouldbedesignedtotakethispotentialshiftintoaccounttomaintainoptimalPLLperformance.
PLLLoopFilterBandwidthTheloopfilterbandwidthofthePLLisprogrammedviaSPIRegister0x0A,Bits.
Changingthesevaluesswitchescapacitorsontheinternalloopfilter.
Noexternalloopfiltercomponentsarerequired.
Thisloopfilterhasapoleat0(P1),andthenazero(Z1)pole(P2)combination.
Z1andP2occurwithinadecadeofeachother.
ThelocationofthezeropoleisdeterminedbyBits.
Forasettingof00000,thezeropoleoccursnear10MHz.
BysettingBitsto11111,theZ1/P2combinationcanbeloweredtoapproximately1MHz.
TherelationshipbetweenBitsandthepositionofthezeropolebetween1MHzand10MHzislinear.
Theinternalcomponentsarenotlowtolerance,however,andcandriftbyasmuchas±30%.
Foroptimalperformance,thebandwidthadjustment(Register0x0A,Bits)shouldbesetto11111foralloperatingmodeswithPLLenabled.
ThePLLbiassettingsAD9776/AD9778/AD9779Rev.
A|Page38of56(Register0x09,Bits)shouldbesetto111.
ThePLLcontrolvoltage(Register0x0A,Bits)isreadbackandispropor-tionaltothedcvoltageattheinternalloopfilteroutput.
WiththePLLbiassettingsgiveninthissection,thereadbackfromthePLLcontrolvoltageshouldtypicallybe010,orpossibly001or011.
AnythingoutsideofthisrangeindicatesthatthePLLisnotoperatingcorrectly.
04812162024283236404448525660850215020501950185017501650145015501350125011501050950FVCO(MHz)PLLBAND05361-072Figure75.
TypicalPLLBandSelectvs.
Frequencyat25°C04812162024283236404448525660850215020501950185017501650145015501350125011501050950FVCO(MHz)PLLBAND05361-113Figure76.
TypicalPLLBandSelectvs.
FrequencyoverTemperatureTheAD977xhasanautosearchfeaturethatdeterminestheoptimalsettingsforthePLL.
Toenabletheautosearchmode,setRegister0x08,Bitsto11111b,andreadbackthevaluefromRegister0x08,Bits.
AutosearchmodeisintendedtofindtheoptimalPLLsettingsonly,afterwhichthesamesettingsshouldbeappliedinmanualmode.
ItisnotrecommendedthatthePLLbesettoautosearchmodeduringregularoperation.
FULL-SCALECURRENTGENERATIONInternalReferenceFull-scalecurrentontheIDACandQDACcanbesetfrom8.
66mAto31.
66mA.
Initially,the1.
2VbandgapreferenceisusedtosetupacurrentinanexternalresistorconnectedtoI120(Pin75).
AsimplifiedblockdiagramofthereferencecircuitryisshowninFigure77.
Therecommendedvaluefortheexternalresistoris10kΩ,whichsetsupanIREFERENCEintheresistorof120μA,whichinturnprovidesaDACoutputfull-scalecurrentof20mA.
Becausethegainerrorisalinearfunctionofthisresistor,ahighprecisionresistorimprovesgainmatchingtotheinternalmatchingspecificationofthedevices.
Internalcurrentmirrorsprovideacurrent-gainscaling,whereIDACorQDACgainisa10-bitwordintheSPIportregister(Register0x0A,Register0x0B,Register0x0E,andRegister0x0F).
ThedefaultvaluefortheDACgainregistersgivesanIFSofapproximately20mA,whereIFSisequalto32102461227V2.
1**+*gainDACRIDACDACFULL-SCALEREFERENCECURRENTCURRENTSCALINGIDACGAINQDACGAINQDACAD9779VREF10kΩ1.
2VBANDGAP0.
1μFI12005361-073Figure77.
ReferenceCircuitry35001000DACGAINCODEIFS(mA)3025201510520040060080005361-074Figure78.
IFSvs.
DACGainCodeApplicationofAuxiliaryDACsinSingleSidebandTransmitterTwoauxiliaryDACsareprovidedontheAD977x.
Thefull-scaleoutputcurrentontheseDACsisderivedfromthe1.
2Vbandgapreferenceandexternalresistor.
Thegainscalefromtheref-erenceamplifiercurrentIREFERENCEtotheauxiliaryDACreferencecurrentis16.
67withtheauxiliaryDACgainsettofullscale(10-bitvalues,SPIRegister0x0DandSPIRegister0x11),thisgivesafull-scalecurrentofapproximately2mAforauxiliaryDAC1andauxiliaryDAC2.
TheauxiliaryDACoutputsarenotdifferential.
OnlyonesideoftheauxiliaryDAC(PorN)isactiveatonetime.
Theinactivesidegoesintoahighimpedancestate(>100kΩ).
Inaddition,thePorNoutputscanactascurrentsourcesorsinks.
ThecontrolofthePandNsideforbothauxiliaryDACsisviaRegister0x0EandRegister0x10,Bits.
Whensourcingcurrent,theoutputcomplianceAD9776/AD9778/AD9779Rev.
A|Page39of56voltageis0Vto1.
6V.
Whensinkingcurrent,theoutputcompliancevoltageis0.
8Vto1.
6V.
TheauxiliaryDACscanbeusedforlocaloscillator(LO)cancella-tionwhentheDACoutputisfollowedbyaquadraturemodulator.
ThisLOfeedthroughiscausedbytheinputreferreddcoffsetvoltageofthequadraturemodulator(andtheDACoutputoffsetvoltagemismatch)andcandegradesystemperformance.
TypicalDAC-to-quadraturemodulatorinterfacesareshowninFigure79andFigure80.
Often,theinputcommon-modevoltageforthemodulatorismuchhigherthantheoutputcompliancerangeoftheDAC,sothataccouplingoradclevelshiftisnecessary.
Iftherequiredcommon-modeinputvoltageonthequadraturemodulatormatchesthatoftheDAC,thenthedcblockingcapacitorsinFigure79canberemoved.
Alow-passorband-passpassivefilterisrecommendedwhenspurioussignalsfromtheDAC(distortionandDACimages)atthequadraturemodulatorinputscanaffectthesystemperformance.
PlacingthefilteratthelocationshowninFigure79andFigure80allowseasydesignofthefilter,asthesourceandloadimpedancescaneasilybedesignedcloseto50Ω.
05361-115AD9779QDACAD9779AUXDAC225ΩTO50Ω0.
1μF0.
1μFOPTIONALPASSIVEFILTERINGQUADRATUREMODULATORV+QUADMODQINPUTSAD9779IDACAD9779AUXDAC125ΩTO50Ω0.
1μF0.
1μFOPTIONALPASSIVEFILTERINGQUADRATUREMODULATORV+QUADMODIINPUTSFigure79.
TypicalUseofAuxiliaryDACsACCouplingtoQuadratureModulator05361-116AD9779IORQDACAD9779AUXDAC1OR225ΩTO50Ω25ΩTO50ΩOPTIONALPASSIVEFILTERINGQUADRATUREMODULATORV+QUADMODIORQINPUTSFigure80.
TypicalUseofAuxiliaryDACsDCCouplingtoQuadratureModulatorwithDCShiftPOWERDISSIPATIONFigure81toFigure89showthepowerdissipationofthe1.
8Vand3.
3VdigitalandclocksuppliesinsingleDACanddualDACmodes.
Inadditiontothis,thepowerdissipation/currentofthe3.
3Vsupply(modeandspeedindependent)insingleDACmodeis102mW/31mA.
IndualDACmode,thisis182mW/55mA.
Furthermore,whenthePLLisenabled,itadds90mW/50mAtothe1.
8VclocksupplyregardlessofthemodeoftheAD9779.
00250fDATA(MSPS)POWER(W)0.
60.
70.
50.
40.
30.
20.
12550751001251501752002258*INTERPOLATION,ZEROSTUFFING8*INTERPOLATION4*INTERPOLATION4*INTERPOLATION,ZEROSTUFFING2*INTERPOLATION1*INTERPOLATION2*INTERPOLATION,ZEROSTUFFING1*INTERPOLATION,ZEROSTUFFING05361-076Figure81.
TotalPowerDissipation,IDataOnly,RealMode00250fDATA(MSPS)POWER(W)0.
42550751001251501752002258*INTERPOLATION4*INTERPOLATION2*INTERPOLATION1*INTERPOLATION0.
30.
20.
105361-078Figure82.
PowerDissipation,Digital1.
8VSupply,IDataOnly,RealMode,DoesNotIncludeZeroStuffing00250fDATA(MSPS)POWER(W)0.
082550751001251501752002258*INTERPOLATION4*INTERPOLATION2*INTERPOLATION1*INTERPOLATION0.
060.
040.
0205361-079Figure83.
PowerDissipation,Clock1.
8VSupply,IDataOnly,RealMode,IncludesModulationModes,DoesNotIncludeZeroStuffingAD9776/AD9778/AD9779Rev.
A|Page40of5600250fDATA(MSPS)POWER(W)0.
0752550751001251501752002250.
0500.
025ALLINTERPOLATIONMODES05361-080Figure84.
Digital3.
3VSupply,IDataOnly,RealMode,IncludesModulationModesandZeroStuffing00300250275fDATA(MSPS)POWER(W)0.
61.
00.
70.
80.
90.
50.
40.
30.
20.
125507510012515017520022505361-0771*INTERPOLATION1*INTERPOLATION,ZEROSTUFFING2*INTERPOLATION,ALLMODULATIONMODES2*INTERPOLATION,ZEROSTUFFING4*INTERPOLATION,ALLMODULATIONMODES4*INTERPOLATION,ZEROSTUFFING8*INTERPOLATION,ALLMODULATIONMODES8*INTERPOLATION,ZEROSTUFFINGFigure85.
TotalPowerDissipation,DualDACMode00250fDATA(MSPS)POWER(W)0.
80.
70.
60.
50.
40.
30.
20.
12550751001251501752002252*INTERPOLATION4*INTERPOLATION1*INTERPOLATION,NOMODULATION8*INTERPOLATION,fDAC/8,fDAC/4,fDAC/2,NOMODULATION05361-081Figure86.
PowerDissipation,Digital1.
8VSupply,IandQData,DualDACMode,DoesNotIncludeZeroStuffing00250fDATA(MSPS)POWER(W)0.
1252550751001251501752002252*INTERPOLATION4*INTERPOLATION1*INTERPOLATION,NOMODULATION8*INTERPOLATION,fDAC/8,fDAC/4,fDAC/2,NOMODULATION0.
1000.
0750.
0500.
02505361-082Figure87.
PowerDissipation,Clock1.
8VSupply,IandQData,DualDACMode,DoesNotIncludeZeroStuffing00250fDATA(MSPS)POWER(W)0.
0752550751001251501752002250.
0500.
025ALLINTERPOLATIONMODES05361-083Figure88.
Digital3.
3VSupply,IandQData,DualDACMode0.
16001200fDAC(MSPS)POWER(W)0.
140.
120.
100.
080.
060.
040.
02200400600800100005361-084Figure89.
PowerDissipationofInverseSincFilterAD9776/AD9778/AD9779Rev.
A|Page41of56POWER-DOWNANDSLEEPMODESINTERLEAVEDDATAMODETheAD977xhasavarietyofpower-downmodes,sothatthedigitalengine,mainTxDACs,orauxiliaryDACscanbepowereddownindividuallyortogether.
ViatheSPIport,themainTxDACscanbeplacedinsleeporpower-downmode.
Insleepmode,theTxDACoutputisturnedoff,thusreducingpowerdissipation.
Thereferenceremainspoweredon,however,sothatrecoveryfromsleepmodeisveryfast.
Withthepower-downmodebitset(Register0x00,Bit4),allanaloganddigitalcircuitry,includingthereference,ispowereddown.
TheSPIportremainsactiveinthismode.
Thismodeoffersmoresubstantialpowersavingsthansleepmode,buttheturn-ontimeismuchlonger.
TheauxiliaryDACsalsohavethecapabilitytobeprogrammedintosleepmodeviatheSPIport.
Theautopower-downenablebit(Register0x00,Bit3)controlsthepower-downfunctionforthedigitalsectionofthedevices.
Theautopower-downfunctionworksinconjunctionwiththeTXENABLEpin(Pin39)accordingtothefollowing:TheTxEnablebitisdualfunction.
Indualportmode,itissimplyusedtopowerdownthedigitalsectionofthedevices.
Ininterleavedmode,theIQdatastreamissynchronizedtoTXENABLE.
Therefore,toachieveIQsynchronization,TXENABLEshouldbeheldlowuntilanIdatawordispresentattheinputstoDataPort1.
IfaDATACLKrisingedgeoccurswhileTXENABLEisatahighlogiclevel,IQdatabecomessynchronizedtotheDATACLKoutput.
TXENABLEcanremainhighandtheinputIQdataremainssynchronized.
Tobebackwards-compatiblewithpreviousDACsfromAnalogDevices,Inc.
suchastheAD9777andAD9786,theusercanalsotoggleTXENABLEonceduringeachdatainputcycle,thuscontinuallyupdatingthesynchronization.
IfTXENABLEisbroughtlowandheldlowformultipleREFCLKcycles,thenthedevicesflushthedataintheinterpolationfilters,andshutdownthedigitalengineafterthefiltersareflushed.
TheamountofREFCLKcyclesittakestogointothispower-downmodeisthenafunctionofthelengthoftheequivalent2*,4*,or8*interpolationfilter.
ThetimingofTXENABLE,I/Qselect,filterflush,anddigitalpower-downareshowninFigure91.
TXENABLE(Pin39)=0:autopower-downenable=0:flushdatapathwith0s1:flushdataformultipleREFCLKcycles;thenautomaticallyplacethedigitalengineinpower-downstate.
DACs,reference,andSPIportarenotaffected.
INTERLEAVEDINPUTDATATxENABLECANREMAINHIGHORTOGGLEFORI/QSYNCHRONIZATIONI1Q1I2Q2TxENABLEFLUSHINGINTERPOLATIONFILTERSPOWERDOWNDIGITALSECTION05361-085orTXENABLE(Pin39)=1:normaloperationAsshowninFigure90,thepowerdissipationsavedbyusingthepowerdownmodeisnearlyproportionaltothedutycycleofthesignalattheTXENABLEpin.
Figure91.
TXENABLEFunctionTheTXENABLEfunctioncanbeinvertedbychangingthestatusofRegister0x02,Bit1.
TheotherbitthatcontrolsIQorderingistheQ-firstbit(Register0x02,Bit0).
WiththeQ-firstbitresettothedefaultof0,theIQpairingthatislatchedistheI1Q1,I2Q2,andsoon.
WithIQfirstsetto1,thefirstIdataisdiscardedandthepairingisI2Q1,I3Q2,andsoon.
NotethatwithIQ-firstset,theIdataisstillroutedtotheinternalIchannel,theQdataisroutedtotheinternalQchannel,andonlythepairingchanges.
0.
90.
80.
70.
60.
50.
40.
30.
20.
10010080604020DUTYCYCLE(%)POWERSAVINGS05361-1192*INTfDATA=50MSPS8*INTfDATA=50MSPS2*INTfDATA=200MSPS4*INTfDATA=50MSPS4*INTfDATA=200MSPS8*INTfDATA=200MSPSTIMINGINFORMATIONFigure92toFigure95showsomeofthevarioustimingpossibilitieswhenthePLLisenabled.
ThecombinationofthesettingsofN2andN3fromFigure74meansthatthereferenceclockfrequencycanbeamultipleoftheactualinputdatarate.
Figure92toFigure95show,respectively,whatthetiminglookslikewhenN2/N3=1and2.
Figure90.
PowerSavingsBasedonDutyCycleofTxEnableIftheTxEnableinvertbit(Register0x02,Bit1)isset,thefunctionofthisTXENABLEpinisinverted.
Ininterleavedmode,set-upandholdtimesofDATACLKouttodatainarethesameasthoseshowninFigure92toFigure95.
ItisrecommendedthatanytogglingofTXENABLEoccurconcurrentlywiththedigitaldatainputupdating.
Inthisway,timingmarginsbetweenDATACLK,TXENABLE,anddigitalinputdataareoptimized.
AD9776/AD9778/AD9779Rev.
A|Page42of5605361-120REFERENCECLOCKINDATACLOCKOUTINPUTDATAtSREFCLKtHREFCLKtSDATACLKtHDATACLKFigure92.
TimingSpecifications,PLLEnabledorDisabled,Interpolation=1*REFERENCECLOCKINDATACLOCKOUTSYNC_INtS_SYNCtH_SYNC05361-121INPUTDATAtSREFCLKtHREFCLKtSDATACLKtHDATACLKFigure93.
TimingSpecifications,PLLEnabledorDisabled,Interpolation=2*05361-122REFERENCECLOCKINDATACLOCKOUTINPUTDATAtSREFCLKtHREFCLKtSDATACLKtHDATACLKtS_SYNCtH_SYNCSYNC_INFigure94.
TimingSpecifications,PLLEnabledorDisabled,Interpolation=4*REFERENCECLOCKINDATACLOCKOUT05361-123INPUTDATAtSREFCLKtHREFCLKtSDATACLKtHDATACLKSYNC_INtS_SYNCtH_SYNCFigure95.
TimingSpecifications,PLLEnabledorDisabled,Interpolation=8*AD9776/AD9778/AD9779Rev.
A|Page43of56SpecificationsaregiveninTable19forthedriftofinputdatasetupandholdtimevs.
temperature,aswellasthedatakeepoutwindow(KOW).
Notethatalthoughthesespecificationsdodrift,thelengthofthekeepoutwindow,whereinputdataisinvalid,changesverylittleovertemperature.
Table19.
AD9779TimingSpecificationsvs.
TemperatureTimingParameterTemperatureMintS(ns)MintH(ns)MaxKOW(ns)REFCLKtoDATA40°C0.
8+2.
2+1.
3+25°C1.
1+2.
5+1.
4+85°C1.
3+2.
9+1.
5DATACLKtoDATA40°C+1.
80.
4+1.
3+25°C+2.
10.
7+1.
4+85°C+2.
50.
9+1.
5SYNC_ItoREFCLK40°Cto+85°C0.
2+1.
0+0.
8SYNCHRONIZATIONOFINPUTDATATODATACLKOUTPUT(PIN37)SynchronizingtheinputdatabustotheDATACLKoutsignalisachievedbymeetingthetimingrelationshipsbetweenDATACLKandDATAtimingspecifiedinTable19.
Iftheuserissynchro-nizingtheinputdatatotheDATACLKout,thesyncinput(SYNC_I)signaldoesnotneedtobeappliedandcanbeignored(connecttoGND).
SYNCHRONIZATIONOFINPUTDATATOTHEREFCLKINPUT(PIN5ANDPIN6)WITHPLLENABLEDORDISABLEDSynchronizingtheinputdatabustotheREFCLKinputrequirestheuseoftheSYNC_Iinputpins(Pin13andPin14).
IftheSYNC_Iinputisnotused,thereisaphaseambiguitybetweentheDATACLKoutandtheREFCLKin.
ThisambiguitymatchestheinterpolationrateinwhichtheAD9779,forexample,iscurrentlyoperating.
BecauseinputdataislatchedontherisingedgeofDATACLK,itisimpossiblefortheusertodetermineontowhichoneofthemultipleinternalDACCLKedges(asanexample,oneoffouredgesin4*interpolation)theinputdataactuallylatches.
FortheusertospecificallydeterminetheexactedgeofREFCLKonwhichthedataisbeinglatched,arisingedgemustbeperiodicallyappliedtoSYNC_I.
ThefrequencyoftheSYNC_IsignalmustbeequaltofDAC/2N,Nbeinganinteger,andmustbenogreaterthanDATACLKforpropersynchronization.
ThereisnolimitonhowslowtheSYNC_Isignalcanbedriven.
AslongasthesetupandholdtimingrelationshipbetweenSYNC_IandREFCLKgiveninTable19ismet,theinputdataislatchedontheimmediatenextrisingedgeofREFCLK.
NotethatarisingedgeofDATACLKoutoccursconcurrentlywiththenextREFCLKrisingedge,afterashortpropagationdelay.
Althoughthispropagationdelayisnotspecified,inputdatasetupandholdtiminginformationisgivenwithrespecttoREFCLKinandDATACLKoutinFigure92toFigure95.
Also,notethatin1*interpolation,becausethereisnophaseambiguity,thereisnoneedtousetheSYNC_Isignal.
ValidTimingWindowInadditiontothetimingrequirementsofSYNC_IwithrespecttoREFCLK,itisimportanttounderstandthatthevalidtimingwindowforSYNC_IislimitedbytheinternalDACsamplerate.
ThisisshowninFigure96.
WhenthetSandtHrequirementsaremet,thevalidtimingwindowforSYNC_IextendsonlyasfarasoneperiodoftheinternalDACsamplerate(minustSandtH).
FailuretomeetthistimingspecificationcanpotentiallyresultinerroneousdatabeinglatchedintotheAD9779digitalinputs.
Asanexample,iftheAD9779inputdatarateis122.
88MSPSandtheREFCLKisthesame,withtheAD9779in4*interpola-tion,theDACsamplerateis1/491.
52MHzorabout2ns.
WithatSof0.
2nsandtHof1.
0ns,thisgivesavalidtimingwindowforSYNC_Iof2ns0.
8ns=1.
2nsThetimingwindowofthedigitalinputdatatoREFCLKcanbemovedinincrementsofoneinternalREFCLKcyclebyusingtheREFCLKOFFSETregister(Register0x7,Bits).
BecauseSYNC_IcanberunatthesamefrequencyasREFCLKwhenthePLLisenabled,bestpracticesuggeststhatinthiscon-dition,REFCLKandSYNC_Ioriginatefromthesamesource.
Thislimitsthevariationintimebetweenthesetwosignalsandmakestheoveralltimingbudgeteasiertoachieve.
AslightdelaymaybenecessaryontheREFCLKpathinthisconfigurationtoaddmoretimingmarginbetweenREFCLKandSYNC_I(seeTable19fortimingrelationship).
05361-124REFCLKSYNC_ItStHtDAC_SAMPLEtDAC_SAMPLEFigure96.
ValidTimingRelationshipforSYNC_ItoREFCLKAD9776/AD9778/AD9779Rev.
A|Page44of56UsingDataDelaytoMeetTimingRequirementsTomeetstricttimingrequirementsatinputdataratesofupto250MSPS,theAD977xhasafinetimingfeature.
Finetimingadjustmentsaremadebyprogrammingvaluesintothedataclockdelayregister(Register0x04,Bits).
ThisregistercanbeusedtoadddelaybetweentheREFCLKinandtheDATACLKout.
Figure97showsthedefaultdelaypresentwhenDATACLKdelayisdisabled.
ThedisablefunctionbitisfoundinRegister0x02,Bit4.
Figure98showsthedelaypresentwhenDATACLKdelayisenabledandsetto0000.
Figure99indicatesthedelaywhenDATACLKdelayisenabledandsetto1111.
NotethatthesetupandholdtimesspecifiedfordatatoDATACLKaredefinedforDATACLKdelaydisabled.
CH11.
00VΩTEKRUN:5.
00GS/sSAMPLECH2500mVΩM2.
00nsCH1420mVΔ:4.
48nS@:40.
28nS2105361-089Figure97.
DelayfromREFCLKtoDATACLKwithDATACLKDelayDisabledCH11.
00VΩTEKRUN:5.
00GS/sSAMPLECH2500mVΩM2.
00nsCH1420mVΔ:4.
76nS@:35.
52nS2105361-090Figure98.
DelayfromREFCLKtoDATACLKOutwithDATACLKDelay=0000CH11.
00VΩTEKRUN:5.
00GS/sSAMPLECH2500mVΩM2.
00nsCH1420mVΔ:7.
84nS@:32.
44nS2105361-091Figure99.
DelayfromREFCLKtoDATACLKOutwithDATACLKDelay=1111ThedifferencebetweentheminimumdelayshowninFigure98andthemaximumdelayshowninFigure99istherangeprogrammableusingtheDATACLKdelayregister.
Thedelay(inabsolutetime)whenprogrammingDATACLKdelaybetween0000and1111isalinearextrapolationbetweenthesetwofigures.
ThetypicaldelaysperincrementovertemperatureareshowninTable20.
Table20.
DataDelayLineTypicalDelaysOverTemperatureDelays40°C+25°C+85°CUnitDelayBetweenDisabledandEnabled370416432psAverageDelayperIncrement171183197psThefrequencyofDATACLKoutdependsonseveralprogram-mablesettings:interpolation,zerostuffing,andinterleaved/dualportmode,allofwhichhaveaneffectontheREFCLKfrequency.
ThedivisorfunctionbetweenREFCLKandDATACLKisequaltothevaluesshowninTable21.
Table21.
REFCLKtoDATACLKDivisorRatioInterpolationZeroStuffingInputModeDivisor1DisabledDualport12DisabledDualport24DisabledDualport48DisabledDualport81DisabledInterleavedInvalid2DisabledInterleaved14DisabledInterleaved28DisabledInterleaved41EnabledDualport22EnabledDualport44EnabledDualport88EnabledDualport161EnabledInterleaved12EnabledInterleaved24EnabledInterleaved48EnabledInterleaved8AD9776/AD9778/AD9779Rev.
A|Page45of56Inadditiontothisdivisorfunction,DATACLKcanbedividedbyuptoanadditionalfactorof4,accordingtothestateoftheDATACLKdivideregister(Register0x03,Bits).
Formoredetails,seeTable22).
Table22.
ExtraDATACLKDivisorRatioRegister0x03,BitsDividerRatio001012104111ThemaximumdivisorresultingfromthecombinationofthevaluesinTable21,andtheDATACLKdivideregisteris32.
ManualInputTimingCorrectionCorrectionofinputtimingcanbeachievedmanually.
ThecorrectionfunctioniscontrolledbyRegister0x03,Bits.
ThefunctionisprogrammedasshowninTable23.
Table23.
InputTimingCorrectionModeRegister0x03,BitsFunction00Errorcheckdisabled01Reserved10Reserved11ReservedNecessarycorrectionscanbemadebyadjustingDATACLKdelayandtheDATACLKinvertbit(Register2,Bit2).
DATACLKdelaycanthenbeswepttofindtherangeoverwhichthetimingisvalid.
Thefinalvaluefordatadelayshouldbethevaluethatcorrespondstothemiddleofthevalidtimingrange.
Ifavalidtimingrangeisnotfoundduringthissweep,theusershouldinverttheDATACLKinvertbitandrepeattheprocess.
MultipleDACSynchronizationTheAD9779hasprogrammablefeaturesthatallowtheCMOSdigitaldatabusinputsandinternalfiltersonmultipledevicestobesynchronized.
ThismeansthattheDATACLKoutputsignalononeAD9779canbeusedtoregistertheoutputdataforadatabusdeliveringdatatomultipleAD9779s.
Thedetailsofthisopera-tionaregivenintheAnalogDevicesApplicationNoteAN-822.
AD9776/AD9778/AD9779Rev.
A|Page46of56EVALUATIONBOARDOPERATIONTheAD977xevaluationboardisdesignedtooptimizetheDACperformanceandthespeedofthedigitalinterface,yetremainsuserfriendly.
Tooperatetheboard,theuserneedsapowersource,aclocksource,andadigitaldatasource.
TheuseralsoneedsaspectrumanalyzeroranoscilloscopetolookattheDACoutput.
ThediagraminFigure100illustratesthetestsetup.
Asineorsquarewaveclockworkswellasaclocksource.
Thedcoffsetontheclockisnotaproblem,sincetheclockisac-coupledontheevaluationboardbeforetheREFCLKinputs.
AllnecessaryconnectionstotheevaluationboardareshowninmoredetailinFigure101.
TheevaluationboardcomeswithsoftwarethatallowstheusertoprogramtheSPIport.
ViatheSPIport,thedevicescanbeprogrammedintoanyofitsvariousoperatingmodes.
Whenfirstoperatingtheevaluationboard,itisusefultostartwithasimpleconfiguration,thatis,aconfigurationinwhichtheSPIportsettingsareascloseaspossibletothedefaultsettings.
ThedefaultsoftwarewindowisshowninFigure102.
Thearrowsindicatewhichsettingsneedtobechangedforaneasyfirsttimeevaluation.
NotethatthisimpliesthatthePLLisnotbeingusedandthattheclockbeingusedisatthespeedoftheDACoutputsamplerate.
ForamoredetaileddescriptionofhowtousethePLL,seethePLLLoopFilterBandwidthsection.
DIGITALPATTERNGENERATORADAPTERCABLESCLOCKGENERATORAD9779EVALUATIONBOARDCLKINSPIPORTDATACLKOUTCLOCKINSPECTRUMANALYZER1.
8VPOWERSUPPLY3.
3VPOWERSUPPLY05361-097Figure100.
TypicalTestSetupSPIPORTAD9779J1CLOCKINP4DigitalInputConnectorS7DCLKOUTAUX33DVDD18DVDD33CVDD18AVDD33J25VSupplyANALOGDEVICESAD9779/8/6REVDS5OUTPUT1S6OUTPUT2AD8349LOCALOSCINPUTMODULATOROUTPUT+5VGNDJP4JP15JP8JP14JP3JP16JP2JP1705361-098Figure101.
AD977xEvaluationBoardShowingAllConnectionsAD9776/AD9778/AD9779Rev.
A|Page47of561.
SETINTERPOLATIONRATE2.
SETINTERPOLATIONFILTERMODE3.
SETINPUTDATAFORMAT4.
SETDATACLKPOLARITYTOMATCHINPUTTIMING05361-099Figure102.
SPIPortSoftwareWindowThedefaultsettingsfortheevaluationboardallowtheusertoviewthedifferentialoutputsthroughatransformerthatconvertstheDACoutputsignaltoasingle-endedsignal.
Ontheevaluationboard,thesetransformersaredesignatedT1A,T2A,T3A,andT4A.
Therearealsofourcommon-modetransformersontheboardthataredesignatedT1B,T2B,T3B,andT4B.
Therecommendedoperatingsetupplacesthetransformerandcommon-modetransformerinseries.
Apairoftransformersandcommon-modetransformersareinstalledoneachDACoutput,sothatthepairscanbesetupineitherorder.
Asanexample,forthefrequencyrangeofdcto30MHz,itisrecommendedthatthetransformerbeplacedrightaftertheDAC.
AboveDACoutputfrequenciesof30MHz,itisrecommendedthatthecommon-modetransformerisplacedrightaftertheDACoutputs,followedbythetransformer.
AD9776/AD9778/AD9779Rev.
A|Page48of56MODIFYINGTHEEVALUATIONBOARDTOUSETHEAD8349ON-BOARDQUADRATUREMODULATORTheevaluationboardcontainsanAnalogDevicesAD8349quadraturemodulator.
TheAD977xandAD8349provideaneasy-to-interfaceDAC/modulatorcombinationthatcanbeeasilyevaluatedontheevaluationboard.
ToroutetheDACoutputsignaltothequadraturemodulator,thefollowingjumpersettingsmustbemade:Unsoldered:JP14,JP15,JP16,JP17Soldered:JP2,JP3,JP4,JP8TheDACoutputareaoftheevaluationboardisshowninFigure103.
ThejumpersthatneedtobechangedtousetheAD8349arecircled.
Alsocircledarethe5VandGNDconnectionsfortheAD8349.
05361-100Figure103.
PhotoofEvaluationBoard,DACOutputAreaAD9776/AD9778/AD9779Rev.
A|Page49of56EVALUATIONBOARDSCHEMATICSC690.
1μF+CVDD18TP2BLACKTP17REDTP1REDL1EXC-CL4532U1L6EXC-CL4532U1C680.
1μFC7722μF16VCVDD18_INC660.
1μF+VDDMDGND22TP14REDTP15BLACKL12EXC-CL4532U1L16EXC-CL4532U1C670.
1μFC4622μF16VVDDM_INDGND2TP13REDR519kΩR5210kΩR5510kΩC260.
1μF+AVDD33TP8BLACKTP19REDTP5REDL3EXC-CL4532U1L13EXC-CL4532U1C280.
1μFC2022μF16VAVDD33_INC490.
1μF+DPWR33TP10BLACKTP21REDTP7REDL5EXC-CL4532U1L15EXC-CL4532U1C480.
1μFC2222μF16VDPWR33_IN+C700.
1μFDVDD18TP4BLACKTP18REDTP3REDL2EXC-CL4532U1L7EXC-CL4532U1C710.
1μFC7622μF16VDVDD18_INC420.
1μF+DVDD33TP9BLACKTP20REDTP6REDL4EXC-CL4532U1L14EXC-CL4532U1C450.
1μFC2122μF16VDVDD33_IN3U6474AC1411U61074AC149U6874AC145U6674AC142U5CSBS1SWSECMAS3SWSECMAS2SWSECMA113274AC14SPI_CSBSPI_CLKSPI_SDISPI_SDO4U5374AC146U5574AC141U6274AC1412U51374AC1410U51174AC148U5974AC1413U61274AC14P1123456R539kΩR549kΩSDI132SCLK132S4SWSECMATP16REDTJAK06RAPCLASS=IOFCI-68898SDO13205361-101Figure104.
EvaluationBoard,Rev.
D,PowerSupplyDecouplingandSPIInterfaceAD9776/AD9778/AD9779Rev.
A|Page50of566AUX1_NAUX1_PAUX2_PCLK_NCLK_PDCLKI120IOUT1_NIOUT1_PIOUT1_NIOUT1_PIOUT2_PIOUT2_NIOUT2_PIOUT2_NIPTATIRQP1D0P1D1P1D10P1D11P1D12P1D13P1D14P1D15P1D2P1D3P1D4P1D5P1D6TP12REDP1D7P1D8P1D9P2D0P2D1P2D10P2D11P2D12P2D13P2D14P2D15P2D2P2D3P2D4P2D5P2D6P2D0P2D1P2D2P2D3P2D4P2D5P2D6P2D7JP7JP18U11U19779TQFP+C44.
7FC291nFVOLTDVDD33DVDD18P2D8P2D9PADPLL_LOCKRESETSPI_CLKSPI_CSBSPI_SDISPI_SDOSPI_CLKSPI_CSBSPI_SDISPI_SDOSYNC_1NSYNC_1PSYNC_ONSYNC_OPVDD18_43VDDA33_76VDDA33_78VDDA33_80VDDC18_1VDDC18_10VDDC18_2VDDC18_9VDDD18_23VDDD18_33VDDD18_53VDDD18_60VDDD18VDDD33_38VDDD33_61VREF_74VSSA_77VSSA_79VSSA_81VSSA_82VSSA_85VSSA_88VSSA_91VSSA_94VSSA_95VSSC_11VSSC_3VSSC_4VSSC_7VSSC_8VSSD_15VSSD_22VSSD_32VSSD_44VSSD_54VSSD_64VSS_12VSS_72TXAUX2_NAUX1_NAUX1_PAUX2_PAUX2_NVDDA33_100VSSA_99VDDA33_98VSSA_97VDDA33_96908986876537759293838473713635242120191817343130292827262559584746454241405756555251504948PADVCCYNCAGND3254SN74LVC1G341657068696766141362634310076788096981102923335360163861747779818285889194959799113478152232445464127239DVDD18DVDD33P2D15DPWR33DPWR33DPWR33TP11RED+C120.
1FC301nFC130.
1FR5922R2622R2622C54.
7FC581nFVOLTCVDD18AVDD33CLK_NCLK_P+C550.
1FC570.
1FC561nFC311nFS1512C140.
1FC64.
7FC400.
1FVOLT+C361nFC351nFC390.
1FC271nFC110.
1FC34.
7FC331nFJP4D1ND1PJP8VOLT+C370.
1FC241nFC90.
1FC14.
7F+C620.
1FC341nFVOLT+C380.
1FC251nFC100.
1FC24.
7FC591nFC611nFC600.
1FC181nFC810F6.
3VVOLTVOLT+C151nFC74.
7FC320.
1F+C784.
7FS2S7DATACLK1212S1612U1074LCX11274LCX112KCLRPREJQ_Q5215431653142R6310R70R1150R1050R80R3225R58227U10KCLRPREJQ_Q91214101113C840.
1FR5610R641kCR1VALJP13JP3D2PD2NJP2JP16JP17R641kDPWR33DGND;5CR2VAL3412SW146P3SADTL1-12T4B1311422TC1-1TT4AS6646P3SADTL1-12T3B13142TC1-1TT3A613S6PADTL1-12T1B4TC1-1TT1A13S6PADTL1-12T2B41362132TC1-1TT2A46412S5R60R1150R950R50JP14JP1505361-102Figure105.
EvaluationBoard,Rev.
D,CircuitryLocaltoDevicesAD9776/AD9778/AD9779Rev.
A|Page51of56G2ENBLVPS1G1AG1BLOIPVPS2G4AG4BQBBPVOUTG3IBBPIBBNQBBNLOINAD834998734612131416111012155U9VDDMDGND2VDDMR141kJP1J4C47100pFC720.
1FC730.
1FC4110F10V221DGND22DGND22DGND22DGND22DGND2DGND2MODULATEDOUTPUT2J5JP921DGND2LOCALOSCOUTPUTC74100pFC540.
1FC7917.
2pFC6517.
2pFC75100pFC510.
1F+JP13R6040R2150R3150R25150R614013P52SETC1-1-13T4464P1SADTL1-12T33JP10R2420R62147.
5C822.
1pFL1155nHC4317.
2pFC4417.
2pFC832.
1pFL1055nHR27300D2ND2PAUX2_PAUX2_NR2320C530.
1FC5217.
2pFC5017.
2pFJP13R2040R4150R12150R17150R214064P1SADTL1-12T53R1520R22147.
5C812.
1pFL1155nHC6317.
2pFC6417.
2pFC802.
1pFL1055nHR19300D1ND1PAUX1_PAUX1_NR162005361-103Figure106.
EvaluationBoard,Rev.
D,AD8349QuadratureModulator45S32R13VALR301kΩR31300ΩR2825ΩR2925ΩPETC1-1-13T2J1CLKINC190.
1μFC16DNBCVDD18CLK_PCLK_NC170.
1μFC230.
1μF105361-104Figure107.
EvaluationBoard,Rev.
D,DACClockInterfaceAD9776/AD9778/AD9779Rev.
A|Page52of56A1P4PKG_TYPE=MOLEX110VALA2A3A4A5A6A7A8A9A10A11A15A16A17A18A19A20A21A22A23A24A25C1P4PKG_TYPE=MOLEX110VALC2C3C4C5C6C7C8C9C10C11C15C16C17C18C19C20C21C22C23C24C25CSBSD1P2D0P2D2P2D4P2D6P2D8P2D10P2D12P2D14P1D0P1D2P1D4P1D6P1D8P1D10P1D12P1D14DGNDBLKE1P4PKG_TYPE=MOLEX110VALE2E3E4E5E6E7E8E9E10E11E15E16E17E18E19E20E21E22E23E24E25SCLKSD0P2D1P2D3P2D5P2D7P2D9P2D11P2D13P2D15P1D1P1D3P1D5P1D7P1D9P1D11P1D13P1D15B1P4PKG_TYPE=MOLEX110VALB2B3B4B5B6B7B8B9B10B11B15B16B17B18B19B20B21B22B23B24B25D1P4PKG_TYPE=MOLEX110VALD2D3D4D5D6D7D8D9D10D11D15D16D17D18D19D20D21D22D23D24D25DGND1BLK05361-105Figure108.
EvaluationBoard,Rev.
D,DigitalInputBuffersVALCNTERM_2P12J25V1234U2ADP3339-1-8CVDD18_INJP19C851μFC861μF1P221234U8ADP3339-3-3DPWR33_INJP23C971μFC961μF1234U7ADP3339-3-3AVDD33_INJP22C941μFC931μF1234U4ADP3339-3-3DVDD33_INJP21C911μFC921μF1234U3ADP3339-1-8DVDD18_INJP20C881μFC891μF05361-106Figure109.
EvaluationBoard,On-BoardVoltageRegulatorsAD9776/AD9778/AD9779Rev.
A|Page53of5605361-107Figure110.
EvaluationBoard,Rev.
D,TopSilkScreen05361-108Figure111.
EvaluationBoard,Rev.
D,TopLayerAD9776/AD9778/AD9779Rev.
A|Page54of5605361-109Figure112.
EvaluationBoard,Rev.
D,Layer205361-110Figure113.
EvaluationBoard,Rev.
D,Layer3AD9776/AD9778/AD9779Rev.
A|Page55of5605361-111Figure114.
EvaluationBoard,Rev.
D,BottomLayer05361-112Figure115.
EvaluationBoard,Rev.
D,BottomSilkscreenAD9776/AD9778/AD9779Rev.
A|Page56of56OUTLINEDIMENSIONSNOTES1.
CENTERFIGURESARETYPICALUNLESSOTHERWISENOTED.
2.
THEPACKAGEHASACONDUCTIVEHEATSLUGTOHELPDISSIPATEHEATANDENSURERELIABLEOPERATIONOFTHEDEVICEOVERTHEFULLINDUSTRIALTEMPERATURERANGE.
THESLUGISEXPOSEDONTHEBOTTOMOFTHEPACKAGEANDELECTRICALLYCONNECTEDTOCHIPGROUND.
ITISRECOMMENDEDTHATNOPCBSIGNALTRACESORVIASBELOCATEDUNDERTHEPACKAGETHATCOULDCOMEINCONTACTWITHTHECONDUCTIVESLUG.
ATTACHINGTHESLUGTOAGROUNDPLANEWILLREDUCETHEJUNCTIONTEMPERATUREOFTHEDEVICEWHICHMAYBEBENEFICIALINHIGHTEMPERATUREENVIRONMENTS.
COMPLIANTTOJEDECSTANDARDSMS-026-AED-HD125265076100755114.
00BSCSQ16.
00BSCSQ0.
270.
220.
170.
50BSC1.
051.
000.
950.
150.
050.
750.
600.
45SEATINGPLANE1.
20MAX12526507610075516.
50NOM7°3.
5°0°COPLANARITY0.
080.
200.
09TOPVIEW(PINSDOWN)BOTTOMVIEW(PINSUP)CONDUCTIVEHEATSINKPIN1Figure116.
100-LeadThinQuadFlatPackage,ExposedPad[TQFP_EP](SV-100-1)DimensionsshowninmillimetersORDERINGGUIDEModelTemperatureRangePackageDescriptionPackageOptionAD9776BSVZ140°Cto+85°C100-leadTQFP_EPSV-100-1AD9776BSVZRL140°Cto+85°C100-leadTQFP_EPSV-100-1AD9778BSVZ140°Cto+85°C100-leadTQFP_EPSV-100-1AD9778BSVZRL140°Cto+85°C100-leadTQFP_EPSV-100-1AD9779BSVZ140°Cto+85°C100-leadTQFP_EPSV-100-1AD9779BSVZRL140°Cto+85°C100-leadTQFP_EPSV-100-1AD9776-EBEvaluationBoardAD9778-EBEvaluationBoardAD9779-EBZ1EvaluationBoard1Z=RoHSCompliantPart.
2005–2007AnalogDevices,Inc.
Allrightsreserved.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
D05361-0-3/07(A)