Exposurez8nrd12

FUNCTIONALBLOCKDIAGRAMAGNDVDDDGNDSCLKCONVSTAD7893VINSDATAREFINTRACK/HOLD*AD7893-5,AD7893-10,AD7893-3SIGNALSCALING*12-BITADCOUTPUTREGISTERREV.
EInformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.
However,noresponsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorotherrightsofthirdpartieswhichmayresultfromitsuse.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofAnalogDevices.
aLC2MOS12-Bit,Serial6sADCin8-PinPackageAD7893FEATURESFast12-BitADCwith6sConversionTime8-PinMini-DlPandSOICSingleSupplyOperationHighSpeed,Easy-to-Use,SerialInterfaceOn-ChipTrack/HoldAmplifierSelectionofInputRanges10VforAD7893-102.
5VforAD7893-30Vto+2.
5VforAD7893-20Vto+5VforAD7893-5LowPower:25mWtypGENERALDESCRIPTIONTheAD7893isafast,12-bitADCthatoperatesfromasingle+5Vsupplyandishousedinasmall8-pinmini-DIPand8-pinSOIC.
Thepartcontainsa6ssuccessiveapproximationA/Dconverter,anon-chiptrack/holdamplifier,anon-chipclockandahighspeedserialinterface.
OutputdatafromtheAD7893isprovidedviaahighspeed,serialinterfaceport.
Thistwo-wireserialinterfacehasaserialclockinputandaserialdataoutputwiththeexternalserialclockaccessingtheserialdatafromthepart.
Inadditiontotraditionaldcaccuracyspecificationssuchaslin-earity,full-scaleandoffseterrors,theAD7893isalsospecifiedfordynamicperformanceparameters,includingharmonicdis-tortionandsignal-to-noiseratio.
Thepartacceptsananaloginputrangeof±10V(AD7893-10),±2.
5V(AD7893-3),0Vto+5V(AD7893-5)or0Vto+2.
5V(AD7893-2)andoperatesfromasingle+5Vsupply,consumingonly25mWtypical.
TheAD7893isfabricatedinAnalogDevices'LinearCompat-ibleCMOS(LC2MOS)process,amixedtechnologyprocessthatcombinesprecisionbipolarcircuitswithlowpowerCMOSlogic.
Thepartisavailableinasmall,8-pin,0.
3"wide,plasticorhermeticdual-in-linepackage(mini-DIP)andinan8-pin,smalloutlineIC(SOIC).
OneTechnologyWay,P.
O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:617/329-4700WorldWideWebSite:http://www.
analog.
comFax:617/326-8703AnalogDevices,Inc.
,1997PRODUCTHIGHLIGHTS1.
Fast,12-BitADCin8-PinPackageTheAD7893containsa6sADC,atrack/holdamplifier,controllogicandahighspeedserialinterface,allinan8-pinpackage.
Thisoffersconsiderablespacesavingoveralterna-tivesolutions.
2.
LowPower,SingleSupplyOperationTheAD7893operatesfromasingle+5Vsupplyandcon-sumesonly25mW.
Thislowpower,singlesupplyoperationmakesitidealforbatterypoweredorportableapplications.
3.
HighSpeedSerialInterfaceThepartprovideshighspeedserialdataandserialclocklines,allowingforaneasy,two-wireserialinterfacearrangement.
AD7893–SPECIFICATIONSABSParameterVersionslVersionsVersionUnitsTestConditions/CommentsDYNAMICPERFORMANCESignalto(Noise+Distortion)Ratio2@+25°C707070dBminfIN=10kHzSineWave,fSAMPLE=117kHzTotalHarmonicDistortion(THD)2–80–80–80dBmaxfIN=10kHzSineWave,fSAMPLE=117kHzPeakHarmonicorSpuriousNoise2–80–80–80dBmaxfIN=10kHzSineWave,fSAMPLE=117kHzIntermodulationDistortion(IMD)2fa=9kHz,fb=9.
5kHz,fSAMPLE=117kHz2ndOrderTerms–80–80–80dBmax3rdOrderTerms–80–80–80dBmaxDCACCURACYResolution121212BitsMinimumResolutionforwhichNoMissingCodesareGuaranteed121212BitsRelativeAccuracy2±1±1/2±1LSBmaxDifferentialNonlinearity2±1±1±1LSBmaxPositiveFull-ScaleError2±3±1.
5±3LSBmaxAD7893-2,AD7893-5UnipolarOffsetError±4±3±4LSBmaxAD7893-10,AD7893-3NegativeFull-ScaleError2±3±1.
5±3LSBmaxBipolarZeroError±4±2±4LSBmaxANALOGINPUTAD7893-10InputVoltageRange±10±10±10VoltsInputResistance161616kminAD7893-3InputVoltageRange±2.
5±2.
5±2.
5VoltsInputResistance444kminAD7893-5InputVoltageRange0to+50to+50to+5VoltsInputResistance999kminAD7893-2InputVoltageRange0to+2.
50to+2.
50to+2.
5VoltsInputCurrent500500500nAmaxREFERENCEINPUTREFINInputVoltageRange2.
375/2.
6252.
375/2.
6252.
375/2.
625Vmin/Vmax2.
5V±5%InputCurrent2210AmaxInputCapacitance3101010pFmaxLOGICINPUTSInputHighVoltage,VINH2.
42.
42.
4VminVDD=5V±5%InputLowVoltage,VINL0.
80.
80.
8VmaxVDD=5V±5%InputCurrent,IIN±10±10±10AmaxVIN=0VtoVDDInputCapacitance,CIN3101010pFmaxLOGICOUTPUTSOutputHighVoltage,VOH4.
04.
04.
0VminISOURCE=200AOutputLowVoltage,VOL0.
40.
40.
4VmaxISINK=1.
6mAOutputCodingAD7893-10,AD7893-32sComplementAD7893-2,AD7893-5Straight(Natural)BinaryCONVERSIONRATEConversionTime666smaxTrack/HoldAcquisitionTime21.
51.
51.
5smaxPOWERREQUIREMENTSVDD+5+5+5Vnom±5%forSpecifiedPerformanceIDD999mAmaxPowerDissipation454545mWmaxTypically25mWNOTES1TemperatureRangesareasfollows:A,BVersions:–40°Cto+85°C,SVersion:–55°Cto+125°C.
2SeeTerminology.
3Sampletested@+25°Ctoensurecompliance.
Specificationssubjecttochangewithoutnotice.
REV.
E–2–(VDD=+5V,AGND=DGND=0V,REFIN=+2.
5V.
AllspecificationsTMINtoTMAXunlessotherwisenoted.
)AD7893–3–REV.
ETIMINGCHARACTERISTICS1,2A,BSParameterVersionsVersionUnitsTestConditions/Commentst15050nsminCONVSTPulseWidtht26070nsminSCLKHighPulseWidtht33040nsminSCLKLowPulseWidtht435060nsmaxSCLKRisingEdgetoDataValidDelayt541010nsminBusRelinquishTimeafterFallingEdgeofSCLK100100nsmaxNOTES1Sampletestedat+25°Ctoensurecompliance.
Allinputsignalsaremeasuredwithtr=tf=1ns(10%to90%of+5V)andtimedfromavoltagelevelof+1.
6V.
2SeeFigure5.
3MeasuredwiththeloadcircuitofFigure1anddefinedasthetimerequiredforanoutputtocross0.
8Vor2.
4V.
4Derivedfromthemeasuredtimetakenbythedataoutputstochange0.
5VwhenloadedwiththecircuitofFigure1.
Themeasurednumberisthenextrapolatedbacktoremovetheeffectsofchargingordischargingthe50pFcapacitor.
Thismeansthatthetime,t5,quotedinthetimingcharacteristicsisthetruebusrelinquishtimeofthepartand,assuch,isindependentofexternalbusloadingcapacitances.
(VDD=+5V,AGND=DGND=0V,REFIN=+2.
5V)ABSOLUTEMAXIMUMRATINGS*(TA=+25°Cunlessotherwisenoted)VDDtoAGND0.
3Vto+7VVDDtoDGND0.
3Vto+7VAnalogInputVoltagetoAGNDAD7893-10,AD7893-517VAD7893-2,AD7893-35V,+10VReferenceInputVoltagetoAGND.
.
.
–0.
3VtoVDD+0.
3VDigitalInputVoltagetoDGND0.
3VtoVDD+0.
3VDigitalOutputVoltagetoDGND0.
3VtoVDD+0.
3VOperatingTemperatureRangeCommercial(A,BVersions)40°Cto+85°CExtended(SVersion)55°Cto+125°CStorageTemperatureRange65°Cto+150°CJunctionTemperature150°CPlasticDIPPackage,PowerDissipation450mWθJAThermalImpedance130°C/WLeadTemperature(Soldering,10sec)260°CCerdipPackage,PowerDissipation450mWθJAThermalImpedance125°C/WLeadTemperature(Soldering,10sec)300°CSOICPackage,PowerDissipation450mWθJAThermalImpedance170°C/WLeadTemperature,SolderingVaporPhase(60sec)215°CInfrared(15sec)220°C*Stressesabovethoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.
Thisisastressratingonly;functionaloperationofthedeviceattheseoranyotherconditionsabovethoselistedintheoperationalsectionsofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
TOOUTPUTPIN+2.
1V1.
6mA200A50pFFigure1.
LoadCircuitforAccessTimeandBusRelinquishTimeWARNING!
ESDSENSITIVEDEVICECAUTIONESD(electrostaticdischarge)sensitivedevice.
Electrostaticchargesashighas4000Vreadilyaccumulateonthehumanbodyandtestequipmentandcandischargewithoutdetection.
AlthoughtheAD7893featuresproprietaryESDprotectioncircuitry,permanentdamagemayoccurondevicessubjectedtohighenergyelectrostaticdischarges.
Therefore,properESDprecautionsarerecommendedtoavoidperformancedegradationorlossoffunctionality.
AD7893REV.
E–4–PINFUNCTIONDESCRIPTIONPinPinNo.
MnemonicDescription1REFINVoltageReferenceInput.
Anexternalreferencesourceshouldbeconnectedtothispintoprovidetherefer-encevoltagefortheAD7893'sconversionprocess.
TheREFINinputisbufferedon-chip.
Thenominalref-erencevoltageforcorrectoperationoftheAD7893is+2.
5V.
2VINAnalogInputChannel.
Theanaloginputrangeis±10V(AD7893-10),±2.
5V(AD7893-3),0Vto+5V(AD7893-5)and0Vto+2.
5V(AD7893-2).
3AGNDAnalogGround.
Groundreferencefortrack/hold,comparatorandDAC.
4SCLKSerialClockInput.
AnexternalserialclockisappliedtothisinputtoobtainserialdatafromtheAD7893.
Anewserialdatabitisclockedoutontherisingedgeofthisserialclock,anddataisvalidonthefallingedge.
Theserialclockinputshouldbetakenlowattheendoftheserialdatatransmission.
5SDATASerialDataOutput.
SerialdatafromtheAD7893isprovidedatthisoutput.
TheserialdataisclockedoutbytherisingedgeofSCLKandisvalidonthefallingedgeofSCLK.
Sixteenbitsofserialdataareprovidedwithfourleadingzerosfollowedbythe12bitsofconversiondata.
OnthesixteenthfallingedgeofSCLK,theSDATAlineisdisabled(three-stated).
OutputdatacodingistwoscomplementfortheAD7893-10andAD7893-3,straightbinaryfortheAD7893-2andAD7893-5.
6DGNDDigitalGround.
Groundreferencefordigitalcircuitry.
7CONVSTConvertStart.
Edge-triggeredlogicinput.
Onthefallingedgeofthisinput,theserialclockcounterisresettozero.
Ontherisingedgeofthisinput,thetrack/holdgoesintoitsholdmodeandconversionisinitiated.
8VDDPositivesupplyvoltage,+5V±5%.
PINCONFIGURATIONDIPandSOIC12348765REFINVINAGNDSCLKDGNDSDATAVDDCONVSTAD7893TOPVIEW(NOTTOSCALE)ORDERINGGUIDETemperatureLinearityPackageModelRangeErrorSNROptions*AD7893AN-2–40°Cto+85°C±1LSB70dBN-8AD7893BN-2–40°Cto+85°C±1/2LSB72dBN-8AD7893AR-2–40°Cto+85°C±1LSB70dBSO-8AD7893BR-2–40°Cto+85°C±1/2LSB72dBSO-8AD7893SQ-2–55°Cto+125°C±1LSB70dBQ-8AD7893AN-5–40°Cto+85°C±1LSB70dBN-8AD7893BN-5–40°Cto+85°C±1/2LSB72dBN-8AD7893AR-5–40°Cto+85°C±1LSB70dBSO-8AD7893BR-5–40°Cto+85°C±1/2LSB72dBSO-8AD7893SQ-5–55°Cto+125°C±1LSB70dBQ-8AD7893AN-10–40°Cto+85°C±1LSB70dBN-8AD7893BN-10–40°Cto+85°C±1/2LSB72dBN-8AD7893AR-10–40°Cto+85°C±1LSB70dBSO-8AD7893BR-10–40°Cto+85°C±1/2LSB72dBSO-8AD7893SQ-10–55°Cto+125°C±1LSB70dBQ-8AD7893AR-3–40°Cto+85°C±1LSB70dBSO-8*N=PlasticDIP,Q=Cerdip,SO=SOIC.
AD7893–5–REV.
ERelativeAccuracyRelativeaccuracyorendpointnonlinearityisthemaximumdeviationfromastraightlinepassingthroughtheendpointsoftheADCtransferfunction.
DifferentialNonlinearityThisisthedifferencebetweenthemeasuredandtheideal1LSBchangebetweenanytwoadjacentcodesintheADC.
PositiveFull-ScaleError(AD7893-10)Thisisthedeviationofthelastcodetransition(01.
.
.
110to01.
.
.
111)fromtheideal4*REFIN–1LSB(AD7893-10±10Vrange)aftertheBipolarZeroErrorhasbeenadjustedout.
PositiveFull-ScaleError(AD7893-3)Thisisthedeviationofthelastcodetransition(01.
.
.
110to01.
.
.
111)fromtheideal(REFIN–1LSB)aftertheBipolarZeroErrorhasbeenadjustedout.
PositiveFull-ScaleError(AD7893-5)Thisisthedeviationofthelastcodetransition(11.
.
.
110to11.
.
.
111)fromtheideal(2*REFIN–1LSB)aftertheUni-polarOffsetErrorhasbeenadjustedout.
PositiveFull-ScaleError(AD7893-2)Thisisthedeviationofthelastcodetransition(11.
.
.
110to11.
.
.
111)fromtheideal(REFIN–1LSB)aftertheUnipolarOffsetErrorhasbeenadjustedout.
BipolarZeroError(AD7893-10,10V;AD7893-3,2.
5V)Thisisthedeviationofthemidscaletransition(all0stoall1s)fromtheideal0V(AGND).
UnipolarOffsetError(AD7893-2,AD7893-5)Thisisthedeviationofthefirstcodetransition(00.
.
.
000to00.
.
.
001)fromtheideal1LSB.
NegativeFull-ScaleError(AD7893-10)Thisisthedeviationofthefirstcodetransition(10.
.
.
000to10.
.
.
001)fromtheideal–4*REFIN+1LSB(AD7893-10±10Vrange)afterBipolarZeroErrorhasbeenadjustedout.
NegativeFull-ScaleError(AD7893-3)Thisisthedeviationofthefirstcodetransition(10.
.
.
000to10.
.
.
001)fromtheideal(–REFIN+1LSB)afterBipolarZeroErrorhasbeenadjustedout.
Track/HoldAcquisitionTimeTrack/Holdacquisitiontimeisthetimerequiredfortheoutputofthetrack/holdamplifiertoreachitsfinalvalue,within±1/2LSB,aftertheendofconversion(thepointatwhichthetrack/holdreturnstotrackmode).
ItalsoappliestosituationswherethereisastepinputchangeontheinputvoltageappliedtotheVINinputoftheAD7893.
Thismeansthattheusermustwaitforthedurationofthetrack/holdacquisitiontimeaftertheendofconversionorafterastepinputchangetoVINbeforestartinganotherconversion,toensurethatthepartoperatestospecification.
TERMINOLOGYSignalto(Noise+Distortion)RatioThisisthemeasuredratioofsignalto(noise+distortion)attheoutputoftheA/Dconverter.
Thesignalisthermsamplitudeofthefundamental.
Noiseisthermssumofallnonfundamentalsignalsuptohalfthesamplingfrequency(fS/2),excludingdc.
Theratioisdependentuponthenumberofquantizationlevelsinthedigitizationprocess;themorelevels,thesmallerthequan-tizationnoise.
Thetheoreticalsignalto(noise+distortion)ratioforanidealN-bitconverterwithasinewaveinputisgivenby:Signalto(Noise+Distortion)=(6.
02N+1.
76)dBThusfora12-bitconverter,thisis74dB.
TotalHarmonicDistortionTotalharmonicdistortion(THD)istheratioofthermssumofharmonicstothefundamental.
FortheAD7893,itisdefinedas:whereV1isthermsamplitudeofthefundamentalandV2,V3,V4,V5andV6arethermsamplitudesofthesecondthroughthesixthharmonics.
PeakHarmonicorSpuriousNoisePeakharmonicorspuriousnoiseisdefinedastheratioofthermsvalueofthenextlargestcomponentintheADCoutputspectrum(uptofS/2andexcludingdc)tothermsvalueofthefundamental.
Normally,thevalueofthisspecificationisdeter-minedbythelargestharmonicinthespectrum,butforpartswheretheharmonicsareburiedinthenoisefloor,itwillbeanoisepeak.
IntermodulationDistortionWithinputsconsistingofsinewavesattwofrequencies,faandfb,anyactivedevicewithnonlinearitieswillcreatedistortionproductsatsumanddifferencefrequenciesofmfa±nfbwherem,n=0,1,2,3,etc.
Intermodulationtermsarethoseforwhichneithermnornareequaltozero.
Forexample,thesecondordertermsinclude(fa+fb)and(fa–fb),whilethethirdordertermsinclude(2fa+fb),(2fa–fb),(fa+2fb)and(fa–2fb).
TheAD7893istestedusingtheCCIFstandardwheretwoinputfrequenciesnearthetopendoftheinputbandwidthareused.
Inthiscase,thesecondandthirdordertermsareofdiffer-entsignificance.
Thesecondordertermsareusuallydistancedinfrequencyfromtheoriginalsinewaves,whilethethirdordertermsareusuallyatafrequencyclosetotheinputfrequencies.
Asaresult,thesecondandthirdordertermsarespecifiedsepa-rately.
ThecalculationoftheintermodulationdistortionispertheTHDspecificationwhereitistheratioofthermssumoftheindividualdistortionproductstothermsamplitudeofthefun-damentalexpressedindBs.
THD(dB)=20logV22+V32+V42+V52+V62V1AD7893REV.
E–6–CONVERTERDETAILSTheAD7893isafast,12-bitsinglesupplyA/Dconverter.
Itprovidestheuserwithsignalscaling(AD7893-10),track/hold,A/Dconverterandserialinterfacelogicfunctionsonasinglechip.
TheA/DconvertersectionoftheAD7893consistsofaconventionalsuccessive-approximationconverterbasedonanR-2Rladderstructure.
ThesignalscalingontheAD7893-10,AD7893-5andAD7893-3allowstheparttohandle±10V,0Vto+5Vand±2.
5Vinputsignals,respectively,whileoperatingfromasingle+5Vsupply.
TheAD7893-2acceptsananalogin-putrangeof0Vto+2.
5V.
Thepartrequiresanexternal+2.
5Vreference.
Thereferenceinputtothepartisbufferedon-chip.
AmajoradvantageoftheAD7893isthatitprovidesalloftheabovefunctionsinan8-pinpackage,either8-pinmini-DIPorSOIC.
Thisofferstheuserconsiderablespacesavingadvantagesoveralternativesolutions.
TheAD7893typicallyconsumesonly25mW,makingitidealforbattery-poweredapplications.
ConversionisinitiatedontheAD7893bypulsingtheCONVSTinput.
OntherisingedgeofCONVST,theon-chiptrack/holdgoesfromtrack-to-holdmodeandtheconversionsequenceisstarted.
Theconversionclockforthepartisgeneratedinternallyusingalaser-trimmedclockoscillatorcircuit.
ConversiontimefortheAD7893is6s,andthetrack/holdacquisitiontimeis1.
5s.
Toobtainoptimumperformancefromthepart,thereadoperationshouldnotoccurduringtheconversionorduring600nspriortothenextconversion.
Thisallowstheparttoop-erateatthroughputratesupto117kHzandtoachievedatasheetspecifications.
Thepartcanoperateathigherthroughputrates(upto133kHz)withslightlydegradedperformance(seeTimingandControlsection).
CIRCUITDESCRIPTIONAnalogInputSectionTheAD7893isofferedasfourparttypes:theAD7893-10,whichhandlesa±10Vinputvoltagerange;theAD7893-3,whichhandlesa±2.
5Vinputvoltagerange;theAD7893-5,whichhandlesa0Vto+5Vinputrange;andtheAD7893-2,whichhandlesa0Vto+2.
5Vinputvoltagerange.
Figure2showstheanaloginputsectionfortheAD7893-10,AD7893-5andAD7893-3.
TheanaloginputrangeoftheAD7893-10is±10Vintoaninputresistanceoftypically33k.
TheanaloginputrangeoftheAD7893-3is±2.
5Vintoaninputresistanceoftypically12k.
TheinputrangeontheAD7893-5is0Vto+5Vintoaninputresistanceoftypically11k.
Thisin-putisbenignwithnodynamicchargingcurrents,astheresistorstageisfollowedbyahighinputimpedancestageofthetrack/holdAGNDAD7893-10/AD7893-5VINREFINTRACK/HOLDTOADCREFERENCECIRCUITRYTOINTERNALCOMPARATORR3R2R1Figure2.
AD7893-10/AD7893-3/AD7893-5AnalogInputStructureamplifier.
FortheAD7893-10,R1=30k;R2=7.
5kandR3=10k.
FortheAD7893-3,R1=R2=6.
5k,andR3isopencircuit.
FortheAD7893-5,R1andR3=5kwhileR2isopen-circuit.
FortheAD7893-10andAD7893-3,thedesignedcodetransi-tionsoccuronsuccessiveintegerLSBvalues(i.
e.
,1LSB,2LSBs,3LSBs.
.
.
).
Outputcodingistwoscomplementbinarywith1LSB=FS/4096.
Theidealinput/outputtransferfunctionfortheAD7893-10andAD7893-3isshowninTableI.
TableI.
IdealInput/OutputCodeTablefortheAD7893-10/AD7893-3DigitalOutputAnalogInput1CodeTransition+FSR/2–1LSB2011.
.
.
110to011.
.
.
111+FSR/2–2LSBs011.
.
.
101to011.
.
.
110+FSR/2–3LSBs011.
.
.
100to011.
.
.
101AGND+1LSB000.
.
.
000to000.
.
.
001AGND111.
.
.
111to000.
.
.
000AGND–1LSB111.
.
.
110to111.
.
.
111–FSR/2+3LSBs100.
.
.
010to100.
.
.
011–FSR/2+2LSBs100.
.
.
001to100.
.
.
010–FSR/2+1LSB100.
.
.
000to100.
.
.
001NOTES1FSRisfull-scalerangeandis20V(AD7893-10)and=5V(AD7893-3)withREFIN=+2.
5V.
21LSB=FSR/4096=4.
883mV(AD7893-10)and1.
22mV(AD7893-3)withREFIN=+2.
5V.
FortheAD7893-5,thedesignedcodetransitionsoccuragainonsuccessiveintegerLSBvalues.
Outputcodingisstraight(natural)binarywith1LSB=FS/4096=5V/4096=1.
22mV.
Theidealinput/outputtransferfunctionfortheAD7893-5isshowninTableII.
TheanaloginputsectionfortheAD7893-2containsnobiasingresistors,andtheVINpindrivestheinputdirectlytothetrack/holdamplifier.
Theanaloginputrangeis0Vto+2.
5Vintoahighimpedancestage,withaninputcurrentoflessthan500nA.
Thisinputisbenign,withnodynamicchargingcur-rents.
Onceagain,thedesignedcodetransitionsoccuronsuc-cessiveintegerLSBvalues.
Outputcodingisstraight(natural)binarywith1LSB=FS/4096=2.
5V/4096=0.
61mV.
TableIIalsoshowstheidealinput/outputtransferfunctionfortheAD7893-2.
TableII.
IdealInput/OutputCodeTableforAD7893-2/AD7893-5DigitalOutputAnalogInput1CodeTransition+FSR–1LSB2111.
.
.
110to111.
.
.
111+FSR–2LSB111.
.
.
101to111.
.
.
110+FSR–3LSB111.
.
.
100to111.
.
.
101AGND+3LSB000.
.
.
010to000.
.
.
011AGND+2LSB000.
.
.
001to000.
.
.
010AGND+1LSB000.
.
.
000to000.
.
.
001NOTES1FSRisFull-ScaleRangeandis5VforAD7893-5and2.
5VforAD7893-2withREFIN=+2.
5V.
21LSB=FSR/4096andis1.
22mVforAD7893-5and0.
61mVforAD7893-2withREFIN=+2.
5V.
AD7893–7–REV.
ETrack/HoldSectionThetrack/holdamplifierontheanaloginputoftheAD7893allowstheADCtoaccuratelyconvertaninputsinewaveoffull-scaleamplitudeto12-bitaccuracy.
Theinputbandwidthofthetrack/holdisgreaterthantheNyquistrateoftheADC,evenwhentheADCisoperatedatitsmaximumthroughputrateof117kHz(i.
e.
,thetrack/holdcanhandleinputfrequenciesinexcessof58kHz).
Thetrack/holdamplifieracquiresaninputsignalto12-bitaccu-racyinlessthan1.
5s.
Theoperationofthetrack/holdisessen-tiallytransparenttotheuser.
Thetrack/holdamplifiergoesfromitstrackingmodetoitsholdmodeatthestartofconversion(i.
e.
,therisingedgeofCONVST).
Theaperturetimeforthetrack/hold(i.
e.
,thedelaytimebetweentheexternalCONVSTsignalandthetrack/holdactuallygoingintohold)istypically15ns.
Attheendofconversion(6saftertherisingedgeofCONVST)thepartreturnstoitstrackingmode.
Theacquisi-tiontimeofthetrack/holdamplifierbeginsatthispoint.
ReferenceInputThereferenceinputtotheAD7893isabufferedon-chipwithamaximumreferenceinputcurrentof1A.
Thepartisspecifiedwitha+2.
5Vreferenceinputvoltage.
ErrorsinthereferencesourcewillresultingainerrorsintheAD7893'stransferfunc-tionandwilladdtothespecifiedfull-scaleerrorsonthepart.
OntheAD7893-10itwillalsoresultinanoffseterrorinjectedintheattenuatorstage.
SuitablereferencesourcesfortheAD7893includetheAD780andAD680precision+2.
5Vreferences.
TimingandControlSectionFigure3showsthetimingandcontrolsequencerequiredtoob-tainoptimumperformancefromtheAD7893.
Inthesequenceshown,conversionisinitiatedontherisingedgeofCONVST,andnewdatafromthisconversionisavailableintheoutputreg-isteroftheAD78936slater.
Oncethereadoperationhastakenplace,afurther600nsshouldbeallowedbeforethenextrisingedgeofCONVSTtooptimizethesettlingofthetrack/holdamplifierbeforethenextconversionisinitiated.
Withtheserialclockfrequencyatitsmaximumof8.
33MHz,theachiev-ablethroughputrateforthepartis6s(conversiontime)plus1.
92s(readtime)plus0.
6s(acquisitiontime).
Thisresultsinaminimumthroughputtimeof8.
52s(equivalenttoathrough-putrateof117kHz).
ThereadoperationconsistsofsixteenserialclockpulsestotheoutputshiftregisteroftheAD7893.
AftersixteenserialclockpulsestheshiftregisterisresetandtheSDATAlineisthree-stated.
Iftherearemoreserialclockpulsesafterthesixteenthclock,theshiftregisterwillbemovedonpastitsresetstate;however,theshiftregisterwillberesetagainonthefallingedgeoftheCONVSTsignaltoensurethatthepartreturnstoaknownstateeveryconversioncycle.
Asaresult,areadoperationfromtheoutputregistershouldnotstraddleacrossthefallingedgeofCONVSTastheoutputshiftregisterwillberesetinthemiddleofthereadoperation,andthedatareadbackintothemicroprocessorwillappearinvalid.
Thethroughputrateofthepartcanbeincreasedbyreadingdataduringconversion.
Ifthedataisreadduringconversion,athroughputtimeof6s(conversiontime)plus1.
5sisachieved.
Thisminimumthroughputtimeof7.
5sisachievedwithaslightreductioninperformancefromtheAD7893.
Thesignalto(noise+distortion)numberislikelytodegradebyap-proximately1.
5dBwhilethecodeflickerfromthepartwillalsoincrease(seeAD7893PERFORMANCEsection).
BecausetheAD7893isprovidedinan8-pinpackagetomini-mizeboardspace,thenumberofpinsavailableforinterfacingisverylimited.
Asaresult,nostatussignalisprovidedfromtheAD7893toindicatewhenconversioniscomplete.
Inmanyapplications,thiswillnotbeaproblemasthedatacanbereadfromtheAD7893duringconversionorafterconversion;how-ever,applicationsthatwanttoachieveoptimumperformancefromtheAD7893willhavetoensurethatthedatareaddoesnotoccurduringconversionorduring600nspriortotherisingedgeofCONVST.
Thiscanbeachievedintwoways.
Thefirstistoensureinsoftwarethatthereadoperationisnotinitiateduntil6saftertherisingedgeofCONVST.
ThiswillonlybepossibleifthesoftwareknowswhentheCONVSTcommandisissued.
ThesecondschemewouldbetousetheCONVSTsig-nalasboththeconversionstartsignalandaninterruptsignal.
ThesimplestwaytodothiswouldbetogenerateasquarewavesignalforCONVSTwithhighandlowtimesof6s(seeFigure4).
ConversionisinitiatedontherisingedgeofCONVST.
ThefallingedgeofCONVSToccurs6slaterandcanbeusedasei-theranactiveloworfalling,edge-triggeredinterruptsignaltotelltheprocessortoreadthedatafromtheAD7893.
Providedthatthereadoperationiscompleted600nsbeforetherisingedgeofCONVST,theAD7893willoperatetospecification.
CONVSTSCLKCONVERSIONISINITIATEDANDTRACK/HOLDGOESINTOHOLDt1CONVERSIONENDS6sLATERSERIALREADOPERATIONOUTPUTSERIALSHIFTREGISTERISRESET600nsMINtCONVERTREADOPERATIONSHOULDEND600nsPRIORTONEXTRISINGEDGEOFCONVSTFigure3.
TimingSequenceforOptimumPerformancefromtheAD7893AD7893REV.
E–8–Thisschemelimitsthethroughputrateto12sminimum;how-ever,dependingontheresponsetimeofthemicroprocessortotheinterruptsignalandthetimetakenbytheprocessortoreadthedata,thismaybethefastestthesystemcouldhaveoperated.
Inanycase,theCONVSTsignaldoesnothavetohavea50:50dutycycle.
Thiscanbetailoredtooptimizethethroughputrateofthepartforagivensystem.
Alternatively,theCONVSTsignalcanbeusedasanormalnarrowpulsewidth.
TherisingedgeofCONVSTcanbeusedasanactivehighorrisingedge-triggeredinterrupt.
Asoftwaredelayof6scanthenbeimplementedbeforedataisreadfromthepart.
SerialInterfaceTheserialinterfacetotheAD7893consistsofjusttwowires,aserialclockinput(SCLK)andtheserialdataoutput(SDATA).
Thisallowsforaneasytouseinterfacetomostmicrocontrollers,DSPprocessorsandshiftregisters.
Figure5showsthetimingdiagramforthereadoperationtotheAD7893.
Theserialclockinput(SCLK)providestheclocksourcefortheserialinterface.
SerialdataisclockedoutfromtheSDATAlineontherisingedgeofthisclockandisvalidonthefallingedgeofSCLK.
Sixteenclockpulsesmustbeprovidedtotheparttoaccesstofullconversionresult.
TheAD7893pro-videsfourleadingzerosfollowedbythe12-bitconversionresultstartingwiththeMSB(DB11).
ThelastdatabittobeclockedoutonthefinalrisingclockedgeistheLSB(DB0).
Onthesix-teenthfallingedgeofSCLK,theSDATAlineisdisabled(three-stated).
Afterthislastbithasbeenclockedout,theSCLKinputshouldreturnlowandremainlowuntilthenextserialdatareadoperation.
Ifthereareextraclockpulsesafterthesixteenthclock,theAD7893willstartoveragainwithoutputtingdatafromitsoutputregister,andthedatabuswillnolongerbethree-statedevenwhentheclockstops.
ProvidedthattheserialclockhasstoppedbeforethenextfallingedgeofCONVST,theAD7893willcontinuetooperatecorrectlywiththeoutputshiftregisterbeingresetonthefallingedgeofCONVST;however,theSCLKlinemustbelowwhenCONVSTgoeslowinordertoresettheoutputshiftregistercorrectly.
Theserialclockinputdoesnothavetobecontinuousduringtheserialreadoperation.
Thesixteenbitsofdata(fourleadingzerosand12bitconversionresult)canbereadfromtheAD7893inanumberofbytes;however,theSCLRinputmustremainlowbe-tweenthetwobytes.
Normally,theoutputregisterisupdatedattheendofconver-sion.
Ifaserialreadfromtheoutputregisterisinprogresswhenconversioniscomplete;however,theupdatingoftheoutputregisterisdeferred.
Inthiscase,theoutputregisterisupdatedwhentheserialreadiscompleted.
IftheserialreadhasnotbeencompletedbeforethenextfallingedgeofCONVST,theoutputregisterwillbeupdatedonthefallingedgeofCONVST,andtheoutputshiftregistercountisreset.
InapplicationswherethedatareadhasbeenstartedandnotcompletedbeforethefallingedgeofCONVST,theusermustprovideaCONVSTpulsewidthofgreaterthan1.
5stoensurecorrectsetupoftheAD7893beforethenextconversionisinitiated.
Inapplicationswheretheoutputupdatetakesplaceeitherattheendofconversionorattheendofaserialreadthatiscompleted1.
5sbeforetherisingedgeofCONVST,thenormalpulsewidthof50nsminimumappliestoCONVST.
CONVSTSCLKCONVERSIONISINITIATEDANDTRACK/HOLDGOESINTOHOLDCONVSTINDICATESTOPTHATCONVERSIONISCOMPLETEtCONVERTSERIALREADOPERATIONPINTSERVICEORPOLLINGROUTINE600nsMINREADOPERATIONSHOULDEND600nsPRIORTONEXTRISINGEDGEOFCONVSTFigure4.
CONVSTUsedasStatusSignalSDATA(O)SCLK(I)FOURLEADINGZEROSDB11DB10THREE-STATETHREE-STATEDB0t5t4t3t2Figure5.
DataReadOperationAD7893–9–REV.
ETheAD7893countstheserialclockedgestoknowwhichbitfromtheoutputregistershouldbeplacedontheSDATAout-put.
Toensurethatthepartdoesnotlosesynchronization,theserialclockcounterisresetonthefallingedgeoftheCONVSTinput,providedtheSCLRlineislow.
TheusershouldensurethatafallingedgeontheCONVSTinputdoesnotoccurwhileaserialdatareadoperationisinprogress.
MICROPROCESSOR/MICROCONTROLLERINTERFACETheAD7893providesatwo-wireserialinterfacethatcanbeusedforconnectiontotheserialportsofDSPprocessorsandmicrocontrollers.
Figures6through9showtheAD7893inter-facedtoanumberofdifferentmicrocontrollersandDSPpro-cessors.
TheAD7893acceptsanexternalserialclockand,asaresult,inallinterfacesshownhere,theprocessor/controllerisconfiguredasthemaster,providingtheserialclockwiththeAD7893configuredastheslaveinthesystem.
AD7893-8051InterfaceFigure6showsaninterfacebetweentheAD7893andthe8XC51microcontroller.
The8XC51isconfiguredforitsMode0serialinterfacemode.
ThediagramshowsthesimplestformoftheinterfacewheretheAD7893istheonlypartconnectedtotheserialportofthe8XC51and,therefore,nodecodingoftheserialreadoperationsisrequired.
ItalsomakesnoprovisionsformonitoringwhenconversioniscompleteontheAD7893.
Eitherofthesetwotaskscanreadilybeaccomplishedwithminormodificationstotheinterface.
TochipselecttheAD7893insystemswheremorethanonedeviceisconnectedtothe8XC51'sserialport,aportbitconfiguredasanoutputfromoneofthe8XC51'sparallelportscanbeusedtogateonorofftheserialclocktotheAD7893.
AsimpleANDfunctiononthisportbitandtheserialclockfromthe8XC51willprovidethisfunction.
TheportbitshouldbehightoselecttheAD7893andlowwhenitisnotselected.
TomonitortheconversiontimeontheAD7893,aschemesuchaspreviouslyoutlinedwithCONVSTcanbeused.
Thiscanbeimplementedintwoways.
OneistoconnecttheCONVSTlinetoanotherparallelportbitthatisconfiguredasaninput.
Thisportbitcanthenbepolledtodeterminewhenconversioniscomplete.
Analternativeistouseaninterruptdrivensystem,inwhichcasetheCONVSTlineshouldbeconnectedtotheINT1inputofthe8XC51.
Theserialclockratefromthe8XC51islimitedtosignificantlylessthantheallowableinputserialclockfrequencywithwhichtheAD7893canoperate.
Asaresult,thetimetoreaddatafromthepartwillactuallybelongerthantheconversiontimeofthepart.
ThismeansthattheAD7893cannotrunatitsmaximumthroughputratewhenusedwiththe8XC51.
AD7893-68HC11InterfaceAninterfacecircuitbetweentheAD7893andthe68HC11microcontrollerisshowninFigure7.
Fortheinterfaceshown,the68HC11SPIportisused,andthe68HC11isconfiguredinitssingle-chipmode.
The68HC11isconfiguredinthemastermodewithitsCPOLbitsettoalogiczeroanditsCPHAbitsettoalogicone.
Aswiththepreviousinterface,thediagramshowsthesimplestformoftheinterfacewheretheAD7893istheonlypartconnectedtotheserialportofthe68HC11and,therefore,nodecodingoftheserialreadoperationsisrequired.
Italsomakesnoprovisionsformonitoringwhenconversioniscom-pleteontheAD7893.
Onceagain,eitherofthesetwotaskscanreadilybeaccom-plishedwithminormodificationstotheinterface.
TochipselecttheAD7893insystemswheremorethanonedeviceiscon-nectedtothe68HC11'sserialport,aportbit,configuredasanoutputfromoneofthe68HC11'sparallelports,canbeusedtogateonorofftheserialclocktotheAD7893.
AsimpleANDfunctiononthisportbitandtheserialclockfromthe68HC11willprovidethisfunction.
TheportbitshouldbehightoselecttheAD7893andlowwhenitisnotselected.
TomonitortheconversiontimeontheAD7893,aschemesuchasoutlinedinthepreviousinterfacewithCONVSTcanbeused.
Thiscanbeimplementedintwoways.
OneistoconnecttheCONVSTlinetoanotherparallelportbitthatisconfiguredasaninput.
Thisportbitcanthenbepolledtodeterminewhenconversioniscomplete.
Analternativeistouseaninterruptdrivensystem,inwhichcasetheCONVSTlineshouldbecon-nectedtotheIRQinputofthe68HC11.
Theserialclockratefromthe68HC11islimitedtosignificantlylessthantheallowableinputserialclockfrequencywithwhichtheAD7893canoperate.
Asaresult,thetimetoreaddatafromthepartwillactuallybelongerthantheconversiontimeofthepart.
ThismeansthattheAD7893cannotrunatitsmaximumthroughputratewhenusedwiththe68HC11.
AD7893SDATASCLK8XC51P3.
0P3.
1Figure6.
AD7893to8XC51InterfaceAD7893SDATASCLK68HC11SCKMISOFigure7.
AD7893to68HC11InterfaceAD7893REV.
E–10–AD7893–ADSP-2105InterfaceAninterfacecircuitbetweentheAD7893andtheADSP-2105DSPprocessorisshowninFigure8.
Intheinterfaceshown,theRFS1outputfromtheADSP-2105'sSPORT1serialportisusedtogatetheserialclock(SCLK1)oftheADSP-2105beforeitisappliedtotheSCLKinputoftheAD7893.
TheRFS1out-putisconfiguredforactivehighoperation.
TheinterfaceensuresanoncontinuousclockfortheAD7893'sserialclockinputwithonlysixteenserialclockpulsesprovided,andtheserialclocklineoftheAD7893remaininglowbetweendatatransfers.
TheSDATAlinefromtheAD7893isconnectedtotheDR1lineoftheADSP-2105'sserialport.
AD7893SDATASCLKADSP-2105DR1RFS1SCLK1Figure8.
AD7893toADSP-2105InterfaceThetimingrelationshipbetweentheSCLK1andRFS1outputsoftheADSP-2105aresuchthatthedelaybetweentherisingedgeoftheSCLK1andtherisingedgeofanactivehighRFS1isupto25ns.
Thereisalsoarequirementthatdatamustbesetup10nspriortothefallingedgeoftheSCLK1tobereadcor-rectlybytheADSP-2105.
ThedataaccesstimefortheAD7893is50nsfromtherisingedgeofitsSCLKinput.
Assuminga10nspropagationdelaythroughtheexternalANDgate,thehightimeoftheSCLK1outputoftheADSP-2105mustbe≥(50+25+10+10)ns,i.
e.
,≥95ns.
ThismeansthattheserialclockfrequencywithwhichtheinterfaceofFigure13canworkwithislimitedto5.
26MHz.
AnalternativeschemeistoconfiguretheADSP-2105toacceptanexternalserialclock.
Inthiscase,anexternalnoncontinuousserialclockthatdrivestheserialclockinputsofboththeADSP-2105andtheAD7893isprovided.
Inthisscheme,theserialclockfrequencyislimitedto5MHzbytheADSP-2105.
TomonitortheconversiontimeontheAD7893,aschemesuchasoutlinedinpreviousinterfaceswithCONVSTcanbeused.
ThiscanbeimplementedbyconnectingtheCONVSTlinedirectlytotheIRQ2inputoftheADSP-2105.
AD7893–DSP56000InterfaceFigure9showsaninterfacecircuitbetweentheAD7893andtheDSP56000DSPprocessor.
TheDSP5600isconfiguredfornor-malmodeasynchronousoperationwithgatedclock.
Itisalsosetupfora16-bitwordwiththegatedserialclockbeinggeneratedbytheDSP56000andappearsontheSC0pin.
TheSC0pinshouldbeconfiguredasanoutputbysettingbitSCD0to1.
Inthismode,theDSP56000providessixteenserialclockpulsestotheAD7893inaserialreadoperation.
TheDSP56000assumesvaliddataonthefirstfallingedgeofSCK,sotheinterfaceissimplytwo-wireasshowninFigure9.
TomonitortheconversiontimeontheAD7893,aschemesuchasoutlinedinpreviousinterfaceexampleswithCONVSTcanbeused.
ThiscanbeimplementedbyconnectingtheCONVSTlinedirectlytotheIRQAinputoftheDSP56000.
AD7893SDATASCLKDSP56000SC0SRDFigure9.
AD7893toDSP56000InterfaceAD7893PERFORMANCELinearityThelinearityoftheAD7893isdeterminedbytheon-chip12-bitD/Aconverter.
ThisisasegmentedDACthatislasertrimmedfor12-bitintegrallinearityanddifferentiallinearity.
Typicalrelativenumbersforthepartare±1/4LSB,whilethetypicalDNLerrorsare±1/2LSB.
NoiseInanA/Dconverter,noiseexhibitsitselfascodeuncertaintyindcapplicationsandasthenoisefloor(inanFFT,forexample)inacapplications.
InasamplingA/DconverterliketheAD7893,allinformationabouttheanaloginputappearsinthebasebandfromdcto1/2thesamplingfrequency.
Theinputbandwidthofthetrack/holdexceedstheNyquistbandwidth;therefore,anantialiasingfiltershouldbeusedtoremoveunwantedsignalsabovefS/2intheinputsignalinapplicationswheresuchsignalsexist.
Figure10showsahistogramplotfor8192conversionsofadcinputusingtheAD7893.
Theanaloginputwassetatthecenterofacodetransition.
ThetimingandcontrolsequenceusedwasperFigure3wheretheoptimumperformanceoftheADCwasachieved.
Itcanbeseenthatalmostallthecodesappearintheoneoutputbin,indicatingverygoodnoiseperformancefromtheADC.
ThermsnoiseperformancefortheAD7893-2fortheaboveplotwas87V.
Sincetheanaloginputrange,andhenceLSBsize,ontheAD7893-10iseighttimeswhatitisfortheAD7893-2,thesameoutputcodedistributionresultsinanout-putrmsnoiseof700VfortheAD7893-10.
CODE90001000(X–4)(X–3)OCCURRENCESOFCODE(X–2)(X–1)X(X+1)(X+2)(X+3)(X+4)80005000400030002000700060000SAMPLINGFREQUENCY=102.
4kHzTA=+25°CFigure10.
Histogramof8192ConversionsofaDCInputAD7893–11–REV.
EEffectiveNumberofBitsTheformulaforsignalto(noise+distortion)ratio(seeTermi-nologysection)isrelatedtotheresolutionornumberofbitsintheconverter.
Rewritingtheformulagivesameasureofperfor-manceexpressedineffectivenumberofbits(N):N=(SNR–1.
76)/6.
02whereSNRisSignalto(Noise+Distortion)Ratio.
Theeffectivenumberofbitsforadevicecanbecalculatedfromitsmeasuredsignalto(noise+distortion)ratio.
Figure13showsatypicalplotofeffectivenumberofbitsversusfrequencyfortheAD7893-2fromdctofSAMPLING/2.
Thesamplingfrequencyis102.
4kHz.
TheplotshowsthattheAD7893convertsaninputsinewaveof51.
2kHztoaneffectivenumbersofbitsof11,whichequatestoasignalto(noise+distortion)levelof68dB.
INPUTFREQUENCY–kHz12.
011.
510.
0051.
225.
6EFFECTIVENUMBEROFBITS11.
010.
5Figure13.
EffectiveNumberofBitsvs.
FrequencyThesamedataispresentedinFigure11asinFigure10exceptthat,inthiscase,theoutputdatareadforthedeviceoccursdur-ingconversion.
Thishastheeffectofinjectingnoiseontothediewhilebitdecisionsarebeingmade;thisincreasesthenoisegen-eratedbytheAD7893.
Thehistogramplotfor8192conversionsofthesamedcinputnowshowsalargerspreadofcodeswiththermsnoisefortheAD7893-2increasingto210V.
Thisef-fectwillvarydependingonwheretheserialclockedgesappearwithrespecttothebittrialsoftheconversionprocess.
Itispos-sibletoachievethesamelevelofperformancewhenreadingduringconversionaswhenreadingafterconversion,dependingontherelationshipoftheserialdockedgestothebittrialpoints.
CODE7500(X–4)(X–3)OCCURRENCESOFCODE70006500600005500500045004000350030002500200015001000500(X–2)(X–1)(X+1)(X+2)(X+3)(X+4)XSAMPLINGFREQUENCY=102.
4kHzTA=+25°CFigure11.
Histogramof8192ConversionswithReadDur-ingConversionDynamicPerformanceWithacombinedconversionandacquisitiontimeof7.
5s,theAD7893isidealforwidebandwidthsignalprocessingapplica-tions.
TheseapplicationsrequireinformationontheADC'seffectonthespectralcontentoftheinputsignal.
Signalto(noise+distortion)ratio,totalharmonicdistortion,peakharmonicorspuriousnoise,andintermodulationdistortionareallspecified.
Figure12showsatypicalFFTplotofa10kHz,0Vto+2.
5VinputafterbeingdigitizedbytheAD7893-2,operatingata102.
4kHzsamplingrate.
Thesignalto(noise+distortion)ratiois71.
5dB,andthetotalharmonicdistortionis–83dB.
FREQUENCY–kHzSNRISSIGNALTO(NOISEANDDISTORTION)RATIO0–30–180051.
225.
6SIGNALAMPLITUDE–dB–60–80–120SAMPLERATE=102.
4kHzINPUTFREQUENCY=10kHzSNR=71.
5dBTA=+25°CFigure12.
AD7893FFTPlotAD7893REV.
E–12–OUTLINEDIMENSIONSDimensionsshownininchesand(mm).
PRINTEDINU.
S.
A.
C1787c–2–1/97PlasticDIP(N-8)PIN10.
280(7.
11)0.
240(6.
10)4581SEATINGPLANE0.
060(1.
52)0.
015(0.
38)0.
130(3.
30)MIN0.
210(5.
33)MAX0.
160(4.
06)0.
115(2.
93)0.
430(10.
92)0.
348(8.
84)0.
022(0.
558)0.
014(0.
356)0.
070(1.
77)0.
045(1.
15)0.
100(2.
54)BSC0.
325(8.
25)0.
300(7.
62)0.
015(0.
381)0.
008(0.
204)0.
195(4.
95)0.
115(2.
93)Cerdip(Q-8)0.
320(8.
13)0.
290(7.
37)0.
015(0.
38)0.
008(0.
20)15°0°0.
005(0.
13)MIN0.
055(1.
4)MAX1PIN14580.
310(7.
87)0.
220(5.
59)0.
405(10.
29)MAX0.
200(5.
08)MAXSEATINGPLANE0.
023(0.
58)0.
014(0.
36)0.
070(1.
78)0.
030(0.
76)0.
060(1.
52)0.
015(0.
38)0.
150(3.
81)MIN0.
200(5.
08)0.
125(3.
18)0.
100(2.
54)BSCSOIC(SO-8)0.
0098(0.
25)0.
0075(0.
19)0.
0500(1.
27)0.
0160(0.
41)8°0°0.
0196(0.
50)0.
0099(0.
25)x45°PIN10.
1574(4.
00)0.
1497(3.
80)0.
2440(6.
20)0.
2284(5.
80)45180.
0192(0.
49)0.
0138(0.
35)0.
0500(1.
27)BSC0.
0688(1.
75)0.
0532(1.
35)0.
0098(0.
25)0.
0040(0.
10)0.
1968(5.
00)0.
1890(4.
80)