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ADC101S021www.
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comSNAS307G–JULY2005–REVISEDJANUARY2014ADC101S021SingleChannel,50to200ksps,10-BitA/DConverterCheckforSamples:ADC101S0211FEATURESDESCRIPTIONTheADC101S021isalow-power,singlechannel2SpecifiedOveraRangeofSampleRates.
CMOS10-bitanalog-to-digitalconverterwithahigh-6-LeadWSONandSOT-23Packagesspeedserialinterface.
UnliketheconventionalVariablePowerManagementpracticeofspecifyingperformanceatasinglesamplerateonly,theADC101S021isfullyspecifiedoveraSinglePowerSupplywith2.
7V-5.
25VRangesampleraterangeof50kspsto200ksps.
TheSPI/QSPI/MICROWIRE/DSPCompatibleconverterisbaseduponasuccessive-approximationregisterarchitecturewithaninternaltrack-and-holdAPPLICATIONScircuit.
PortableSystemsTheoutputserialdataisstraightbinary,andisRemoteDataAcquisitioncompatiblewithseveralstandards,suchasSPI,QSPI,MICROWIRE,andmanycommonDSPInstrumentationandControlSystemsserialinterfaces.
TheADC101S021operateswithasinglesupplythatcanrangefrom+2.
7Vto+5.
25V.
Normalpowerconsumptionusinga+3.
6Vor+5.
25Vsupplyis2.
34mWand8.
9mW,respectively.
Thepower-downfeaturereducesthepowerconsumptiontoaslowas2.
6Wusinga+5.
25Vsupply.
TheADC101S021ispackagedin6-leadWSONandSOT-23packages.
Operationovertheindustrialtemperaturerangeof40°Cto+85°Cisensured.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2Alltrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2005–2014,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
ADC101S021SNAS307G–JULY2005–REVISEDJANUARY2014www.
ti.
comThesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
Table1.
KeySpecificationsVALUEUNITDNL+0.
16/-0.
09LSB(typ)INL+0.
14/-0.
13LSB(typ)SNR61.
6dB(typ)PowerConsumption3.
6VSupply2.
34mW(typ)5.
25VSupply8.
9mW(typ)Table2.
Pin-CompatibleAlternativesbyResolutionandSpeed(1)ResolutionSpecifiedforSampleRateRangeof:50to200ksps200to500ksps500kspsto1Msps12-bitADC121S021ADC121S051ADC121S10110-bitADC101S021ADC101S051ADC101S1018-bitADC081S021ADC081S051ADC081S101(1)Alldevicesarefullypinandfunctioncompatible.
ConnectionDiagramFigure1.
6-LeadSOT-23orWSONSeeDBVorNGFPackageBlockDiagramPINDESCRIPTIONSANDEQUIVALENTCIRCUITSPinNo.
SymbolDescriptionANALOGI/O3VINAnaloginput.
Thissignalcanrangefrom0VtoVA.
DIGITALI/O4SCLKDigitalclockinput.
Thisclockdirectlycontrolstheconversionandreadoutprocesses.
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comSNAS307G–JULY2005–REVISEDJANUARY2014PINDESCRIPTIONSANDEQUIVALENTCIRCUITS(continued)PinNo.
SymbolDescriptionANALOGI/O5SDATADigitaldataoutput.
TheoutputsamplesareclockedoutofthispinonfallingedgesoftheSCLKpin.
6CSChipselect.
OnthefallingedgeofCS,aconversionprocessbegins.
POWERSUPPLYPositivesupplypin.
Thispinshouldbeconnectedtoaquiet+2.
7Vto+5.
25Vsourceandbypassedto1VAGNDwitha1Fcapacitoranda0.
1Fmonolithiccapacitorlocatedwithin1cmofthepowerpin.
2GNDThegroundreturnforthesupplyandsignals.
PADGNDForpackagesuffixCISD(X)only,itisrecommendedthatthecenterpadshouldbeconnectedtoground.
AbsoluteMaximumRatings(1)(2)(3)AnalogSupplyVoltageVA0.
3Vto6.
5VVoltageonAnyAnalogPintoGND0.
3Vto(VA+0.
3V)VoltageonAnyDigitalPintoGND0.
3Vto6.
5VInputCurrentatAnyPin(4)±10mAPackageInputCurrent(4)±20mAPowerConsumptionatTA=25°CSee(5)ESDSusceptibility(6)HumanBodyModel3500VMachineModel300VJunctionTemperature+150°CStorageTemperature65°Cto+150°C(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlyforthetestconditionslisted.
Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
(3)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
(4)Whentheinputvoltageatanypinexceedsthepowersupply(thatis,VINVA),thecurrentatthatpinshouldbelimitedto10mA.
The20mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithaninputcurrentof10mAtotwo.
TheAbsoluteMaximumRatingspecificationdoesnotapplytotheVApin.
ThecurrentintotheVApinislimitedbytheAnalogSupplyVoltagespecification.
(5)Theabsolutemaximumjunctiontemperature(TJmax)forthisdeviceis150°C.
ThemaximumallowablepowerdissipationisdictatedbyTJmax,thejunction-to-ambientthermalresistance(θJA),andtheambienttemperature(TA),andcanbecalculatedusingtheformulaPDmax=(TJmaxTA)/θJA.
Thevaluesformaximumpowerdissipationlistedabovewillbereachedonlywhenthedeviceisoperatedinaseverefaultcondition(e.
g.
wheninputoroutputpinsaredrivenbeyondthepowersupplyvoltages,orthepowersupplypolarityisreversed).
Obviously,suchconditionsshouldalwaysbeavoided.
(6)Humanbodymodelis100pFcapacitordischargedthrougha1.
5kresistor.
Machinemodelis220pFdischargedthroughzeroohms.
OperatingRatings(1)(2)OperatingTemperatureRange40°C≤TA≤+85°CVASupplyVoltage+2.
7Vto+5.
25VDigitalInputPinsVoltageRange0.
3Vto5.
25V(regardlessofsupplyvoltage)AnalogInputPinsVoltageRange0VtoVAClockFrequency25kHzto20MHzSampleRateupto1Msps(1)AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotensurespecificperformancelimits.
Forensuredspecificationsandtestconditions,seetheElectricalCharacteristics.
Theensuredspecificationsapplyonlyforthetestconditionslisted.
Someperformancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions.
(2)AllvoltagesaremeasuredwithrespecttoGND=0V,unlessotherwisespecified.
Copyright2005–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:ADC101S021ADC101S021SNAS307G–JULY2005–REVISEDJANUARY2014www.
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comPackageThermalResistancePackageθJA6-leadWSON94°C/W6-leadSOT-23265°C/WSolderingprocessmustcomplywithReflowTemperatureProfilespecifications.
Refertohttp://www.
ti.
com/packaging.
(1)(1)Reflowtemperatureprofilesaredifferentforlead-freeandnon-lead-freepackages.
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comSNAS307G–JULY2005–REVISEDJANUARY2014ADC101S021ConverterElectricalCharacteristics(1)(2)ThefollowingspecificationsapplyforVA=+2.
7Vto5.
25V,fSCLK=1MHzto4MHz,fSAMPLE=50kspsto200ksps,CL=15pF,unlessotherwisenoted.
BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(2)STATICCONVERTERCHARACTERISTICSResolutionwithNoMissingCodesBits+0.
14LSB(max)VA=+2.
7to+3.
6V±0.
70.
13LSB(min)INLIntegralNon-Linearity+0.
14LSB(max)VA=+4.
75to+5.
25V±0.
70.
13LSB(min)+0.
12LSB(max)VA=+2.
7to+3.
6V±0.
60.
07LSB(min)DNLDifferentialNon-Linearity+0.
16LSB(min)VA=+4.
75to+5.
25V±0.
60.
09LSB(min)VA=+2.
7Vto+3.
6VVOFFOffsetError0.
09±0.
7LSB(max)VA=+4.
75to+5.
25VVA=+2.
7Vto+3.
6V0.
06GEGainError±1.
0LSB(max)VA=+4.
75to+5.
25V0.
27DYNAMICCONVERTERCHARACTERISTICSVA=+2.
7to5.
25VSINADSignal-to-NoisePlusDistortionRatio61.
560.
7dB(min)fIN=100kHz,0.
02dBFSVA=+2.
7to5.
25VSNRSignal-to-NoiseRatio61.
661dB(min)fIN=100kHz,0.
02dBFSVA=+2.
7to5.
25VTHDTotalHarmonicDistortion7972.
5dB(max)fIN=100kHz,0.
02dBFSVA=+2.
7to5.
25VSFDRSpurious-FreeDynamicRange7974dB(min)fIN=100kHz,0.
02dBFSVA=+2.
7to5.
25VENOBEffectiveNumberofBits9.
99.
8Bits(min)fIN=100kHz,0.
02dBFSIntermodulationDistortion,SecondVA=+5.
25V83dBOrderTermsfa=103.
5kHz,fb=113.
5kHzIMDIntermodulationDistortion,ThirdOrderVA=+5.
25V82dBTermsfa=103.
5kHz,fb=113.
5kHzVA=+5V11MHzFPBW-3dBFullPowerBandwidthVA=+3V8MHzANALOGINPUTCHARACTERISTICSVINInputRange0toVAVIDCLDCLeakageCurrent±1A(max)TrackMode30pFCINAInputCapacitanceHoldMode4pFDIGITALINPUTCHARACTERISTICSVA=+5.
25V2.
4V(min)VIHInputHighVoltageVA=+3.
6V2.
1V(min)VA=+5V0.
8V(max)VILInputLowVoltageVA=+3V0.
4V(max)IINInputCurrentVIN=0VorVA±0.
1±1A(max)CINDDigitalInputCapacitance24pF(max)(1)TestedlimitsarespecifiedtoTI'sAOQL(AverageOutgoingQualityLevel).
(2)Datasheetmin/maxspecificationlimitsareensuredbydesign,test,orstatisticalanalysis.
Copyright2005–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:ADC101S021ADC101S021SNAS307G–JULY2005–REVISEDJANUARY2014www.
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comADC101S021ConverterElectricalCharacteristics(1)(2)(continued)ThefollowingspecificationsapplyforVA=+2.
7Vto5.
25V,fSCLK=1MHzto4MHz,fSAMPLE=50kspsto200ksps,CL=15pF,unlessotherwisenoted.
BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
LimitsSymbolParameterConditionsTypicalUnits(2)DIGITALOUTPUTCHARACTERISTICSISOURCE=200AVA0.
07VA0.
2V(min)VOHOutputHighVoltageISOURCE=1mAVA0.
1VISINK=200A0.
030.
4V(max)VOLOutputLowVoltageISINK=1mA0.
1VIOZH,IOZLTRI-STATELeakageCurrent±0.
1±10A(max)COUTTRI-STATEOutputCapacitance24pF(max)OutputCodingStraight(Natural)BinaryPOWERSUPPLYCHARACTERISTICS2.
7V(min)VASupplyVoltage5.
25V(max)VA=+5.
25V,1.
72.
4mA(max)fSAMPLE=200kspsSupplyCurrent,NormalMode(Operational,CSlow)VA=+3.
6V,0.
651.
1mA(max)fSAMPLE=200kspsIAfSCLK=0MHz,VA=+5.
25V500nAfSAMPLE=0kspsSupplyCurrent,Shutdown(CShigh)VA=+5.
25V,fSCLK=4MHz,60AfSAMPLE=0kspsVA=+5.
25V8.
912.
6mW(max)PowerConsumption,NormalMode(Operational,CSlow)VA=+3.
6V2.
344.
0mW(max)fSCLK=0MHz,VA=+5.
25VPD2.
6WfSAMPLE=0kspsPowerConsumption,Shutdown(CShigh)VA=+5.
25V,fSCLK=4MHz,315WfSAMPLE=0kspsACELECTRICALCHARACTERISTICS1.
0MHz(min)fSCLKClockFrequency(3)4.
0MHz(max)50ksps(min)fSSampleRate(3)200ksps(max)40%(min)DCSCLKDutyCyclefSCLK=4MHz5060%(max)tACQMinimumTimeRequiredforAcquisition350ns(max)ThroughputTimeAcquisitionTime+ConversionTime20SCLKcyclestQUIET(4)50ns(min)tADApertureDelay3nstAJApertureJitter30ps(3)Thisisthefrequencyrangeoverwhichtheelectricalperformanceisensured.
ThedeviceisfunctionaloverawiderrangewhichisspecifiedunderOperatingRatings.
(4)MinimumQuietTimerequiredbybusrelinquishandthestartofthenextconversion.
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comSNAS307G–JULY2005–REVISEDJANUARY2014ADC101S021TimingSpecificationsThefollowingspecificationsapplyforVA=+2.
7Vto5.
25V,GND=0V,fSCLK=1.
0MHzto4.
0MHz,CL=25pF,fSAMPLE=50kspsto200ksps,BoldfacelimitsapplyforTA=TMINtoTMAX:allotherlimitsTA=25°C.
SymbolParameterConditionsTypicalLimitsUnitstCSMinimumCSPulseWidth10ns(min)tSUCStoSCLKSetupTime10ns(min)tENDelayfromCSUntilSDATATRI-STATEDisabled(1)20ns(max)VA=+2.
7Vto+3.
6V40ns(max)tACCDataAccessTimeafterSCLKFallingEdge(2)VA=+4.
75Vto+5.
25V20ns(max)tCLSCLKLowPulseWidth0.
4xtSCLKns(min)tCHSCLKHighPulseWidth0.
4xtSCLKns(min)VA=+2.
7Vto+3.
6V7ns(min)tHSCLKtoDataValidHoldTimeVA=+4.
75Vto+5.
25V5ns(min)25ns(max)VA=+2.
7Vto+3.
6V5ns(min)tDISSCLKFallingEdgetoSDATAHighImpedance(3)25ns(max)VA=+4.
75Vto+5.
25V5ns(min)tPOWER-Power-UpTimefromFullPower-Down1sUP(1)MeasuredwiththetimingtestcircuitshowninFigure2anddefinedasthetimetakenbytheoutputsignaltocross1.
0V.
(2)MeasuredwiththetimingtestcircuitshowninFigure2anddefinedasthetimetakenbytheoutputsignaltocross1.
0Vor2.
0V.
(3)tDISisderivedfromthetimetakenbytheoutputstochangeby0.
5VwiththetimingtestcircuitshowninFigure2.
Themeasurednumberisthenadjustedtoremovetheeffectsofchargingordischargingtheoutputcapacitance.
ThismeansthattDISisthetruebusrelinquishtime,independentofthebusloading.
TimingDiagramsFigure2.
TimingTestCircuitCopyright2005–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:ADC101S021ADC101S021SNAS307G–JULY2005–REVISEDJANUARY2014www.
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comFigure3.
ADC101S021SerialTimingDiagramSpecificationDefinitionsACQUISITIONTIMEisthetimerequiredtoacquiretheinputvoltage.
Thatis,itistimerequiredfortheholdcapacitortochargeuptotheinputvoltage.
AcquisitiontimeismeasuredbackwardsfromthefallingedgeofCSwhenthesignalissampledandthepartmovesfromtracktohold.
ThestartofthetimeintervalthatcontainsTACQisthe13thrisingedgeofSCLKofthepreviousconversionwhenthepartmovesfromholdtotrack.
Theusermustensurethatthetimebetweenthe13thrisingedgeofSCLKandthefallingedgeofthenextCSisnotlessthanTACQtomeetperformancespecifications.
APERTUREDELAYisthetimeafterthefallingedgeofCSwhentheinputsignalisacquiredorheldforconversion.
APERTUREJITTER(APERTUREUNCERTAINTY)isthevariationinaperturedelayfromsampletosample.
Aperturejittermanifestsitselfasnoiseintheoutput.
CONVERSIONTIMEisthetimerequired,aftertheinputvoltageisacquired,fortheADCtoconverttheinputvoltagetoadigitalword.
ThisisfromthefallingedgeofCSwhentheinputsignalissampledtothe16thfallingedgeofSCLKwhentheSDATAoutputgoesintoTRI-STATE.
DIFFERENTIALNON-LINEARITY(DNL)isthemeasureofthemaximumdeviationfromtheidealstepsizeof1LSB.
DUTYCYCLEistheratioofthetimethatarepetitivedigitalwaveformishightothetotaltimeofoneperiod.
ThespecificationherereferstotheSCLK.
EFFECTIVENUMBEROFBITS(ENOB,orEFFECTIVEBITS)isanothermethodofspecifyingSignal-to-NoiseandDistortionorSINAD.
ENOBisdefinedas(SINAD1.
76)/6.
02andsaysthattheconverterisequivalenttoaperfectADCofthis(ENOB)numberofbits.
FULLPOWERBANDWIDTHisameasureofthefrequencyatwhichthereconstructedoutputfundamentaldrops3dBbelowitslowfrequencyvalueforafullscaleinput.
GAINERRORisthedeviationofthelastcodetransition(111.
.
.
110)to(111.
.
.
111)fromtheideal(VREF1.
5LSB),afteradjustingforoffseterror.
INTEGRALNON-LINEARITY(INL)isameasureofthedeviationofeachindividualcodefromalinedrawnfromnegativefullscale(LSBbelowthefirstcodetransition)throughpositivefullscale(LSBabovethelastcodetransition).
Thedeviationofanygivencodefromthisstraightlineismeasuredfromthecenterofthatcodevalue.
INTERMODULATIONDISTORTION(IMD)isthecreationofadditionalspectralcomponentsasaresultoftwosinusoidalfrequenciesbeingappliedtotheADCinputatthesametime.
Itisdefinedastheratioofthepowerinthesecondandthirdorderintermodulationproductstothesumofthepowerinbothoftheoriginalfrequencies.
IMDisusuallyexpressedindB.
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comSNAS307G–JULY2005–REVISEDJANUARY2014MISSINGCODESarethoseoutputcodesthatwillneverappearattheADCoutputs.
TheADC101S021isensurednottohaveanymissingcodes.
OFFSETERRORisthedeviationofthefirstcodetransition(000.
.
.
000)to(000.
.
.
001)fromtheideal(i.
e.
GND+0.
5LSB).
SIGNALTONOISERATIO(SNR)istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofthesumofallotherspectralcomponentsbelowone-halfthesamplingfrequency,notincludingharmonicsord.
c.
SIGNALTONOISEPLUSDISTORTION(S/N+DorSINAD)Istheratio,expressedindB,ofthermsvalueoftheinputsignaltothermsvalueofalloftheotherspectralcomponentsbelowhalftheclockfrequency,includingharmonicsbutexcludingd.
c.
SPURIOUSFREEDYNAMICRANGE(SFDR)isthedifference,expressedindB,betweenthedesiredsignalamplitudetotheamplitudeofthepeakspuriousspectralcomponent,whereaspuriousspectralcomponentisanysignalpresentintheoutputspectrumthatisnotpresentattheinputandmayormaynotbeaharmonic.
TOTALHARMONICDISTORTION(THD)istheratio,expressedindBordBc,ofthermstotalofthefirstfiveharmoniccomponentsattheoutputtothermsleveloftheinputsignalfrequencyasseenattheoutput.
THDiscalculatedaswhereAf1istheRMSpoweroftheinputfrequencyattheoutputAf2throughAf6aretheRMSpowerinthefirst5harmonicfrequencies(1)THROUGHPUTTIMEistheminimumtimerequiredbetweenthestartoftwosuccessiveconversion.
Itistheacquisitiontimeplustheconversiontime.
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comTypicalPerformanceCharacteristicsTA=+25°C,fSAMPLE=50kspsto200ksps,fSCLK=1MHzto4MHz,fIN=100kHzunlessotherwisestated.
DNLINLfSCLK=1MHzfSCLK=1MHzFigure4.
Figure5.
DNLINLfSCLK=4MHzfSCLK=4MHzFigure6.
Figure7.
DNLINLvs.
vs.
ClockFrequencyClockFrequencyFigure8.
Figure9.
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comSNAS307G–JULY2005–REVISEDJANUARY2014TypicalPerformanceCharacteristics(continued)TA=+25°C,fSAMPLE=50kspsto200ksps,fSCLK=1MHzto4MHz,fIN=100kHzunlessotherwisestated.
SNRSINADvs.
vs.
ClockFrequencyClockFrequencyFigure10.
Figure11.
SFDRTHDvs.
vs.
ClockFrequencyClockFrequencyFigure12.
Figure13.
PowerConsumptionvs.
SpectralResponse,VA=5.
25VThroughput,fSCLK=4MHzfSCLK=4MHzFigure14.
Figure15.
Copyright2005–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11ProductFolderLinks:ADC101S021ADC101S021SNAS307G–JULY2005–REVISEDJANUARY2014www.
ti.
comAPPLICATIONSINFORMATIONADC101S021OperationTheADC101S021isasuccessive-approximationanalog-to-digitalconverterdesignedaroundacharge-redistributiondigital-to-analogconvertercore.
SimplifiedschematicsoftheADC101S021inbothtrackandholdmodesareshowninFigure16andFigure17,respectively.
InFigure16,thedeviceisintrackmode:switchSW1connectsthesamplingcapacitortotheinputandSW2balancesthecomparatorinputs.
ThedeviceisinthisstateuntilCSisbroughtlow,atwhichpointthedevicemovestotheholdmode.
Figure17showsthedeviceinholdmode:switchSW1connectsthesamplingcapacitortoground,maintainingthesampledvoltage,andswitchSW2unbalancesthecomparator.
Thecontrollogictheninstructsthecharge-redistributionDACtoaddorsubtractfixedamountsofchargefromthesamplingcapacitoruntilthecomparatorisbalanced.
Whenthecomparatorisbalanced,thedigitalwordsuppliedtotheDACisthedigitalrepresentationoftheanaloginputvoltage.
Thedevicemovesfromholdmodetotrackmodeonthe13thrisingedgeofSCLK.
Figure16.
ADC101S021inTrackModeFigure17.
ADC101S021inHoldModeUsingtheADC101S021TheserialinterfacetimingdiagramfortheADCisshowninFigure3.
CSischipselect,whichinitiatesconversionsontheADCandframestheserialdatatransfers.
SCLK(serialclock)controlsboththeconversionprocessandthetimingofserialdata.
SDATAistheserialdataoutpin,whereaconversionresultisfoundasaserialdatastream.
BasicoperationoftheADCbeginswithCSgoinglow,whichinitiatesaconversionprocessanddatatransfer.
SubsequentrisingandfallingedgesofSCLKwillbelabelledwithreferencetothefallingedgeofCS;forexample,"thethirdfallingedgeofSCLK"shallrefertothethirdfallingedgeofSCLKafterCSgoeslow.
AtthefallofCS,theSDATApincomesoutofTRI-STATEandtheconvertermovesfromtrackmodetoholdmode.
TheinputsignalissampledandheldforconversiononthefallingedgeofCS.
Theconvertermovesfromholdmodetotrackmodeonthe13thrisingedgeofSCLK(seeFigure3).
ItisatthispointthattheintervalfortheTACQspecificationbegins.
Atleast350nsmustpassbetweenthe13thrisingedgeofSCLKandthenextfallingedgeofCS.
TheSDATApinwillbeplacedbackintoTRI-STATEafterthe16thfallingedgeofSCLK,orattherisingedgeofCS,whicheveroccursfirst.
Afteraconversioniscompleted,thequiettime(tQUIET)mustbesatisfiedbeforebringingCSlowagaintobeginanotherconversion.
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comSNAS307G–JULY2005–REVISEDJANUARY2014SixteenSCLKcyclesarerequiredtoreadacompletesamplefromtheADC.
Thesamplebits(includingleadingortrailingzeroes)areclockedoutonfallingedgesofSCLK,andareintendedtobeclockedinbyareceiveronsubsequentrisingedgesofSCLK.
TheADCwillproducethreeleadingzerobitsonSDATA,followedbytendatabits,mostsignificantfirst.
Afterthedatabits,theADCwillclockouttwotrailingzeros.
IfCSgoeslowbeforetherisingedgeofSCLK,anadditional(fourth)zerobitmaybecapturedbythenextfallingedgeofSCLK.
DeterminingThroughputThroughputdependsonthefrequencyofSCLKandhowmuchtimeisallowedtoelapsebetweentheendofoneconversionandthestartofanother.
AtthemaximumspecifiedSCLKfrequency,themaximumensuredthroughputisobtainedbyusinga20SCLKframe.
AsshowninFigure3,theminimumallowedtimebetweenCSfallingedgesisdeterminedby1)12.
5SCLKsforHoldmode,2)thelargeroftwoquantities:eithertheminimumrequiredtimeforTrackmode(tACQ)or2.
5SCLKstofinishreadingtheresultand3)0,1/2or1SCLKpaddingtoensureanevennumberofSCLKcyclessothereisafallingSCLKedgewhenCSnextfalls.
Forexample,atthefastestrateforthisfamilyofparts,SCLKis20MHzand2.
5SCLKsare125ns,sotheminimumtimebetweenCSfallingedgesiscalculatedby:12.
5*50ns+350ns+0.
5*50ns=1000ns(2)(12.
5SCLKs+tACQ+1/2SCLK)whichcorrespondstoamaximumthroughputof1MSPS.
Attheslowestrateforthisfamily,SCLKis1MHz.
Usinga20cycleconversionframeasshowninFigure3yieldsa20μstimebetweenCSfallingedgesforathroughputof50KSPS.
Itispossible,however,tousefewerthan20clockcyclesprovidedthetimingparametersaremet.
Witha1MHzSCLK,thereare2500nsin2.
5SCLKcycles,whichisgreaterthantACQ.
Afterthelastdatabithascomeout,theclockwillneedonefullcycletoreturntoafallingedge.
ThusthetotaltimebetweenfallingedgesofCSis12.
5*1μs+2.
5*1μs+1*1μs=16μswhichisathroughputof62.
5KSPS.
ADC101S021TransferFunctionTheoutputformatoftheADCisstraightbinary.
CodetransitionsoccurmidwaybetweensuccessiveintegerLSBvalues.
TheLSBwidthfortheADCisVA/1024.
TheidealtransfercharacteristicisshowninFigure18.
Thetransitionfromanoutputcodeof0000000000toacodeof0000000001isat1/2LSB,oravoltageofVA/2048.
OthercodetransitionsoccuratstepsofoneLSB.
Figure18.
IdealTransferCharacteristicCopyright2005–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLinks:ADC101S021ADC101S021SNAS307G–JULY2005–REVISEDJANUARY2014www.
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comTypicalApplicationCircuitAtypicalapplicationoftheADCisshowninFigure19.
PowerisprovidedinthisexamplebytheTILP2950low-dropoutvoltageregulator,availableinavarietyoffixedandadjustableoutputvoltages.
ThepowersupplypinisbypassedwithacapacitornetworklocatedclosetotheADC.
BecausethereferencefortheADCisthesupplyvoltage,anynoiseonthesupplywilldegradedevicenoiseperformance.
Tokeepnoiseoffthesupply,useadedicatedlinearregulatorforthisdevice,orprovidesufficientdecouplingfromothercircuitrytokeepnoiseofftheADCsupplypin.
BecauseoftheADC'slowpowerrequirements,itisalsopossibletouseaprecisionreferenceasapowersupplytomaximizeperformance.
Thethree-wireinterfaceisshownconnectedtoamicroprocessororDSP.
Figure19.
TypicalApplicationCircuitAnalogInputsAnequivalentcircuitfortheADC'sinputisshowninFigure20.
DiodesD1andD2provideESDprotectionfortheanaloginputs.
Atnotimeshouldtheanaloginputgobeyond(VA+300mV)or(GND300mV),astheseESDdiodeswillbeginconducting,whichcouldresultinerraticoperation.
Forthisreason,theESDdiodesshouldnotbeusedtoclamptheinputsignal.
ThecapacitorC1inFigure20hasatypicalvalueof4pF,andismainlythepackagepincapacitance.
ResistorR1istheonresistanceofthetrack/holdswitch,andistypically500.
CapacitorC2istheADCsamplingcapacitorandistypically26pF.
TheADCwilldeliverbestperformancewhendrivenbyalow-impedancesourcetoeliminatedistortioncausedbythechargingofthesamplingcapacitance.
ThisisespeciallyimportantwhenusingtheADCtosampleACsignals.
Alsoimportantwhensamplingdynamicsignalsisananti-aliasingfilterFigure20.
EquivalentInputCircuitDigitalInputsandOutputsTheADCdigitalinputs(SCLKandCS)arenotlimitedbythesamemaximumratingsastheanaloginputs.
Thedigitalinputpinsareinsteadlimitedto+5.
25VwithrespecttoGND,regardlessofVA,thesupplyvoltage.
ThisallowstheADCtobeinterfacedwithawiderangeoflogiclevels,independentofthesupplyvoltage.
14SubmitDocumentationFeedbackCopyright2005–2014,TexasInstrumentsIncorporatedProductFolderLinks:ADC101S021ADC101S021www.
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comSNAS307G–JULY2005–REVISEDJANUARY2014ModesofOperationTheADChastwopossiblemodesofoperation:normalmode,andshutdownmode.
TheADCentersnormalmode(andaconversionprocessisbegun)whenCSispulledlow.
ThedevicewillentershutdownmodeifCSispulledhighbeforethetenthfallingedgeofSCLKafterCSispulledlow,orwillstayinnormalmodeifCSremainslow.
Onceinshutdownmode,thedevicewillstaythereuntilCSisbroughtlowagain.
Byvaryingtheratiooftimespentinthenormalandshutdownmodes,asystemmaytrade-offthroughputforpowerconsumption,withasamplerateaslowaszero.
NormalModeThefastestpossiblethroughputisobtainedbyleavingtheADCinnormalmodeatalltimes,sotherearenopower-updelays.
Tokeepthedeviceinnormalmodecontinuously,CSmustbekeptlowuntilafterthe10thfallingedgeofSCLKafterthestartofaconversion(rememberthataconversionisinitiatedbybringingCSlow).
IfCSisbroughthighafterthe10thfallingedge,butbeforethe16thfallingedge,thedevicewillremaininnormalmode,butthecurrentconversionwillbeaborted,andSDATAwillreturntoTRI-STATE(truncatingtheoutputword).
SixteenSCLKcyclesarerequiredtoreadallofaconversionwordfromthedevice.
AftersixteenSCLKcycleshaveelapsed,CSmaybeidledeitherhighorlowuntilthenextconversion.
IfCSisidledlow,itmustbebroughthighagainbeforethestartofthenextconversion,whichbeginswhenCSisagainbroughtlow.
AftersixteenSCLKcycles,SDATAreturnstoTRI-STATE.
Anotherconversionmaybestarted,aftertQUIEThaselapsed,bybringingCSlowagain.
ShutdownModeShutdownmodeisappropriateforapplicationsthateitherdonotsamplecontinuously,oritisacceptabletotradethroughputforpowerconsumption.
WhentheADCisinshutdownmode,alloftheanalogcircuitryisturnedoff.
Toentershutdownmode,aconversionmustbeinterruptedbybringingCShighanytimebetweenthesecondandtenthfallingedgesofSCLK,asshowninFigure21.
OnceCShasbeenbroughthighinthismanner,thedevicewillentershutdownmode,thecurrentconversionwillbeabortedandSDATAwillenterTRI-STATE.
IfCSisbroughthighbeforethesecondfallingedgeofSCLK,thedevicewillnotchangemode;thisistoavoidaccidentallychangingmodeasaresultofnoiseontheCSline.
Figure21.
EnteringShutdownModeFigure22.
EnteringNormalModeToexitshutdownmode,bringCSbacklow.
UponbringingCSlow,theADCwillbeginpoweringup(power-uptimeisspecifiedintheTimingSpecificationstable).
Thispower-updelayresultsinthefirstconversionresultbeingunusable.
Thesecondconversionperformedafterpower-up,however,isvalid,asshowninFigure22.
Copyright2005–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:ADC101S021ADC101S021SNAS307G–JULY2005–REVISEDJANUARY2014www.
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comIfCSisbroughtbackhighbeforethe10thfallingedgeofSCLK,thedevicewillreturntoshutdownmode.
ThisisdonetoavoidaccidentallyenteringnormalmodeasaresultofnoiseontheCSline.
Toexitshutdownmodeandremaininnormalmode,CSmustbekeptlowuntilafterthe10thfallingedgeofSCLK.
TheADCwillbefullypowered-upafter16SCLKcycles.
PowerManagementTheADCtakestimetopower-up,eitherafterfirstapplyingVA,orafterreturningtonormalmodefromshutdownmode.
Thiscorrespondstoone"dummy"conversionforanySCLKfrequencywithinthespecificationsinthisdocument.
Afterthisfirstdummyconversion,theADCwillperformconversionsproperly.
NotethatthetQUIETtimemuststillbeincludedbetweenthefirstdummyconversionandthesecondvalidconversion.
WhentheVAsupplyisfirstapplied,theADCmaypowerupineitherofthetwomodes:normalorshutdown.
Assuch,onedummyconversionshouldbeperformedafterstart-up,asdescribedinthepreviousparagraph.
Thepartmaythenbeplacedintoeithernormalmodeortheshutdownmode,asdescribedinSectionsNormalModeandShutdownMode.
WhentheADCisoperatedcontinuouslyinnormalmode,themaximumensuredthroughputisfSCLK/20atthemaximumspecifiedfSCLK.
ThroughputmaybetradedforpowerconsumptionbyrunningfSCLKatitsmaximumspecifiedrateandperformingfewerconversionsperunittime,raisingtheADCCSlineafterthe10thandbeforethe15thfallofSCLKbetweenconversions.
AplotoftypicalpowerconsumptionversusthroughputisshownintheTypicalPerformanceCharacteristicssection.
Tocalculatethepowerconsumptionforagiventhroughput,multiplythefractionoftimespentinthenormalmodebythenormalmodepowerconsumptionandaddthefractionoftimespentinshutdownmodemultipliedbytheshutdownmodepowerconsumption.
Notethatthecurveofpowerconsumptionvs.
throughputisessentiallylinear.
Thisisbecausethepowerconsumptionintheshutdownmodeissosmallthatitcanbeignoredforallpracticalpurposes.
PowerSupplyNoiseConsiderationsThechargingofanyoutputloadcapacitancerequirescurrentfromthepowersupply,VA.
Thecurrentpulsesrequiredfromthesupplytochargetheoutputcapacitancewillcausevoltagevariationsonthesupply.
Ifthesevariationsarelargeenough,theycoulddegradeSNRandSINADperformanceoftheADC.
Furthermore,dischargingtheoutputcapacitancewhenthedigitaloutputgoesfromalogichightoalogiclowwilldumpcurrentintothediesubstrate,whichisresistive.
Loaddischargecurrentswillcause"groundbounce"noiseinthesubstratethatwilldegradenoiseperformanceifthatcurrentislargeenough.
Thelargertheoutputcapacitance,themorecurrentflowsthroughthediesubstrateandthegreateristhenoisecoupledintotheanalogchannel,degradingnoiseperformance.
Tokeepnoiseoutofthepowersupply,keeptheoutputloadcapacitanceassmallaspractical.
Itisgoodpracticetousea100seriesresistorattheADCoutput,locatedasclosetotheADCoutputpinaspractical.
Thiswilllimitthechargeanddischargecurrentoftheoutputcapacitanceandmaintainnoiseperformance.
REVISIONHISTORYChangesfromRevisionF(March2013)toRevisionGPageChangedsentenceinthe"UsingtheADC101S021"section12ChangesfromRevisionE(March2013)toRevisionFPageChangedlayoutofNationalDataSheettoTIformat1616SubmitDocumentationFeedbackCopyright2005–2014,TexasInstrumentsIncorporatedProductFolderLinks:ADC101S021PACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesADC101S021CIMF/NOPBACTIVESOT-23DBV61000RoHS&GreenSNLevel-1-260C-UNLIM-40to85X08CADC101S021CIMFX/NOPBACTIVESOT-23DBV63000RoHS&GreenSNLevel-1-260C-UNLIM-40to85X08CADC101S021CISD/NOPBACTIVEWSONNGF61000RoHS&GreenSNLevel-1-260C-UNLIM-40to85X8CADC101S021CISDX/NOPBACTIVEWSONNGF64500RoHS&GreenSNLevel-1-260C-UNLIM-40to85X8C(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantADC101S021CIMF/NOPBSOT-23DBV61000178.
08.
43.
23.
21.
44.
08.
0Q3ADC101S021CIMFX/NOPBSOT-23DBV63000178.
08.
43.
23.
21.
44.
08.
0Q3ADC101S021CISD/NOPBWSONNGF61000178.
012.
42.
82.
51.
08.
012.
0Q1ADC101S021CISDX/NOPBWSONNGF64500330.
012.
42.
82.
51.
08.
012.
0Q1PACKAGEMATERIALSINFORMATIONwww.
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com20-Dec-2016PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)ADC101S021CIMF/NOPBSOT-23DBV61000210.
0185.
035.
0ADC101S021CIMFX/NOPBSOT-23DBV63000210.
0185.
035.
0ADC101S021CISD/NOPBWSONNGF61000210.
0185.
035.
0ADC101S021CISDX/NOPBWSONNGF64500367.
0367.
035.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com20-Dec-2016PackMaterials-Page2www.
ti.
comPACKAGEOUTLINEC0.
220.
08TYP0.
253.
02.
62X0.
951.
45MAX0.
150.
00TYP6X0.
500.
250.
60.
3TYP80TYP1.
9A3.
052.
75B1.
751.
45(1.
1)SOT-23-1.
45mmmaxheightDBV0006ASMALLOUTLINETRANSISTOR4214840/B03/2018NOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Bodydimensionsdonotincludemoldflashorprotrusion.
Moldflashandprotrusionshallnotexceed0.
15perside.
4.
Leads1,2,3maybewiderthanleads4,5,6forpackageorientation.
5.
RefernceJEDECMO-178.
0.
2CAB13452INDEXAREAPIN16GAGEPLANESEATINGPLANE0.
1CSCALE4.
000www.
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comEXAMPLEBOARDLAYOUT0.
07MAXARROUND0.
07MINARROUND6X(1.
1)6X(0.
6)(2.
6)2X(0.
95)(R0.
05)TYP4214840/B03/2018SOT-23-1.
45mmmaxheightDBV0006ASMALLOUTLINETRANSISTORNOTES:(continued)6.
PublicationIPC-7351mayhavealternatedesigns.
7.
Soldermasktolerancesbetweenandaroundsignalpadscanvarybasedonboardfabricationsite.
SYMMLANDPATTERNEXAMPLEEXPOSEDMETALSHOWNSCALE:15XPKG134526SOLDERMASKOPENINGMETALUNDERSOLDERMASKSOLDERMASKDEFINEDEXPOSEDMETALMETALSOLDERMASKOPENINGNONSOLDERMASKDEFINED(PREFERRED)SOLDERMASKDETAILSEXPOSEDMETALwww.
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6)2X(0.
95)6X(1.
1)6X(0.
6)(R0.
05)TYPSOT-23-1.
45mmmaxheightDBV0006ASMALLOUTLINETRANSISTOR4214840/B03/2018NOTES:(continued)8.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
9.
Boardassemblysitemayhavedifferentrecommendationsforstencildesign.
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