ONnip12

600MHz,32*16BufferedAnalogCrosspointSwitchDataSheetAD8104/AD8105Rev.
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TechnicalSupportwww.
analog.
comFEATURESHighchannelcount,32*16highspeed,nonblockingswitcharrayDifferentialorsingle-endedoperationDifferentialG=+1(AD8104)orG=+2(AD8105)PincompatiblewithAD8117/AD8118,32*32switcharraysFlexiblepowersuppliesSingle+5Vsupply,ordual±2.
5VsuppliesSerialorparallelprogrammingofswitcharrayHighimpedanceoutputdisableallowsconnectionofmultipledeviceswithminimalloadingonoutputbusExcellentvideoperformance>50MHz0.
1dBgainflatness0.
05%differentialgainerror(RL=150)0.
05°phaseerror(RL=150)ExcellentacperformanceBandwidth:600MHzSlewrate:1800V/sSettlingtime:2.
5nsto1%Lowpowerof1.
7WLowallhostilecrosstalkIP12IN12IP14IN14VPOSVPOSVPOSVPOSVPOSVPOSVPOSVPOSIP1IN1IP3IN3IP5IN5IP7IN7IP9IN9IP11IN11IP13IN13IP15IN15VPOSVPOSVPOSAC2322212019181716151413121110987654321AD8104/AD8105BOTTOMVIEW(NottoScale)06612-005Figure5.
304-BallBGAPinConfiguration(BottomView)DataSheetAD8104/AD8105Rev.
A|Page9of362122232019181716151413121110987654321ANCNCNCNCNCNCNCNCNCABNCNCNCNCNCNCNCNCNCBCVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGCDVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGDEEFFGGHHJJKKLLMMNNPPRRTTUUVVWWYVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGYAAVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGAAABOP10ON8OP8ON6OP6ON4OP4ON2OP2ABACVPOSVPOSVPOSIN16IP16IN18IP18IN20IP20IN22IP22IN24IP24IN26IP26IN28IP28IN30IP30VPOSVPOSVPOSVPOSVPOSVPOSVPOSVPOSIN17IP17IN19IP19IN21IP21IN23IP23IN25IP25IN27IP27IN29IP29IN31IP31VPOSVPOSVPOSVPOSVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGVNEGVPOSVPOSVPOSVPOSVPOSNCVPOSVNEGVOCMVDDDGNDRESETWED5D4D3D2D1D0VDDDGNDVOCMVNEGVPOSVPOSON15NCNCVNEGVOCMVOCMVNEGON14OP15NCNCVNEGVNEGVNEGVNEGOP14ON13NCNCVNEGVNEGVNEGVNEGON12OP13NCNCVNEGVNEGVNEGVNEGOP12ON11NCNCVNEGVNEGVNEGVNEGON10OP11ON9OP9ON7OP7ON5OP5ON3OP3ON1NCNCVNEGVOCMVOCMVNEGON0OP1NCVPOSVPOSVNEGVOCMVDDDGNDDATAOUTCLKDATAINSER/PARDGNDA3A2A1A0VDDDGNDVOCMVNEGVPOSOP0VPOSVPOSVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGVNEGVPOSVPOSVPOSVPOSVPOSVPOSVPOSIP0IN0IP2IN2IP4IN4IP6IN6IP8IN8IP10IN10IP12IN12IP14IN14VPOSVPOSVPOSVPOSVPOSVPOSVPOSVPOSIP1IN1IP3IN3IP5IN5IP7IN7IP9IN9IP11IN11IP13IN13IP15IN15VPOSVPOSVPOSAC2322212019181716151413121110987654321AD8104/AD8105TOPVIEW(NottoScale)06612-006Figure6.
304-BallBGAPinConfiguration(TopView)Table8.
PinFunctionDescriptionsPinNo.
MnemonicDescriptionA1VPOSAnalogPositivePowerSupply.
A2VPOSAnalogPositivePowerSupply.
A3VPOSAnalogPositivePowerSupply.
A4NCNoConnect.
A5NCNoConnect.
A6NCNoConnect.
A7NCNoConnect.
A8NCNoConnect.
A9NCNoConnect.
A10NCNoConnect.
A11NCNoConnect.
A12NCNoConnect.
A13NCNoConnect.
A14NCNoConnect.
A15NCNoConnect.
A16NCNoConnect.
PinNo.
MnemonicDescriptionA17NCNoConnect.
A18NCNoConnect.
A19NCNoConnect.
A20VPOSAnalogPositivePowerSupply.
A21VPOSAnalogPositivePowerSupply.
A22VPOSAnalogPositivePowerSupply.
A23VPOSAnalogPositivePowerSupply.
B1VPOSAnalogPositivePowerSupply.
B2VPOSAnalogPositivePowerSupply.
B3VPOSAnalogPositivePowerSupply.
B4VPOSAnalogPositivePowerSupply.
B5NCNoConnect.
B6NCNoConnect.
B7NCNoConnect.
B8NCNoConnect.
B9NCNoConnect.
AD8104/AD8105DataSheetRev.
A|Page10of36PinNo.
MnemonicDescriptionB10NCNoConnect.
B11NCNoConnect.
B12NCNoConnect.
B13NCNoConnect.
B14NCNoConnect.
B15NCNoConnect.
B16NCNoConnect.
B17NCNoConnect.
B18NCNoConnect.
B19NCNoConnect.
B20NCNoConnect.
B21VPOSAnalogPositivePowerSupply.
B22VPOSAnalogPositivePowerSupply.
B23VPOSAnalogPositivePowerSupply.
C1VPOSAnalogPositivePowerSupply.
C2VPOSAnalogPositivePowerSupply.
C3VPOSAnalogPositivePowerSupply.
C4VPOSAnalogPositivePowerSupply.
C5VNEGAnalogNegativePowerSupply.
C6VNEGAnalogNegativePowerSupply.
C7VNEGAnalogNegativePowerSupply.
C8VNEGAnalogNegativePowerSupply.
C9VNEGAnalogNegativePowerSupply.
C10VNEGAnalogNegativePowerSupply.
C11VPOSAnalogPositivePowerSupply.
C12VPOSAnalogPositivePowerSupply.
C13VPOSAnalogPositivePowerSupply.
C14VNEGAnalogNegativePowerSupply.
C15VNEGAnalogNegativePowerSupply.
C16VNEGAnalogNegativePowerSupply.
C17VNEGAnalogNegativePowerSupply.
C18VNEGAnalogNegativePowerSupply.
C19VNEGAnalogNegativePowerSupply.
C20VPOSAnalogPositivePowerSupply.
C21VPOSAnalogPositivePowerSupply.
C22VPOSAnalogPositivePowerSupply.
C23VPOSAnalogPositivePowerSupply.
D1VPOSAnalogPositivePowerSupply.
D2IP0InputNumber0,PositivePhase.
D3VPOSAnalogPositivePowerSupply.
D4VNEGAnalogNegativePowerSupply.
D5VOCMOutputCommon-ModeReferenceSupply.
D6VNEGAnalogNegativePowerSupply.
D7VNEGAnalogNegativePowerSupply.
D8VNEGAnalogNegativePowerSupply.
D9VNEGAnalogNegativePowerSupply.
D10VNEGAnalogNegativePowerSupply.
D11VPOSAnalogPositivePowerSupply.
D12VPOSAnalogPositivePowerSupply.
D13VPOSAnalogPositivePowerSupply.
D14VNEGAnalogNegativePowerSupply.
D15VNEGAnalogNegativePowerSupply.
PinNo.
MnemonicDescriptionD16VNEGAnalogNegativePowerSupply.
D17VNEGAnalogNegativePowerSupply.
D18VNEGAnalogNegativePowerSupply.
D19VOCMOutputCommon-ModeReferenceSupply.
D20VNEGAnalogNegativePowerSupply.
D21VPOSAnalogPositivePowerSupply.
D22VPOSAnalogPositivePowerSupply.
D23IN16InputNumber16,NegativePhase.
E1IP1InputNumber1,PositivePhase.
E2IN0InputNumber0,NegativePhase.
E3VNEGAnalogNegativePowerSupply.
E4VOCMOutputCommon-ModeReferenceSupply.
E20VOCMOutputCommon-ModeReferenceSupply.
E21VNEGAnalogNegativePowerSupply.
E22IN17InputNumber17,NegativePhase.
E23IP16InputNumber16,PositivePhase.
F1IN1InputNumber1,NegativePhase.
F2IP2InputNumber2,PositivePhase.
F3VNEGAnalogNegativePowerSupply.
F4VDDLogicPositivePowerSupply.
F20VDDLogicPositivePowerSupply.
F21VNEGAnalogNegativePowerSupply.
F22IP17InputNumber17,PositivePhase.
F23IN18InputNumber18,NegativePhase.
G1IP3InputNumber3,PositivePhase.
G2IN2InputNumber2,NegativePhase.
G3VNEGAnalogNegativePowerSupply.
G4DGNDLogicNegativePowerSupply.
G20DGNDLogicNegativePowerSupply.
G21VNEGAnalogNegativePowerSupply.
G22IN19InputNumber19,NegativePhase.
G23IP18InputNumber18,PositivePhase.
H1IN3InputNumber3,NegativePhase.
H2IP4InputNumber4,PositivePhase.
H3VNEGAnalogNegativePowerSupply.
H4DATAOUTControlPin:SerialDataOut.
H20RESETControlPin:SecondRankDataReset.
H21VNEGAnalogNegativePowerSupply.
H22IP19InputNumber19,PositivePhase.
H23IN20InputNumber20,NegativePhase.
J1IP5InputNumber5,PositivePhase.
J2IN4InputNumber4,NegativePhase.
J3VNEGAnalogNegativePowerSupply.
J4CLKControlPin:SerialDataClock.
J20UPDATEControlPin:SecondRankWriteStrobe.
J21VNEGAnalogNegativePowerSupply.
J22IN21InputNumber21,NegativePhase.
J23IP20InputNumber20,PositivePhase.
K1IN5InputNumber5,NegativePhase.
DataSheetAD8104/AD8105Rev.
A|Page11of36PinNo.
MnemonicDescriptionK2IP6InputNumber6,PositivePhase.
K3VNEGAnalogNegativePowerSupply.
K4DATAINControlPin:SerialDataIn.
K20WEControlPin:FirstRankWriteStrobe.
K21VNEGAnalogNegativePowerSupply.
K22IP21InputNumber21,PositivePhase.
K23IN22InputNumber22,NegativePhase.
L1IP7InputNumber7,PositivePhase.
L2IN6InputNumber6,NegativePhase.
L3VPOSAnalogPositivePowerSupply.
L4SER/PARControlPin:Serial/ParallelModeSelect.
L20D5ControlPin:InputAddressBit5.
L21VPOSAnalogPositivePowerSupply.
L22IN23InputNumber23,NegativePhase.
L23IP22InputNumber22,PositivePhase.
M1IN7InputNumber7,NegativePhase.
M2IP8InputNumber8,PositivePhase.
M3VPOSAnalogPositivePowerSupply.
M4DGNDLogicNegativePowerSupplyM20D4ControlPin:InputAddressBit4.
M21VPOSAnalogPositivePowerSupply.
M22IP23InputNumber23,PositivePhase.
M23IN24InputNumber24,NegativePhase.
N1IP9InputNumber9,PositivePhase.
N2IN8InputNumber8,NegativePhase.
N3VPOSAnalogPositivePowerSupply.
N4A3ControlPin:OutputAddressBit3.
N20D3ControlPin:InputAddressBit3.
N21VPOSAnalogPositivePowerSupply.
N22IN25InputNumber25,NegativePhase.
N23IP24InputNumber24,PositivePhase.
P1IN9InputNumber9,NegativePhase.
P2IP10InputNumber10,PositivePhase.
P3VNEGAnalogNegativePowerSupply.
P4A2ControlPin:OutputAddressBit2.
P20D2ControlPin:InputAddressBit2.
P21VNEGAnalogNegativePowerSupply.
P22IP25InputNumber25,PositivePhase.
P23IN26InputNumber26,NegativePhase.
R1IP11InputNumber11,PositivePhase.
R2IN10InputNumber10,NegativePhase.
R3VNEGAnalogNegativePowerSupply.
R4A1ControlPin:OutputAddressBit1.
R20D1ControlPin:InputAddressBit1.
R21VNEGAnalogNegativePowerSupply.
R22IN27InputNumber27,NegativePhase.
R23IP26InputNumber26,PositivePhase.
T1IN11InputNumber11,NegativePhase.
T2IP12InputNumber12,PositivePhase.
T3VNEGAnalogNegativePowerSupply.
T4A0ControlPin:OutputAddressBit0.
T20D0ControlPin:InputAddressBit0.
PinNo.
MnemonicDescriptionT21VNEGAnalogNegativePowerSupply.
T22IP27InputNumber27,PositivePhase.
T23IN28InputNumber28,NegativePhase.
U1IP13InputNumber13,PositivePhase.
U2IN12InputNumber12,NegativePhase.
U3VNEGAnalogNegativePowerSupply.
U4VDDLogicPositivePowerSupply.
U20VDDLogicPositivePowerSupply.
U21VNEGAnalogNegativePowerSupply.
U22IN29InputNumber29,NegativePhase.
U23IP28InputNumber28,PositivePhase.
V1IN13InputNumber13,NegativePhase.
V2IP14InputNumber14,PositivePhase.
V3VNEGAnalogNegativePowerSupply.
V4DGNDLogicNegativePowerSupply.
V20DGNDLogicNegativePowerSupply.
V21VNEGAnalogNegativePowerSupply.
V22IP29InputNumber29,PositivePhase.
V23IN30InputNumber30,NegativePhase.
W1IP15InputNumber15,PositivePhase.
W2IN14InputNumber14,NegativePhase.
W3VNEGAnalogNegativePowerSupply.
W4VOCMOutputCommon-ModeReferenceSupply.
W20VOCMOutputCommon-ModeReferenceSupply.
W21VNEGAnalogNegativePowerSupply.
W22IN31InputNumber31,NegativePhase.
W23IP30InputNumber30,PositivePhase.
Y1IN15InputNumber15,NegativePhase.
Y2VPOSAnalogPositivePowerSupply.
Y3VPOSAnalogPositivePowerSupply.
Y4VNEGAnalogNegativePowerSupply.
Y5VOCMOutputCommon-ModeReferenceSupply.
Y6VNEGAnalogNegativePowerSupply.
Y7VNEGAnalogNegativePowerSupply.
Y8VNEGAnalogNegativePowerSupply.
Y9VNEGAnalogNegativePowerSupply.
Y10VNEGAnalogNegativePowerSupply.
Y11VPOSAnalogPositivePowerSupply.
Y12VPOSAnalogPositivePowerSupply.
Y13VPOSAnalogPositivePowerSupply.
Y14VNEGAnalogNegativePowerSupply.
Y15VNEGAnalogNegativePowerSupply.
Y16VNEGAnalogNegativePowerSupply.
Y17VNEGAnalogNegativePowerSupply.
Y18VNEGAnalogNegativePowerSupply.
Y19VOCMOutputCommon-ModeReferenceSupply.
Y20VNEGAnalogNegativePowerSupply.
Y21VPOSAnalogPositivePowerSupply.
Y22IP31InputNumber31,PositivePhase.
AD8104/AD8105DataSheetRev.
A|Page12of36PinNo.
MnemonicDescriptionY23VPOSAnalogPositivePowerSupply.
AA1VPOSAnalogPositivePowerSupply.
AA2VPOSAnalogPositivePowerSupply.
AA3VPOSAnalogPositivePowerSupply.
AA4VPOSAnalogPositivePowerSupply.
AA5VNEGAnalogNegativePowerSupply.
AA6VNEGAnalogNegativePowerSupply.
AA7VNEGAnalogNegativePowerSupply.
AA8VNEGAnalogNegativePowerSupply.
AA9VNEGAnalogNegativePowerSupply.
AA10VNEGAnalogNegativePowerSupply.
AA11VPOSAnalogPositivePowerSupply.
AA12VPOSAnalogPositivePowerSupply.
AA13VPOSAnalogPositivePowerSupply.
AA14VNEGAnalogNegativePowerSupply.
AA15VNEGAnalogNegativePowerSupply.
AA16VNEGAnalogNegativePowerSupply.
AA17VNEGAnalogNegativePowerSupply.
AA18VNEGAnalogNegativePowerSupply.
AA19VNEGAnalogNegativePowerSupply.
AA20VPOSAnalogPositivePowerSupply.
AA21VPOSAnalogPositivePowerSupply.
AA22VPOSAnalogPositivePowerSupply.
AA23VPOSAnalogPositivePowerSupply.
AB1VPOSAnalogPositivePowerSupply.
AB2VPOSAnalogPositivePowerSupply.
AB3VPOSAnalogPositivePowerSupply.
AB4OP0OutputNumber0,PositivePhase.
AB5ON0OutputNumber0,NegativePhase.
AB6OP2OutputNumber2,PositivePhase.
AB7ON2OutputNumber2,NegativePhase.
AB8OP4OutputNumber4,PositivePhase.
AB9ON4OutputNumber4,NegativePhase.
AB10OP6OutputNumber6,PositivePhase.
AB11ON6OutputNumber6,NegativePhase.
AB12OP8OutputNumber8,PositivePhase.
AB13ON8OutputNumber8,NegativePhase.
PinNo.
MnemonicDescriptionAB14OP10OutputNumber10,PositivePhase.
AB15ON10OutputNumber10,NegativePhase.
AB16OP12OutputNumber12,PositivePhase.
AB17ON12OutputNumber12,NegativePhase.
AB18OP14OutputNumber14,PositivePhase.
AB19ON14OutputNumber14,NegativePhase.
AB20VPOSAnalogPositivePowerSupply.
AB21VPOSAnalogPositivePowerSupply.
AB22VPOSAnalogPositivePowerSupply.
AB23VPOSAnalogPositivePowerSupply.
AC1VPOSAnalogPositivePowerSupply.
AC2VPOSAnalogPositivePowerSupply.
AC3VPOSAnalogPositivePowerSupply.
AC4VPOSAnalogPositivePowerSupply.
AC5OP1OutputNumber1,PositivePhase.
AC6ON1OutputNumber1,NegativePhase.
AC7OP3OutputNumber3,PositivePhase.
AC8ON3OutputNumber3,NegativePhase.
AC9OP5OutputNumber5,PositivePhase.
AC10ON5OutputNumber5,NegativePhase.
AC11OP7OutputNumber7,PositivePhase.
AC12ON7OutputNumber7,NegativePhase.
AC13OP9OutputNumber9,PositivePhase.
AC14ON9OutputNumber9,NegativePhase.
AC15OP11OutputNumber11,PositivePhase.
AC16ON11OutputNumber11,NegativePhase.
AC17OP13OutputNumber13,PositivePhase.
AC18ON13OutputNumber13,NegativePhase.
AC19OP15OutputNumber15,PositivePhase.
AC20ON15OutputNumber15,NegativePhase.
AC21VPOSAnalogPositivePowerSupply.
AC22VPOSAnalogPositivePowerSupply.
AC23VPOSAnalogPositivePowerSupply.
DataSheetAD8104/AD8105Rev.
A|Page13of36TRUTHTABLEANDLOGICDIAGRAMTable9.
OperationTruthTableWEUPDATECLKDataInputDataOutputRESETSER/PAROperation/CommentXXXXX0XAsynchronousreset.
Alloutputsaredisabled.
Remainderoflogicin192-bitshiftregisterisunchanged.
1XDatai1Datai-19210Serialmode.
ThedataontheserialDATAINlineisloadedintotheserialregister.
ThefirstbitclockedintotheserialregisterappearsatDATAOUT192clockcycleslater.
0XXD0…D52A0…A33Notapplicableinparallelmode11Parallelmode.
ThedataonparallellinesD0toD5areloadedintotheshiftregisterlocationaddressedbyA0toA3.
10XXNotapplicableinparallelmode1XSwitchmatrixupdate.
Datainthe192-bitshiftregistertransfersintotheparallellatchesthatcontroltheswitcharray.
1XXXX11Nochangeinlogic.
1Datai:serialdata.
2D0…D5:databits.
3A0…A3:addressbits.
AD8104/AD8105DataSheetRev.
A|Page14of36D1D0QSDQCLKD0D1D2D3D4D5D1D0QSDQCLKD1D0QSDQCLKD1D0QSDQD1D0QSDQCLKD1D0QSDQCLKUPDATERESETA3A2A1A0D1D0QSDQOUT1ENOUT0ENOUT15ENOUT2ENOUT3ENOUT4ENOUT5ENOUT6ENOUT7ENOUT8ENOUT9ENOUT10ENOUT11ENOUT12ENOUT13ENOUT14END1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKDECODED1D0QSDQCLKSWITCHMATRIXOUTPUTENABLE51216DCLRQOUT0B0ENADCLRQOUT0B1ENADCLRQOUT0B2ENADCLRQOUT0B3ENADCLRQOUT0B4ENADCLRQOUT0ENENADCLRQOUT1B0ENADCLRQOUT14ENENADCLRQOUT15B0ENADCLRQOUT15B1ENADCLRQOUT15B2ENADCLRQOUT15B3ENADCLRQOUT15B4ENADCLRQOUT15ENENADATAOUT(SERIAL)PARALLELDATA(OUTPUTENABLE)SER/PARWEDATAIN(SERIAL)CLKOUTPUTADDRESS4TO16DECODERCLKCLK06612-007Figure7.
LogicDiagramDataSheetAD8104/AD8105Rev.
A|Page15of36I/OSCHEMATICSOPn,ONn06612-008Figure8.
AD8104/AD8105EnabledOutput(seealsoESDProtectionMap,Figure18)0.
4pF30k3.
4pF3.
4pFOPnONn06612-009Figure9.
AD8104/AD8105DisabledOutput(seealsoESDProtectionMap,Figure18)1.
3pF1.
3pF0.
3pFIPnINn250025002538253806612-010Figure10.
AD8104Receiver(seealsoESDProtectionMap,Figure18)250050750.
3pF1.
3pF1.
3pF25005075IPnINn06612-011Figure11.
AD8105Receiver(seealsoESDProtectionMap,Figure18)1.
3pF1.
3pF0.
3pFIPnINn2500250006612-012Figure12.
AD8104/AD8105ReceiverSimplifiedEquivalentCircuitWhenDrivingDifferentially1.
6pFIPnINn3.
33kAD8104G=+13.
76kAD8105G=+206612-013Figure13.
AD8104/AD8105ReceiverSimplifiedEquivalentCircuitWhenDrivingSingle-EndedVOCMVNEG06612-014Figure14.
VOCMInput(seealsoESDProtectionMap,Figure18)RESETDGNDVDD1k25k06612-015Figure15.
ResetInput(seealsoESDProtectionMap,Figure18)AD8104/AD8105DataSheetRev.
A|Page16of36CLK,SER/PAR,WE,UPDATE,DATAIN,A[3:0],D[5:0]DGND1k06612-016Figure16.
LogicInput(seealsoESDProtectionMap,Figure18)VDDDGNDDATAOUT06612-017Figure17.
LogicOutput(seealsoESDProtectionMap,Figure18)VPOSVNEGIPn,INn,OPn,ONn,VOCMVDDDGNDCLK,RESET,SER/PAR,WE,UPDATE,DATAIN,DATAOUT,A[3:0],D[5:0]06612-018Figure18.
ESDProtectionMapDataSheetAD8104/AD8105Rev.
A|Page17of36TYPICALPERFORMANCECHARACTERISTICSVS=±2.
5VatTA=25°C,RL,diff=200,VOCM=0V,differentialI/Omode,unlessotherwisenoted.
10–101000GAIN(dB)FREQUENCY(MHz)–202–8–6–4468110100AD8105AD810406612-019Figure19.
AD8104,AD8105SmallSignalFrequencyResponse,200mVp-p10–101000GAIN(dB)FREQUENCY(MHz)–202–8–6–4468110100AD8105AD810406612-020Figure20.
AD8104,AD8105LargeSignalFrequencyResponse,2Vp-p10–1001000NORMALIZEDGAIN(dB)FREQUENCY(MHz)86420–2–4–6–81001010pF5pF2pF0pF06612-021Figure21.
AD8104SmallSignalFrequencyResponsewithCapacitiveLoads,200mVp-p200054006612-022FREQUENCY(MHz)COUNT18016014012010080604020560580600620640660680700800Figure22.
AD81043dBBandwidthHistogram,OneDevice,All512Channels0–2.
0NORMALIZEDBANDWIDTHERROR(%)NUMBEROFENABLEDCHANNELS–1.
0–1.
5–0.
5128640216141006612-023Figure23.
AD8104BandwidthErrorvs.
EnabledChannels0–70–60–50–40–30–20–10300k1M10M100M1G2GCMR(dB)FREQUENCY(Hz)DIFFERENTIALOUT06612-024Figure24.
AD8104,AD8105Common-ModeRejectionAD8104/AD8105DataSheetRev.
A|Page18of36–15–950.
11000PSR(dB)FREQUENCY(MHz)–25–35–45–55–65–75–85100101VNEGAGGRESSORDIFFERENTIALOUTVPOSAGGRESSORVOCMAGGRESSOR06612-025Figure25.
AD8104PowerSupplyRejection10–500.
11000PSR(dB)FREQUENCY(MHz)50–5–30–35–40–45100101–10–15–20–25VNEGAGGRESSORVPOSAGGRESSORVOCMAGGRESSORSINGLE-ENDEDOUT06612-026Figure26.
AD8104PowerSupplyRejection,Single-Ended1401601800204060801001201k10k100k1MNOISESPECTRALDENSITY(nV/Hz)FREQUENCY(Hz)DIFFERENTIALOUTAD8105AD810406612-027Figure27.
AD8104,AD8105NoiseSpectralDensity,RTO0–100–60–80–40–20300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)DIFFERENTIALIN/OUT06612-028Figure28.
AD8104Crosstalk,OneAdjacentChannel300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)–100–80–60–40–200DIFFERENTIALIN/OUT06612-029Figure29.
AD8105Crosstalk,OneAdjacentChannel0–100–60–80–40–20300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)SINGLE-ENDEDIN/OUT06612-030Figure30.
AD8104Crosstalk,OneAdjacentChannel,Single-EndedDataSheetAD8104/AD8105Rev.
A|Page19of36300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)–100–80–60–40–200SINGLE-ENDEDIN/OUT06612-031Figure31.
AD8105Crosstalk,OneAdjacentChannel,Single-Ended0–120–60–80–100–40–20300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)06612-032DIFFERENTIALIN/OUTFigure32.
AD8104Crosstalk,AllHostile300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)–100–80–60–40–200DIFFERENTIALIN/OUT06612-033Figure33.
AD8105Crosstalk,AllHostile0–120–60–80–100–40–20300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)06612-034SINGLE-ENDEDIN/OUTFigure34.
AD8104Crosstalk,AllHostile,Single-Ended300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)–100–80–60–40–200SINGLE-ENDEDIN/OUT06612-035Figure35.
AD8105Crosstalk,AllHostile,Single-Ended0–100–60–80–40–20300k1M10M100M1G2GFEEDTHROUGH(dB)FREQUENCY(Hz)DIFFERENTIALIN/OUT06612-036Figure36.
AD8104Crosstalk,OffIsolationAD8104/AD8105DataSheetRev.
A|Page20of360–100–60–80–40–20300k1M10M100M1G2GFEEDTHROUGH(dB)FREQUENCY(Hz)SINGLE-ENDEDIN/OUT06612-037Figure37.
AD8104Crosstalk,OffIsolation,Single-Ended6000500002000100030004000300k1M10M100M1GINPUTIMPEDANCE()FREQUENCY(Hz)DIFFERENTIALINAD8105AD810406612-038Figure38.
AD8104,AD8105InputImpedance300k1M10M100M1GINPUTIMPEDANCE()FREQUENCY(Hz)050010001500200025003000350040004500AD8105AD8104SINGLE-ENDEDIN06612-039Figure39.
AD8104,AD8105InputImpedance,Single-Ended300002500020000150001000050000100k1M10M100M1GOUTPUTIMPEDANCE()FREQUENCY(Hz)DIFFERENTIALOUT06612-040Figure40.
AD8104,AD8105OutputImpedance,Disabled10000.
1100k1GOUTPUTIMPEDANCE()FREQUENCY(Hz)10110010M100M1M06612-041Figure41.
AD8104,AD8105OutputImpedance,Enabled0.
4–0.
4015VOUT(V,DIFF)TIME(ns)–0.
200.
2357911130.
3–0.
3–0.
10.
14681012141206612-042Figure42.
AD8104SmallSignalPulseResponse,200mVp-pDataSheetAD8104/AD8105Rev.
A|Page21of360.
20–0.
20015VOUT(V,SE)TIME(ns)–0.
1000.
10357911130.
15–0.
15–0.
050.
0546810121412N-CHANNELP-CHANNEL06612-043Figure43.
AD8104SmallSignalPulseResponse,Single-Ended,200mVp-p2.
0–2.
0015VOUT(V,DIFF)TIME(ns)–1.
001.
0357911131.
5–1.
5–0.
50.
54681012141206612-044Figure44.
AD8104LargeSignalPulseResponse,2Vp-p1.
0–1.
0015VOUT(V,SE)TIME(ns)–0.
60.
2357911130.
6–0.
2046810121412N-CHANNELP-CHANNEL–0.
40.
40.
8–0.
806612-045Figure45.
AD8104LargeSignalPulseResponse,Single-Ended,2Vp-p1.
5–1.
5–40120VOUT(V,DIFF)TIME(ns)1.
00.
50–0.
5–1.
03–3210–1–2100806040200–20VOUTUPDATEUPDATE(V)06612-046Figure46.
AD8104SwitchingTime2–40VOUT(V,DIFF)TIME(ns)10–1–2–3543215000–1000SLEWRATE(V/s)40003000200010000SLEWRATEVOUT06612-047Figure47.
AD8104LargeSignalRisingEdgeandSlewRate2–40VOUT(V,DIFF)1ns/DIV10–1–2–3543213500–2500SLEWRATE(V/s)25001500500–500–1500SLEWRATEVOUT06612-048Figure48.
AD8104LargeSignalFallingEdgeandSlewRateAD8104/AD8105DataSheetRev.
A|Page22of3650–40100OFFSET(mV)TEMPERATURE(C)43129080706050403020100–10–20–3006612-049Figure49.
AD8104VOSvs.
TemperaturewithAllOutputsEnabled50–20–0.
100.
10VOUT(mV,DIFF)TIME(s)403020100–100.
080.
060.
040.
020–0.
02–0.
04–0.
06–0.
0806612-050Figure50.
AD8104SwitchingTransient(Glitch)0.
020–0.
010–700700DIFFERENTIALGAINERROR(%)VIN,DIFF(mV)0.
0150.
0100.
0050–0.
005–500500300100–100–30006612-051Figure51.
AD8104Gainvs.
DCVoltage,CarrierFrequency=3.
58MHz,SubcarrierAmplitude=600mVp-p,Differential0.
014–0.
004DIFFERENTIALPHASEERROR(%)VIN,DIFF(mV)0.
0120.
0100.
0080.
0060.
0040.
0020–0.
002–700700–500500300100–100–30006612-052Figure52.
AD8104Phasevs.
DCVoltage,CarrierFrequency=3.
58MHz,SubcarrierAmplitude=600mVp-p,Differential2.
0–2.
0018VOUT(V,DIFF)TIME(ns)1614121086421.
51.
00.
50–0.
5–1.
0–1.
510pF5pF2pF0pF06612-053Figure53.
AD8104LargeSignalPulseResponsewithCapacitiveLoads0.
4–0.
4018VOUT(V,DIFF)TIME(ns)0.
30.
20.
10–0.
1–0.
2–0.
316141210864210pF5pF2pF0pF06612-054Figure54.
AD8104SmallSignalPulseResponsewithCapacitiveLoadsDataSheetAD8104/AD8105Rev.
A|Page23of361.
4–0.
2–50150VOUT(V,DIFF)TIME(ns)1.
21.
00.
80.
60.
40.
202.
8–0.
42.
42.
01.
61.
20.
80.
401301109070503010–10–30UPDATEVOUTUPDATE(V)06612-055Figure55.
AD8104EnableTime1.
4–0.
2–50150VOUT(V,DIFF)TIME(ns)1.
21.
00.
80.
60.
40.
202.
8–0.
42.
42.
01.
61.
20.
80.
401301109070503010–10–30VOUTUPDATEUPDATE(V)06612-056Figure56.
AD8104DisableTime0–0.
05–50100GAIN(dB)TEMPERATURE(°C)–250255075–0.
01–0.
02–0.
03–0.
0406612-057Figure57.
AD8104DCGainvs.
Temperature06612-058600100–3595IPOSANDINEGCURRENT(mA)TEMPERATURE(°C)IDDCURRENT(A)50040030020085035075065055045085756555453525155–5–15–25IDD(SERIALMODE)IDD(PARALLELMODE)IPOSANDINEG(ALLOUTPUTSENABLED)IPOSANDINEG(ALLOUTPUTSDISABLED)Figure58.
AD8104,AD8105QuiescentSupplyCurrentsvs.
Temperature06612-059360200116CHANNELSIPOSANDINEG(mA)IDD(A)340320300280260240220234567891011121314154004805606407208008809601040IPOS,INEGIDDSERIALIDDPARALLELFigure59.
AD8104,AD8105QuiescentSupplyCurrentsvs.
EnabledOutputs65–507OUTPUTERROR(%)TIME(ns)4536215545352515506050403020103.
25–0.
252.
752.
251.
751.
250.
750.
2503.
002.
502.
001.
501.
000.
50(V,DIFF)VOUTVIN(VOUT–VIN)/VOUT06612-060Figure60.
AD8104SettlingTimeAD8104/AD8105DataSheetRev.
A|Page24of365–507OUTPUT/INPUT(%)TIME(ns)654321–443210–1–2–306612-061Figure61.
AD8104SettlingTime(Zoom)2.
5–2.
50700VOUT(V,SE)TIME(ns)600500400300200100–1.
5–1.
0–2.
000.
5–0.
51.
52.
01.
0VINNVOUTNVOUTPVINP06612-062Figure62.
AD8104OverdriveRecovery,Single-Ended0700VOUT(V,SE)TIME(ns)600500400300200100–1.
5–2.
0–1.
000.
5–0.
51.
52.
01.
0VOUTPVINPVINNVOUTN06612-063Figure63.
AD8105OverdriveRecovery,Single-Ended–30–1001000DISTORTION(dBc)FREQUENCY(MHz)–90–80–70–60–50–400.
1101001VOUT=2Vp-p,DIFFSECONDHARMONICTHIRDHARMONIC06612-064Figure64.
AD8104HarmonicDistortionDataSheetAD8104/AD8105Rev.
A|Page25of36THEORYOFOPERATIONTheAD8104/AD8105arefullydifferentialcrosspointarrayswith16outputs,eachofwhichcanbeconnectedtoanyoneof32inputs.
Organizedbyoutputrow,32switchableinputtransconductancestagesareconnectedtoeachoutputbuffertoform32-to-1multiplexers.
Thereare16ofthesemultiplexers,eachwithitsinputswiredinparallel,foratotalarrayof512transconductancestagesformingamulticast-capablecrosspointswitch.
Decodinglogicforeachoutputselectsone(ornone)ofthetransconductancestagestodrivetheoutputstage.
Theenabledtransconductancestagedrivestheoutputstage,andfeedbackformsaclosed-loopamplifierwithadifferentialgainof+1(thedifferencebetweentheoutputvoltagesisequaltothedifferencebetweentheinputvoltages).
Asecondfeedbackloopcontrolsthecommon-modeoutputlevel,forcingtheaverageofthedifferentialoutputvoltagestomatchthevoltageontheVOCMreferencepin.
Althougheachoutputhasanindependentcommon-modecontrolloop,theVOCMreferenceiscommonfortheentirechip,andassuchneedstobedrivenwithalowimpedancetoavoidcrosstalk.
EachdifferentialinputtotheAD8104/AD8105isbufferedbyareceiver.
Thepurposeofthisreceiveristoprovideanextendedinputcommon-moderange,andtoremovethiscommonmodefromthesignalchain.
Liketheoutputmultiplexers,theinputreceiverhasbothadifferentialloopandacommon-modecontrolloop.
Amask-programmablefeedbacknetworksetstheclosed-loopdifferentialgain.
FortheAD8104,thisdifferentialgainis+1,andfortheAD8105,thisdifferentialgainis+2.
Thereceiverhasaninputstagethatdoesnotrespondtothecommonmodeofthesignal.
Thisarchitecture,alongwiththeattenuatingfeedbacknetwork,allowstheusertoapplyinputvoltagesthatextendfromrailtorail.
Excessdifferentialloopgainbandwidthproductreducestheeffectoftheclosed-loopgainonthebandwidthofthedevice.
TheoutputstageoftheAD8104/AD8105isdesignedforlowdifferentialgainandphaseerrorwhendrivingcompositevideosignals.
Italsoprovidesslewcurrentforfastpulseresponsewhendrivingcomponentvideosignals.
Unlikemanymulti-plexerdesigns,theserequirementsarebalancedsuchthatlargesignalbandwidthisverysimilartosmallsignalbandwidth.
Thedesignloadis150Ω,butprovisionsaremadetodriveloadsaslowas75Ωaslongason-chippowerdissipationlimitsarenotexceeded.
TheoutputsoftheAD8104/AD8105canbedisabledtominimizeon-chippowerdissipation.
Whendisabled,thereisafeedbacknetworkof25kΩbetweenthedifferentialoutputs.
ThishighimpedanceallowsmultipleICstobebussedtogetherwithoutadditionalbuffering.
Caremustbetakentoreduceoutputcapacitance,whichresultsinmoreovershootandfrequencydomainpeaking.
Aseriesofinternalamplifiersdriveinternalnodessuchthatawidebandhighimpedanceispresentedatthedisabledoutput,evenwhiletheoutputbusisunderlargesignalswings.
Whentheoutputsaredisabledanddrivenexternally,thevoltageappliedtothemshouldnotexceedthevalidoutputswingrangefortheAD8104/AD8105inordertokeeptheseinternalamplifiersintheirlinearrangeofoperation.
ApplyingexcessdifferentialvoltagestothedisabledoutputscancausedamagetotheAD8104/AD8105andshouldbeavoided(seetheAbsoluteMaximumRatingssectionforguidelines).
TheconnectionoftheAD8104/AD8105iscontrolledbyaflexibleTTL-compatiblelogicinterface.
Eitherparallelorserialloadingintoafirstrankoflatchespreprogramseachoutput.
Aglobalupdatesignalmovestheprogrammingdataintothesecondrankoflatches,simultaneouslyupdatingalloutputs.
Inserialmode,aserial-outpinallowsdevicestobedaisy-chainedtogetherforsingle-pinprogrammingofmultipleICs.
Apower-onresetpinisavailabletoavoidbusconflictsbydisablingalloutputs.
Thispower-onresetclearsthesecondrankoflatches,butdoesnotclearthefirstrankoflatches.
Inparallelmode,toquicklyclearthefirstrank,abroadcastparallelprogrammingfeatureisavailable.
Inserialmode,preprogrammingindividualinputsisnotpossibleandtheentireshiftregisterneedstobeflushed.
TheAD8104/AD8105canoperateonasingle+5Vsupply,poweringboththesignalpath(withtheVPOS/VNEGsupplypins),andthecontrollogicinterface(withtheVDD/DGNDsupplypins).
However,toeasilyinterfacetoground-referencedvideosignals,splitsupplyoperationispossiblewith±2.
5Vsupplies.
Inthiscase,aflexiblelogicinterfaceallowsthecontrollogicsupplies(VDD/DGND)toberunoff+2V/0Vto+5V/0Vwhilethecoreremainsonsplitsupplies.
Additionalflexibilityintheanalogoutputcommon-modelevelfacilitatesunequalsplitsupplies.
If+3V/–2Vsuppliesto+2V/–3Vsuppliesaredesired,theVOCMpincanstillbesetto0Vforground-referencedvideosignals.
AD8104/AD8105DataSheetRev.
A|Page26of36APPLICATIONSINFORMATIONPROGRAMMINGTheAD8104/AD8105havetwooptionsforchangingtheprogrammingofthecrosspointmatrix.
Inthefirstoption,aserialwordof192bitscanbeprovidedtoupdatetheentirematrixeachtime.
Thesecondoptionallowsforchangingtheprogrammingofasingleoutputviaaparallelinterface.
Theserialoptionrequiresfewersignals,butmoretime(clockcycles)forchangingtheprogramming,whiletheparallelprogrammingtechniquerequiresmoresignals,butcanchangeasingleoutputatatimeandrequiresfewerclockcyclestocompleteprogramming.
SerialProgrammingDescriptionTheserialprogrammingmodeusestheCLK,DATAIN,UPDATE,andSER/PARdevicepins.
ThefirststepistoassertalowonSER/PARinordertoenabletheserialprogrammingmode.
TheparallelclockWEshouldbeheldhighduringtheentireserialprogrammingoperation.
TheUPDATEsignalshouldbehighduringthetimethatdataisshiftedintotheserialportofthedevice.
AlthoughthedatastillshiftsinwhenUPDATEislow,thetransparent,asynchronouslatchesallowtheshiftingdatatoreachthematrix.
Thiscausesthematrixtotrytoupdatetoeveryintermediatestateasdefinedbytheshiftingdata.
ThedataatDATAINisclockedinateveryfallingedgeofCLK.
Atotalof192bitsmustbeshiftedintocompletetheprogram-ming.
Foreachofthe16outputs,therearefivebits(D0toD4)thatdeterminethesourceofitsinputfollowedbyonebit(D5)thatdeterminestheenabledstateoftheoutput.
IfD5islow(outputdisabled),thefiveassociatedbits(D0toD4)donotmatter,becausenoinputisswitchedtothatoutput.
Thesecomprisethefirst96bitsofDATAIN.
Theremaining96bitsofDATAINshouldbesettozero.
Ifastringof96zerosisnotsuffixedtothefirst96bitsofDATAIN,acertaintestmodeisemployedthatcancausethedevicetodrawupto40%moresupplycurrent.
Themostsignificantoutputaddressdata,theenablebit(D5),isshiftedinfirst,followedbytheinputaddress(D4toD0)enteredsequentiallywithD4firstandD0last.
Eachremainingoutputisprogrammedsequentially,untiltheleastsignificantoutputaddressdataisshiftedin.
Atthispoint,UPDATEcanbetakenlow,whichprogramsthedeviceaccordingtothedatathatwasjustshiftedin.
TheUPDATElatchesareasynchronousandwhenUPDATEislow,theyaretransparent.
IfmorethanoneAD8104/AD8105deviceistobeseriallyprogrammedinasystem,theDATAOUTsignalfromonedevicecanbeconnectedtotheDATAINofthenextdevicetoformaserialchain.
AlloftheCLK,UPDATE,andSER/PARpinsshouldbeconnectedinparallelandoperatedasdescribedpreviously.
TheserialdataisinputtotheDATAINpinofthefirstdeviceofthechain,anditripplesthroughtothelast.
Therefore,thedataforthelastdeviceinthechainshouldcomeatthebeginningoftheprogrammingsequence.
Thelengthoftheprogrammingsequenceis192bitstimesthenumberofdevicesinthechain.
ParallelProgrammingDescriptionWhenusingtheparallelprogrammingmode,itisnotnecessarytoreprogramtheentiredevicewhenmakingchangestothematrix.
Infact,parallelprogrammingallowsthemodificationofasingleoutputatatime.
BecausethistakesonlyoneWE/UPDATEcycle,significanttimesavingscanberealizedbyusingparallelprogramming.
OneimportantconsiderationinusingparallelprogrammingisthattheRESETsignaldoesnotresetallregistersintheAD8104/AD8105.
Whentakenlow,theRESETsignalonlysetseachoutputtothedisabledstate.
Thisishelpfulduringpower-uptoensurethattwoparalleloutputsarenotactiveatthesametime.
Afterinitialpower-up,theinternalregistersinthedevicegenerallyhaverandomdata,eventhoughtheRESETsignalhasbeenasserted.
Ifparallelprogrammingisusedtoprogramoneoutput,thenthatoutputisproperlyprogrammed,buttherestofthedevicehasarandomprogramstatedependingontheinternalregistercontentatpower-up.
Therefore,whenusingparallelprogramming,itisessentialthatalloutputsbeprogrammedtoadesiredstateafterpower-up.
Thisensuresthattheprogrammingmatrixisalwaysinaknownstate.
Fromthenon,parallelprogrammingcanbeusedtomodifyasingleoutputormoreatatime.
Insimilarfashion,ifUPDATEistakenlowafterinitialpower-up,therandompower-updataintheshiftregisterisprogrammedintothematrix.
Therefore,inordertopreventthecrosspointfrombeingprogrammedintoanunknownstate,donotapplyalowlogicleveltoUPDATEafterpowerisinitiallyapplied.
Programmingthefullshiftregisteronetimetoadesiredstate,byeitherserialorparallelprogrammingafterinitialpower-up,eliminatesthepossibilityofprogrammingthematrixtoanunknownstate.
Tochangetheprogrammingofanoutputviaparallelprogram-ming,SER/PARandUPDATEshouldbetakenhigh.
Theserialprogrammingclock,CLK,shouldbelefthighduringparallelprogramming.
Theparallelclock,WE,shouldstartinthehighstate.
The4-bitaddressoftheoutputtobeprogrammedshouldbeputonA0toA3.
Thefirstfivedatabits(D0toD4)shouldcontaintheinformationthatidentifiestheinputthatispro-grammedtotheoutputthatisaddressed.
Thesixthdatabit(D5)determinestheenabledstateoftheoutput.
IfD5islow(outputdisabled),thenthedataonD0toD4doesnotmatter.
Afterthedesiredaddressanddatasignalshavebeenestablished,theycanbelatchedintotheshiftregisterbyahightolowtransitionoftheWEsignal.
Thematrixisnotprogrammed,DataSheetAD8104/AD8105Rev.
A|Page27of36however,untiltheUPDATEsignalistakenlow.
ItisthuspossibletolatchinnewdataforseveraloralloftheoutputsfirstviasuccessivenegativetransitionsofWEwhileUPDATEisheldhigh,andthenhaveallthenewdatatakeeffectwhenUPDATEgoeslow.
Thistechniqueshouldbeusedwhenprogrammingthedeviceforthefirsttimeafterpower-upwhenusingparallelprogramming.
ResetWhenpoweringuptheAD8104/AD8105,itisusuallydesirabletohavetheoutputscomeupinthedisabledstate.
TheRESETpin,whentakenlow,causesalloutputstobeinthedisabledstate.
However,theUPDATEsignaldoesnotresetallregistersintheAD8104/AD8105.
Thisisimportantwhenoperatingintheparallelprogrammingmode.
RefertotheParallelProgrammingDescriptionsectionforinformationaboutprogramminginternalregistersafterpower-up.
Serialprogrammingprogramstheentirematrixeachtime;therefore,nospecialconsiderationsapply.
Sincethedataintheshiftregisterisrandomafterpower-up,itshouldnotbeusedtoprogramthematrix,orthematrixcanenterunknownstates.
Topreventthis,donotapplyalogiclowsignaltoUPDATEinitiallyafterpower-up.
Theshiftregistershouldfirstbeloadedwiththedesireddata,andthenUPDATEcanbetakenlowtoprogramthedevice.
TheRESETpinhasa20kΩpull-upresistortoVDDthatcanbeusedtocreateasimplepower-upresetcircuit.
AcapacitorfromRESETtogroundholdsRESETlowforsometimewhiletherestofthedevicestabilizes.
Thelowconditioncausesalltheoutputstobedisabled.
Thecapacitorthenchargesthroughthepull-upresistortothehighstate,thusallowingfullprogrammingcapabilityofthedevice.
BecausetheAD8104/AD8105haverandomdataintheinternalregistersatpower-up,thedevicemaypowerupinateststatewherethesupplycurrentislargerthantypical.
Therefore,theRESETpinshouldbeusedtodisablealloutputsandbringthedeviceoutofanytestmode.
OPERATINGMODESTheAD8104/AD8105hasfullydifferentialinputsandoutputs.
Theinputsandoutputscanalsobeoperatedinasingle-endedfashion.
Thispresentsseveraloptionsforcircuitconfigurationsthatrequiredifferentgainsandtreatmentofterminations,iftheyareused.
DifferentialInputEachdifferentialinputtotheAD8104/AD8105isappliedtoadifferentialreceiver.
Thesereceiversallowtheusertodrivetheinputswithadifferentialsignalwithanuncertaincommon-modevoltage,suchasfromaremotesourceovertwistedpair.
Thereceiversrespondonlytothedifferenceininputvoltages,andrestoresacommon-modevoltagesuitablefortheinternalsignalpath.
Noiseorcrosstalkthatispresentinbothinputsisrejectedbytheinputstage,asspecifiedbyitscommon-moderejectionratio(CMRR).
Differentialoperationoffersagreatnoisebenefitforsignalsthatarepropagatedoverdistanceinanoisyenvironment.
IN+VOCMIN–RGRGRCVRRFRFOUT–OUT+TOSWITCHMATRIX06612-065Figure65.
InputReceiverEquivalentCircuitThecircuitconfigurationusedbythedifferentialinputreceiversissimilartothatofseveralAnalogDevices,Inc.
general-purposedifferentialamplifiers,suchastheAD8131.
Itisavoltagefeedbackamplifierwithinternalgainsettingresistors.
Thearrangementoffeedbackmakesthedifferentialinputimped-anceappeartobe5kΩacrosstheinputs.
kΩ52,=*=GdmINRRThisimpedancecreatesasmalldifferentialterminationerroriftheuserdoesnotaccountforthe5kΩparallelelement,althoughthiserrorislessthan1%inmostcases.
Additionally,thesourceimpedancedrivingtheAD8104/AD8105appearsinparallelwiththeinternalgain-settingresistors,suchthattheremaybeagainerrorforsomevaluesofsourceresistance.
TheAD8104/AD8105areadjustedsuchthatitsgainsarecorrectwhendrivenbyaback-terminated75Ωsourceimpedanceateachinputphase(37.
5Ωeffectiveimpedancetogroundateachinputpin,or75Ωdifferentialsourceimpedanceacrosspairsofinputpins).
Ifadifferentsourceimpedanceispresented,thedifferentialgainoftheAD8104/AD8105canbecalculatedbySGFdmINOUT,dmdmRRRVVG+==,where:RG=2.
5kΩ.
RSistheusersingle-endedsourceresistance(suchas37.
5Ωforaback-terminated75Ωsource).
RF=2.
538kΩfortheAD8104and5.
075kΩfortheAD8105.
InthecaseoftheAD8104,SdmRG+=kΩ5.
2kΩ538.
2InthecaseoftheAD8105,SdmRG+=kΩ5.
2kΩ075.
5AD8104/AD8105DataSheetRev.
A|Page28of36Whenoperatingwithadifferentialinput,caremustbetakentokeepthecommonmode,oraverage,oftheinputvoltageswithinthelinearoperatingrangeoftheAD8104/AD8105receiver.
Thiscommon-moderangecanextendrail-to-rail,providedthedifferentialsignalswingissmallenoughtoavoidforwardbiasingtheESDdiodes(itissafesttokeepthecommonmodeplusdifferentialsignalexcursionswithinthesupplyvoltagesofthepart).
SeetheSpecificationssectionforguaranteedinputrange.
ThedifferentialoutputoftheAD8104/AD8105receiverislinearforapeakof1.
4Vofoutputvoltagedifference(1.
4VpeakinputdifferencefortheAD8104,and0.
7VpeakinputdifferencefortheAD8105).
Takingtheoutputdifferentially,usingthetwooutputphases,thisallows2.
8Vp-poflinearoutputsignalswing.
Beyondthislevel,thesignalpathcansaturateandlimitsthesignalswing.
Thisisnotadesiredoperation,asthesupplycurrentincreasesandthesignalpathisslowtorecoverfromclipping.
Theabsolutemaximumalloweddifferentialinputsignalislimitedbythelong-termreliabilityoftheinputstage.
ThelimitsintheAbsoluteMaximumRatingssectionshouldbeobservedinordertoavoiddegradingdeviceperformancepermanently.
RCVRAD8104OPnONnIPnINn505006612-066Figure66.
ExampleofInputDrivenDifferentiallySingle-EndedInputTheAD8104/AD8105inputreceiverscanbedrivensingle-endedly(unbalanced).
Fromthestandpointofthereceiver,thereisverylittledifferencebetweensignalsappliedpositiveandnegativeintwophasestotheinputpairvs.
asignalappliedtooneinputonlywiththeotherinputheldataconstantpotential.
Onesmalldifferenceisthatthecommonmodebetweentheinputpinsischangingifonlyoneinputismoving,andthereisaverysmallcommon-modetodifferentialconversiongaininthereceiverthataddsanadditionalgainerrortotheoutput(seethecommon-moderejectionratiofortheinputstageintheSpecificationssection).
Forlowfrequencies,thisgainerrorisnegligible.
Thecommon-moderejectionratiodegradeswithincreasingfrequency.
WhenoperatingtheAD8104/AD8105receiverssingle-endedly,theobservedinputresistanceateachinputpinislowerthaninthedifferentialinputcase,duetoafractionofthereceiverinternaloutputvoltageappearingasacommon-modesignalonitsinputterminals,bootstrappingthevoltageontheinputresistance.
Thissingle-endedinputresistancecanbecalculatedbytheequation)(21FSGFSGINRRRRRRRwhere:RG=2.
5kΩ.
RSistheusersingle-endedsourceresistance(suchas37.
5Ωforaback-terminated75Ωsource).
RF=2.
538kΩfortheAD8104and5.
075kΩfortheAD8105.
Inmostcases,asingle-endedinputsignalisreferredtomidsup-ply,typicallyground.
Inthiscase,theundrivendifferentialinputcanbeconnectedtoground.
Forbestdynamicperformanceandlowestoffsetvoltage,thisunusedinputshouldbeterminatedwithanimpedancematchingthedriveninput,insteadofbeingdirectlyshortedtoground.
Duetothedifferentialfeedbackofthereceiver,thereishighfrequencysignalcurrentintheundriveninputanditshouldbetreatedasasignallineintheboarddesign.
RCVROPnONnIPnINn7575(OR37.
5)AD810406612-067Figure67.
ExampleofInputDrivenSingle-EndedACCouplingofInputsItispossibletoaccoupletheinputsoftheAD8104/AD8105receiver.
Thisissimplifiedbecausethebiascurrentdoesnotneedtobesuppliedexternally.
AcapacitorinserieswiththeinputstotheAD8104/AD8105createsahigh-passfilterwiththeinputimpedanceofthedevice.
Thiscapacitorneedstobesizedsuchthatthecornerfrequencyislowenoughforfrequenciesofinterest.
DifferentialOutputBenefitsofDifferentialOperationTheAD8104/AD8105haveafullydifferentialswitchcore,withdifferentialoutputs.
Thetwooutputvoltagesmoveinoppositepolarity,withadifferentialfeedbackloopmaintainingafixedoutputstagedifferentialgainof+1(thedifferentoverallsignalpathgainsbetweentheAD8104andAD8105aresetintheinputstageforbestsignal-to-noiseratio).
Thisdifferentialoutputstageprovidesabenefitofcrosstalk-cancelingduetoparasiticcouplingfromoneoutputtoanotherbeingequalandoutofphase.
Additionally,iftheoutputofthedeviceisutilizedinadifferentialdesign,noise,crosstalk,andoffsetvoltagesgeneratedon-chipthatarecoupledequallyintobothoutputsarecancelledbythecommon-moderejectionratioofthenextdeviceinthesignalchain.
ByutilizingtheAD8104/AD8105outputsinadifferentialapplication,thebestpossiblenoiseandoffsetspecificationscanberealized.
DataSheetAD8104/AD8105Rev.
A|Page29of36DifferentialGainThespecifiedsignalpathgainoftheAD8104/AD8105referstoitsdifferentialgain.
FortheAD8104,thegainof+1meansthatthedifferenceinvoltagebetweenthetwooutputterminalsisequaltothedifferenceappliedbetweenthetwoinputterminals.
FortheAD8105,theratioofoutputdifferencevoltagetoappliedinputdifferencevoltageis+2.
Thecommonmode,oraveragevoltageofthepairofoutputsignalsissetbythevoltageontheVOCMpin.
Thisvoltageistypicallysettomidsupply(oftenground),butcanbemovedapproximately±0.
5Vtoaccommodatecaseswherethedesiredoutputcommon-modevoltagemaynotbemidsupply(asinthecaseofunequalsplitsupplies).
AdjustingVOCMcanlimitdifferentialswinginternallybelowthespecificationslistedinTable1.
Regardlessofthedifferentialgainofthedevice,thecommon-modegainfortheAD8104andAD8105is+1totheoutput.
ThismeansthatthecommonmodeoftheoutputvoltagesdirectlyfollowsthereferencevoltageappliedtotheVOCMinput.
TheVOCMreferenceisahighspeedsignalinput,commontoalloutputstagesonthedevice.
Itrequiresonlysmallamountsofbiascurrent,butnoiseappearingonthispinisbufferedtotheoutputsofalltheoutputstages.
Assuch,theVOCMnodeshouldbeconnectedtoalownoise,lowimpedancevoltagetoavoidbeingasourceofnoise,offset,andcrosstalkinthesignalpath.
TerminationTheAD8104/AD8105aredesignedtodrive150Ωoneachoutput(oraneffective300Ωdifferential),buttheoutputstageiscapableofsupplyingthecurrenttodrive100Ωloads(200Ωdifferential)overthespecifiedoperatingtemperaturerange.
Ifcareistakentoobservethemaximumpowerderatingcurves,theoutputstagecandrive75Ωloadswithslightlyreducedslewrateandbandwidth(aneffective150Ωdifferentialload).
Terminationattheloadendisrecommendedforbestsignalintegrity.
Thisloadterminationisoftenaresistortoagroundreferenceoneachindividualoutput.
ByterminatingtothesamevoltagelevelthatdrivestheVOCMreference,thepowerdissipationduetodcterminationcurrentisreduced.
Indifferentialsignalpaths,itisoftendesirabletoterminatedifferentially,withasingleresistoracrossthedifferentialoutputsattheloadend.
ThisisacceptablefortheAD8104/AD8105,butwhenthedeviceoutputsareplacedinadisabledstate,asmallamountofdcbiascurrentisrequirediftheoutputistopresentasahighimpedanceoveranexcursionofoutputbusvoltages.
IftheAD8104/AD8105disabledoutputsarefloated(orsimplytiedtogetherbyaresistor),internalnodessaturateandanincreaseindisabledoutputcurrentmaybeobserved.
Forbestpulseresponse,itisoftendesirabletoplaceaseriesresistorineachoutputtomatchthecharacteristicimpedanceandterminationoftheoutputtraceorcable.
Thisisknownasback-termination,andhelpsshortensettlingtimebyterminatingreflectedsignalswhendrivingaloadthatisnotaccuratelyterminatedattheloadend.
Asideeffectofback-terminationisanattenuationoftheoutputsignalbyafactoroftwo.
Inthiscase,againoftwoisusuallynecessarysomewhereinthesignalpathtorestorethesignal.
OPnONn5050100+–AD8104/AD810506612-068Figure68.
ExampleofBack-TerminatedDifferentialLoadSingle-EndedOutputUsageTheAD8104/AD8105outputpairscanbeusedsingle-endedly,takingonlyoneoutputandnotusingthesecond.
Thisisoftendesiredtoreducetheroutingcomplexityinthedesign,orbecauseasingle-endedloadisbeingdrivendirectly.
Thismodeofoperationproducesgoodresults,buthassomeshortcomingswhencomparedtotakingtheoutputdifferentially.
Whenobservingthesingle-endedoutput,noisethatiscommontobothoutputsappearsintheoutputsignal.
Thisincludesthermalnoiseinthechipbiasing,aswellascrosstalkthatiscoupledintothesignalpath.
Thiscomponentnoiseandcrosstalkisequalinbothoutputs,andassuchcanbeignoredbyadifferentialreceiverwithahighcommon-moderejectionratio.
However,whentakingtheoutputsingle-ended,thisnoiseispresentwithrespecttotheground(orVOCM)referenceandisnotrejected.
Whenobservingtheoutputsingle-ended,thedistributionofoffsetvoltagesappearsgreater.
Inthedifferentialcase,thedifferencebetweentheoutputswhenthedifferencebetweentheinputsiszeroisasmalldifferentialoffset.
Thisoffsetiscreatedfrommismatchesincomponentsofthesignalpath,whichmustbecorrectedbythefinitedifferentialloopgainofthedevice.
Inthesingle-endedcase,thisdifferentialoffsetisstillobserved,butanadditionaloffsetcomponentisalsorelevant.
Thisadditionalcomponentisthecommon-modeoffset,whichisadifferencebetweentheaverageoftheoutputsandtheVOCMreference.
Thisoffsetiscreatedbymismatchesthataffectthesignalpathinacommon-modemanner,andiscorrectedbythefinitecommon-modeloopgainofthedevice.
Adifferentialreceiverwouldrejectthiscommon-modeoffsetvoltage,butinthesingle-endedcase,thisoffsetisobservedwithrespecttothesignalground.
Thesingle-endedoutputsumshalfthedifferen-tialoffsetvoltageandallofthecommon-modeoffsetvoltageforanetincreaseinobservedoffset.
AD8104/AD8105DataSheetRev.
A|Page30of36Single-EndedGainTheAD8104/AD8105operateasaclosed-loopdifferentialamplifier.
Theprimarycontrolloopforcesthedifferencebetweentheoutputterminalstobearatioofthedifferencebetweentheinputterminals.
Oneoutputincreasesinvoltage,whiletheotherdecreasesanequalamounttomakethetotaldifferencecorrect.
TheaverageoftheseoutputvoltagesisforcedtobeequaltothevoltageontheVOCMterminalbyasecondcontrolloop.
IfonlyoneoutputterminalisobservedwithrespecttotheVOCMterminal,onlyhalfofthedifferencevoltageisobserved.
Thisimpliesthatwhenusingonlyoneoutputofthedevice,halfofthedifferentialgainisobserved.
AnAD8104takenwithsingle-endedoutputappearstohaveagainof+0.
5.
AnAD8105hasasingle-endedgainof+1.
Thisfactorofonehalfinthegainincreasesthenoiseofthedevicewhenreferredtotheinput,contributingtohighernoisespecificationsforsingle-endedoutputdesigns.
TerminationWhenoperatingtheAD8104/AD8105withasingle-endedoutput,thepreferredoutputterminationschemeisaresistorattheloadendtotheVOCMvoltage.
Aback-terminationcanbeused,atanadditionalcostofonehalfthesignalgain.
Insingle-endedoutputoperation,thecomplementaryphaseoftheoutputisnotused,andmayormaynotbeterminatedlocally.
Althoughtheunusedoutputcanbefloatedtoreducepowerdissipation,thereareseveralreasonsforterminatingtheunusedoutputwithaloadresistancematchedtotheloadonthesignaloutput.
Onecomponentofcrosstalkismagnetic,couplingbymutualinductancebetweenoutputpackagetracesandbondwiresthatcarryloadcurrent.
Inadifferentialdesign,thereiscouplingfromonepairofoutputstootheradjacentpairsofoutputs.
Thedifferentialnatureoftheoutputsignalsimultaneouslydrivesthecouplingfieldinonedirectionforonephaseoftheoutput,andinanoppositedirectionfortheotherphaseoftheoutput.
Thesemagneticfieldsdonotcoupleexactlyequalintoadjacentoutputpairsduetodifferentproximities,buttheydodestructivelycancelthecrosstalktosomeextent.
Iftheloadcurrentineachoutputisequal,thiscancellationisgreater,andlessadjacentcrosstalkisobserved(regardlessifthesecondoutputisactuallybeingused).
Asecondbenefitofbalancingtheoutputloadsinadifferentialpairistoreducefluctuationsincurrentrequirementsfromthepowersupply.
Insingle-endedloads,theloadcurrentsalternatefromthepositivesupplytothenegativesupply.
Thiscreatesaparasiticsignalvoltageinthesupplypinsduetothefiniteresistanceandinductanceofthesupplies.
Thissupplyfluctuationappearsascrosstalkinalloutputs,attenuatedbythepowersupplyrejectionratio(PSRR)ofthedevice.
Atlowfrequencies,thisisanegligiblecomponentofcrosstalk,butPSRRfallsoffasfrequencyincreases.
Withdifferential,balancedloads,asoneoutputdrawscurrentfromthepositivesupply,theotheroutputdrawscurrentfromthenegativesupply.
Whenthephasealternates,thefirstoutputdrawscurrentfromthenegativesupplyandthesecondfromthepositivesupply.
Theeffectisthatamoreconstantcurrentisdrawnfromeachsupply,suchthatthecrosstalk-inducingsupplyfluctuationisminimized.
Athirdbenefitofdrivingbalancedloadscanbeseenifoneconsidersthattheoutputpulseresponsechangesasloadchanges.
ThedifferentialsignalcontrolloopintheAD8104/AD8105forcesthedifferenceoftheoutputstobeafixedratiotothedifferenceoftheinputs.
Ifthetwooutputresponsesaredifferentduetoloading,thiscreatesadifferencethatthecontrolloopseesassignalresponseerror,anditattemptstocorrectthiserror.
Thisdistortstheoutputsignalfromtheidealresponseifthetwooutputswerebalanced.
OPnONn7575150AD8104/AD810506612-069Figure69.
ExampleofBack-TerminatedSingle-EndedLoadDecouplingThesignalpathoftheAD8104/AD8105isbasedonhighopen-loopgainamplifierswithnegativefeedback.
Dominant-polecompensationisusedon-chiptostabilizetheseamplifiersovertherangeofexpectedappliedswingandloadconditions.
Toguaranteethisdesignedstability,propersupplydecouplingisnecessarywithrespecttoboththedifferentialcontrolloopsandthecommon-modecontrolloopsofthesignalpath.
Signal-generatedcurrentsmustreturntotheirsourcesthroughlowimpedancepathsatallfrequenciesinwhichthereisstillloopgain(upto700MHzataminimum).
AwidebandparallelcapacitorarrangementisnecessarytoproperlydecoupletheAD8104/AD8105.
ThesignalpathcompensationcapacitorsintheAD8104/AD8105areconnectedtotheVNEGsupply.
Athighfrequencies,thislimitsthepowersupplyrejectionratio(PSRR)fromtheVNEGsupplytoalowervaluethanthatfromtheVPOSsupply.
Ifgivenachoice,anapplicationboardshouldbedesignedsuchthattheVNEGpowerissuppliedfromalowinductanceplane,subjecttoaleastamountofnoise.
TheVOCMshouldbeconsideredareferencepinandnotapowersupply.
Itisaninputtothehighspeed,highgaincommon-modecontrolloopofallreceiversandoutputdrivers.
Inthesingle-endedoutputsense,thereisnorejectionfromnoiseontheVOCMnettotheoutput.
Forthisreason,caremustbetakentoproducealownoiseVOCMsourceovertheentirerangeoffrequenciesofinterest.
Thisisnotonlyimportanttosingle-endedoperation,buttodifferentialDataSheetAD8104/AD8105Rev.
A|Page31of36operationaswell,asthereisacommon-mode-to-differentialgainconversionthatbecomesgreaterathigherfrequencies.
DuringoperationoftheAD8104/AD8105,transientcurrentsflowintotheVOCMnetfromtheamplifiercontrolloops.
Althoughthemagnitudeofthesecurrentsaresmall(10Ato20Aperoutput),theycancontributetocrosstalkiftheyflowthroughsignificantimpedances.
DrivingVOCMwithalowimpedance,lownoisesourceisdesirable.
PowerDissipationCalculationofPowerDissipation841585MAXIMUMPOWER(W)AMBIENTTEMPERATURE(°C)TJ=150°C76525354555657506612-070Figure70.
MaximumDiePowerDissipationvs.
AmbientTemperatureThecurveinFigure70wascalculatedfromJAAMBIENTMAXJUNCTIONMAXDTTPθ=,,(1)Asanexample,iftheAD8104/AD8105isenclosedinanenvi-ronmentat45°C(TA),thetotalon-chipdissipationunderallloadandsupplyconditionsmustnotbeallowedtoexceed7.
0W.
Whencalculatingon-chippowerdissipation,itisnecessarytoincludethermscurrentbeingdeliveredtotheload,multipliedbythermsvoltagedropontheAD8104/AD8105outputdevices.
Forasinusoidaloutput,theon-chippowerdissipationduetotheloadcanbeapproximatedby()RMSOUTPUTRMSUTPUTOPOSOUTPUTDIVVP,,,*=Fornonsinusoidaloutput,thepowerdissipationshouldbecalculatedbyintegratingtheon-chipvoltagedropmultipliedbytheloadcurrentoveroneperiod.
TheusercansubtractthequiescentcurrentfortheClassABoutputstagewhencalculatingtheloadedpowerdissipation.
Foreachoutputstagedrivingaload,subtractaquiescentpoweraccordingto()QUIESCENTOUTPUTNEGPOSOUTPUTDQIVVP,,*=whereIOUTPUT,QUIESCENT=1.
65mAforeachsingle-endedoutputpin.
Foreachdisabledoutput,thequiescentpowersupplycurrentinVPOSandVNEGdropsbyapproximately9mA.
QNPNQPNPVNEGVPOSVOUTPUTIOUTPUTIOUTPUT,QUIESCENTIOUTPUT,QUIESCENT06612-071Figure71.
SimplifiedOutputStageExampleFortheAD8104/AD8105,inanambienttemperatureof85°C,withall16outputsdriving1Vrmsinto100Ωloadsandpowersuppliesat±2.
5V,followthesesteps:1.
CalculatepowerdissipationofAD8104/AD8105usingdatasheetquiescentcurrents.
DisregardVDDcurrent,asitisinsignificant.
()()VNEGNEGVPOSPOSQUIESCENTDIVIVP*+*=,()()W7.
1mA340V5.
2mA340V5.
2,=*+*=QUIESCENTDP2.
Calculatepowerdissipationfromloads.
Foradifferentialoutputandground-referencedload,theoutputpowerissymmetricalineachoutputphase.
()RMSOUTPUTRMSOUTPUTPOSOUTPUTDIVVP,,,*=()()mW15Ω100/V1V1V5.
2,=*=OUTPUTDPThereare16outputpairs,or32outputcurrents.
W48.
0mW1532,=*=OUTPUTDnP3.
Subtractthequiescentoutputstagecurrentfornumberofloads(32inthisexample).
Theoutputstageiseitherstanding,ordrivingaload,butthecurrentonlyneedstobecountedonce(validforoutputvoltages>0.
5V).
()QUIESCENTOUTPUTNEGPOSOUTPUTDQIVVP,,*=()mW25.
8mA65.
1V)5.
2(V5.
2,=*=OUTPUTDQPThereare16outputpairs,or32outputcurrents.
W26.
0mW25.
832,=*=OUTPUTDQnP4.
Verifythatthepowerdissipationdoesnotexceedthemaximumallowedvalue.
OUTPUTDQOUTPUTDQUIESCENTDCHIPONDnPnPPP,,,,+=W9.
1W26.
0W48.
0W7.
1,=+=CHIPONDPFromFigure70orEquation1,thispowerdissipationisbelowthemaximumalloweddissipationforallambienttemperaturesuptoandincluding85°C.
AD8104/AD8105DataSheetRev.
A|Page32of36Short-CircuitOutputConditionsAlthoughthereisshort-circuitcurrentprotectionontheAD8104/AD8105outputs,theoutputcurrentcanreachvaluesof80mAintoagroundedoutput.
Anysustainedoperationwithtoomanyshortedoutputscanexceedthemaximumdietemperatureandcanresultindevicefailure(seetheAbsoluteMaximumRatingssection).
CrosstalkManysystems,suchasbroadcastvideoandKVMswitches,thathandlenumerousanalogsignalchannels,havestrictrequire-mentsforkeepingthevarioussignalsfrominfluencinganyoftheothersinthesystem.
Crosstalkisthetermusedtodescribethecouplingofthesignalsofothernearbychannelstoagivenchannel.
Whentherearemanysignalsincloseproximityinasystem,asisundoubtedlythecaseinasystemthatusestheAD8104/AD8105,thecrosstalkissuescanbequitecomplex.
Agoodunderstandingofthenatureofcrosstalkandsomedefinitionoftermsisrequiredinordertospecifyasystemthatusesoneormorecrosspointdevices.
TypesofCrosstalkCrosstalkcanbepropagatedbymeansofanyofthreemethods.
Thesefallintothecategoriesofelectricfield,magneticfield,andsharingofcommonimpedances.
Thissectionexplainstheseeffects.
Everyconductorcanbebotharadiatorofelectricfieldsandareceiverofelectricfields.
Theelectricfieldcrosstalkmechanismoccurswhentheelectricfieldcreatedbythetransmitterpropagatesacrossastraycapacitance(forexample,freespace),coupleswiththereceiver,andinducesavoltage.
Thisvoltageisanunwantedcrosstalksignalinanychannelthatreceivesit.
Currentsflowinginconductorscreatemagneticfieldsthatcirculatearoundthecurrents.
Thesemagneticfieldsthengeneratevoltagesinanyotherconductorswhosepathstheylink.
Theundesiredinducedvoltagesintheseotherchannelsarecrosstalksignals.
Thechannelsthatcrosstalkcanbesaidtohaveamutualinductancethatcouplessignalsfromonechanneltoanother.
Thepowersupplies,grounds,andothersignalreturnpathsofamultichannelsystemaregenerallysharedbythevariouschannels.
Whenacurrentfromonechannelflowsinoneofthesepaths,avoltagethatisdevelopedacrosstheimpedancebecomesaninputcrosstalksignalforotherchannelsthatsharethecommonimpedance.
Allthesesourcesofcrosstalkarevectorquantities;therefore,themagnitudescannotsimplybeaddedtogethertoobtainthetotalcrosstalk.
Infact,thereareconditionswheredrivingadditionalcircuitsinparallelinagivenconfigurationcanactuallyreducethecrosstalk.
BecausetheAD8104/AD8105arefullydifferentialdesigns,manysourcesofcrosstalkeitherdestructivelycancel,orarecommonmodetothesignalandcanberejectedbyadifferentialreceiver.
AreasofCrosstalkApracticalAD8104/AD8105circuitmustbemountedtosomesortofcircuitboardinordertoconnectittopowersuppliesandmeasurementequipment.
Greatcaremustbetakentocreateanevaluationboardthataddsminimumcrosstalktotheintrinsicdevice.
This,however,raisestheissuethatthecrosstalkofasystemisacombinationoftheintrinsiccrosstalkofthedevicesinadditiontothecircuitboardtowhichtheyaremounted.
Itisimportanttotrytoseparatethesetwoareaswhenattemptingtominimizetheeffectofcrosstalk.
Inaddition,crosstalkcanoccuramongtheinputstoacross-pointandamongtheoutputs.
Itcanalsooccurfrominputtooutput.
Techniquesarediscussedinthefollowingsectionsfordiagnosingwhichpartofasystemiscontributingtocrosstalk.
MeasuringCrosstalkCrosstalkismeasuredbyapplyingasignaltooneormorechannelsandmeasuringtherelativestrengthofthatsignalonadesiredselectedchannel.
ThemeasurementisusuallyexpressedasdBdownfromthemagnitudeofthetestsignal.
Thecrosstalkisexpressedby=)()(log2010sAsAXTTESTSELwhere:s=jω,theLaplacetransformvariable.
ASEL(s)istheamplitudeofthecrosstalkinducedsignalintheselectedchannel.
ATEST(s)istheamplitudeofthetestsignal.
Itcanbeseenthatcrosstalkisafunctionoffrequency,butnotafunctionofthemagnitudeofthetestsignal(tofirstorder).
Inaddition,thecrosstalksignalhasaphaserelativetothetestsignalassociatedwithit.
Anetworkanalyzerismostcommonlyusedtomeasurecrosstalkoverafrequencyrangeofinterest.
Itcanprovidebothmagnitudeandphaseinformationaboutthecrosstalksignal.
Asacrosspointsystemordevicegrowslarger,thenumberoftheoreticalcrosstalkcombinationsandpermutationscanbecomeextremelylarge.
Forexample,inthecaseofthe32*16matrixoftheAD8104/AD8105,lookatthenumberofcrosstalktermsthatcanbeconsideredforasinglechannel,forexample,theinputIN00.
IN00isprogrammedtoconnecttooneoftheAD8104/AD8105outputswherethemeasurementcanbemade.
First,thecrosstalktermsassociatedwithdrivingatestsignalintoeachoftheother31inputscanbemeasuredoneatatime,whileapplyingnosignaltoIN00.
Thenthecrosstalktermsassociatedwithdrivingaparalleltestsignalintoall31otherinputscanbemeasuredtwoatatimeinallpossiblecombinations,thenthreeatatime,andsoon,until,finally,DataSheetAD8104/AD8105Rev.
A|Page33of36thereisonlyonewaytodriveatestsignalintoall31otherinputsinparallel.
Eachofthesecasesislegitimatelydifferentfromtheothersandmayyieldauniquevalue,dependingontheresolutionofthemeasurementsystem,butitishardlypracticaltomeasureallthesetermsandthenspecifythem.
Inaddition,thisdescribesthecrosstalkmatrixforjustoneinputchannel.
Asimilarcrosstalkmatrixcanbeproposedforeveryotherinput.
Inaddition,ifthepossiblecombinationsandpermutationsforconnectinginputstotheotheroutputs(notusedformeasurement)aretakenintoconsideration,thenumbersratherquicklygrowtoastronomicalproportions.
IfalargercrosspointarrayofmultipleAD8104/AD8105devicesisconstructed,thenumbersgrowlargerstill.
Obviously,somesubsetofallthesecasesmustbeselectedtobeusedasaguideforapracticalmeasureofcrosstalk.
Onecommonmethodistomeasureall-hostilecrosstalk;thismeansthatthecrosstalktotheselectedchannelismeasuredwhileallothersystemchannelsaredriveninparallel.
Ingeneral,thisyieldstheworstcrosstalknumber,butthisisnotalwaysthecase,duetothevectornatureofthecrosstalksignal.
Otherusefulcrosstalkmeasurementsarethosecreatedbyonenearestneighbororbythetwonearestneighborsoneitherside.
Thesecrosstalkmeasurementsaregenerallyhigherthanthoseofmoredistantchannels,sotheycanserveasaworst-casemeasureforanyotherone-channelortwo-channelcrosstalkmeasurements.
InputandOutputCrosstalkCapacitivecouplingisvoltage-driven(dV/dt),butisgenerallyaconstantratio.
Capacitivecrosstalkisproportionaltoinputoroutputvoltage,butthisratioisnotreducedbysimplyreducingsignalswings.
Attenuationfactorsmustbechangedbychangingimpedances(loweringmutualcapacitance),ordestructivecancelingmustbeutilizedbysummingequalandoutofphasecomponents.
ForhighinputimpedancedevicessuchastheAD8104/AD8105,capacitancesgenerallydominateinput-generatedcrosstalk.
Inductivecouplingisproportionaltocurrent(dI/dt),andoftenscalesasaconstantratiowithsignalvoltage,butalsoshowsadependenceonimpedances(loadcurrent).
Inductivecouplingcanalsobereducedbyconstructivecancelingofequalandoutofphasefields.
Inthecaseofdrivinglowimpedancevideoloads,outputinductancescontributehighlytooutputcrosstalk.
TheflexibleprogrammingcapabilityoftheAD8104/AD8105canbeusedtodiagnosewhethercrosstalkisoccurringmoreontheinputsideortheoutputside.
Someexamplesareillustrative.
Agiveninputpair(IN07inthemiddleforthisexample)canbeprogrammedtodriveOUT07(alsointhemiddle).
TheinputstoIN07arejustterminatedtoground(via50Ωor75Ω)andnosignalisapplied.
Alltheotherinputsaredriveninparallelwiththesametestsignal(practicallyprovidedbyadistributionamplifier),withallotheroutputsexceptOUT07disabled.
SincegroundedIN07isprogrammedtodriveOUT07,nosignalshouldbepresent.
Anysignalthatispresentcanbeattributedtotheother31hostileinputsignals,becausenootheroutputsaredriven(theyarealldisabled).
Thus,thismethodmeasurestheallhostileinputcontributiontocrosstalkintoIN07.
Ofcourse,themethodcanbeusedforotherinputchannelsandcombinationsofhostileinputs.
Foroutputcrosstalkmeasurement,asingleinputchannelisdriven(IN00,forexample)andalloutputsotherthanagivenoutput(IN07inthemiddle)areprogrammedtoconnecttoIN00.
OUT07isprogrammedtoconnecttoIN15(farawayfromIN00),whichisterminatedtoground.
ThusOUT07shouldnothaveasignalpresentsinceitislisteningtoaquietinput.
AnysignalmeasuredattheOUT07canbeattributedtotheoutputcrosstalkoftheother16hostileoutputs.
Again,thismethodcanbemodifiedtomeasureotherchannelsandothercrosspointmatrixcombinations.
EffectofImpedancesonCrosstalkTheinputsidecrosstalkcanbeinfluencedbytheoutputimpedanceofthesourcesthatdrivetheinputs.
Thelowertheimpedanceofthedrivesource,thelowerthemagnitudeofthecrosstalk.
Thedominantcrosstalkmechanismontheinputsideiscapacitivecoupling.
Thehighimpedanceinputsdonothavesignificantcurrentflowtocreatemagneticallyinducedcrosstalk.
However,significantcurrentcanflowthroughtheinputtermi-nationresistorsandtheloopsthatdrivethem.
Thus,thePCboardontheinputsidecancontributetomagneticallycoupledcrosstalk.
Fromacircuitstandpoint,theinputcrosstalkmechanismlookslikeacapacitorcouplingtoaresistiveload.
Forlowfrequencies,themagnitudeofthecrosstalkisgivenby()sCRXTMS*=)(log2010where:RSisthesourceresistance.
CMisthemutualcapacitancebetweenthetestsignalcircuitandtheselectedcircuit.
sistheLaplacetransformvariable.
Fromtheprecedingequation,itcanbeobservedthatthiscrosstalkmechanismhasahigh-passnature;itcanalsobeminimizedbyreducingthecouplingcapacitanceoftheinputcircuitsandloweringtheoutputimpedanceofthedrivers.
Iftheinputisdrivenfroma75Ωterminatedcable,theinputcrosstalkcanbereducedbybufferingthissignalwithalowoutputimpedancebuffer.
AD8104/AD8105DataSheetRev.
A|Page34of36Ontheoutputside,thecrosstalkcanbereducedbydrivingalighterload.
AlthoughtheAD8104/AD8105arespecifiedwithexcellentdifferentialgainandphasewhendrivingastandard150Ωvideoload,thecrosstalkishigherthantheminimumobtainableduetothehighoutputcurrents.
ThesecurrentsinducecrosstalkviathemutualinductanceoftheoutputpinsandbondwiresoftheAD8104/AD8105.
Fromacircuitstandpoint,thisoutputcrosstalkmechanismlookslikeatransformerwithamutualinductancebetweenthewindingsthatdrivealoadresistor.
Forlowfrequencies,themagnitudeofthecrosstalkisgivenby*=LXYRsMXT10log20where:MXYisthemutualinductanceofOutputXtoOutputY.
RListheloadresistanceonthemeasuredoutput.
ThiscrosstalkmechanismcanbeminimizedbykeepingthemutualinductancelowandincreasingRL.
Themutualinductancecanbekeptlowbyincreasingthespacingoftheconductorsandminimizingtheirparallellength.
PCBLayoutExtremecaremustbeexercisedtominimizeadditionalcrosstalkgeneratedbythesystemcircuitboard(s).
Theareasthatmustbecarefullydetailedaregrounding,shielding,signalrouting,andsupplybypassing.
ThepackagingoftheAD8104/AD8105isdesignedtohelpkeepthecrosstalktoaminimum.
OntheBGAsubstrate,eachpairiscarefullyroutedtopredominatelycoupletoeachother,withshieldingtracesseparatingadjacentsignalpairs.
Theballgridarrayisarrangedsuchthatsimilarboardroutingcanbeachieved.
Onlytheoutertworowsareusedforsignals,suchthatviascanbeusedtotaketheinputrowstoalowersignalplaneifdesired.
Theinputandoutputsignalshaveminimumcrosstalkiftheyarelocatedbetweengroundplanesonlayersaboveandbelow,andseparatedbygroundinbetween.
ViasshouldbelocatedasclosetotheICaspossibletocarrytheinputsandoutputstotheinnerlayer.
Theinputandoutputsignalssurfaceattheinputterminationresistorsandtheoutputseriesback-terminationresistors.
Totheextentpossible,thesesignalsshouldalsobeseparatedassoonastheyemergefromtheICpackage.
PCBTerminationLayoutAsfrequenciesofoperationincrease,theimportanceofpropertransmissionlinesignalroutingbecomesmoreimportant.
ThebandwidthoftheAD8104/AD8105islargeenoughthatusinghighimpedanceroutingdoesnotprovideaflatin-bandfrequencyresponseforpracticalsignaltracelengths.
ItisnecessaryfortheusertochooseacharacteristicimpedancesuitablefortheapplicationandproperlyterminatetheinputandoutputsignalsoftheAD8104/AD8105.
Traditionally,videoapplicationshaveused75Ωsingle-endedenvironments.
RFapplicationsaregenerally50Ωsingle-ended(andboardmanufacturershavethemostexperiencewiththisapplication).
CAT-5cablingisusuallydrivenasdifferentialpairsof100Ωdifferentialimpedance.
Forflexibility,theAD8104/AD8105donotcontainon-chipterminationresistors.
Thisflexibilityinapplicationcomeswithsomeboardlayoutchallenges.
Thedistancebetweenthetermi-nationoftheinputtransmissionlineandtheAD8104/AD8105dieisahighimpedancestub,andcausesreflectionsoftheinputsignal.
Withsomesimplification,itcanbeshownthatthesereflectionscausepeakingoftheinputatregularintervalsinfrequency,dependentonthepropagationspeed(VP)ofthesignalinthechosenboardmaterialandthedistance(d)betweentheterminationresistorandtheAD8104/AD8105.
Ifthedistanceisgreatenough,thesepeakscanoccurin-band.
Infact,practicalexperienceshowsthatthesepeaksarenothigh-Q,andshouldbepushedouttothreeorfourtimesthedesiredbandwidthtoavoidaneffectonthesignal.
ForaboarddesignerusingFR4(VP=144*106m/s),thismeanstheAD8104/AD8105inputshouldbeplacednofartherthan1.
5cmaftertheterminationresistors,andpreferablyshouldbeplacedevencloser.
TheBGAsubstrateroutinginsidetheAD8104/AD8105isapproximately1cminlengthandaddstothestublength,so1.
5cmPCBroutingequatestod=2.
5*102minthecalculations.
()dVnfPPEAK412*+=wheren={0,1,2,3,…}.
Insomecases,itisdifficulttoplacetheterminationclosetotheAD8104/AD8105duetospaceconstraints,differentialrouting,andlargeresistorfootprints.
ApreferablesolutioninthiscaseistomaintainacontrolledtransmissionlinepasttheAD8104/AD8105inputsandterminatetheendoftheline.
Thisisknownasfly-bytermination.
TheinputimpedanceoftheAD8104/AD8105islargeenoughandstublengthinsidethepackageissmallenoughthatthisworkswellinpractice.
Implementationoffly-byinputterminationoftenincludesbringingthesignalinononeroutinglayer,thenpassingthroughafilledviaundertheAD8104/AD8105inputball,thenbackouttoterminationonanothersignallayer.
Inthiscase,caremustbetakentotiethereferencegroundplanestogethernearthesignalviaifthesignallayersarereferencedtodifferentgroundplanes.
OPnONnIPnINn75AD8104/AD810506612-072Figure72.
Fly-ByInputTermination,GroundsfortheTwoTransmissionLinesShownMustbeTiedTogetherClosetotheINnPinDataSheetAD8104/AD8105Rev.
A|Page35of36IfmultipleAD8104/AD8105devicesaretobedriveninparallel,afly-byinputterminationschemeisveryuseful,butthedistancefromeachAD8104/AD8105inputtothedriveninputtransmis-sionlineisastubthatshouldbeminimizedinlengthandparasiticsusingthediscussedguidelines.
WhendrivingtheAD8104/AD8105single-endedly,theundriveninputisoftenterminatedwitharesistancetobalancetheinputstage.
Itcanbeseenthatbyterminatingtheundriveninputwitharesistorofonehalfthecharacteristicimpedance,theinputstageisperfectlybalanced(37.
5Ω,forexample,tobalancethetwoparallel75Ωterminationsonthedriveninput).
However,duetothefeedbackintheinputreceiver,thereishighspeedsignalcurrentleavingtheundriveninput.
Toterminatethishighspeedsignal,propertransmissionlinetechniquesshouldbeused.
Onesolutionistoadjustthetracewidthtocreateatransmissionlineofhalfthecharacteristicimpedanceandterminatethefarendwiththisresistance(37.
5Ωina75Ωsystem).
Thisisnotoftenpracticalastracewidthsbecomelarge.
Inmostcases,thebestpracticalsolutionistoplacethehalf-characteristicimpedanceresistorascloseaspossible(preferablylessthan1.
5cmaway)andtoreducetheparasiticsofthestub(byremovingthegroundplaneunderthestub,forexample).
Ineithercase,thedesignermustdecideifthelayoutcomplexitycreatedbyabalanced,terminatedsolutionispreferabletosimplygroundingtheundriveninputattheballwithnotrace.
Althoughtheexamplesdiscussedsofarareforinputtermina-tion,thetheoryissimilarforoutputback-termination.
TakingtheAD8104/AD8105asanidealvoltagesource,anydistanceofroutingbetweentheAD8104/AD8105andaback-terminationresistorisanimpedancemismatchthatpotentiallycreatesreflections.
Forthisreason,back-terminationresistorsshouldalsobeplacedclosetotheAD8104/AD8105.
Inpractice,becauseback-terminationresistorsareserieselements,theycanbeplacedclosetotheAD8104/AD8105outputs.
AD8104/AD8105DataSheetRev.
A|Page36of36OUTLINEDIMENSIONS*COMPLIANTTOJEDECSTANDARDSMO-192-BAN-2WITHTHEEXCEPTIONTOPACKAGEHEIGHT.
DETAILAABCDEFGHJKLMNPRTUVWYAAABAC135791115171921231346810122161820221427.
94BSCSQBOTTOMVIEWA1CORNERINDEXAREA1.
27BSCTOPVIEW31.
00BSCSQBALLA1INDICATOR0.
10MIN0.
700.
630.
561.
070.
990.
92COPLANARITY0.
200.
900.
750.
60SEATINGPLANEBALLDIAMETERDETAILA*1.
765MAX022206-A0.
25MIN(4)Figure73.
304-BallBallGridArray,ThermallyEnhanced[BGA_ED](BP-304)DimensionsshowninmillimetersORDERINGGUIDEModel1TemperatureRangePackageDescriptionPackageOptionAD8104ABPZ40°Cto+85°C304-BallBallGridArray,ThermallyEnhanced[BGA_ED]BP-304AD8105ABPZ40°Cto+85°C304-BallBallGridArray,ThermallyEnhanced[BGA_ED]BP-3041Z=RoHSCompliantPart.
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