OUT26ip12

600MHz,32*32Buffered,AnalogCrosspointSwitchDataSheetAD8117/AD8118Rev.
BDocumentFeedbackInformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.
However,noresponsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorotherrightsofthirdpartiesthatmayresultfromitsuse.
Specificationssubjecttochangewithoutnotice.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofAnalogDevices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
OneTechnologyWay,P.
O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:781.
329.
47002007–2016AnalogDevices,Inc.
Allrightsreserved.
TechnicalSupportwww.
analog.
comFEATURESHighchannelcount,32*32highspeed,nonblockingswitcharrayDifferentialorsingle-endedoperationDifferentialG=+1(AD8117)orG=+2(AD8118)FlexiblepowersuppliesSingle+5Vsupply,ordual±2.
5VsuppliesSerialorparallelprogrammingofswitcharrayHighimpedanceoutputdisableallowsconnectionofmultipledeviceswithminimalloadingonoutputbusExcellentvideoperformance>50MHz0.
1dBgainflatness0.
05%/0.
05°differentialgain/phaseerror(RL=150Ω)ExcellentacperformanceBandwidth:600MHzSlewrate:1800V/μsSettlingtime:2.
5nsto1%Lowpowerof2.
5WLowallhostilecrosstalkIP12IN12IP14IN14VPOSVPOSVPOSVPOSVPOSVPOSVPOSVPOSIP1IN1IP3IN3IP5IN5IP7IN7IP9IN9IP11IN11IP13IN13IP15IN15VPOSVPOSVPOSAC2322212019181716151413121110987654321AD8117/AD8118BOTTOMVIEW(NottoScale)06365-005Figure5.
304-BallBGA_EDPinConfiguration,BottomViewDataSheetAD8117/AD8118Rev.
B|Page9of362322212019181716151413121110987654321AON21OP23ON23OP25ON25OP27ON27OP29ON29ABOP22ON22OP24ON24OP26ON26OP28ON28OP30BCVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGCDVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGDEEFFGGHHJJKKLLMMNNPPRRTTUUVVWWYVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGYAAVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGAAABOP10ON8OP8ON6OP6ON4OP4ON2OP2ABACVPOSVPOSVPOSIN16IP16IN18IP18IN20IP20IN22IP22IN24IP24IN26IP26IN28IP28IN30IP30VPOSVPOSVPOSVPOSVPOSVPOSVPOSVPOSIN17IP17IN19IP19IN21IP21IN23IP23IN25IP25IN27IP27IN29IP29IN31IP31VPOSVPOSVPOSVPOSVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGVNEGVPOSVPOSVPOSVPOSVPOSOP16VPOSVNEGVOCMVDDDGNDRESETWED5D4D3D2D1D0VDDDGNDVOCMVNEGVPOSVPOSON15OP17ON16VNEGVOCMVOCMVNEGON14OP15ON17OP18VNEGVNEGVNEGVNEGOP14ON13OP19ON18VNEGVNEGVNEGVNEGON12OP13ON19OP20VNEGVNEGVNEGVNEGOP12ON11OP21ON20VNEGVNEGVNEGVNEGON10OP11ON9OP9ON7OP7ON5OP5ON3OP3ON1OP31ON30VNEGVOCMVOCMVNEGON0OP1ON31VPOSVPOSVNEGVOCMVDDDGNDDATAOUTCLKDATAINSER/PARA4A3A2A1A0VDDDGNDVOCMVNEGVPOSOP0VPOSVPOSVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGVNEGVPOSVPOSVPOSVNEGVNEGVNEGVNEGVNEGVNEGVPOSVPOSVPOSVPOSVPOSVPOSVPOSIP0IN0IP2IN2IP4IN4IP6IN6IP8IN8IP10IN10IP12IN12IP14IN14VPOSVPOSVPOSVPOSVPOSVPOSVPOSVPOSIP1IN1IP3IN3IP5IN5IP7IN7IP9IN9IP11IN11IP13IN13IP15IN15VPOSVPOSVPOSAC2322212019181716151413121110987654321AD8117/AD8118TOPVIEW(NottoScale)06365-006Figure6.
304-BallBGA_EDPinConfiguration,TopViewTable8.
304-BallBGA_ED,PinFunctionDescriptionPinNo.
MnemonicDescriptionA1VPOSAnalogPositivePowerSupply.
A2VPOSAnalogPositivePowerSupply.
A3VPOSAnalogPositivePowerSupply.
A4ON31OutputNumber31,NegativePhase.
A5OP31OutputNumber31,PositivePhase.
A6ON29OutputNumber29,NegativePhase.
A7OP29OutputNumber29,PositivePhase.
A8ON27OutputNumber27,NegativePhase.
A9OP27OutputNumber27,PositivePhase.
A10ON25OutputNumber25,NegativePhase.
A11OP25OutputNumber25,PositivePhase.
A12ON23OutputNumber23,NegativePhase.
A13OP23OutputNumber23,PositivePhase.
A14ON21OutputNumber21,NegativePhase.
A15OP21OutputNumber21,PositivePhase.
PinNo.
MnemonicDescriptionA16ON19OutputNumber19,NegativePhase.
A17OP19OutputNumber19,PositivePhase.
A18ON17OutputNumber17,NegativePhase.
A19OP17OutputNumber17,PositivePhase.
A20VPOSAnalogPositivePowerSupply.
A21VPOSAnalogPositivePowerSupply.
A22VPOSAnalogPositivePowerSupply.
A23VPOSAnalogPositivePowerSupply.
B1VPOSAnalogPositivePowerSupply.
B2VPOSAnalogPositivePowerSupply.
B3VPOSAnalogPositivePowerSupply.
B4VPOSAnalogPositivePowerSupply.
B5ON30OutputNumber30,NegativePhase.
B6OP30OutputNumber30,PositivePhase.
B7ON28OutputNumber28,NegativePhase.
AD8117/AD8118DataSheetRev.
B|Page10of36PinNo.
MnemonicDescriptionB8OP28OutputNumber28,PositivePhase.
B9ON26OutputNumber26,NegativePhase.
B10OP26OutputNumber26,PositivePhase.
B11ON24OutputNumber24,NegativePhase.
B12OP24OutputNumber24,PositivePhase.
B13ON22OutputNumber22,NegativePhase.
B14OP22OutputNumber22,PositivePhase.
B15ON20OutputNumber20,NegativePhase.
B16OP20OutputNumber20,PositivePhase.
B17ON18OutputNumber18,NegativePhase.
B18OP18OutputNumber18,PositivePhase.
B19ON16OutputNumber16,NegativePhase.
B20OP16OutputNumber16,PositivePhase.
B21VPOSAnalogPositivePowerSupply.
B22VPOSAnalogPositivePowerSupply.
B23VPOSAnalogPositivePowerSupply.
C1VPOSAnalogPositivePowerSupply.
C2VPOSAnalogPositivePowerSupply.
C3VPOSAnalogPositivePowerSupply.
C4VPOSAnalogPositivePowerSupply.
C5VNEGAnalogNegativePowerSupply.
C6VNEGAnalogNegativePowerSupply.
C7VNEGAnalogNegativePowerSupply.
C8VNEGAnalogNegativePowerSupply.
C9VNEGAnalogNegativePowerSupply.
C10VNEGAnalogNegativePowerSupply.
C11VPOSAnalogPositivePowerSupply.
C12VPOSAnalogPositivePowerSupply.
C13VPOSAnalogPositivePowerSupply.
C14VNEGAnalogNegativePowerSupply.
C15VNEGAnalogNegativePowerSupply.
C16VNEGAnalogNegativePowerSupply.
C17VNEGAnalogNegativePowerSupply.
C18VNEGAnalogNegativePowerSupply.
C19VNEGAnalogNegativePowerSupply.
C20VPOSAnalogPositivePowerSupply.
C21VPOSAnalogPositivePowerSupply.
C22VPOSAnalogPositivePowerSupply.
C23VPOSAnalogPositivePowerSupply.
D1VPOSAnalogPositivePowerSupply.
D2IP0InputNumber0,PositivePhase.
D3VPOSAnalogPositivePowerSupply.
D4VNEGAnalogNegativePowerSupply.
D5VOCMOutputCommon-ModeReferenceSupply.
D6VNEGAnalogNegativePowerSupply.
D7VNEGAnalogNegativePowerSupply.
D8VNEGAnalogNegativePowerSupply.
D9VNEGAnalogNegativePowerSupply.
D10VNEGAnalogNegativePowerSupply.
D11VPOSAnalogPositivePowerSupply.
D12VPOSAnalogPositivePowerSupply.
PinNo.
MnemonicDescriptionD13VPOSAnalogPositivePowerSupply.
D14VNEGAnalogNegativePowerSupply.
D15VNEGAnalogNegativePowerSupply.
D16VNEGAnalogNegativePowerSupply.
D17VNEGAnalogNegativePowerSupply.
D18VNEGAnalogNegativePowerSupply.
D19VOCMOutputCommon-ModeReferenceSupply.
D20VNEGAnalogNegativePowerSupply.
D21VPOSAnalogPositivePowerSupply.
D22VPOSAnalogPositivePowerSupply.
D23IN16InputNumber16,NegativePhase.
E1IP1InputNumber1,PositivePhase.
E2IN0InputNumber0,NegativePhase.
E3VNEGAnalogNegativePowerSupply.
E4VOCMOutputCommon-ModeReferenceSupply.
E20VOCMOutputCommon-ModeReferenceSupply.
E21VNEGAnalogNegativePowerSupply.
E22IN17InputNumber17,NegativePhase.
E23IP16InputNumber16,PositivePhase.
F1IN1InputNumber1,NegativePhase.
F2IP2InputNumber2,PositivePhase.
F3VNEGAnalogNegativePowerSupply.
F4VDDLogicPositivePowerSupply.
F20VDDLogicPositivePowerSupply.
F21VNEGAnalogNegativePowerSupply.
F22IP17InputNumber17,PositivePhase.
F23IN18InputNumber18,NegativePhase.
G1IP3InputNumber3,PositivePhase.
G2IN2InputNumber2,NegativePhase.
G3VNEGAnalogNegativePowerSupply.
G4DGNDLogicNegativePowerSupply.
G20DGNDLogicNegativePowerSupply.
G21VNEGAnalogNegativePowerSupply.
G22IN19InputNumber19,NegativePhase.
G23IP18InputNumber18,PositivePhase.
H1IN3InputNumber3,NegativePhase.
H2IP4InputNumber4,PositivePhase.
H3VNEGAnalogNegativePowerSupply.
H4DATAOUTControlPin:SerialDataOut.
H20RESETControlPin:SecondRankDataReset.
H21VNEGAnalogNegativePowerSupply.
H22IP19InputNumber19,PositivePhase.
H23IN20InputNumber20,NegativePhase.
J1IP5InputNumber5,PositivePhase.
J2IN4InputNumber4,NegativePhase.
J3VNEGAnalogNegativePowerSupply.
J4CLKControlPin:SerialDataClock.
J20UPDATEControlPin:SecondRankWriteStrobe.
J21VNEGAnalogNegativePowerSupply.
J22IN21InputNumber21,NegativePhase.
DataSheetAD8117/AD8118Rev.
B|Page11of36PinNo.
MnemonicDescriptionJ23IP20InputNumber20,PositivePhase.
K1IN5InputNumber5,NegativePhase.
K2IP6InputNumber6,PositivePhase.
K3VNEGAnalogNegativePowerSupply.
K4DATAINControlPin:SerialDataIn.
K20WEControlPin:FirstRankWriteStrobe.
K21VNEGAnalogNegativePowerSupply.
K22IP21InputNumber21,PositivePhase.
K23IN22InputNumber22,NegativePhase.
L1IP7InputNumber7,PositivePhase.
L2IN6InputNumber6,NegativePhase.
L3VPOSAnalogPositivePowerSupply.
L4SER/PARControlPin:Serial/ParallelModeSelect.
L20D5ControlPin:InputAddressBit5.
L21VPOSAnalogPositivePowerSupply.
L22IN23InputNumber23,NegativePhase.
L23IP22InputNumber22,PositivePhase.
M1IN7InputNumber7,NegativePhase.
M2IP8InputNumber8,PositivePhase.
M3VPOSAnalogPositivePowerSupply.
M4A4ControlPin:OutputAddressBit4.
M20D4ControlPin:InputAddressBit4.
M21VPOSAnalogPositivePowerSupply.
M22IP23InputNumber23,PositivePhase.
M23IN24InputNumber24,NegativePhase.
N1IP9InputNumber9,PositivePhase.
N2IN8InputNumber8,NegativePhase.
N3VPOSAnalogPositivePowerSupply.
N4A3ControlPin:OutputAddressBit3.
N20D3ControlPin:InputAddressBit3.
N21VPOSAnalogPositivePowerSupply.
N22IN25InputNumber25,NegativePhase.
N23IP24InputNumber24,PositivePhase.
P1IN9InputNumber9,NegativePhase.
P2IP10InputNumber10,PositivePhase.
P3VNEGAnalogNegativePowerSupply.
P4A2ControlPin:OutputAddressBit2.
P20D2ControlPin:InputAddressBit2.
P21VNEGAnalogNegativePowerSupply.
P22IP25InputNumber25,PositivePhase.
P23IN26InputNumber26,NegativePhase.
R1IP11InputNumber11,PositivePhase.
R2IN10InputNumber10,NegativePhase.
R3VNEGAnalogNegativePowerSupply.
R4A1ControlPin:OutputAddressBit1.
R20D1ControlPin:InputAddressBit1.
R21VNEGAnalogNegativePowerSupply.
R22IN27InputNumber27,NegativePhase.
R23IP26InputNumber26,PositivePhase.
T1IN11InputNumber11,NegativePhase.
T2IP12InputNumber12,PositivePhase.
T3VNEGAnalogNegativePowerSupply.
T4A0ControlPin:OutputAddressBit0.
PinNo.
MnemonicDescriptionT20D0ControlPin:InputAddressBit0.
T21VNEGAnalogNegativePowerSupply.
T22IP27InputNumber27,PositivePhase.
T23IN28InputNumber28,NegativePhase.
U1IP13InputNumber13,PositivePhase.
U2IN12InputNumber12,NegativePhase.
U3VNEGAnalogNegativePowerSupply.
U4VDDLogicPositivePowerSupply.
U20VDDLogicPositivePowerSupply.
U21VNEGAnalogNegativePowerSupply.
U22IN29InputNumber29,NegativePhase.
U23IP28InputNumber28,PositivePhase.
V1IN13InputNumber13,NegativePhase.
V2IP14InputNumber14,PositivePhase.
V3VNEGAnalogNegativePowerSupply.
V4DGNDLogicNegativePowerSupply.
V20DGNDLogicNegativePowerSupply.
V21VNEGAnalogNegativePowerSupply.
V22IP29InputNumber29,PositivePhase.
V23IN30InputNumber30,NegativePhase.
W1IP15InputNumber15,PositivePhase.
W2IN14InputNumber14,NegativePhase.
W3VNEGAnalogNegativePowerSupply.
W4VOCMOutputCommon-ModeReferenceSupply.
W20VOCMOutputCommon-ModeReferenceSupply.
W21VNEGAnalogNegativePowerSupply.
W22IN31InputNumber31,NegativePhase.
W23IP30InputNumber30,PositivePhase.
Y1IN15InputNumber15,NegativePhase.
Y2VPOSAnalogPositivePowerSupply.
Y3VPOSAnalogPositivePowerSupply.
Y4VNEGAnalogNegativePowerSupply.
Y5VOCMOutputCommon-ModeReferenceSupply.
Y6VNEGAnalogNegativePowerSupply.
Y7VNEGAnalogNegativePowerSupply.
Y8VNEGAnalogNegativePowerSupply.
Y9VNEGAnalogNegativePowerSupply.
Y10VNEGAnalogNegativePowerSupply.
Y11VPOSAnalogPositivePowerSupply.
Y12VPOSAnalogPositivePowerSupply.
Y13VPOSAnalogPositivePowerSupply.
Y14VNEGAnalogNegativePowerSupply.
Y15VNEGAnalogNegativePowerSupply.
Y16VNEGAnalogNegativePowerSupply.
Y17VNEGAnalogNegativePowerSupply.
Y18VNEGAnalogNegativePowerSupply.
Y19VOCMOutputCommon-ModeReferenceSupply.
Y20VNEGAnalogNegativePowerSupply.
Y21VPOSAnalogPositivePowerSupply.
Y22IP31InputNumber31,PositivePhase.
AD8117/AD8118DataSheetRev.
B|Page12of36PinNo.
MnemonicDescriptionY23VPOSAnalogPositivePowerSupply.
AA1VPOSAnalogPositivePowerSupply.
AA2VPOSAnalogPositivePowerSupply.
AA3VPOSAnalogPositivePowerSupply.
AA4VPOSAnalogPositivePowerSupply.
AA5VNEGAnalogNegativePowerSupply.
AA6VNEGAnalogNegativePowerSupply.
AA7VNEGAnalogNegativePowerSupply.
AA8VNEGAnalogNegativePowerSupply.
AA9VNEGAnalogNegativePowerSupply.
AA10VNEGAnalogNegativePowerSupply.
AA11VPOSAnalogPositivePowerSupply.
AA12VPOSAnalogPositivePowerSupply.
AA13VPOSAnalogPositivePowerSupply.
AA14VNEGAnalogNegativePowerSupply.
AA15VNEGAnalogNegativePowerSupply.
AA16VNEGAnalogNegativePowerSupply.
AA17VNEGAnalogNegativePowerSupply.
AA18VNEGAnalogNegativePowerSupply.
AA19VNEGAnalogNegativePowerSupply.
AA20VPOSAnalogPositivePowerSupply.
AA21VPOSAnalogPositivePowerSupply.
AA22VPOSAnalogPositivePowerSupply.
AA23VPOSAnalogPositivePowerSupply.
AB1VPOSAnalogPositivePowerSupply.
AB2VPOSAnalogPositivePowerSupply.
AB3VPOSAnalogPositivePowerSupply.
AB4OP0OutputNumber0,PositivePhase.
AB5ON0OutputNumber0,NegativePhase.
AB6OP2OutputNumber2,PositivePhase.
AB7ON2OutputNumber2,NegativePhase.
AB8OP4OutputNumber4,PositivePhase.
AB9ON4OutputNumber4,NegativePhase.
AB10OP6OutputNumber6,PositivePhase.
AB11ON6OutputNumber6,NegativePhase.
AB12OP8OutputNumber8,PositivePhase.
PinNo.
MnemonicDescriptionAB13ON8OutputNumber8,NegativePhase.
AB14OP10OutputNumber10,PositivePhase.
AB15ON10OutputNumber10,NegativePhase.
AB16OP12OutputNumber12,PositivePhase.
AB17ON12OutputNumber12,NegativePhase.
AB18OP14OutputNumber14,PositivePhase.
AB19ON14OutputNumber14,NegativePhase.
AB20VPOSAnalogPositivePowerSupply.
AB21VPOSAnalogPositivePowerSupply.
AB22VPOSAnalogPositivePowerSupply.
AB23VPOSAnalogPositivePowerSupply.
AC1VPOSAnalogPositivePowerSupply.
AC2VPOSAnalogPositivePowerSupply.
AC3VPOSAnalogPositivePowerSupply.
AC4VPOSAnalogPositivePowerSupply.
AC5OP1OutputNumber1,PositivePhase.
AC6ON1OutputNumber1,NegativePhase.
AC7OP3OutputNumber3,PositivePhase.
AC8ON3OutputNumber3,NegativePhase.
AC9OP5OutputNumber5,PositivePhase.
AC10ON5OutputNumber5,NegativePhase.
AC11OP7OutputNumber7,PositivePhase.
AC12ON7OutputNumber7,NegativePhase.
AC13OP9OutputNumber9,PositivePhase.
AC14ON9OutputNumber9,NegativePhase.
AC15OP11OutputNumber11,PositivePhase.
AC16ON11OutputNumber11,NegativePhase.
AC17OP13OutputNumber13,PositivePhase.
AC18ON13OutputNumber13,NegativePhase.
AC19OP15OutputNumber15,PositivePhase.
AC20ON15OutputNumber15,NegativePhase.
AC21VPOSAnalogPositivePowerSupply.
AC22VPOSAnalogPositivePowerSupply.
AC23VPOSAnalogPositivePowerSupply.
DataSheetAD8117/AD8118Rev.
B|Page13of36TRUTHTABLEANDLOGICDIAGRAMTable9.
OperationTruthTableWEUPDATECLKDataInputDataOutputRESETSER/PAROperation/CommentXXXXX0XAsynchronousreset.
Alloutputsaredisabled.
Remainderoflogicin192-bitshiftregisterisunchanged.
0XXD0…D51Notapplicableinparallelmode10Broadcast.
ThedataonparallellinesD0toD5areloadedintoall32outputaddresslocationsofthe192-bitshiftregister.
1XDatai2Datai-19210Serialmode.
ThedataontheserialDATAINlineisloadedintotheserialregister.
ThefirstbitclockedintotheserialregisterappearsatDATAOUT192clockcycleslater.
0XXD0…D51A0…A43Notapplicableinparallelmode11Parallelprogrammingmode.
ThedataonparallellinesD0toD5areloadedintotheshiftregisterlocationaddressedbyA0toA4.
10XXNotapplicableinparallelmode1XSwitchmatrixupdate.
Datainthe192-bitshiftregistertransfersintotheparallellatchesthatcontroltheswitcharray.
1XXXX11Nochangeinlogic.
1D0…D5:databits.
2Datai:serialdata.
3A0…A4:addressbits.
AD8117/AD8118DataSheetRev.
B|Page14of3606365-007D1D0QSDQCLKD0D1D2D3D4D5D1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKUPDATERESETA4A3A2A1A0D1D0QSDQCLKOUT1ENOUT0ENOUT2ENOUT3ENOUT4ENOUT5ENOUT6ENOUT7ENOUT8ENOUT9ENOUT10ENOUT11ENOUT12ENOUT13ENOUT14ENOUT15ENOUT16ENOUT17ENOUT18ENOUT19ENOUT20ENOUT21ENOUT22ENOUT23ENOUT24ENOUT25ENOUT26ENOUT27ENOUT28ENOUT29ENOUT30ENOUT31END1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKD1D0QSDQCLKDECODED1D0QSDQCLKSWITCHMATRIXOUTPUTENABLE102432DCLRQOUT0B0ENADCLRQOUT0B1ENADCLRQOUT0B2ENADCLRQOUT0B3ENADCLRQOUT0B4ENADCLRQOUT0ENENADCLRQOUT1B0ENADCLRQOUT30ENENADCLRQOUT31B0ENADCLRQOUT31B1ENADCLRQOUT31B2ENADCLRQOUT31B3ENADCLRQOUT31B4ENADCLRQOUT31ENENADATAOUT(SERIAL)PARALLELDATA(OUTPUTENABLE)SER/PARWEDATAIN(SERIAL)CLKOUTPUTADDRESS5TO32DECODERFigure7.
LogicDiagramDataSheetAD8117/AD8118Rev.
B|Page15of36INPUT/OUTPUTSCHEMATICSOPn,ONn06365-008Figure8.
AD8117/AD8118EnabledOutput(AlsoSeeESDProtectionMap,Figure18)0.
4pF30k3.
4pF3.
4pFOPnONn06365-009Figure9.
AD8117/AD8118DisabledOutput(AlsoSeeESDProtectionMap,Figure18)1.
3pF1.
3pF0.
3pFIPnINn250025002538253806365-010Figure10.
AD8117Receiver(AlsoSeeESDProtectionMap,Figure18)250050750.
3pF1.
3pF1.
3pF25005075IPnINn06365-068Figure11.
AD8118Receiver(AlsoSeeESDProtectionMap,Figure18)1.
3pF1.
3pF0.
3pFIPnINn2500250006365-011Figure12.
AD8117/AD8118ReceiverSimplifiedEquivalentCircuitWhenDrivingDifferentially1.
6pFIPnINn3.
33kAD8117G=+13.
76kAD8118G=+206365-012Figure13.
AD8117/AD8118ReceiverSimplifiedEquivalentCircuitWhenDrivingSingle-EndedVOCMVNEG06365-013Figure14.
VOCMInput(AlsoSeeESDProtectionMap,Figure18)RESETDGNDVDD1k25k06365-014Figure15.
ResetInput(AlsoSeeESDProtectionMap,Figure18)AD8117/AD8118DataSheetRev.
B|Page16of36CLK,SER/PAR,WE,UPDATE,DATAIN,A[4:0],D[5:0]DGND1k06365-015Figure16.
LogicInput(AlsoSeeESDProtectionMap,Figure18)VDDDGNDDATAOUT06365-016Figure17.
LogicOutput(AlsoSeeESDProtectionMap,Figure18)VPOSVNEGIPn,INn,OPn,ONn,VOCMVDDDGNDCLK,RESET,SER/PAR,WE,UPDATE,DATAIN,DATAOUT,A[4:0],D[5:0]06365-017Figure18.
ESDProtectionMapDataSheetAD8117/AD8118Rev.
B|Page17of36TYPICALPERFORMANCECHARACTERISTICSVS=±2.
5VatTA=25°C,RL,diff=200Ω,VOCM=0V,differentialinput/outputmode,unlessotherwisenoted.
10–101000GAIN(dB)FREQUENCY(MHz)–202–8–6–446811010006365-018AD8118AD8117Figure19.
AD8117,AD8118SmallSignalFrequencyResponse,200mVp-p10–101000GAIN(dB)FREQUENCY(MHz)–202–8–6–446811010006365-019AD8118AD8117Figure20.
AD8117,AD8118LargeSignalFrequencyResponse,2Vp-p10–1001000NORMALIZEDGAIN(dB)FREQUENCY(MHz)86420–2–4–6–81001010pF5pF2pF0pF06365-020Figure21.
AD8117SmallSignalFrequencyResponsewithCapacitiveLoads,200mVp-p4000540700COUNTFREQUENCY(MHz)3502002501505030010068066064062060058056006365-021Figure22.
AD81173dBBandwidthHistogram,OneDevice,All1024Channels0–332NORMALIZEDBANDWIDTHERROR(%)NUMBEROFENABLEDCHANNELS–1–22624222012864218161410302806365-022Figure23.
AD8117BandwidthErrorvs.
EnabledChannels0–70–60–50–40–30–20–10300k1M10M100M1G2GCMR(dB)FREQUENCY(Hz)DIFFERENTIALOUT06365-023Figure24.
AD8117,AD8118Common-ModeRejectionAD8117/AD8118DataSheetRev.
B|Page18of36–15–950.
11000PSR(dB)FREQUENCY(MHz)–25–35–45–55–65–75–85100101VNEGAGGRESSORDIFFERENTIALOUTVPOSAGGRESSORVOCMAGGRESSOR06365-024Figure25.
AD8117PowerSupplyRejection10–500.
11000PSR(dB)FREQUENCY(MHz)50–5–30–35–40–45100101–10–15–20–25VNEGAGGRESSORVPOSAGGRESSORVOCMAGGRESSOR06365-025SINGLE-ENDEDOUTFigure26.
AD8117PowerSupplyRejection,Single-Ended1401601800204060801001201k10k100k1MNOISESPECTRALDENSITY(nV/Hz)FREQUENCY(Hz)DIFFERENTIALOUT06365-026AD8118AD8117Figure27.
AD8117,AD8118NoiseSpectralDensity,RTO0–100–60–80–40–20300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)DIFFERENTIALIN/OUT06365-027Figure28.
AD8117Crosstalk,OneAdjacentChannel300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)06365-070–100–80–60–40–200DIFFERENTIALIN/OUTFigure29.
AD8118Crosstalk,OneAdjacentChannel0–100–60–80–40–20300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)SINGLE-ENDEDIN/OUT06365-028Figure30.
AD8117Crosstalk,OneAdjacentChannel,Single-EndedDataSheetAD8117/AD8118Rev.
B|Page19of36300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)06365-071–100–80–60–40–200SINGLE-ENDEDIN/OUTFigure31.
AD8118Crosstalk,OneAdjacentChannel,Single-Ended0–100–60–80–40–20300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)DIFFERENTIALIN/OUT06365-029Figure32.
AD8117Crosstalk,AllHostile300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)06365-072–100–80–60–40–200DIFFERENTIALIN/OUTFigure33.
AD8118Crosstalk,AllHostile0–100–60–80–40–20300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)SINGLE-ENDEDIN/OUT06365-030Figure34.
AD8117Crosstalk,AllHostile,Single-Ended300k1M10M100M1GCROSSTALK(dB)FREQUENCY(Hz)06365-073–100–80–60–40–200SINGLE-ENDEDIN/OUTFigure35.
AD8118Crosstalk,AllHostile,Single-Ended0–100–60–80–40–20300k1M10M100M1G2GFEEDTHROUGH(dB)FREQUENCY(Hz)DIFFERENTIALIN/OUT06365-031Figure36.
AD8117Crosstalk,OffIsolationAD8117/AD8118DataSheetRev.
B|Page20of360–100–60–80–40–20300k1M10M100M1G2GFEEDTHROUGH(dB)FREQUENCY(Hz)SINGLE-ENDEDIN/OUT06365-032Figure37.
AD8117Crosstalk,OffIsolation,Single-Ended6k5k02k1k3k4k300k1M10M100M1GINPUTIMPEDANCE()FREQUENCY(Hz)06365-033DIFFERENTIALINAD8118AD8117Figure38.
AD8117,AD8118InputImpedance300k1M10M100M1GINPUTIMPEDANCE()FREQUENCY(Hz)06365-034050010001500200025003000350040004500AD8118AD8117SINGLE-ENDEDINFigure39.
AD8117,AD8118InputImpedance,Single-Ended30k25k20k15k10k5k0100k1M10M100M1GOUTPUTIMPEDANCE()FREQUENCY(Hz)DIFFERENTIALOUT06365-035Figure40.
AD8117,AD8118OutputImpedance,Disabled10000.
1100k1GOUTPUTIMPEDANCE()FREQUENCY(Hz)10110010M100M1M06365-036Figure41.
AD8117,AD8118OutputImpedance,Enabled0.
4–0.
4015VOUT(V,DIFF)TIME(ns)–0.
200.
2357911130.
3–0.
3–0.
10.
14681012141206365-037Figure42.
AD8117SmallSignalPulseResponse,200mVp-pDataSheetAD8117/AD8118Rev.
B|Page21of360.
20–0.
20015VOUT(V,SE)TIME(ns)–0.
1000.
10357911130.
15–0.
15–0.
050.
0546810121412N-CHANNELP-CHANNEL06365-038Figure43.
AD8117SmallSignalPulseResponse,Single-Ended,200mVp-p2.
0–2.
0015VOUT(V,DIFF)TIME(ns)–1.
001.
0357911131.
5–1.
5–0.
50.
54681012141206365-039Figure44.
AD8117LargeSignalPulseResponse,2Vp-p1.
0–1.
0015VOUT(V,SE)TIME(ns)–0.
60.
2357911130.
6–0.
2046810121412N-CHANNELP-CHANNEL–0.
40.
40.
8–0.
806365-040Figure45.
AD8117LargeSignalPulseResponse,Single-Ended,2Vp-p1.
5–1.
5–40120VOUT(V,DIFF)TIME(ns)1.
00.
50–0.
5–1.
03–3210–1–2100806040200–20VOUTUPDATE06365-041UPDATE(V)Figure46.
AD8117SwitchingTime2–40VOUT(V,DIFF)TIME(ns)10–1–2–3543215000–1000SLEWRATE(V/s)40003000200010000SLEWRATEVOUT06365-042Figure47.
AD8117LargeSignalRisingEdgeandSlewRate2–40VOUT(V,DIFF)1ns/DIV10–1–2–3543213500–2500SLEWRATE(V/s)25001500500–500–1500SLEWRATEVOUT06365-043Figure48.
AD8117LargeSignalFallingEdgeandSlewRateAD8117/AD8118DataSheetRev.
B|Page22of3650–40100OFFSET(mV)TEMPERATURE(C)43129080706050403020100–10–20–3006365-044Figure49.
AD8117VOSvs.
TemperatureinBroadcastMode50–20–0.
100.
10VOUT(mV,DIFF)TIME(s)403020100–100.
080.
060.
040.
020–0.
02–0.
04–0.
06–0.
0806365-045Figure50.
AD8117SwitchingTransient(Glitch)0.
020–0.
010–700700DIFFERENTIALGAINERROR(%)VIN,DIFF(mV)0.
0150.
0100.
0050–0.
005–500500300100–100–30006365-046Figure51.
AD8117Gainvs.
DCVoltage,CarrierFrequency=3.
58MHz,SubcarrierAmplitude=600mVp-p,Differential0.
014–0.
004DIFFERENTIALPHASEERROR(%)VIN,DIFF(mV)0.
0120.
0100.
0080.
0060.
0040.
0020–0.
00206365-047–700700–500500300100–100–300Figure52.
AD8117Phasevs.
DCVoltage,CarrierFrequency=3.
58MHz,SubcarrierAmplitude=600mVp-p,Differential2.
0–2.
0018VOUT(V,DIFF)TIME(ns)1614121086421.
51.
00.
50–0.
5–1.
0–1.
510pF5pF2pF0pF06365-048Figure53.
AD8117LargeSignalPulseResponsewithCapacitiveLoads0.
4–0.
4018VOUT(V,DIFF)TIME(ns)0.
30.
20.
10–0.
1–0.
2–0.
316141210864210pF5pF2pF0pF06365-049Figure54.
AD8117SmallSignalPulseResponsewithCapacitiveLoadsDataSheetAD8117/AD8118Rev.
B|Page23of361.
4–0.
2–50150VOUT(V,DIFF)TIME(ns)1.
21.
00.
80.
60.
40.
202.
8–0.
42.
42.
01.
61.
20.
80.
401301109070503010–10–30UPDATEVOUT06365-050UPDATE(V)Figure55.
AD8117EnableTime1.
4–0.
2–50150VOUT(V,DIFF)TIME(ns)1.
21.
00.
80.
60.
40.
202.
8–0.
42.
42.
01.
61.
20.
80.
401301109070503010–10–30VOUTUPDATE06365-051UPDATE(V)Figure56.
AD8117DisableTime0–0.
05–50100GAIN(dB)TEMPERATURE(C)–250255075–0.
01–0.
02–0.
03–0.
0406365-052Figure57.
AD8117DCGainvs.
Temperature600100–3595IPOSANDINEG(mA)TEMPERATURE(°C)IDD(A)50040030020090040080070060050085756555453525155–5–15–25IDD(PARALLELMODE)IDD(SERIALMODE)IPOSANDINEG(BROADCAST)IPOSANDINEG(ALLOUTPUTSDISABLED)06365-053Figure58.
AD8117,AD8118QuiescentSupplyCurrentsvs.
Temperature50020032IPOSANDINEG(mA)CHANNELS450400350300250950850750650550450900800700600500IDD(A)282420161284IDDPARALLELIDDSERIALIPOS,INEG06365-054Figure59.
AD8117,AD8118QuiescentSupplyCurrentsvs.
EnabledOutputs65–507OUTPUTERROR(%)TIME(ns)4536215545352515506050403020103.
25–0.
252.
752.
251.
751.
250.
750.
2503.
002.
502.
001.
501.
000.
50(V,DIFF)VOUTVIN(VOUT–VIN)/VOUT06365-055Figure60.
AD8117SettlingTimeAD8117/AD8118DataSheetRev.
B|Page24of365–507OUTPUT/INPUT(%)TIME(ns)654321–443210–1–2–306365-056Figure61.
AD8117SettlingTime(Zoom)2.
5–2.
50700VOUT(V,SE)TIME(ns)600500400300200100–1.
5–1.
0–2.
000.
5–0.
51.
52.
01.
0VINNVOUTNVOUTPVINP06365-057Figure62.
AD8117OverdriveRecovery,Single-Ended0700VOUT(V,SE)TIME(ns)600500400300200100–1.
5–2.
0–1.
000.
5–0.
51.
52.
01.
006365-069VOUTPVINPVINNVOUTNFigure63.
AD8118OverdriveRecovery,Single-Ended–30–1001000DISTORTION(dBc)FREQUENCY(MHz)–90–80–70–60–50–400.
1101001VOUT=2Vp-p,DIFFSECONDHARMONICTHIRDHARMONIC06365-058Figure64.
AD8117HarmonicDistortionDataSheetAD8117/AD8118Rev.
B|Page25of36THEORYOFOPERATIONTheAD8117/AD8118arefullydifferentialcrosspointarrayswith32outputs,eachofwhichcanbeconnectedtoanyoneof32inputs.
Organizedbyoutputrow,32switchableinputtrans-conductancestagesareconnectedtoeachoutputbuffertoform32-to-1multiplexers.
Thereare32ofthesemultiplexers,eachwithitsinputswiredinparallel,foratotalarrayof1024transconductancestagesformingamulticast-capablecrosspointswitch.
Decodinglogicforeachoutputselectsone(ornone)ofthetransconductancestagestodrivetheoutputstage.
Theenabledtransconductancestagedrivestheoutputstage,andfeedbackformsaclosed-loopamplifierwithadifferentialgainofone(thedifferencebetweentheoutputvoltagesisequaltothedifferencebetweentheinputvoltages).
Asecondfeedbackloopcontrolsthecommon-modeoutputlevel,forcingtheaverageofthedifferentialoutputvoltagestomatchthevoltageontheVOCMreferencepin.
Althougheachoutputhasanindependentcommon-modecontrolloop,theVOCMreferenceiscommonfortheentirechip,andassuchneedstobedrivenwithalowimpedancetoavoidcrosstalk.
EachdifferentialinputtotheAD8117/AD8118isbufferedbyareceiver.
Thepurposeofthisreceiveristoprovideanextendedinputcommon-moderange,andtoremovethiscommonmodefromthesignalchain.
Liketheoutputmultiplexers,theinputreceiverhasbothadifferentialloopandacommon-modecontrolloop.
Amask-programmablefeedbacknetworksetstheclosed-loopdifferentialgain.
FortheAD8117,thisdifferentialgainisone,andfortheAD8118,thisdifferentialgainistwo.
Thereceiverhasaninputstagethatdoesnotrespondtothecommonmodeofthesignal.
Thisarchitecture,alongwiththeattenuatingfeedbacknetwork,allowstheusertoapplyinputvoltagesthatextendfromrail-to-rail.
Excessdifferentialloopgainbandwidthproductreducestheeffectoftheclosed-loopgainonthebandwidthofthedevice.
TheoutputstageoftheAD8117/AD8118isdesignedforlowdifferentialgainandphaseerrorwhendrivingcompositevideosignals.
Italsoprovidesslewcurrentforfastpulseresponsewhendrivingcomponentvideosignals.
Unlikemanymulti-plexerdesigns,theserequirementsarebalancedsuchthatlargesignalbandwidthisverysimilartosmallsignalbandwidth.
Thedesignloadis150Ω,butprovisionsaremadetodriveloadsaslowas75Ωsolongason-chippowerdissipationlimitsarenotexceeded.
TheoutputsoftheAD8117/AD8118canbedisabledtominimizeon-chippowerdissipation.
Whendisabled,thereisafeedbacknetworkof25kΩbetweenthedifferentialoutputs.
ThishighimpedanceallowsmultipleICstobebussedtogetherwithoutadditionalbuffering.
Caremustbetakentoreduceoutputcapacitance,whichresultsinmoreovershootandfrequencydomainpeaking.
Aseriesofinternalamplifiersdriveinternalnodessuchthatawidebandhighimpedanceispresentedatthedisabledoutput,evenwhiletheoutputbusisunderlargesignalswings.
Whentheoutputsaredisabledanddrivenexternally,thevoltageappliedtothemmustnotexceedthevalidoutputswingrangefortheAD8117/AD8118tokeeptheseinternalamplifiersintheirlinearrangeofoperation.
ApplyingexcessdifferentialvoltagestothedisabledoutputscancausedamagetotheAD8117/AD8118andmustbeavoided(seetheAbsoluteMaximumRatingssectionforguidelines).
TheconnectionoftheAD8117/AD8118iscontrolledbyaflexibleTTL-compatiblelogicinterface.
Eitherparallelorserialloadingintoafirstrankoflatchespreprogramseachoutput.
Aglobalupdatesignalmovestheprogrammingdataintothesecondrankoflatches,simultaneouslyupdatingalloutputs.
Inserialmode,aserial-outpinallowsdevicestobedaisy-chainedtogetherforsingle-pinprogrammingofmultipleICs.
Apower-onresetpinisavailabletoavoidbusconflictsbydisablingalloutputs.
Thispower-onresetclearsthesecondrankoflatches,butdoesnotclearthefirstrankoflatches.
Inparallelmode,toquicklyclearthefirstrank,abroadcastparallelprogrammingfeatureisavailable.
Inserialmode,preprogrammingindividualinputsisnotpossibleandtheentireshiftregisterneedstobeflushed.
TheAD8117/AD8118canoperateonasingle+5Vsupply,poweringboththesignalpath(withtheVPOS/VNEGsupplypins),andthecontrollogicinterface(withtheVDD/DGNDsupplypins).
However,toeasilyinterfacetoground-referencedvideosignals,splitsupplyoperationispossiblewith±2.
5Vsupplies.
Inthiscase,aflexiblelogicinterfaceallowsthecontrollogicsupplies(VDD/DGND)toberunoff+2V/0Vto+5V/0Vwhilethecoreremainsonsplitsupplies.
Additionalflexibilityintheanalogoutputcommon-modelevelfacilitatesunequalsplitsupplies.
If+3V/–2Vsuppliesto+2V/–3Vsuppliesaredesired,theVOCMpincanstillbesetto0Vforground-referencedvideosignals.
AD8117/AD8118DataSheetRev.
B|Page26of36APPLICATIONSINFORMATIONPROGRAMMINGTheAD8117/AD8118havetwooptionsforchangingtheprogrammingofthecrosspointmatrix.
Inthefirstoption,aserialwordof192bitscanbeprovidedthatupdatestheentirematrixeachtime.
Thesecondoptionallowsforchangingtheprogrammingofasingleoutputviaaparallelinterface.
Theserialoptionrequiresfewersignals,butmoretime(clockcycles)forchangingtheprogramming,whiletheparallelprogrammingtechniquerequiresmoresignals,butcanchangeasingleoutputatatimeandrequiresfewerclockcyclestocompleteprogramming.
SerialProgrammingDescriptionTheserialprogrammingmodeusestheCLK,DATAIN,UPDATE,andSER/PARdevicepins.
ThefirststepistoassertalowonSER/PARtoenabletheserialprogrammingmode.
HoldtheparallelclockWEhighduringtheentireserialprogrammingoperation.
HoldtheUPDATEsignalhighduringthetimethatdataisshiftedintotheserialportofthedevice.
AlthoughthedatastillshiftsinwhenUPDATEislow,thetransparent,asynchronouslatchesallowtheshiftingdatatoreachthematrix.
Thiscausesthematrixtotrytoupdatetoeveryintermediatestateasdefinedbytheshiftingdata.
ThedataatDATAINisclockedinateveryfallingedgeofCLK.
Atotalof192bitsmustbeshiftedintocompletetheprogram-ming.
Foreachofthe32outputs,therearefivebits(D0toD4)thatdeterminethesourceofitsinputfollowedbyonebit(D5)thatdeterminestheenabledstateoftheoutput.
IfD5islow(outputdisabled),thefiveassociatedbits(D0toD4)donotmatter,becausenoinputisswitchedtothatoutput.
Themostsignificantoutputaddressdataisshiftedinfirst,withtheenablebit(D5)shiftedinfirst,followedbytheinputaddress(D4toD0)enteredsequentiallywithD4firstandD0last.
Eachremainingoutputisprogrammedsequentially,untiltheleastsignificantoutputaddressdataisshiftedin.
Atthispoint,UPDATEcanbetakenlow,whichcausestheprogrammingofthedeviceaccordingtothedatathatwasjustshiftedin.
TheUPDATElatchesareasynchronousandwhenUPDATEislow,theyaretransparent.
IfmorethanoneAD8117/AD8118deviceistobeseriallyprogrammedinasystem,theDATAOUTsignalfromonedevicecanbeconnectedtotheDATAINofthenextdevicetoformaserialchain.
ConnectalloftheCLK,UPDATE,andSER/PARpinsinparallelandoperatethemasdescribedpreviously.
TheserialdataisinputtotheDATAINpinofthefirstdeviceofthechain,anditripplesthroughtothelast.
Therefore,thedataforthelastdeviceinthechainmustcomeatthebeginningoftheprogrammingsequence.
Thelengthoftheprogrammingsequenceis192bitstimesthenumberofdevicesinthechain.
ParallelProgrammingDescriptionWhenusingtheparallelprogrammingmode,itisnotnecessarytoreprogramtheentiredevicewhenmakingchangestothematrix.
Infact,parallelprogrammingallowsthemodificationofasingleoutputatatime.
BecausethistakesonlyoneWE/UPDATEcycle,significanttimesavingscanberealizedbyusingparallelprogramming.
OneimportantconsiderationinusingparallelprogrammingisthattheRESETsignaldoesnotresetallregistersintheAD8117/AD8118.
Whentakenlow,theRESETsignalonlysetseachoutputtothedisabledstate.
Thisishelpfulduringpower-uptoensurethattwoparalleloutputsarenotactiveatthesametime.
Afterinitialpower-up,theinternalregistersinthedevicegenerallyhaverandomdata,eventhoughtheRESETsignalhasbeenasserted.
Ifparallelprogrammingisusedtoprogramoneoutput,thatoutputisproperlyprogrammed,buttherestofthedevicehasarandomprogramstatedependingontheinternalregistercontentatpower-up.
Therefore,whenusingparallelprogramming,itisessentialthatalloutputsbeprogrammedtoadesiredstateafterpower-up.
Thisensuresthattheprogrammingmatrixisalwaysinaknownstate.
Fromthenon,parallelprogrammingcanbeusedtomodifyasingleoutputormoreatatime.
Insimilarfashion,ifUPDATEistakenlowafterinitialpower-up,therandompower-updataintheshiftregisterisprogrammedintothematrix.
Therefore,topreventthecrosspointfrombeingprogrammedintoanunknownstate,donotapplyalowlogicleveltoUPDATEafterpowerisinitiallyapplied.
Programmingthefullshiftregisteronetimetoadesiredstate,byeitherserialorparallelprogrammingafterinitialpower-up,eliminatesthepossibilityofprogrammingthematrixtoanunknownstate.
Tochangetheprogrammingofanoutputviaparallelprogramming,takeSER/PARandUPDATEhigh.
Leavetheserialprogrammingclock(CLK)highduringparallelprogramming.
Starttheparallelclock(WE)inthehighstate.
The5-bitaddressoftheoutputtobeprogrammedmustbeputonA0toA4.
Thefirstfivedatabits(D0toD4)mustcontaintheinformationthatidentifiestheinputthatisprogrammedtotheoutputthatisaddressed.
Thesixthdatabit(D5)determinestheenabledstateoftheoutput.
IfD5islow(outputdisabled),thenthedataonD0toD4doesnotmatter.
Afterthedesiredaddressanddatasignalshavebeenestablished,theycanbelatchedintotheshiftregisterbyahightolowtransitionoftheWEsignal.
Thematrixisnotprogrammed,however,untiltheUPDATEsignalistakenlow.
ItisthuspossibletolatchinnewdataforseveraloralloftheoutputsfirstviasuccessivenegativetransitionsofWEwhileUPDATEisheldhigh,andthenhaveallthenewdatatakeeffectwhenUPDATEgoeslow.
Usethistechniquewhenprogrammingthedeviceforthefirsttimeafterpower-upwhenusingparallelprogramming.
DataSheetAD8117/AD8118Rev.
B|Page27of36ResetWhenpoweringuptheAD8117/AD8118,itisusuallydesirabletohavetheoutputscomeupinthedisabledstate.
TheRESETpin,whentakenlow,causesalloutputstobeinthedisabledstate.
However,theUPDATEsignaldoesnotresetallregistersintheAD8117/AD8118.
Thisisimportantwhenoperatingintheparallelprogrammingmode.
RefertotheParallelProgrammingDescriptionsectionforinformationaboutprogramminginternalregistersafterpower-up.
Serialprogrammingprogramstheentirematrixeachtime;therefore,nospecialconsiderationsapply.
Becausethedataintheshiftregisterisrandomafterpower-up,donotuseittoprogramthematrix,orthematrixcanenterunknownstates.
Topreventthis,donotapplyalogiclowsignaltoUPDATEinitiallyafterpower-up.
Loadtheshiftregisterfirstbeloadedwiththedesireddata,andthenUPDATEcanbetakenlowtoprogramthedevice.
TheRESETpinhasa20kΩpull-upresistortoVDDthatcanbeusedtocreateasimplepower-upresetcircuit.
AcapacitorfromRESETtogroundholdsRESETlowforsometimewhiletherestofthedevicestabilizes.
Thelowconditioncausesalltheoutputstobedisabled.
Thecapacitorthenchargesthroughthepull-upresistortothehighstate,thusallowingfullprogrammingcapabilityofthedevice.
BroadcastTheAD8117/AD8118logicinterfacehasabroadcastmode,inwhichallfirstranklatchescanbesimultaneouslyparallel-programmedtothesamedatainonewritecycle.
Thisisespeciallyusefulinclearingrandomfirstrankdataafterpower-up.
Toaccessthebroadcastmode,thedeviceisparallelprogrammedusingtheWE,A0toA4,D0toD5,andUPDATEdevicepins.
TheonlydifferenceisthattheSER/PARpinisheldlow,asifserialprogramming.
ByholdingCLKhigh,noserialclockingoccurs,andinstead,WEcanbeusedtoclockallfirstranklatchesinthechipatonce.
OPERATINGMODESTheAD8117/AD8118hasfullydifferentialinputsandoutputs.
Theinputsandoutputscanalsobeoperatedinasingle-endedfashion.
Thispresentsseveraloptionsforcircuitconfigurationsthatrequiredifferentgainsandtreatmentofterminations,iftheyareused.
DifferentialInputEachdifferentialinputtotheAD8117/AD8118isappliedtoadifferentialreceiver.
Thesereceiversallowtheusertodrivetheinputswithadifferentialsignalwithanuncertaincommon-modevoltage,suchasfromaremotesourceovertwistedpair.
Thereceiversrespondonlytothedifferenceininputvoltagesandrestoreacommon-modevoltagesuitablefortheinternalsignalpath.
Noiseorcrosstalkthatispresentinbothinputsisrejectedbytheinputstage,asspecifiedbyitscommon-moderejectionratio(CMRR).
Differentialoperationoffersagreatnoisebenefitforsignalsthatarepropagatedoverdistanceinanoisyenvironment.
IN+VOCMIN–RGRGRCVRRFRFOUT–OUT+TOSWITCHMATRIX06365-059Figure65.
InputReceiverEquivalentCircuitThecircuitconfigurationusedbythedifferentialinputreceiversissimilartothatofseveralAnalogDevices,Inc.
general-purposedifferentialamplifiers,suchastheAD8131.
Itisavoltagefeedbackamplifierwithinternalgainsettingresistors.
Thearrangementoffeedbackmakesthedifferentialinputimpedanceappeartobe5kΩacrosstheinputs.
kΩ52,GdmINRRThisimpedancecreatesasmalldifferentialterminationerroriftheuserdoesnotaccountforthe5kΩparallelelement,althoughthiserrorislessthan1%inmostcases.
Additionally,thesourceimpedancedrivingtheAD8117/AD8118appearsinparallelwiththeinternalgain-settingresistors,suchthattheremaybeagainerrorforsomevaluesofsourceresistance.
TheAD8117/AD8118areadjustedsuchthatitsgainsarecorrectwhendrivenbyabackterminated75Ωsourceimpedanceateachinputphase(37.
5Ωeffectiveimpedancetogroundateachinputpin,or75Ωdifferentialsourceimpedanceacrosspairsofinputpins).
Ifadifferentsourceimpedanceispresented,thedifferentialgainoftheAD8117/AD8118canbecalculatedbySGFdmINOUT,dmdmRRRVVG,where:RG=2.
5kΩ.
RSistheusersingle-endedsourceresistance(suchas37.
5Ωforabackterminated75Ωsource).
RF=2.
538kΩfortheAD8117and5.
075kΩfortheAD8118.
InthecaseoftheAD8117,SdmRGkΩ5.
2kΩ538.
2InthecaseoftheAD8118,SdmRGkΩ5.
2kΩ075.
5Whenoperatingwithadifferentialinput,caremustbetakentokeepthecommonmode,oraverage,oftheinputvoltageswithinthelinearoperatingrangeoftheAD8117/AD8118receiver.
Thiscommon-moderangecanextendrail-to-rail,providedthedifferentialsignalswingissmallenoughtoavoidforwardbiasingtheESDdiodes(itissafesttokeepthecommonmodeplusdifferentialsignalexcursionswithinthesupplyvoltagesofthedevice).
SeetheSpecificationssectionforguaranteedinputrange.
AD8117/AD8118DataSheetRev.
B|Page28of36ThedifferentialoutputoftheAD8117/AD8118receiverislinearforapeakof1.
4Vofoutputvoltagedifference(1.
4VpeakinputdifferencefortheAD8117,and0.
7VpeakinputdifferencefortheAD8118).
Takingtheoutputdifferentially,usingthetwooutputphases,thisallows2.
8Vp-poflinearoutputsignalswing.
Beyondthislevel,thesignalpathcansaturateandlimitthesignalswing.
Thisisnotadesiredoperationbecausethesupplycurrentincreasesandthesignalpathisslowtorecoverfromclipping.
Theabsolutemaximumalloweddifferentialinputsignalislimitedbythelong-termreliabilityoftheinputstage.
ObservethelimitsintheAbsoluteMaximumRatingssectiontoavoiddegradingdeviceperformancepermanently.
RCVRAD8117OPnONnIPnINn505006365-060Figure66.
ExampleofInputDrivenDifferentiallySingle-EndedInputTheAD8117/AD8118inputreceiverscanbedrivensingle-endedly(unbalanced).
Fromthestandpointofthereceiver,thereisverylittledifferencebetweensignalsappliedpositiveandnegativeintwophasestotheinputpair,vs.
asignalappliedtooneinputonlywiththeotherinputheldataconstantpotential.
Onesmalldifferenceisthatthecommonmodebetweentheinputpinsischangingifonlyoneinputismoving,andthereisaverysmallcommon-modetodifferentialconversiongaininthereceiverthataddsanadditionalgainerrortotheoutput(seethecommon-moderejectionratiofortheinputstageintheSpecificationssection).
Forlowfrequencies,thisgainerrorisnegligible.
Thecommon-moderejectionratiodegradeswithincreasingfrequency.
WhenoperatingtheAD8117/AD8118receiverssingle-endedly,theobservedinputresistanceateachinputpinislowerthaninthedifferentialinputcase,duetoafractionofthereceiverinternaloutputvoltageappearingasacommon-modesignalonitsinputterminals,bootstrappingthevoltageontheinputresistance.
Calculatethissingle-endedinputresistanceby)(21FSGFSGINRRRRRRRwhere:RG=2.
5kΩ.
RSistheusersingle-endedsourceresistance(suchas37.
5Ωforabackterminated75Ωsource).
RF=2.
538kΩfortheAD8117and5.
075kΩfortheAD8118.
Inmostcases,asingle-endedinputsignalisreferredtomidsupply,typicallyground.
Inthiscase,theundrivendifferentialinputcanbeconnectedtoground.
Forbestdynamicperformanceandlowestoffsetvoltage,terminatethisunusedinputwithanimpedancematchingthedriveninput,insteadofbeingdirectlyshortedtoground.
Duetothedifferentialfeedbackofthereceiver,thereisahighfrequencysignalcurrentintheundriveninputanditmustbetreatedasasignallineintheboarddesign.
RCVROPnONnIPnINn7575(OR37.
5)06365-061AD8117Figure67.
ExampleofInputDrivenSingle-EndedACCouplingofInputsItispossibletoaccoupletheinputsoftheAD8117/AD8118receiver.
Thisissimplifiedbecausethebiascurrentdoesnotneedtobesuppliedexternally.
AcapacitorinserieswiththeinputstotheAD8117/AD8118createsahigh-passfilterwiththeinputimpedanceofthedevice.
Thiscapacitorneedstobesizedsuchthatthecornerfrequencyislowenoughforfrequenciesofinterest.
DifferentialOutputBenefitsofDifferentialOperationTheAD8117/AD8118haveafullydifferentialswitchcore,withdifferentialoutputs.
Thetwooutputvoltagesmoveinoppositepolarity,withadifferentialfeedbackloopmaintainingafixedoutputstagedifferentialgainof+1(thedifferentoverallsignalpathgainsbetweentheAD8117andAD8118aresetintheinputstageforbestsignal-to-noiseratio).
Thisdifferentialoutputstageprovidesabenefitofcrosstalkcancelingduetoparasiticcouplingfromoneoutputtoanother,beingequalandoutofphase.
Additionally,iftheoutputofthedeviceisutilizedinadifferentialdesign,noise,crosstalk,andoffsetvoltagesgeneratedon-chipthatarecoupledequallyintobothoutputsarecancelledbythecommon-moderejectionratioofthenextdeviceinthesignalchain.
ByutilizingtheAD8117/AD8118outputsinadifferentialapplication,thebestpossiblenoiseandoffsetspecificationscanberealized.
DifferentialGainThespecifiedsignalpathgainoftheAD8117/AD8118referstoitsdifferentialgain.
FortheAD8117,thegainof+1meansthatthedifferenceinvoltagebetweenthetwooutputterminalsisequaltothedifferenceappliedbetweenthetwoinputterminals.
FortheAD8118,theratioofoutputdifferencevoltagetoappliedinputdifferencevoltageis+2.
Thecommonmode,oraveragevoltageofthepairofoutputsignalsissetbythevoltageontheVOCMpin.
Thisvoltageistypicallysettomidsupply(oftenground),butcanbemovedapproximately±0.
5Vtoaccommodatecaseswherethedesiredoutputcommon-modevoltagemaynotbemidsupply(asinthecaseofunequalsplitsupplies).
AdjustingVOCMcanlimitDataSheetAD8117/AD8118Rev.
B|Page29of36differentialswinginternallybelowthespecificationsonthedatasheet.
Regardlessofthedifferentialgainofthedevice,thecommon-modegainfortheAD8117andAD8118is+1totheoutput.
ThismeansthatthecommonmodeoftheoutputvoltagesdirectlyfollowsthereferencevoltageappliedtotheVOCMinput.
TheVOCMreferenceisahighspeedsignalinput,commontoalloutputstagesonthedevice.
Itrequiresonlysmallamountsofbiascurrent,butnoiseappearingonthispinisbufferedtotheoutputsofalltheoutputstages.
Assuch,connecttheVOCMnodetoalownoise,lowimpedancevoltagetoavoidbeingasourceofnoise,offset,andcrosstalkinthesignalpath.
TerminationTheAD8117/AD8118aredesignedtodrive150Ωoneachoutput(oraneffective300Ωdifferential),buttheoutputstageiscapableofsupplyingthecurrenttodrive100Ωloads(200Ωdifferential)overthespecifiedoperatingtemperaturerange.
Ifcareistakentoobservethemaximumpowerderatingcurves,theoutputstagecandrive75Ωloadswithslightlyreducedslewrateandbandwidth(aneffective150Ωdifferentialload).
Terminationattheloadendisrecommendedforbestsignalintegrity.
Thisloadterminationisoftenaresistortoagroundreferenceoneachindividualoutput.
ByterminatingtothesamevoltagelevelthatdrivestheVOCMreference,thepowerdissipationduetodcterminationcurrentisreduced.
Indifferentialsignalpaths,itisoftendesirabletoterminatedifferentially,withasingleresistoracrossthedifferentialoutputsattheloadend.
ThisisacceptablefortheAD8117/AD8118,butwhenthedeviceoutputsareplacedinadisabledstate,asmallamountofdcbiascurrentisrequirediftheoutputistopresentasahighimpedanceoveranexcursionofoutputbusvoltages.
IftheAD8117/AD8118disabledoutputsarefloated(orsimplytiedtogetherbyaresistor),internalnodessaturateandanincreaseindisabledoutputcurrentmaybeobserved.
Forbestpulseresponse,itisoftendesirabletoplaceaseriesresistorineachoutputtomatchthecharacteristicimpedanceandterminationoftheoutputtraceorcable.
Thisisknownasbacktermination,andhelpsshortensettlingtimebyterminatingreflectedsignalswhendrivingaloadthatisnotaccuratelyterminatedattheloadend.
Asideeffectofbackterminationisanattenuationoftheoutputsignalbyafactoroftwo.
Inthiscase,againoftwoisusuallynecessarysomewhereinthesignalpathtorestorethesignal.
OPnONn5050100+–06365-062AD8117/AD8118Figure68.
ExampleofBackTerminatedDifferentialLoadSingle-EndedOutputUsageTheAD8117/AD8118outputpairscanbeusedsingle-endedly,takingonlyoneoutputandnotusingthesecond.
Thisisoftendesiredtoreducetheroutingcomplexityinthedesign,orbecauseasingle-endedloadisbeingdrivendirectly.
Thismodeofoperationproducesgoodresults,buthassomeshortcomingswhencomparedtotakingtheoutputdifferentially.
Whenobservingthesingle-endedoutput,noisethatiscommontobothoutputsappearsintheoutputsignal.
Thisincludesthermalnoiseinthechipbiasing,aswellascrosstalkthatiscoupledintothesignalpath.
Thiscomponentnoiseandcrosstalkisequalinbothoutputs,andassuchcanbeignoredbyadifferentialreceiverwithahighcommon-moderejectionratio.
However,whentakingtheoutputsingle-ended,thisnoiseispresentwithrespecttotheground(orVOCM)referenceandisnotrejected.
Whenobservingtheoutputsingle-ended,thedistributionofoffsetvoltagesappearsgreater.
Inthedifferentialcase,thedifferencebetweentheoutputswhenthedifferencebetweentheinputsiszeroisasmalldifferentialoffset.
Thisoffsetiscreatedfrommismatchesincomponentsofthesignalpath,whichmustbecorrectedbythefinitedifferentialloopgainofthedevice.
Inthesingle-endedcase,thisdifferentialoffsetisstillobserved,butanadditionaloffsetcomponentisalsorelevant.
Thisadditionalcomponentisthecommon-modeoffset,whichisadifferencebetweentheaverageoftheoutputsandtheVOCMreference.
Thisoffsetiscreatedbymismatchesthataffectthesignalpathinacommon-modemanner,andiscorrectedbythefinitecommon-modeloopgainofthedevice.
Adifferentialreceiverwouldrejectthiscommon-modeoffsetvoltage,butinthesingle-endedcase,thisoffsetisobservedwithrespecttothesignalground.
Thesingle-endedoutputsumshalfthedifferentialoffsetvoltageandallofthecommon-modeoffsetvoltageforanetincreaseinobservedoffset.
Single-EndedGainTheAD8117/AD8118operateasaclosed-loopdifferentialamplifier.
Theprimarycontrolloopforcesthedifferencebetweentheoutputterminalstobearatioofthedifferencebetweentheinputterminals.
Oneoutputincreasesinvoltage,whiletheotherdecreasesanequalamounttomakethetotaldifferencecorrect.
TheaverageoftheseoutputvoltagesisforcedtobeequaltothevoltageontheVOCMterminalbyasecondcontrolloop.
IfonlyoneoutputterminalisobservedwithrespecttotheVOCMterminal,onlyhalfofthedifferencevoltageisobserved.
Thisimpliesthatwhenusingonlyoneoutputofthedevice,halfofthedifferentialgainisobserved.
AnAD8117takenwithsingle-endedoutputappearstohaveagainof+0.
5.
AnAD8118hasasingle-endedgainof+1.
Thisfactorofonehalfinthegainincreasesthenoiseofthedevicewhenreferredtotheinput,contributingtohighernoisespecificationsforsingle-endedoutputdesigns.
AD8117/AD8118DataSheetRev.
B|Page30of36TerminationWhenoperatingtheAD8117/AD8118withasingle-endedoutput,thepreferredoutputterminationschemeisaresistorattheloadendtotheVOCMvoltage.
Abackterminationcanbeused,atanadditionalcostofonehalfthesignalgain.
Insingle-endedoutputoperation,thecomplementaryphaseoftheoutputisnotused,andmayormaynotbeterminatedlocally.
Althoughtheunusedoutputcanbefloatedtoreducepowerdissipation,thereareseveralreasonsforterminatingtheunusedoutputwithaloadresistancematchedtotheloadonthesignaloutput.
Onecomponentofcrosstalkismagnetic,couplingbymutualinductancebetweenoutputpackagetracesandbondwiresthatcarryloadcurrent.
Inadifferentialdesign,thereiscouplingfromonepairofoutputstootheradjacentpairsofoutputs.
Thedifferentialnatureoftheoutputsignalsimultaneouslydrivesthecouplingfieldinonedirectionforonephaseoftheoutput,andinanoppositedirectionfortheotherphaseoftheoutput.
Thesemagneticfieldsdonotcoupleexactlyequalintoadjacentoutputpairsduetodifferentproximities,buttheydodestructivelycancelthecrosstalktosomeextent.
Iftheloadcurrentineachoutputisequal,thiscancellationisgreater,andlessadjacentcrosstalkisobserved(regardlessifthesecondoutputisactuallybeingused).
Asecondbenefitofbalancingtheoutputloadsinadifferentialpairistoreducefluctuationsincurrentrequirementsfromthepowersupply.
Insingle-endedloads,theloadcurrentsalternatefromthepositivesupplytothenegativesupply.
Thiscreatesaparasiticsignalvoltageinthesupplypinsduetothefiniteresistanceandinductanceofthesupplies.
Thissupplyfluctuationappearsascrosstalkinalloutputs,attenuatedbythepowersupplyrejectionratio(PSRR)ofthedevice.
Atlowfrequencies,thisisanegligiblecomponentofcrosstalk,butPSRRfallsoffasfrequencyincreases.
Withdifferential,balancedloads,asoneoutputdrawscurrentfromthepositivesupply,theotheroutputdrawscurrentfromthenegativesupply.
Whenthephasealternates,thefirstoutputdrawscurrentfromthenegativesupplyandthesecondfromthepositivesupply.
Theeffectisthatamoreconstantcurrentisdrawnfromeachsupply,suchthatthecrosstalk-inducingsupplyfluctuationisminimized.
Athirdbenefitofdrivingbalancedloadscanbeseenifoneconsidersthattheoutputpulseresponsechangesasloadchanges.
ThedifferentialsignalcontrolloopintheAD8117/AD8118forcesthedifferenceoftheoutputstobeafixedratiotothedifferenceoftheinputs.
Ifthetwooutputresponsesaredifferentduetoloading,thiscreatesadifferencethatthecontrolloopseesassignalresponseerror,anditattemptstocorrectthiserror.
Thisdistortstheoutputsignalfromtheidealresponseifthetwooutputswerebalanced.
OPnONn757515006365-063AD8117/AD8118Figure69.
ExampleofBackTerminatedSingle-EndedLoadDecouplingThesignalpathoftheAD8117/AD8118isbasedonhighopen-loopgainamplifierswithnegativefeedback.
Dominant-polecompensationisusedon-chiptostabilizetheseamplifiersovertherangeofexpectedappliedswingandloadconditions.
Toguaranteethisdesignedstability,propersupplydecouplingisnecessarywithrespecttoboththedifferentialcontrolloopsandthecommon-modecontrolloopsofthesignalpath.
Signal-generatedcurrentsmustreturntotheirsourcesthroughlowimpedancepathsatallfrequenciesinwhichthereisstillloopgain(upto700MHzataminimum).
AwidebandparallelcapacitorarrangementisnecessarytoproperlydecoupletheAD8117/AD8118.
ThesignalpathcompensationcapacitorsintheAD8117/AD8118areconnectedtotheVNEGsupply.
Athighfrequencies,thislimitsthepowersupplyrejectionratio(PSRR)fromtheVNEGsupplytoalowervaluethanthatfromtheVPOSsupply.
Ifgivenachoice,designanapplicationboardsuchthattheVNEGpowerissuppliedfromalowinductanceplane,subjecttoaleastamountofnoise.
ConsidertheVOCMareferencepinandnotapowersupply.
Itisaninputtothehighspeed,highgaincommon-modecontrolloopofallreceiversandoutputdrivers.
Inthesingle-endedoutputsense,thereisnorejectionfromnoiseontheVOCMnettotheoutput.
Forthisreason,caremustbetakentoproducealownoiseVOCMsourceovertheentirerangeoffrequenciesofinterest.
Thisisnotonlyimportanttosingle-endedoperation,buttodifferentialoperation,asthereisacommon-modetodifferentialgainconversionthatbecomesgreaterathigherfrequencies.
DuringoperationoftheAD8117/AD8118,transientcurrentsflowintotheVOCMnetfromtheamplifiercontrolloops.
Althoughthemagnitudeofthesecurrentsaresmall(10μAto20μAperoutput),theycancontributetocrosstalkiftheyflowthroughsignificantimpedances.
DrivingVOCMwithalowimpedance,lownoisesourceisdesirable.
DataSheetAD8117/AD8118Rev.
B|Page31of36PowerDissipationCalculationofPowerDissipation841585MAXIMUMPOWER(W)AMBIENTTEMPERATURE(°C)TJ=150°C76525354555657506365-064Figure70.
MaximumDiePowerDissipationvs.
AmbientTemperatureThecurveinFigure70wascalculatedfromJAAMBIENTMAXJUNCTIONMAXDTTP,,(1)Asanexample,iftheAD8117/AD8118isenclosedinanenvi-ronmentat45°C(TA),thetotalon-chipdissipationunderallloadandsupplyconditionsmustnotbeallowedtoexceed7.
0W.
Whencalculatingon-chippowerdissipation,itisnecessarytoincludethermscurrentbeingdeliveredtotheload,multipliedbythermsvoltagedropontheAD8117/AD8118outputdevices.
Forasinusoidaloutput,theon-chippowerdissipationduetotheloadcanbeapproximatedbyRMSOUTPUTRMSUTPUTOPOSOUTPUTDIVVP,,,Fornonsinusoidaloutput,calculatethepowerdissipationbyintegratingtheon-chipvoltagedropmultipliedbytheloadcurrentoveroneperiod.
TheusercansubtractthequiescentcurrentfortheClassABoutputstagewhencalculatingtheloadedpowerdissipation.
Foreachoutputstagedrivingaload,subtractaquiescentpoweraccordingtoQUIESCENTOUTPUTNEGPOSOUTPUTDQIVVP,,whereIOUTPUT,QUIESCENT=1.
65mAforeachsingle-endedoutputpin.
Foreachdisabledoutput,thequiescentpowersupplycurrentinVPOSandVNEGdropsbyapproximately9mA.
QNPNQPNPVNEGVPOSVOUTPUTIOUTPUTIOUTPUT,QUIESCENTIOUTPUT,QUIESCENT06365-065Figure71.
SimplifiedOutputStageExampleFortheAD8117/AD8118,inanambienttemperatureof85°C,withall32outputsdriving1Vrmsinto100Ωloadsandpowersuppliesat±2.
5V,followthesesteps:1.
CalculatepowerdissipationofAD8117/AD8118usingdatasheetquiescentcurrents.
DisregardVDDcurrent,asitisinsignificant.
VNEGNEGVPOSPOSQUIESCENTDIVIVP,W5.
2mA500V5.
2mA500V5.
2,QUIESCENTDP2.
Calculatepowerdissipationfromloads.
Foradifferentialoutputandground-referencedload,theoutputpowerissymmetricalineachoutputphase.
RMSOUTPUTRMSOUTPUTPOSOUTPUTDIVVP,,,mW15Ω100/V1V1V5.
2,OUTPUTDPThereare32outputpairs,or64outputcurrents.
W96.
0mW1564,OUTPUTDnP3.
Subtractthequiescentoutputstagecurrentfornumberofloads(64inthisexample).
Theoutputstageiseitherstanding,ordrivingaload,butthecurrentonlyneedstobecountedonce(validforoutputvoltages>0.
5V).
QUIESCENTOUTPUTNEGPOSOUTPUTDQIVVP,,mW25.
8mA65.
1V)5.
2(V5.
2,OUTPUTDQPThereare32outputpairs,or64outputcurrents.
W53.
0mW25.
864,OUTPUTDQnP4.
Verifythatthepowerdissipationdoesnotexceedmaximumallowedvalue.
OUTPUTDQOUTPUTDQUIESCENTDCHIPONDnPnPPP,,,,W9.
2W53.
0W96.
0W5.
2,CHIPONDPFromFigure70orEquation1,thispowerdissipationisbelowthemaximumalloweddissipationforallambienttemperaturesuptoandincluding85°C.
AD8117/AD8118DataSheetRev.
B|Page32of36Short-CircuitOutputConditionsAlthoughthereisshort-circuitcurrentprotectionontheAD8117/AD8118outputs,theoutputcurrentcanreachvaluesof80mAintoagroundedoutput.
Anysustainedoperationwithtoomanyshortedoutputscanexceedthemaximumdietemperatureandcanresultindevicefailure(seetheAbsoluteMaximumRatingssection).
CrosstalkManysystems,suchasbroadcastvideoandKVMswitches,thathandlenumerousanalogsignalchannels,havestrictrequirementsforkeepingthevarioussignalsfrominfluencinganyoftheothersinthesystem.
Crosstalkisthetermusedtodescribethecouplingofthesignalsofothernearbychannelstoagivenchannel.
Whentherearemanysignalsincloseproximityinasystem,asisundoubtedlythecaseinasystemthatusestheAD8117/AD8118,thecrosstalkissuescanbequitecomplex.
Agoodunderstandingofthenatureofcrosstalkandsomedefinitionoftermsisrequiredtospecifyasystemthatusesoneormorecrosspointdevices.
TypesofCrosstalkCrosstalkcanbepropagatedbymeansofanyofthreemethods.
Thesefallintothecategoriesofelectricfield,magneticfield,andsharingofcommonimpedances.
Thissectionexplainstheseeffects.
Everyconductorcanbebotharadiatorofelectricfieldsandareceiverofelectricfields.
Theelectricfieldcrosstalkmechanismoccurswhentheelectricfieldcreatedbythetransmitterpropagatesacrossastraycapacitance(forexamplefreespace),coupleswiththereceiver,andinducesavoltage.
Thisvoltageisanunwantedcrosstalksignalinanychannelthatreceivesit.
Currentsflowinginconductorscreatemagneticfieldsthatcirculatearoundthecurrents.
Thesemagneticfieldsthengeneratevoltagesinanyotherconductorswhosepathstheylink.
Theundesiredinducedvoltagesintheseotherchannelsarecrosstalksignals.
Thechannelsthatcrosstalkcanbesaidtohaveamutualinductancethatcouplessignalsfromonechanneltoanother.
Variouschannelsgenerallysharethepowersupplies,grounds,andothersignalreturnpathsofamultichannelsystem.
Whenacurrentfromonechannelflowsinoneofthesepaths,avoltagethatisdevelopedacrosstheimpedancebecomesaninputcrosstalksignalforotherchannelsthatsharethecommonimpedance.
Allthesesourcesofcrosstalkarevectorquantities;therefore,themagnitudescannotsimplybeaddedtogethertoobtainthetotalcrosstalk.
Infact,thereareconditionswheredrivingadditionalcircuitsinparallelinagivenconfigurationcanactuallyreducethecrosstalk.
BecausetheAD8117/AD8118arefullydifferentialdesigns,manysourcesofcrosstalkeitherdestructivelycancel,orarecommonmodetothesignalandcanberejectedbyadifferentialreceiver.
AreasofCrosstalkApracticalAD8117/AD8118circuitmustbemountedtosomesortofcircuitboardtoconnectittopowersuppliesandmeasurementequipment.
Greatcarehasbeentakentocreateanevaluationboardthataddsminimumcrosstalktotheintrinsicdevice.
This,however,raisestheissuethatasystem'scrosstalkisacombinationoftheintrinsiccrosstalkofthedevicesinadditiontothecircuitboardtowhichtheyaremounted.
Itisimportanttotrytoseparatethesetwoareaswhenattemptingtominimizetheeffectofcrosstalk.
Inaddition,crosstalkcanoccuramongtheinputstoacrosspointandamongtheoutputs.
Itcanalsooccurfrominputtooutput.
Techniquesarediscussedinthefollowingsectionsfordiagnosingwhichpartofasystemiscontributingtocrosstalk.
MeasuringCrosstalkCrosstalkismeasuredbyapplyingasignaltooneormorechannelsandmeasuringtherelativestrengthofthatsignalonadesiredselectedchannel.
ThemeasurementisusuallyexpressedasdBdownfromthemagnitudeofthetestsignal.
Thecrosstalkisexpressedby=)()(log2010sAsAXTTESTSELwhere:s=jω,theLaplacetransformvariable.
ASEL(s)istheamplitudeofthecrosstalkinducedsignalintheselectedchannel.
ATEST(s)istheamplitudeofthetestsignal.
Itcanbeseenthatcrosstalkisafunctionoffrequency,butnotafunctionofthemagnitudeofthetestsignal(tofirstorder).
Inaddition,thecrosstalksignalhasaphaserelativetothetestsignalassociatedwithit.
Anetworkanalyzerismostcommonlyusedtomeasurecrosstalkoverafrequencyrangeofinterest.
Itcanprovidebothmagnitudeandphaseinformationaboutthecrosstalksignal.
Asacrosspointsystemordevicegrowslarger,thenumberoftheoreticalcrosstalkcombinationsandpermutationscanbecomeextremelylarge.
Forexample,inthecaseofthe32*32matrixoftheAD8117/AD8118,lookatthenumberofcrosstalktermsthatcanbeconsideredforasinglechannel,forexample,theinputIN00.
IN00isprogrammedtoconnecttooneoftheAD8117/AD8118outputswherethemeasurementcanbemade.
First,thecrosstalktermsassociatedwithdrivingatestsignalintoeachoftheother31inputscanbemeasuredoneatatime,whileapplyingnosignaltoIN00.
Thenthecrosstalktermsassociatedwithdrivingaparalleltestsignalintoall31otherinputscanbemeasuredtwoatatimeinallpossiblecombinations,thenthreeatatime,andsoon,until,finally,thereisonlyonewaytodriveatestsignalintoall31otherinputsinparallel.
Eachofthesecasesislegitimatelydifferentfromtheothersandmightyieldauniquevalue,dependingontheresolutionoftheDataSheetAD8117/AD8118Rev.
B|Page33of36measurementsystem,butitishardlypracticaltomeasureallthesetermsandthenspecifythem.
Inaddition,thisdescribesthecrosstalkmatrixforjustoneinputchannel.
Asimilarcrosstalkmatrixcanbeproposedforeveryotherinput.
Inaddition,ifthepossiblecombinationsandpermutationsforconnectinginputstotheotheroutputs(notusedformeasure-ment)aretakenintoconsideration,thenumbersratherquicklygrowtoastronomicalproportions.
IfalargercrosspointarrayofmultipleAD8117/AD8118sisconstructed,thenumbersgrowlargerstill.
Obviously,somesubsetofallthesecasesmustbeselectedtobeusedasaguideforapracticalmeasureofcrosstalk.
Onecommonmethodistomeasureallhostilecrosstalk;thismeansthatthecrosstalktotheselectedchannelismeasuredwhileallothersystemchannelsaredriveninparallel.
Ingeneral,thisyieldstheworstcrosstalknumber,butthisisnotalwaysthecase,duetothevectornatureofthecrosstalksignal.
Otherusefulcrosstalkmeasurementsarethosecreatedbyonenearestneighbororbythetwonearestneighborsoneitherside.
Thesecrosstalkmeasurementsaregenerallyhigherthanthoseofmoredistantchannels,sotheycanserveasaworst-casemeasureforanyotherone-channelortwo-channelcrosstalkmeasurements.
InputandOutputCrosstalkCapacitivecouplingisvoltage-driven(dV/dt),butisgenerallyaconstantratio.
Capacitivecrosstalkisproportionaltoinputoroutputvoltage,butthisratioisnotreducedbysimplyreducingsignalswings.
Attenuationfactorsmustbechangedbychangingimpedances(loweringmutualcapacitance),ordestructivecancelingmustbeutilizedbysummingequalandoutofphasecomponents.
ForhighinputimpedancedevicessuchastheAD8117/AD8118,capacitancesgenerallydominateinput-generatedcrosstalk.
Inductivecouplingisproportionaltocurrent(dI/dt),andoftenscalesasaconstantratiowithsignalvoltage,butalsoshowsadependenceonimpedances(loadcurrent).
Inductivecouplingcanalsobereducedbyconstructivecancelingofequalandoutofphasefields.
Inthecaseofdrivinglowimpedancevideoloads,outputinductancescontributehighlytooutputcrosstalk.
TheflexibleprogrammingcapabilityoftheAD8117/AD8118canbeusedtodiagnosewhethercrosstalkisoccurringmoreontheinputsideortheoutputside.
Someexamplesareillustrative.
Agiveninputpair(IN07inthemiddleforthisexample)canbeprogrammedtodriveOUT07(alsointhemiddle).
TheinputstoIN07arejustterminatedtoground(via50Ωor75Ω)andnosignalisapplied.
Alltheotherinputsaredriveninparallelwiththesametestsignal(practicallyprovidedbyadistributionamplifier),withallotheroutputsexceptOUT07disabled.
BecausegroundedIN07isprogrammedtodriveOUT07,nosignalispresent.
Anysignalthatispresentcanbeattributedtotheother15hostileinputsignals,becausenootheroutputsaredriven(theyarealldisabled).
Thus,thismethodmeasurestheallhostileinputcontributiontocrosstalkintoIN07.
Ofcourse,themethodcanbeusedforotherinputchannelsandcombinationsofhostileinputs.
Foroutputcrosstalkmeasurement,asingleinputchannelisdriven(IN00,forexample)andalloutputsotherthanagivenoutput(IN07inthemiddle)areprogrammedtoconnecttoIN00.
OUT07isprogrammedtoconnecttoIN15(farawayfromIN00),whichisterminatedtoground.
Thus,OUT07doesnothaveasignalpresentbecauseitislisteningtoaquietinput.
AnysignalmeasuredattheOUT07canbeattributedtotheoutputcrosstalkoftheother16hostileoutputs.
Again,thismethodcanbemodifiedtomeasureotherchannelsandothercrosspointmatrixcombinations.
EffectofImpedancesonCrosstalkTheinputsidecrosstalkcanbeinfluencedbytheoutputimpedanceofthesourcesthatdrivetheinputs.
Thelowertheimpedanceofthedrivesource,thelowerthemagnitudeofthecrosstalk.
Thedominantcrosstalkmechanismontheinputsideiscapacitivecoupling.
Thehighimpedanceinputsdonothavesignificantcurrentflowtocreatemagneticallyinducedcrosstalk.
However,significantcurrentcanflowthroughtheinputtermi-nationresistorsandtheloopsthatdrivethem.
Thus,thePCboardontheinputsidecancontributetomagneticallycoupledcrosstalk.
Fromacircuitstandpoint,theinputcrosstalkmechanismlookslikeacapacitorcouplingtoaresistiveload.
Forlowfrequencies,themagnitudeofthecrosstalkisgivenby[]sCRXTMS*=)(log2010where:RSisthesourceresistance.
CMisthemutualcapacitancebetweenthetestsignalcircuitandtheselectedcircuit.
sistheLaplacetransformvariable.
Fromtheprecedingequation,itcanbeobservedthatthiscrosstalkmechanismhasahigh-passnature;itcanalsobeminimizedbyreducingthecouplingcapacitanceoftheinputcircuitsandloweringtheoutputimpedanceofthedrivers.
Iftheinputisdrivenfroma75Ωterminatedcable,theinputcrosstalkcanbereducedbybufferingthissignalwithalowoutputimpedancebuffer.
Ontheoutputside,thecrosstalkcanbereducedbydrivingalighterload.
AlthoughtheAD8117/AD8118arespecifiedwithexcellentdifferentialgainandphasewhendrivingastandard150Ωvideoload,thecrosstalkishigherthantheminimumobtainableduetothehighoutputcurrents.
ThesecurrentsAD8117/AD8118DataSheetRev.
B|Page34of36inducecrosstalkviathemutualinductanceoftheoutputpinsandbondwiresoftheAD8117/AD8118.
Fromacircuitstandpoint,thisoutputcrosstalkmechanismlookslikeatransformerwithamutualinductancebetweenthewindingsthatdrivealoadresistor.
Forlowfrequencies,themagnitudeofthecrosstalkisgivenbyLXYRsMXT10log20where:MXYisthemutualinductanceofOutputXtoOutputY.
RListheloadresistanceonthemeasuredoutput.
ThiscrosstalkmechanismcanbeminimizedbykeepingthemutualinductancelowandincreasingRL.
Themutualinductancecanbekeptlowbyincreasingthespacingoftheconductorsandminimizingtheirparallellength.
PCBLayoutExtremecaremustbeexercisedtominimizeadditionalcrosstalkgeneratedbythesystemcircuitboard(s).
Theareasthatmustbecarefullydetailedaregrounding,shielding,signalrouting,andsupplybypassing.
ThepackagingoftheAD8117/AD8118isdesignedtohelpkeepthecrosstalktoaminimum.
OntheBGAsubstrate,eachpairiscarefullyroutedtopredominatelycoupletoeachother,withshieldingtracesseparatingadjacentsignalpairs.
Theballgridarrayisarrangedsuchthatsimilarboardroutingcanbeachieved.
Onlytheoutertworowsareusedforsignals,suchthatviascanbeusedtotaketheinputrowstoalowersignalplaneifdesired.
Theinputandoutputsignalshaveminimumcrosstalkiftheyarelocatedbetweengroundplanesonlayersaboveandbelow,andseparatedbygroundinbetween.
LocateviasasclosetotheICaspossibletocarrytheinputsandoutputstotheinnerlayer.
Theinputandoutputsignalssurfaceattheinputterminationresistorsandtheoutputseriesbackterminationresistors.
Totheextentpossible,alsoseparatethesesignalsassoonastheyemergefromtheICpackage.
PCBTerminationLayoutAsfrequenciesofoperationincrease,theimportanceofpropertransmissionlinesignalroutingbecomesmoreimportant.
ThebandwidthoftheAD8117/AD8118islargeenoughthatusinghighimpedanceroutingdoesnotprovideaflatin-bandfrequencyresponseforpracticalsignaltracelengths.
ItisnecessaryfortheusertochooseacharacteristicimpedancesuitablefortheapplicationandproperlyterminatetheinputandoutputsignalsoftheAD8117/AD8118.
Traditionally,videoapplicationshaveused75Ωsingle-endedenvironments.
RFapplicationsaregenerally50Ωsingle-ended(andboardmanufacturershavethemostexperiencewiththisapplication).
CAT-5cablingisusuallydrivenasdifferentialpairsof100Ωdifferentialimpedance.
Forflexibility,theAD8117/AD8118donotcontainon-chipterminationresistors.
Thisflexibilityinapplicationcomeswithsomeboardlayoutchallenges.
Thedistancebetweenthetermi-nationoftheinputtransmissionlineandtheAD8117/AD8118dieisahighimpedancestub,andcausesreflectionsoftheinputsignal.
Withsomesimplification,itcanbeshownthatthesereflectionscausepeakingoftheinputatregularintervalsinfrequency,dependentonthepropagationspeed(VP)ofthesignalinthechosenboardmaterialandthedistance(d)betweentheterminationresistorandtheAD8117/AD8118.
Ifthedistanceisgreatenough,thesepeakscanoccurin-band.
Infact,practicalexperienceshowsthatthesepeaksarenothigh-Q,andmustbepushedouttothreeorfourtimesthedesiredbandwidthtonothaveaneffectonthesignal.
ForaboarddesignerusingFR4(VP=144*106m/s),thismeansplacingtheAD8117/AD8118inputnofartherthan1.
5cmaftertheterminationresistors,andpreferablyevencloser.
TheBGAsubstrateroutinginsidetheAD8117/AD8118isapproximately1cminlengthandaddstothestublength,so1.
5cmPCBroutingequatestod=2.
5*102minthecalculations.
dVnfPPEAK412wheren={0,1,2,3,…}.
Insomecases,itisdifficulttoplacetheterminationclosetotheAD8117/AD8118duetospaceconstraints,differentialrouting,andlargeresistorfootprints.
ApreferablesolutioninthiscaseistomaintainacontrolledtransmissionlinepasttheAD8117/AD8118inputsandterminatetheendoftheline.
Thisisknownasfly-bytermination.
TheinputimpedanceoftheAD8117/AD8118islargeenoughandstublengthinsidethepackageissmallenoughthatthisworkswellinpractice.
Implementationoffly-byinputterminationoftenincludesbringingthesignalinononeroutinglayer,thenpassingthroughafilledviaundertheAD8117/AD8118inputball,thenbackouttoterminationonanothersignallayer.
Inthiscase,caremustbetakentotiethereferencegroundplanestogethernearthesignalviaifthesignallayersarereferencedtodifferentgroundplanes.
OPnONnIPnINn7506365-066AD8117/AD8118Figure72.
Fly-ByInputTermination,GroundsfortheTwoTransmissionLinesShownMustbeTiedTogetherClosetotheINnPinDataSheetAD8117/AD8118Rev.
B|Page35of36IfmultipleAD8117/AD8118saredriveninparallel,afly-byinputterminationschemeisveryuseful,butthedistancefromeachAD8117/AD8118inputtothedriveninputtransmissionlineisastubthatmustbeminimizedinlengthandparasiticsusingthediscussedguidelines.
WhendrivingtheAD8117/AD8118single-endedly,theundriveninputisoftenterminatedwitharesistancetobalancetheinputstage.
Itcanbeseenthatbyterminatingtheundriveninputwitharesistorofonehalfthecharacteristicimpedance,theinputstageisperfectlybalanced(37.
5Ω,forexample,tobalancethetwoparallel75Ωterminationsonthedriveninput).
However,duetothefeedbackintheinputreceiver,thereishighspeedsignalcurrentleavingtheundriveninput.
Toterminatethishighspeedsignal,usepropertransmissionlinetechniques.
Onesolutionistoadjustthetracewidthtocreateatransmissionlineofhalfthecharacteristicimpedanceandterminatethefarendwiththisresistance(37.
5Ωina75Ωsystem).
Thisisnotoftenpracticalastracewidthsbecomelarge.
Inmostcases,thebestpracticalsolutionistoplacethehalfcharacteristicimpedanceresistorascloseaspossible(preferablylessthan1.
5cmaway)andtoreducetheparasiticsofthestub(byremovingthegroundplaneunderthestub,forexample).
Ineithercase,thedesignermustdecideifthelayoutcomplexitycreatedbyabalanced,terminatedsolutionispreferabletosimplygroundingtheundriveninputattheballwithnotrace.
Althoughtheexamplesdiscussedsofarareforinputtermination,thetheoryissimilarforoutputbacktermination.
TakingtheAD8117/AD8118asanidealvoltagesource,anydistanceofroutingbetweentheAD8117/AD8118andabackterminationresistorisanimpedancemismatchthatpotentiallycreatesreflections.
Forthisreason,alsoplacebackterminationresistorsclosetotheAD8117/AD8118.
Inpractice,becausebackterminationresistorsareserieselements,theycanbeplacedclosetotheAD8117/AD8118outputs.
GNDVOCMVDDAD8117/AD8118ON[31:0],OP[31:0]IN[31:0],IP[31:0]CLKRESETWEUPDATEDATAINDATAOUTJ3PLD_VDDPC_VDDPC_GNDSMASMAVPOSVNEGDGNDVDDVPOSVNEGCPLD5050LOGICPCPARALLELPORTIN[31:0],IP[31:0]LOGICISOLATORSJ8,W3TOW7ON[31:0],OP[31:0]ANALOG06365-067Figure73.
EvaluationBoardSimplifiedSchematicAD8117/AD8118DataSheetRev.
B|Page36of36OUTLINEDIMENSIONS*COMPLIANTTOJEDECSTANDARDSMO-192-BAN-2WITHTHEEXCEPTIONTOPACKAGEHEIGHT.
DETAILAABCDEFGHJKLMNPRTUVWYAAABAC135791115171921231346810122161820221427.
94BSCSQBOTTOMVIEWA1CORNERINDEXAREA1.
27BSCTOPVIEW31.
00BSCSQBALLA1INDICATOR0.
10MIN0.
700.
630.
561.
070.
990.
92COPLANARITY0.
200.
900.
750.
60SEATINGPLANEBALLDIAMETERDETAILA*1.
765MAX022206-A0.
25MIN(4)Figure74.
304-BallBallGridArray,ThermallyEnhanced[BGA_ED](BP-304)DimensionsshowninmillimetersORDERINGGUIDEModel1TemperatureRangePackageDescriptionPackageOptionAD8117ABPZ40°Cto+85°C304-BallBallGridArrayPackage,ThermallyEnhanced[BGA_ED]BP-304AD8117-EVALEvaluationBoardAD8118ABPZ40°Cto+85°C304-BallBallGridArrayPackage,ThermallyEnhanced[BGA_ED]BP-304AD8118-EVALEvaluationBoard1Z=RoHSCompliantPart.
2007–2016AnalogDevices,Inc.
Allrightsreserved.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
D06365-0-5/16(B)