IP8ip12

4.
25Gbps,16*16,DigitalCrosspointSwitchDataSheetADN4604Rev.
ADocumentFeedbackInformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.
However,noresponsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorotherrightsofthirdpartiesthatmayresultfromitsuse.
Specificationssubjecttochangewithoutnotice.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofAnalogDevices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
OneTechnologyWay,P.
O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:781.
329.
47002009–2013AnalogDevices,Inc.
Allrightsreserved.
TechnicalSupportwww.
analog.
comFEATURESDCto4.
25GbpsperportNRZdatarateProgrammablereceiveequalization12dBboostat2GHzCompensates40inchesofFR4at4.
25GbpsProgrammabletransmitpreemphasis/deemphasisUpto12dBboostat4.
25GbpsCompensates40inchesofFR4at4.
25GbpsLowpower:130mWperchannelat3.
3V(outputsenabled)16*16,fullydifferential,nonblockingarrayDoublerankconnectionprogrammingwithdualconnectionmapsLowjitter,typically20psFlexibleI/OsupplyrangeDC-orac-coupleddifferentialCMLinputsProgrammableCMLoutputlevelsPer-laneinputP/Npairinversionforroutingease50Ωon-chipI/OterminationSupports8b/10b,scrambledoruncodedNRZdataSerial(I2CslaveorSPI)controlinterface100-leadTQFP,Pb-freepackageAPPLICATIONSFiberopticnetworkswitchingHighspeedserialbackplaneroutingtoOC-48withFECXAUI:10GBASE-KX4GigabitEthernetoverbackplane:1000BASE-KX1*,2*,and4*FibreChannelInfiniBandDigitalvideo(HDMI,DVI,DisplayPort,3G-/HD-/SD-SDI)DatastoragenetworksFUNCTIONALBLOCKDIAGRAMEQRXTXPRE-EMPHASIS16*16SWITCHMATRIXCONNECTIONMAP0CONNECTIONMAP1SERIALINTERFACECONTROLLOGICPER-PORTOUTPUTLEVELSETTINGSOUTPUTLEVELHOOKUPTABLEADN4604VCCVEEDVCCOP[15:0]VTTON,VTTOSON[15:0]IP[15:0]VTTIE,VTTIWIN[15:0]I2C/SPIADDR1/SDISDA/SDOSCL/SCKRESETUPDATEADDR0/CS07934-001Figure1.
GENERALDESCRIPTIONTheADN4604isa16*16asynchronous,protocolagnostic,digitalcrosspointswitch,with16differentialPECL-/CML-compatibleinputsand16differentialCMLoutputs.
TheADN4604isoptimizedfornonreturn-to-zero(NRZ)sig-nalingwithdataratesofupto4.
25Gbpsperport.
Eachportoffersafixedlevelofinputequalizationandprogrammableoutputswingandoutputpreemphasis.
TheADN4604nonblockingswitchcoreimplementsa16*16crossbarandsupportsindependentchannelswitchingthroughtheserialcontrolinterface.
TheADN4604haslowlatencyandverylowchannel-to-channelskew.
AnI2CorSPIinterfaceisusedtocontrolthedeviceandpro-videaccesstoadvancedfeatures,suchasadditionallevelsofpreemphasisandoutputdisable.
TheADN4604ispackagedina100-leadTQFPpackageandoperatesfrom40°Cto+85°C.
ADN4604*PRODUCTPAGEQUICKLINKSLastContentUpdate:02/23/2017COMPARABLEPARTSViewaparametricsearchofcomparableparts.
EVALUATIONKITSADN4604EvaluationBoardDOCUMENTATIONDataSheetADN4604:XstreamTM4.
25Gbps,16x16,DigitalCrosspointSwitchDataSheetDESIGNRESOURCESADN4604MaterialDeclarationPCN-PDNInformationQualityAndReliabilitySymbolsandFootprintsDISCUSSIONSViewallADN4604EngineerZoneDiscussions.
SAMPLEANDBUYVisittheproductpagetoseepricingoptions.
TECHNICALSUPPORTSubmitatechnicalquestionorfindyourregionalsupportnumber.
DOCUMENTFEEDBACKSubmitfeedbackforthisdatasheet.
ThispageisdynamicallygeneratedbyAnalogDevices,Inc.
,andinsertedintothisdatasheet.
Adynamicchangetothecontentonthispagewillnottriggerachangetoeithertherevisionnumberorthecontentoftheproductdatasheet.
Thisdynamicpagemaybefrequentlymodified.
ADN4604DataSheetRev.
A|Page2of40TABLEOFCONTENTSFeatures1Applications.
1FunctionalBlockDiagram1GeneralDescription.
1RevisionHistory2Specifications.
3ElectricalSpecifications.
3I2CTimingSpecifications.
4SPITimingSpecifications5AbsoluteMaximumRatings.
6ESDCaution.
6PinConfigurationandFunctionDescriptions.
7TypicalPerformanceCharacteristics10TheoryofOperation16Introduction.
16Receivers.
16SwitchCore17Transmitters19Termination.
23I2CSerialControlInterface.
24Reset.
24I2CDataWrite.
24I2CDataRead.
25SPISerialControlInterface26RegisterMap28ApplicationsInformation.
32SupplySequencing34PowerDissipation.
34OutputCompliance34PrintedCircuitBoard(PCB)LayoutGuidelines36OutlineDimensions.
38OrderingGuide38REVISIONHISTORY3/13—Rev.
0toRev.
AChangestoSwitchingTimeParameterandOperatingRangeParameter,Table13ChangestoLogicCharacteristicsParameters,Table14ChangestoReceiversSection.
16ChangestoSwitchCoreSection17ChangestoTransmittersSectionandFigure4219ChangestoBasicSettingsSectionandTable11.
20ChangetoTable182910/09—Revision0:InitialVersionDataSheetADN4604Rev.
A|Page3of40SPECIFICATIONSELECTRICALSPECIFICATIONSVCC=3.
3V,VTTIx=3.
3V,VTTOx=3.
3V,DVCC=3.
3V,VEE=0V,RL=50,datarate=4.
25Gbps,ac-coupledinputsandoutputs,differentialinputswing=800mVp-p,TA=27°C,unlessotherwisenoted.
Table1.
ParameterConditionsMinTypMaxUnitDYNAMICPERFORMANCEDataRate(DR)perChannel(NRZ)DC4.
25GbpsDeterministicJitterDatarate=4.
25Gbps,nochannel20psp-pRandomJitterRMS,nochannel1psrmsResidualDeterministicJitterwithReceiveEqualizationDatarate=4.
25Gbps,20in.
FR4,EQboost=12dB27psp-pDatarate=4.
25Gbps,30in.
FR4,EQboost=12dB43psp-pDatarate=4.
25Gbps,40in.
FR4,EQboost=12dB70psp-pResidualDeterministicJitterwithTransmitPreemphasisDatarate=4.
25Gbps,20in.
FR4,PEboost=4.
2dB23psp-pDatarate=4.
25Gbps,30in.
FR4,PEboost=6dB25psp-pDatarate=4.
25Gbps,40in.
FR4,PEboost=6dB35psp-pPropagationDelayInputtooutput,EQboost=12dB800psChannel-to-ChannelSkew±50psSwitchingTimeMeasuredfromVILleveloffallingedgeofupdateto50%ofoutputsignaltransition100nsOutputRise/FallTime20%to80%75psINPUTCHARACTERISTICSDifferentialInputVoltageSwingVICM1=VCC0.
6V;VCC=VMINtoVMAX,TA=TMINtoTMAX2002000mVp-pdiffInputVoltageRangeSingle-endedabsolutevoltagelevel,VLVEE+1.
1VSingle-endedabsolutevoltagelevel,VHVCC+0.
3VOUTPUTCHARACTERISTICSOutputVoltageSwingDifferential,PEboost=0dB,defaultoutputlevel,atdc600800900mVp-pdiffOutputVoltageRangeSingle-endedabsolutevoltagelevel,VLVCC–1.
3VSingle-endedabsolutevoltagelevel,VHVCC+0.
2VPer-PortOutputCurrentPEboost=0dB,defaultoutputlevel16mAPEboost=6dB,defaultoutputlevel32mATERMINATIONCHARACTERISTICSResistanceSingle-ended,VCC=2.
7Vto3.
6V,VTTI=2.
2Vto3.
6V,VTTO=2.
2Vto3.
6V,TA=TMINtoTMAX;445056TemperatureCoefficient0.
025/°CPOWERSUPPLYOperatingRangeVCCVEE=0V2.
73.
33.
6VDVCCVEE=0V2.
73.
33.
6VVTTIE,VTTIWVEE=0V,VCC=3.
3V1.
33.
3VCC+0.
3VVTTON,VTTOSVEE=0V,VCC=3.
3V2.
223.
3VCC+0.
3VSupplyCurrentOutputsdisabledICC95110mAIDVCC2035mAITTIE+ITTIW+ITTON+ITTOS010mASupplyCurrentAlloutputsenabled,ac-coupledI/O,400mVI/Oswings(800mVp-pdifferential),PEboost=0dB,50Ωfar-endterminationsICC342370mAIDVCC2035mAITTIE+ITTIW+ITTON+ITTOS256280mASupplyCurrentAlloutputsenabled,ac-coupledI/O,400mVI/Oswings(800mVp-pdifferential),PEboost=6dB,50Ωfar-endterminationsICC486540mAIDVCC2035mAITTIE+ITTIW+ITTON+ITTOS512540mAADN4604DataSheetRev.
A|Page4of40ParameterConditionsMinTypMaxUnitTHERMALCHARACTERISTICSOperatingTemperatureRange40+85°CθJAStillair;JEDEC4-layertestboard24.
9°C/WθJBStillair11.
6°C/WθJCAttheexposedpad0.
95°C/WLOGICCHARACTERISTICSInputHighVoltageThreshold(VIH)DVCC=3.
3V0.
7*DVCCDVCCVInputLowVoltageThreshold(VIL)DVCC=3.
3VVEE0.
3*DVCCVOutputHighVoltage(VOH)2kΩpull-upresistortoDVCCDVCCVOutputLowVoltage(VOL)IOL=3mAVEE0.
4V1VICMistheinputcommon-modevoltage.
2MinimumVTTOisonlyapplicableforalimitedrangeofoutputcurrentsettings.
RefertothePowerDissipationsection.
I2CTIMINGSPECIFICATIONS07934-002SPSrSSDASCLtftftftftBUFtLOWtHD:STAtHD:DATtHIGHtSU:DATtSU:STAtSU:STOtHD:STAFigure2.
I2CTimingDiagramTable2.
I2CTimingSpecificationsParameterSymbolMinMaxUnitSCLClockFrequencyfSCL0400+kHzHoldTimeforaStartConditiontHD;STA0.
6μsSetupTimeforaRepeatedStartConditiontSU;STA0.
6μsLowPeriodoftheSCLClocktLOW1.
3μsHighPeriodoftheSCLClocktHIGH0.
6μsDataHoldTimetHD;DAT0μsDataSetupTimetSU;DAT10nsRiseTimeforBothSDAandSCLtr1300nsFallTimeforBothSDAandSCLtf1300nsSetupTimeforStopConditiontSU;STO0.
6μsBus-FreeTimeBetweenaStopConditionandaStartConditiontBUF1nsBusIdleTimeAfteraReset10nsResetPulseWidth10nsDataSheetADN4604Rev.
A|Page5of40SPITIMINGSPECIFICATIONSt1t2t3t5t6t4t8t7A7CSSCKSDISDOA6A5A4A3A2A1A0D7D6D5D4D3D2D1D0XXXXXXXXXXXXXXXX07934-003Figure3.
SPIWriteTimingDiagramt1t2t9t3t5t6t4t7t8A7CSSCKSDIA6A5A4A3A2A1A0D7D6D5D4D3D2D1D0XSDOXXXXXXXD7D6D5D4D3D2D1D007934-004Figure4.
SPIReadTimingDiagramTable3.
SPITimingSpecificationsParameterSymbolMinMaxUnitSCKClockFrequencyfSCK010MHzCStoSCLKSetupTimet110nsSCLKHighPulseWidtht240nsSCLKLowPulseWidtht340nsDataAccessTimeAfterSCLKFallingEdget435nsDataSetupTimePriortoSCLKRisingEdget520nsDataHoldTimeAfterSCLKRisingEdget610nsCStoSCLKHoldTimet710nsCStoSDOHighImpedancet840nsCSHighPulseWidtht910nsADN4604DataSheetRev.
A|Page6of40ABSOLUTEMAXIMUMRATINGSTable4.
ParameterRatingVCCtoVEE3.
7VDVCCtoVEE3.
7VVTTIE,VTTIWVCC+0.
6VVTTON,VTTOSVCC+0.
6VInternalPowerDissipation14.
9WDifferentialInputVoltage2.
0VLogicInputVoltageVEE–0.
3VIP1265IN1266VEE67IP1368IN1369VTTIE70IP1471IN1472VCC73IP1574IN1575SDA/SDO07934-005NOTES1.
THEADN4604TQFPHASANEXPOSEDPADDLE(EPAD)ONTHEUNDERSIDEOFTHEPACKAGETHATAIDSINHEATDISSIPATION.
THEEPADMUSTBEELECTRICALLYCONNECTEDTOTHEVEESUPPLYPLANETOMEETTHERMALSPECIFICATIONS.
2.
SDA/SCL/ADDR1/0FORI2COPERATION.
SCK/SDO/SDI/CSFORSPIOPERATION.
Figure5.
PinConfigurationADN4604DataSheetRev.
A|Page8of40Table5.
PinFunctionDescriptionsPinNo.
MnemonicTypeDescription1RESETControlConfigurationRegistersReset,ActiveLow.
ThispinisnormallypulleduptoDVCC.
2IP0InputHighSpeedInput.
3IN0InputHighSpeedInputComplement.
4,13,22,35,41,54,63,72,85,91VCCPowerPositiveSupply.
5IP1InputHighSpeedInput.
6IN1InputHighSpeedInputComplement.
7,19VTTIWPowerInputTerminationSupply(West).
ThesepinsarenormallytiedtotheVTTIEpins.
8IP2InputHighSpeedInput.
9IN2InputHighSpeedInputComplement.
10,16,29,38,47,60,66,79,88,97,EPADVEEPowerNegativeSupply.
11IP3InputHighSpeedInput.
12IN3InputHighSpeedInputComplement.
14IP4InputHighSpeedInput.
15IN4InputHighSpeedInputComplement.
17IP5InputHighSpeedInput.
18IN5InputHighSpeedInputComplement.
20IP6InputHighSpeedInput.
21IN6InputHighSpeedInputComplement.
23IP7InputHighSpeedInput.
24IN7InputHighSpeedInputComplement.
25UPDATEControlSecondRankWriteEnable,ActiveLow.
ThispinisnormallypulleduptoDVCC.
26I2C/SPIControlI2C/SPIControlInterfaceSelection,I2CActiveLow.
27OP0OutputHighSpeedOutput.
28ON0OutputHighSpeedOutputComplement.
30OP1OutputHighSpeedOutput.
31ON1OutputHighSpeedOutputComplement.
32,44VTTOSPowerOutputTerminationSupply(South).
ThesepinsarenormallytiedtotheVTTONpins.
33OP2OutputHighSpeedOutput.
34ON2OutputHighSpeedOutputComplement.
36OP3OutputHighSpeedOutput.
37ON3OutputHighSpeedOutputComplement.
39OP4OutputHighSpeedOutput.
40ON4OutputHighSpeedOutputComplement.
42OP5OutputHighSpeedOutput.
43ON5OutputHighSpeedOutputComplement.
45OP6OutputHighSpeedOutput.
46ON6OutputHighSpeedOutputComplement.
48OP7OutputHighSpeedOutput.
49ON7OutputHighSpeedOutputComplement.
50ADDR1/SDIControlI2CSlaveAddressBit1(MSB)orSPIDataInput.
51ADDR0/CSControlI2CSlaveAddressBit0(LSB)orSPIChipSelect(ActiveLow).
52IP8InputHighSpeedInput.
53IN8InputHighSpeedInputComplement.
55IP9InputHighSpeedInput.
56IN9InputHighSpeedInputComplement.
DataSheetADN4604Rev.
A|Page9of40PinNo.
MnemonicTypeDescription57,69VTTIEPowerInputTerminationSupply(East).
ThesepinsarenormallytiedtotheVTTIWpins.
58IP10InputHighSpeedInput.
59IN10InputHighSpeedInputComplement.
61IP11InputHighSpeedInput.
62IN11InputHighSpeedInputComplement.
64IP12InputHighSpeedInput.
65IN12InputHighSpeedInputComplement.
67IP13InputHighSpeedInput.
68IN13InputHighSpeedInputComplement.
70IP14InputHighSpeedInput.
71IN14InputHighSpeedInputComplement.
73IP15InputHighSpeedInput.
74IN15InputHighSpeedInputComplement.
75SDA/SDOControlI2CDataorSPIDataOutput.
76SCL/SCKControlI2CClockorSPIClock.
77OP8OutputHighSpeedOutput.
78ON8OutputHighSpeedOutputComplement.
80OP9OutputHighSpeedOutput.
81ON9OutputHighSpeedOutputComplement.
82,94VTTONPowerOutputTerminationSupply(North).
ThesepinsarenormallytiedtotheVTTOSpins.
83OP10OutputHighSpeedOutput.
84ON10OutputHighSpeedOutputComplement.
86OP11OutputHighSpeedOutput.
87ON11OutputHighSpeedOutputComplement.
89OP12OutputHighSpeedOutput.
90ON12OutputHighSpeedOutputComplement.
92OP13OutputHighSpeedOutput.
93ON13OutputHighSpeedOutputComplement.
95OP14OutputHighSpeedOutput.
96ON14OutputHighSpeedOutputComplement.
98OP15OutputHighSpeedOutput.
99ON15OutputHighSpeedOutputComplement.
100DVCCPowerDigitalPositiveSupply.
ADN4604DataSheetRev.
A|Page10of40TYPICALPERFORMANCECHARACTERISTICSVCC=3.
3V,VTTIx=3.
3V,VTTOx=3.
3V,DVCC=3.
3V,VEE=0V,RL=50Ω,datarate=4.
25Gbps,ac-coupledinputsandoutputs,differentialinputswing=800mVp-p,TA=27°C,unlessotherwisenoted.
50CABLES22HIGHSPEEDSAMPLINGOSCILLOSCOPE50CABLES2250ADN4604AC-COUPLEDEVALUATIONBOARDINPUTPINOUTPUTPINPATTERNGENERATORDATAOUTTP2TP107934-0060.
167IU/DIV200mV/DIVREFERENCEEYEDIAGRAMATTP1Figure6.
StandardTestCircuit200mV/DIV0.
167IU/DIV07934-007Figure7.
3.
25GbpsInputEye(TP1fromFigure6)200mV/DIV0.
167IU/DIV07934-008Figure8.
4.
25GbpsInputEye(TP1fromFigure6)200mV/DIV0.
167IU/DIV07934-009Figure9.
3.
25GbpsOutputEye(TP2fromFigure6)200mV/DIV0.
167IU/DIV07934-010Figure10.
4.
25GbpsOutputEye(TP2fromFigure6)DataSheetADN4604Rev.
A|Page11of4050CABLES22TP3HIGHSPEEDSAMPLINGOSCILLOSCOPE50CABLES2250ADN4604AC-COUPLEDEVALUATIONBOARDINPUTPINOUTPUTPINPATTERNGENERATORDATAOUTTP150CABLES22TP2FR4TESTBACKPLANEDIFFERENTIALSTRIPLINETRACES8milsWIDE,8milsSPACE,8milsDIELECTRICHEIGHTLENGTHS=10INCHES,20INCHES,30INCHES,40INCHES0.
167IU/DIV200mV/DIVREFERENCEEYEDIAGRAMATTP107934-011Figure11.
EqualizationTestCircuit200mV/DIV0.
167IU/DIV07934-012Figure12.
4.
25GbpsInputEye,20InchFR4InputChannel(TP2fromFigure11)200mV/DIV0.
167IU/DIV07934-013Figure13.
4.
25GbpsInputEye,40-InchFR4InputChannel(TP2fromFigure11)200mV/DIV0.
167IU/DIV07934-014Figure14.
4.
25GbpsOutputEye,20-InchFR4InputChannel,EQ=12dB(TP3fromFigure11)200mV/DIV0.
167IU/DIV07934-015Figure15.
4.
25GbpsOutputEye,40-InchFR4InputChannel,EQ=12dB(TP3fromFigure11)ADN4604DataSheetRev.
A|Page12of4050CABLES22TP3HIGHSPEEDSAMPLINGOSCILLOSCOPE50CABLES2250ADN4604AC-COUPLEDEVALUATIONBOARDINPUTPINOUTPUTPINPATTERNGENERATORDATAOUTTP150CABLES22TP2FR4TESTBACKPLANEDIFFERENTIALSTRIPLINETRACES8milsWIDE,8milsSPACE,8milsDIELECTRICHEIGHTLENGTHS=10INCHES,20INCHES,30INCHES,40INCHES07934-0160.
167IU/DIV200mV/DIVREFERENCEEYEDIAGRAMATTP1Figure16.
PreemphasisTestCircuit200mV/DIV0.
167IU/DIV07934-017Figure17.
4.
25GbpsOutputEye,20-InchFR4OutputChannel,PE=0dB(TP3fromFigure16)200mV/DIV0.
167IU/DIV07934-018Figure18.
4.
25GbpsOutputEye,40-InchFR4InputChannel,PE=0dB(TP3fromFigure16)200mV/DIV0.
167IU/DIV07934-019Figure19.
4.
25GbpsOutputEye,20-InchFR4InputChannel,PE=4.
2dB(TP3fromFigure16)200mV/DIV0.
167IU/DIV07934-020Figure20.
4.
25GbpsOutputEye,40-InchFR4InputChannel,PE=6dB(TP3fromFigure16)DataSheetADN4604Rev.
A|Page13of40020406080100012345DETERMINISTICJITTER(ps)DATARATE(Gbps)07934-036EQ=12dBEQ=0dBFigure21.
DeterministicJittervs.
DataRate0204060801002.
52.
62.
72.
82.
93.
03.
13.
23.
33.
43.
63.
5DETERMINISTICJITTER(ps)SUPPLYVOLTAGE(V)EQ=12dBEQ=0dB07934-034Figure22.
DeterministicJittervs.
SupplyVoltage020406080100–40–20020406080DETERMINISTICJITTER(ps)TEMPERATURE(°C)07934-035EQ=0dBEQ=12dBFigure23.
DeterministicJittervs.
Temperature01002003004005006007008009001000012345EYEHEIGHT(mVp-pDIFF)DATARATE(Gbps)07934-029Figure24.
EyeHeightvs.
DataRate010020030040050060070080090010002.
72.
82.
93.
03.
13.
23.
33.
43.
53.
6EYEHEIGHT(mVp-pDIFF)SUPPLYVOLTAGE(V)07934-028Figure25.
EyeHeightvs.
SupplyVoltage01002003004005006007008009001000–40–1510356085EYEHEIGHT(mVp-pDIFF)TEMPERATURE(°C)07934-037Figure26.
EyeHeightvs.
TemperatureADN4604DataSheetRev.
A|Page14of400102030405060708090100010203040DETERMINISTICJITTER(ps)INPUTFR4TRACELENGTH(Inches)07934-031EQ=12dBEQ=0dBFigure27.
DeterministicJittervs.
InputFR4ChannelLength02040608010000.
51.
01.
52.
0DETERMINISTICJITTER(ps)DIFFERENTIALINPUTSWING(Vp-p)07934-033EQ=12dBEQ=0dBFigure28.
DeterministicJittervs.
DifferentialInputSwing01020304050607080901.
82.
02.
22.
42.
62.
83.
03.
23.
43.
6DETERMINISTICJITTER(ps)OUTPUTTERMINATIONVOLTAGEVTTOx(V)07934-025OUTPUTLEVEL=1200mVp-pDIFFOUTPUTLEVEL=800mVp-pDIFFOUTPUTLEVEL=200mVp-pDIFFFigure29.
DeterministicJittervs.
OutputTerminationVoltage(VTTO)0102030405060708090100010203040506070DETERMINISTICJITTER(ps)OUTPUTFR4TRACELENGTH(Inches)0dB2dB4.
2dB6dB9.
5dB12dB07934-0307.
8dBFigure30.
DeterministicJittervs.
OutputFR4ChannelLength0204060801000.
91.
21.
51.
82.
12.
42.
73.
03.
33.
6DETERMINISTICJITTER(ps)INPUTCOMMON-MODEVOLTAGE(V)07934-032EQ=0dBEQ=12dBFigure31.
DeterministicJittervs.
InputCommon-ModeVoltage07934-0380–2–4–6–8–10–12–14–16–181G100M10M1M100k–20LOSS(dB)FREQUENCY(Hz)6"10"20"30"40"Figure32.
S21TestTracesDataSheetADN4604Rev.
A|Page15of400102030405060708090100–40–20020406080RISE/FALLTIME(ps)TEMPERATURE(°C)07934-026FALLTIMERISETIMEFigure33.
Rise/FallTimevs.
Temperature50055060065070075080085090095010002.
72.
82.
93.
03.
13.
23.
33.
43.
53.
6DELAY(ps)SUPPLYVOLTAGE(V)EQ=0EQ=12dB07934-023Figure34.
PropagationDelayvs.
SupplyVoltage0510152025750760770780790800810820830840HITSPROPAGATIONDELAY(ps)07934-021Figure35.
PropagationDelayHistogram050,000100,000150,000200,000250,000300,000350,000400,000450,000500,000–7–6–5–4–2–3–10123456SAMPLESJITTER(ps)07934-024Figure36.
RandomJitterHistogram5005506006507007508008509009501000–40–30–20–1001020304050607080DELAY(ps)TEMPERATURE(°C)EQ=0dBEQ=12dB07934-022Figure37.
PropagationDelayvs.
Temperature–50–45–40–35–30–25–20–15–10–50510M100M1G10GRETURNLOSS(dB)FREQUENCY(Hz)S11S22XAUI_SPEC07934-027Figure38.
ReturnLoss(S11,S22)ADN4604DataSheetRev.
A|Page16of40THEORYOFOPERATIONINTRODUCTIONTheADN4604isa16*16,buffered,asynchronouscrosspointswitchthatprovidesinputequalization,outputpreemphasis,andoutputlevelprogrammingcapabilities.
Thereceiversintegrateanequalizerthatisoptimizedtocompensatefortypicalbackplanelosses.
Theswitchsupportsmulticastandbroadcastoperation,allowingtheADN4604toworkinredundancyandport-replicationapplications.
Thepartoffersextensivelyprogrammableoutputlevelsandpreemphasissettings.
EQRXTXPRE-EMPHASIS16*16SWITCHMATRIXCONNECTIONMAP0CONNECTIONMAP1SERIALINTERFACECONTROLLOGICPER-PORTOUTPUTLEVELSETTINGSOUTPUTLEVELHOOKUPTABLEADN4604VCCVEEDVCCOP[15:0]VTTON,VTTOSON[15:0]IP[15:0]VTTIE,VTTIWIN[15:0]I2C/SPIADDR1/SDISDA/SDOSCL/SCKRESETUPDATEADDR0/CS07934-039Figure39.
BlockDiagramTheconfigurationofthecrosspointiscontrolledthroughaserialinterface.
ThisinterfacesupportsbothI2CandSPIprotocols,whichcanbeselectedusingtheI2C/SPIdedicatedcontrolpin.
TherearetwoI2CaddresspinsavailableasdescribedinTable6.
Table6.
SerialInterfaceControlModesPinNo.
I2C/SPI=0I2C/SPI=1PinNamePinFunctionPinNamePinFunction50ADDR1I2CAddressMSBSDISPIDataInput51ADDR0I2CAddressLSBCSSPIChipSelect75SDAI2CDataSDOSPIDataOutput76SCLI2CClockSCKSPIClockRECEIVERSTheADN4604receiverinputsincorporate50Ωterminationresistors,ESDprotection,andanequalizerthatisoptimizedforoperationoverlongbackplanetraces.
Eachreceivechannelalsoprovidesapositive/negative(P/N)inversionfunction,whichallowstheusertoswapthesignoftheinputsignalpathtoeliminatetheneedforboard-levelcrossoversinthereceiverchannel.
VCCVTTIxIPxINxVEESIMPLIFIEDRECEIVERINPUTCIRCUITRLNRLRLPRLQ1Q2I1R31kR1750R2750RN52RP5207934-040Figure40.
SimplifiedInputCircuitEqualizationTheADN4604receiverincorporatesacontinuoustimeequalizer(EQ)thatprovides12dBofhighfrequencyboosttocompensateupto40inchesofFR4at4.
25Gbps.
Eachinputhasanequalizercontrolbit.
Bydefault,theprogrammableboostissetto12dB.
Theboostcanbesetto0dBbyprogrammingaLogic0totherespectiveregisterbitforthecorrespondingchannel.
Table7.
EqualizationControlRegistersEQ[15:0]EqualizationBoost00dB112dB(default)LaneInversionThereceiverP/Ninversionisafeatureintendedtoallowtheusertoimplementtheequivalentofaboard-levelcrossoverinamuchsmallerareaandwithoutadditionalviaimpedancediscontinuitiesthatdegradethehighfrequencyintegrityofthesignalpath.
TheP/Ninversionisavailableindependentlyforeachofthe16inputchannelsandiscontrolledbywritingtotheSIGNbitoftheRXcontrolregisters(Addresses0x12andAddress0x13).
Notethatusingthisfeaturetoaccountforsignalinversionsdownstreamofthereceiverrequiresadditionalattentionwhenswitchingconnectivity.
Table8.
SignalPathPolarityControlSIGN[15:0]SignalPathPolarity0Noninverting(default)1InvertingDataSheetADN4604Rev.
A|Page17of40SWITCHCORETheADN4604switchcoreisafullynonblocking16*16arraythatallowsmulticastandbroadcastconfigurations.
Theconfig-urationoftheswitchcoreisprogrammedthroughtheserialcontrolinterface.
Thecrosspointconfigurationmapcontrolstheconnectivityoftheswitchcore.
Thecrosspointconfigurationmapconsistsofadouble-rankregisterarchitecturewhereeachrankconsistsofan8-byteconfigurationmapasshowninFigure41.
Thesecondrankregisterscontainthecurrentstateofthecrosspoint.
Thefirstrankregisterscontainthenextstate.
Eachentryintheconnectionmapstoresfourbitsperoutput,whichindicateswhichofthe16inputsareconnectedtoagivenoutput.
Anentireconnectivitymatrixcanbeprogrammedatoncebypassingdatafromthefirstrankregistersintothesecondrankregisters.
Thefirstrankregistersaretwoseparatevolatile8-bytememorybankswhichstoreconnectionconfigurationsforthecross-point.
Map0isthedefaultmapandislocatedatAddress0x90toAddress0x97.
Bydefault,Map0containsadiagonalconnectionconfigurationwherebyInput15isconnectedtoOutput0,Input14toOutput1,Input13toOutput2,andsoon.
Similarly,bydefault,Map1containstheoppositediagonalconnectionconfigurationwhereInput0isconnectedtooutput0,Input1toOutput1,andsoon.
Bothmapsareread/writeaccessibleregisters.
TheactivemapisselectedbywritingtotheXPTtableselectregister(Address0x81).
ThecrosspointisconfiguredbyaddressingtheregisterassignedtothedesiredoutputandwritingthedesiredconnectiondataintothefirstrankoflatchesineitherMap0orMap1.
Theconnectiondataisequivalenttothebinarycodedvalueoftheinputnumber.
Thisprocessisrepeateduntileachofthedesiredconnectionsisprogrammed.
Insituationswheremultipleoutputsaretobeprogrammedtoasingleinput,abroadcastcommandisavailable.
AbroadcastcommandisissuedbywritingthebinaryvalueofthedesiredinputtotheXPTbroadcastregister(Address0x82).
Thebroad-castisappliedtotheselectedmapasselectedinthemaptableselectregister(Address0x81).
Alloutputconnectionsareupdatedsimultaneouslybypassingthedatafromthefirstrankoflatchesintothesecondrankbywriting0x01totheXPTupdateregister(Address0x80).
Thisisawrite-onlyregister.
TheUPDATEpinisedgesensitive.
TheswitchingtimeofthecrosspointarrayismeasuredfromtheVILlevelofthefallingedgeoftheupdatesignaltothe50%ofthehigh-speedoutputsignaltransition.
IftheUPDATEstrobeisunused,thispinshouldbepulledhighThecurrentstateofthecrosspointconnectivityisavailablebyreadingtheXPTstatusregisters(Address0xB0toAddress0xB7).
RegisterdescriptionsfortheMap0,Map1andXPTstatusregistersareprovidedinTable9.
AcompleteregistermapisprovidedinTable18.
07934-041015015INPUTSOUTPUTSXPTCORE015015INPUTSOUTPUTSREGISTER0x90TOREGISTER0x97XPTMAP0015015INPUTSOUTPUTSREGISTER0x98TOREGISTER0x9FXPTMAP101MAPTABLESELECTREGISTER0x81XPTSTATUSREADREGISTER0xB0TOREGISTER0xB7UPDATEPINUPDATEREGISTER0x80FIRSTRANKREGISTERSSECONDRANKREGISTERSFigure41.
CrosspointConnectionMapBlockDiagramADN4604DataSheetRev.
A|Page18of40Table9.
XPTControlRegistersRegisterNameAddressBitBitNameDescriptionDefaultUpdate0x800UPDATEUpdatesXPTswitchcore(activehigh,writeonly)N/AMapTableSelect0x810MAPTABLESELECT0:Map0isselected0x001:Map1isselectedXPTBroadcast0x823:0BROADCAST[3:0]Alloutputsconnectionassignment,writeonlyN/AXPTMap0Control00x907:4OUT1[3:0]Output1connectionassignment0xEF3:0OUT0[3:0]Output0connectionassignmentXPTMap0Control10x917:4OUT3[3:0]Output3connectionassignment0xCD3:0OUT2[3:0]Output2connectionassignmentXPTMap0Control20x927:4OUT5[3:0]Output5connectionassignment0xAB3:0OUT4[3:0]Output4connectionassignmentXPTMap0Control30x937:4OUT7[3:0]Output7connectionassignment0x893:0OUT6[3:0]Output6connectionassignmentXPTMap0Control40x947:4OUT9[3:0]Output9connectionassignment0x673:0OUT8[3:0]Output8connectionassignmentXPTMap0Control50x957:4OUT11[3:0]Output11connectionassignment0x453:0OUT10[3:0]Output10connectionassignmentXPTMap0Control60x967:4OUT13[3:0]Output13connectionassignment0x233:0OUT12[3:0]Output12connectionassignmentXPTMap0Control70x977:4OUT15[3:0]Output15connectionassignment0x013:0OUT14[3:0]Output14connectionassignmentXPTMap1Control00x987:4OUT1[3:0]Output1connectionassignment0x103:0OUT0[3:0]Output0connectionassignmentXPTMap1Control10x997:4OUT3[3:0]Output3connectionassignment0x323:0OUT2[3:0]Output2connectionassignmentXPTMap1Control20x9A7:4OUT5[3:0]Output5connectionassignment0x543:0OUT4[3:0]Output4connectionassignmentXPTMap1Control30x9B7:4OUT7[3:0]Output7connectionassignment0x763:0OUT6[3:0]Output6connectionassignmentXPTMap1Control40x9C7:4OUT9[3:0]Output9connectionassignment0x983:0OUT8[3:0]Output8connectionassignmentXPTMap1Control50x9D7:4OUT11[3:0]Output11connectionassignment0xBA3:0OUT10[3:0]Output10connectionassignmentXPTMap1Control60x9E7:4OUT13[3:0]Output13connectionassignment0xDC3:0OUT12[3:0]Output12connectionassignmentXPTMap1Control70x9F7:4OUT15[3:0]Output15connectionassignment0xFE3:0OUT14[3:0]Output14connectionassignmentXPTStatus00xB07:4OUT1[3:0]Output1connectionstatus,readonly0xEF3:0OUT0[3:0]Output0connectionstatus,readonlyXPTStatus10xB17:4OUT3[3:0]Output3connectionstatus,readonly0xCD3:0OUT2[3:0]Output2connectionstatus,readonlyXPTStatus20xB27:4OUT5[3:0]Output5connectionstatus,readonly0xAB3:0OUT4[3:0]Output4connectionstatus,readonlyXPTStatus30xB37:4OUT7[3:0]Output7connectionstatus,readonly0x893:0OUT6[3:0]Output6connectionstatus,readonlyXPTStatus40xB47:4OUT9[3:0]Output9connectionstatus,readonly0x673:0OUT8[3:0]Output8connectionstatus,readonlyXPTStatus50xB57:4OUT11[3:0]Output11connectionstatus,readonly0x453:0OUT10[3:0]Output10connectionstatus,readonlyXPTStatus60xB67:4OUT13[3:0]Output13connectionstatus,readonly0x233:0OUT12[3:0]Output12connectionstatus,readonlyXPTStatus70xB77:4OUT15[3:0]Output15connectionstatus,readonly0x013:0OUT14[3:0]Output14connectionstatus,readonlyDataSheetADN4604Rev.
A|Page19of40TRANSMITTERSTheADN4604transmitteroutputsincorporate50Ωtermin-ationresistors,ESDprotection,andoutputcurrentswitches.
Eachchannelprovidesindependentcontrolofboththeabsoluteoutputlevelandthepreemphasisoutputlevel.
Notethatthechoiceofoutputlevelaffectstheoutputcommon-modelevel.
ON-CHIPTERMINATIONESDVCCVTTOxOPxONxVEEV3VCV2VPV1VNQ1ITIDC+IPEQ2RP50RN5007934-042Figure42.
SimplifiedTXOutputCircuitPreemphasisTransmissionlineattenuationcanbeequalizedatthetrans-mitterusingpreemphasis.
Thetransmitequalizersettingcanbechosenbymatchingthechannellosstotheamountofboostprovidedbythepreemphasis.
BasicSettingsInthebasicmodeofoperation,predefinedpreemphasissettingsareavailablethroughalookuptable.
Eachtableentryrequirestwobytesofmemory.
Theamountofpreemphasisprovidedisindependentofthefull-scalecurrentoutput.
Transmitterpreemphasislevels,aswellasdcoutputlevels,canbesetthroughtheserialcontrolinterface.
Theoutputlevelandamountofpreemphasiscanbeindependentlyprogrammedthroughadvancedregisters.
Bydefault,however,thetotaloutputamplitudeandpreemphasissettingspaceisreducedtoasingletableofbasicsettingsthatprovideseightlevelsofoutputequalizationtoeaseprogrammingfortypicalFR4channels.
Table10summarizestheabsoluteoutputlevel,preemphasislevel,andhighfrequencyboostforcontrolsetting.
ThefullresolutionofeightsettingsisavailablethroughtheserialinterfacebywritingtoBits[2:0](theTXPE[2:0]bits)oftheBasicTXControlregistersshowninTable11.
Asinglesettingisprogrammedtoalloutputssimultaneouslybywritingtothe0x18broadcastaddress.
TheTXhasfourpossibleoutputenablestates(disabled,standby,squelched,andenabled)controlledbytheTXEN[1:0]bitsasshowninTable11.
Disabledisthelowestpower-downstate.
Whensquelched,theoutputvoltageatbothPandNoutputswillbethecommon-modevoltageasdefinedbytheoutputcurrentsettings.
Instandby,theoutputlevelofbothPandNoutputswillbepulleduptotheterminationsupply(VTTONorVTTOS).
TheTXCTLSELECTbit(Bit6)intheTX[15:0]basiccontrolregisterdetermineswhetherthepreemphasisandoutputcurrentcontrolsforthechannelofinterestareselectedfromthepredefinedlookuptableordirectlyfromtheTX[15:0]DriveControl[1:0]registers(perchannel).
Figure43isanillustrationoftheTXcontrolcircuit.
SettingtheTXCTLSELECTbitlow(defaultsetting)selectspreemphasiscontrolfromthepredefined,optimizedlookuptable(Address0x60toAddress0x6F).
07934-043TABLEENTRY0TABLEENTRY1TABLEENTRY2TABLEENTRY3TABLEENTRY4TABLEENTRY5TABLEENTRY6TABLEENTRY716161616161616161616163PE[2:0]TXCTLSELECTIPxOPxINxONxTXPEROUTPUTPORTLOOKUPTABLEBASICSETTINGSPERPORTOUTPUTLEVELADVANCEDSETTINGSTXEN[1:0]2Figure43.
TransmitterControlBlockDiagramInapplicationswherethedefaultpreemphasissettingsinthelookuptablearenotsufficient,thelookuptableentriescanbemodifiedbyprogrammingtheTXlookuptableregisters(0x60to0x6F)showninTable12.
Inapplicationswheretheeighttableentriesareinsufficient,eachoutputcanbeprogrammedindividually.
Table10.
PreemphasisBoostandOvershootvs.
SettingPESettingMainTapCurrent(mA)DelayedTapCurrent(mA)Boost(dB)Overshoot(%)DCSwing(mVp-p)01600.
0080011622.
02580021654.
262.
580031686.
010080041187.
81455505889.
520040064612.
030030074612.
0300300ADN4604DataSheetRev.
A|Page20of40Table11displaystheTXBasicControlregister.
TheTXBasicControlregisterconsistsofonebyte(8bits)foreachofthe16outputchannels.
EachTXBasicControlregisterhasthesamefunctionality.
Themappingofregisteraddresstooutputchannelisshowninthefirstcolumn.
Alloutputscanbesimultaneouslyprogrammedwithacommonoutputlevel,pre-emphasisandenablestateusingtheTXbroadcastregisteratAddress0x18asshowninTable11.
NotethatthisoverwritesanydatapreviouslystoredinAddresses0x20to0x2F.
ThisregisteronlyaffectsthestateoftheTXBasicControlRegisterandnottheTXLookupTable,TXAdvancedControl,norXPTControlregisters.
Table11.
TXBasicControlRegisterAddress:ChannelDefaultRegisterNameBitBitNameDescription0x18:Broadcast1,0x20:Output0,0x21:Output1,0x22:Output2,0x23:Output3,0x24:Output4,0x25:Output5,0x26:Output6,0x27:Output7,0x28:Output8,0x29:Output9,0x2A:Output10,0x2B:Output11,0x2C:Output12,0x2D:Output13,0x2E:Output14,0x2F:Output150x00TXbasiccontrol6TXCTLSELECT0:PEandoutputlevelcontrolisderivedfromcommonlookuptable1:PEandoutputlevelcontrolisderivedfromperportdrivecontrolregisters5:4TXEN[1:0]00:TXdisabled,lowestpowerstate01:TXstandby.
10:TXsquelched.
11:TXenabled3ReservedReserved.
Setto0.
2:0PE[2:0]IfTXCTLSELECT=0,seeTable10000:TableEntry0001:TableEntry1010:TableEntry2011:TableEntry3100:TableEntry4101:TableEntry5110:TableEntry6111:TableEntry7IfTXCTLSELECT=1,PE[2:0]areignored1Thebroadcastregister,Address0x18,iswrite-only.
Table12displaystheTXlookuptableregister.
TheTXlookuptableregisterconsistsoftwobytes(16bits)foreachoftheeightpossibletableentriesselectedbythePE[2:0]fieldinTable11.
Themappingoftableentrytoregisteraddressisshowninthefirstcolumn.
Bydefault,theTXLookupTableregistercontainsthepreemphasissettingslistedinTable10,however,thesevaluescanbechangedforaflexibleselectionofoutputlevelsandpreemphasisboosts.
Table13listsavarietyofpossibleoutputlevelandpreemphasisboostsettingsandthecorrespondingTXDrive0andTXDrive1codes.
Table12.
TXLookupTableRegistersAddress:ChannelDefaultRegisterNameBitBitNameDescription0x60:TableEntry00xFFTXLookupTableDrive07DRVEN10:Driver1disabled1:Driver1enabled0x62:TableEntry10xFF0x64:TableEntry20xFF6:4DRVLV1[2:0]Driver1current=decimal(DRVLV1[2:0])+10x66:TableEntry30xFF0x68:TableEntry40xDC3DRVEN00:Driver0disabled1:Driver0enabled0x6A:TableEntry50xBB0x6C:TableEntry60x992:0DRVLV0[2:0]Driver0current=decimal(DRVLV0[2:0])+10x6E:TableEntry70x990x61:TableEntry00x00TXLookupTableDrive17DRVEND0:DriverDdisabled1:DriverDenabled0x63:TableEntry10x990x65:TableEntry20xCC6:4DRVLVD[2:0]DriverDCurrent=decimal(DRVLVD[2:0])+10x67:TableEntry30xFF0x69:TableEntry40xFF3DRVEN20:Driver2disabled1:Driver2enabled0x6B:TableEntry50xFF0x6D:TableEntry60xDD2:0DRVLV2[2:0]Driver2current=decimal(DRVLV2[2:0])+10x6F:TableEntry70xDDDataSheetADN4604Rev.
A|Page21of40AdvancedSettingsInadditiontothebasicsettingsprovidedintheTXbasiccontrolregisters,advancedsettingsareavailableinTXDrive0ControlandTXDrive1Controlregisters(Address0x30toAddress0x4F).
Theadvancedsettingsareusefulinapplicationswhereeachoutputrequiresanindividuallyprogrammedpreemphasisoroutputlevelsettingbeyondwhatisavailableinthelookuptableinbasicmode.
Toenabletheseadvancedsettings,settheTXCTLSELECTbitintheTXbasiccontrolregistertoalogichigh.
Next,programtheTXDrive0controlandDrive1controlregisters(Address0x30toAddress0x4F)tothedesiredoutputlevelandboostvalues.
AsubsetofpossiblesettingsisprovidedinTable13.
AnexpandedlistofavailablesettingsisshowninTable19intheApplicationsInformationsection.
TheseadvancedsettingscanalsobeusedtomodifytheTXlookuptablesettings(Address0x60toAddress0x6F).
TheadvancedsettingsregistermapisshowninTable15.
Thepreemphasisboostequationfollows.
)1(log20]dB[10VVVDCSWDCSWPESWGain(1)VTTOVH-PEVSW-PEVL-PEVL-DCVSW-DCVH-DCVOCMTPE07934-044Figure44.
SignalLevelDefinitionsTable13.
TXPreemphasisandOutputSwingAdvancedSettingsSingle-EndedOutputLevelsandPEBoostRegisterSettingsOutputCurrentVSW-DC1(mV)VSW-PE1(mV)PEBoost%PE(dB)TXDrive0TXDrive1ITTO1(mA)2002000.
000.
000xBB0x00820030050.
003.
520xBB0x991220035075.
004.
860xBB0xAA14200400100.
006.
020xBB0xBB16200450125.
007.
040xBB0xCC18200500150.
007.
960xBB0xDD20200600200.
009.
540xBB0xFF243003000.
000.
000xDD0x001230040033.
332.
500xDD0x991630045050.
003.
520xDD0xAA1830050066.
674.
440xDD0xBB2030055083.
335.
260xDD0xCC22300600100.
006.
020xDD0xDD24300700133.
337.
360xDD0xFF284004000.
000.
000xFF0x001640050025.
001.
940xFF0x992040055037.
502.
770xFF0xAA2240060050.
003.
520xFF0xBB2440065062.
504.
220xFF0xCC2640070075.
004.
860xFF0xDD28400800100.
006.
020xFF0xFF325005000.
000.
000xFF0x0B206006000.
000.
000xFF0x0F241SymboldefinitionsareshowninTable14.
Table14.
SymbolDefinitionsSymbolFormulaDefinitionIDCProgrammableOutputcurrentthatsetsoutputlevelIPEProgrammableOutputcurrentforPEdelayedtapITTOIDC+IPETotaltransmitteroutputcurrentTPEPreemphasispulsewidthVDPP-DC25Ω*IDC*2Peak-to-peakdifferentialvoltageswingofnon-preemphasizedwaveformVDPP-PE25Ω*ITTO*2Peak-to-peakdifferentialvoltageswingofpreemphasizedwaveformVSW-DCVDPP-DC/2=VH-DC–VL-DCDCsingle-endedvoltageswingVSW-PEVDPP-PE/2=VH-PE–VL-PEPreemphasizedsingle-endedvoltageswingVOCM_DC-COUPLED25Ω*ITTO/2Outputcommon-modeshift,dc-coupledoutputsVOCM_AC-COUPLED50Ω*ITTO/2Outputcommon-modeshift,ac-coupledoutputsVOCMVTTOVOCM=(VH-DC+VL-DC)/2Outputcommon-modevoltageVH-DCVTTOVOCM+VDPP-DC/2DCsingle-endedoutputhighvoltageVL-DCVTTOVOCMVDPP-DC/2DCsingle-endedoutputlowvoltageVH-PEVTTOVOCM+VDPP-PE/2Maximumsingle-endedoutputvoltageVL-PEVTTOVOCMVDPP-PE/2Minimumsingle-endedoutputvoltageVTTOOutputterminationvoltageADN4604DataSheetRev.
A|Page22of40Table15displaystheTXadvancedcontrolregisters.
TheTXadvancedcontrolregistersconsistoftwobytes(16bits)foreachofthe16outputchannels.
Themappingofregisteraddresstooutputchannelisshowninthefirstcolumn.
TheTXadvancedcontrolregistersprovidesultimateflexibilityofperportoutputlevelandpreemphasisboost.
Table13listsavarietyofpossibleoutputlevelsandpreemphasisboostsettingsandthecorrespondingTXDrive0andTXDrive1codes.
Table15.
TXAdvancedControlRegistersAddress:ChannelDefaultRegisterNameBitBitNameDescription0x30:Output0,0x32:Output1,0x34:Output2,0x36:Output3,0x38:Output4,0x3A:Output5,0x3C:Output6,0x3E:Output7,0x40:Output8,0x42:Output9,0x44:Output10,0x46:Output11,0x48:Output12,0x4A:Output13,0x4C:Output14,0x4E:Output150xFFTXDrive0control7DRVEN10:Driver1disabled1:Driver1enabled6:4DRVLV1[2:0]Driver1current=decimal(DRVLV1[2:0])+13DRVEN00:Driver0disabled1:Driver0enabled2:0DRVLV0[2:0]Driver0current=decimal(DRVLV0[2:0])+10x31:Output0,0x33:Output1,0x35:Output2,0x37:Output3,0x39:Output4,0x3B:Output5,0x3D:Output6,0x3F:Output7,0x41:Output8,0x43:Output9,0x45:Output10,0x47:Output11,0x49:Output12,0x4B:Output13,0x4D:Output14,0x4F:Output150x00TXDrive1control7DRVEND0:DriverDdisabled1:DriverDenabled6:4DRVLVD[2:0]DriverDcurrent=decimal(DRVLVD[2:0])+13DRVEN20:Driver2disabled1:Driver2enabled2:0DRVLV2[2:0]Driver2current=decimal(DRVLV2[2:0])+1DataSheetADN4604Rev.
A|Page23of40TERMINATIONTheinputsandoutputsincludeintegrated50Ωterminationresistors.
Forapplicationsthatrequireexternalterminationresistors,theinternalresistorscanbedisabled.
Forexample,disablingtheintegrated50Ωterminationresistorsallowsalternativeterminationvaluessuchas75ΩasshowninFigure45.
Notethattheintegrated50Ωterminationresistorsareoptimalforhighdataratedigitalsignaling.
Disablingtheterminationscanreducetheoverallperformance.
Theterminationcontrolisseparatedbyquadrants(North=Outputs[15:8],South=Outputs[7:0],East=Inputs[15:8],andWest=Inputs[7:0]).
Table16showstheterminationcontrolregister.
ALogic0enablestheterminationsfortherespectivequadrant.
ALogic1disablestheterminationsfortherespectivequadrant.
Theterminationsareenabledbydefault.
CML505050507575VEEVTTOx50VTTOxVCCVTTIxVTTIxADN46047575505007934-045RxFigure45.
75Ωto50ΩImpedanceTranslator.
Table16.
TerminationControlRegisterAddressDefaultRegisterNameBitBitNameDescription0xF00x00Terminationcontrol3TXN_TERMOutput[15:8](North)terminationcontrol0:Terminationsenabled1:Terminationsdisabled2TXS_TERMOutput[7:0](South)terminationcontrol0:Terminationsenabled1:Terminationsdisabled1RXE_TERMInput[15:8](East)terminationcontrol0:Terminationsenabled1:Terminationsdisabled0RXW_TERMInput[7:0](West)terminationcontrol0:Terminationsenabled1:TerminationsdisabledADN4604DataSheetRev.
A|Page24of40I2CSERIALCONTROLINTERFACETheADN4604registersetiscontrolledthrougha2-wireI2Cinterface.
TheADN4604actsonlyasanI2Cslavedevice.
Therefore,theI2CbusinthesystemneedstoincludeanI2CmastertoconfiguretheADN4604andotherI2Cdevicesthatmaybeonthebus.
TheADN4604I2Cinterfacecanberuninthestandard(100kHz)andfast(400kHz)modes.
TheSDAlineonlychangesvaluewhentheSCLpinislowwithtwoexceptions.
Toindicatethebeginningorcontinuationofatransfer,theSDApinisdrivenlowwhiletheSCLpinishigh;toindicatetheendofatransfer,theSDAlineisdrivenhighwhiletheSCLlineishigh.
Therefore,itisimportanttocontroltheSCLclocktotoggleonlywhentheSDAlineisstableunlessindicatingastart,repeatedstart,orstopcondition.
Table17.
I2CDeviceAddressAssignmentADDR1PinADDR0PinI2CDeviceAddress000x90010x92100x94110x96RESETOninitialpower-up,oratanypointinoperation,theADN4604registersetcanberestoredtothedefaultvaluesbypullingtheRESETpintolowaccordingtothespecificationinTable2.
Duringnormaloperation,however,theRESETpinmustbepulleduptoDVCC.
Asoftwareresetisavailablebywritingthevalue0x01totheResetregisteratAddress0x00.
Thisregisteriswriteonly.
I2CDATAWRITETowritedatatotheADN4604registerset,amicrocontroller,oranyotherI2Cmaster,mustsendtheappropriatecontrolsignalstotheADN4604slavedevice.
Thestepstobefollowedarelistedbelow;thesignalsarecontrolledbytheI2Cmaster,unlessotherwisespecified.
AdiagramoftheprocedureisshowninFigure46.
1.
Sendastartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow).
2.
SendtheADN4604partaddress(sevenbits)whoseupperfourbitsarethestaticvalueb10010andwhoselowerthreebitsarecontrolledbytheinputpinsI2C_A[1:0].
ThistransfershouldbeMSBfirst.
3.
Sendthewriteindicatorbit(0).
4.
WaitfortheADN4604toacknowledgetherequest.
5.
Sendtheregisteraddress(eightbits)towhichdataistobewritten.
ThistransfershouldbeMSBfirst.
6.
WaitfortheADN4604toacknowledgetherequest.
7.
Sendthedata(eightbits)tobewrittentotheregisterwhoseaddresswassetinStep5.
ThistransfershouldbeMSBfirst.
8.
WaitfortheADN4604toacknowledgetherequest.
9.
Dooneormoreofthefollowing:a.
Sendastopcondition(whileholdingtheSCLlinehigh,pulltheSDAlinehigh)andreleasecontrolofthebus.
b.
Sendarepeatedstartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow)andcontinuewithStep2ofthewriteproceduretoperformawrite.
c.
Sendarepeatedstartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow)andcontinuewithStep2ofthisproceduretoperformareadfromanotheraddress.
d.
Sendarepeatedstartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow)andcontinuewithStep8ofthereadprocedure(intheI2CDataReadsection)toperformareadfromthesameaddresssetinStep5.
TheADN4604writeprocessisshowninFigure46.
TheSCLsignalisshownalongwithageneralwriteoperationandaspecificexample.
Intheexample,data0x92iswrittentoAddress0x6DofanADN4604partwithapartaddressof0x4B.
ItisimportanttonotethattheSDAlineonlychangeswhentheSCLlineislow,exceptforthecaseofsendingastart,stop,orrepeatedstartcondition,Step1andStep9inthiscase.
STARTR/WACKACKACKSTOPDATAADDR[1:0]b10010REGISTERADDRSCLSDASDAEXAMPLE1223456789a07934-046Figure46.
I2CWriteDiagramDataSheetADN4604Rev.
A|Page25of40I2CDATAREADToreaddatafromtheADN4604registerset,amicrocontroller,oranyotherI2CmastermustsendtheappropriatecontrolsignalstotheADN4604slavedevice.
Thestepsarelistedbelow;thesignalsarecontrolledbytheI2Cmaster,unlessotherwisespecified.
AdiagramoftheprocedureisshowninFigure47.
1.
Sendastartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow).
2.
SendtheADN4604partaddress(sevenbits)whoseupperfivebitsarethestaticvalueb10010andwhoselowertwobitsarecontrolledbytheinputpinsADDR1andADDR0.
ThistransfershouldbeMSBfirst.
3.
Sendthewriteindicatorbit(0).
4.
WaitfortheADN4604toacknowledgetherequest.
5.
Sendtheregisteraddress(eightbits)fromwhichdataistoberead.
ThistransfershouldbeMSBfirst.
TheregisteraddressiskeptinmemoryintheADN4604untilthepartisresetortheregisteraddressiswrittenoverwiththesameprocedure(Step1toStep6).
6.
WaitfortheADN4604toacknowledgetherequest.
7.
Sendarepeatedstartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow).
8.
SendtheADN4604partaddress(sevenbits)whoseupperfivebitsarethestaticvalueb10010andwhoselowertwobitsarecontrolledbytheinputpinsADDR1andADDR0.
ThistransfershouldbeMSBfirst.
9.
Sendthereadindicatorbit(1).
10.
WaitfortheADN4604toacknowledgetherequest.
11.
TheADN4604thenseriallytransfersthedata(eightbits)heldintheregisterindicatedbytheaddresssetinStep5.
12.
Acknowledgethedata.
13.
Dooneormoreofthefollowing:a.
Sendastopcondition(whileholdingtheSCLlinehighpulltheSDAlinehigh)andreleasecontrolofthebus.
b.
Sendarepeatedstartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow)andcontinuewithStep2ofthewriteprocedure(seetheI2CDataWritesection)toperformawrite.
c.
Sendarepeatedstartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow)andcontinuewithStep2ofthisproceduretoperformareadfromanotheraddress.
d.
Sendarepeatedstartcondition(whileholdingtheSCLlinehigh,pulltheSDAlinelow)andcontinuewithStep8ofthisproceduretoperformareadfromthesameaddress.
TheADN4604readprocessisshowninFigure47.
TheSCLsignalisshownalongwithageneralreadoperationandaspecificexample.
Intheexample,Data0x49isreadfromAddress0x6DofanADN4604partwithapartaddressof0x4B.
ThepartaddressissevenbitswideandiscomposedoftheADN4604staticupperfivebits(b10010)andthepinprogram-mablelowertwobits(ADDR1andADDR0).
Inthisexample,theADDR1andADDR0bitsaresettob01.
InFigure47,thecorrespondingstepnumberisvisibleinthecircleunderthewaveform.
TheSCLlineisdrivenbytheI2CmasterandneverbytheADN4604slave.
AsfortheSDAline,thedataintheshadedpolygonsisdrivenbytheADN4604,whereasthedatainthenonshadedpolygonsisdrivenbytheI2Cmaster.
Theendphasecaseshownisthatof13a.
NotethattheSDAlineonlychangeswhentheSCLlineislow,exceptforthecaseofsendingastart,stop,orrepeatedstartcondition,asinStep1,Step7,andStep13.
InFigure47,AisthesameasACKinFigure46.
Equally,SrrepresentsarepeatedstartwheretheSDAlineisbroughthighbeforeSCLisraised.
SDAisthendroppedwhileSCLisstillhigh.
SCLSDASDAEXAMPLE1223456788910111213ab10010AASrDATAASTOPREGISTERADDRSTARTADDR[1:0]ADDR[1:0]b10010R/WAR/W07934-047Figure47.
I2CReadDiagramADN4604DataSheetRev.
A|Page26of40SPISERIALCONTROLINTERFACETheSPIserialinterfaceoftheADN4604consistsoffourwires:CS,SCK,SDI,andSDO.
CSisusedtoselectthedevicewhenmorethanonedeviceisconnectedtotheserialclockanddatalines.
CSisalsousedtodistinguishbetweenreadandwritecommands(seeFigure48).
SCKisusedtoclockdatainandoutofthepart.
Datacaneithercontaineightbitsofregisteraddressordata.
TheSDIlineisusedtowritetotheregisters,andtheSDOlineisusedtoreaddatabackfromtheregisters.
DataonSDIisclockedontherisingedgeofSCK.
DataonSDOchangesonthefallingedgeofSCK.
Therecommendedpull-upresistorvalueisbetween500Ωand1kΩ.
Strongpull-upsareneededwhenserialclockspeedsthatareclosetothemaximumlimitareusedorwhentheSPIinterfacelinesareexperiencinglargecapacitiveloading.
Largerresistorvaluescanbeusedforpull-upresistorswhentheserialclockspeedisreduced.
ThepartoperatesinslavemodeandrequiresanexternallyappliedserialclocktotheSCLKinput.
Theserialinterfaceisdesignedtoallowtheparttobeinterfacedtosystemsthatprovideaserialclockthatissynchronizedtotheserialdata.
WriteOperationFigure48showsthediagramforawriteoperationtotheADN4604.
DataisclockedintotheregistersontherisingedgeofSCK.
WhentheCSlineishigh,theSDIandSDOlinesareinthree-statemode.
OnlywhentheCSgoesfromhightolowdoesthepartacceptanydataontheSDIline.
Toallowcontinuouswrites,theaddresspointerregisterauto-incrementsbyonewithouthavingtoloadtheaddresspointerregistereachtime.
Subsequentdatabytesarewrittenintosequentialregisters.
Notethatnotallregistersinthe256-byteaddressspaceexistandnotallregistersarewritable.
Zeroesshouldbeenteredfornonexistingaddressfieldswhenimplementingacontinuouswriteoperation.
Address0xD0toAddress0xEFarereservedandshouldnotbeoverwritten.
AcontinuouswritesequenceisshowninFigure49.
ReadOperationFigure48showsthediagramforawriteoperationtotheADN4604.
Toreadbackfromaregister,firstwritetotheaddresspointerregisterwiththedesiredstartingaddress.
AreadcommandisdistinguishedfromawritecommandbytheoccurrenceofCSgoinghighaftertheaddresspointeriswritten.
SubsequentclockcycleswithCSassertedlowstreamdatastartingfromthedesiredregisteraddressontoSDO,MSBfirst.
SDOchangesonthefallingedgeofSCK.
MultipledatareadsarepossibleinSPIinterfacemodeastheaddresspointerregisterisauto-incremented.
AcontinuousreadsequenceisshowninFigure50.
SDIADDRESSXXXXXXXXSDODATACSWRITEOPERATIONHI-ZHI-ZREADOPERATIONSDIADDRESSDATASDOCS07934-048Figure48.
SPI—CorrectUseofCSDuringSPICommunicationsDataSheetADN4604Rev.
A|Page27of40ADDRESSDATABYTE0DATABYTE1DATABYTENCSSCKSDISDOHI-Z07934-049Figure49.
SPIContinuousWriteSequenceADDRESSXXXXXXXXXXXXXXXXXXXXXXXXCSSCKSDISDOHI-ZDATABYTE0DATABYTE1DATABYTEN07934-050Figure50.
SPIContinuousReadSequenceADN4604DataSheetRev.
A|Page28of40REGISTERMAPRegistersrepeatedperportorpertableentryaregroupedtogether.
Registeraddressmappingisshowninthefirstcolumn.
Table18.
RegisterMapAddress:ChannelDefaultRegisterNameBitBitNameDescription0x00N/ARESET0ResetSoftwarereset.
Writeonly.
0x100xFFRXEQControl07EQ[7]Equalizerboostcontrolforinput70:0dB1:12dB6EQ[6]EqualizerboostcontrolforInput65EQ[5]EqualizerboostcontrolforInput54EQ[4]EqualizerboostcontrolforInput43EQ[3]EqualizerboostcontrolforInput32EQ[2]EqualizerboostcontrolforInput21EQ[1]EqualizerboostcontrolforInput10EQ[0]EqualizerboostcontrolforInput00x110xFFRXEQControl115EQ[15]EqualizerboostcontrolforInput150:0dB1:12dB14EQ[14]EqualizerboostcontrolforInput1413EQ[13]EqualizerboostcontrolforInput1312EQ[12]EqualizerboostcontrolforInput1211EQ[11]EqualizerboostcontrolforInput1110EQ[10]EqualizerboostcontrolforInput109EQ[9]EqualizerboostcontrolforInput98EQ[8]EqualizerboostcontrolforInput80x120x00RXControl07SIGN[7]SignalpathpolarityinversionforInput70:Noninverting1:Inverting6SIGN[6]SignalpathpolarityinversionforInput65SIGN[5]SignalpathpolarityinversionforInput54SIGN[4]SignalpathpolarityinversionforInput43SIGN[3]SignalpathpolarityinversionforInput32SIGN[2]SignalpathpolarityinversionforInput21SIGN[1]SignalpathpolarityinversionforInput10SIGN[0]SignalpathpolarityinversionforInput00x130x00RXControl115SIGN[15]SignalpathpolarityinversionforInput150:Noninverting1:Inverting14SIGN[14]SignalpathpolarityinversionforInput1413SIGN[13]SignalpathpolarityinversionforInput1312SIGN[12]SignalpathpolarityinversionforInput1211SIGN[11]SignalpathpolarityinversionforInput1110SIGN[10]SignalpathpolarityinversionforInput109SIGN[9]SignalpathpolarityinversionforInput98SIGN[8]SignalpathpolarityinversionforInput8DataSheetADN4604Rev.
A|Page29of40Address:ChannelDefaultRegisterNameBitBitNameDescription0x18:Broadcast1,0x20:Output0,0x21:Output1,0x22:Output2,0x23:Output3,0x24:Output4,0x25:Output5,0x26:Output6,0x27:Output7,0x28:Output8,0x29:Output9,0x2A:Output10,0x2B:Output11,0x2C:Output12,0x2D:Output13,0x2E:Output14,0x2F:Output150x00TXbasiccontrol6TXCTLSELECT0:PEandoutputlevelcontrolisderivedfromcommonlookuptable1:PEandoutputlevelcontrolisderivedfromperportdrivecontrolregisters5:4TXEN[1:0]00:TXdisabled,lowestpowerstate01:TXstandby10:TXsquelched11:TXenabled3ReservedReserved.
Setto0.
2:0PE[2:0]IfTXCTLSELECT=0,seeTable10Selectedtableentry=decimal(PE[2:0])IfTXCTLSELECT=1,PE[2:0]areignored0x30:Output0,0x32:Output1,0x34:Output2,0x36:Output3,0x38:Output4,0x3A:Output5,0x3C:Output6,0x3E:Output7,0x40:Output8,0x42:Output9,0x44:Output10,0x46:Output11,0x48:Output12,0x4A:Output13,0x4C:Output14,0x4E:Output150xFFTXDrive0control7DRVEN10:Driver1disabled1:Driver1enabled6:4DRVLV1[2:0]Driver1current=decimal(DRVLV1[2:0])+13DRVEN00:Driver0disabled1:Driver0enabled2:0DRVLV0[2:0]Driver0current=decimal(DRVLV0[2:0])+10x31:Output0,0x33:Output1,0x35:Output2,0x37:Output3,0x39:Output4,0x3B:Output5,0x3D:Output6,0x3F:Output7,0x41:Output8,0x43:Output9,0x45:Output10,0x47:Output11,0x49:Output12,0x4B:Output13,0x4D:Output14,0x4F:Output150x00TXDrive1control7DRVEND0:DriverDdisabled1:DriverDenabled6:4DRVLVD[2:0]DriverDcurrent=decimal(DRVLVD[2:0])+13DRVEN20:Driver2disabled1:Driver2enabled2:0DRVLV2[2:0]Driver2current=decimal(DRVLV2[2:0])+10x60:TableEntry00xFFTXLookupTable07DRVEN10:Driver1disabled1:Driver1enabled0x62:TableEntry10xFF0x64:TableEntry20xFF6:4DRVLV1[2:0]Driver1current=decimal(DRVLV1[2:0])+10x66:TableEntry30xFF0x68:TableEntry40xDC3DRVEN00:Driver0disabled1:Driver0enabled0x6A:TableEntry50xBB0x6C:TableEntry60x992:0DRVLV0[2:0]Driver0current=decimal(DRVLV0[2:0])+10x6E:TableEntry70x99ADN4604DataSheetRev.
A|Page30of40Address:ChannelDefaultRegisterNameBitBitNameDescription0x61:TableEntry00x00TXLookupTable17DRVEND0:DriverDdisabled1:DriverDenabled0x63:TableEntry10x990x65:TableEntry20xCC6:4DRVLVD[2:0]DriverDcurrent=decimal(DRVLVD[2:0])+10x67:TableEntry30xFF0x69:TableEntry40xFF3DRVEN20:Driver2disabled1:Driver2enabled0x6B:TableEntry50xFF0x6D:TableEntry60xDD2:0DRVLV2[2:0]Driver2current=decimal(DRVLV2[2:0])+10x6F:TableEntry70xDD0x80WriteonlyUpdate0UPDATEUpdatesXPTswitchcore(activehigh,writeonly)0x810x00Maptableselect0MAPTABLESELECT0:Map0isselected1:Map1isselected0x82WriteonlyXPTbroadcast3:0BROADCAST[3:0]Alloutputsconnectionassignment0x900xEFXPTMap0Control07:4OUT1[3:0]Output1connectionassignment3:0OUT0[3:0]Output0connectionassignment0x910xCDXPTMap0Control17:4OUT3[3:0]Output3connectionassignment3:0OUT2[3:0]Output2connectionassignment0x920xABXPTMap0Control27:4OUT5[3:0]Output5connectionassignment3:0OUT4[3:0]Output4connectionassignment0x930x89XPTMap0Control37:4OUT7[3:0]Output7connectionassignment3:0OUT6[3:0]Output6connectionassignment0x940x67XPTMap0Control47:4OUT9[3:0]Output9connectionassignment3:0OUT8[3:0]Output8connectionassignment0x950x45XPTMap0Control57:4OUT11[3:0]Output11connectionassignment3:0OUT10[3:0]Output10connectionassignment0x960x23XPTMap0Control67:4OUT13[3:0]Output13connectionassignment3:0OUT12[3:0]Output12connectionassignment0x970x01XPTMap0Control77:4OUT15[3:0]Output15connectionassignment3:0OUT14[3:0]Output14connectionassignment0x980x10XPTMap1Control07:4OUT1[3:0]Output1connectionassignment3:0OUT0[3:0]Output0connectionassignment0x990x32XPTMap1Control17:4OUT3[3:0]Output3connectionassignment3:0OUT2[3:0]Output2connectionassignment0x9A0x54XPTMap1Control27:4OUT5[3:0]Output5connectionassignment3:0OUT4[3:0]Output4connectionassignment0x9B0x76XPTMap1Control37:4OUT7[3:0]Output7connectionassignment3:0OUT6[3:0]Output6connectionassignment0x9C0x98XPTMap1Control47:4OUT9[3:0]Output9connectionassignment3:0OUT8[3:0]Output8connectionassignment0x9D0xBAXPTMap1Control57:4OUT11[3:0]Output11connectionassignment3:0OUT10[3:0]Output10connectionassignment0x9E0xDCXPTMap1Control67:4OUT13[3:0]Output13connectionassignment3:0OUT12[3:0]Output12connectionassignment0x9F0xFEXPTMap1Control77:4OUT15[3:0]Output15connectionassignment3:0OUT14[3:0]Output14connectionassignmentDataSheetADN4604Rev.
A|Page31of40Address:ChannelDefaultRegisterNameBitBitNameDescription0xB00xEFXPTStatus07:4OUT1[3:0]Output1connectionstatus3:0OUT0[3:0]Output0connectionstatus0xB10xCDXPTStatus17:4OUT3[3:0]Output3connectionstatus3:0OUT2[3:0]Output2connectionstatus0xB20xABXPTStatus27:4OUT5[3:0]Output5connectionstatus3:0OUT4[3:0]Output4connectionstatus0xB30x89XPTStatus37:4OUT7[3:0]Output7connectionstatus3:0OUT6[3:0]Output6connectionstatus0xB40x67XPTStatus47:4OUT9[3:0]Output9connectionstatus3:0OUT8[3:0]Output8connectionstatus0xB50x45XPTStatus57:4OUT11[3:0]Output11connectionstatus3:0OUT10[3:0]Output10connectionstatus0xB60x23XPTStatus67:4OUT13[3:0]Output13connectionstatus3:0OUT12[3:0]Output12connectionstatus0xB70x01XPTStatus77:4OUT15[3:0]Output15connectionstatus3:0OUT14[3:0]Output14connectionstatus0xF00x00Terminationcontrol3TXN_TERMOutput[15:8](North)terminationcontrol0:Terminationsenabled1:Terminationsdisabled2TXS_TERMOutput[7:0](South)terminationcontrol1RXE_TERMInput[15:8](East)terminationcontrol0RXW_TERMInput[7:0](West)terminationcontrol0xFERevision7:0REV[7:0]Read-only0xFF0x04DeviceID7:0ID[7:0]Read-only1Broadcastregister,Address0x18,iswrite-only.
ADN4604DataSheetRev.
A|Page32of40APPLICATIONSINFORMATIONTheADN4604isanasynchronousandprotocolagnosticdigitalswitchand,therefore,isapplicabletoawiderangeofapplica-tionsincludingnetworkroutinganddigitalvideoswitching.
TheADN4604supportsthedataratesandsignalinglevelsofHDMI,DVI,DisplayPortandSD-,HD-,and3G-SDIdigitalvideo.
TheADN4604canbeusedtocreatematrixswitches.
Anexampleblockdiagramofa16*16matrixswitchisshowninFigure51.
SinceHDMI,DVI,andDisplayPortarequadlaneprotocols,fourADN4604sareusedtocreateafull16*16matrixswitch.
Smallerarrays,suchas4*4and8*8,requireoneandtwoADN4604devices,respectively.
ProperhighspeedPCBdesigntechniquesshouldbeusedtomaintainthesignalintegrityofthehighdataratesignals.
Itisimportanttominimizethelane-to-laneskewandcrosstalkintheseapplications.
ADN4604IN0IN1IN15OUT0OUT1OUT15ADN4604IN0IN1IN15OUT0OUT1OUT15ADN4604IN0IN1IN15OUT0OUT1OUT15ADN4604IN0IN1IN15OUT0OUT1OUT15SOURCE1SOURCE2SOURCE16SOURCE3SOURCE4SOURCE5SOURCE6SOURCE7SOURCE8SOURCE9SOURCE10SOURCE11SOURCE12SOURCE13SOURCE14SOURCE15DISPLAY1DISPLAY2DISPLAY16DISPLAY3DISPLAY4DISPLAY5DISPLAY6DISPLAY7DISPLAY8DISPLAY9DISPLAY10DISPLAY11DISPLAY12DISPLAY13DISPLAY14DISPLAY1507934-051Figure51.
ADN4604DigitalVideo(DVI,HDMI,DisplayPort)MatrixSwitchBlockDiagramDataSheetADN4604Rev.
A|Page33of40O/EO/EE/OE/OCDRCDRO/EE/OCDRADN460416*16CROSSPOINTSWITCHIN1IN2IN15OUT1OUT2OUT1507934-052Figure52.
ADN4604NetworkingSwitchApplicationBlockDiagramPEEQLOSSYCHANNEL8LANEUPLINKPATH8LANEDOWNLINKPATHLOSSYCHANNELASIC2EQPEASIC1Z0Z0Z0Z0Z0Z0Z0Z007934-053Figure53.
Multi-LaneSignalConditioningApplicationDiagramADN4604DataSheetRev.
A|Page34of40SUPPLYSEQUENCINGIdeally,allpowersuppliesshouldbebroughtuptotheappropri-atelevelssimultaneously(powersupplyrequirementsaresetbythesupplylimitsinTable1andtheabsolutemaximumratingslistedinTable4).
IfthepowersuppliestotheADN4604arebroughtupseparately,thesupplypower-upsequenceisasfollows:DVCCpoweredfirst,followedbyVCC,and,lasttheterminationsupplies(VTTIE,VTTIW,VTTON,andVTTOS).
Thepower-downsequenceisreversedwithterminationsuppliesbeingpoweredofffirst.
TheterminationsuppliescontainESDprotectiondiodestotheVCCpowerdomain.
Toavoidasustainedhighcurrentconditioninthesedevices(ISUSTAINED<100mA),theVTTIandVTTOsuppliesshouldbepoweredonafterVCCandshouldbepoweredoffbeforeVCC.
Ifthesystempowersupplieshaveahighimpedanceinthepoweredoffstate,thensupplysequencingisnotrequiredprovidedthefollowinglimitsareobserved:PeakcurrentfromVTTIxorVTTOxtoVCC<200mASustainedcurrentfromVTTIxorVTTOxtoVCC<100mAPOWERDISSIPATIONThepowerdissipationoftheADN4604dependsonthesupplyvoltages,I/Ocouplingtype,anddeviceconfiguration.
Theinputterminationresistorsdissipatepowerdependingonthedifferentialinputswingandcommon-modevoltage.
Whenac-coupled,thecommon-modevoltageisequaltotheterminationsupplyvoltage(VTTIEorVTTIW).
Whilethecurrentdrawnfromtheinputterminationsupplyiseffectivelyzero,thereisstillpowerandheatdissipatedintheterminationresistorsasaresultofthedifferentialsignalswing.
Thecoresupplycurrentandoutputterminationcurrentarestronglydependentondeviceconfiguration,suchasthenumberofchannelsenabled,outputlevelsetting,andoutputpreemphasissetting.
Inhighambienttemperatureoperatingconditions,itisimpor-tanttoavoidexceedingthemaximumjunctiontemperatureofthedevice.
Limitingthetotalpowerdissipationcanbeachievedbythefollowing:ReducingtheoutputswingReducingthepreemphasislevelDecreasingthesupplyvoltageswithintheallowablerangesdefinedinTable1DisablingunusedchannelsAlternatively,thethermalresistancecanbereducedbyAddinganexternalheat-sinkIncreasingtheairflowRefertothePrintedCircuitBoard(PCB)LayoutGuidelinessectionforrecommendationsforproperthermalstencillayoutandfabrication.
OUTPUTCOMPLIANCEInlowvoltageapplications,usersmustpaycarefulattentiontoboththedifferentialandcommon-modesignallevel.
Thechoiceofoutputvoltageswing,preemphasissetting,supplyvoltages(VCCandVTTO),andoutputcoupling(acordc)affectpeakandsettledsingle-endedvoltageswingsandthecommon-modeshiftmeasuredacrosstheoutputterminationresistors.
Thesechoicesalsoaffectoutputcurrentand,consequently,powerconsumption.
Table19showsthechangeinoutputcommonmode(ΔVOCM=VCCVOCM)withoutputlevelandpreemphasissetting.
Single-endedoutputlevelsarecalculatedforVTTOsuppliesof3.
3Vand2.
5Vtoillustratepracticalchallengesofreducingthesupplyvoltage.
TheminimumVL(minVL)cannotbebelowtheabsoluteminimumlevelspecifiedinTable1.
Thecombinationsofoutputlevel,preemphasis,supplyvoltage,andoutputcouplingforwhichtheminimumVLspecificationisviolatedarelistedasN/AinTable1.
SincetheabsoluteminimumoutputvoltagespecifiedinTable1isrelativetoVCC,decreasingVCCisrequiredtomaintaintheoutputlevelswithinthespecifiedlimitswhenloweroutputterminationvoltagesarerequired.
VTTOvoltagesaslowas1.
8Vareallowableforoutputswingslessthanorequalto400mV(single-ended).
Figure54illustratesanapplicationwheretheADN4604isusedasadc-coupledleveltranslatortointerfacea3.
3VCMLdrivertoanASICwith1.
8VI/Os.
ThediodeinserieswithVCCreducesthevoltageatVCCforimprovedoutputcompliance.
CMLVEEVTTOx1.
8V1.
8V3.
3V3.
3VVCCVTTIxADN4604CML3.
3VZ0Z0Z0Z007934-054ASICRxFigure54.
DC-CoupledLevelTranslatorApplicationCircuitDataSheetADN4604Rev.
A|Page35of40Table19.
OutputVoltageRangeandOutputCommon-ModeShiftvs.
OutputLevelandPESettingSingle-EndedOutputLevelsandPEBoostRegisterSettingsOutputCurrentAC-CoupledOutputsDC-CoupledOutputsVCC=VTTO=3.
3VVCC=2.
7VVTTO=2.
5VVCC=VTTO=3.
3VVCC=2.
7VVTTO=2.
5VVSW-DC1(mV)VSW-PE1(mV)PEBoost%PE(dB)TXDrive0TXDrive1ITTO1(mA)VOCM1(mV)VH-PE1(V)VL-PE1(V)VH-PE1(V)VL-PE1(V)VOCM1(mV)VH-DC1(V)VL-DC1(V)VH-PE1(V)VL-PE1(V)1001000.
000.
000x990x0041003.
253.
152.
452.
35503.
33.
22.
52.
410015050.
003.
520x990x8861503.
2253.
0752.
4252.
275753.
33.
152.
52.
35100200100.
006.
020x990x9982003.
232.
42.
21003.
33.
12.
52.
3100250150.
007.
960x990xAA102503.
1752.
9252.
3752.
1251253.
33.
052.
52.
25100300200.
009.
540x990xBB123003.
152.
852.
352.
051503.
332.
52.
2100350250.
0010.
880x990xCC143503.
1252.
7752.
3251.
9751753.
32.
952.
52.
15100400300.
0012.
040x990xDD164003.
12.
72.
31.
92003.
32.
92.
52.
1100450350.
0013.
060x990xEE184503.
0752.
6252.
2751.
8252253.
32.
852.
52.
05100500400.
0013.
980x990xFF205003.
052.
552.
251.
752503.
32.
82.
522002000.
000.
000xBB0x0082003.
232.
42.
21003.
33.
12.
52.
320025025.
001.
940xBB0x88102503.
1752.
9252.
3752.
1251253.
33.
052.
52.
2520030050.
003.
520xBB0x99123003.
152.
852.
352.
051503.
332.
52.
220035075.
004.
860xBB0xAA143503.
1252.
7752.
3251.
9751753.
32.
952.
52.
15200400100.
006.
020xBB0xBB164003.
12.
72.
31.
92003.
32.
92.
52.
1200450125.
007.
040xBB0xCC184503.
0752.
6252.
2751.
8252253.
32.
852.
52.
05200500150.
007.
960xBB0xDD205003.
052.
552.
251.
752503.
32.
82.
52200550175.
008.
790xBB0xEE225503.
0252.
4752.
2251.
6752753.
32.
752.
51.
95200600200.
009.
540xBB0xFF2460032.
42.
21.
63003.
32.
72.
51.
93003000.
000.
000xDD0x00123003.
152.
852.
352.
051503.
332.
52.
230035016.
671.
340xDD0x88143503.
1252.
7752.
3251.
9751753.
32.
952.
52.
1530040033.
332.
500xDD0x99164003.
12.
72.
31.
92003.
32.
92.
52.
130045050.
003.
520xDD0xAA184503.
0752.
6252.
2751.
8252253.
32.
852.
52.
0530050066.
674.
440xDD0xBB205003.
052.
552.
251.
752503.
32.
82.
5230055083.
335.
260xDD0xCC225503.
0252.
4752.
2251.
6752753.
32.
752.
51.
95300600100.
006.
020xDD0xDD2460032.
42.
21.
63003.
32.
72.
51.
9300650116.
676.
720xDD0xEE266502.
9752.
3252.
1751.
5253253.
32.
652.
51.
85300700133.
337.
360xDD0xFF287002.
952.
252.
151.
453503.
32.
62.
51.
84004000.
000.
000xFF0x00164003.
12.
72.
31.
92003.
32.
92.
52.
140045012.
501.
020xFF0x88184503.
0752.
6252.
2751.
8252253.
32.
852.
52.
0540050025.
001.
940xFF0x99205003.
052.
552.
251.
752503.
32.
82.
5240055037.
502.
770xFF0xAA225503.
0252.
4752.
2251.
6752753.
32.
752.
51.
9540060050.
003.
520xFF0xBB2460032.
42.
21.
63003.
32.
72.
51.
940065062.
504.
220xFF0xCC266502.
9752.
3252.
1751.
5253253.
32.
652.
51.
8540070075.
004.
860xFF0xDD287002.
952.
252.
151.
453503.
32.
62.
51.
840075087.
505.
460xFF0xEE307502.
9252.
175N/A2N/A23753.
32.
552.
51.
75400800100.
006.
020xFF0xFF328002.
92.
1N/A2N/A24003.
32.
52.
51.
74504500.
000.
000xFF0x09184503.
0752.
6252.
2751.
8252253.
32.
852.
52.
0545065044.
443.
190xFF0xBD266502.
9752.
3252.
1751.
5253253.
32.
652.
51.
855005000.
000.
000xFF0x0B205003.
052.
55N/A2N/A22503.
32.
82.
5250070040.
002.
920xFF0xBF287002.
952.
252.
151.
453503.
32.
62.
51.
85505500.
000.
000xFF0x0D225503.
0252.
4752.
2251.
6752753.
32.
752.
51.
9555065018.
181.
450xFF0x9F266502.
9752.
3252.
1751.
5253253.
32.
652.
51.
856006000.
000.
000xFF0x0F2460032.
4N/A2N/A23003.
32.
72.
51.
91SymboldefinitionsareshowninTable14.
2Thissettingisnotallowedwhenac-coupledwithVCC=2.
7VandVTTON=2.
5VorVTTOS=2.
5V.
ADN4604DataSheetRev.
A|Page36of40PRINTEDCIRCUITBOARD(PCB)LAYOUTGUIDELINESThehighspeeddifferentialinputsandoutputsshouldberoutedwith100Ωcontrolledimpedancedifferentialtransmissionlines.
Thetransmissionlines,eithermicrostriporstripline,shouldbereferencedtoasolidlowimpedancereferenceplane.
AnexampleofaPCBcross-sectionisshowninFigure55.
Thetracewidth(W),differentialspacing(S),heightabovereferenceplane(H),anddielectricconstantofthePCBmaterialdeterminethecharacteristicimpedance.
Adjacentchannelsshouldbekeptapartbyadistancegreaterthan3Wtominimizecrosstalk.
PCBDIELECTRICSIGNAL(MICROSTRIP)SOLDERMASKPCBDIELECTRICPCBDIELECTRICPCBDIELECTRICREFERENCEPLANEREFERENCEPLANESIGNAL(STRIPLINE)WSWHWSW07934-055Figure55.
ExampleofaPCBCross-SectionThermalPaddleDesignTheTQFPisdesignedwithanexposedthermalpaddletoconductheatawayfromthepackageandintothePCB.
ByincorporatingthermalviasintothePCBthermalpaddle,heatisdissipatedmoreeffectivelyintotheinnermetallayersofthePCB.
Toensuredeviceperformanceatelevatedtemperatures,itisimportanttohaveasufficientnumberofthermalviasincorporatedintothedesign.
AninsufficientnumberofthermalviasresultsinaθJAvaluelargerthanspecifiedinTable1.
Itisrecommendedthataviaarrayof4*4or5*5withadiameterof0.
3mmto0.
33mmbeusedtosetapitchbetween1.
0mmand1.
2mm.
ArepresentativeofthesearraysisshowninFigure56.
THERMALVIATHERMALPADDLE07934-056Figure56.
PCBThermalPaddleandViaStencilDesignfortheThermalPaddleToeffectivelyremoveheatfromthepackageandtoenhanceelectricalperformance,thethermalpaddlemustbesoldered(bonded)tothePCBthermalpaddle,preferablywithminimumvoids.
However,eliminatingvoidsmaynotbepossiblebecauseofthepresenceofthermalviasandthelargesizeofthethermalpaddleforlargersizepackages.
Also,outgassingduringthereflowprocessmaycausedefects(splatter,solderballing)ifthesolderpastecoverageistoobig.
Itisrecommendedthatsmallermultipleopeningsinthestencilbeusedinsteadofonebigopeningforprintingsolderpasteonthethermalpaddleregion.
Thistypicallyresultsin50%to80%solderpastecoverage.
Figure57showshowtoachievetheselevelsofcoverage.
VoidswithinsolderjointsundertheexposedpaddlecanhaveanadverseaffectonhighspeedandRFapplications,aswellasonthermalperformance.
Becausethepackageincorporatesalargecenterpaddle,controllingsoldervoidingwithinthisregioncanbedifficult.
Voidswithinthisgroundplanecanincreasethecurrentpathofthecircuit.
Themaximumsizeforavoidshouldbelessthanviapitchwithintheplane.
Thisassuresthatanyoneviaisnotrenderedineffectualwhenanyvoidincreasesthecurrentpathbeyondthedistancetothenextavailablevia.
1.
35mm*1.
35mmSQUARESAT1.
65mmPITCHCOVERAGE:68%07934-057Figure57.
TypicalThermalPaddleStencilDesignDataSheetADN4604Rev.
A|Page37of40Largevoidsinthethermalpaddleareashouldbeavoided.
Tocontrolvoidsinthethermalpaddlearea,soldermaskingmayberequiredforthermalviastopreventsolderwickinginsidetheviaduringreflow,thusdisplacingthesolderawayfromtheinterfacebetweenthepackagethermalpaddleandthermalpaddlelandonthePCB.
Thereareseveralmethodsemployedforthispurpose,suchasviatenting(toporbottomside),usingdryfilmsoldermask;viapluggingwithliquidphoto-imagible(LPI)soldermaskfromthebottomside;orviaencroaching.
TheseoptionsaredepictedinFigure58.
Incaseofviatenting,thesoldermaskdiametershouldbe100micronslargerthantheviadiameter.
(A)(B)(D)(C)VIASOLDERMASKCOPPERPLATING07934-058Figure58.
SolderMaskOptionsforThermalVias:(A)ViaTentingfromtheTop;(B)ViaTentingfromtheBottom;(C)ViaPlugging,Bottom;and(D)ViaEncroaching,BottomADN4604DataSheetRev.
A|Page38of40OUTLINEDIMENSIONSCOMPLIANTTOJEDECSTANDARDSMS-026-AED-HD021809-A125265076100755114.
00BSCSQ16.
00BSCSQ0.
270.
220.
170.
50BSC1.
051.
000.
950.
150.
050.
750.
600.
45SEATINGPLANE1.
20MAX12526507610075516.
50NOM7°3.
5°0°COPLANARITY0.
080.
200.
09TOPVIEW(PINSDOWN)BOTTOMVIEW(PINSUP)CONDUCTIVEHEATSINKPIN1FORPROPERCONNECTIONOFTHEEXPOSEDPAD,REFERTOTHEPINCONFIGURATIONANDFUNCTIONDESCRIPTIONSSECTIONOFTHISDATASHEET.
Figure59.
100-LeadThinQuadFlatPackage,ExposedPad[TQFP_EP](SV-100-1)DimensionsshowninmillimetersORDERINGGUIDEModel1TemperatureRangePackageDescriptionPackageOptionOrderingQuantityADN4604ASVZ40°Cto+85°C100-LeadThinQuadFlatPackage[TQFP_EP]SV-100-1ADN4604ASVZ-RL40°Cto+85°C100-LeadThinQuadFlatPackage[TQFP_EP],13"Tape&ReelSV-100-11000ADN4604-EVALZEvaluationBoard1Z=RoHSCompliantPart.
DataSheetADN4604Rev.
A|Page39of40NOTESADN4604DataSheetRev.
A|Page40of40NOTESPurchaseoflicensedI2CcomponentsofAnalogDevicesoroneofitssublicensedAssociatedCompaniesconveysalicenseforthepurchaserunderthePhilipsI2CPatentRightstousethesecomponentsinanI2Csystem,providedthatthesystemconformstotheI2CStandardSpecificationasdefinedbyPhilips.
2009–2013AnalogDevices,Inc.
Allrightsreserved.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
D07934-0-3/13(A)