B7ios6.1.3完美越狱

GeneralPurpose3Vto5.
5V16Bit22KSPSDSPCODECTLV320AIC10December2001HPADataAcquisitionDataManualSLWS093FiiiContentsSectionTitlePage1Introduction1–11.
1Features1–11.
2FunctionalBlockDiagram1–31.
3TerminalAssignments1–41.
4OrderingInformation1–51.
5TerminalFunctions1–61.
6DefinitionsandTerminology1–71.
7RegisterFunctionalSummary1–82FunctionalDescription2–12.
1DeviceFunctions2–12.
1.
1OperatingFrequencies2–12.
1.
2ADCSignalChannel2–12.
1.
3DACSignalChannel2–22.
1.
4MICInput2–42.
1.
5AntialiasingFilter2–42.
1.
6Sigma-DeltaADC2–42.
1.
7DecimationFilter2–42.
1.
8Sigma-DeltaDAC2–42.
1.
9InterpolationFilter2–42.
1.
10AnalogandDigitalLoopback2–52.
1.
11FIROverflowFlag2–52.
1.
12FIRBypassMode2–52.
1.
13Low-PowerMode2–52.
1.
14Event-MonitorMode2–52.
2ResetandPower-DownFunctions2–62.
2.
1SoftwareandHardwareReset2–62.
2.
2SoftwareandHardwarePowerDown2–62.
3ClockSource2–72.
4DataOut(DOUT)2–72.
4.
1DataOut,MasterMode2–72.
4.
2DataOut,SlaveMode2–72.
5DataIn(DIN)2–72.
6FC(HardwareSecondaryCommunicationRequest)2–72.
7Frame-SyncFunctionforTLV320AIC102–72.
7.
1Frame-Sync(FS)Function—Continuous-TransferMode(MasterOnly)2–92.
7.
2Frame-Sync(FS)Function—Fast-TransferMode(SlaveOnly)2–9iv2.
7.
3Frame-Sync(FS)Function—MasterMode2–92.
7.
4Frame-Sync(FS)Function—SlaveMode2–102.
7.
5Frame-SyncDelayed(FSD)Function,CascadeMode2–10.
.
.
2.
8MultiplexedAnalogInputandOutput2–112.
8.
1MultiplexedAnalogInput2–112.
8.
2AnalogOutput2–122.
8.
3Single-EndedAnalogInput2–122.
8.
4Single-EndedAnalogOutput2–123SerialCommunications3–13.
1PrimarySerialCommunication3–13.
2SecondarySerialCommunication3–23.
2.
1RegisterProgramming3–33.
2.
2HardwareSecondarySerialCommunicationRequest3–4.
.
.
.
3.
2.
3SoftwareSecondarySerialCommunicationRequest3–5.
.
.
.
3.
3DirectConfigurationMode3–53.
4ContinuousDataTransferMode3–73.
5DINandDOUTDataFormat3–83.
5.
1PrimarySerialCommunicationDINandDOUTDataFormat3–83.
5.
2SecondarySerialCommunicationDINandDOUTDataFormat3–83.
5.
3DirectConfigurationDCSIDataFormat3–84Specifications4–14.
1AbsoluteMaximumRatingsOverOperatingFree-AirTemperatureRange4–14.
2RecommendedOperatingConditions4–14.
3ElectricalCharacteristicsOverRecommendedOperatingFree-AirTemperatureRange,AVDD=5V/3.
3V,DVDD=5V/3.
3V4–14.
3.
1DigitalInputsandOutputs,Fs=8kHz,OutputNotLoaded4–14.
3.
2ADCPathFilter,Fs=8kHz4–24.
3.
3ADCDynamicPerformance,Fs=8kHz4–24.
3.
4ADCChannelCharacteristics4–34.
3.
5DACPathFilter,Fs=8kHz4–34.
3.
6DACDynamicPerformance4–34.
3.
7DACChannelCharacteristics4–44.
3.
8Op-AmpInterface(A1,A3,A4)4–44.
3.
9Power-SupplyRejection4–44.
3.
10PowerSupply4–54.
4TimingRequirements4–54.
4.
1MasterModeTimingRequirements4–5v5ParameterMeasurementInformation5–16MechanicalInformation6–1AppendixA—RegisterSetA–1ListofIllustrationsFigureTitlePage2–1TimingSequenceofADCChannel(PrimaryCommunicationOnly)2–12–2TimingSequenceofADCChannel(PrimaryandSecondaryCommunication)2–22–3TimingSequenceofDACChannel(PrimaryCommunicationOnly)2–32–4TimingSequenceofDACChannel(PrimaryandSecondaryCommunication)2–32–5TypicalMicrophoneInterface2–42–6EventMonitorModeTiming2–52–7InternalPower-DownLogic2–62–8TimingDiagramfortheFSPulseMode(M1M0=00)2–82–9TimingDiagramfortheSPI_CP0Mode(M1M0=01)2–82–10TimingDiagramfortheSPI_CP1Mode(M1M0=10)2–82–11TimingDiagramfortheFSFrameMode(M1M0=11)2–92–12MasterDeviceFrame-SyncSignalWithPrimaryandSecondaryCommunication(NoSlaves)2–92–13MasterDevice'sFSOutputtoDSPandFSDOutputtotheSlave2–102–14CascadeModeConnection(toDSPInterface)2–102–15Master-SlaveFrame-SyncTiming2–112–16INPandINMInternalSelf-Biased(AVDD/2)Circuit2–112–17DifferentialOutputDrive(Ground-Referenced)2–122–18Single-EndedInput2–122–19Single-EndedOutput2–123–1PrimarySerialCommunicationTiming3–13–2HardwareandSoftwareSecondaryCommunicationRequest3–23–3Device3/Register1ReadOperationTimingDiagram3–33–4Device3/Register1WriteOperationTimingDiagram3–43–5FSOutputWhenHardwareSecondarySerialCommunicationIsRequestedOnlyOnce(NoSlave)3–43–6OutputWhenHardwareSecondarySerialCommunicationIsRequested(ThreeSlaves)3–53–7FSOutputDuringSoftwareSecondarySerialCommunicationRequest(NoSlave)3–53–8DirectConfiguration3–6vi3–9DirectConfigurationModeTiming3–73–10ContinuousDataTransferModeTiming3–73–11PrimaryCommunicationDINandDOUTDataFormat3–83–12SecondaryCommunicationDINandDOUTDataFormat3–83–13DirectCommunicationDCSIDataFormat3–85–1FC,FSandFSDTiming5–15–2SerialCommunicationTiming5–15–3FFT–ADCChannel5–25–4FFT–ADCChannel5–25–5FFT–DACChannel5–35–6FFT–DACChannel5–35–7FFT–ADCChannel5–45–8FFT–ADCChannel5–45–9FFT–DACChannel5–55–10FFT–DACChannel5–5ListofTablesTableTitlePage2–1SerialInterfaceModes2–83–1LeastSignificantBitControlFunction3–21–11IntroductionTheTLV320AIC10provideshighresolutionsignalconversionfromdigital-to-analog(D/A)andfromanalog-to-digital(A/D)usingoversamplingsigma-deltatechnology.
Itallows2-to-1MUXinputswithbuilt-inantialiasingfilterandamplificationforgeneral-purposeapplicationssuchastelephonehybridinterface,electretmicrophonepreamp,etc.
BothINandAUXinputsacceptnormalanalogsignals.
Thisdeviceconsistsofapairof16-bitsynchronousserialconversionpaths(oneforeachdirection),andincludesaninterpolationfilterbeforetheDACandadecimationfilteraftertheADC.
TheFIRfilterscanbebypassedtoofferflexibilityandpowersavings.
Otheroverheadfunctionsprovideon-chipincludetiming(programmablesamplerate,continuousdatatransfer,andFIRbypass)andcontrol(programmable-gainamplifier,communicationprotocol,etc.
).
Thesigma-deltaarchitectureproduceshigh-resolutionanalog-to-digitalanddigital-to-analogconversionatlowsystemcost.
TheTLV320AIC10designenhancescommunicationwiththeDSP.
ThecontinuousdatatransfermodefullysupportsTI'sDSPautobuffering(ABU)toreduceDSPinterruptserviceoverhead.
Theautomaticcascadingdetection(ACD)makescascadeprogrammingsimpleandsupportsacascadeoperationofonemasteranduptosevenslaves.
Thedirect-configurationmodeforhostinterfaceusesasingle-wireserialporttodirectlyprograminternalregisterswithoutinterferencefromthedataconversionserialport,orwithoutresettingtheentiredevice.
TheeventmonitormodeallowstheDSPtomonitorexternaleventslikephoneoff-hookringdetection.
Inthelower-powermode,theTLV320AIC10convertsdataatasamplingrateof8KSPSconsumingonly39mW.
TheprogrammablefunctionsofthisdeviceareconfiguredthroughaserialinterfacethatcanbegluelesslyinterfacedtoanyDSPthataccepts4-wireserialcommunications,suchastheTMS320Cxx.
Theoptionsincludesoftwarereset,devicepower-down,separatecontrolforADCandDACturnoff,communicationsprotocol,signal-samplingrate,gaincontrol,andsystem-testmodes,asoutlinedinAppendixA.
TheTLV320AIC10isparticularlysuitableforavarietyofapplicationsinhands-freecarkits,VOIP,cablemodem,speech,andthetelephonyareaincludinglow-bitrate,high-qualitycompression,speechenhancement,recognition,andsynthesis.
Itslow-groupdelaycharacteristicmakesitsuitableforsingleormultichannelactive-controlapplications.
TheTLV320AIC10ischaracterizedforcommercialoperationfrom0°Cto70°C,andindustrialoperationfrom–40°Cto85°C.
1.
1FeaturesC54xxsoftwaredriveravailable16-bitoversamplingsigma-deltaA/Dconverter16-bitoversamplingsigma-deltaD/AconverterMaximumoutputconversionrate:–22kspswithon-chipFIRfilter–88kspswithFIRbypassedVoicebandbandwidthinFIR-bypassedmodeandfinalsamplingrateat8ksps–90-dBSNR/ADCand87-dBSNR/DACwithDSPsFIR(FIRbypassedat88ksps/5V)–87-dBSNR/ADCand85-dBSNR/DACwithDSPsFIR(FIRbypassedat88ksps/3.
3V)On-chipFIRproduced84-dBSNRforADCand85-dBSNRforDACover11-kHzBWBuilt-infunctionsincludingPGA,antialiasinganalogfilter,andoperationalamplifiersforgeneral-purposeinterface(suchasMICinterfaceandhybridinterface)1–2GluelessserialportinterfacetoDSPs(TITMS320Cxx,SPI,orstandardDSPs)Automaticcascadingdetection(ACD)makescascadeprogrammingsimpleandallowsupto8devicestobeconnectedincascade.
On-flyreconfigurationmodesincludesecondary-communicationmodeanddirect-configurationmode(hostinterface).
Continuousdata-transfermodeforusewithautobuffering(ABU)toreduceDSPinterruptserviceoverheadEvent-monitormodeprovidesexternal-eventcontrol,suchasRING/OFF-HOOKdetectionProgrammableADCandDACconversionrateProgrammableinputandoutputgaincontrolSeparatesoftwarecontrolforADCandDACpower-downAnalog(3-Vto5.
5-V)supplyoperationDigital(3-Vto5.
5-V)supplyoperationPowerdissipation(PD)of39mWrmstypicalfor8-kspsat3.
3VHardwarepower-downmodeto0.
5mWInternalandexternalreferencevoltage(Vref)Differentialandsingle-endedanaloginput/output2s-complementdataformatTestmode,whichincludesdigitalloopbackandanalogloopback600-ohmoutputdriver1–31.
2FunctionalBlockDiagramSigma–DeltaADCSincFilterLowPassFilterSigma–DeltaDACADREFPADREFMMCLKInterfaceCircuitDiv256xNDINM/SFSDFSSCLKM0M1OUTPOUTMPGAPGADOUTInternalClockCircuitFIRFilterAnalogLoopbackDecimationFilterAnti–AliasingFilterVMID@5mAVALTIFLAGFCDCSIDAREFPDAREFMMUXAURXMAURXFPINMINPAURXCP1.
5Vor2.
5VDTXOPDTXIMReceiverorMICAmpTransmitterAmpDTXIPDTXOM+–+––+A3A4A2A1SincFilterFIRFilterInterpolationFilterDigitalLoopbackSW4SW5SW6SW2SW3SW1Note:SwitchesSWxareControlledbyBitD6ofControlRegister1.
ref1–41.
3TerminalAssignments1415NCNCAVDD2AVSSNCNCDVDD2DVSSNCM/SALTINDCSI36353433323130292827262516123456789101112AURXFPAURXMAURXCPDTXOPDTXOMDTXIPDTXIMOUTPOUTMM0M1PWRDWN17181920FILT47464544434842INMINPAVAVNCFSFLAGFCDVDINNCSCLKMCLKFSD40393841212223243713NCVMIDDVRESETDOUTPFBPACKAGE(TOPVIEW)SSDD1DD1SSSSAVNCSSAVNCNOTE:AllNCpinsshouldbeleftunconnected.
1–51.
3TerminalAssignments(Continued)98765ABCDEF321GHJ4ALTINMCLKPWRDWNFSDFLAGAVSSAVDD2AVSSAVDD1FILTAURXFPAURXMAVSSVMIDRESETDINDVDD2INPDVDD1DTXIMAURXCPDTXOMM0OUTPNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCDTXOPDTXIPOUTMM1NCDVSSDOUTSCLKFSFCDCSIM/SNCDVSSNCNCNCNCNCAVSSAVSSINMNCNCNCNCNCNCGQEPACKAGE(TOPVIEW)NOTE:AllNCpinsshouldbeleftunconnected.
NC1.
4OrderingInformationTPACKAGESTA48-PINTQFPPFB80-PINMicroStarJuniorGQE0°Cto70°CTLV320AIC10CTLV320AIC10CGQE–40°Cto85°CTLV320AIC10ITLV320AIC10IGQE1–61.
5TerminalFunctionsTERMINALSI/ONAMENO.
I/ODESCRIPTIONNAMEPFBGQEI/ODESCRIPTIONALTIN26G9ISerialinputintheeventmonitormode.
Tiethispintolowifnotused.
AURXCP3C1IReceiver-path/GPamplifiernoninvertinginput.
ItneedstobeconnectedtoAVSSifnotused.
AURXM2C2IReceiver-pathamplifierA1invertinginput,orinvertinginputtoauxiliaryanaloginput.
ItneedstobeconnectedtoAVSSifnotused.
Canalsobeusedforgeneral-purposeamplification.
AURXFP1B1IReceiver-pathamplifierA1feedback,ornoninvertinginputtoauxiliaryanaloginput.
ItneedstobeconnectedtoAVSSifnotused.
Canalsobeusedforgeneral-purposeamplification.
AVDD145B4IAnalogpowersupplyAVDD234D8IAnalogpowersupplyAVSS33,40,42,46A3,B3,B5,B6,D9IAnaloggroundDCSI25G8IDirectconfigurationserialinputfordirectlyprogrammingofinternalcontrolregisters.
Tiethispintohighifnotused.
DIN17J4IDatainput.
DINreceivestheDACinputdataandregisterdatafromtheexternaldigitalsignalprocessor(DSP),andissynchronizedtoSCLKandFS.
DataislatchedatthefallingedgeofSCLKwhenFSislow.
DINisathighimpedancewhenFSisnotactivated.
DOUT16H4ODataoutput.
DOUTtransmitstheADCoutputbitsandregistersdata,andissynchronizedtoSCLKandFS.
DataissentoutattherisingedgeofSCLKwhenFSislow.
DOUTisathighimpedancewhenFSisnotactivated.
DTXIM7E1ITransmitter-pathamplifierA3analoginvertinginput.
Canalsobeusedforgeneral-purposeamplification.
DTXIP6E2ITransmitter-pathamplifierA4analognoninvertinginput.
Canalsobeusedforgeneral-purposeamplification.
DTXOM5D1OTransmitterpathamplifierA4feedbackfornegativeoutput.
Canalsobeusedforgeneral-purposeamplification.
DTXOP4D2OTransmitterpathamplifierA3feedbackforpositiveoutput.
Canalsobeusedfornegativeoutput.
DVDD115J3IDigitalpowersupplyDVDD230E9IDigitalpowersupplyDVSS14,29E8,H3IDigitalgroundFC24H7IHardwarerequestforsecondarycommunication.
Tiethispintolowifnotused.
FILT38B7OBandgapfilter.
FILTisprovidedfordecouplingofthebandgapreference,andprovides2.
5V.
Theoptimalcapacitorvalueis0.
1F(ceramic).
Thisvoltagenodeshouldbeloadedonlywithahigh-impedancedcload.
FLAG23J7OControlledbybitD4ofcontrolregister3.
IfD4=0(default),theFLAGpinoutputsthecommunicationflagthatgoeslow/hightoindicateprimary-communication/secondary-communicationinterval,respectively.
IfD4=1,theFLAGpinoutputsthevalueofD3.
FS22H6I/OFramesync.
WhenFSgoeslow,DINbeginsreceivingdatabitsandDOUTbeginstransmittingdatabits.
Inmastermode,FSisinternallygeneratedandislowduringdatatransmissiontoDINandfromDOUT.
Inslavemode,FSisexternallygenerated.
FSD21J6OFrame-syncdelayedoutput.
TheFSDoutputsynchronizesaslavedevicetotheframesyncofthemasterdevice.
FSDisappliedtotheslaveFSinputandhasthesamedurationasthemasterFSsignal.
Requiresapullupresistorifnotused.
INM48B2IInvertinginputtoanalogmodulator.
INMrequiresanexternalR-Cantialiasfilterwithlowoutputimpedanceiftheinternalantialiasfilterisbypassed.
INP47A2INoninvertinginputtoanalogmodulator.
INPrequiresanexternalR-Cantialiasfilterwithlowoutputimpedanceiftheinternalantialiasfilterisbypassed.
M010G1ICombinewithM1toselectserialinterfacemode(frame-syncmode)M111G2ICombinewithM0toselectserialinterfacemode(frame-syncmode)1–71.
5TerminalFunctions(Continued)TERMINALSI/ONAMENO.
I/ODESCRIPTIONNAMEPFBGQEI/ODESCRIPTIONMCLK20J5IMasterclock.
MCLKderivestheinternalclocksofthesigma-deltaanaloginterfacecircuit.
M/S27F8IMaster/slaveselectinput.
WhenM/Sishigh,thedeviceisthemaster,andwhenislow,itisaslave.
NC18,28,31,32,35,36,37,39,41,44A6,A7,C9,C8,F9NoconnectionOUTM9F2ODACsinvertingoutput.
OUTMisfunctionallyidenticalwithandcomplementarytoOUTP.
OUTP8F1ODACsnoninvertingoutput.
OUTPcanalsobeusedaloneforsingle-endedoperation.
PWRDWN12H1IPowerdown.
WhenPWRDWNispulledlow,thedevicegoesintoapower-downmode,theserialinterfaceisdisabled,andmostofthehigh-speedclocksaredisabled.
However,allregistervaluesaresustainedandthedeviceresumesfull-poweroperationwithoutreinitializationwhenPWRDWNispulledhighagain.
PWRDWNresetsthecountersonlyandpreservestheprogrammedregistercontents.
Seeparagraph2.
2.
2formoreinformation.
RESET13J2ITheresetfunctionisprovidedtoinitializealltheinternalregisterstotheirdefaultvalues.
Theserialportcanbeconfiguredtothedefaultstateaccordingly.
SeeAppendixA,RegisterSet,andSubsection2.
2,ResetandPower-DownFunctionsfordetaileddescriptions.
AllRESETpinsofdevicesincascademustbetiedtogether.
SCLK19H5I/OShiftclock.
SCLKsignalclocksserialdataintoDINandoutofDOUTduringtheframe-syncinterval.
Whenconfiguredasanoutput(M/Shigh),SCLKisgeneratedinternallybymultiplyingtheframe-syncsignalfrequencyby256(cascadedevices4).
Whenconfiguredasaninput(M/Slow),SCLKisgeneratedexternallyandmustbesynchronouswiththemasterclockandframesync.
VMID43A4OReferencevoltageoutputatAVDD/21.
6DefinitionsandTerminologyDatatransferintervalThetimeduringwhichdataistransferredfromDOUTtoDIN.
Theintervalis16shiftclocksandthedatatransferisinitiatedbythefallingedgeoftheFSsignal.
SignaldataThisreferstotheinputsignalandalloftheconvertedrepresentationsthroughtheADCchannel,andthesignalthroughtheDACchanneltotheanalogoutput.
Thisisincontrastwiththepurely-digitalsoftwarecontroldata.
PrimarycommunicationPrimarycommunicationreferstothedigitaldata-transferinterval.
Sincethedeviceissynchronous,thesignaldatawordsfromtheADCchannelandtotheDACchanneloccursimultaneously.
SecondarycommunicationSecondarycommunicationreferstothedigitalcontrolandconfigurationdata-transferintervalintoDIN,andtheregisterread-datacyclefromDOUT.
Thedatatransferoccurswhenrequestedbyhardwareorsoftware.
SPISerialperipheralinterfacestandardsetbyMotorolaFrame/pulsesyncFrame/pulsesyncrefersonlytothefallingedgeofthesignalFSthatinitiatesthedata-transferinterval.
TheprimaryFSstartstheprimarycommunication,andthesecondaryFSstartsthesecondarycommunication.
Frame/pulsesyncandsamplingperiodFrame/pulsesyncandsamplingperiodisthetimebetweenfallingedgesofsuccessiveprimaryFSsignalsanditisalwaysequalto256xSCLKifthenumberofcascadingdevicesislessthan5,or512xSCLKifthenumberofcascadingdevicesisgreaterthan4.
fsThesamplingfrequencyADCchannelADCchannelreferstoallsignal-processingcircuitsbetweentheanaloginputandthedigitalconversionresultatDOUT.
1–8DACchannelDACchannelreferstoallsignal-processingcircuitsbetweenthedigitaldatawordappliedtoDINandthedifferentialoutputanalogsignalavailableatOUTPandOUTM.
HostAhostisanyprocessingsystemthatinterfacestoDIN,DOUT,SCLK,FS,and/orMCLK.
PGAProgrammablegainamplifierFIRFinite-durationimpulseresponseDCSIDirectconfigurationserialinterfacewithhost1.
7RegisterFunctionalSummaryTherearefivecontrolregisterswhichareusedasfollows:Register0Theno-opregister.
Addressingregister0allowssecondary-communicationrequestwithoutalteringanyotherregisters.
Register1Controlregister1.
Thedatainthisregisterhasthefollowingfunctions:ProducetheoutputflagtoindicateadecimatorFIRfilteroverflow(readcycleonly)Enableofgeneral-purposeoperationalamplifiersA1,A3,andA4Enable/bypassADCsanalogantialiasingfilterSelectnormalorauxiliaryanaloginputControl16-bitor(15+1)-bitmodeofDACoperationActivatesoftwareresetEnable/bypassthedecimatorFIRfilterEnable/bypasstheinterpolatorFIRfilterRegister2Controlregister2.
Thedatainthisregisterhasthefollowingfunctions:Controlofthelow-powermodethatconvertsdataattherateof8kspsControloftheN-divideregisterthatdeterminesthefilterclockrateandsampleperiodRegister3Controlregister3.
Thedatainthisregisterhasthefollowingfunctions:SoftwarepowerdownSelectionofanalogloopback,digitalloopback,andeventmonitormodeControlofcontinuousdatatransfermodeControlofthevalueofone-bitgeneral-purposeoutputflagControltheoutputofFLAGpinEnable/disableADCpathEnable/disableDACpathControlof16-bitor(15+1)-bitmodeofADCoperationRegister4Controlregister4.
Thedatainthisregisterhasthefollowingfunctions:Controlofthe4-bitgainofinputPGAControlofthe4-bitgainofoutputPGA2–12FunctionalDescription2.
1DeviceFunctions2.
1.
1OperatingFrequenciesThesamplingfrequencyrepresentedbythefrequencyoftheprimarycommunicationisderivedfromthemasterclock(MCLK)inputwiththefollowingequation:Fs=Sampling(conversion)frequency=MCLK/(256*N),N=1,2.
.
.
,32Theinverseofthesamplingfrequencyisthetimebetweenthefallingedgesoftwosuccessiveprimaryframe-syncsignals.
Thistimeistheconversionperiod.
Forexample,tosettheconversionrateto8kHz,MCLK=256*N*8000.
NOTE:ThevalueofNisdefinedincontrolregister2anditspower-upvalueis32.
2.
1.
2ADCSignalChannelBothIN(INP,INM)andAUX(AURXFP,AURXM)inputscanusethebuilt-inantialiasingfilterthatcanbebypassedbywritinga1tobitD5ofcontrolregister1.
TheAUXinputcanalsobeconnectedtothegeneral-purposeamplifierA1forgeneral-purposeapplications,suchaselectret-microphoneinterfaceand2-to-4-wirehybridinterface,bywritinga1tobitD6ofcontrolregister1.
BitD4ofcontrolregister1selectsbetweenINorAUXfortheADC.
TheselectedinputsignalisamplifiedbythePGAandappliedtotheADCinput.
TheADCconvertsthesignalintodiscrete-outputdigitalwordsin2s-complementdataformat,correspondingtotheanalog-signalvalueatsamplingtime.
These16-bit(or15-bit)digitalwords,representingsampledvaluesoftheanaloginputsignalafterPGA,areclockedoutoftheserialport(DOUT)atthepositiveedgeofSCLKduringtheframe-sync(FS)intervalattherateofonebitforeachSCLKandonewordforeachprimarycommunication.
Duringsecondarycommunication,thedatapreviouslyprogrammedintotheregisterscanbereadout.
Ifaregisterreadisnotrequired,all16bitsareclearedto0inthesecondarycommunication.
Thisreadoperationisaccomplishedbysendingtheappropriateregisteraddress(D11-D9)withthereadbit(D12)setto1duringpresentsecondarycommunication.
ThetimingsequenceisshowninFigures2–1and2–2.
ThedecimationFIRfiltercanbebypassedbywritinga1tobitD2ofcontrolregister1.
ThewholeADCchannelcanbeturnedoffforpowersavingsbywriting01tobitsD2andD1ofcontrolregister3.
D016SCLKsSCLKFSDOUT(16-bit)DOUT(15+1-bit)D1MSBLSBLSBD15M/SD1011516MSBD15D14D14……………………NOTES:A.
M/Sisusedtoindicatewhetherthe15-bitdatacomesfromamasteroraslavedevice(master:M/S=1,slave:M/S=0).
B.
TheMSB(D15)isstable(thehostcanlatchthedatainatthistime)atthefallingedgingofSCLKnumber0;thelastbit(D0,M/S)isstableatthefallingedgingofSCLKnumber15.
Figure2–1.
TimingSequenceofADCChannel(PrimaryCommunicationOnly)2–2FSDOUT(16-bit)DOUT(15+1-bit)PrimarySecondary16SCLKs#SCLKsPerSamplingPeriod(SeeNoteC)16–bitADCData15–bitADCData+M/SM/S+RegisterData/M/S+All0(SeeNoteA)#SCLKs(SeeNoteB)M/S+RegisterData/M/S+All0(SeeNoteA)Primary16SCLKsNOTES:A.
M/Sbit(D15)inthesecondarycommunicationisusedtoindicatewhethertheregisterdata(addressandcontent)comefromamasterdeviceoraslavedeviceifreadbitisset.
Otherwise,itisall0sexceptM/Sbit(master:M/S=1,slave:M/S=0).
B.
ThenumberofSCLKsbetweenFS(primary)andFS(secondary)is128ifcascadingdevicesarelessthan5,or256ifcascadingdevicesaregreaterthan4.
C.
ThenumberofSCLKsperdatasamplingperiodis256ifcascadingdevicesarelessthan5,or512ifcascadingdevicesaregreaterthan4.
Figure2–2.
TimingSequenceofADCChannel(PrimaryandSecondaryCommunication)2.
1.
3DACSignalChannelDINreceivedthe16-bitserialdataword(2scomplement)fromthehostduringtheprimarycommunicationinterval.
These16-bitdigitalwords,representinganalogoutputsignalbeforePGA,areclockedintotheserialport(DIN)atthefallingedgeofSCLKduringtheframe-syncinterval,onebitforeachSCLKandonewordforeachprimarycommunicationinterval.
Thedataareconvertedtoapulsetrainbythesigma-deltaDACcomprisedofadigital-interpolationfilterandadigital1-bitmodulator.
Theoutputofthemodulatoristhenpassedtoaninternallow-passfiltertocompletethesignalreconstruction.
Finally,theresultinganalogsignalappliedtotheinputofaprogrammable-gainamplifieriscapableofdifferentiallydrivinga600-ohmloadatOUTPandOUTM.
ThetimingsequenceisshowninFigure2–3.
Duringsecondarycommunication,thedigitalcontrolandconfigurationdata,togetherwiththeregisteraddress,areclockedinthroughDIN(seeAppendixAforregistermap).
These16-bitdataareusedeithertoinitializetheregisterorreadoutregistercontentthroughDOUT.
Ifaregisterinitializationisnotrequired,ano-operationword(D15-D9areallsetto0)canbeused.
IfD12issetto1,thecontentofthecontrolregister,specifiedbyD7-D0,aresentoutthroughDOUTduringthesamesecondarycommunication(seeSection2.
1.
5).
ThetimingsequenceisshowninFigure2–4.
TheinterpolationFIRfiltercanbebypassedbywritinga1tobitD2ofcontrolregister1.
ThewholeDACchannelcanbeturnedoffforpowersavingsbywriting10tobitsD2andD1ofcontrolregister3.
2–3D016SCLKsSCLKFSDIN(16-bit)DIN(15+1-bit)D1MSBLSBLSBD15D0=0D1011516MSBD15D14D14……………………14(SeeNoteA)NOTEA:d0=0meansnosecondary-communicationrequest(softwaresecondary-requestcontrol,seeSection3.
2).
Figure2–3.
TimingSequenceofDACChannel(PrimaryCommunicationOnly)FSDIN(16-bit)(SeeNoteA)DIN(15+1-bit)PrimarySecondary16SCLKs#SCLKsBetweenSamplingPeriod(SeeNoteD)16–bitDACData#SCLKsBetweenPrimary16SCLKsFS(Primary)andFS(Secondary)(SeeNoteC)15–bitDACData+D0=1(SeeNoteB)RegisterRead/WriteRegisterRead/WriteNOTES:A.
FChastobesethighforasecondarycommunicationrequestwhen16-bitDACdataformatisused(seeSection3.
2).
B.
D0=1meanssecondarycommunicationrequest(softwaresecondaryrequestcontrol,seeSection3.
2)C.
ThenumberofSCLKsbetweenFS(Primary)andFS(Secondary)is128ifcascadingdevicesarelessthan5,or256ifcascadingdevicesaregreaterthan4.
D.
ThenumberofSCLKsperdatasamplingperiodis256ifcascadingdevicesarelessthan5,or512ifcascadingdevicesaregreaterthan4.
Figure2–4.
TimingSequenceofDACChannel(PrimaryandSecondaryCommunication)2–42.
1.
4MICInputTheauxiliaryinputs(AURXFP,AURXCP,andAURXM)canbeprogrammedtointerfacewithamicrophonesuchasanelectretmicrophone,asillustratedinFigure2.
5,bywritinga1tobitD6andD4ofcontrolregister1.
EnablingMICinputwithDGautomaticallyselectsAURxchannelforADCinput.
Sigma-DeltaADCPGATLV320AIC10Anti-AliasingFilterAURXFPElectretMicrophoneMIC_BIASVMID10kAURXMAURXCPS2D+–1k10k0.
1FVrefFigure2–5.
TypicalMicrophoneInterface2.
1.
5AntialiasingFilterThebuilt-inantialiasingfilterhasa3-dBcutofffrequencyof70kHz.
2.
1.
6Sigma-DeltaADCThesigma-deltaanalog-to-digitalconverterisasigma-deltamodulatorwith128*oversampling.
TheADCprovideshigh-resolution,low-noiseperformanceusingoversamplingtechniques.
Duetotheoversamplingemployed,onlysingle-poleRCfiltersarerequiredontheanaloginputs.
2.
1.
7DecimationFilterThedecimationfiltersreducethedigitaldataratetothesamplingrate.
Thisisaccomplishedbydecimatingwitharatioof1:64.
Theoutputofthedecimationfilterisa16-bit2s-complementdatawordclockingatthesamplerateselectedforthatparticulardatachannel.
TheBWofthefilteris0.
45*FSandscaleslinearlywiththesamplerate.
2.
1.
8Sigma-DeltaDACThesigma-deltadigital-to-analogconverterisasigma-deltamodulatorwith128*oversampling.
TheDACprovideshigh-resolution,low-noiseperformanceusingoversamplingtechniques.
2.
1.
9InterpolationFilterTheinterpolationfilterresamplesthedigitaldataatarateof64timestheincomingsamplerate.
Thehigh-speeddataoutputfromtheinterpolationfilteristhenusedinthesigma-deltaDAC.
TheBWofthefilteris0.
45xFSandscaleslinearlywiththesamplerate.
2–52.
1.
10AnalogandDigitalLoopbackTheanaloganddigitalloopbacksprovideameansoftestingthemodemdataADC/DACchannelsandcanbeusedforin-circuitsystemleveltests.
TheanalogloopbackroutestheDAClow-passfilteroutputintotheanaloginputwhereitisthenconvertedbytheADCtoadigitalword.
ThedigitalloopbackroutestheADCoutputtotheDACinputonthedevice.
Analogloopbackisenabledbywriting01tobitsD7andD6respectivelyincontrolregister3.
Digitalloopbackisenabledbywriting10tobitsD7andD6incontrolregister3(seeAppendixA).
2.
1.
11FIROverflowFlagThedecimatorFIRfiltersetsanoverflowflag(bitD7)incontrolregister1toindicatethattheinputanalogsignalhasexceededtherangeoftheinternaldecimation-filtercalculations.
WhentheFIRoverflowflaghasbeensetintheregister,itremainssetuntiltheregisterisreadbytheuser.
Readingthisvalueresetstheoverflowflag.
IfFIRoverflowoccurs,theinputsignalhastobeattenuatedeitherbythePGAorsomeothermethod.
2.
1.
12FIRBypassModeAnoptionisprovidedtobypasstheFIRfiltersectionsofthedecimationandinterpolationfilters.
ThismodeisselectedthroughbitD2ofcontrolregister1,andeffectivelyincreasesthefrequencyoftheFSandSCLKsignalsto4timesthenormalFIR-filteroutputrate,sincethedecimation/interpolationfactorofthebypassedfilterstageis4.
Thesincfiltersofthetwopathscannotbebypassed.
TheAIC10iscapableofsupportingamaximumoffourdevicesincascade.
IftheFIRfilterisbypassed,thesignal-to-noiseratio(SNR)isreducedto69dB.
TheFIRbypassmodeoffersuserstheflexibilitytoimplementtheirowndecimation/interpolationFIRfilterbasedonapplication-specificrequirements.
ForexampleuserscanselectthismodetobypassbothdecimationandinterpolationFIRfiltersandimplementalower-orderFIRfilteroranIIRfilterexternallyintheDSPforapplicationsthatrequiregroupdelayssmallerthan17/Fs,whichistheAIC10stotalgroupdelay.
2.
1.
13Low-PowerModeToselectthelow-powermode,inwhichtheAIC10typicallyconsumes38.
6mW,setbitD7ofcontrolregister2to1andsetthesamplingrateat8ksps.
2.
1.
14Event-MonitorModeThismodeisonlyavailableduringtheregister-writecycle,andisenabledbywriting11tobitsD6andD7ofcontrolregister3;performingaregisterreadterminatesevent-monitormode3.
Theeventmonitormodeisprovidedforapplicationsthatneedhardwarecontrolandmonitoringofexternalevents.
ByallowingthedevicetodrivetheFLAGterminal(setthroughbitD3ofthecontrolregister3),thehostDSPiscapableofsystemcontrolthroughthesameserialportthatconnectsthedevice.
AlongwiththiscontrolisthecapabilityofmonitoringthevalueoftheALTINterminalduringasecondarycommunicationcycle.
OneapplicationofthisfunctionisinmonitoringRINGDETECTorOFFHOOKDETECTfromaphone-answeringsystem.
FLAGallowsresponsetotheseincomingcontrolsignals.
Figure2–6showsthetimingassociatedwiththisoperatingmode.
FSDOUTALTDIPrimarySecondary16bitsNOTEA:WhenDINperformsawriteoperation(setsD12to0)duringsecondarycommunication.
Figure2–6.
EventMonitorModeTiming2–62.
2ResetandPower-DownFunctions2.
2.
1SoftwareandHardwareResetTheTLV320AIC10resetstheinternalcountersandregistersinresponsetoeitheroftwoevents:Alow-goingresetpulseisappliedtoterminalRESETA1iswrittentotheprogrammable-softwareresetbit(D3ofcontrolregister1)Eithereventresetsthecontrolregistersandclearsallthesequentialcircuitsinthedevice.
Resetsignalsshouldbeatleastsixmaster-clockperiodslong.
Itisrecommendedtosynchronizetheresetsignalwiththemasterclockinmaster/slavecascade,andtotieallresetpinstogether.
Fordevicesincascade,ittakesatleasttwoFScyclestoapplysoftwareresettoalldevices,withthemasterbeingalwaysprogrammedlast.
2.
2.
2SoftwareandHardwarePowerDownWiththeexceptionofthedigitalinterface,thedeviceentersthepower-downmodewhenD1andD2incontrolregister3aresetto1.
WhenPWRDWNistakenlow,theentiredeviceispowereddown.
Ineithercase,theregistercontentsarepreservedandtheoutputofthemonitoramplifierisheldatthemidpointvoltagetominimizepopsandclicks.
Theamountofpowerdrawnduringsoftwarepowerdownishigherthanitisduringahardwarepowerdownbecauseofthecurrentrequiredtokeepthedigitalinterfaceactive.
Additionaldifferencesbetweensoftwareandhardwarepower-downmodesaredetailedinthefollowingparagraphs.
Figure2–7representstheinternalpower-downlogic.
PWRDWNSoftwarePowerDown(ForControlRegister3,D1&D2)D1andD2AreProgrammedThroughaSecondaryWriteOperationInternalTLV320AIC10Figure2–7.
InternalPower-DownLogic2.
2.
2.
1SoftwarePowerDownWhenD1andD2ofcontrolregister3aresetto1,TLV320AIC10entersthesoftwarepower-downmode.
Inthisstate,thedigital-interfacecircuitisstillactive,whiletheinternalADCandDACchannelsanddifferentialoutputsOUTPandOUTMaredisabled,andDOUTandFSDareinactive.
Registerdatainsecondaryserialcommunicationsisstillaccepted,butdatainprimaryserialcommunicationsisignored.
ThedevicereturnstonormaloperationwhenD1andD2ofcontrolregister3arereset.
2.
2.
2.
2HardwarePowerDownWhenPWRDWNisheldlow,thedeviceentersthehardwarepower-downmode.
Inthisstate,theinternal-clockcontrolcircuitandthedifferentialoutputsOUTPandOUTMaredisabled.
AllotherdigitalI/Osareeitherdisabled,orremaininthesamestatetheywereinimmediatelybeforepowerdown.
DINcannotacceptanydatainput.
ThedevicecanonlybereturnedtonormaloperationbytakingandholdingPWRDWNhigh.
Whennotholdingthedeviceinthehardwarepower-downmode,PWRDWNshouldbetiedhigh.
2–72.
3ClockSourceMCLKistheexternalmaster-clockinput.
Theclockcircuitgeneratesanddistributesthenecessaryclocksthroughoutthedevice.
Whenthedeviceisinthemastermode,SCLKandFSareoutputandderivedfromMCLKinordertoprovideclockingoftheserialcommunicationsbetweenthedeviceandaDSP(digitalsignalprocessor).
Whenintheslavemode,SCLKandFSareallinputs.
TheSCLKcanbeconnectedtoafasterclocksourcetospeedupserialcommunicationbetweentheslaveandthemasterwhiletheinternalclockismaintainedat256clocksperFSperiodforinternalprocessing.
InSPImode,thedeviceisaslaveandSCLKisconnectedtotheSPICLKsource.
2.
4DataOut(DOUT)DOUTisplacedinthehigh-impedancestateaftercompletingtransmissionoftheLSB.
InprimarycommunicationthedatawordistheADCconversionresult.
Insecondarycommunicationthedataintheregisterreadresultswhenrequestedbytheread/write(R/W)bit.
Ifaregisterreadisnotrequested,theloweightbitsofthesecondarywordareallzeroes.
Thestateofthemaster/slave(M/S)terminalisreflectedbytheMSBinsecondarycommunication(DOUT,bitD15),andbytheLSBinprimarycommunication(DOUT,bitD0).
2.
4.
1DataOut,MasterModeInthemastermode,DOUTistakenfromthehigh-impedancestatebythefallingedgeofthemasterframe-sync(FS).
ThemostsignificantdatabitthenappearsfirstonDOUT.
2.
4.
2DataOut,SlaveModeIntheslavemode,DOUTistakenfromthehigh-impedancestatebythefallingedgeoftheexternalframe-sync(FS).
ThemostsignificantdatabitthenappearsfirstonDOUT.
2.
5DataIn(DIN)Inaprimarycommunication,thedatawordistheinputdigitalsignaltotheDACchannel.
If(15+1)-bitdataformatisused,theLSB(D0)isusedtorequestasecondarycommunication.
Inasecondarycommunication,thedataisthecontrolandconfigurationdatathatsetsthedeviceforaparticularfunction(seeSection3,SerialCommunications).
TheLSBofcontrolregister1determineswhetheritisa15-bitora16-bitinput.
2.
6FC(HardwareSecondaryCommunicationRequest)TheFCinputprovidesforhardwarerequestsforsecondarycommunications.
FCworksinconjunctionwiththeLSBoftheprimarydataword.
FCshouldbetiedlowifnotused.
2.
7Frame-SyncFunctionforTLV320AIC10Theframe-syncsignal(FS)indicatesthedeviceisreadytosendorreceivedata.
FSisanoutputiftheM/SpinisconnectedtoHI(mastermode),andaninputiftheM/SpinisconnectedtoLO(slavemode).
TheoutputFSDisadelayversionofthefirstframe-syncsignal(FS)thatisoutput32SCLKsafterthefirstFS,andservesastheframe-syncinputtothenextslave(seeFigure2–14).
ThedatatransferredoutofDOUTandintoDINbeginsonthefallingedgeoftheFSsignal.
Itcanbeconfiguredasaframeorasapulsesignal,asdeterminedbypinsM0andM1.
Innormaloperation,thedigitalserialinterfaceconsistsoftheshiftclock(SCLK),theframe-syncsignal(FS),theADC-channeldataoutput(DOUT),andtheDAC-channeldatainput(DIN).
Duringtheprimaryframe-synchronizationinterval,SCLKclockstheADCchannelresultsoutthroughDOUT,andclocks16-bit/(15+1)DACdatainthroughDIN.
Duringthesecondaryframe-syncinterval,SCLKclockstheregisterdataoutthroughDOUTinnormaloperation.
Ifthereadbit(D12)issetto1andthedevicetransferscontrolanddeviceparameterinthroughDOUT.
ThetimingsequenceisshowninFigures2-1,2-2,2-3,and2-4.
2–8TheTLV320AIC10hasfourserial-interfacemodesthatsupportmostmodernDSPengines.
ThismodescanbeselectedbyM0andM1.
Inmode0(Figure2–8),FSisone-bitwideanditisactivehighoneSCLKperiodbeforethefirstbit(MSB)ofeachdatatransmission.
Inmodes1(Figure2–9)and2(Figure2–10),theTLV320AIC10operatesasaslavetointerfacewithanSPImasterinwhichFSistheSPISELthatdeterminesthesamplingrate.
SCLKneedstobefree-running.
Inmode3(Figure2–11),FSislowduringdatatransmissionintoDINandDOUT.
Table2–1.
SerialInterfaceModesMODEM1M0FRAMESYNC(FS)FORMAT000Pulsemode101SPI_CP0mode(SPImode0)210SPI_CP1mode(SPImode1)311FramemodeD016SCLKsSCLKFSDIN/DOUT(16-bit)D1MSBLSBD15011516D14………………14Figure2–8.
TimingDiagramfortheFSPulseMode(M1M0=00)D016SCLKs(SCLK)(FS)DIN/DOUT(16-bit)D1MSBLSBD150115D14………………14SPICLKSPISELFigure2–9.
TimingDiagramfortheSPI_CP0Mode(M1M0=01)D016SCLKs(SCLK)(FS)DIN/DOUT(16-bit)D1MSBLSBD150115D14………………14SPICLKSPISELFigure2–10.
TimingDiagramfortheSPI_CP1Mode(M1M0=10)2–9D016SCLKsSCLKFSDIN/DOUT(16-bit)D1MSBLSBD15011516D14………………14Figure2–11.
TimingDiagramfortheFSFrameMode(M1M0=11)NOTE:Inframemode,ifAIC10isinslavemode,DIN/DOUTshouldbedelayedbyoneSCLKfromthefallingedgeofFS.
2.
7.
1Frame-Sync(FS)Function—Continuous-TransferMode(MasterOnly)Writinga1tobitD5ofcontrolregister3enablesthecontinuous-transfermode.
Inthismode,thedatabitsaretransmittedandreceivedcontiguouslywithnoinactivitybetweenbitsattheverynextFS,andnofurtherframesyncFSsaregenerated.
Secondarycommunicationisnotavailable.
Todisablethecontinuoustransfermode,usethedirect-configurationmode(seeSection3.
3)orresetthedevice.
2.
7.
2Frame-Sync(FS)Function—Fast-TransferMode(SlaveOnly)ByconnectingthefastclocktotheSCLKpin,datacanbetransmittedandreceivedatahigherratethan256xFsintheslavemodeforastand-aloneAIC10.
2.
7.
3Frame-Sync(FS)Function—MasterModeThemastermodeintheTLV320AIC10isselectedbyconnectingpinM/SpintoHI.
Inthemastermode,theTLV320AIC10generatestheframe-syncsignal(FS)totheDSPthatgoeslowontherisingedgeofSCLKandremainslowduringa16-bitdatatransfer.
DIN/DOUTPrimarySecondary16SCLKsPrimary16SCLKsFS(seeNoteB)FS(seeNoteA)PrimaryPrimaryNOTES:A.
PrimaryandsecondaryserialcommunicationsB.
PrimaryserialcommunicationonlyFigure2–12.
MasterDeviceFrame-SyncSignalWithPrimaryandSecondaryCommunication(NoSlaves)2–102.
7.
4Frame-Sync(FS)Function—SlaveModeTheslavemodeisselectedbyconnectingpinM/StoLO.
Theframe-synctimingisgeneratedexternallybythemaster,asshowninFigure2–13(thatis,FSD)andisappliedtoFSoftheslavetocontroltheADCandDACtiming.
MP32SCLKsFSD(Master)toFS(Slave)FS(MastertoDSP)SPMSSSMPNOTE:MP:masterprimary(master-devicedataistransferredduringthisperiod,theDOUToftheslavedeviceisinhigh-impedancestate).
SP:slaveprimary(slavedevicedataistransferredduringthisperiod,theDOUTofmasterdeviceisinhigh-impedancestate).
MS:mastersecondary(masterdevicecontrolregisterinformationistransferredduringthisperiod,theDOUTofslavedeviceisinhigh-impedancestate).
SS:slavesecondary(slavedevicecontrolregisterinformationistransferredduringthisperiod,theDOUTofmasterdeviceisinhigh-impedancestate).
Figure2–13.
MasterDevice'sFSOutputtoDSPandFSDOutputtotheSlave2.
7.
5Frame-SyncDelayed(FSD)Function,CascadeModeIncascademode,theDSPmustbeabletoidentifythemasterandslavesaccordingtotheregistermapshowninAppendixA.
Eachdeviceinthecascadecontainsa3-bitcascaderegister(D15-D13intheregisteraddress)thathasbeenprogrammedbytheACD(automaticcascadedetection)withanaddressvalueequaltoitspositioninthecascadeduringthedevice'spower-upinitialization(seeAppendixA).
Thedeviceaddressofthemasterisalwaysequaltothenumberofslavesinthecascade.
Forexample,inFigure2–14,D15-D13ofthemasteris011,asshowninrow4ofTableA-1(AppendixA).
TheDSPreceivesallframe-syncpulsesfromthemasterthoughthemastersFS.
ThemasterFSDisoutputtothefirstslave,andthefirstslaveFSDisoutputtothesecondslavedevice,andsoon.
Figure2–14showsthecascadeof4TLV320AIC10sinwhichtheclosestonetotheDSPisthemaster,andtherestareslaves.
TheFSDoutputofeachdeviceisinputtotheFSterminalofthesucceedingdevice.
Figure2–15showstheFSDtimingsequenceinthecascade.
MCLKDINDOUTFSSCLKMCLKDINDOUTFSSCLKMCLKDINDOUTFSSCLKSlave2Slave1Slave0MasterMCLKDINDOUTFSDSCLKFSDFSDFSCLKOUTDXDRFSXFSRCLKXCLKRTMS320C54XXDVDDFSDM/SM/SM/SM/S(orMasterClockSource)DVDD1kFigure2–14.
CascadeModeConnection(toDSPInterface)2–11M32SCLKsMasterFSPS2PS1PS0PMSS2SSMasterFSD,Slave2FSSlave2FSD,Slave1FSSlave1FSD,Slave0FSSlave0FSD(SeeNote)32SCLKs32SCLKs32SCLKsFigure2–15.
Master-SlaveFrame-SyncTiming2.
8MultiplexedAnalogInputandOutputThetwodifferentialanaloginputs(INPandINM,orAUXPandAUXM)aremultiplexedintothesigma-deltamodulator.
TheperformanceoftheAUXchannelissimilartothenormal-inputchannel.
Thegainoftheinputamplifiersissetthroughcontrolregister4.
2.
8.
1MultiplexedAnalogInputToproduceexcellentcommon-moderejectionofunwanted-signalperformance,theanalogsignalisprocesseddifferentiallyuntilitisconvertedtodigitaldata.
ThesignalappliedtotheINMandINPterminalsshouldbedifferentialtopreservethedevicespecifications.
Thesignalsourcedrivingtheanaloginputs(INPandINM,orAUXPandAUXM)shouldhavealowsourceimpedancetoattainthelowestnoiseperformanceandaccuracy.
Toobtainmaximumdynamicrange,thesignalshouldbeac-coupledtotheinputterminal.
Theanaloginputsignalisself-biasedtothemid-supply.
BitsD3andD4ofcontrolregister1selecttheseinputsources.
Thedefaultconditionself-biasestheinput,sincetheregisterdefaultvalueselectsINPandINMasthesourcesfortheADC.
TLV320AIC10INPVINPINMVINMAVDD/2Figure2–16.
INPandINMInternalSelf-Biased(AVDD/2)Circuit2–122.
8.
2AnalogOutputOUTPandOUTMaredifferentialoutputsandcantypicallydrivea600-loaddirectly.
Figure2–17showsthecircuitwhentheloadisground-referenced.
–OUTM+10k10k10kLoad10k+5V–5VTLE2062OUTPFigure2–17.
DifferentialOutputDrive(Ground-Referenced)2.
8.
3Single-EndedAnalogInputThetwodifferentialinputs(INPandINM,orAUXPandAUXM)canbeconfiguredtoworkassingle-endedinputsbyconnectingINPorAUXPtotheanaloginput,andINMorAUXMtotheexternalcommon-modeinput.
ThisisillustratedinFigure2–18.
Followingarethevalidsingle-endedinputconfiguration:Ifthesignalcommon-modeisabout2.
5V,thenconnectsignaltoINPanditscommonmodetoINM.
Ifthecommonmodeoftheinputsignalisdifferentfrom2.
5V,thencapacitivelycouplesignalontoINPandcapacitivelycouplecommonmodeontoINM.
Specialcase:IfcommonmodeofsignalisAGND,thencapacitivelycoupleAGNDontoINM.
WheneverINPandINMarebothcapacitivelycoupledthedeviceinternallysetsthebias.
NeverconnectAGNDdirectlytoINM.
ItsetsinputcommonmodetoAGNDwhichwouldmeanthenegativegoingsignalgetsclamped.
AnalogInputINPINMCommon-ModeInputCFigure2–18.
Single-EndedInput2.
8.
4Single-EndedAnalogOutputThedifferentialoutputofTLV320AIC10canbeconfiguredasasingle-endedoutput.
ThisisillustratedinFigure2–19.
RLOUTPOUTMCFigure2–19.
Single-EndedOutput3–13SerialCommunicationsDOUT,DIN,SCLK,SXCLK,FS,andFcaretheserialcommunicationsignals.
SCLKisusedtoperforminternalprocessinganddatatransferforserialinterfacebetweenAIC10andDSP.
Inthepulse/frameFSmode,thereare256SCLKspersamplingperiod(512iftherearemorethan4devicesincascade).
Thedigital-outputdatafortheADCistakenfromDOUT.
Thedigital-inputdatafortheDACisappliedtoDIN.
Thesynchronizationclockfortheserialcommunicationdataandtheframe-syncistakenfromSCLK.
Theframe-syncsignalthatstartstheADCandDACdata-transferintervalistakenfromFS.
PrimaryserialcommunicationisusedforsignaldatatransmittedfromtheADCortotheDAC.
Secondarycommunicationisusedtoreadorwritewordsthatcontrolboththeoptionsandthecircuitconfigurationsofthedevice.
Thepurposeoftheprimaryandsecondarycommunicationsistoallowconversiondataandcontroldatatobetransferredacrossthesameserialport.
Aprimarytransferisalwaysdedicatedtoconversiondata.
Asecondarytransferoranasynchronouscommunicationisusedtosetupand/orreadtheregistervalues.
Aprimarytransferoccursforeveryconversionperiod.
Asecondarytransferoccursonlywhenrequested.
Secondaryserialcommunicationcanberequestedeitherbyhardware(FCterminal)orbysoftware(D0ofprimarydatainputtoDIN).
ThedirectconfigurationmodeusespinDCSItoprogramcontrolregistersinstantly.
3.
1PrimarySerialCommunicationPrimaryserialcommunicationisusedtotransmitandreceiveconversionsignaldata.
TheDACwordlengthdependsonthestatesofbitD0incontrolregister1.
Afterpoweruporreset,thedevicedefaultsto15-bitmode.
WhentheDACwordlengthis15bits,thelastbitoftheprimary16-bitserialcommunicationwordisacontrolbitusedtorequestsecondaryserialcommunication.
Inthe16-bitmode,all16bitsoftheprimary-communicationwordareusedasdatafortheDAC,andthehardwareterminalFCmustbeusedtorequestsecondarycommunication.
Figure3-1showsthetimingrelationshipforSCLK,FS,DOUT,andDINinaprimarycommunication.
Thetimingsequenceforthisoperationisasfollows:FSisbroughtlowbytheTLV320AIC10.
A16-bitwordistransmittedfromtheADC(DOUT),andthena16-bitwordisreceivedfromtheDAC(DIN).
D0D13D15D14D12D11D10D9D8D7D6D5D4D3D2D1SCLKFSDIND0D13D15D14D12D11D10D9D8D7D6D5D4D3D2D1DOUTFigure3–1.
PrimarySerialCommunicationTiming3–23.
2SecondarySerialCommunicationSecondaryserialcommunicationisusedtoreadorwrite16-bitwordsthatprogramboththeoptionsandthecircuitconfigurationsofthedevice.
Registerprogrammingalwaysoccursduringsecondarycommunication.
Fourprimaryandsecondarycommunicationcyclesarerequestedtoprogramthefourregisters.
Ifthedefaultvalueforaparticularregisterisdesired,thentheregisteraddressingcanbeomittedduringsecondarycommunications.
TheNOOPcommandaddressesapseudo-register(register0),andnoregisterprogrammingtakesplaceduringthissecondarycommunication.
Ifsecondarycommunicationisdesiredforanydevice(eithermasterorslave),thenasecondarycommunicationmustberequestedforalldevices,startingwiththemaster.
Thisresultsinasecondaryframe-sync(FS)foralldevices.
TheNOOPcommandcanbeusedfordevicesthatdonotneedasecondaryoperation.
Duringasecondarycommunication,aregistercanbewrittentoorreadfrom.
Whenwritingtoaregister,DINcontainsthevaluetobewritten.
ThedatareturnedonDOUTis+0000000000000(3-bitdeviceaddress).
Therearetwomethodsofinitiatingasecondarycommunication,asillustratedinFigure3–2:AssertingahighlevelonFC(hardwarerequest)AssertingtheLSBoftheDIN16-bitserialcommunicationhighwhileinthe15-bitmode(softwarerequest)NOTE:Thesecondarycommunicationrequestshouldnotbeassertedduringthefirsttwosamplesafterpowerup.
FC(Hardware)16-BitMode(Control1Register,D0)InternalTLV320AIC10(LSBofDIN)SecondaryRequestFigure3–2.
HardwareandSoftwareSecondaryCommunicationRequestPullingFChighcausesthestartofthesecondarycommunications128or256SCLKs(seeFigures2–2and2–4)afterthestartoftheprimarycommunicationframe,dependingonthenumberofdevicesincascade.
ThesecondmethodtoinitiateasecondarycommunicationisassertingtheLSBhigh.
AsoftwarerequestistypicallyusedwhentherequestresolutionoftheDACchannelislessthan16bits.
Thentheleastsignificantbit(D0)canbeusedforsecondaryrequests,asshowninTable3–1.
Therequestismadebyplacingthedeviceinthe15-bitDACmodeandmakingtheLSBofDINhigh.
Allcascadingdevicesmustbein15-bitDACmode,andsettheirLSBsto1sforrequestingsoftwaresecondarycommunication.
Table3–1.
LeastSignificantBitControlFunctionCONTROLBITD0CONTROLBITFUNCTION0Nooperation(NOOP)1Secondarycommunicationrequest3–33.
2.
1RegisterProgrammingAllregisterprogrammingoccursduringsecondarycommunicationthroughDINorALTI,anddataarelatchedandvalidonthefallingedgeoftheSCLKduringtheframe-syncsignal.
Ifthedefaultvalueofaparticularregisterisdesired,thatregisterdoesnotneedtobeaddressedduringthesecondarycommunicationinterval.
TheNOOPcommand(DS15-DS8allsetto0)addressesthepseudo-register(register0),andnoregisterprogrammingtakesplaceduringthecommunication.
Inaddition,eachregistercanbereadbackthroughDOUTduringsecondarycommunicationsbysettingthereadbit(D12)to1.
Whenaregisterisinthereadmode,nodatacanbewrittentotheregisterduringthiscycle.
Asubsequentsecondarycommunicationisrequiredtoreturnthisregistertothewritemode.
Forexample,ifthecontentsofcontrolregister1ofdevice3aredesiredtobereadoutfromDOUT,thefollowingproceduremustbeperformedthroughDIN:RequestsecondarycommunicationbysettingeitherD0=1(softwarerequest),orFC=high(hardwarerequest)duringtheprimarycommunicationinterval.
Duringthesecondarycommunicationinterval(FS),senddatainthroughDINusingthefollowingformat:DeviceAddressRWRegisterAddressXRegisterContent0111001xxxxxxxxxDS15DS0Then,duringthesameframe,thefollowingdataisreadfromDOUT;thelast8bitsofDOUTcontainsregister1data.
DeviceAddressRWRegisterAddressXRegisterContent011xxxxxddddddddDS15DS0Figure3–3isthetimingdiagramofthisprocedure.
DOUTPSDINRegister1ReadFSLow8Bit(D0–D7)IstheContentofRegister1Figure3–3.
Device3/Register1ReadOperationTimingDiagram3–4Toprogramcontrolregister1,thefollowingproceduremustbeperformedthroughDIN:RequestsecondarycommunicationbysettingeitherD0=1(softwarerequest),orFC=high(hardwarerequest)duringtheprimarycommunicationinterval.
Atthesecondarycommunicationinterval(FS),senddatainthefollowingformatthroughDIN:DeviceAddressRWRegisterAddressXRegisterContent0110001xddddddddDS15DS0ThefollowingisthedataoutofDOUT.
DeviceAddressRWRegisterAddressXRegisterContent0110xxxx00000000DS15DS0Figure3–4isthetimingdiagramofthisprocedure.
DOUTPSDINRegisterWriteFS(DeviceAddr)+All0Figure3–4.
Device3/Register1WriteOperationTimingDiagram3.
2.
2HardwareSecondarySerialCommunicationRequestAsecondarycommunicationcanberequestedbyassertinganFCpulsethatsetsaninternalflag.
Thisflagisresetassoonastheprogrammingofcontrolregistersisfinished.
Thus,oneFCpulseneedstobeassertedpersecondarycommunicationrequest.
Figures3–5and3–6showtheFSoutputfromamasterdevice.
DINFSPrimarySecondaryPrimaryFCSecondaryRequestNoSecondaryRequestDACDataInRegisterRead/WriteDACDataInDOUTADCDataOutRegisterRead/WriteADCDataOutFigure3–5.
FSOutputWhenHardwareSecondarySerialCommunicationIsRequestedOnlyOnce(NoSlave)3–5MMasterFSPS2PS1PS0PMSS2SSFC(SeeNote)S1SS0MP(FCpulseneedstobeinsertedanytimewithintheprimarycommunication)NOTES:A.
FCofmasterdeviceandslavedevicesshouldbeconnectedtogetherB.
Primarycommunicationinterval=256SCLKsifcascadingdevices4Figure3–6.
OutputWhenHardwareSecondarySerialCommunicationIsRequested(ThreeSlaves)3.
2.
3SoftwareSecondarySerialCommunicationRequestTheLSBoftheDACdatawithinaprimarytransfercanrequestasecondarycommunicationthroughbitD0ofcontrolregister1whenthedeviceisinthe15-bitmode.
Forallserialcommunications,themostsignificantbitistransferredfirst.
Fora16-bitADCwordanda16-bitDACword,D15isthemostsignificantbitandD0istheleastsignificantbit.
Fora15-bitDACdatawordinaprimarycommunication,D15isthemostsignificantbit,D1istheleastsignificantbit.
BitD0isthenusedforthesecondarycommunicationrequestcontrol.
Alldigitaldatavaluesarein2s-complementdataformat(seeFigure3–7).
Ifthedataformatissetto16-bitword,all16bitsareeitherADCorDACdata,andsecondarycommunicationcanonlyberequestedbyhardware(FCterminal),orcontrolregisterscanbeprogrammedbythedirectconfigurationmode.
PSDINRegisterFSNoSecondaryCommunicationRequestData(D0=1)Read/WritePData(D0=0)SecondaryCommunicationRequestFigure3–7.
FSOutputDuringSoftwareSecondarySerialCommunicationRequest(NoSlave)3.
3DirectConfigurationModeForDSPapplicationsthatusecontinuousdatatransfermodeforautobuffering,orforDMAoperationsthatdonothavethecapabilitytointerferewiththedataconversionchannelbyinsertingthesecondarycommunication,theTLV320AIC10sdirect-configurationmodeprovidesaflexiblealternativetoprogrammingcontrolregistersthroughpinDCSI.
TheserialinputtoDCSIshouldnormallybeinahighstate,startitsvaliddatawithastartbitoflogiclow,andpullhighasastopbitaftertransmissionoftheLSB.
DCSIrequiresapullupresistorfor3-stateinput.
TheAIC10registersdatabitsonthefallingedgeofSCLK.
Figure3–8showsatypicalconnectionbetweentheC54xandtheAIC10usingDCSIfordirectconfigurationofcontrolregisters.
Figure3–9showsthetimingdiagramforthedirectconfigurationmode.
3–6TMS320C54XXTLV320AIC10DCSIM/SFSDFSDINDOUTSCLKDVDDTLV320AIC10DCSIM/SFSDINDOUTSCLKDGNDDX0FSX1FSR1DX1DR1CLKX1CLKR1CLKX0DVDD1kTMS320C5402TLV320AIC10MCLKDCSIFSDFSDINDOUTSCLKHostProcessorSDOCLKINBFSX0BFSR0BDX0BDR0BCLKX0BCLKR0DVDD1kMCLKM/SDVDD(UsePullupResistorifSDOIs3-StateSerialBus)(a)DirectConfigurationBetweenC54andAIC10(b)DirectConfigurationforHostInterfaceFigure3–8.
DirectConfigurationFSDDVDD1kDVDD1k3–7D0D13D15D14D12D11D10D9D8D7D6D5D4D3D2D1SCLKDCSIStartBit=0DeviceAddressRegisterAddressRegisterDataStopBit=1Figure3–9.
DirectConfigurationModeTimingToprogramcontrolregister1ofdevice3,senddatainwiththefollowingformatthroughDCSI:SBDeviceAddressRegisterAddressXRegisterContent0011001xxxxxxxxxD15D03.
4ContinuousDataTransferModeIncontinuousdatatransfermode,the16-bitconverterdataaretransferredcontiguouslywithnoinactivitybetweenbits.
Thismodeisavailableinthestand-alonemasterwithM1M0=00(FS-pulsemode)andselectedbysettingbitD5ofcontrolregister3to1.
Thesecondarycommunicationrequestisnotallowedinthismodeandthereforethedirectconfigurationmodeshouldbeusedtoprogramtheinternalcontrolregisters.
ThecontinuousdatatransfermodeisdesignedtosupporttheTIDSPMcBSPsautobufferingunit(ABU)operationinwhichserialportinterruptsarenotgeneratedwitheachwordtransferredtopreventCPUsISRoverheads.
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0SCLKFSDINDOUTE15E13E12E15E14E13E12E14C0C0Figure3–10.
ContinuousDataTransferModeTiming3–83.
5DINandDOUTDataFormat3.
5.
1PrimarySerialCommunicationDINandDOUTDataFormatDIN(15+1)-BitModeA/D&D/ADataSecondaryCommunicationRequestD15–D1D0DOUT(15+1)-BitModeM/SBitD15–D1D0DIN16-BitModeA/D&D/ADataD15–D0DOUT16-BitModeD15–D0Figure3–11.
PrimaryCommunicationDINandDOUTDataFormat3.
5.
2SecondarySerialCommunicationDINandDOUTDataFormat0D8D15D14D13XXXXD7–D0D8D15D14D131D11D10D9D7–D0DIN(Read)RegisterAddressDon'tCareReservedR/WDeviceAddressD8D15D14D13D11D10D9D7–D0DIN(Write)DatatotheRegisterDeviceAddressDOUT(Read)RegisterDataFigure3–12.
SecondaryCommunicationDINandDOUTDataFormat3.
5.
3DirectConfigurationDCSIDataFormat0D12RegisterAddressDeviceAddressD8D14D13D11D10D9D7–D0DCSI(Write)DatatotheRegisterStartBitStopBit1Figure3–13.
DirectCommunicationDCSIDataFormat4–14Specifications4.
1AbsoluteMaximumRatingsOverOperatingFree-AirTemperatureRange(UnlessOtherwiseNoted)Supplyvoltagerange,DVDD,AVDD(seeNote1)–0.
3Vto7VOutputvoltagerange,alldigitaloutputsignals–0.
3VtoDVDD+0.
3VInputvoltagerange,alldigitalinputsignals–0.
3VtoDVDD+0.
3VCasetemperaturefor10seconds:package260°COperatingfree-airtemperaturerange,TA–40°Cto85°CStoragetemperaturerange,Tstg–65°Cto150°CStressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.
Thesearestressratingsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperatingconditions"isnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
NOTE1:AllvoltagevaluesarewithrespecttoVSS.
4.
2RecommendedOperatingConditionsMINNOMMAXUNITAnalogsupplyvoltage,AVDD35.
5VDigitalsupplyvoltage,DVDD35.
5VAnalogsignalpeak-to-peakinputvoltage,VI(analog)(5Vsupply),single-ended3VAnalogsignalpeak-to-peakinputvoltage,VI(analog)(3.
3Vsupply),single-ended2VDifferentialoutputloadresistance,RL600Outputloadcapacitance,CL20pFDividerN=Even40MasterclockDividerNOddMaxcascade=4devices15MHzMasterclockDividerN=OddMaxcascade=8devices10MHzADCorDACconversionrate22kHzOperatingfree-airtemperature,TA–4085°C4.
3ElectricalCharacteristicsOverRecommendedOperatingFree-AirTemperatureRange,AVDD=5V/3.
3V,DVDD=5V/3.
3V4.
3.
1DigitalInputsandOutputs,Fs=8kHz,OutputNotLoadedPARAMETERTESTCONDITIONSMINTYPMAXUNITVOHHigh-leveloutputvoltage,DOUTIO=-360A2.
4DVDD+0.
5VVOLLow-leveloutputvoltage,DOUTIO=2mADVSS–0.
50.
4VIIHHigh-levelinputcurrent,anydigitalinputVIH=5V10AIILLow-levelinputcurrent,anydigitalinputVIL=0.
6V10ACiInputcapacitance10pFCoOutputcapacitance10pF4–24.
3.
2ADCPathFilter,Fs=8kHz(seeNote2)PARAMETERTESTCONDITIONSMINTYPMAXUNIT0Hzto300Hz–0.
50.
2300Hzto3kHz–0.
50.
25Filtergainrelativetogainat1020Hz3.
3kHz–0.
50.
3dBFiltergainrelativetogainat1020Hz3.
6kHz–3dB4kHz–35≥4.
4kHz–74NOTE2:Thefiltergainoutsideofthepassbandismeasuredwithrespecttothegainat1024Hz.
Theanaloginputtestsignalisasinewavewith0dB=4VI(PP)asthereferencelevelfortheanaloginputsignal.
Thepassbandis0to3600Hzforan8-kHzsamplerate.
Thispassbandscaleslinearlywiththesamplerate.
4.
3.
3ADCDynamicPerformance,Fs=8kHz4.
3.
3.
1ADCSignal-to-Noise(seeNote3)PARAMETERTESTCONDITIONSMINTYPMAXUNITVI=–1dB7884SNRSignaltonoiseratioVI=–3dB7681dBSNRSignal-to-noiseratioVI=–9dB7278dBVI=–40dB3742NOTE3:Thetestconditionisa1020-Hzinputsignalwithan8-kHzconversionrate.
Inputandoutputcommonmodeis2.
5Vfor5-Vsupply,and1.
5-Vfor3.
3-Vsupply.
4.
3.
3.
2ADCSignal-to-Distortion(seeNote3)PARAMETERTESTCONDITIONSMINTYPMAXUNITVI=–1dB7680THDSignaltototalharmonicdistortionVI=–3dB7680dBTHDSignal-to-totalharmonicdistortionVI=–9dB8085dBVI=–40dB6472NOTE3:Thetestconditionisa1020-Hzinputsignalwithan8-kHzconversionrate.
Inputandoutputcommonmodeis2.
5Vfor5-Vsupply,and1.
5-Vfor3.
3-Vsupply.
4.
3.
3.
3ADCSignal-to-Distortion+Noise(seeNote3)PARAMETERTESTCONDITIONSMINTYPMAXUNITVI=–1dB7680THD+NSignaltototalharmonicdistortion+noiseVI=–3dB7479dBTHD+NSignal-to-totalharmonicdistortion+noiseVI=–9dB7278dBVI=–40dB3843NOTE3:Thetestconditionisa1020-Hzinputsignalwithan8-kHzconversionrate.
Inputandoutputcommonmodeis2.
5Vfor5-Vsupply,and1.
5Vfor3.
3-Vsupply.
4–34.
3.
4ADCChannelCharacteristicsPARAMETERTESTCONDITIONSMINTYPMAXUNITVI(PP)Peak-to-peakinputvoltage(differential)Preampgain=0dB4VDynamicrangeVI=–3dB82dBIntrachannelisolation87dBEGGainerrorVI=–1dBat1020Hz0.
6dBEO(ADC)ADCconverteroffseterror±15mVCMRRCommon-moderejectionratioatINM,INPorAUXM,AUXPVI=–1dBat1020Hz80dBIdlechannelnoise(on-chipreference)VINP,INM=0V2570VrmsRjInputresistanceTA=25°C35kChanneldelay17/fss4.
3.
5DACPathFilter,Fs=8kHz(seeNote4)PARAMETERTESTCONDITIONSMINTYPMAXUNIT0Hzto300Hz–0.
50.
2300Hzto3kHz–0.
650.
25Filtergainrelativetogainat1020Hz3.
3kHz–0.
750.
3dBFiltergainrelativetogainat1020Hz3.
6kHz–3dB4kHz–35≥4.
4kHz–74NOTE4:Thefiltergainoutsideofthepassbandismeasuredwithrespecttothegainat1020Hz.
Theinputsignalisthedigitalequivalentofasinewave(digitalfullscale=0dB).
ThenominaldifferentialDACchanneloutputwiththisinputconditionis6VI(PP).
Thepassbandis0to3600Hzforan8-kHzsamplerate.
Thispassbandscaleslinearlywiththeconversionrate.
4.
3.
6DACDynamicPerformance4.
3.
6.
1DACSignal-to-NoiseWhenLoadis600(seeNote5)PARAMETERTESTCONDITIONSMINTYPMAXUNITVI=0dB8085SNRSignaltonoiseratioVI=–3dB7884dBSNRSignal-to-noiseratioVI=–9dB7278dBVI=–40dB3542NOTE5:Thetestconditionisthedigitalequivalentofa1020-Hzinputsignalwithan8-kHzconversionrate.
Thetestismeasuredatoutputofapplicationschematiclow-passfilter.
Thetestisconductedin16-bitmode.
4.
3.
6.
2DACSignal-to-Distortionwhenloadis600(seeNote5)PARAMETERTESTCONDITIONSMINTYPMAXUNITVI=0dB7077THDSignaltototalharmonicdistortionVI=–3dB7885dBTHDSignal-to-totalharmonicdistortionVI=–9dB7885dBVI=–40dB6266NOTE5:Thetestconditionisthedigitalequivalentofa1020-Hzinputsignalwithan8-kHzconversionrate.
Thetestismeasuredatoutputofapplicationschematiclow-passfilter.
Thetestisconductedin16-bitmode.
4–44.
3.
6.
3DACSignal-to-Distortion+NoiseWhenLoadis600(seeNote5)PARAMETERTESTCONDITIONSMINTYPMAXUNITVI=0dB7077THD+NSignaltototalharmonicdistortion+noiseVI=–3dB7378dBTHD+NSignal-to-totalharmonicdistortion+noiseVI=–9dB7078dBVI=–40dB3542NOTE5:Thetestconditionisthedigitalequivalentofa1020-Hzinputsignalwithan8-kHzconversionrate.
Thetestismeasuredatoutputofapplicationschematiclow-passfilter.
Thetestisconductedin16-bitmode.
4.
3.
7DACChannelCharacteristicsPARAMETERTESTCONDITIONSMINTYPMAXUNITDynamicrangeVI=0dBat1020Hz82dBInterchannelisolation100dBEGGainerror,0dBVO=0dBat1020Hz0.
5dBIdlechannelnarrowbandnoise0kHzto4kHz,SeeNote62570VrmsVOOOutputoffsetvoltageatOUT(differential)DIN=allzeros30mVVAnalogoutputvoltage5VDifferentialwithrespecttocommonmode–44VVOAnalogoutputvoltage3.
3VDifferentialwithresecttocommonmodeandfull-scaledigitalinput–2.
52.
5VChanneldelay18/fsNOTE6:Theconversionrateis8kHz.
4.
3.
8Op-AmpInterface(A1,A3,A4)PARAMETERTESTCONDITIONSMINTYPMAXUNITAVGain100Inputvoltagerange0.
5AVDD–0.
5VInputoffsetvoltage10mVInputoffsetcurrent0mAOutputpower15mWSNRSignal-to-noiseratioInputfrequency=1020Hz90dBTHD+NSignal-to-totalharmonicdistortion+noiseInputfrequency=1020Hz90dBUnity-gainbandwidthOpenloop10MHzNoiseoutputvoltage30Vrms4.
3.
9Power-SupplyRejection(seeNote7)PARAMETERTESTCONDITIONSMINTYPMAXUNITAVDDSupply-voltagerejectionratio,analogsupplyfj=0tofs/275dBDVDDSupplyvoltagerejectionratioDACchannelfj=0to30kHz95dBDVDDSupply-voltagerejectionratioADCchannelfj=0to30kHz86dBNOTE7:PowersupplyrejectionmeasurementsaremadewithboththeADCandtheDACchannelsidleanda200-mVpeak-to-peaksignalappliedtotheappropriatesupply.
4–54.
3.
10PowerSupply4.
3.
10.
1Low-PowerMode(setcontrolregisterbitD7to1)PARAMETERTESTCONDITIONSMINTYPMAXUNITPDPowerdissipationAllsectionson,VDD=3.
3V39.
3mWI(analog)SupplycurrentAllsectionson,AVDD=3.
3V9.
7mAIDD(analog)SupplycurrentAllsectionson,AVDD=5V11.
2mAI(digital)SupplycurrentAllsectionson,AVDD=3.
3V2.
3mAIDD(digital)SupplycurrentAllsectionson,AVDD=5V4.
9mA4.
3.
10.
2NormalOperationPARAMETERTESTCONDITIONSMINTYPMAXUNITPDPowerdissipationAllsectionson,VDD=3.
3V48.
5mWAllsectionson,AVDD=3.
3V13.
6mAI(analog)SupplycurrentAllsectionson,AVDD=5V14.
8mAIDD(analog)SupplycurrentPowerdown,AVDD=3.
3V3APowerdown,AVDD=5V11AAllsectionson,AVDD=3.
3V1.
1mAIDD(digital)SupplycurrentAllsectionson,AVDD=5V2.
3mAIDD(digital)SupplycurrentPowerdown,AVDD=3.
3V0.
15mAPowerdown,AVDD=5V0.
6mA4.
4TimingRequirements(seeParameterMeasurementInformation)4.
4.
1MasterModeTimingRequirementsPARAMETERSTESTCONDITIONSMINTYPMAXUNITtd(1)Delaytime,SCLK↑toFS↓5nstd(2)Delaytime,SCLK↑toDOUT15nstsuSetuptime,DIN,beforeSCLKlow5nsthHoldtime,DIN,afterSCLKhigh1/2T+5nstenEnabletime,FS↓toDOUT1/2T+5nstdisDisabletime,FS↑toDOUTHi-ZCL=20pF5nstd(3)Delaytime,MCLK↓toSCLK↑L10nstd(CH-FL)Delaytime,SCLKhightoFS/FSDhigh(seeFigure5-1)5nstd(CH-FH)Delaytime,SCLKhightoFS/FSDhigh5nstw(H)Pulseduration,MCLKhigh12.
5nstw(L)Pulseduration,MCLKlow12.
5ns4–65–15ParameterMeasurementInformationSCLKFC/FS/FSDtd(CH–FL)0.
8V2.
4Vtd(CH–FH)Figure5–1.
FC,FS,andFSDTimingMCLKSCLKFSDOUTDINtd(3)td(1)tw(L)tw(H)tenthtsuD15D15D14D14td(2)tdlsFigure5–2.
SerialCommunicationTiming5–2–150–120–90–60–30005001000150020002500300035004000AMPLITUDEvsFREQUENCYf–Frequency–Hzfs=8kHzInput=–3dBAmplitude–dBFigure5–3.
FFT–ADCChannel–150–120–90–60–300010002000300040005000600070008000AMPLITUDEvsFREQUENCYf–Frequency–Hzfs=16kHzInput=–3dBAmplitude–dBFigure5–4.
FFT–ADCChannel5–3–150–120–90–60–30005001000150020002500300035004000AMPLITUDEvsFREQUENCYf–Frequency–Hzfs=8kHzInput=–3dBAmplitude–dBFigure5–5.
FFT–DACChannel–150–120–90–60–300010002000300040005000600070008000AMPLITUDEvsFREQUENCYf–Frequency–Hzfs=16kHzInput=–3dBAmplitude–dBFigure5–6.
FFT–DACChannel5–4–150–120–90–60–30005001000150020002500300035004000AMPLITUDEvsFREQUENCYf–Frequency–Hzfs=8kHzInput=–1dBAmplitude–dBFigure5–7.
FFT–ADCChannel–150–120–90–60–300010002000300040005000600070008000AMPLITUDEvsFREQUENCYf–Frequency–Hzfs=16kHzInput=–1dBAmplitude–dBFigure5–8.
FFT–ADCChannel5–5–150–120–90–60–30005001000150020002500300035004000AMPLITUDEvsFREQUENCYf–Frequency–Hzfs=8kHzInput=–0dBAmplitude–dBFigure5–9.
FFT–DACChannel–150–120–90–60–300010002000300040005000600070008000AMPLITUDEvsFREQUENCYf–Frequency–Hzfs=16kHzInput=–0dBAmplitude–dBFigure5–10.
FFT–DACChannel5–66–16MechanicalInformationPFB(S-PQFP-G48)PLASTICQUADFLATPACK4073176/B10/96GagePlane0,13NOM0,250,450,75SeatingPlane0,05MIN0,170,2724251312SQ36377,206,804815,50TYPSQ8,809,201,050,951,20MAX0,080,50M0,080°–ā7°NOTES:A.
Alllineardimensionsareinmillimeters.
B.
Thisdrawingissubjecttochangewithoutnotice.
C.
FallswithinJEDECMS-0266–2GQE(S-PBGA-N80)PLASTICBALLGRIDARRAY98765JHGFED321CBA44,00TYPSeatingPlane5,104,90SQ0,620,680,250,351,00MAX0,500,500,08M0,054200461/C10/000,110,21NOTES:A.
Alllineardimensionsareinmillimeters.
B.
Thisdrawingissubjecttochangewithoutnotice.
C.
MicroStarJuniorBGAconfigurationD.
FallswithinJEDECMO-225MicroStarJuniorisatrademarkofTexasInstruments.
A–1AppendixARegisterSetBitsD15throughD13representthedeviceaddressinthecascadesetbytheautomaticcascadedetectiondescribedinSection2.
1.
13.
Incascading,themasteristhedevicedirectlyconnectedtotheDSP.
Forexample,iftherearefourdevicesinthecascade,asshowninrow4ofTableA-1andinSection2.
7.
5,thedeviceaddressD15-D13ofthemasterwillhaveabinaryvalueof011.
Theotherthreeslavesaddressesare010,001,and000,correspondingtotheirpositionsinthecascade.
Thedeviceaddressforastand-alonedeviceisalways000.
BitsD11throughD8comprisetheaddressoftheregisterthatiswrittenwithdatacarriedinD7throughD0.
D12determinesareadorwritecycletotheaddressedregister;alowselectsawritecycle.
Thefollowingtableshowstheregistermap.
REGISTERMAPD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0DeviceAddressRWRegisterAddressXControlRegisterContentTableA–1.
DeviceAddressD15D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14DeviceAddressR/WRegisterAdressXRegisterContentDevice0REGISTERMAP000000000000000000000000Device1001001001001001001001Device2010010010010010010Device3011011011011011Device4100100100100Device5101101101Device6110110Device711187654312DEVICEADDRESS(D15–D13)#DevicesinCascadeTableA–2.
RegisterAddressREGISTERNO.
D11D10D9REGISTERNAME0000Nooperation1001Control12010Control23011Control34100Control4A–2A.
1ControlRegister1TableA–3.
RegisterMapD7D6D5D4D3D2D1D0DESCRIPTIONovfDecimatorFIRoverflowflag–1EnableHYBRIDreceiver/MICamp(A1)–0DisableHYBRID/MICamp(A1)––1Bypassantialiasingfilter––0Enableantialiasingfilter–––1––––SelectAUXPandAUXMforADC–––0––––SelectINPandINMforADC––––1–––Softwarereset––––0–––Default1––Bypassdecimation/interpolationFIRfilter0–NormaloperationwithFIRfilter1–EnableHYBRIDtransmitter/MICamps(A3,A4)0–DisableHYBRIDtransmitter/MICamps(A3,A4)116-bitdataformatforDAC015-bitdata+LSBformatforDACDefaultvalue:00000000NOTE:Asoftwareresetisaone-shotoperationandthisbitisclearedto0afterreset.
Itisnotnecessarytowritea0toendthemasterresetoperation.
EnablingtheD6bitautomaticallyselectsAUXchannelfortheADCinput.
A.
2ControlRegister2TableA–4.
ControlRegister2D7D6D5D4D3D2D1D0DIVIDEVALUE1Low-poweroperationmode0Normaloperationmode–1S–Dmodulatorstops–0S–Dmodulatorruns––RReserved–––11111FrequencyDividerN=31–––00001FrequencyDividerN=1–––00000FrequencyDividerN=32Defaultvalue:00000000NOTE:TheserialportinterfacealwaysgluelesslyworkswiththeDSP.
Thefollowingmodeswillnotproduce50%dutycycleSCLK:1.
Ifthenumberofdevicesincascade>4andNisanoddnumber(i.
e.
,N=1,3,5,.
.
.
)2.
Ifthenumberofdevicesincascade≤4,FIRisbypassed,andN≠4,8,12,16,20,24,28,32A–3A.
3ControlRegister3TableA–5.
ControlRegister3D7D6D5D4D3D2D1D0DESCRIPTION00Default01Analogloopbackenabled10Digitalloopbackenabled11Event-monitormodeenabled(writecycleonly)––1Continuousdata-transfermode(masteronly)––0Default–––1––––FLAGoutput=D3–––0––––FLAGoutput=secondarycommunicationflag–––F–––FLAGvalue00–Default01–DisableADCchannel10–DisableDACchannel11–Softwarepower-downmode116-bitdataformatforADC0Not16-bitdataformatforADCDefaultvalue:00000000A–4A.
4ControlRegister4TableA–6.
ControlRegister4D7D6D5D4D3D2D1D0DESCRIPTION1111––––ADCinputPGAgain=MUTE1110––––ADCinputPGAgain=24dB1101––––ADCinputPGAgain=18dB1100––––ADCinputPGAgain=12dB1011––––ADCinputPGAgain=9dB1010––––ADCinputPGAgain=6dB1001––––ADCinputPGAgain=3dB1000––––ADCinputPGAgain=–3dB0111––––ADCinputPGAgain=–6dB0110––––ADCinputPGAgain=–9dB0101––––ADCinputPGAgain=–12dB0100––––ADCinputPGAgain=–18dB0011––––ADCinputPGAgain=–24dB0010––––ADCinputPGAgain=–30dB0001––––ADCinputPGAgain=–36dB0000––––ADCinputPGAgain=0dB––––1111DACoutputPGAgain=MUTE––––1110DACoutputPGAgain=24dB––––1101DACoutputPGAgain=18dB––––1100DACoutputPGAgain=12dB––––1011DACoutputPGAgain=9dB––––1010DACoutputPGAgain=6dB––––1001DACoutputPGAgain=3dB––––1000DACoutputPGAgain=–3dB––––0111DACoutputPGAgain=–6dB––––0110DACoutputPGAgain=–9dB––––0101DACoutputPGAgain=–12dB––––0100DACoutputPGAgain=–18dB––––0011DACoutputPGAgain=–24dB––––0010DACoutputPGAgain=–30dB––––0001DACoutputPGAgain=–36dB––––0000DACoutputPGAgain=0dBDefaultvalue:00000000A–5Sigma-DeltaADCPGATLV320AIC10Anti-AliasingFilterAURXCPAURXFPAURXMVMIDDTXOPDTXIMDTXIPDTXOMSigma-DeltaDACPGALowPassFilterOUTPOUTMVrefFigureA–1.
DifferentialConfigurationforHybridConnectionA–6Sigma-DeltaADCPGATLV320AIC10Anti-AliasingFilterAURXCPAURXFPAURXMVrefVMIDDTXOPDTXIMDTXIPDTXOMSigma-DeltaDACPGALowPassFilterOUTPOUTMFigureA–2.
Single-EndedConfigurationofHybridConnectionPACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesTLV320AIC10CPFBACTIVETQFPPFB48250RoHS&GreenNIPDAULevel-2-260C-1YEAR0to70320AIC10CTLV320AIC10IPFBACTIVETQFPPFB48250RoHS&GreenNIPDAULevel-2-260C-1YEAR-40to85320AIC10ITLV320AIC10IPFBG4ACTIVETQFPPFB48250RoHS&GreenNIPDAULevel-2-260C-1YEAR-40to85320AIC10I(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
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