columnios5

IS42VM16100G1Rev.
A|Mar.
2011www.
issi.
comDescriptionTheseIS42VM16100Gisalowpower16,777,216bitsCMOSSynchronousDRAMorganizedas2banksof524,288wordsx16bits.
Theseproductsareofferingfullysynchronousoperationandarereferencedtoapositiveedgeoftheclock.
Allinputsandoutputsaresynchronizedwiththerisingedgeoftheclockinput.
Thedatapathsareinternallypipelinedtoachievehighbandwidth.
AllinputandoutputvoltagelevelsarecompatiblewithLVCMOS.
JEDECstandard1.
8Vpowersupply.
Autorefreshandselfrefresh.
AllpinsarecompatiblewithLVCMOSinterface.
4Krefreshcycle/64ms.
ProgrammableBurstLengthandBurstType.
-1,2,4,8orFullPageforSequentialBurst.
-4or8forInterleaveBurst.
ProgrammableCASLatency:2,3clocks.
ProgrammableDriverStrengthControl-FullStrengthor1/2,1/4ofFullStrengthDeepPowerDownMode.
Allinputsandoutputsreferencedtothepositiveedgeofthesystemclock.
DatamaskfunctionbyDQM.
Internaldualbanksoperation.
BurstReadSingleWriteoperation.
SpecialFunctionSupport.
-PASR(PartialArraySelfRefresh)-AutoTCSR(TemperatureCompensatedSelfRefresh)Automaticprecharge,includesCONCURRENTAutoPrechargeModeandcontrolledPrecharge.
Features512Kx16Bitsx2BanksLowPowerSynchronousDRAMCopyright2010IntegratedSiliconSolution,Inc.
Allrightsreserved.
ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithoutnotice.
ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.
Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.
IntegratedSiliconSolution,Inc.
doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.
ProductsarenotauthorizedforuseinsuchapplicationsunlessIntegratedSiliconSolution,Inc.
receiveswrittenassurancetoitssatisfaction,that:a.
)theriskofinjuryordamagehasbeenminimized;b.
)theuserassumeallsuchrisks;andc.
)potentialliabilityofIntegratedSiliconSolution,Incisadequatelyprotectedunderthecircumstances2IS42VM16100GRev.
A|Mar.
2011www.
issi.
comFigure1:60BallFBGABallAssignmentVSSDQ15DQ0VDDDQ14VSSQVDDQDQ1DQ13VDDQVSSQDQ2DQ12DQ11DQ4DQ3DQ10VSSQVDDQDQ5DQ9VDDQVSSQDQ6DQ8NCNCDQ7NCNCNCNCNCUDQMLDQM/WENCCLK/RAS/CASCKENCNC/CSA11A9NCNCA8A7A0A10A6A5A2A1VSSA4A3VDDABCDEFGHJKLMNPR1234567[TopView]3IS42VM16100GRev.
A|Mar.
2011www.
issi.
comFigure2:50PinTSOPIIPinAssignmentVDDDQ0DQ1VSSQDQ2DQ3VDDQDQ4DQ5VSSQDQ6DQ7VDDQLDQM/WE/CAS/RAS/CSA11/BAA10/APA0A1A2A3VDDVSSDQ15DQ14VSSQDQ13DQ12VDDQDQ11DQ10VSSQDQ9DQ8VDDQN.
CUDQMCLKCKEN.
CA9A8A7A6A5A4VSS504948474645444342414039383736353433323130292827261234567891011121314151617181920212223242550PinTSOPII[TopView]4IS42VM16100GRev.
A|Mar.
2011www.
issi.
comTable2:PinDescriptionsPinPinNameDescriptionsCLKSystemClockThesystemclockinput.
AllotherinputsareregisteredtotheSDRAMontherisingedgeCLK.
CKEClockEnableControlsinternalclocksignalandwhendeactivated,theSDRAMwillbeoneofthestatesamongpowerdown,suspendorselfrefresh.
/CSChipSelectEnableordisableallinputsexceptCLK,CKEandDQM.
A11BankAddressSelectsbanktobeactivatedduringRASactivity.
Selectsbanktoberead/writtenduringCASactivity.
A0~A10AddressRowAddress:RA0~RA10ColumnAddress:CA0~CA7AutoPrecharge:A10/RAS,/CAS,/WERowAddressStrobe,ColumnAddressStrobe,WriteEnableRAS,CASandWEdefinetheoperation.
Referfunctiontruthtablefordetails.
LDQM/UDQMDataInput/OutputMaskControlsoutputbuffersinreadmodeandmasksinputdatainwritemode.
DQ0~DQ15DataInput/OutputDatainput/outputpin.
VDD/VSSPowerSupply/GroundPowersupplyforinternalcircuitsandinputbuffers.
VDDQ/VSSQDataOutputPower/GroundPowersupplyforoutputbuffers.
NCNoConnectionNoconnection.
5IS42VM16100GRev.
A|Mar.
2011www.
issi.
comTCSRPASRFigure3:FunctionalBlockDiagramCONTROLLOGICCOMMANDDECODERCOLUMNADDRESSBUFFER&BURSTCOUNTERCLOCKGENERATORCLKCKEROWADDRESSBUFFER&REFRESHCOUNTER/CS/RAS/CAS/WEMODEREGISTERBANKBROWDECODERBANKAROWDECODERSENSEAMPLIFIERCOLUMNDECODER&LATCHCIRCUITDQDQMADDRESSDATACONTROLCIRCUITLATCHCIRCUITINPUT&OUTPUTBUFFEREXTENDEDMODEREGISTER6IS42VM16100GRev.
A|Mar.
2011www.
issi.
comCKE↓CKEIDLEROWACTIVESELFREFRESHCBRREFRESHPOWERDOWNACTIVEPOWERDOWNREADWRITEREADAWRITEAPRE-CHARGEREADSUSPENDREADASUSPENDWRITESUSPENDWRITEASUSPENDPOWERONMODEREGISTERSETPRECHARGECKE↓CKECKE↓CKECKE↓CKEREADWRITECKE↓CKEREADWRITEPREACTREFMRSAutomaticSequenceManualInputFigure4:SimplifiedStateDiagramEXTENDEDMODEREGISTERSETDEEPPOWERDOWN7IS42VM16100GRev.
A|Mar.
2011www.
issi.
comWBBurstTypeAccesseswithinagivenburstmaybeprogrammedtobeeithersequentialorinterleaved;thisisreferredtoasthebursttypeandisselectedviabitM3.
Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,thebursttypeandthestartingcolumnaddress,asshowninTable3.
Table3:BurstDefinitionM9WriteBurstMode0BurstReadandBurstWrite1BurstReadandSingleWriteM3BurstType0Sequential1InterleaveM6M5M4CASLatency000Reserved001101020113100Reserved101Reserved110Reserved111ReservedM2M1M0BurstLengthM3=0M3=100011001220104401188100ReservedReserved101ReservedReserved110ReservedReserved111FullPageReservedBurstLengthStartingColumnAddressOrderofAccessWithinaBurstSequentialInterleavedA2A1A0200-10-111-01-04000-1-2-30-1-2-3011-2-3-01-0-3-2102-3-0-12-3-0-1113-0-1-23-2-1-080000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-2-3-4-5-6-7-01-0-3-2-5-4-7-60102-3-4-5-6-7-0-12-3-0-1-6-7-4-50113-4-5-6-7-0-1-23-2-1-0-7-6-5-41004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-6-7-0-1-2-3-45-4-7-6-1-0-3-21106-7-0-1-2-3-4-56-7-4-5-2-3-0-11117-0-1-2-3-4-5-67-6-5-4-3-2-1-0FullPagen=A0-7(Location0-256)Cn,Cn+1.
Cn+2,Cn+3,Cn+4……Cn-1,Cn.
.
.
NotSupportedNote:1.
Forfull-pageaccesses:y=2562.
Foraburstlengthoftwo,A1-A7selecttheblock-of-twoburst;A0selectsthestartingcolumnwithintheblock.
3.
Foraburstlengthoffour,A2-A7selecttheblock-of-fourburst;A0-A1selectthestartingcolumnwithintheblock.
4.
Foraburstlengthofeight,A3-A7selecttheblock-of-eightburst;A0-A2selectthestartingcolumnwithintheblock.
5.
Forafull-pageburst,thefullrowisselectedandA0-A7selectthestartingcolumn.
6.
Wheneveraboundaryoftheblockisreachedwithinagivensequenceabove,thefollowingaccesswrapswithintheblock.
7.
Foraburstlengthofone,A0-A7selecttheuniquecolumntobeaccessed,andmoderegisterbitM3isignored.
0CASLatencyBTBurstLengthAddressBus01234561098711A0A1A2A3A4A5A6A7A8A9A10A11ModeRegister(Mx)000Figure5:ModeRegisterDefinitionNote:M11(A11)mustbesetto"0"toselectModeRegister(vs.
theExtendedModeRegister)8IS42VM16100GRev.
A|Mar.
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com1PASRFigure6:ExtendedModeRegisterAddressBusExtendedModeRegister(Ex)01234561098711A0A1A2A3A4A5A6A7A8A9A10A11E2E1E0SelfRefreshCoverage000AllBanks001OneBank(A11=0)010Reserved011Reserved100Reserved101HalfofOneBank(A11=0,RowAddressMSB=0)110QuarterofOneBank(A11=0,RowAddress2MSB=0)111ReservedNote:E11(A11)mustbesetto"1"toselectExtendModeRegister(vs.
thebaseModeRegister)E6E5DriverStrength00FullStrength011/2Strength101/4Strength11Reserved0000DSTCSRE4E3MaximumCaseTemp.
0085°0170°1045°11Auto9IS42VM16100GRev.
A|Mar.
2011www.
issi.
comIngeneral,this16MbSDRAM(512Kx16Bitsx2banks)isadual-bankDRAMthatoperatesat1.
8Vandincludesasynchronousinterface(allsignalsareregisteredonthepositiveedgeoftheclocksignal,CLK).
Eachofthe8,388,608-bitbanksisorganizedas2,048rowsby256columnsby16-bitsReadandwriteaccessestotheSDRAMareburstoriented;accessesstartataselectedlocationandcontinueforaprogrammednumberoflocationsinaprogrammedsequence.
AccessesbeginwiththeregistrationofanACTIVEcommand,whichisthenfollowedbyaREADorWRITEcommand.
TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandrowtobeaccessed(A11selectthebank,A0-A10selecttherow).
Theaddressbits(A11selectthebank,A0-A7selectthecolumn)registeredcoincidentwiththeREADorWRITEcommandareusedtoselectthestartingcolumnlocationfortheburstaccess.
Priortonormaloperation,theSDRAMmustbeinitialized.
Thefollowingsectionsprovidedetailedinformationcoveringdeviceinitialization,registerdefinition,commanddescriptionsanddeviceoperation.
PowerupandInitializationSDRAMsmustbepoweredupandinitializedinapredefinedmanner.
Operationalproceduresotherthanthosespecifiedmayresultinundefinedoperation.
OncepowerisappliedtoVDDandVDDQ(simultaneously)andtheclockisstable(stableclockisdefinedasasignalcyclingwithintimingconstraintsspecifiedfortheclockpin),theSDRAMrequiresa100sdelaypriortoissuinganycommandotherthanaCOMMANDINHIBITorNOP.
CKEmustbeheldhighduringtheentireinitializationperioduntiltheRECHARGEcommandhasbeenissued.
Startingatsomepointduringthis100speriodandcontinuingatleastthroughtheendofthisperiod,COMMANDINHIBITorNOPcommandsshouldbeapplied.
Oncethe100sdelayhasbeensatisfiedwithatleastoneCOMMANDINHIBITorNOPcommandhavingbeenapplied,aPRECHARGEcommandshouldbeapplied.
Allbanksmustthenbeprecharged,therebyplacingthedeviceintheallbanksidlestate.
Onceintheidlestate,twoAUTOREFRESHcyclesmustbeperformed.
AftertheAUTOREFRESHcyclesarecomplete,theSDRAMisreadyformoderegisterprogramming.
Becausethemoderegisterwillpowerupinanunknownstate,itshouldbeloadedpriortoapplyinganyoperationalcommand.
Andaextendedmoderegistersetcommandwillbeissuedtoprogramspecificmodeofselfrefreshoperation(PASR).
Thefollowingthesecycles,theLowPowerSDRAMisreadyfornormaloperation.
RegisterDefinitionModeRegisterThemoderegisterisusedtodefinethespecificmodeofoperationoftheSDRAM.
Thisdefinitionincludestheselectionofaburstlength,abursttype,aCASlatency,anoperatingmodeandawriteburstmode.
ThemoderegisterisprogrammedviatheLOADMODEREGISTERcommandandwillretainthestoredinformationuntilitisprogrammedagainorthedevicelosespower.
ModeregisterbitsM0-M2specifytheburstlength,M3specifiesthetypeofburst(sequentialorinterleaved),M4-M6specifytheCASlatency,M7andM8specifytheoperatingmode,M9specifiesthewriteburstmode,andM10shouldbesettozero.
M11shouldbesettozerotopreventextendedmoderegister.
Themoderegistermustbeloadedwhenallbanksareidle,andthecontrollermustwaitthespecifiedtimebeforeinitiatingthesubsequentoperation.
Violatingeitheroftheserequirementswillresultinunspecifiedoperation.
FunctionalDescriptionExtendedModeRegisterTheExtendedModeRegistercontrolsthefunctionsbeyondthosecontrolledbytheModeRegister.
TheseadditionalfunctionsarespecialfeaturesoftheBATRAMdevice.
TheyincludeTemperatureCompensatedSelfRefresh(TCSR)Control,andPartialArraySelfRefresh(PASR)andDriverStrength(DS).
TheExtendedModeRegisterisprogrammedviatheModeRegisterSetcommand(A11=1)andretainsthestoredinformationuntilitisprogrammedagainorthedevicelosespower.
TheExtendedModeRegistermustbeprogrammedwithM7throughM10setto"0".
TheExtendedModeRegistermustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimebeforeinitiatinganysubsequentoperation.
Violatingeitheroftheserequirementsresultsinunspecifiedoperation.
10IS42VM16100GRev.
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2011www.
issi.
comBurstLengthReadandwriteaccessestotheSDRAMareburstoriented,withtheburstlengthbeingprogrammable,asshowninFigure1.
TheburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcanbeaccessedforagivenREADorWRITEcommand.
Burstlengthsof1,2,4or8locationsareavailableforboththesequentialandtheinterleavedbursttypes,andafull-pageburstisavailableforthesequentialtype.
Thefull-pageburstisusedinconjunctionwiththeBURSTTERMINATEcommandtogeneratearbitraryburstlengths.
Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfutureversionsmayresult.
WhenaREADorWRITEcommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.
Allaccessesforthatbursttakeplacewithinthisblock,meaningthattheburstwillwrapwithintheblockifaboundaryisreached.
TheblockisuniquelyselectedbyA1-A7whentheburstlengthissettotwo;byA2-A7whentheburstlengthissettofour;andbyA3-A7whentheburstlengthissettoeight.
Theremaining(leastsignificant)addressbit(s)is(are)usedtoselectthestartinglocationwithintheblock.
Full-pageburstswrapwithinthepageiftheboundaryisreached.
Bank(Row)ActiveTheBankActivecommandisusedtoactivatearowinaspecifiedbankofthedevice.
ThiscommandisinitiatedbyactivatingCS,RASanddeassertingCAS,WEatthepositiveedgeoftheclock.
ThevalueontheA11selectsthebank,andthevalueontheA0-A10selectstherow.
Thisrowremainsactiveforcolumnaccessuntilaprechargecommandisissuedtothatbank.
ReadandwriteoperationscanonlybeinitiatedonthisactivatedbankaftertheminimumtRCDtimeispassedfromtheactivatecommand.
ReadTheREADcommandisusedtoinitiatetheburstreadofdata.
ThiscommandisinitiatedbyactivatingCS,CAS,anddeassertingWE,RASatthepositiveedgeoftheclock.
A11inputselectthebank,A0-A7addressinputsselectthestartingcolumnlocation.
ThevalueoninputA10determineswhetherornotAutoPrechargeisused.
IfAutoPrechargeisselectedtherowbeingaccessedwillbeprechargedattheendoftheREADburst;ifAutoPrechargeisnotselected,therowwillremainactiveforsubsequentaccesses.
ThelengthofburstandtheCASlatencywillbedeterminedbythevaluesprogrammedduringtheMRScommand.
WriteTheWRITEcommandisusedtoinitiatetheburstwriteofdata.
ThiscommandisinitiatedbyactivatingCS,CAS,WEanddeassertingRASatthepositiveedgeoftheclock.
A11inputselectthebank,A0-A7addressinputsselectthestartingcolumnlocation.
ThevalueoninputA10determineswhetherornotAutoPrechargeisused.
IfAutoPrechargeisselectedtherowbeingaccessedwillbeprechargedattheendoftheWRITEburst;ifAutoPrechargeisnotselected,therowwillremainactiveforsubsequentaccesses.
11IS42VM16100GRev.
A|Mar.
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issi.
comCASLatencyTheCASlatencyisthedelay,inclockcycles,betweentheregistrationofaREADcommandandtheavailabilityofthefirstpieceofoutputdata.
Thelatencycanbesettotwoorthreeclocks.
IfaREADcommandisregisteredatclockedgen,andthelatencyismclocks,thedatawillbeavailablebyclockedgen+m.
TheDQswillstartdrivingasaresultoftheclockedgeonecycleearlier(n+m-1),andprovidedthattherelevantaccesstimesaremet,thedatawillbevalidbyclockedgen+m.
Forexample,assumingthattheclockcycletimeissuchthatallrelevantaccesstimesaremet,ifaREADcommandisregisteredatT0andthelatencyisprogrammedtotwoclocks,theDQswillstartdrivingafterT1andthedatawillbevalidbyT2,asshowninFigure7.
Reservedstatesshouldnotbeusedasunknownoperationorincompatibilitywithfutureversionsmayresult.
OperatingModeThenormaloperatingmodeisselectedbysettingM7andM8tozero;theothercombinationsofvaluesforM7andM8arereservedforfutureuseand/ortestmodes.
TheprogrammedburstlengthappliestobothREADandWRITEbursts.
Testmodesandreservedstatesshouldnotbeusedbecauseunknownoperationorincompatibilitywithfutureversionsmayresult.
WriteBurstModeWhenM9=0,theburstlengthprogrammedviaM0-M2appliestobothREADandWRITEbursts;whenM9=1,theprogrammedburstlengthappliestoREADbursts,butwriteaccessesaresingle-location(nonburst)accesses.
CLKCOMMANDDQNOPNOPDoutT0T1T2tLZtOHtACCASLatency=2T3READCLKCOMMANDDQNOPNOPDoutT0T1T2tLZtOHtACCASLatency=3T3NOPT4READDON'TCAREUNDEFINEDFigure7:CASLatency12IS42VM16100GRev.
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comTable4:CommandTruthTableFunctionCKEn-1CKEn/CS/RAS/CAS/WEDQMAddrA10NoteCommandInhinit(NOP)HXHXXXXXNoOperation(NOP)HXLHHHXXModeRegisterSetHXLLLLXOPCODE4ExtendedModeRegisterSetHXLLLLXOPCODE4Active(selectbankandactivaterow)HXLLHHXBank/RowReadHXLHLHL/HBank/ColL5ReadwithAutoprechargeHXLHLHL/HBank/ColH5WriteHXLHLLL/HBank/ColL5WritewithAutoprechargeHXLHLLL/HBank/ColH5PrechargeAllBanksHXLLHLXXHPrechargeSelectedBankHXLLHLXBankLBurstStopHHLHHLXXAutoRefreshHHLLLHXX3SelfRefreshEntryHLLLLHXX3SelfRefreshExitLHHXXXXX2LHHHPrechargePowerDownEntryHLHXXXXXLHHHPrechargeDownExitLHHXXXXXLHHHClockSuspendEntryHLHXXXXXLVVVClockSuspendExitLHXXXDeepPowerDownEntryHLLHHLXX6DeepPowerDownExitLHXXXNote:1.
CKEnisthelogicstateofCKEatclockedgen;CKEn-1wasthestateofCKEatthepreviousclockedge.
H:HighLevel,L:LowLevel,X:Don'tCare,V:Valid2.
ExitingSelfRefreshoccursbyasynchronouslybringingCKEfromlowtohighandwillputthedeviceintheallbanksidlestateoncetXSRismet.
CommandInhibitorNOPcommandsshouldbeissuedonanyclockedgesoccuringduringthetXSRperiod.
AminimumoftwoNOPcommandsmustbeprovidedduringtXSRperiod.
3.
Duringrefreshoperation,internalrefreshcountercontrolsrowaddressing;allinputsandI/Osare"Don'tCare"exceptforCKE.
4.
A0-A10defineOPCODEwrittentothemoderegister,andA11mustbeissued0inthemoderegisterset,and1intheextendedmoderegisterset.
5.
DQM"L"meansthedataWrite/OuputEnableand"H"meanstheWriteinhibit/OutputHigh-Z.
WriteDQMLatencyis0CLKandReadDQMLatencyis2CLK.
6.
StandardSDRAMpartsassignthiscommandsequenceasBurstTerminate.
ForBatRamparts,theBurstTerminatecommandisassignedtotheDeepPowerDownfunction.
13IS42VM16100GRev.
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comTable5:FunctionTruthTableCurrentStateCommandActionNote/CS/RAS/CAS/WEA11A0-A10DescriptionIdleLLLLOPCODEModeRegisterSetSettheModeRegister14LLLHXXAutoorSelfRefreshStartAutoorSelfRefresh5LLHLBAXPrechargeNoOperationLLHHBARowAdd.
BankActivateActivatetheSpecifiedBankandRowLHLLBAColAdd.
/A10Write/WriteAPILLEGAL4LHLHBAColAdd.
/A10Read/ReadAPILLEGAL4LHHHXXNoOperationNoOperation3HXXXXXDeviceDeselectNoOperationorPowerDown3RowActiveLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargePrecharge7LLHHBARowAdd.
BankActivateILLEGAL4LHLLBAColAdd.
/A10Write/WriteAPStartWrite:OptionalAP(A10=H)6LHLHBAColAdd.
/A10Read/ReadAPStartRead:OptionalAP(A10=H)6LHHHXXNoOperationNoOperationHXXXXXDeviceDeselectNoOperationReadLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeTerminationBurst:StartthePrechargeLLHHBARowAdd.
BankActivateILLEGAL4LHLLBAColAdd.
/A10Write/WriteAPTerminationBurst:StartWrite(AP)8,9LHLHBAColAdd.
/A10Read/ReadAPTeriminationBurst:StartRead(AP)8LHHHXXNoOperationContinuetheBurstHXXXXXDeviceDeselectContinuetheBurst14IS42VM16100GRev.
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comTable5:FunctionTruthTableCurrentStateCommandActionNote/CS/RAS/CAS/WEA11A0-A10DescriptionWriteLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeTerminationBurst:StartthePrecharge10LLHHBARowAdd.
BankActivateILLEGAL4LHLLBAColAdd.
/A10Write/WriteAPTerminationBurst:StartWrite(AP)8LHLHBAColAdd.
/A10Read/ReadAPTeriminationBurst:StartREAD(AP)8,9LHHHXXNoOperationContinuetheBurstHXXXXXDeviceDeselectContinuetheBurstReadwithAutoPrechargeLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeILLEGAL4,12LLHHBARowAdd.
BankActivateILLEGAL4,12LHLLBAColAdd.
/A10Write/WriteAPILLEGAL12LHLHBAColAdd.
/A10Read/ReadAPILLEGAL12LHHHXXNoOperationContinuetheBurstHXXXXXDeviceDeselectContinuetheBurstWritewithAutoPrechargeLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeILLEGAL4,12LLHHBARowAdd.
BankActivateILLEGAL4,12LHLLBAColAdd.
/A10Write/WriteAPILLEGAL12LHLHBAColAdd.
/A10Read/ReadAPILLEGAL12LHHHXXNoOperationContinuetheBurstHXXXXXDeviceDeselectContinuetheBurst15IS42VM16100GRev.
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comTable5:FunctionTruthTableCurrentStateCommandActionNote/CS/RAS/CAS/WEA11A0-A10DescriptionPrechargingLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeNoOperation:Bank(s)IdleaftertRPLLHHBARowAdd.
BankActivateILLEGAL4,12LHLLBAColAdd.
/A10Write/WriteAPILLEGAL4,12LHLHBAColAdd.
/A10Read/ReadAPILLEGAL4,12LHHHXXNoOperationNoOperation:Bank(s)IdleaftertRPHXXXXXDeviceDeselectNoOperation:Bank(s)IdleaftertRPRowActivatingLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeILLEGAL4,12LLHHBARowAdd.
BankActivateILLEGAL4,11,12LHLLBAColAdd.
/A10Write/WriteAPILLEGAL4,12LHLHBAColAdd.
/A10Read/ReadAPILLEGAL4,12LHHHXXNoOperationNoOperation:ROwActiveaftertRCDHXXXXXDeviceDeselectNoOperation:ROwActiveaftertRCDWriteRecoveringLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeILLEGAL4,13LLHHBARowAdd.
BankActivateILLEGAL4,12LHLLBAColAdd.
/A10Write/WriteAPStartWrite:OptionalAP(A10=H)LHLHBAColAdd.
/A10Read/ReadAPStartWrite:OptionalAP(A10=H)9LHHHXXNoOperationNoOperation:RowActiveaftertDPLHXXXXXDeviceDeselectNoOperation:RowActiveaftertDPL16IS42VM16100GRev.
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comTable5:FunctionTruthTableCurrentStateCommandActionNote/CS/RAS/CAS/WEA11A0-A10DescriptionWriteRecoveringwithAutoPrechargeLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeILLEGAL4,13LLHHBARowAdd.
BankActivateILLEGAL4,12LHLLBAColAdd.
/A10Write/WriteAPILLEGAL4,12LHLHBAColAdd.
/A10Read/ReadAPILLEGAL4,9,12LHHHXXNoOperationNoOperation:PrechargeaftertDPLHXXXXXDeviceDeselectNoOperation:PrechargeaftertDPLRefreshingLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeILLEGAL13LLHHBARowAdd.
BankActivateILLEGAL13LHLLBAColAdd.
/A10Write/WriteAPILLEGAL13LHLHBAColAdd.
/A10Read/ReadAPILLEGAL13LHHHXXNoOperationNoOperation:IdleaftertRCHXXXXXDeviceDeselectNoOperation:IdleaftertRCModeRegisterAccessingLLLLOPCODEModeRegisterSetILLEGAL13,14LLLHXXAutoorSelfRefreshILLEGAL13LLHLBAXPrechargeILLEGAL13LLHHBARowAdd.
BankActivateILLEGAL13LHLLBAColAdd.
/A10Write/WriteAPILLEGAL13LHLHBAColAdd.
/A10Read/ReadAPILLEGAL13LHHHXXNoOperationNoOperation:Idleafter2ClockCycleHXXXXXDeviceDeselectNoOperation:Idleafter2ClockCycle17IS42VM16100GRev.
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comNote:1.
H:LogicHigh,L:LogicLow,X:Don'tcare,A11:BankAddress,AP:AutoPrecharge.
2.
AllentriesassumethatCKEwasactiveduringtheprecedingclockcycle.
3.
IfbothbanksareidleandCKEisinactive,theninpowerdowncycle4.
Illegaltobankinspecifiedstates.
FunctionmaybelegalinthebankindicatedbyBankAddress,dependingonthestateofthatbank.
5.
IfbothbanksareidleandCKEisinactive,thenSelfRefreshmode.
6.
IllegaliftRCDisnotsatisfied.
7.
IllegaliftRASisnotsatisfied.
8.
Mustsatisfyburstinterruptcondition.
9.
Mustsatisfybuscontention,busturnaround,and/orwriterecoveryrequirements.
10.
Mustmaskprecedingdatawhichdon'tsatisfytDPL.
11.
IllegaliftRRDisnotsatisfied12.
Illegalforsinglebank,butlegalforotherbanksinmulti-bankdevices.
13.
Illegalforallbanks.
14.
ModeRegisterSetandExtendedModeRegisterSetissamecommandtruthtableexceptA11.
18IS42VM16100GRev.
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2011www.
issi.
comTable6:CKETruthTableCurrentStateCKECommandActionNotePrevCycleCurrentCycle/CS/RAS/CAS/WEA11A0-A10SelfRefreshHXXXXXXXINVALID2LHHXXXXXExitSelfRefreshwithDeviceDeselect3LHLHHHXXExitSelfRefreshwithNoOperation3LHLHHLXXILLEGAL3LHLHLXXXILLEGAL3LHLLXXXXILLEGAL3LLXXXXXXMaintainSelfRefreshPowerDownHXXXXXXXINVALID2LHHXXXXXPowerDownModeExit,AllBanksIdle3LHHHXXLHLLXXXXILLEGAL3XLXXXXXLXXLLXXXXXXMaintainPowerDownModeDeepPowerDownHXXXXXXXINVALID2LHXXXXXXDeepPowerDownModeExit6LLXXXXXXMaintainDeepPowerDownModeAllBanksIdleHHHXXXRefertotheIdleStatesectionoftheCurrentStateTruthTable4HHLHXX4HHLLHX4HHLLLHXXAutoRefreshHHLLLLOPCODEModeRegisterSet5HLHXXXRefertotheIdleStatesectionoftheCurrentStateTruthTable4HLLHXX4HLLLHX4HLLLLHXXEntrySelfRefresh5HLLLLLOPCODEModeRegisterSetLXXXXXXXPowerDown5AnyStateotherthanlistedaboveHHXXXXXXRefertoOperationsoftheCurrentStateTruthTableHLXXXXXXBeginClockSuspendnextcycleLHXXXXXXExitClockSuspendnextcycleLLXXXXXXMaintainClockSuspend19IS42VM16100GRev.
A|Mar.
2011www.
issi.
comNote:1.
H:LogicHigh,L:LogicLow,X:Don'tcare2.
ForthegivencurrentstateCKEmustbelowinthepreviouscycle.
3.
WhenCKEhasalowtohightransition,theclockandotherinputsarere-enabledasynchronously.
Whenexitingpowerdownmode,aNOP(orDeviceDeselect)commandisrequiredonthefirstpositiveedgeofclockafterCKEgoeshigh.
4.
Theaddressinputsdependonthecommandthatisissued.
5.
ThePrechargePowerDownmode,theSelfRefreshmode,andtheModeRegisterSetcanonlybeenteredfromtheallbanksidlestate.
6.
WhenCKEhasalowtohightransition,theclockandotherinputsarere-enabledasynchronously.
Whenexitingdeeppowerdownmode,aNOP(orDeviceDeselect)commandisrequiredonthefirstpositiveedgeofclockafterCKEgoeshighandismaintainedforaminimum100usec.
20IS42VM16100GRev.
A|Mar.
2011www.
issi.
comTable7:AbsoluteMaximumRatingParameterSymbolRatingUnitAmbientTemperature(Industrial)TA-40~85°CAmbientTemperature(Commercial)0~70StorageTemperatureTSTG-55~150°CVoltageonAnyPinrelativetoVSSVIN,VOUT-1.
0~2.
6VVoltageonVDDrelativetoVSSVDD,VDDQ-1.
0~2.
6VShortCircuitOutputCurrentIOS50mAPowerDissipationPD1WNote:Stressesgreaterthanthoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.
Thisisastressratingonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.
Table8:Capacitance(TA=25°C,f=1MHz,VDD=1.
8V)ParameterPinSymbolMinMaxUnitInputCapacitanceCLKCI124pFA0~A11,CKE,/CS,/RAS,/CAS,/WE,L(U)DQMCI224pFDataInput/OutputCapacitanceDQ0~DQ15CIO35pFTable9:DCOperatingCondition(VoltagereferencedtoVSS=0V,TA=-40~85°C)ParameterSymbolMinTypMaxUnitNotePowerSupplyVoltageVDD1.
71.
81.
95VVDDQ1.
71.
81.
95V1InputHighVoltageVIH0.
8xVDDQ-VDDQ+0.
3V2InputLowVoltageVIL-0.
300.
3V3OutputHighVoltageVOH0.
9xVDDQ--VIOH=-0.
1mAOutputLowVoltageVOL--0.
2VIOL=+0.
1mAInputLeakageCurrentILI-1-1uA4OutputLeakageCurrentILO-1.
51.
5uA5Note:1.
VDDQmustnotexceedthelevelofVDD2.
VIH(max)=VDDQ+1.
5VAC.
Theovershootvoltagedurationis≤3ns.
3.
VIL(min)=-1.
0VAC.
Theovershootvoltagedurationis≤3ns.
4.
Anyinput0V≤VIN≤VDDQ.
InputleakagecurrentsincludeHi-Zoutputleakageforallbi-directionalbufferswithtri-stateoutputs.
5.
DOUTisdisabled,0V≤VOUT≤VDDQ.
21IS42VM16100GRev.
A|Mar.
2011www.
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comTable10:ACOperatingCondition(TA=-40~85°C,VDD=1.
8V±0.
15V,VSS=0V)ParameterSymbolTypUnitACInputHigh/LowLevelVoltageVIH/VIL0.
9xVDDQ/0.
2VInputTimingMeasurementReferenceLevelVoltageVTRIP0.
5xVDDQVInputRise/FallTimetR/tF1/1nsOutputTimingMeasurementReferenceLevelVoltageVOUTREF0.
5xVDDQVOutputLoadCapacitanceforAccessTimeMeasurementCL30pFOutput500500VDDQ30pFOutput30pF50VTT=0.
5xVDDQZ0=50DCOutputLoadCircuitACOutputLoadCircuit22IS42VM16100GRev.
A|Mar.
2011www.
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comNote:1.
Measuredwithoutputsopen.
2.
Refreshperiodis64ms.
Table11:DCCharacteristic(DCoperatingconditionsunlessotherwisenoted)ParameterSymTestConditionSpeedUnitNote-60-75-10OperatingCurrentICC1BurstLength=1,OneBankActive,tRC≥tRC(min)IOL=0mA40mA1PrechargeStandbyCurrentinPowerDownModeICC2PCKE≤VIL(max),tCK=10ns60uAICC2PSCKE&CLK≤VIL(max),tCK=∞60PrechargeStandbyCurrentinNonPowerDownModeICC2NCKE≥VIH(min),/CS≥VIH(min),tCK=10nsInputsignalsarechangedonetimeduring2clks.
6mAICC2NSCKE≥VIH(min),CLK≤VIL(max),tCK=∞Inputsignalsarestable.
2ActiveStandbyCurrentinPowerDownModeICC3PCKE≤VIL(max),tCK=10ns1.
0mAICC3PSCKE&CLK≤VIL(max),tCK=∞0.
5ActiveStandbyCurrentinNonPowerDownModeICC3NCKE≥VIH(min),/CS≥VIH(min),tCK=10nsInputsignalsarechangedonetimeduring2clks.
12mAICC3NSCKE≥VIH(min),CLK≤VIL(max),tCK=∞Inputsignalsarestable.
8BurstModeOperatingCurrentICC4tCK>tCK(min),IOL=0mA,PageBurstAllBanksActivated,tCCD=1clk554535mA1AutoRefreshCurrent(4KCycle)ICC5tRC≥tRFC(min),AllBanksActive30mA2SelfRefreshCurrentPASRTCSRICC6CKE≤0.
2VuA2Banks45~85°C100-40~45°C851Bank45~85°C90-40~45°C75DeepPowerDownModeCurrentICC710uA23IS42VM16100GRev.
A|Mar.
2011www.
issi.
comTable12:ACCharacteristic(ACoperationconditionsunlessotherwisenoted)ParameterSym-60-75-10UnitNoteMinMaxMinMaxMinMaxCLKCycleTimeCL=3tCK36.
010007.
51000101000ns1CL=2tCK2101010AccesstimefromCLK(pos.
edge)CL=3tAC35.
5682CL=2tAC2888CLKHigh-LevelWidthtCH2.
52.
52.
53CLKLow-LevelWidthtCL2.
52.
52.
53CKESetupTimetCKS1.
52.
02.
0CKEHoldTimetCKH1.
01.
01.
0/CS,/RAS,/CAS,/WE,DQMSetupTimetCMS1.
52.
02.
0/CS,/RAS,/CAS,/WE,DQMHoldTimetCMH1.
01.
01.
0AddressSetupTimetAS1.
52.
02.
0AddressHoldTimetAH1.
01.
01.
0Data-InSetupTimetDS1.
52.
02.
0Data-InHoldTimetDH1.
01.
01.
0Data-OutHigh-ImpedanceTimefromCLK(pos.
edge)CL=3tHZ35.
5684CL=2tHZ2888Data-OutLow-ImpedanceTimetLZ1.
01.
01.
0Data-OutHoldTime(load)tOH2.
52.
52.
5Data-OutHoldTime(noload)tOHN1.
81.
81.
8ACTIVEtoPRECHARGEcommandtRAS42100K45100K40100KPRECHARGEcommandperiodtRP1822.
520ACTIVEbankatoACTIVEbankacommandtRC6067.
5645ACTIVEbankatoACTIVEbankbcommandtRRD121520ACTIVEtoREADorWRITEdelaytRCD1822.
530READ/WRITEcommandtoREAD/WRITEcommandtCCD111CLK6WRITEcommandtoinputdatadelaytDWD0006Data-intoPRECHARGEcommandtDPL121520ns7Data-intoACTIVEcommandtDAL3037.
5407DQMtodatahigh-impedanceduringREADstDQZ222CLK6DQMtodatamaskduringWRITEstDQM0006LOADMODEREGISTERcommandtoACTIVEorREFRESHcommandtMRD2228Data-outtohigh-impedancefromPRECHARGEcommandCL=3tROH33336CL=2tROH2222Lastdata-intoburstSTOPcommandtBDL1116Lastdata-intonewREAD/WRITEcommandtCDL1116CKEtoclockdisableorpower-downentrymodetCKED111CLK9CKEtoclockenableorpower-downexitsetupmodetPED1119Refreshperiod(4,096refreshcycles)tREF646464msAUTOREFRESHperiodtRFC808080ns5ExitSELFREFRESHtoACTIVEcommandtXSR8080805TransitiontimetT0.
51.
20.
51.
20.
51.
224IS42VM16100GRev.
A|Mar.
2011www.
issi.
comNote:1.
Theclockfrequencymustremainconstant(stableclockisdefinedasasignalcyclingwithintimingconstraintsspecifiedfortheclockpin)duringaccessorprechargestates(READ,WRITE,includingtDPL,andPRECHARGEcommands).
CKEmaybeusedtoreducethedatarate.
2.
tACatCL=3withnoloadis5.
5nsandisguaranteedbydesign.
Accesstimetobemeasuredwithinputsignalsof1V/nsedgerate,from0.
8Vto0.
2V.
IftR>1ns,then(tR/2-0.
5)nsshouldbeaddedtotheparameter.
3.
ACcharacteristicsassumetT=1ns.
IftR&tF>1ns,then[(tR+tF)/2-1]nsshouldbeaddedtotheparameter.
4.
tHZdefinesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVOHorVOL.
ThelastvaliddataelementwillmeettOHbeforegoingHigh-Z.
5.
Parameterguaranteedbydesign.
6.
RequiredclocksarespecifiedbyJEDECfunctionalityandarenotdependentonanytimingparameter.
7.
TimingactuallyspecifiedbytDPLplustRP;clock(s)specifiedasareferenceonlyatminimumcyclerate8.
JEDECandPC100specifythreeclocks.
9.
TimingactuallyspecifiedbytCKs;clock(s)specifiedasareferenceonlyatminimumcyclerate.
25IS42VM16100GRev.
A|Mar.
2011www.
issi.
comTemperatureCompensatedSelfRefreshTemperatureCompensatedSelfRefreshallowsthecontrollertoprogramtheRefreshintervalduringSELFREFRESHmode,accordingtothecasetemperatureoftheLowPowerSDRAMdevice.
ThisallowsgreatpowersavingsduringSELFREFRESHduringmostoperatingtemperatureranges.
OnlyduringextremetemperatureswouldthecontrollerhavetoselectaTCSRlevelthatwillguaranteedataduringSELFREFRESH.
EverycellintheDRAMrequiresrefreshingduetothecapacitorlosingitschargeovertime.
Therefreshrateisdependentontemperature.
Athighertemperaturesacapacitorloseschargequickerthanatlowertemperatures,requiringthecellstoberefreshedmoreoften.
Historically,duringSelfRefresh,therefreshratehasbeensettoaccommodatetheworstcase,orhighesttemperaturerangeexpected.
Thus,duringambienttemperatures,thepowerconsumedduringrefreshwasunnecessarilyhigh,becausetherefreshratewassettoaccommodatethehighertemperatures.
SettingM4andM3,allowtheDRAMtoaccommodatemorespecifictemperatureregionsduringSELFREFRESH.
Therearefourtemperaturesettings,whichwillvarytheSELFREFRESHcurrentaccordingtotheselectedtemperature.
ThisselectablerefreshratewillsavepowerwhentheDRAMisoperatingatnormaltemperatures.
PartialArraySelfRefreshForfurtherpowersavingsduringSELFREFRESH,thePASRfeatureallowsthecontrollertoselecttheamountofmemorythatwillberefreshedduringSELFREFRESH.
TherefreshoptionsareTwoBank;alltwobanks,OneBank;bank0.
WRITEandREADcommandscanstilloccurduringstandardoperation,butonlytheselectedbankswillberefreshedduringSELFREFRESH.
Datainbanksthataredisabledwillbelost.
DeepPowerDownDeepPowerDownisanoperatingmodetoachievemaximumpowerreductionbyeliminatingthepowerofthewholememoryarrayofthedevices.
DatawillnotberetainedoncethedeviceentersDeepPowerDownMode.
Thismodeisenteredbyhavingallbanksidlethen/CSand/WEheldlowwith/RASand/CASheldhighattherisingedgeoftheclock,whileCKEislow.
ThismodeisexitedbyassertingCKEhigh.
SpecialOperationforLowPowerConsumption26IS42VM16100GRev.
A|Mar.
2011www.
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comFigure7:DeepPowerDownModeEntryFigure8:DeepPowerDownModeExit/CS/RAS/CAS/WECLKCKE100stRPtRFCDeepPowerDownExitAllBanksPrechargeAutoRefreshModeRegisterSetExtendedModeRegisterSetNewCommandAutoRefreshDON'TCARECLKCKEPrechargeifneededDeepPowerDownEntrytRP/CS/RAS/CAS/WEDON'TCARE27IS42VM16100GRev.
A|Mar.
2011www.
issi.
comOrderingInformation–VDD=1.
8VIndustrialRange:(-40oCto+85oC)ConfigurationFrequency(MHz)Speed(ns)OrderPartNo.
Description1Mx161666IS42VM16100G-6TLI50-pinTSOP-II,Lead-free1337.
5IS42VM16100G-75TLI50-pinTSOP-II,Lead-free1666IS42VM16100G-6BLI60-ballBGA,Lead-free1337.
5IS42VM16100G-75BLI60-ballBGA,Lead-freeNote:PleasecontactISSIforavailabilityofTSOPoption.
28IS42VM16100GRev.
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comMouserElectronicsAuthorizedDistributorClicktoViewPricing,Inventory,Delivery&LifecycleInformation:ISSI:IS42VM16100G-75TLI-TRIS42VM16100G-75BLI-TRIS42VM16100G-75TLIIS42VM16100G-75BLI