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RML40xEDKProcessorReferenceDesignUserGuideforEDK8.
1UG082(v5.
0)June30,2006ML40xEDKProcessorReferenceDesignwww.
xilinx.
comUG082(v5.
0)June30,2006XilinxisdisclosingthisDocumentandIntellectualProperty(hereinafter"theDesign")toyouforuseinthedevelopmentofdesignstooperateon,orinterfacewithXilinxFPGAs.
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TheDesignisnotdesignedorintendedforuseinthedevelopmentofon-linecontrolequipmentinhazardousenvironmentsrequiringfail-safecontrols,suchasintheoperationofnuclearfacilities,aircraftnavigationorcommunicationssystems,airtrafficcontrol,lifesupport,orweaponssystems("High-RiskApplications").
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2004–2006Xilinx,Inc.
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RevisionHistoryThefollowingtableshowstherevisionhistoryforthisdocument.
DateVersionRevision11/22/041.
0InitialXilinxrelease.
03/04/052.
0RenamedtitlefromML401EvaluationPlatformuserguidetoML40xEvaluationPlatformuserguide.
ExpandeddocumentfromML401-specifictoincludeML401,ML402,andML403platforms.
Added"BuildingtheLinuxBSP(PPC405SystemsOnly)"section.
07/05/053.
0RenamedtitlefromML40xEvaluationPlatformuserguidetoML40xEDKProcessorEvaluationPlatformuserguide.
UpdatedtheuserguideforEDK7.
1release.
Revisedthe"BuildingtheLinuxBSP(PPC405SystemsOnly)"section.
02/14/064.
0UpdatedtheuserguideforEDK8.
1release.
05/04/064.
1Updated"InstructionsforDownloadingtheDesign.
"06/30/065.
0ExpandedtoincludeML405evaluationplatform.
RML40xEDKProcessorReferenceDesignwww.
xilinx.
com3UG082(v5.
0)June30,2006ScheduleofFigures.
7ScheduleofTables9Preface:AboutThisGuideGuideContents11AdditionalResources11Conventions12Typographical.
12OnlineDocument13Chapter1:IntroductiontotheML40xEmbeddedProcessorReferenceSystemIntroduction15Requirements15CoreConnect16ReferenceSystemInformation16FurtherReading.
17ResourcesforEDKUsers(IncludingNewUsers)17DocumentationProvidedbyXilinx.
17IBMCoreConnectDocumentation17Chapter2:ML40xEmbeddedProcessorReferenceSystemIntroduction19Hardware19Overview19ProcessorLocalBus(PLB)22On-ChipPeripheralBus(OPB)23DeviceControlRegister(DCR)24Interrupts.
24Clock/ResetDistribution25CPUDebugviaJTAG26ErrorLEDs26IPVersionandSource26SynthesisandImplementation27DesignFlowEnvironment.
27MemoryMap28ML40xSpecificRegisters.
29ML40xBoardGeneralPurposeI/ORegisters29ML40xControlRegister130ML40xControlRegister231ML40xCharacterLCDGeneralPurposeI/ORegisters32TableofContents4www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006RML40xDifferentialExpansionHeaderGeneralPurposeI/ORegisters32ML40xSingle-EndedExpansionHeaderGeneralPurposeI/ORegisters33ExtendingorModifyingtheDesign34AddingorRemovingIPCores34Chapter3:EDKTutorialandDemonstrationIntroduction35InstructionsforInvokingtheEDKtools35LaunchingXilinxPlatformStudio(XPS)36InstructionsforSelectingSoftwareApplication.
36InstructionsforBuildingandImplementingtheDesign36InstructionsforDownloadingtheDesign.
37DownloadUsingParallelCableIVorPlatformCableUSB(iMPACTProgram)37DownloadUsingtheSystemACEInterface38Software39BuildingtheLinuxBSP(PPC405SystemsOnly)41Chapter4:IntroductiontoHardwareReferenceIPIntroduction43HardwareReferenceIPSourceFormatandSize.
44Chapter5:UsingIPIFtoBuildIPIntroduction45SRAMProtocolOverviewofIPIF46BasicWriteTransactions47BasicReadTransactions48IPIFStatusandControlSignals48UsingIPIFtoCreateaGPIOPeripheralfromScratch48UsingIPIFtoConnectaPre-ExistentPeripheraltotheBus50Conclusion.
51Chapter6:OPBAC97SoundControllerOverview53RelatedDocuments53Features.
53ModulePortInterface54Implementation.
56MemoryMap57Chapter7:OPBPS/2Controller(Dual)Overview61RelatedDocuments61Features.
61ModulePortInterface62ML40xEDKProcessorReferenceDesignwww.
xilinx.
com5UG082(v5.
0)June30,2006RImplementation.
64MemoryMap65Chapter8:PLBTFTLCDControllerOverview71RelatedDocuments71Features.
71ModulePortInterface71Hardware75Implementation75VideoTiming76MemoryMap78VideoMemory78ControlRegisters(DCRInterface)796www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006RML40xEDKProcessorReferenceDesignwww.
xilinx.
com7UG082(v5.
0)June30,2006Chapter1:IntroductiontotheML40xEmbeddedProcessorReferenceSystemChapter2:ML40xEmbeddedProcessorReferenceSystemFigure2-1:HardwareViewofML40xEmbeddedMicroBlazeReferenceSystem20Figure2-2:HardwareViewofML40xEmbeddedPPC405ReferenceSystem21Figure2-3:ClockGeneration25Chapter3:EDKTutorialandDemonstrationChapter4:IntroductiontoHardwareReferenceIPChapter5:UsingIPIFtoBuildIPFigure5-1:IPIFSRAMModuleInterface46Figure5-2:IPIFSimpleSRAMWriteCycle47Figure5-3:IPIFSimpleSRAMReadCycle.
48Figure5-4:IPIFSRAMModuletoGPIOLogicInterface.
49Chapter6:OPBAC97SoundControllerFigure6-1:OPBAC97SoundControllerBlockDiagram.
56Chapter7:OPBPS/2Controller(Dual)Figure7-1:OPBPS/2ControllerBlockDiagram64Chapter8:PLBTFTLCDControllerFigure8-1:High-LevelBlockDiagram.
75Figure8-2:HsyncandTFTClock76Figure8-3:HorizontalData76Figure8-4:Vsyncandh_syncs.
77Figure8-5:VerticalData77ScheduleofFigures8www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006RML40xEDKProcessorReferenceDesignwww.
xilinx.
com9UG082(v5.
0)June30,2006Chapter1:IntroductiontotheML40xEmbeddedProcessorReferenceSystemChapter2:ML40xEmbeddedProcessorReferenceSystemTable2-1:IPCoresintheML40xEmbeddedProcessorReferenceSystem.
26Table2-2:MemoryMaps.
28Table2-3:GPIORegisters(Address0x90000000-0x90000004)29Table2-4:ControlRegister1(Address0x90000008)30Table2-5:ControlRegister2(Address0x9000000C)31Table2-6:CharacterLCDGPIORegisters(Address0x90002000-0x90002004)32Table2-7:DifferentialExpansionHeaderGPIORegs(Addr0x90001000-0x90001004).
32Table2-8:Single-EndedExpansionHeaderGPIORegs(Addr0x90001008-0x9000100C)33Chapter3:EDKTutorialandDemonstrationTable3-1:DemonstrationSoftwareApplications39Chapter4:IntroductiontoHardwareReferenceIPTable4-1:HardwareReferenceIPandLogicUtilization44Chapter5:UsingIPIFtoBuildIPChapter6:OPBAC97SoundControllerTable6-1:GlobalSignals54Table6-2:OPBSlaveSignals54Table6-3:ExternalI/OPins54Table6-4:Generics(Parameters)55Table6-5:MemoryMap.
57Chapter7:OPBPS/2Controller(Dual)Table7-1:OPBSlaveSignals62Table7-2:ExternalI/OPins62Table7-3:Parameters63Table7-4:MemoryMapTable65Table7-5:OPBPS/2SlaveDevicePinDescription66Chapter8:PLBTFTLCDControllerTable8-1:GlobalSignals71ScheduleofTables10www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006RTable8-2:PLBMasterSignals72Table8-3:DCRSlaveSignals.
73Table8-4:ExternalOutputPins73Table8-5:Parameters74Table8-6:PixelColorEncoding.
78Table8-7:ControlRegisters(DCRInterface)79ML40xEDKProcessorReferenceDesignwww.
xilinx.
com11UG082(v5.
0)June30,2006RPrefaceAboutThisGuideThisuserguidedocumentstheML40xreferencedesign.
GuideContentsThisuserguidecontainsthefollowingchapters:Chapter1,"IntroductiontotheML40xEmbeddedProcessorReferenceSystem"Chapter2,"ML40xEmbeddedProcessorReferenceSystem"Chapter3,"EDKTutorialandDemonstration"Chapter4,"IntroductiontoHardwareReferenceIP"Chapter5,"UsingIPIFtoBuildIP"Chapter6,"OPBAC97SoundController"Chapter7,"OPBPS/2Controller(Dual)"Chapter8,"PLBTFTLCDController"AdditionalResourcesTofindadditionaldocumentation,seetheXilinxwebsiteat:http://www.
xilinx.
com/literature.
TosearchtheAnswerDatabaseofsilicon,software,andIPquestionsandanswers,ortocreateatechnicalsupportWebCase,seetheXilinxwebsiteat:http://www.
xilinx.
com/support.
12www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Preface:AboutThisGuideRConventionsThisdocumentusesthefollowingconventions.
Anexampleillustrateseachconvention.
TypographicalThefollowingtypographicalconventionsareusedinthisdocument:ConventionMeaningorUseExampleCourierfontMessages,prompts,andprogramfilesthatthesystemdisplaysspeedgrade:-100CourierboldLiteralcommandsthatyouenterinasyntacticalstatementngdbuilddesign_nameHelveticaboldCommandsthatyouselectfromamenuFile→OpenKeyboardshortcutsCtrl+CItalicfontVariablesinasyntaxstatementforwhichyoumustsupplyvaluesngdbuilddesign_nameReferencestoothermanualsSeetheDevelopmentSystemReferenceGuideformoreinformation.
EmphasisintextIfawireisdrawnsothatitoverlapsthepinofasymbol,thetwonetsarenotconnected.
Squarebrackets[]Anoptionalentryorparameter.
However,inbusspecifications,suchasbus[7:0],theyarerequired.
ngdbuild[option_name]design_nameBraces{}Alistofitemsfromwhichyoumustchooseoneormorelowpwr={on|off}Verticalbar|Separatesitemsinalistofchoiceslowpwr={on|off}Verticalellipsis.
.
.
RepetitivematerialthathasbeenomittedIOB#1:Name=QOUT'IOB#2:Name=CLKIN'.
.
.
Horizontalellipsis.
.
.
Repetitivematerialthathasbeenomittedallowblockblock_nameloc1loc2.
.
.
locn;ML40xEDKProcessorReferenceDesignwww.
xilinx.
com13UG082(v5.
0)June30,2006ConventionsROnlineDocumentThefollowingconventionsareusedinthisdocument:ConventionMeaningorUseExampleBluetextCross-referencelinktoalocationinthecurrentdocumentSeethesection"AdditionalResources"fordetails.
Referto"TitleFormats"inChapter1fordetails.
RedtextCross-referencelinktoalocationinanotherdocumentSeeFigure2-5intheVirtex-IIPlatformFPGAUserGuide.
Blue,underlinedtextHyperlinktoawebsite(URL)Gotohttp://www.
xilinx.
comforthelatestspeedfiles.
14www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Preface:AboutThisGuideRML40xEDKProcessorReferenceDesignwww.
xilinx.
com15UG082(v5.
0)June30,2006RChapter1IntroductiontotheML40xEmbeddedProcessorReferenceSystemIntroductionThischapterbrieflydescribesthereferencesystemprovidedforML40xevaluationplatforms.
TheML40xEmbeddedProcessorReferenceSystemcontainsacombinationofknownworkinghardwareandsoftwareelementsthat,together,createanentiresystem.
ItdemonstratesasystemusingtheProcessorLocalBus(PLB),On-ChipPeripheralBus(OPB),DeviceControlRegister(DCR)Bus,andthePowerPC405orMicroBlazeprocessorcore.
ThedesignoperatesundertheEmbeddedDevelopmentKit(EDK)suiteoftoolsthatprovidesagraphicaltoolframeworkfordesigningembeddedhardwareandsoftware.
ThereferencesystemisintendedtofamiliarizeuserswiththeVirtex-4product,itsdesigntoolflows,anditsfeatures.
ItprovidesafoundationforthosewhoarelearninghowtouseembeddedprocessorsinVirtex-4FPGAs.
ThisdocumentcoversMicroBlazebasedsystemsforML401,ML402,ML403boardsinadditiontoPowerPC405basedsystemsfortheML403andML405boards.
RequirementsThefollowinghardwareandsoftwarearerequiredinordertousetheML40xEmbeddedProcessorReferenceSystem.
OperatingSystemRequirements:WindowsXPProfessionalorLinuxNote:APCisrequiredforFPGAdownloadanddebugviaXilinxdownloadcables.
HardwareRequirements:XilinxML401,ML402,ML403,orML405evaluationplatformSoftwareRequirements:EmbeddedDevelopmentKit(EDK)8.
1-ServicePack1forML401,ML402,ML403-ServicePack2forML405ISE8.
1i-ServicePack2forML01,ML402,ML403-ServicePack3forML40516www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter1:IntroductiontotheML40xEmbeddedProcessorReferenceSystemRFornewEDKusers,theML40xEmbeddedProcessorReferenceSystemprovidesanexcellentexampleofhowtheEDKtoolscanbeusedtodesignafullfeaturedembeddedsystemconsistingofhardwareandsoftware.
ThereferencesystemalsoillustrateshowtodebugdesignsunderEDK.
ReferencestoadditionalinformationaboutlearningtouseEDKisavailablein"FurtherReading,"page17.
CoreConnectDownloadandinstallationoftheIBMCoreConnectToolkitcanbeusefulforhardwareandsystems.
TheCoreConnectToolkitisonlyavailabletoCoreConnectlicensees.
XilinxhassimplifiedtheprocessofbecomingaCoreConnectlicenseethroughWeb-basedregistrationavailableathttp://www.
xilinx.
com/coreconnect.
CoreConnectlicenseesareentitledtofullaccesstotheCoreConnectToolkitincludingpowerfulbusfunctionalmodeling,busmonitoringtools,andperiodicupdates.
TogetthemostoutoftheEmbeddedDevelopmentKit,XilinxrecommendstheuseoftheIBMCoreConnectToolkit.
ReferenceSystemInformationThissectionisanoverviewofthefeaturesoftheML40xEmbeddedProcessorReferenceSystem.
Althoughtheinformationcontainedinthereferencesystemchapterisnotexhaustive,itcoversthebasicrequirementstoeffectivelyusetheMicroBlazeorPowerPCprocessor.
Chapter2,"ML40xEmbeddedProcessorReferenceSystem"andChapter3,"EDKTutorialandDemonstration"haveinstructionsonhowtosynthesizeandrunthedesignsthroughtheXilinxImplementationTools(ISE)fortheVirtex-4family.
Thereferencesystemchapterscontainsectionsabout:HardwareusedinthesystemHDLfileorganizationSynthesisandimplementationSoftwareapplicationsthatinteroperatewiththesystemInstructionstorunthesoftwareapplicationsTheML40xEmbeddedProcessorReferenceSystemisanexampleofacompletelyembeddedcomputer.
Itprovidesawidevarietyofmemoryinterfacesonthreedifferingbuses,aswellasvariousperipheralssuchasmemorycontrollers,generalpurposeI/O(GPIO),andUARTs.
Theexamplesoftwareprovidedwiththisreferencesystemisdesignedtodemonstratethesystemrunningastand-aloneapplication.
TheEmbeddedProcessorReferenceSystemprovidesadditionalstudyofthePLB,OPB,andDCRbuses.
Inaddition,itaffordstheopportunitytoseehowOPB-baseddevicesareusedinasystem.
Step-by-stepinstructionsareprovidedtohelptheuserthroughthedesignflowandtotargetaVirtex-4device.
UserscanmodifytheML40xEmbeddedProcessorReferenceSystemtoaddandsubtractperipherals,aswellastochangethesoftwarefortheirowncustom-designedsystems.
Thesedesignscanbesynthesizedandrunthroughplace-and-routetoproduceabitstreamforVirtex-4devices.
Note:TheREADMEfileintheEDKprojectdirectoryofthereferencedesigncontainsimportantreleasenotesandinformationaboutthedesign.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com17UG082(v5.
0)June30,2006FurtherReadingRFurtherReadingXilinxprovidesawealthofvaluableinformationtoassistyouinyourdesignefforts.
SomeoftherelevantdocumentationislistedbelowwithmoreinformationavailablethroughtheXilinxSupportwebsiteathttp://www.
xilinx.
com/support.
ToobtainthemostrecentrevisionofdocumentationrelatedtotheML40xboard,seethecorrespondingWebpage:ML401:http://www.
xilinx.
com/ml401ML402:http://www.
xilinx.
com/ml402ML403:http://www.
xilinx.
com/ml403ML405:http://www.
xilinx.
com/ml405ResourcesforEDKUsers(IncludingNewUsers)EDKMainWebPagehttp://www.
xilinx.
com/ise/embedded/edk.
htmGettingStartedwiththeEDKhttp://www.
xilinx.
com/ise/embedded/edk_getstarted.
pdfEmbeddedSystemToolsGuidehttp://www.
xilinx.
com/ise/embedded/est_guide.
pdfEDKTutorialsandDesignExampleshttp://www.
xilinx.
com/ise/embedded/edk_examples.
htmEmbeddedProcessorDiscussionForumhttp://toolbox.
xilinx.
com/cgi-bin/forum14@@/Embedded%20ProcessorsDocumentationProvidedbyXilinxVirtex-4DataSheet:DCandSwitchingCharacteristicshttp://www.
xilinx.
com/bvdocs/publications/ds302.
pdfVirtex-4UserGuidehttp://www.
xilinx.
com/bvdocs/userguides/ug070.
pdfIBMCoreConnectDocumentationTheEmbeddedDevelopmentKitintegrateswiththeIBMCoreConnectToolkit.
Thetoolkitprovidesanumberoffeatures,enhancingdesignproductivityandallowingyoutogetthemostfromtheEDK.
Toobtainthetoolkit,youmustbealicenseeoftheIBMCoreConnectBusArchitecture.
LicensingCoreConnectprovidesaccesstoawealthofdocumentation,BusFunctionalModels,HardwareIP,andthetoolkit.
XilinxprovidesaWeb-basedlicensingmechanismthatallowsyoutoobtaintheCoreConnecttoolkitfromourwebsite.
TolicenseCoreConnect,useanInternetbrowsertoaccesshttp://www.
xilinx.
com/ipcenter/processor_central/register_coreconnect.
htm.
Afteryourrequesthasbeenapproved(typicallywithin24hours),youwillreceiveane-mailgrantingaccesstoaprotectedwebsite.
Youcanthendownloadthetoolkit.
Ifyouprefer,youcanalsolicenseCoreConnectdirectlyfromIBM.
IfyouwouldlikefurtherinformationonCoreConnectBusArchitecture,seeIBM'sCoreConnectwebsiteathttp://www.
ibm.
com/chips/products/coreconnect.
18www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter1:IntroductiontotheML40xEmbeddedProcessorReferenceSystemRML40xEDKProcessorReferenceDesignwww.
xilinx.
com19UG082(v5.
0)June30,2006RChapter2ML40xEmbeddedProcessorReferenceSystemIntroductionTheML40xEmbeddedProcessorReferenceSystemisanexampleofalargeVirtex-4basedsystem.
AnIBMCoreConnectinfrastructureconnectstheCPUtonumerousperipheralsusingProcessorLocalBus(PLB),On-ChipPeripheralBus(OPB),andDeviceControlRegister(DCR)busestobuildacompletesystem.
Thisdocumentdescribesthecontentsofthereferencesystemandprovidesinformationabouthowthesystemisorganizedandimplemented.
Acompletedesigncycleincorporatingsynthesis,FPGAimplementation,anddownloadisdescribed.
TheinformationintroducesmanyaspectsoftheML40xEmbeddedProcessorReferenceSystem,buttheusershouldrefertoadditionalspecificdocumentationformoredetailedinformationaboutthesoftware,tools,peripherals,interfaceprotocols,andcapabilitiesoftheFPGA.
HardwareOverviewFigure2-1,page20providesahigh-levelviewofthehardwarecontentsoftheEmbeddedMicroBlazeProcessorSystem.
Figure2-2,page21providesanoverviewofthePPC405-basedsystemforML403.
ThesedesignsdemonstrateasystemthatusesPLB,OPB,andDCRdevices.
ThePLBprotocolgenerallysupportshigherbandwidths,sothehigh-bandwidthdevicesareplacedthere.
TheOPBconnectsthelower-performanceperipheraldevicestotheCPU.
TheOPBoffersalesscomplexprotocolrelativetothePLB,makingiteasiertodesignperipheralsthatdonotrequirethehighestperformance.
TheOPBalsohastheadvantagethatitcansupportagreaternumberofdevices.
DCRisusedwithcontrolandstatusregistersforsimplicitywhenperformanceisnotimportant.
RefertothePLB,OPB,andDCRCoreConnectArchitectureSpecificationsformoreinformation.
ThehardwaredevicesusedinthisdesignaredescribedinmoredetailintheProcessorIPReferenceGuide(see/doc/proc_ip_ref_guide.
pdf)andinChapter4,"IntroductiontoHardwareReferenceIP.
"20www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter2:ML40xEmbeddedProcessorReferenceSystemRFigure2-1:HardwareViewofML40xEmbeddedMicroBlazeReferenceSystemUG082_02_01_050406DDRMemoryUSBMemoryMappedDCRBusDDRMEMCOPB2PLBBridgeZBTSRAMFlashButtons,LEDs,IIC,andmisc.
I/OsPLBARBOPBARBEthernetIPIFUARTEMCDCRBridgeIPIFMDMPS/2PS/2IPIFSystemACEMPUIPIFINTCIPIFIPIFEMCIPIFAC97SoundCtlrIPIFIPIFIPIFIPIFTFTLCDControllerGPIOGPIOExpansionHeaderGPIOIPIFCharLCDGPIOIPIFMicroBlazeDLMBILMBINTLMBBRAMCTLRLMBBRAMCTLRBRAMML40xEDKProcessorReferenceDesignwww.
xilinx.
com21UG082(v5.
0)June30,2006HardwareRFigure2-2:HardwareViewofML40xEmbeddedPPC405ReferenceSystemUG082_02_02_050406DDRMemoryUSBMemoryMappedDCRBusDDRMEMCPLB2OPBBridgeBRAMBRAMMEMCZBTSRAMFlashPLBARBOPBARBEthernetIPIFIICUARTEMCDCRBridgeIPIFIPIFPS/2PS/2SystemACEMPUIPIFINTCIPIFIPIFEMCIPIFAC97SoundControllerIPIFIPIFIPIFIPIFTFTLCDControllerGPIOGPIOExpansionHeaderGPIOIPIFCharLCDGPIOIPIFDSPLBISPLBINTPPC405ProcessorBlockButtons,LEDs,IIC,andmisc.
I/Os22www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter2:ML40xEmbeddedProcessorReferenceSystemRProcessorLocalBus(PLB)ThePLBconnectstheCPUtohigh-performancedevices,suchasmemorycontrollers.
ThePLBprotocolsupportshigherbandwidthtransactionsandhasafeaturesetbetterthanOPB/DCR.
PLBsupportsmemoryoperationsOPB/DCR.
HighlightsofthePLBprotocolincludesynchronousarchitecture,independentread/writedatapaths,andsplittransactionaddress/databuses.
Thereferencedesignincludesa64-bitPLBinfrastructurewith64-bitmasterandslavedevicesattached.
ThePLBdevicesinthereferencesysteminclude:PLBMasters640x480VGAControllerOPB-to-PLBBridge(MicroBlazesystem)PPC405Instruction-SidePLBInterface(PPC405system)PPC405Data-SidePLBInterface(PPC405system)PLBSlavesDoubleDataRate(DDR)SDRAMControllerBRAMController(PPC405systems)PLB-to-OPBBridge(PPC405system)PLBArbiter64-bitXilinxPLBArbiterIngeneral,allPLBdevicesareoptimizedaroundtheFPGAarchitectureandusepipeliningtoimprovemaximumclockfrequenciesandreducelogicutilization.
Refertothedocumentationaccompanyingeachdeviceformoreinformationaboutitsdesign.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com23UG082(v5.
0)June30,2006HardwareROn-ChipPeripheralBus(OPB)TheOPBconnectslower-performanceperipheraldevicestothesystem.
TheOPBhasalesscomplexarchitecture,simplifyingperipheraldevelopment.
OPBandPLBdevicescancommunicatebywayofanOPB-to-PLBBridgeoranPLB-to-OPBBridge.
TheOPBdevicesinthereferencesysteminclude:OPBMastersEthernetController(DMAEngine,ifenabled)MicroBlazeProcessorInstruction-SideInterface(MicroBlazesystem)MicroBlazeProcessorData-SideInterface(MicroBlazesystem)PLB-to-OPBBridge(PPC405system)OPBSlavesIICController(PPC405system)General-PurposeInput/Output(GPIO)x316450UARTInterruptControllerExternalMemoryControllerx2MicroprocessorDebugModule(MicroBlazesystem)AC97SoundControllerOPB-to-DCRBridgeEthernetControllerDualPS/2ControllerSystemACEMPUInterfaceOPB-to-PLBBridge-In(MicroBlazesystem)OPBArbiterIngeneral,allOPBdevicesareoptimizedaroundtheFPGAarchitectureandmakeuseofpipeliningtoimprovemaximumclockfrequenciesandreducelogicutilization.
Refertotheaccompanyingdocumentationforeachdeviceformoreinformationaboutitsdesign.
TheOPBdevicesinthereferencedesignmakeuseofIntellectualPropertyInterFace(IPIF)modulestofurthersimplifyIPdevelopment.
TheIPIFconvertstheOPBprotocolintocommoninterfaces,suchasanSRAMprotocoloracontrolregisterinterface.
IPIFmodulesalsoprovidesupportforDMAandinterruptfunctionality.
IPIFmodulessimplifysoftwaredevelopmentbecausetheIPIFframeworkhasmanycommonfeatures.
RefertoChapter5,"UsingIPIFtoBuildIP"formoreinformation.
TheIPIFisdesignedmainlytosupportawidevarietyofcommoninterfaces,butmightnotbetheoptimalsolutioninallcases.
Whereadditionalperformanceorfunctionalityisrequired,theusercandevelopacustomOPBinterface.
TheIPIFprotocolscanalsobeextendedtosupportotherbusstandards,suchasPLB.
ThisallowsthebackendinterfacetotheIPtoremainthesamewhilethebusinterfacelogicintheIPIFischanged.
ThisprovidesanefficientmeansforsupportingdifferentbusstandardswiththesameIPdevice.
TheOPBspecificationsupportsmastersandslavesofupto64bitswithadynamicbussizingcapabilitythatallowsOPBmastersandslavesofdifferentsizestocommunicatewitheachother.
TheML40xEmbeddedProcessorReferenceSystemusesasubsetoftheOPBspecificationthatsupportsonly32-bitbyteenablemastersandslaves.
Legacydevicesutilizing8-or16-bitinterfacesorthosethatrequiredynamicbussizingfunctionalityarenotdirectlysupported.
ItisrecommendedthatallnewOPBperipheralssupportbyte-enableoperationsforbetterperformanceandreducedlogicutilization.
24www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter2:ML40xEmbeddedProcessorReferenceSystemRDeviceControlRegister(DCR)TheDCRbusoffersaverysimpleinterfaceprotocolandisusedforaccessingcontrolandstatusregistersinvariousdevices.
ItallowsforregisteraccesstovariousdeviceswithoutoverloadingtheOPBandPLBinterfaces.
BecauseDCRdevicesaregenerallyaccessedinfrequentlyanddonothavehigh-performancerequirements,theyareusedthroughoutthereferencedesignforfunctions,suchaserrorstatusregisters,interruptcontrollers,anddeviceinitializationlogic.
AnOPB-to-DCRBridgeisinstantiatedtolocatethe4-KBDCRspacewithinthegeneralsystemmemoryspace.
TheDCRslavedevicesconnectedtotheOPB-to-DCRBridgeinclude:PLBArbiter(ifenabled)VGATFTLCDControllerTheDCRspecificationrequiresthattheDCRmasterandslaveclocksbesynchronoustoeachotherandrelatedinfrequencybyanintegermultiple.
ItisimportanttobeawareoftheclockdomainsofeachoftheDCRdevicestoensureproperfunctionality.
InterruptsAninterruptcontrollerforinterruptsiscontrolledthroughtheOPB.
ItallowsmultipleedgeorlevelsensitiveinterruptsfromperipheralstobeOR'edtogetherbacktotheCPU.
Theabilityforbitwisemaskingofindividualinterruptsisalsoprovided.
TheconnectionsfromtheIPtotheinterruptcontrollerare:UARTMicroprocessordebugmodule(MicroBlazesystem)EthernetcontrollerPS/2Port#1PS/2Port#2ExternalUSBchipSystemACEMPUAC97soundcontroller(playbuffer)AC97soundcontroller(recordbuffer)EthernetPHYIICcontroller(PPC405system)ML40xEDKProcessorReferenceDesignwww.
xilinx.
com25UG082(v5.
0)June30,2006HardwareRClock/ResetDistributionVirtex-4FPGAshaveabundantclockmanagementandglobalclockbufferresources.
Todemonstratesomeofthesecapabilities,theML40xEmbeddedProcessorReferenceSystemusesavarietyofdifferentclocks.
Figure2-3,page25illustratesuseofthedigitalclockmanagers(DCMs)forgeneratingthemainclocksinthedesign.
A100-MHzinputreferenceclockisusedtogeneratethemain100-MHzPLB,OPB,andDCRclocks.
TheCLK90/180/270outputoftheDCMproducesa100-MHzclockthatisphaseshiftedby90/180/270degreesforusebytheDDRSDRAMcontroller.
TheCLKFXoutputoftheDCMproducesa300-MHzprocessorclockforPPC405designs.
Themain100-MHzclockisdividedbyfourtocreatea25-MHzVGAclock.
AsecondDCMisusedtorecoveranddeskewtheexternalclockfromtheDDRSDRAM.
AthirdDCM(notshown)isusedtodeskewtheexternallydrivenSRAMclockwiththeinternal100-MHzclock.
Becauseeachclockisreferencedfromthesame100-MHzclock,theyareallphasealignedtoeachother.
ThissynchronousphasealignmentisrequiredbytheCPUandmanyotherdevicessotheycanpasssignalsfromoneclockdomaintoanother.
AfterasystemresetoratFPGAstartup,adebouncecircuitinsidetheProcessorSystemResetIPModuleholdstheFPGAinresetuntiltheDCMhaslockedontoitsreferenceclock.
OncetheDCMislockedandtheclocksremainstableforseveralcycles,theresetconditionisreleasedtoallowthesystemlogictobeginoperating.
Forexample,theCPUbeginsfetchinginstructionsafewcyclesafterresetisreleased.
Becausetheresetnetisahigh-fanoutsignal,itmightnotbeabletoreachallthelogicinthedesignwithinoneclockcycle.
UserIPblocksshouldbedesignedtotakeintoaccountthepossibleskewintheglobalresetandstillstartupproperly.
Alternatively,theglobalresetcanberegisteredlocallyineachIPblocktogenerateasynchronousresetsignal.
Figure2-3:ClockGenerationUG082_02_03_050406CLK1XCLK180CLK90CLK270CLKDVINCLKFXPLB/OPB/OCMVGADigitalClockManager1ExternalReferenceClock100MHzOff-chipconnectionforboarddeskew100MHz100MHz+90°100MHz+180°100MHz+270°CLK90CLK270INDDRController100MHz+270°100MHz+90°DDRControllerDigitalClockManager225MHzPPC405300MHz(notusedinMicroBlazesystems)26www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter2:ML40xEmbeddedProcessorReferenceSystemRCPUDebugviaJTAGTheCPUintheML40xEmbeddedProcessorReferenceSystemcanbedebuggedviaJTAGusingtheEDKtools.
ThepreferredmethodofcommunicatingwiththeCPUviaJTAGistocombinetheCPUJTAGchainwiththeFPGA'smainJTAGchain,whichisalsousedtodownloadbitstreams.
ForMicroBlazedesigns,thismethodrequirestheusertoinstantiateanOPBMDMcomponentanddirectlyconnectittotheCPUintheuser'sdesign.
ForPPC405designs,aJTAGPPCcomponentmustbeinstantiatedandconnectedtothePPC405processor.
TheprimaryadvantageofsharingthesameJTAGchainforCPUdebugandFPGAprogrammingisthatthissimplifiesthenumberofcablesneeded;asingleJTAGcable(liketheXilinxParallelCableIVcable)canbeusedforbitstreamdownloadaswellasCPUsoftwaredebugging.
ErrorLEDsThedesigncontainstwo*errorLEDoutputstosignalOPB(Error1)andPLB(Error2)errors.
OPBerrors(Error1LEDontheML40xboard)signalanOPBtimeoutorOPBerroracknowledgecondition.
PLBerrors(Error2LEDontheML40xboard)signalaPLBtimeoutordataerroracknowledgeconditionasreportedbythePLBarbiter.
Controlregistersinthedesignallowtheerrorconditionstobecleared.
See"ML40xControlRegister2,"page31formoreinformation.
Note:*OntheML403andML405boards,onlytheError1LEDispresent.
ItsignalsbothPLBandOPBerrorconditions.
IPVersionandSourceTable2-1(whichspansmultiplepages)summarizesthelistofIPcoresmakinguptheML40xEmbeddedProcessorReferenceSystem.
ThetableshowsthehardwareversionnumberofeachIPcoreusedinthedesign.
ThetablealsolistswhetherthesourceoftheIPisfromtheEDKinstallationorwhetheritisreferenceIPinthelocalpcoresdirectory.
Table2-1:IPCoresintheML40xEmbeddedProcessorReferenceSystemHardwareIPVersionSourcebram_block1.
00.
aEDKInstallationdcm_module1.
00.
aEDKInstallationdcr_v291.
00.
aEDKInstallationjtagppc_cntlr(PPC405systems)2.
00.
aEDKInstallationlmb_bram_if_cntlr(MicroBlazesystems)1.
00.
bLocalpcoresDirectory(1)lmb_v10(MicroBlazesystems)1.
00.
aEDKInstallationmicroblaze4.
00.
aEDKInstallationmisc_logic1.
00.
aLocalpcoresDirectoryopb_ac97_controller_ref1.
00.
aLocalpcoresDirectoryopb_emc2.
00.
aEDKInstallationML40xEDKProcessorReferenceDesignwww.
xilinx.
com27UG082(v5.
0)June30,2006SynthesisandImplementationRSynthesisandImplementationTheML40xEmbeddedProcessorReferenceSystemcanbesynthesizedandplaced/routedintoaVirtex-4FPGAundertheEDKtools.
Abasicsetoftimingconstraintsforthedesignisprovidedtoallowthedesigntogothroughplace-and-route.
DesignFlowEnvironmentTheEDKprovidesanenvironmenttohelpmanagethedesignflowfortheML40xEmbeddedProcessorReferenceSystemincludingsynthesis,implementation,andsoftwarecompilation.
EDKoffersaGUIorcommandlineinterfacetorunthesetoolsaspartofthedesignflow.
ConsulttheEDKdocumentationformoreinformation.
opb_ethernet1.
02.
aEDKInstallationopb_gpio3.
01.
bEDKInstallationopb_iic(PPC405systems)1.
01.
dEDKInstallationopb_intc1.
00.
cEDKInstallationopb_mdm(MicroBlazesystems)2.
01.
a(ML401)2.
00.
a(ML402/ML403)LocalpcoresDirectory(2)EDKInstallationopb_ps2_dual_ref1.
00.
aLocalpcoresDirectoryopb_sysace1.
00.
cEDKInstallationopb_uart165501.
00.
dEDKInstallationopb_v201.
10.
cEDKInstallationopb2dcr_bridge1.
00.
bEDKInstallationopb2plb_bridge(MicroBlazesystems)1.
00.
cEDKInstallationplb_bram_if_cntlr(PPC405systems)1.
00.
bEDKInstallationplb_ddr1.
11.
aEDKInstallationplb_tft_cntlr_ref1.
00.
cLocalpcoresDirectoryplb_v341.
02.
aEDKInstallationplb2opb_bridge(PPC405systems)1.
01.
aEDKInstallationppc405_virtex4(PPC405systems)1.
00.
aEDKInstallationproc_sys_reset1.
00.
aEDKInstallationNotes:1.
Modifiedtoreducepowerconsumption.
2.
Modifiedtousealternateboundaryscan(BSCAN)primitiverequiredforearlyVirtex-4engineeringsample(ES)devices.
Table2-1:IPCoresintheML40xEmbeddedProcessorReferenceSystemHardwareIPVersionSource28www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter2:ML40xEmbeddedProcessorReferenceSystemRMemoryMapThissectiondiagramsthesystemmemorymapfortheML40xEmbeddedProcessorReferenceSystem.
ItalsodocumentsthelocationoftheDCRdevicesasmappedbytheOPBtoDCRBridge.
ThememorymapshowninTable2-2reflectsthedefaultlocationofthesystemdevicesasdefinedinthesystem.
mhsfile.
Table2-2:MemoryMapsUG082_02_04_050406512BDualGPIO900001FF9000000064KB00000000LMBBRAM0000FFFF512BA8000000IICControllerA80001FFOPBtoPLBBridgeFFFE80FFFFFE8000256BOPBMDMD1000FDFD1000FC032BOPBINTC200FFFFF200000001MBOPBEMC(ZBTSRAM)287FFFFF280000008MBOPBEMC(Flash)900011FF90001000512BDualGPIO(ExpansionHeader)900021FF90002000512BGPIO(CharacterLCD)A50000FFA5000000256BOPBEMC(USB)4KBmemaddr=DCRaddrx4D0000000OPBtoDCRBridgeD0000FFF8KBUART1A0001FFFA000000016KB60000000Ethernet60003FFF8KBA9000000PS/2(Dual)A9001FFF512BCF000000SystemACEMPUCF0001FFTFTControlRegs(0x080-0x081)8BTFTVGAControllerD0000207D0000200A6000000AC97SoundA60000FF256B192MBPLBtoOPBBridgeBRAM3FFFFFFF20000000256MB7FFFFFFF60000000256MBDFFFFFFF80000000768MBFFFFFFFFFFFF000064KBDDRSDRAM03FFFFFF0000000064MBDDRSDRAMShadowMemory0FFFFFFF04000000192MBDDRSDRAM13FFFFFF1000000064MBDDRSDRAMShadowMemory1FFFFFFF14000000MicroBlazesystemsonlyPPC405systemsonlyPPC405systemsonlyPPC405systemsonlyPPC405systemsonly1FFFFFFF10000000256MBMicroBlazesystemsonlyMicroBlazesystemsonlyPLBDeviceMemoryMap(PPC405)DeviceAddressMaxMinSizeOPBDeviceMemoryMapOPBtoDCRBridgeMemory-MappedDCRDeviceMapDeviceAddressMaxMinSizeCommentComment(DCRAddrRange)DeviceAddressMaxMinSizeCommentPLBDeviceMemoryMap(MicroBlaze)DeviceAddressMaxMinSizeCommentShadowmemoryallowsvideomemorytobeaccessedasanuncachedregion.
ShadowMemorycontainsthreecopiesofDDRmemory.
Shadowmemoryallowsvideomemorytobeaccessedasanuncachedregion.
ShadowMemorycontainsthreecopiesofDDRmemory.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com29UG082(v5.
0)June30,2006ML40xSpecificRegistersRML40xSpecificRegistersThedesignalsocontainsanumberofregisterbitstocontrolvariousitemsontheML40xsuchasthebuttonsandLEDs.
SeetheEDKProcessorIPReferenceGuideat(/doc/proc_ip_ref_guide.
pdf)formoreinformationabouttheGPIO.
Table2-3throughTable2-8containinformationaboutcontrolandstatusregistersspecifictotheML40xEmbeddedProcessorReferenceSystem.
ML40xBoardGeneralPurposeI/ORegistersTable2-3(whichspanstothenextpage)showsthestandardsetofGPIOdata/directionregistersataddress0x90000000-0x90000004.
Table2-3:GPIORegisters(Address0x90000000-0x90000004)Bit(s)Description0(LSB)GeneralPurposeLED01GeneralPurposeLED12GeneralPurposeLED23GeneralPurposeLED34CenterDirectionalLED5WestDirectionalLED6SouthDirectionalLED7EastDirectionalLED8NorthDirectionalLED9CenterDirectionalButton10WestDirectionalButton11SouthDirectionalButton12EastDirectionalButton13NorthDirectionalButton14GeneralPurposeDIPSwitch1(ML401/ML402only)15GeneralPurposeDIPSwitch2(ML401/ML402only)16GeneralPurposeDIPSwitch3(ML401/ML402only)17GeneralPurposeDIPSwitch4(ML401/ML402only)18GeneralPurposeDIPSwitch5(ML401/ML402only)19GeneralPurposeDIPSwitch6(ML401/ML402only)20GeneralPurposeDIPSwitch7(ML401/ML402only)21GeneralPurposeDIPSwitch8(ML401/ML402only)22SMA"InputN"(ML401/ML403/ML405only)23SMA"InputP"(ML401/ML403/ML405only)24SMA"OutputN"(ML401/ML403/ML405only)30www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter2:ML40xEmbeddedProcessorReferenceSystemRML40xControlRegister1Table2-4showsControlRegister1locatedataddress0x90000008.
25SMA"OutputP"(ML401/ML403/ML405only)26UserClock(ML401/ML403/ML405only)27IICBusSelect0(ML405only)28IICBusSelect1(ML405only)31-29(MSB)ReservedNote:A1valueindicatesabuttonwaspushedorturnsONanLED.
Table2-3:GPIORegisters(Address0x90000000-0x90000004)(Continued)Bit(s)DescriptionTable2-4:ControlRegister1(Address0x90000008)Bit(s)Description0(LSB)IICSCL.
ValidonlywhenIICGPIOisenabled(see"ML40xControlRegister2,"Bit6).
Readingthisbitreadsthevaluefromtheexternalpin.
Writingthisbitsetsthevalueoftheexternalpinifthecorrespondingdirectionbitissettoa"write"(see"ML40xControlRegister2,"Bit0).
1IICSDA.
ValidonlywhenIICGPIOisenabled(see"ML40xControlRegister2,"Bit6).
Readingthisbitreadsthevaluefromtheexternalpin.
Writingthisbitsetsthevalueoftheexternalpinifthecorrespondingdirectionbitissettoa"write"(see"ML40xControlRegister2,"Bit1).
7-2Reserved.
8PS/2MouseClock.
ValidonlywhenPS/2GPIOisenabled(see"ML40xControlRegister2,"Bit7).
Readingthisbitreadsthevaluefromtheexternalpin.
Writingthisbitsetsthevalueoftheexternalpinifthecorrespondingdirectionbitissettoa"write"(see"ML40xControlRegister2,"Bit8).
9PS/2MouseData.
ValidonlywhenPS/2GPIOisenabled(see"ML40xControlRegister2,"Bit7).
Readingthisbitreadsthevaluefromtheexternalpin.
Writingthisbitsetsthevalueoftheexternalpinifthecorrespondingdirectionbitissettoa"write"(see"ML40xControlRegister2,"Bit9).
10PS/2KeyboardClock.
ValidonlywhenPS/2GPIOisenabled(see"ML40xControlRegister2,"Bit7).
Readingthisbitreadsthevaluefromtheexternalpin.
Writingthisbitsetsthevalueoftheexternalpinifthecorrespondingdirectionbitissettoa"write"(see"ML40xControlRegister2,"Bit10).
11PS/2KeyboardData.
ValidonlywhenPS/2GPIOisenabled(see"ML40xControlRegister2,"Bit7).
Readingthisbitreadsthevaluefromtheexternalpin.
Writingthisbitsetsthevalueoftheexternalpinifthecorrespondingdirectionbitissettoa"write"(see"ML40xControlRegister2,"Bit11).
12CPUResetButton.
ValidonlywhenCPUResetGPIOisenabled(see"ML40xControlRegister2,"Bit12).
Readingthisbitreadsthevaluefromtheexternalpin.
A"1"valueindicatestheCPUresetbuttonwaspushed.
31-13(MSB)Reserved.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com31UG082(v5.
0)June30,2006ML40xSpecificRegistersRML40xControlRegister2Table2-5showsControlRegister2locatedataddress0x9000000C.
Table2-5:ControlRegister2(Address0x9000000C)Bit(s)Description0(LSB)IICSCLI/ODirection.
ValidonlywhenIICGPIOisenabled(see"ML40xControlRegister2,"Bit6).
Settingthisbittoa1makestheGPIOIICSCLbitareadinput.
Settingthisbitto0makestheGPIOIICSCLbitawriteoutput.
1IICSDAI/ODirection.
ValidonlywhenIICGPIOisenabled(see"ML40xControlRegister2,"Bit6).
Settingthisbittoa1makestheGPIOIICSDAbitareadinput.
Settingthisbitto0makestheGPIOIICSDAbitawriteoutput.
2Error1LEDReset.
Writinga1tothisbitholdstheError1LEDoff.
Thisbitmustbewrittenbacktoa0topermitnormaloperation.
3Error1LEDSet.
Writinga1tothisbitholdstheError1LEDon.
Thisbitmustbewrittenbacktoa0topermitnormaloperation.
4Error2LEDReset.
Writinga1tothisbitholdstheError2LEDoff.
Thisbitmustbewrittenbacktoa0topermitnormaloperation.
(ML401/ML402only)5Error2LEDSet.
Writinga1tothisbitholdstheError2LEDon.
Thisbitmustbewrittenbacktoa0topermitnormaloperation.
(ML401/ML402only)6IICGPIO.
Writingthisbittoa1makestheIICSCL/SDApinscontrolledviaGPIOregisters.
Writingthisbittoa0makesIICSCL/SDApinscontrolledbytheOPBIICController(ifinstantiatedinsystem.
mhs).
7IICPS/2.
Writingthisbittoa1makesthePS/2mouse/keyboardpinscontrolledviaGPIOregisters.
Writingthisbittoa0makesthePS/2pinscontrolledbytheOPBDualPS/2Controller.
8PS/2MouseClockI/ODirection.
ValidonlywhenPS/2GPIOisenabled(see"ML40xControlRegister2,"Bit7).
Settingthisbittoa1makesthePS/2MouseClockbitareadinput.
Settingthisbitto0makesthebitawriteoutput.
9PS/2MouseDataI/ODirection.
ValidonlywhenPS/2GPIOisenabled(see"ML40xControlRegister2,",Bit7).
Settingthisbittoa1makesthePS/2MouseDatabitareadinput.
Settingthisbitto0makesthebitawriteoutput.
10PS/2KeyboardClockI/ODirection.
ValidonlywhenPS/2GPIOisenabled(see"ML40xControlRegister2,"Bit7).
Settingthisbittoa1makesthePS/2KeyboardClockbitareadinput.
Settingthisbitto0makesthebitawriteoutput.
11PS/2KeyboardDataI/ODirection.
ValidonlywhenPS/2GPIOisenabled(see"ML40xControlRegister2,"Bit7).
Settingthisbittoa1makesthePS/2KeyboardDatabitareadinput.
Settingthisbitto0makesthebitawriteoutput.
12CPUResetGPIO.
Writingthisbittoa1makesthestateoftheCPUResetbuttonreadableusingML40xControlRegister1,Bit12.
Settingthisbittoa1preventstheCPUResetbuttonfromcausingasystemreset.
Thisbitmustbesetbackto0fornormaloperationoftheCPUResetbutton.
13USBReset.
Settingthisbittoa1resetstheUSBcontrollerchip.
Thisbitmustbesetbackto0topermitnormaloperationoftheUSBcontroller.
31-14(MSB)Reserved.
32www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter2:ML40xEmbeddedProcessorReferenceSystemRML40xCharacterLCDGeneralPurposeI/ORegistersTable2-6showsthecharacterLCDregisters,whichareastandardsetofGPIOdata/directionregistersataddress0x90002000-0x90002004.
ML40xDifferentialExpansionHeaderGeneralPurposeI/ORegistersTable2-7showsthedifferentialexpansionheaderregisters,whichareastandardsetofGPIOdata/directionregistersataddress0x90001000-0x90001004.
Table2-6:CharacterLCDGPIORegisters(Address0x90002000-0x90002004)Bit(s)Description0(LSB)CharacterLCDPin"DB4"1CharacterLCDPin"DB5"2CharacterLCDPin"DB6"3CharacterLCDPin"DB7"4CharacterLCDPin"RW"5CharacterLCDPin"RS"6CharacterLCDPin"E"31-7(MSB)ReservedTable2-7:DifferentialExpansionHeaderGPIORegs(Addr0x90001000-0x90001004)BitDescriptionBitDescription1-0J5,Pin4;J5,Pin217-16J5,Pin36;J5,Pin343-2J5,Pin8;J5,Pin619-18J5,Pin40;J5,Pin385-4J5,Pin12;J5,Pin1021-20J5,Pin44;J5,Pin427-6J5,Pin16;J5,Pin1423-22J5,Pin48;J5,Pin469-8J5,Pin20;J5,Pin1825-24J5,Pin52;J5,Pin5011-10J5,Pin24;J5,Pin2227-26J5,Pin56;J5,Pin5413-12J5,Pin28;J5,Pin2629-28J5,Pin60;J5,Pin5815-14J5,Pin32;J5,Pin3031-30J5,Pin64;J5,Pin62ML40xEDKProcessorReferenceDesignwww.
xilinx.
com33UG082(v5.
0)June30,2006ML40xSpecificRegistersRML40xSingle-EndedExpansionHeaderGeneralPurposeI/ORegistersTable2-8showsthesingle-endedexpansionheaderregisters,whichareastandardsetofGPIOdata/directionregistersataddress0x90001008-0x9000100C.
Table2-8:Single-EndedExpansionHeaderGPIORegs(Addr0x90001008-0x9000100C)BitDescriptionBitDescription0J6,Pin216J6,Pin341J6,Pin417J6,Pin362J6,Pin618J6,Pin383J6,Pin819J6,Pin404J6,Pin1020J6,Pin425J6,Pin1221J6,Pin446J6,Pin1422J6,Pin467J6,Pin1623J6,Pin488J6,Pin1824J6,Pin509J6,Pin2025J6,Pin5210J6,Pin2226J6,Pin5411J6,Pin2427J6,Pin5612J6,Pin2628J6,Pin5813J6,Pin2829J6,Pin6014J6,Pin3030J6,Pin6215J6,Pin3231J6,Pin6434www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter2:ML40xEmbeddedProcessorReferenceSystemRExtendingorModifyingtheDesignTheML40xEmbeddedProcessorReferenceSystemisagoodstartingpointfromwhichausercanadd,remove,ormodifycomponentsinthesystem.
BecausemostoftheIPinthedesignisattachedtotheCoreConnectinfrastructureunderEDK,addingorremovingdevicesisafairlystraightforwardprocess.
Belowisanoverviewformakingvariouschangestothesystem.
AddingorRemovingIPCoresToremoveanIPcore:1.
DeletetheinstantiationforthatpieceofIPfromthesystem.
mhsfile(orusetheAdd/EditCoresfeatureoftheEDKGUI).
2.
DeleteallcorrespondingexternalI/Oportsfromthesystem.
mhsfile.
3.
RemovecorrespondingUCFfileentriesspecifyingtimingorpinoutlocationsforthatIP.
ToaddanIPcore:1.
Instantiatethedevicebyaddingittothesystem.
mhsfile(orusetheAdd/EditCoresfeatureoftheEDKGUI).
2.
ConnectitsexternalI/Otothetoplevel.
3.
Setitsconfigurationparameters(i.
e.
,baseaddress)inthesystem.
mhsfile(orusetheAdd/EditCoresfeatureoftheEDKGUI).
4.
AddappropriatetimingandpinoutconstraintstotheUCFfile.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com35UG082(v5.
0)June30,2006RChapter3EDKTutorialandDemonstrationIntroductionThischaptercontainsbasicinstructionsforusingtheEDKtoolswiththeML40xEmbeddedProcessorReferenceSystem.
Itisdesignedtohelpillustratethestepstobuildanddownloadthedesign.
Informationaboutdemonstrationsoftwareapplicationsisalsoprovided.
TheinstructionsthatfollowprovideonlyanoverviewofthecapabilitiesofEDK.
MuchmoredetailaboutoperatingtheEDKtoolscanbefoundintheEDKdocumentation.
Thischapterassumesthatthereferencedesignandallothernecessarytoolsareproperlyinstalled.
InstructionsforInvokingtheEDKtoolsThistutorialsectionandthosethatfollowhavedirectorypathnamesthatareshownseparatedbythe"/"characteraspertheUNIXconvention.
ForWindows,the"\"shouldbeusedtoseparatedirectorypaths.
Theinstructionsthatfollowreferencethelocatedat:ML401MicroBlaze:/projects/ml401_emb_ref/ML402MicroBlaze:/projects/ml402_emb_ref/ML403MicroBlaze:/projects/ml403_emb_ref/PPC405:/projects/ml403_emb_ref_ppc/ML405MicroBlaze:/projects/ml405_emb_ref/PPC405:/projects/ml405_emb_ref_ppc/ThesearetheareaswheretheEDKXilinxMicroprocessorProject(XMP)filesresideafterinstallingtheML40xEmbeddedProcessorReferenceSystem.
36www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter3:EDKTutorialandDemonstrationRLaunchingXilinxPlatformStudio(XPS)1.
OpentheXPSGUI.
OnaPC,click:Start→Programs→XilinxPlatformStudio.
OnLinux,sourcethenecessaryenvironmentscripts,andlaunchXPS:$xps2.
OpenXPSprojectfilefortheML40xEmbeddedProcessorReferenceSystem:ClickFile→OpenProject.
Browsetofindthe.
Selectthefilesystem.
xmp,clickOpen.
ThisopenstheprojectfileunderEDK.
Itisnowreadytobuildordownloadthesystemusingtheuser-selectedsoftwareapplicationprogram.
Youarenowreadytoproceedwiththefollowinginstructions.
InstructionsforSelectingSoftwareApplicationThesystem.
xmpEDKprojectfilesupportsmultipleusersoftwareapplications.
Toselectwhichsoftwareapplicationtocompile,followtheinstructionsbelow.
1.
ClicktheApplicationstabontheleft-handpane,thenscrolldownandlookforProject:hello_uart.
2.
Right-clickonProject:hello_uartandselectMakeProjectActive.
Note:Thistutorialusesthehello_uartapplicationasanexample.
Toselectadifferentsoftwareapplication,right-clickontheactiveprojectandselectMakeProjectInactive.
Thenfindthesoftwareapplicationofinterestandmakethatprojectactive.
See"Software,"page39formoreinformation.
InstructionsforBuildingandImplementingtheDesignAftersuccessfullyloadingthedesign,itcannowbesynthesizedandplace-and-routedtoberunonrealML40xhardware.
1.
Synthesizethedesign.
InXPS,clickHardware→GenerateNetlist.
Note:Thisstepmighttakesometimetocomplete.
InXPS,clickHardware→GenerateBitstream.
Note:Thisstepmighttakesometimetocomplete.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com37UG082(v5.
0)June30,2006InstructionsforDownloadingtheDesignRInstructionsforDownloadingtheDesignThehardwarebitstreamsandsoftwarebinaryexecutablefilescanbedownloadedtotheML40xboardusingadownloadcable(XilinxParallelCableIVorPlatformCableUSB)ortheSystemACEinterface.
Thedownloadeddesignrunsthehello_uartprogram.
Toseethisprogramrunning,connectaserialcablefromaPCtotheML40xboard.
UseaterminalprogramlikeHyperTerminal(shippedwithWindows)andsettheCOMportsettingsto9600baud,8DataBits,NoParity,1StopBit,Noflowcontrol.
Aftertheprogramisdownloadedusingtheinstructionsbelow,youshouldseeHelloWorld!
onyourterminal.
TheboardthenechoesthecharactersyoutypeuntilyoupresstheEscapekey.
DownloadUsingParallelCableIVorPlatformCableUSB(iMPACTProgram)Afterthedesignisimplemented,abitstreamcanbegeneratedanddownloadedintoanFPGAusingaprogramlikeiMPACT,availablewiththeXilinxISEtools.
(APCshouldbeusedforthisstep.
)1.
ConnectthedownloadcablefromaPCtotheML40xboardandpowerontheboard.
2.
ClickDeviceConfiguration→DownloadBitstreamwithinXPS.
Note:Thisloadsabitstreamcontainingabootloopprogramthateffectivelyidlestheprocessor-notthesoftwareprogramthatyouhavespecified.
Youmustcontinuewiththeremainingstepsinthissectiontoloadyourprogram.
3.
ClickDebug→LaunchXMD.
.
.
Note:OntheML401board,youmustconfigureXMDtocommunicatewiththeopb_mdmmoduleusingBSCANnumber1insteadofthedefaultofBSCAN0.
Refertothe/READMEfileandSolutionRecord#20060formoreinformation.
Bydefault,theML401xmd_microblaze_0.
optfileisconfiguredforParallelCableIVdownloadandrequireseditingforusewiththePlatformCableUSB.
Note:ForML402,ML403,andML405,the"settheXMDDebugOptions…,"messageappearsthefirsttimeyourunXMD.
ClickOKtoenterdebugoptioninformationsuchasthetypeofJTAGcableyouareusing.
ThenclickSavewhenfinished.
YoumaychangedebugoptionsatanytimebyselectingDebug→XMDDebugOptionsfromtheXPSGUI.
Refertothe/READMEfileformoreinformation.
4.
ThisopensanXMDcommandshell.
5.
TypeintoXMD:dowmicroblaze_0/code/hello_uart.
elf(MicroBlazesystems)dowppc405_0/code/hello_uart.
elf(PPC405systems)Thisloadsthecodeintomemory.
6.
Typeruntostarttheprogram.
38www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter3:EDKTutorialandDemonstrationRDownloadUsingtheSystemACEInterfaceTheSystemACEconfigurationmanagementsystemallowstheusertostorehardwareandsoftwareinformationonaCompactFlashdeviceanduseittoprogramoneormoredevicesviaJTAG.
TheML40xplatformusestheSystemACEchipinconjunctionwithstandardCompactFlashcardstoenablehardwareandsoftwareprogrammingoftheFPGA.
MoreinformationabouttheSystemACEinterfaceisavailablefromhttp://www.
xilinx.
com/systemace.
EDKsupportsthegenerationofSystemACEfilestodownloadbitstreamsandsoftwareapplicationsontoVirtex-4FPGAs.
Thisisaccomplishedbyconcatenating(1)theJTAGcommandstodownloadthebitstreamwith(2)theJTAGcommandstodownloadthesoftwareprogram.
ThiscombinedsetofJTAGcommandsisencodedintoanACEfilethatcanbereadfromaCompactFlashcardbytheSystemACEchip.
ThisdownloadmethodcreatesanACEfilethatcontainsthebitstreamandsoftwarethatcanbesavedtotheCompactFlashdeviceandinsertedintotheML40xboard.
1.
WithinXPS,selectDeviceConfiguration→GenerateSystemACEFile.
Note:Thiscommandusesthelocalscriptfile/genace.
tcl(overridingtheEDKdefaultscript)togeneratetheACEfile/implementation/system.
ace.
2.
CopythisfiletoyourCompactFlashdevice.
-IfusinganewlyformattedMicrodriveorCompactFlashdevice,copyittotherootdirectory.
-IfusingtheCompactFlashdevicethatshippedwithML40x,copytheACEfileintotheML40x\myacedirectoryoftheCompactFlashdevice.
-RenametheexistingACEfiletosystem_my_ace.
baksothereisonlyoneACEfileinthedirectory.
Note:OntheML402board,itmightbenecessarytobackuptheoldACEfileofftheCompactFlashdeviceduetothelimiteddiskspace.
3.
InserttheCompactFlashdeviceintotheML40x.
-IftheACEfileisintherootdirectory,itdownloadsimmediately.
-IftheACEfileisintheML40x\myacedirectoryoftheCompactFlashdevice,selectMyOWNAceFileonthebootloadermenu.
RefertotheSystemACEandEDKdocumentationforfurtherdetails.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com39UG082(v5.
0)June30,2006SoftwareRSoftwareTable3-1(whichspansmultiplepages)liststhedemonstrationsoftwareapplicationsportedtotheEDKdesign.
Thedemonstrationsoftwareiskeptapartfromthehardwaredesigntomakeitreusableforotherprojects.
TheuserselectsthedesiredsoftwareprojectbyselectingtheApplicationstabintheleft-handwindowpaneandchoosingwhichapplicationtouse.
Table3-1:DemonstrationSoftwareApplicationsNameDescriptionDesignFilesbootloadDisplaysmenuonVGA/LCD/SerialPortandloadsappropriateACEfilebasedonuserinput.
sw/standalone/bootload/button_led_testTurnsonLEDswhenbuttonsarepressed.
sw/standalone/button_led_test/flash_helloProgramdesignedtobeloadedfromlinearflashdescribingtheprocessbywhichitwasloaded.
sw/standalone/flash_hello/flash_loadProgramthatloadsdatafromSystemACECompactFlashcardsandprogramsthemintoFLASHmemory.
sw/standalone/flash_load/flash_testProgramthatwritesandreadsFLASHtotestit.
sw/standalone/flash_test/helloUsingC'sstudiolibrary,printsHelloworld!
andechoescharactersenteredviastandardinputtostandardoutput.
sw/standalone/hello/hello_uartUsingtheEDKUARTdriver,printsHelloworld!
ontheUARTandoutputscharactersenteredviastandardinputtostandardoutput.
sw/standalone/hello_uart/iic_eepromWritestestpatterntoIICandreadsbackdata(Note:ThistestwilloverwritethecontentsofIIConlyifenabledtodoso.
)sw/standalone/iic_eeprom/my_aceProgramaskingusertocreatetheirownACEfile.
sw/standalone/my_ace/my_plat_flashProgramaskingusertoloadtheirowndesignintoPlatformFlash.
sw/standalone/my_plat_flash/plat_flash_menuAProgramlistingthedemosavailableonthePlatformFlash.
(ML401andML405only.
)sw/standalone/plat_flash_menu/ps2_scancodes_polledPolled,readskeystrokesonakeyboardattachedtoPS/2port1anddisplayscorrespondingPS/2scancodesonstandardoutput.
sw/standalone/ps2_scancodes_polled/simonSimongameusingLCD,LEDs,andbuttonsontheML40x.
sw/standalone/simon/slideshowReadsaudioandvideofilesfromCompactFlashviaSystemACEinterfaceanddisplaysaslideshowaccompaniedbymusic.
sw/standalone/slideshow/sysace_rebooterProgramthatasksuserwithwhichSystemACEconfigurationtoreconfigure.
sw/standalone/sysace_rebooter/40www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter3:EDKTutorialandDemonstrationRtest_ac97ProgramthatrecordssoundfromtheLine-In/Microphoneinputs,storestheaudiodataintoDDRmemory,thenplaysthesoundtotheLine-OutandHeadphoneoutputs.
sw/standalone/test_ac97/testfatfsSimpletestprogramthatreadsfilesfromCompactFlashviaSystemACEinterface.
sw/standalone/testfatfs/usb_hpi_testEchoescharacterstypedonaUSBkeyboardtotheLCDandserialportontheML40x.
sw/standalone/usb_hpi_test/usb_printerPrintsHelloWorld!
toaUSBprinter.
sw/standalone/usb_printerwebserverImplementsawebserverthatdisplaysML40xDIPswitchsettingsandcontrolsLEDs.
sw/standalone/web_server/xromML40xboardtestanddiagnosticprogram.
sw/standalone/ml40x/sw/standalone/xrom/Table3-1:DemonstrationSoftwareApplications(Continued)NameDescriptionDesignFilesML40xEDKProcessorReferenceDesignwww.
xilinx.
com41UG082(v5.
0)June30,2006BuildingtheLinuxBSP(PPC405SystemsOnly)RBuildingtheLinuxBSP(PPC405SystemsOnly)TheEDKdesigncomeswithMLD/TCLtechnologytogenerateaLinuxBSPforML40xandascripttopatchaMontaVistaLinuxkernelfromtheML300LSPforusewiththisBSP.
TobuildaBSPforandtopatchtheLinuxkernel,proceedasfollows:1.
StartXPSandloadtheLinuxXMP:$xpssystem_linux.
xmp2.
GeneratetheLinuxBSPwithTools→GenerateLibrariesandBSPs.
TheresultingLinuxBSPislocatedinppc405_0/libsrc/linux_mvl31_v1_00_a/linux.
3.
QuitXPS.
4.
CreateacopyoftheMontaVistaLinuxkernelfortheML300board.
TheLinuxkernelandthetoolstobuildtheLinuxkernelareavailablefromMontaVista(http://www.
mvista.
com).
ForfurtherinformationaboutusingLinuxwithEDK,refertoXilinxXAPP765:GettingStartedwithEDKandMontaVistaLinux.
5.
PatchtheLinuxkernelforusewiththeML40xboard:$cdlinux$.
/patch_linuxThisstepcopiesthe.
configfilefromthelinuxdirectorytotheLinuxkernel,patchestheLinuxkernelwithnecessarychangesfortheML40xboard,andcopiestheLinuxBSPintotheLinuxkernel.
BuildtheLinuxkernel.
$cd$makeoldconfigdepbzImageTheresultingLinuxkernelresidesinarch/ppc/boot/images/zImage.
elf6.
TobuildanACEfileconsistingoftheFPGAbitstreamandtheLinuxkernel,clickTools→Xygwinshelltorunashell,thentype:$xmd-tclgenace.
tcl-jprog-hwimplementation/download.
bit-elf-aceimplementation/system.
ace42www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter3:EDKTutorialandDemonstrationRML40xEDKProcessorReferenceDesignwww.
xilinx.
com43UG082(v5.
0)June30,2006RChapter4IntroductiontoHardwareReferenceIPIntroductionTheEmbeddedProcessorReferenceSystemcontainsadditionalhardwareIPbeyondwhatisbeshippedwiththeEDKtoolsuite.
ThishardwareIPsupportssomeofthefeaturesontheML40xboard.
TheIPanditssourcecodeisprovidedasareferenceexampletoillustratehowhardwarecanbedesignedtointerfacewiththeProcessorLocalBus(PLB),On-chipPeripheralBus(OPB),andDeviceControlRegister(DCR)bus.
Generally,theinterfaceandfunctionoftheIPisdescribed,alongwithsufficientregisterinformationforcustomerstousethedevices.
ThereferenceIPsourcecodeislocatedwithinthepcoresdirectoryoftheML40xReferenceSystem'sEDKprojectdirectory.
InadditiontodescribingtheindividualhardwareIPs,thisdocumentalsointroducestheconceptoftheIPInterFace(IPIF)modules.
Thesemodulesaredesignedtogreatlyacceleratetheprocessofconnectingtopre-existentIPorcreatingnewIPinasystem.
ThespecificationdefinesaCoreConnectcompliantinterfaceononesideandasimpleinterfaceforconnectingtoexistentIPontheotherside.
ThehardwareIPusestheIBMCoreConnectbusstandardsasitsmeansofcommunicationbetweentheembeddedprocessorandotherdevices.
ThesestandardsaredocumentedintheIBMCoreConnectrelease.
Pleaseseethe"FurtherReading,"page17sectionformoreinformationonwheretofindtherelevantdocuments.
ForfurtherinformationontheIPIFandeachIP,see:Chapter5,"UsingIPIFtoBuildIP"Chapter6,"OPBAC97SoundController"Chapter7,"OPBPS/2Controller(Dual)"Chapter8,"PLBTFTLCDController"44www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter4:IntroductiontoHardwareReferenceIPRHardwareReferenceIPSourceFormatandSizeThehardwarereferenceIPavailablewiththeML40xEmbeddedProcessorReferenceSystemoriginatesinonelanguageaseitherVerilogorVHDLsourcecode.
IPdeliveredinVerilogorVHDLsourceformatisdirectlyviewableandeditablebytheuserasatextfile.
TheEDKtoolshandletheprocessofbuildingsystemsconsistingofamixtureofIPwrittenindifferentlanguages.
Forexample,thePLBTFTLCDControllerisavailableonlyinVerilogsourcecode,sotheEDKtoolsneedtoconvertthedesignintoablackboxnetlistforuseinatop-levelVHDL-baseddesign.
Table4-1providesinformationaboutthesourcecodeformatandresourceutilizationforthesecores.
ManyoftheIPblocksareparameterizeablesotheirsizemightincreaseordecreasedependingonhowtheyareconfigured.
TheseareanumbersrepresentafullimplementationofeachIPsynthesizedwiththeXilinxtoolXST.
ItisimportanttonotethatwhenIPisconnectedtogetherinasystem,logicoptimizationsandresourcesharingcanfurtherreducetheoveralllogiccount.
Sliceutilizationisonlyanestimatebecausethepackingoflookuptables(LUTs)andflip-flops(FFs)intoslicesdependsontheoverallsystemimplementation.
Thesearealltitlesofindividualdocumenttypesinabook.
Someareautonumbered,somearenot.
Table4-1:HardwareReferenceIPandLogicUtilizationSourceCodeFormatLogicUtilizationNameVerilogVHDLSliceFFsLUTsSlices(Est)BlockRAMsOPBAC97SoundControllerX1832041510OPBPS/2ControllerX2654302360PLBTFTLCDControllerX2762891931ML40xEDKProcessorReferenceDesignwww.
xilinx.
com45UG082(v5.
0)June30,2006RChapter5UsingIPIFtoBuildIPIntroductionVirtex-4devicescombineembeddedprocessorsandFPGAfabricintooneintegratedcircuit.
Inthepast,systemdevelopmenteffortsreliedonengineersbuildingeachcomponentfromscratch.
Today,engineershaveawidevarietyofmicroprocessorperipheralsintheirIPlibraries.
TheIntellectualPropertyInterFace(IPIF)isdesignedtoeasethecreationofnewIP,aswellastheintegrationofexistentIP,withinaVirtex-4device.
ThischapterillustratestheutilityoftheIPIFtointegrateIPintoasystem.
TheIPIFmodulessimplifythedevelopmentofCoreConnectdevices.
TheIPIFconvertscomplexsystembuses,suchasthePLBorOPB,intocommoninterfaces,suchasanSRAMprotocoloracontrolregisterinterface.
ThismakesIPIFmodulesidealforquicklydevelopingnewbusperipherals,orconvertingexistingIPtoworkinaCoreConnectbus-basedsystem.
TheIPIFmodulesprovidepoint-to-pointinterfacesusingsimpletimingrelationshipsandverylightprotocols.
TheIPIFisdesignedtobebus-agnostic.
ThisallowsthebackendinterfacefortheIPtoremainthesamewhileonlythebusinterfacelogicintheIPIFischanged.
It,therefore,providesanefficientmeansforsupportingdifferentbusstandardswithoutchangetotheIPdevice.
IPIFmodulesalsoprovidesupportforDMAandinterruptfunctionality.
TheIPIFisdesignedtosupportawidevarietyofcommoninterfaces(likeSRAM,FIFO,andcontrolregisterprotocols).
Whereadditionalperformanceorfunctionalityisrequired,theusercandevelopacustomOPBorPLBbusinterface.
IPIFmodulessimplifydriversoftwaredevelopmentbecausetheIPIFframeworkcontainsmanycommonfeatures.
Theseincludeaconsistentmeansofinterrupthandling,DMA,andorganizingcontrol/statusregisters.
ThisdocumentdemonstrateshowquicklyandeasilyanewpieceofIPcanbedevelopedusingtheIPIF.
TheprocessandstepsforbuildinganewCoreConnectdevicebasedontheSRAMprotocolIPIFisdescribedbelow.
Forthissampledesign,a32-bitGeneralPurposeI/O(GPIO)deviceiscreated.
TheGPIOallowsaCoreConnectmastersuchastheCPUtocontrolasetofexternalpinsusingasimplememory-mappedinterface.
46www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter5:UsingIPIFtoBuildIPRSRAMProtocolOverviewofIPIFFigure5-1diagramstheconnectionsbetweentheIPIFandtheuserIPforSRAMprotocolinterface.
TheIPIFsimplifiesthedesignbyprovidingaPLBorOPBinterfaceandcondensingitdowntoasmallsetofeasilyunderstoodsignals.
AllinterfacesignalswiththeIPIFaresynchronoustorisingclockedges.
TheIPIFtakestheclockfromtheOPBorPLBbusinterfaceandpassesittotheIP,causingtheIPtousethesameglobalclockasthebusitisconnectedto.
TheSRAMinterfaceprotocolusedbytheIPIFcanbedescribedbyobservingawriteandreadtransaction.
Figure5-1:IPIFSRAMModuleInterfaceUG082_05_01_050406IPSlavePeripheralSRAMModuleBus2IP_ClkBus2IP_Addr[m:0]Bus2IP_Data[0:n]IP2Bus_Data[0:n]Bus2IP_BE[0:b]Bus2IP_SRAM_CEBus2IP_WrReqIP2Bus_WrAckBus2IP_RdReqIP2Bus_RetryIP2Bus_ErrorIPIFSlaveSRAMModuleNote:SupportsbothwithandwithoutDMABusBus2IP_ResetIP2Bus_ToutSupIP2Bus_Intr[0:i]IP2Bus_RdAckML40xEDKProcessorReferenceDesignwww.
xilinx.
com47UG082(v5.
0)June30,2006SRAMProtocolOverviewofIPIFRBasicWriteTransactionsFigure5-2showsthetimingdiagramforawritetransaction.
AwritetransactionbeginswhentheIPIFdrivestheaddress(Bus2IP_Addr),byteenables(Bus2IP_BE),andwritedata(Bus2IP_Data)totheIP.
Notethatthesignaldirectionisspecifiedinthesignalname:Bus2IPversusIP2Bus.
TheIPIFqualifiesthewritebyassertingasingleclockcycleHighpulse(Bus2IP_WrReq)atthebeginningofthetransaction.
ItthenwaitsfortheIPdevicetoacknowledgecompletionofthewritebysendingbackasingleclockcycleHighpulseonIP2Bus_WrAck.
DuringtheentiretransactionfromBus2IP_WrReqtoIP2Bus_WrAck,thesignalBus2IP_SRAM_CEisheldhighasanenvelopingsignalaroundthetransaction.
Afteracompletedtransaction,theIPIFcanissueanewtransaction.
NotethatburstwritetransactionsonthebusareconvertedintoaseriesofsingledatatransferstotheIP,whichalllookalike.
Figure5-2:IPIFSimpleSRAMWriteCycleUG082_05_02_050406Bus2IP_AddrBus2IP_BEBus2IP_SRAM_CEBus2IP_WrReqLaterAckduetoIPresponseBus2IP_DataBus2IP_ClkIP2Bus_WrAckValidValidValidValidValidValid48www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter5:UsingIPIFtoBuildIPRBasicReadTransactionsFigure5-3diagramsareadtransaction,whichlooksverysimilartoawritetransaction.
AreadtransactionbeginswhentheIPIFdrivestheaddress(Bus2IP_Addr)andbyteenables(Bus2IP_BE)totheIP.
Itqualifiesthereadbyassertingasingleclockcyclehighpulse(Bus2IP_RdReq)atthebeginningofthetransaction.
ItthenwaitsfortheIPdevicetoacknowledgecompletionofthereadbysendingbackasingleclockcycleHighacknowledgepulseonIP2Bus_RdAck.
DuringtheentiretransactionfromBus2IP_RdReqtoIP2Bus_RdAck,thesignalBus2IP_SRAM_CEisheldhighasanenvelopingsignalaroundthetransaction.
Afteracompletedtransaction,theIPIFcanissueanewtransaction.
NotethatburstreadtransactionsonthebusareconvertedintoaseriesofsingledatatransferstotheIP,whichalllookalike.
IPIFStatusandControlSignalsExtrastatusandcontrolsignalsarealsopresentintheSRAMprotocol.
IftheIP2Bus_RetrysignalisassertedinsteadofIP2Bus_RdAck/IP2Bus_WrAck,theIPIFwillassertretryonthebussideandterminatethetransaction.
IP2Bus_ErrorassertedwithIP2Bus_RdAck/IP2Bus_WrAckwillcausetheIPIFtosignalanerroronthebusinterface.
ForslowIPdevices,anIP2Bus_ToutSupsignalcanbeassertedtopreventtimeoutsonthebusinterface.
FinallytheBus2IP_Resetpassesthebus-sideresettotheIP.
UsingIPIFtoCreateaGPIOPeripheralfromScratchAGeneralPurposeInput/Output(GPIO)peripheralcanbeusedtoshowhowtheIPIFsimplifiesnewperipheralcreation.
TheGPIOmodulehasthree32-bitregisters:oneregistertocontroltheTBUFforeachI/Opin,oneregistertowritetheI/Opins,andoneregistertoreadtheI/Opins.
TheGPIOperipheralusesaverysmallamountofadditional"controllogic"whenusedwitha32-BitIPIFSlaveSRAMmodule.
Figure5-4,page49showsaconceptualviewofthelogicnecessarytobuildtheGPIOmoduleusingtheIPIFSlaveSRAMmodule.
TheIP2Bus_RdAck/IP2Bus_WrAcksignalsaredirectlyconnectedtothecorrespondingBus2IP_RdReq/Bus2IP_WrReqsignals,sinceitonlytakesoneclockcycletoreadorwritetheGPIOregisters.
Ifmore"accesstime"isFigure5-3:IPIFSimpleSRAMReadCycleUG082_05_03_050406Bus2IP_AddrBus2IP_BEBus2IP_SRAM_CEBus2IP_RdReqLaterAckduetoIPresponseIP2Bus_DataBus2IP_ClkIP2Bus_RdAckValidValidValidValidValidValidML40xEDKProcessorReferenceDesignwww.
xilinx.
com49UG082(v5.
0)June30,2006UsingIPIFtoCreateaGPIOPeripheralfromScratchRrequiredbytheregisters,asimpleSRL16-basedshiftregisterbetweentheReq/Acksignalscouldbeusedtosetthenumberofcyclestheregisterwillrespondin.
Anexampleuseofthisfunctionistogaintimingmarginbytreatingtheregisteraccessasamulticyclepath.
ThissimpleenhancementtotheIPIFcanhaveverypositiveeffectsinmeetingthetimingrequirementstypicalofcomplexmicroprocessor-basedsystems.
Notethatregisterresponsetimecanbetuneddifferentlybetweenthereadandthewrite.
TodriveanexternalI/Opin,theoutputenableforthatpinmustbeasserted,allowingthepintobedrivenHighorLowbaseduponthecontentsofthewriteregister.
Iftheoutputenableforagivenpinisdeasserted,thepin'sdriverisputinahighimpedancestate,allowinganexternaldevicetodrivethepin.
TheCPUcansensethecurrentvalueofanypin(regardlessofitsdirection)byreadingthereadregister.
DrivingthedirectionoftheI/Opiniscontrolledbythecontentsofthethree-stateregister.
Figure5-4:IPIFSRAMModuletoGPIOLogicInterfaceDCQSCEDCQCEDCQCEDCQCEDCQCEDCQSCEDCQSCEDCQSCEDCQIPIFSlaveModuleOPB[8:15][0:7][0:7][8:15][16:23][24:31][0:7][8:15][16:23][24:31][24:31][16:23][8:15][0:7][24:31][16:23]WrReqBE[0]BE[1]BE[2]Addr[29]Addr[29]Addr[29]Addr[29]Addr[29]Addr[29]Addr[29]Addr[29][0:31][0:31]Addr[29]BE[3]BE[0]BE[1]BE[2]BE[3]WrReqWrReqWrReqWrReqWrReqWrReqWrReq10Bus2IP_ResetBus2IP_RdReqBus2IP_WrReqBus2IP_BE[0:3]Bus2IP_Data[0:31]Bus2IP_Addr[0:31]Bus2IP_ClkBus2IP_SRAM_CEIP2Bus_ToutSupIP2Bus_ErrorIP2Bus_RetryIP2Bus_RdAckIP2Bus_WrAckIP2Bus_Data[0:31]Bus2IP_ResetUG082_05_04_050406TIO50www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter5:UsingIPIFtoBuildIPRTheGPIOregisterssupportbyteenablesduringwritestothe32-bitregisters.
AsetofsimpleANDgatesisallthatisrequiredtogenerateaclockenabletotheregisters.
Four3-inputANDgatesareusedtodrivethefourbytesofthethree-statecontrolregister,andfourmore3-inputANDgatesareusedtodrivethefourbytesofoutput-pindata.
TheIPIFusesasetofuser-specifiedparametersthatallowcommonthings,suchasthebaseaddressoftheIP,tobeestablished.
Theseparametersarespecifiedbeforethesystemisimplementedinordertominimizethelogicareaandmaximizetheperformanceofthesystem.
NotethatintheGPIOexample,additionaldecodingisusedexternallytospecifytwodifferentmemorylocations.
OnelocationisusedforreadingfromorwritingtotheI/Opins(readregisterandwriteregistersharethesameaddress),andonelocationisusedfor3-statecontrol,readingandwritingtothebitthatcontrolstheToftheI/Opins.
UsingIPIFtoConnectaPre-ExistentPeripheraltotheBusOften,somelegacyIPneedstobebroughtintoamodernsystem.
ManyoftheselegacyIPsusesomeformofan8-bitmicroprocessorbus.
Typically,thismightconsistofafewaddresslines,an8-bitdatabus,areadandwritesignal,achipenable,aclock,areset,andperhapsaninterruptpin.
Inmostinstances,thiskindofIPcanbealmostdirectlyconnectedtotheIPIFSRAMmodule.
ThisparticularIPIFmodulewasactuallydesignedtoservethisverypurpose.
ToconnectalegacyIP,simplyconnecttheaddress,data,chipenable,clock,reset,andinterruptpinstotheircorrespondingversionsintheIPIFSRAMmodule.
Somesmallamountoflogicmightbeneededtogenerateaproperlytimedreadorwritesignal.
TheIPIFSRAMmoduleprovidesseparateReq/Ackpairsforreadandwrite,becausemanyolderperipheralsrequiredifferenttimingforreadsandwrites.
Forreadorwrite,thelogicbetweentheIPandtheIPIFmustaccomplishtwothings:ProvidetheproperresponsetimetotheIPIFsotheperipheral'sregistercanbereadorwrittenProvidetheproperrelationshipofthereadorwritesignalontheIPrelativetotheaddressanddataConsiderthefollowingexample:TheIPmightexpectitswritesignaltobevalidoneclockafteraddressanddataisvalidandbeheldforfourclockcyclestoproperlywritethedata.
Afterwritegoesinvalid,theaddressanddatamustbeheldforoneadditionalcycle.
Toaccommodatethiskindofpattern,asix-stageshiftregister(SR)canbeimplemented.
TheDinputtotheSRistiedtotheBus2IP_WrReqpin,andtheQoutputoftheSRistiedtotheIP2Bus_WrAckpinoftheIPIF.
Thisprovidesthepropertimingforthelengthoftimethecyclemustbeheldonthebus.
Byusingthefirst,second,third,andfourthtapsoftheSR,andfeedingthemintoanORgate,awritestrobecanbegeneratedfortheIP.
Ifthiswritestrobemustbeglitch-free,taps0,1,2,and3couldbeused,OR'ed,andfedintoasynchronizingregister.
XilinxFPGAsareabundantlyequippedwithflip-flops,sotheamountoflogicisnotanissue.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com51UG082(v5.
0)June30,2006ConclusionRConclusionUsingtheIPIFwithasmallamountoflogicmakesitveryeasytocreateCoreConnectdeviceswithlittleknowledgeofthebusesused.
ForcomplexbusessuchasPLB,thissavesthedesignertimeandhelpstoensureIPfunctionscorrectly,sincetheIPIFprovidesapre-verifieddesigntoconnectto.
TheGPIOdesignisjustoneexampleofhowIPIFcanbeused.
MoreexamplesofIPIFdesignsareprovidedwithinmanyoftheotherIPdevicesinthereferencesystems.
ThedesignerwhowantstolearnaboutIPIFshouldstudythesamplesourcecodeforsomeoftheseIPIF-baseddesignsincontextwithsimulationtogainexperiencewithIPIF.
TheIPIFusedintheML40xEmbeddedProcessorReferenceSystemcurrentlysupportsonlytheSRAMmodule.
AdditionalIPIFmodulesareavailablethroughEDKthatsupportmanyparameterizeablefeatures.
RefertotheIPIFchapteroftheProcessorIPReferenceGuidelocatedin/doc/proc_ip_ref_guide.
pdf.
Note:TheHardwareReferenceIPinthefollowingchaptersarebuiltusingIPIFmodulesconformingtoanearlierversionofthespecification.
PleaserefertotheIPIFchapteroftheProcessorIPReferenceGuide(locatedin/doc/proc_ip_ref_guide.
pdf)forthelatestinformationanddocumentationonIPIFcores.
NewdesignsshouldusetheseIPIFmodules,availablethroughEDK.
Forreference,theearlierversionoftheIPIFspecisavailableinChapter6ofXilinxUG057:ML300EDKReferenceDesignUserGuide.
52www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter5:UsingIPIFtoBuildIPRML40xEDKProcessorReferenceDesignwww.
xilinx.
com53UG082(v5.
0)June30,2006RChapter6OPBAC97SoundControllerOverviewThismoduleisanOn-ChipPeripheralBus(OPB)slavedevicethatisdesignedtocontrolanAC97AudioCodecchip.
Itprovidesasimplememory-mappedinterfacetocommunicatewiththehigh-speedserialportsoftheAC97Codec.
TheOPBAC97SoundControllermoduleallowsfullaccesstoallcontrolandstatusregistersintheAC97chipandprovidesdatabufferingforstereoplaybackandrecording.
RelatedDocumentsThefollowingdocumentsprovideadditionalinformation:IBMCoreConnect64-BitOn-ChipPeripheralBus:ArchitectureSpecifications,V2.
1Virtex-4PlatformFPGAs(DataSheets)IntelAudioCodec'97(AC97)Specificationhttp://www.
intel.
com/technology/computing/audio/index.
htmFeatures16-deepFIFObufferforrecordandplaybackdataCapableofgeneratinginterruptswhenplay/recordFIFOsreachgivenfullnessthresholds54www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter6:OPBAC97SoundControllerRModulePortInterfaceInformationaboutthesignals,pins,andparametersforthemoduleislistedintablesTable6-1,Table6-2,Table6-3,Table6-4,page55.
Table6-1:GlobalSignalsNameDirectionDescriptionOPB_ClkInputOPBsystemclockOPB_RstInputOPBsystemresetTable6-2:OPBSlaveSignalsNameDirectionDescriptionOPB_ABus[0:31]InputOPBaddressbusOPB_BE[0:3]InputOPBbyteenablesOPB_DBus[0:31]InputOPBdatabusOPB_RNWInputOPBread-not-writeOPB_selectInputOPBselectOPB_seqAddrInputOPBsequentialaddressOPB_AC97_CONTROLLER_DBus[0:31]OutputSlavedatabusOPB_AC97_CONTROLLER_errAckOutputSlaveerroracknowledgeOPB_AC97_CONTROLLER_retryOutputSlavebuscycleretryOPB_AC97_CONTROLLER_toutSupOutputSlavetime-outsuppressOPB_AC97_CONTROLLER_xferAckOutputSlavetransferacknowledgeTable6-3:ExternalI/OPinsNameDirectionDescriptionPlayback_InterruptOutputInterruptgeneratedwhenplaybufferfullnessisatorbelowprogrammedthreshold.
Record_InterruptOutputInterruptgeneratedwhenrecordbufferfullnessisatoraboveprogrammedthreshold.
Bit_ClkInputSerialBitClockfromAC97Codec.
SyncOutputFramesynchronizationsignaltoAC97Codec.
SData_OutOutputSerialDataoutputtoAC97Codec.
SData_InInputSerialDatainputfromAC97Codec.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com55UG082(v5.
0)June30,2006ModulePortInterfaceRTable6-4:Generics(Parameters)NameDefaultDescriptionC_OPB_AWIDTH32AddressbuswidthofOPB.
Shouldbesetto32.
C_OPB_DWIDTH32DatabuswidthofOPB.
Shouldbesetto32.
C_BASEADDRN/ABaseAddressofAC97SoundController.
Shouldbesetto256-byte(orhigherpowerof2)boundary.
C_HIGHADDRN/AEndAddressofAC97SoundController.
Shouldbesetto(BaseAddress+0xFF)orhigher.
TotalmemoryspacefromC_BASEADDRtoC_HIGHADDRmustbepowerof2.
C_PLAYBACK1PlaybackEnable.
Setto1toallowplayback.
Setto0toremoveplaybacklogic.
C_RECORD1RecordEnable.
Setto1toallowrecord.
Setto0toremoverecordlogic.
C_PLAY_INTR_LEVEL2SetsplaybackFIFOfullnessthresholdatwhichinterruptisgenerated:0=NoInterrupt1=emptyNumWords=02=halfemptyNumWords=84=fullNumWords=16C_REC_INTR_LEVEL3SetsrecordFIFOfullnessthresholdatwhichinterruptisgenerated:0=NoInterrupt1=emptyNumWords=02=halfemptyNumWords=84=fullNumWords=1656www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter6:OPBAC97SoundControllerRImplementationFigure6-1,page56showsablockdiagramoftheOPBAC97SoundController.
TheOPBAC97SoundControllermodulemanagesthreeprimaryfunctionstocontroltheAC97Codecchip.
IthandlestheplaybackFIFO,recordFIFO,andtheCodec'scontrol/statusregisters.
TheplaybackFIFOisa16-worddeepx16-bitwideFIFO.
Theplaybackdataisstoredbyalternatingbetweenleftandrightchanneldata(beginningwiththeleftchannel).
Thisallowsthe16-entryFIFOtostoreatotalofeightstereodatasamples.
SoftwareshouldbeinterruptdrivenandprogrammedtorefilltheplaybackFIFOafteraninterruptisreceivedstatingthattheFIFOisnearlyempty.
Ifoperatinginpolledmode,thesoftwareshouldpolltheplaybackFIFO-fullstatusbitandrefilltheFIFOwhenitisnotfull.
IftheplaybackFIFOgoesintoanunderruncondition(FIFOisemptyandCodecrequestsmoredata),anerrorflagbitisset.
IftheplaybackFIFOisunderrun,theFIFOmustberesettocleartheerrorflagandtoensureproperoperation.
TheFIFOthresholdatwhichaninterruptisgeneratedcanbesettooneoffourpossiblefullnesslevels.
TheOPBAC97controllerlogicautomaticallyhandlestheprocessofserializingtheleft/rightplaybackdataandsendingitouttotheCodecchipwhenrequested.
Figure6-1:OPBAC97SoundControllerBlockDiagramSData_InSData_OutParalleltoSerialSerialtoParallelSerialtoParallelParalleltoSerialParalleltoSerialPlaybackFIFORecordFIFOAC97CodecAC97InterfaceLogicCodecDataCodecControl/StatusRegisterOPBInterfaceLogic161616167161616167AddressWriteDataReadDataOPBOPBAC97SoundControllerUG082_06_01_050406MUXQDQDDQAC97ClockDomainOPBClockDomainML40xEDKProcessorReferenceDesignwww.
xilinx.
com57UG082(v5.
0)June30,2006MemoryMapRTherecordFIFOisa16-worddeepx16-bitwideFIFO.
Therecorddataisstoredinanalternatingfashionbetweenleftandrightchanneldata(beginningwiththeleftchannel).
Thisallowsthe16-entryFIFOtostoreatotalofeightstereodatasamples.
SoftwareshouldbeinterruptdrivenandprogrammedtoemptytherecordFIFOafteraninterruptisreceivedstatingthattheFIFOisnearlyfull.
Ifoperatinginpolledmode,thesoftwareshouldpolltheplaybackFIFO-emptystatusbitandgetdatafromtheFIFOwhenitisnotempty.
IftherecordFIFOgoesintoanoverruncondition(FIFOisfullandCodecsendsmoredata),anerrorflagbitisset.
IftherecordFIFOisoverrun,theFIFOmustberesettocleartheerrorflagandtoensureproperoperation.
TheFIFOthresholdatwhichaninterruptisgeneratedcanbesettooneoffourpossibleemptinesslevels.
TheOPBAC97controllerlogicautomaticallyhandlestheprocessofparallelizingtheleft/rightserialrecorddatathatisreceivedfromtheCodecchip.
TheplaybackandrecordFIFOsmustbeoperatedwiththesamesamplingfrequencybetweentheleftandrightchannels.
TheFIFOlogicdoesnotsupporttheleftandrightchannelsoperatingatdifferentfrequencies.
Accesstothecontrol/statusregistersintheCodecchipisperformedthroughasetofkeyholeregisters.
TowritetothecontrolregistersintheCodecchip,thewritedataandthentheaddresstobeaccessedarewrittentotworegistersintheOPBAC97controller.
ThiscausesthewritedatatobeserializedandsenttotheCodecchip.
Astatusbitsignalswhenthewriteiscomplete.
ReadingastatusregisterintheCodecchipisperformedinasimilarmanner.
ThereadaddressiswrittentotheOPBAC97controller.
ThiscausesareadcommandtobeserializedandsenttotheCodecchip.
WhentheCodecchiprespondswiththereaddata,astatusbitissetindicatingthatthereturndataisavailable.
Seethe"MemoryMap"sectionformoreinformationaboutusingtheseregisters.
TheBit_ClkfromtheAC97Codecchiptypicallyrunsatafrequencyof12.
288MHzwhiletheOPBclockrunswithatypicalfrequencyof50-100MHz.
Becauseoftheasynchronousrelationshipbetweenthesetwoclockdomains,theOPBAC97controllercontainsspeciallogictopassdatabetweenthesetwoclockdomains.
Inorderforthissynchronizinglogictofunctionproperly,itisimportantthattheOPBclockfrequencyisatleasttwotimeshigherthantheAC97Bit_Clkfrequency.
MemoryMapInformationaboutthememorymappedregistersisshowninTable6-5(whichspansmultiplepages).
Table6-5:MemoryMapRegisterAddressBitsRead/WriteDescriptionBaseAddress+0[16:31]WWrite16-bitdatasampletoplaybackFIFO.
Datashouldbewrittentwoatatimetowritedatatotheleftchannelfollowedbytherightchannel.
BaseAddress+4[16:31]RRead16-bitdatasamplefromrecordFIFO.
Datashouldbereadtwoatatimetogetdatafromtheleftchannelfollowedbytherightchannel.
58www.
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comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter6:OPBAC97SoundControllerRBaseAddress+8[24]RRecordFIFOOverrun:0=FIFOhasnotoverrun1=FIFOhasoverrunNote:RecordFIFOmustberesettoclearthisbit.
Afteranoverrunhasoccurred,theRecordFIFOwillnotoperateproperlyuntilitisreset.
[25]RPlayFIFOUnderrun:0=FIFOhasnotunderrun1=FIFOhasunderrunNote:PlayFIFOmustberesettoclearthisbit.
Afteranunderrunhasoccurred,thePlayFIFOwillnotoperateproperlyuntilitisreset.
[26]RCodecReady:0=Codecisnotreadytoreceivecommandsordata.
(Thiscanoccurduringinitialpower-onorimmediatelyafterreset.
)1=Codecreadytorun[27]RRegisterAccessFinish:0=AC97Controllerwaitingforaccesstocontrol/statusregisterinCodectocomplete.
1=AC97Controllerisfinishedaccessingthecontrol/statusregisterinCodec.
Note:Thisbitisclearedwhenthereisawritetothe"AC97ControlAddressRegister"(describedbelow).
[28]RRecordFIFOEmpty:0=RecordFIFOnotEmpty1=RecordFIFOEmpty[29]RRecordFIFOFull:0=RecordFIFOnotFull1=RecordFIFOFull[30]RPlaybackFIFOHalfFull:0=PlaybackFIFOnotHalfFull1=PlaybackFIFOHalfFull[31](LSB)RPlaybackFIFOFull:0=PlaybackFIFOnotFull1=PlaybackFIFOFullTable6-5:MemoryMap(Continued)RegisterAddressBitsRead/WriteDescriptionML40xEDKProcessorReferenceDesignwww.
xilinx.
com59UG082(v5.
0)June30,2006MemoryMapRBaseAddress+12[30]WClear/ResetRecordFIFO:0=DonotResetRecordFIFO1=ResetRecordFIFO.
ResettingtherecordFIFOalsoclearsthe"RecordFIFOOverrun"statusbit.
[31]WClear/ResetPlayFIFO:0=DonotResetPlayFIFO1=ResetPlayFIFO.
ResettingthePlayFIFOalsoclearsthe"PlayFIFOUnderrun"statusbit.
BaseAddress+16[24:30]WAC97ControlAddressRegister:Setsthe7-bitaddressofcontrolorstatusregisterintheCodecchiptobeaccessed.
Writingtothisregisterclearsthe"RegisterAccessFinish"statusbit.
[31]WAC97ControlAddressRegister:0=Performawritetotheaddressspecifiedabove.
Thewritedatacomesfromthe"AC97ControlDataWriteRegister"whichshouldbesetbeforehand.
1=Performsareadtotheaddressabove.
Writingtothisregisterclearsthe"RegisterAccessFinish"statusbit.
Thisbitisassertedhighwhentheoperationiscomplete.
BaseAddress+20[24:31]RAC97StatusDataReadRegister:ReturnsdatafromthestatusregisterintheCodecthatwasreadbythecommandabove.
Dataisvalidwhenthe"RegisterAccessFinish"flagisset.
BaseAddress+24[24:31]WAC97ControlDataWriteRegister:ContainsthedatatobewrittentothecontrolregisterintheCodec.
Thisregisterisusedinconjunctionwiththe"AC97ControlAddressRegister"describedabove.
Table6-5:MemoryMap(Continued)RegisterAddressBitsRead/WriteDescription60www.
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comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter6:OPBAC97SoundControllerRML40xEDKProcessorReferenceDesignwww.
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com61UG082(v5.
0)June30,2006RChapter7OPBPS/2Controller(Dual)OverviewThismoduleisanOn-ChipPeripheralBus(OPB)slavedevicethatisdesignedtocontroltwoPS/2devicessuchasamouseandkeyboard.
ItutilizestheXilinxIntellectualPropertyInterFace(IPIF)tosimplifyitsdesign.
TheOPBPS/2Controllermodulegeneratesinterruptsuponvarioustransmitorreceiveconditions.
ThisdocumentassumestheuserisalreadyfamiliarwiththePS/2interfaceprotocol.
AdditionalinformationaboutPS/2portsandperipheralsiswidelyavailableontheInternetorthroughacomputerhardwarereferencemanual.
RelatedDocumentsThefollowingdocumentsprovideadditionalinformation:IPIFSpecificationIBMCoreConnect64-BitOn-ChipPeripheralBus:ArchitectureSpecifications,V2.
1Virtex-4PlatformFPGAs(DataSheets)Features32-bitOPBslaveutilizinga32-bitIPIFSlaveSRAMinterfaceImplements8-bitread/writeinterfacefoundinmanyPCstocontroleachPS/2port62www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter7:OPBPS/2Controller(Dual)RModulePortInterfaceInformationaboutthesignals,pins,andparametersforthemoduleislistedintablesTable7-1,Table7-2,andTable7-3,page63.
Table7-1:OPBSlaveSignalsNameDirectionDescriptionIPIF_RstInputOPBsystemresetOPB_BE[0:3]InputOPBbyteenablesOPB_SelectInputOPBselectOPB_Dbus[0:31]InputOPBdatabusOPB_ClkInputOPBsystemclockOPB_Abus[0:31]InputOPBaddressbusOPB_RNWInputOPBreadnotwriteOPB_seqAddrInputOPBsequentialaddressSln_XferAckOutputSlavetransferacknowledgeSln_Dbus[0:31]OutputSlavedatabusSln_DBusEnOutputSlavedatabusenableSln_errAckOutputSlaveerroracknowledgeSln_retryOutputSlavebuscycleretrySln_toutSupOutputSlavetimeoutsuppressTable7-2:ExternalI/OPinsNameDirectionDescriptionSys_Intr1OutputInterrupt,Port#1Clkin1InputPS/2ClockIn,Port#1Clkpd1OutputPS/2ClockPulldown,Port#1Rx1InputPS/2SerialDataIn,Port#1Txpd1OutputPS/2SerialDataOutPulldown,Port#1Sys_Intr2OutputInterrupt,Port#2Clkin2InputPS/2ClockIn,Port#2Clkpd2OutputPS/2ClockPulldown,Port#2Rx2InputPS/2SerialDataIn,Port#2Txpd2OutputPS/2SerialDataOutPulldown,Port#2ML40xEDKProcessorReferenceDesignwww.
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com63UG082(v5.
0)June30,2006ModulePortInterfaceRTable7-3:ParametersNameDescriptionC_BASEADDR32-bitbaseaddressofPS/2controller(mustbealignedto8-KBboundary)C_HIGHADDRUpperaddressboundary,mustbesettovalueofC_BASEADDR+0x1FFF(8-KBboundary)64www.
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comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter7:OPBPS/2Controller(Dual)RImplementationFigure7-1showsablockdiagramoftheOPBPS/2Controllermodule.
ItusesanIPIFslavewithanSRAMinterfaceinadditiontosimplestatemachinesandshiftregisterstoimplementitsfunctionality.
EachPS/2portiscontrolledbyaseparatesetofeightbyte-wideregisters.
Fortransmittingdata,abytewritetothetransmitregistercausesthatdatatobeserializedandsenttothePS/2device.
Statusregistersandinterruptsthensignalwhenthetransmissioniscompleteandifthereareanyerrorsreported.
Similarly,receiverstatusregistersandinterruptssignalwhendatahasbeenreceivedfromthePS/2device.
Anyerrorswithreceiveddataarealsoreported.
ThePS/2controllercanbeoperatedinapolledmodeoraninterruptdrivenmode.
Intheinterruptdrivenmode,separateregisterbitsforsetting,clearing,andmaskingofindividualinterruptsareprovided.
BecausethePS/2interfaceusesanopencollectorcircuitfortransmittingdata,theoutputsignalsClkpdandTxpdshouldbetiedtoatransistororlogicgatecapableofpullingthe5VPS/2clockanddatasignalslow.
NotethatthePS/2protocolspecifies5Vsignalling.
Therefore,itisnecessarytohavetheproperinterfacecircuitrytopreventover-voltageconditionsontheFPGAI/O.
ConsulttheschematicsanddocumentationfortheXilinxML40xboardforanexampleimplementationofaPS/2portinterfacecircuit.
Figure7-1:OPBPS/2ControllerBlockDiagramMisccontrollogicTXStateMachineRXStateMachinePS2_1_DATA_OUTPS2_1_DATA_INPS2_1_CLK_OUTPS2_1_CLK_INPS2_2_DATA_OUTPS2_2_DATA_INPS2_2_CLK_OUTPS2_2_CLK_INUG082_07_01_050406ShiftRegistersandClockControlsMemoryMappedRegistersps2_reg.
vps2_sie.
vOPBSlaveIPIFMisccontrollogicTXStateMachineRXStateMachineShiftRegistersandClockControlsMemoryMappedRegistersps2_reg.
vps2_sie.
vOPBML40xEDKProcessorReferenceDesignwww.
xilinx.
com65UG082(v5.
0)June30,2006MemoryMapRMemoryMapInformationaboutthememorymappedregistersisshowninTable7-4.
Note:1.
Control/statusregistersforPS/2Port#1startatthebaseaddress(valueofparameterC_BASEADDR).
2.
Control/statusregistersforPS/2Port#2startatthebaseaddress+0x1000(valueofparameterC_BASEADDR+0x1000).
AllfieldsmarkedReservedreturnzero.
ThefieldinINTSTA(x10)isAND'edwiththefieldsinINTM(x18),thenthebitsgetOR'edtoformasingleInterruptsignal.
TheregisterpairsINTSTA/INTCLRandINTMSET/INTMCLRareimplementedtoallowsinglebitregisterupdateswhichreducethelatencyofinterrupthandling.
INTCLRandINTMCLRarehelperfunctionsthatmakesettingandclearingtheInterruptStatusRegisterandInterruptMaskRegisterfaster.
TheregisterdefinitionsareshowninTable7-5,page66(thistablespansseveralpages).
Note:ThesecondPS/2Porthasanidenticalsetofcontrol/statusregistersatanadditionaloffsetof0x1000.
Table7-4:MemoryMapTableOffsetBit0Bit1Bit2Bit3Bit4Bit5Bit6Bit7Bit8-31x00ReservedSRSTR*x04ReservedSTR.
6tx_full_staSTR.
7rx_full_staR*x08RXRR*x0cTXRR*x10ReservedINSTA.
2rx_fullINSTA.
3rx_errINSTA.
4rx_ovfINSTA.
5tx_ackfINSTA.
6tx_noackINSTA.
7wdt_toutR*x14ReservedINTCLR.
2rx_fullINTCLR.
3rx_errINTCLR.
4rx_ovfINTCLR.
5tx_ackfINTCLR.
6tx_noackINTCLR.
7wdt_toutR*x18ReservedINTMSET.
2rx_fullINTMSET.
3rx_errINTMSET.
4rx_ovfINTMSET.
5tx_ackfINTMSET.
6tx_noackINTMSET.
7wdt_toutR*x1cReservedINTMCLR.
2rx_fullINTMCLR.
3rx_errINTMCLR.
4rx_ovfINTMCLR.
5tx_ackfINTMCLR.
6tx_noackINTMCLR.
7wdt_toutR**R=Reserved66www.
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comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter7:OPBPS/2Controller(Dual)RTable7-5:OPBPS/2SlaveDevicePinDescriptionNameFieldNameBitDirectionDescriptionBaseAddress+0(Offsetx00)SRST7WSoftwareReset.
Writing'1'intothisregisterresultsinthePS/2controllerbeingresettoidlestate.
Also,registersatoffsetx04,x10,x14willberesetbythisbitaswell.
BaseAddress+4(Offsetx04)STR.
6tx_full_sta6RTXRegisterFull.
PS/2SerialInterfaceEngineisbusy.
ThisregistercanonlybemodifiedbyPS/2SIEhardware.
SoftwaredoesnothavedirectwritepermissiontochangethisfieldbecausethisfieldissetbythestatemachineintheSIE.
SoftwarecanclearthisfieldindirectlyisbyusingtheSRSTregister.
STR.
7rx_full_sta7RRXRegisterFull.
PS/2SerialInterfaceEnginereceivedabytepackage.
Theassociatedinterrupt"rx_full"(INTSTA.
3)willalsobeset.
SoftwaredoesnothavedirectwritepermissiontochangethisfieldsincethisfieldissetbythestatemachineintheSIE.
SoftwarecanclearthisfieldindirectlyisbyusingtheSRSTregister.
BaseAddress+8(Offsetx08)RXR[0:7]RRXreceiveddata.
BaseAddress+12(Offsetx0c)TXR[0:7]WTXtransmissiondata.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com67UG082(v5.
0)June30,2006MemoryMapRBaseAddress+16(Offsetx10)INSTA.
2rx_full2RInterruptStatusRegister-RXdataregisterfull.
ThisfieldisupdatedbythePS/2SerialInterfacewhentheSIEhasreceivedadatapacket.
Softwareclearsthisfieldbywritinga'1'intothecorrespondinginterruptclearregisterINTCLR.
2(offsetx14.
2)INSTA.
3rx_err3RInterruptStatusRegister-RXdataerror.
ThisfieldisupdatedbythePS/2SerialInterfacewhentheSIEhasfoundthatRXdataisabadpacket.
Softwareclearsthisfieldbywritinga'1'intothecorrespondinginterruptclearregisterINTCLR.
3(offsetx14.
3)INSTA.
4rx_ovf4RInterruptStatusRegister-RXdataregisteroverflow.
ThisfieldisupdatedbythePS/2SerialInterfacewhentheSIEoverwritesadatapacketbeforethepreviousdatawasread.
Softwareclearsthisfieldbywritinga'1'intothecorrespondinginterruptclearregisterINTCLR.
4(offsetx14.
4)INSTA.
5tx_ackf5RInterruptStatusRegister-TXacknowledgereceived.
ThisfieldisupdatedbythePS/2SerialInterfacewhentheSIEcompletestransmissionofadatabyteandhasreceivedacknowledgementfromthePS/2device.
Softwareclearsthisfieldbywritingan'1'intothecorrespondinginterruptclearregisterINTCLR.
5(offsetx14.
5)INSTA.
6tx_noack6RInterruptStatusRegister-TXacknowledgenotreceived.
ThisfieldisupdatedbythePS/2SerialInterfacewhentheSIEcompletestransmissionofadatabytebuthasnotyetreceivedacknowledgementfromthePS/2device.
Softwareclearsthisfieldbywritingan'1'intothecorrespondinginterruptclearregisterINTCLR.
6(offsetx14.
6)INSTA.
7wdt_tout7RInterruptStatusRegister-Watchdogtimertimeout.
ThisfieldisupdatedbythePS/2SerialInterfacewhentheSIEdoesnotreceiveaPS/2Clockwhileapacketisstillbeingtransmitted.
Softwareclearsthisfieldbywritingan'1'intothecorrespondinginterruptclearregisterINTCLR.
7(offsetx14.
7)Table7-5:OPBPS/2SlaveDevicePinDescription(Continued)NameFieldNameBitDirectionDescription68www.
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comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter7:OPBPS/2Controller(Dual)RBaseAddress+20(Offsetx14)INTCLR.
2rx_full2R*/WInterruptClearRegister-RXdataregisterfull.
Writinga'1'tothisfieldclearsINTSTA.
2.
Writinga'0'hasnoeffect.
INTCLR.
3rx_err3R*/WInterruptClearRegister-RXdataerror.
Writinga'1'tothisfieldclearsINTSTA.
3.
Writinga'0'hasnoeffect.
INTCLR.
4rx_ovfl4R*/WInterruptClearRegister-RXdataregisteroverflow.
Writinga'1'tothisfieldclearsINTSTA.
4.
Writinga'0'hasnoeffect.
INTCLR.
5tx_ack5R*/WInterruptClearRegister-TXacknowledgereceived.
Writinga'1'tothisfieldclearsINTSTA.
5.
Writinga'0'hasnoeffect.
INTCLR.
6tx_noak6R*/WInterruptClearRegister-TXacknowledgenotreceived.
Writinga'1'tothisfieldclearsINTSTA.
6.
Writinga'0'hasnoeffect.
INTCLR.
7wdt_toutl7R*/WInterruptClearRegister-Watchdogtimertimeout.
Writinga'1'tothisfieldclearsINTSTA.
7.
Writinga'0'hasnoeffect.
*IfsoftwaretriestoreadfromINTCLR(offsetx14),thevalueofINTSTA(offsetx10)isreturned.
BaseAddress+24(Offsetx18)INTMSET.
2rx_full2R*/WInterruptMaskSetRegister-RXdataregisterfull.
Writinga'1'tothisfieldsetsINTM.
2.
Writinga'0'hasnoeffect.
INTMSET.
3rx_err3R*/WInterruptMaskSetRegister-RXdataerror.
Writinga'1'tothisfieldsetsINTM.
3.
Writinga'0'hasnoeffect.
INTMSET.
4rx_ovf4R*/WInterruptMaskSetRegister-RXdataregisteroverflow.
Writinga'1'tothisfieldsetsINTM.
4.
Writinga'0'hasnoeffect.
INTMSET.
5tx_ack5R*/WInterruptMaskSetRegister-TXacknowledgereceived.
Writinga'1'tothisfieldsetsINTM.
5.
Writinga'0'hasnoeffect.
INTMSET.
6tx_noack6R*/WInterruptMaskSetRegister-TXacknowledgenotreceived.
Writinga'1'tothisfieldsetsINTM.
6.
Writinga'0'hasnoeffect.
INTMSET.
7wdt_tout7R*/WInterruptMaskSetRegister-Watchdogtimertimeout.
Writinga'1'tothisfieldsetsINTM.
7.
Writinga'0'hasnoeffect.
*IfsoftwaretriestoreadfromINTMSET(offsetx18),thevalueofINTMregisterisreturned.
Table7-5:OPBPS/2SlaveDevicePinDescription(Continued)NameFieldNameBitDirectionDescriptionML40xEDKProcessorReferenceDesignwww.
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com69UG082(v5.
0)June30,2006MemoryMapRBaseAddress+28(Offsetx1C)INTMCLR.
2rx_full2R*/WInterruptMaskClearRegister-RXdataregisterfull.
Writinga'1'tothisfieldclearsINTM.
2.
Writinga'0'hasnoeffect.
INTMCLR.
3rx_err3R*/WInterruptMaskClearRegister-RXdataerror.
Writinga'1'tothisfieldclearsINTM.
3.
Writinga'0'hasnoeffect.
INTMCLR.
4rx_ovf4R*/WInterruptMaskClearRegister-RXdataregisteroverflow.
Writinga'1'tothisfieldclearsINTM.
4.
Writinga'0'hasnoeffect.
INTMCLR.
5rx_ack5R*/WInterruptMaskClearRegister-TXacknowledgereceived.
Writinga'1'tothisfieldclearsINTM.
5.
Writinga'0'hasnoeffectINTMCLR.
6rx_noack6R*/WInterruptMaskClearRegister-TXacknowledgenotreceived.
Writinga'1'tothisfieldclearsINTM.
6.
Writinga'0'hasnoeffect.
INTMCLR.
7wdt_tout7R*/WInterruptMaskClearRegister-Watchdogtimertimeout.
Writinga'1'tothisfieldclearsINTM.
7.
Writinga'0'hasnoeffect.
*IfsoftwaretriestoreadfromIINTMCLR(offsetx1C),thevalueofINTM(offsetx18)isreturned.
Table7-5:OPBPS/2SlaveDevicePinDescription(Continued)NameFieldNameBitDirectionDescription70www.
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comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter7:OPBPS/2Controller(Dual)RML40xEDKProcessorReferenceDesignwww.
xilinx.
com71UG082(v5.
0)June30,2006RChapter8PLBTFTLCDControllerOverviewThePLBTFTLCDControllerisahardwaredisplaycontrollerfora640x480resolutionTFTorVGAscreen.
Itiscapableofshowingupto256KcolorsandisdesignedforaTFTdisplay,butcanalsobeusedfortheVGAportontheXilinxML40xboard.
ThedesigncontainsaPLBmasterinterfacethatreadsvideodatafromaPLBattachedmemorydevice(notpartofthisdesign)anddisplaysthedataontotheTFTscreen.
ThedesignalsocontainsaDeviceControlRegister(DCR)interfaceusedforconfiguringthecontroller.
RelatedDocumentsThefollowingdocumentsprovideadditionalinformationIBMCoreConnect32-BitDeviceControlRegisterBus:ArchitectureSpecificationsIBMCoreConnect64-BitProcessorLocalBus:ArchitectureSpecificationVirtex-4PlatformFPGAs(DataSheets)Features32-bitDCRslaveinterfaceforcontrolregisters64-bitPLBmasterinterfaceforfetchingpixeldataSupportforasynchronousPLBandTFTclocksModulePortInterfaceInformationaboutthesignals,pins,andparametersforthemoduleislistedinTable8-1,Table8-2,page72,Table8-3,page73,Table8-4,page73,andTable8-5,page74.
Table8-1:GlobalSignalsNameDirectionDescriptionSYS_dcrClkInputDCRSystemClockSYS_plbClkInputPLBSystemClockSYS_plbResetInputPLBSystemResetSYS_tftClkInputTFTVideoClock72www.
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comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter8:PLBTFTLCDControllerRTable8-2:PLBMasterSignalsNameDirectionDescriptionPLB_MnAddrAckInputPLBmasteraddressacknowledgePLB_MnBusyInputPLBmasterslavebusyindicatorPLB_MnErrInputPLBmasterslaveerrorindicatorPLB_MnRdBTermInputPLBmasterterminatereadburstindicatorPLB_MnRdDAckInputPLBmasterreaddataacknowledgePLB_MnRdDBus[0:63]InputPLBmasterreaddatabusPLB_MnRdWdAddr[0:3]InputPLBmasterreadwordaddressPLB_MnRearbitrateInputPLBmasterbusrearbitrateindicatorPLB_Mnssize[0:1]InputPLBslavedatabussizePLB_MnWrBTermInputPLBmasterterminatewriteburstindicatorPLB_MnWrDAckInputPLBmasterwritedataacknowledgePLB_pendPri[0:1]InputPLBpendingrequestpriorityPLB_pendReqInputPLBpendingbusrequestindicatorPLB_reqPri[0:1]InputPLBcurrentrequestpriorityMn_abortOutputMasterabortbusrequestindicatorMn_ABus[0:31]OutputMasteraddressbusMn_BE[0:7]OutputMasterbyteenablesMn_busLockOutputMasterbuslockMn_compressOutputMastercompresseddatatransferindicatorMn_guardedOutputMasterguardedtransferindicatorMn_lockErrOutputMasterlockerrorindicatorMn_msize[0:1]OutputMasterdatabussizeMn_orderedOutputMastersynchronizetransferindicatorMn_priority[0:1]OutputMasterbusrequestpriorityMn_rdBurstOutputMasterburstreadtransferindicatorMn_requestOutputMasterbusrequestMn_RNWOutputMasterread/notwriteMn_size[0:3]OutputMastertransfersizeMn_type[0:2]OutputMastertransfertypeMn_wrBurstOutputMasterburstwritetransferindicatorMn_wrDBus[0:63]OutputMasterwritedatabusML40xEDKProcessorReferenceDesignwww.
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com73UG082(v5.
0)June30,2006ModulePortInterfaceRTable8-3:DCRSlaveSignalsNameDirectionDescriptionDCR_ABus[0:9]InputDCRAddressBusDCR_DBusIn[0:31]InputDCRDataBusInDCR_ReadInputDCRReadStrobeDCR_WriteInputDCRWriteStrobeDCR_AckOutputDCRAcknowledgeDCR_DBusOut[0:31]OutputDCRDataBusOutTable8-4:ExternalOutputPinsNameDirectionDescriptionTFT_LCD_HSYNCOutputHorizontalSync(NegativePolarity)TFT_LCD_VSYNCOutputVerticalSync(NegativePolarity)TFT_LCD_DEOutputDataEnableTFT_LCD_CLKOutputVideoClockTFT_LCD_DPSOutputSelectionofScanDirectionTFT_LCD_R[5:0]OutputRedPixelDataTFT_LCD_G[5:0]OutputGreenPixelDataTFT_LCD_B[5:0]OutputBluePixelData74www.
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comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter8:PLBTFTLCDControllerRTable8-5:ParametersNameDefaultDescriptionC_DCR_BASEADDRN/ABaseaddressofDCRcontrolregisters.
MustbealignedonanevenDCRaddressboundary(leastsignificantbit=0).
C_DCR_HIGHADDRN/AUpperaddressboundary,mustbesettovalueofC_DCR_BASEADDR+1.
C_DEAFULT_TFT_BASE_ADDR[0:10]N/AMostsignificantbitsofbaseaddressforvideomemory.
The11mostsignificantbitsofthisaddressdefinethe2MBregionofmemoryusedforthevideoframestorage.
C_DPS_INIT1InitialresetstateofDPScontrolbit:0=DPSoutputbitresetsto0.
Thisinitializesthedisplaytouseanormalscandirection.
1=DPSoutputbitresetsto1.
Thisinitializesthedisplaytouseareversescandirection(rotatesscreen180degrees).
C_ON_INIT1InitialresetstateofTFTenable/disablebit:0=DisableTFTdisplayonreset.
Thiscausesablackscreentobedisplayedonreset.
1=EnableTFTdisplayonreset.
ThiscausesthePLBTFTLCDcontrollertooperatenormallyonreset.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com75UG082(v5.
0)June30,2006HardwareRHardwareImplementationFigure8-1showsahigh-levelblockdiagramofthedesign.
ThePLBTFTLCDControllerhasaPLBmasterinterfacethatreadspixeldatafromanexternalPLBmemorydevice.
Itreadsthepixeldataforeachdisplaylineusingaseriesof16-doublewordbursttransactions.
ThepixeldataisstoredinaninternallinebufferandthensentouttotheTFTdisplaywiththenecessarytimingtocorrectlydisplaytheimage.
ThevideomemoryisarrangedsothateachRGBpixelisrepresentedbya32-bitwordinmemory(see"MemoryMap,"page78).
Aseachlineintervalbegins,dataisfetchedfrommemory,buffered,andthendisplayed.
Thisprocessrepeatscontinuouslyovereverylineandframetobedisplayedonthe640x480VGATFTscreen.
ThebackendlogicdrivingtheTFTdisplayoperatesinthesameclockdomainasthevideoclock.
ItreadsoutdatafromthedualportlinebufferandtransmitsthepixeldatatotheTFT.
Thebackendlogicautomaticallyhandlesthetimingofallthevideosynchronizationsignals,includingbackporchandfrontporchblanking.
See"VideoTiming,"page76formoreinformation.
ThePLBTFTLCDControllerallowsforthePLBclockandTFTvideoclockstobeasynchronoustoeachother.
SpeciallogicallowscontrolsignalstobepassedbetweenasynchronousPLBandTFTclockdomains.
AdualportBRAMisusedasthelinebuffertopassvideodatabetweenthetwoclockdomains.
ItisimportanttodesignthesystemsothatthereissufficientbandwidthbetweenthePLBTFTLCDControllerandthePLBmemorydevicetomeetthevideobandwidthrequirementsoftheTFT.
Furthermore,theremustbeenoughavailablebandwidthremainingfortherestofthesystem.
Ifmorebandwidthisneededfortherestofthesystem,theTFTclockfrequencycanbereduced.
However,reducingtheTFTclockfrequencyalsolowerstherefreshrateofthescreen.
ThisleadstoanoticeableflickeronthescreeniftheTFTclockistooslow.
Figure8-1:High-LevelBlockDiagramUG082_08_01_0504061kBx18bitDualPortBRAMTFTInterfaceLogicSynchronizerColumnAddrRedDataGreenDataBlueDataColumnAddrGetLineVideoSignalstoTFTDisplayRedDataGreenDataBlueDataPLBInterfaceLogic(Master)PLBTFTClockDomainPLBClockDomain106661066676www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter8:PLBTFTLCDControllerRThePLBinterfacelogichastheabilitytoskipreadingalineofdataifitfailstofinishreadingdatafromapreviousline.
ThispreventstemporaryshortagesofavailablePLBbandwidthfromcausingthePLBTFTcontrollerfromlosingsynchronizationbetweenthePLBandTFTinterfacelogic.
NotethatextremeshortagesofavailablebandwidthforthePLBTFTcontrollercancausethescreentoappear"unstable"asstalelinesofvideodataaredisplayedonthescreen.
ADCRinterfaceallowssoftwaretochangethebaseaddressofvideomemorytobereadfrom.
Thisallowsframesofvideotobedrawninothermemorylocationswithoutbeingseenonthedisplay.
Thesoftwarecanthenchangethevideomemorybaseaddresstodisplayadifferentframewhenitisready.
TheDCRinterfacealsoallowsthedisplaytoberotatedby180degreesorturnedoff.
WhenthedisplayisturnedoffablackscreenisoutputwhilethePLBinterfacestopsrequestingdata.
VideoTimingThediagramsinFigure8-2throughFigure8-5describethetimingofvideosignalsfromthePLBTFTLCDController.
Figure8-2:HsyncandTFTClockFigure8-3:HorizontalDataUG082_08_02_050406th=800TFTClocks(Horizontal)Hsyncthp=96TFTClocksththpUG082_08_03_050406D(0,Y)thp=96TFTClocksthb=48TFTClocksDE=640TFTClocksthf=16TFTClocksthp112thbthf640CLK(Fixed)1CLKInvalidInvalidHsyncCLKDER0toR5G0toG5B0toB5D(1,Y)D(639,Y)ML40xEDKProcessorReferenceDesignwww.
xilinx.
com77UG082(v5.
0)June30,2006HardwareRFigure8-4:Vsyncandh_syncsUG082_08_04_050406tvp=2h_syncstv=525h_syncs(Vertical)VsyncDisplayperiodis480h_syncstvtvpFigure8-5:VerticalDataUG082_08_05_050406D(0,Y)tvp=2h_syncstvb=31h_syncsDE=640TFTClockstvf=12h_syncstvp1D(X,Y)D(X,0)D(X,479)123tvbtvf480H(Fixed)1HInvalidInvalidInvalidInvalidNote:X=0to639VsyncDER0toR5G0toG5B0toB5R0toR5G0toG5B0toB5HsyncD(1,Y)D(639,Y)D(638,Y)D(X,Y)DEDisplayperiodis480h_syncs78www.
xilinx.
comML40xEDKProcessorReferenceDesignUG082(v5.
0)June30,2006Chapter8:PLBTFTLCDControllerRMemoryMapVideoMemoryThevideomemoryisstoredina2MBregionofmemoryconsistingof1024datawords(1word=32bits)perlineby512linesperframe.
Ofthis1024x512memoryspace,onlythefirst640columnsand480rowsaredisplayedonthescreen.
Foragivenrow(0to479)andcolumn(0to639),thepixelcolorinformationisencodedasshowninTable8-6.
Table8-6:PixelColorEncodingPixelAddressBitsDescriptionTFTBaseAddress+(4096*row)+(4*column)[31:24]Undefined.
[23:18]RedPixelData:000000=darkest→111111=brightest[17:16]Undefined.
[15:10]GreenPixelData:000000=darkest→111111=brightest[9:8]Undefined.
[7:2]BluePixelData:000000=darkest→111111=brightest[1:0]Undefined.
ML40xEDKProcessorReferenceDesignwww.
xilinx.
com79UG082(v5.
0)June30,2006MemoryMapRControlRegisters(DCRInterface)TheregisterdefinitionsareshowninTable8-7.
Table8-7:ControlRegisters(DCRInterface)RegisterAddressBitsRead/WriteDescriptionDCRBaseAddress+0[31:0]RWBaseAddressofvideomemory.
ThisistheaddressofaPLBaccessiblememorydevicethatactsasthevideomemory.
Thisaddressmustbealignedona2MBboundary(i.
e.
,onlytheupper11bitsarewritableandtheremainingaddressbitsarealways0).
DCRBaseAddress+1[31:2]-Undefined.
[1]RWDPScontrolbit:0=SetDPSoutputbitto0.
Thissetsthedisplaytouseanormalscandirection.
1=SetDPSoutputbitto1.
Thissetsthedisplaytouseareversescandirection(rotatesscreen180degrees).
[0]RWTFTenable/disablebit:0=DisableTFTdisplay.
ThiscausesablackscreentobedisplayedanditdisablesthegenerationofPLBreadtransactions.
1=EnableTFTdisplay.
ThiscausesthePLBTFTLCDcontrollertooperatenormally.