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Zynq-7000AllProgrammableSoCZC702BaseTargetedReferenceDesign(ISEDesignSuite14.
4)UserGuideUG925(v3.
0)January31,2013Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com2UG925(v3.
0)January31,2013NoticeofDisclaimerTheinformationdisclosedtoyouhereunder(the"Materials")isprovidedsolelyfortheselectionanduseofXilinxproducts.
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Copyright2012,2013Xilinx,Inc.
Xilinx,theXilinxlogo,Artix,ISE,Kintex,Spartan,Virtex,Vivado,Zynq,andotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountries.
AMBA,AMBADesigner,ARM,ARM1176JZ-S,CoreSight,Cortex,andPrimeCellaretrademarksofARMintheEUandothercountries.
PCIExpressisatrademarkofPCI-SIGandusedunderlicense.
HDMI,HDMIlogo,andHigh-DefinitionMultimediaInterfacearetrademarksofHDMILicensingLLC.
Allothertrademarksarethepropertyoftheirrespectiveowners.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com3UG925(v3.
0)January31,2013RevisionHistoryThefollowingtableshowstherevisionhistoryforthisdocument.
DateVersionRevision06/21/121.
0InitialXilinxrelease.
10/08/122.
0UpdatedforISEDesignSuite14.
2.
ReplacedAXIVTCwithVTCthroughout.
ChangedSobelenginetoSobelfilter.
Chapter1,Introduction:AddedR,RW,COR,SoC,andSCtoTable1-1.
ExpandeddescriptionsoftheTRD.
UpdatedtheblockdiagraminFigure1-1.
Chapter2,FunctionalDescription:InFigure2-1,replacedthecontinuouslinewithadottedlineforMonitorandbetweenVIDEO_MUX0andClk_detectandrevisedAXIInterconnectinputs.
AddedsliceregisterstoTable2-1.
InTable2-2,changedSOBEL_ENGINEtoFILTER_VDMAandFILTER_ENGINE.
AddedFILTER_0_interruptrowinTable2-3,andSOBEL_VDMAchangedtoFILTER_VDMA.
InTable2-4,GPIObitnumber7becameN/A.
InPLClocks,page18,(FCLKCLK[3:0])became(FCLK_CLK).
InPLReset,page18,(FCLKRESETN[3:0])becameFCLK_RESET[3:0]_NandFCLKRESETN[0]changedtoFCLK_RESET0_N.
InClocking,page18,PSFCLKCLK[0]changedtoPSFCLK_CLK0.
InTable2-5,clocksignalsourcesanduseswereupdated.
InTable2-7,addedxFilter,changedfrequencyandconnectionofs_axi_CONTROL_BUS_ACLKanddeleteds_axi_SOBEL_CONTROL_ACLK.
ChangedfrequencyofINTERCONNECT_ACLKbus.
ChangedSOBEL_ENGINEtoFILTER_ENGINEandSOBEL_VDMAtoFILTER_VDMA.
AddedinformationtotheendofthetableforDVI2AXI_0,CRESAMPLE_0,andYUV2RGB_0components.
InProcessorSystemResetModule,page21,inputtotheproc_sys_resetcoreisgeneratedbyPSProc_sys_reset_1_N.
InClockDetect,page23,FMCchangedtoFMC-IMAGEON.
Thev_cresample,v_ycrcb2rgb,vsrc_sel,sobel_filter_top,anddvi2axisectionswereadded.
Startinginfmcimageonhdmiin,page25,YCbCrwaschangedtoYCrCb.
InFigure2-2,addedxFiltertotheDeviceDrivers.
IntheBootLoadersection,removed"HDMIin"chip.
InxFilter,page31,updatedtheintroductorytextforclarityandreformattedtheIOTCLarguments.
ModifiedthedescriptionofFigure2-4forclarity.
ModifiedthedescriptionsofFigure2-6andFigure2-7forclarityandaddeddescriptionofcases4,5,and6.
ModifiedSoftwareSobelFilterProcessing,page37forclarity.
AddedxFiltersectionstoXilinxLinuxKernel,page28.
Figure2-4,GUIforTRDApplicationwasreplacedandnotesabouttheGUIwereadded.
AXIwasaddedtothePlotGraphdescriptions.
DDR3wasremovedfromFigure2-6andFigure2-7.
TheSoftwareSobelFilterProcessing,page37descriptionandAPIchanged.
AppendixA,RegisterDescription:NewsectionswereaddedfromSobelFilterRegisters,page39totheendoftheappendix.
RemovedredundantinstancesofTPG.
AppendixB,DirectoryStructure:FigureB-1,DirectoryStructure,wasupdated.
AppendixD,AdditionalResources:PG012,LogiCOREIPChromaResamplerProductGuideandPG014,LogiCOREIPYCrCbtoRGBColor-SpaceConverterProductGuidewereaddedtoreferences.
AppendixE,RegulatoryandComplianceInformationwasadded.
AppendixF,Warrantywasadded.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com4UG925(v3.
0)January31,201311/12/122.
1UpdatedforISEDesignSuite14.
3.
Chapter1,Introduction:Documentandwebsitereferenceschangedthroughoutthebook.
InBaseTRDKeyFeatures,page10,1GBDDR3runningat533MHzwasremoved.
Chapter2,FunctionalDescription:Figure2-1linecolorschanged.
Table2-1cellvalueschanged.
Table2-2Peripheralnameschanged.
UnderClocking,page18,RGB2YUVblockwasremoved.
InTable2-6,theprocessorisps7_0,andPERF_MON_HP0,PERF_MON_HP2,VTC_0,andDVI2AXI_0sectionschanged.
Thedvi2axiConverterheadingchangedtodvi2axionpage25.
Figure2-4wasreplacedandaGUIexplanationadded.
Figure2-5wasaddedtoshowminimizedGUImode.
InsectionGraphicalUserInterface,page33,theFileBrowserandCommandLineShellparagraphswereremoved.
ThedirectorystructurechangedinFigureB-1.
AppendixD,AdditionalResources:Appendixwasreorganized.
AlinkwasaddedfortheMasterAnswerRecordfortheZC702board.
AppendixE,RegulatoryandComplianceInformation:ADeclarationofConformitylinkwasadded.
11/19/122.
1.
1Madetypographicaledits.
01/31/133.
0UpdatedforISEDesignSuite14.
4.
Chapter2,FunctionalDescription:Figure2-1waschangedinthePerformanceMonitorandTPG_0areas.
Table2-1changedUsed19,052to19,805,42to43,23,881to24,094,and%ofUsed35to37.
Table2-2,deletedPERF_MON_HP2rowandrenamednextrowtoPERF_MON_HP2_HP0_HP2.
APU,page16,endofCortex-A9Coresectionadded"ForthisTRD,bothARMcoresrunat667MHz.
"Table2-6,PERF_MON_HP0changedtoPERF_MON_HP0_HP2.
InthatsamesectionaddednewrowSLOT_1_AXI_ACLK1500Yesclk_150mhzandremovedPERF_MON_HP2section.
InTPG_0section,changedclktoaclk,148to150,video_clk_inttoclk_150mhz,S_AXI_ACLKtos_axi_aclk,andDVI2AXI_0sectiontoVID_IN_AXI4S.
ResetModulechangedtoProcessorSystemResetModule,page21.
AXIVDMAVideoDirectMemoryAccess,page21changedtoAXIVideoDirectMemoryAccess.
HeadingVTConpage22changedtoVideoTimingController.
Inthesamesection,VTCIPinlastparagraphchangedto"VideoTimingControllerIP.
"Addedfinalsentenceinthatsection"Fordetailedinformationon.
.
.
".
TheTPGsectionchangedtoTestPatternGenerator,page24.
SectionlogiCVC-ML,page24wasadded.
InAXIPerformanceMonitor,page25addedthefinalsentence,"Formoreinformation.
.
.
"InChromaResampler,page25editedthelastsentenceandadded"andlicensinginformation.
.
.
"AXIPerformanceMonitor,page25changedInstance:PERF_MON_HP0_HP2anddropped's'atInstance.
Thelastsentenceinthesamesectionchangedfrom"TwoAXIPerformanceMonitorsareinstantiated"to"TwoslotsofAXIPerformanceMonitorsareused.
"VideoMultiplexer,page26addedthefinalsentence"Fordetailedinformation.
.
.
"Thedvi2axisectiononpage25wasremoved.
Figure2-2changed"XilinxDMA"blockto"XilinxAXIVDMA.
"Table2-7changed"coreDMA"to"XilinxAXIVDMA.
"XVDMADriver,page30changed"XilinxDMA"to"XilinxAXIVDMA.
"XFILTER_STOP,page32bulletswitched"Ondemandmode"with"Continuousmode"inbothsentences.
Application,page32addedanewsentenceatend"TheLinuxkernelisinSMPmodeandboth.
.
.
"Figure2-4andFigure2-5werereplaced.
InControlandDecisionMaking,page35thebullet"SobelFilter(usingthexFilterdriver)"wasadded.
InUserSpaceDeviceControl,page36deleted"Sobelfilter"bullet.
DateVersionRevisionZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com5UG925(v3.
0)January31,201301/31/13,continued3.
0AppendixA,RegisterDescription:RemovedtheAXITPGRegisterssection.
ModifiedTableA-4andaddedarowforBitPosition7.
AppendixB,DirectoryStructure:ThedirectorystructureinFigureB-1changed.
AppendixD,AdditionalResources:AddedreferencesforPG043andPG103.
DateVersionRevisionZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com6UG925(v3.
0)January31,2013TableofContentsRevisionHistory3Chapter1:IntroductionTheBaseTargetedAPSoCReferenceDesign.
8BaseTRDKeyFeatures10Chapter2:FunctionalDescriptionHardwareArchitecture13SoftwareArchitecture27AppendixA:RegisterDescriptionClockDetectRegisters38SobelFilterRegisters39AppendixB:DirectoryStructureIncludedFilesandSystems42AppendixC:InstalltheZynq-7000APSoCDesignandDevelopmentEnvironmentInstalltheXilinxISEDesignSuite44SetUpLinuxSystemSoftwareDevelopmentTools.
44SetUpgitTools44AppendixD:AdditionalResourcesXilinxResources45SolutionCenters.
45FurtherResources45References47AppendixE:RegulatoryandComplianceInformationDeclarationofConformity.
48Directives48Standards48Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com7UG925(v3.
0)January31,2013Markings.
49AppendixF:WarrantyZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com8UG925(v3.
0)January31,2013Chapter1IntroductionThisuserguidedescribestheBaseTargetedReferenceDesign(TRD)basedonZynq-7000AllProgrammableSoC(APSoC)architecture.
TheTRDisincludedwiththeZC702evaluationkit.
TolearnmoreabouttheZC702evaluationkitandhowtoevaluatedifferentdemonstrationsbasedonZynq-7000APSoCarchitecture,refertoUG926,Zynq-7000AllProgrammableSoC:ZC702EvaluationKitandVideoandImagingKitGettingStartedGuide.
ThisdocumentexplainsthefunctionalarchitectureofthehardwareandsoftwarecomponentsoftheTRD.
AlsoprovidedareregisterdescriptionsforIP/logicimplementedinprogrammablelogic(PL),BaseTRDpackagedirectorystructure,andpointerstoenabletheusertofurtherdevelopembeddedplatformsbasedonZynq-7000APSoCarchitecture.
TobuildhardwareandsoftwarefortheBaseTRD,refertotheXilinxZynq-7000BaseTargetedReferenceDesignpagewiki.
xilinx.
com/zc702-base-trd.
TheBaseTargetedAPSoCReferenceDesignTheBaseTRDshowcasesvariousfeaturesandcapabilitiesoftheZynqAPSoCZ-7020devicefortheembeddeddomaininasinglepackageusingaXilinxstandardZynqLinux-basedvideopipelinedesign.
TheBaseTRDconsistsoftwoprocessingelements:TheZynq-7000APSoCprocessingsystem(PS)andavideoacceleratorbasedonPL.
TheAPSoCallowstheusertoimplementaspecificfunctionalityeitherasasoftwareprogramrunningontheZynq-7000APSoCPSorasahardwaredesigninsidethePL.
TheBaseTRDdemonstratesanoptimizationofhowtheusercanseamlesslyswitchbetweenasoftwareorahardwareimplementation,contributingtoeaseofuse.
TheTRDalsodemonstratesthevalueofoffloadingcomputation-intensivetasksontoPL,therebyfreeingtheCPUresourcesavailableforuser-specificapplications.
SoftwaredeveloperscanleveragetheBaseTRDandstartprogrammingrightawayusingthewidelyknownEclipse-basedintegrateddevelopmentenvironment(IDE),GNUcompilertoolchain,Linuxoperatingsystem(OS),andlibraries.
EmbeddedhardwaredesignersnowhaveimmediateaccesstotheindustrystandardARMCortex-A9coreprocessorsystemandvideoIPsrunningonPLoutofthebox.
Inaddition,theTRDalsoprovidescustomerswithaccesstothevariousPL-basedvideocomponentssuchasvideodirectmemoryaccessZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com9UG925(v3.
0)January31,2013TheBaseTargetedAPSoCReferenceDesign(VDMA),videotimingcontroller(VTC),videotestpatterngenerator(TPG),Sobelfilter,andtheXylonlogiCVC-MLdisplaycontroller[Ref1].
TheseIPsarepartofthevideopipelineimplementedinthePL.
TheBaseTRDconsistsofaPSbasedontheembeddedARMCortex-A9coreprocessor,avideoprocessingpipelineimplementedinPL,andaLinux-basedsoftwareapplicationthatincludesaQt-basedgraphicaluserinterface(GUI)[Ref2]toprovideusercontrolandmonitoring.
TheLinux-basedsoftwareplatformandsoftwareapplicationrunontheARMCortex-A9cores.
Thesoftwareapplicationworksintandemwithhardwareandprovidestheuserthechoiceofoffloadingcomputation-intensiveprocessingtothePL-basedhardwaresubsystem.
TheZynq-7000APSoCBaseTRDreferencedesign(Figure1-1)consistsofthesecomponents:AdualARMCortex-A9coreprocessor-basedembeddedLinuxOS,boardsupportpackage(BSP),andU-BootbootloaderPL-basedhardwareIPsthatenableaccelerationofcomputation-intensivevideoprocessingtasksLinux-basedapplicationsoftwarecomponentstoconfigureandcontrolthePL-implementedhardwareprocessingIPsandthedataflowbetweenPL-basedvideocomponentsandthePSZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com10UG925(v3.
0)January31,2013BaseTRDKeyFeaturesTheTRDdeliverablesincludesourcecodeforRTLdesignandsoftwarepackagessuchastheLinuxOS,devicedrivers,theapplication,andtheGUI.
Note:ThecamerasuppliedwiththevideokitisnotsupportedwiththeTRD.
BaseTRDKeyFeaturesComponentsintheBaseTRDarefurtherdescribedinthissection.
TheBaseTRDprocessingsystem(PS)includes:AdualARMCortex-A9coreARMAMBAAXIinterconnectMulti-protocol,32-bitDDRDRAMcontrollerStandardperipheralinterfacesincludingUSB,Ethernet,UART,I2C,SDMMC,andGPIOX-RefTarget-Figure1-1Figure1-1:Zynq-7000APSoCBaseTRDSystemBlockDiagramLinuxUserSpaceLinuxKernelProcessingSystemQt-BasedMultithreadedApplicationKernelLibrariesandUtilitiesDeviceDriversDDRMemoryControllerProgrammableLogicDisplayControllerVideoTestPatternGeneratorVideoOutputUG925_c1_01_080812S_AXI3_HP64bitM_AXI3_GP32bitVideoProcessing(SobelFilter)APUAMBASwitchesAMBASwitches(Optional)VideoInputwithZynq-7000VideoandImagingKitZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com11UG925(v3.
0)January31,2013BaseTRDKeyFeaturesBaseTRDprogrammablelogicincludes:TwoAXIinterconnects,64-bitwideat150MHzOneAXIinterconnect,32-bitwideat75MHzAXIVDMA(s)AfullHDvideoinputandoutputinterfaceASobelacceleratorTwoAXIPerformanceMonitorsBaseTRDsoftwareincludes:XilinxZynq-7000standardLinuxkernel(basedonOpenSourceLinux3.
x)LinuxdevicedriversforTRD-specificIPsQt-basedLinuxapplicationdemonstratingthevideoprocessingpipelineListofAcronymsTable1-1listsacronymsusedinthisdocument.
Table1-1:AcronymsAcronymDefinitionAFIAXIFIFOinterfaceAPUApplicationprocessorunitBSPBoardsupportpackageCORClearonreadDTBDevicetreebinaryDTSDevicetreesourceEDKEmbeddedDevelopmentKitAPSoCAllProgrammableSoCFMCFPGAmezzaninecardFPSFramespersecondFSBLFirst-stagebootloaderGICGeneralinterruptcontrollerGUIGraphicaluserinterfaceHDHighdefinitionIDEIntegrateddevelopmentenvironmentIOPInput/outputperipheralsIPIntellectualpropertyZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com12UG925(v3.
0)January31,2013BaseTRDKeyFeaturesKFLOPSkilofloating-pointoperationspersecondOCMOn-chipmemoryOSOperatingsystemPLProgrammablelogic(insidetheZynq-7000APSoC)PSProcessingsystemRReadonlyRTLRegistertransferlevelRWRead/WriteSCSelfclearSDSecureDigitalSDMMCSecureDigitalMultimediaCardSDKSoftwareDevelopmentKitSoCSystemonChipTDPTargetedDesignPlatformTPG(Video)TestPatternGeneratorTRDTargetedReferenceDesignTTCTriple-timercounterVDMAVideodirectmemoryaccessVTCVideotimingcontrollerXPSXilinxPlatformStudioZC702PlatformdevelopmentboardbasedontheZynqAPSoCZ-7020deviceZynqZ-7020AnimplementationoftheZynq-7000APSoCwithafixedfeaturesetandPLcapabilitiesTable1-1:Acronyms(Cont'd)AcronymDefinitionZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com13UG925(v3.
0)January31,2013Chapter2FunctionalDescriptionThischapterdescribestheZynq-7000APSoCZC702BaseTargetedReferenceDesign(TRD)hardwaredesign,softwaresystem,andvideodemonstrationapplicationcomponents.
ItalsodescribeshowdataflowsthroughthevariousconnectedIPsandincludesinformationabouttheflowofapplicationcontrol.
TobuildhardwareandsoftwarefortheBaseTRD,refertotheXilinxZynq-7000BaseTargetedReferenceDesignwikipagewiki.
xilinx.
com/zc702-base-trd.
HardwareArchitectureTheblockdiagramfortheBaseTRDisshowninFigure2-1.
Thisdesignhastwoparts:Processingsystem(PS)VideoIPsandcustomlogicimplementedinprogrammablelogic(PL)Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com14UG925(v3.
0)January31,2013HardwareArchitectureX-RefTarget-Figure2-1Figure2-1:Zynq-7000APSoCBaseTRDHardwareBlockDiagramUG925_c2_01_011813Bank0MIO(15:0)I/OPeripheralsFLASHMemoryInterfacesClockGenerationSPI0SPI1I2C0I2C1CAN0CAN1UART0UART1GPIOSD0SD1USB0USB1Enet0Enet1SRAM/NORNANDQuadSPIBank1MIO(53:16)InputClockandFreqExtendedMIO(EMIO)PStoPLClockPortsPSI2C-1(EMIO)I/OMUX(MIO)ResetProcessingSystem(PS)DAPDEVCIRQProgrammableLogictoMemoryInterconnectHighPerformanceAXI32b/64bSlavePortsMemoryInterfacesDDR2/3,LPDDR2ControllerSWDTTTCDMASChannelGICSnoopControlUnitMMUNEON/FPUEngineApplicationProcessorUnit(APU)32KBICache32KBDCacheCortex-A9MPCoreCPUMMUNEON/FPUEngine32KBICache32KBDCacheCortex-A9MPCoreCPUCoreSightComponentsSystemLevelControlRegsCentralInterconnectAXIInterconnectAXIInterconnect64bAXIACPSlavePortOCMInterconnect255KBOCM512KBL2CacheandControllerBootROM32bGPAXIMasterPorts32bGPAXISlavePorts121314158910114567012301230123SMMMMMMMMMSlaveSlaveAXIInterconnectSlaveSlaveMasterMasterPerfMonDMASyncLOGICVC_0TPGVDMAMM2SS2MMSobelVDMASobelFilterCRESAMPLE_0HDMI_INVideoIn1080pVideoOut1080pLocalPcoreEDKIPThirdPartyIPCOREGeneratorEDKIPAXIInterfaceVideoInterfaceAXIStreamingInterfaceS2MMMYUV2RGB_0VTC_0VIDEO_MUX_0Clk_detectVideoSyncSignalsMonitorTPG_0VID_IN_AXI4SZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com15UG925(v3.
0)January31,2013HardwareArchitectureThissystemisimplementedinaZynq-7000APSoCdevice(XC7Z020-CLG484-1)usingISEDesignSuite,version14.
3tools.
ThePLhardwareutilizationfortheimplementeddesignisshowninTable2-1.
ThePL-implementedvideoIPandcustomlogicaddressmapisshowninTable2-2.
SystemConfigurationProcessingSystemThisdesignmakesfulluseofthesefourmajorcomponentsinthePS:Applicationprocessorunit(APU)InterconnectInput/outputperipherals(IOP)Table2-1:PLHardwareUtilizationforDeviceXC7Z020-CLG484-1(1)FPGAComponentsTotalAvailableUsed%ofUsedLUTs53,20019,80537I/Os2004321FPGALogicMemoryRAMB36E11402115RAMB18E1280155Sliceregisters106,40024,09422Notes:1.
Thefiguresprovidedhereareonlyindicativeofnatureandcanvarybetweendifferenttoolchainversions.
Table2-2:FPGALogicAddressMapfortheZynq-7000APSoCZC702BaseTRDInstancePeripheralBaseAddressHighAddressCLK_DETECT_0clk_detect0x400600000x4006FFFFVTC_0axi_vtc0x400700000x4007FFFFTPG_0axi_tpg0x400800000x4008FFFFTPG_VDMAaxi_vdma0x400900000x4009FFFFFILTER_VDMAaxi_vdma0x400B00000x400BFFFFLOGICVC_0LogiCVC0x400300000x4003FFFFPERF_MON_HP0_HP2axi_perf_mon0x400F00000x400FFFFFCRESAMPLE_0v_cresample0x400400000x4004FFFFYUV2RGB_0v_ycrcb2rgb0x400500000x4005FFFFFILTER_ENGINEsobel_filter_top0x400D00000x400DFFFFZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com16UG925(v3.
0)January31,2013HardwareArchitectureMemoryinterfacesThissectiondescribessomeofthefeaturesofthePSusedinthisdesign.
Fordetailedinformationaboutthecompletefeaturesetincludingafunctionaldescription,seeUG585,Zynq-7000AllProgrammableSoCTechnicalReferenceManual.
APUTheAPUincludesthedualARMCortex-A9coreprocessor,snoopcontrolunit(SCU),L2cachecontroller,on-chipmemory(OCM),8-channelDMA,systemwatchdogtimer(SWDT),andtripletimercontroller(TTC)blocks.
Cortex-A9Core-TheARMCortex-A9coreprocessorimplementstheARMv7architectureandruns32-bitARMinstructions,16-bitand32-bitThumbinstructions,and8-bitJavabytecodesintheJazellestate.
ThemediaprocessingengineimplementsARMNEONcoprocessortechnology,asingleinstructionmultipledata(SIMD)architecturethataddsinstructionstargetedataudio,video,3Dgraphics,image,andspeechprocessing.
ForthisTRD,bothARMcoresrunat667MHz.
GeneralInterruptController-TheGICcollectsinterruptsfromvarioussourcesanddistributestheseinterruptstoeachoftheARMcores.
TheinterruptdistributorholdsthelistofpendinginterruptsforeachARMCortex-A9coreprocessorandthenselectsthehighestpriorityinterruptbeforeissuingittotheCortex-A9processorinterface.
InterruptsofequalpriorityareresolvedbyselectingthelowestID.
Atotalof64sharedperipheralinterrupts(PLinterrupts+PSI/Operipheralinterrupts)aresupported,startingfromID32.
Table2-3listsinterruptIDsforinterruptscomingfromPL.
InterconnectTheinterconnectunitconnectsallPSandPLmasterandslavedevices.
ThereareatotalofsixAdvancedeXtensibleInterface(AXI)slaveportsdedicatedforAXImastersresidinginthePL,andfouroftheseportscontaindeepFIFOstoimprovedatathroughput.
TwoAXImasterportsprovideaccesstoAXIslavesinthePL.
Inthisdesign,mastersinPLareconnectedthroughtwoAXIslaveportswithdeepFIFOs.
OneAXImasterportisusedtoaccessregistersinAXIslaveIPsinPL.
Anadvancedperipheralbus(APB)masterportisprovidedforaccessingsoftwareprogrammableregistersofallPSmodules.
ThetoplevelswitchisAXI3-compliant,thesoftTable2-3:InterruptIDsforPL-GeneratedInterruptsInterruptlineIDTypeInstanceCVC_DISPLAY_interrupt91LevelCVC_DISPLAYTPG_VDMA_s2mm_introut90LevelTPG_VDMAFIILTER_VDMA_s2mm_introut89LevelFIILTER_VDMAFIILTER_VDMA_mm2s_introut88LevelFIILTER_VDMAFILTER_0_interrupt87LevelFILTER_ENGINEZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com17UG925(v3.
0)January31,2013HardwareArchitectureIPsprovidedbyXilinxareAXI4-compliant,andthesoftAXIinterconnectIPprovidesprotocolbridgingasneeded.
S_AXI_HP-ThehighperformanceslaveAXIinterfaces(S_AXI_HP)connectthePLtoAFIblocksinthePS.
ThePLhasfourAXImastersoutofwhichtwoareconnectedtotheS_AXI_HP0portandtwoareconnectedtotheS_AXI_HP2port.
TheHPportenablesahighthroughputdatapathbetweenAXImastersintheprogrammablelogicandtheprocessingsystem'sDDR3memory.
ThemainaimoftheAXIFIFOinterface(AFI)unitsistosmoothoutthisvariablelatency,allowingtheabilitytostreamdatacontinuouslyfromDDRtothePLmastersandfromthePLmasterstoDDR.
ThePL-sideinterfaceofAFIrunsontheclockcomingfromthePL.
Inthisdesign,a150MHzclockisconnectedfromthePLside.
TheDDR-sideclockisrunningon2/3oftheDDR_CLK(533MHz).
ThehighperformanceAXIinterfacemoduleprovidesseveral"hooks"toassistinbandwidthmanagementofmastersconnectedtodifferentPLports.
ControllingissuancecapabilityavailablefromthePLportisoneofthehooksexercisedinthisdesigntoobtainafairshareofbandwidthbetweentwomasters,SOBELVDMA,andthedisplaycontroller.
M_AXI_GP-ThisAXImasterportinterfaceswithAXIslaveIPsinPLthroughanAXILiteinterconnect.
TheCPUmanagesinitializingandcontrollingthevideopipelinethroughthisport.
IOP-TheIOPunitincludescommunicationperipherals.
GPIO,Ethernet,USB,I2C,andSDcontrollersfromthePSareusedextensivelyinthisdesign.
GPIO-The64-bitgeneralpurposeinput/outputs(GPIOs)areconnectedtothePLthroughtheextendablemultiplexedI/O(EMIO)interface.
Sixty-fourbitsaredividedintotwobanks,eachof32bits.
BecauseeachGPIObitcanbedynamicallyconfiguredasinputoroutput,GPIObitsareusedinthisdesignforavarietyoffunctions.
Table2-4liststheGPIObitandpurposeindesign.
MemoryInterfacesThememoryinterfacesunitincludestheDDRmemorycontrollerandnonvolatilememorycontrollers.
TheDDRmemorycontrollerincludesa4-portarbiter.
OneAXIportisdedicatedforARMCPUaccessandtwoportsarededicatedforhighperformanceAXIinterfacemasterdevicesintheprogrammablelogic.
TheremainingportissharedbyallotherAXImasters.
InTable2-4:GPIOBitsFunctionalDescriptionGPIOBitNumberNetNamePurpose0ps7_0_GPIO_O[0]Resetsvideoreceivingblockdvi2axibridge1ps7_0_GPIO_O[1]ResetsSobelfilterblock3ps7_0_GPIO_O[3]Selectsalineforthevideomultiplexer—eithertheexternalvideosourceortheinternallygeneratedtestpattern6ps7_0_GPIO_O[6]FMC-IMAGEONI2Cmultiplexerreset2,4,5,7N/AN/AZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com18UG925(v3.
0)January31,2013HardwareArchitecturethisdesign,DDR3isconfiguredtorunat533MHz,andtheAXIinterfaceisrunningat355MHz.
PLClocksThePSprovidesfour(FCLK_CLK)fullyprogrammableclockstothePL.
TheseclocksarerouteddirectlytoPLclockbufferstoserveasafrequencysourceforthePL.
TheclockgeneratormoduleinPLgetsa100MHzclockfromFCLK_CLK0.
PLResetThePSprovidesfourFCLK_RESET[3:0]_NfullyprogrammableresetsignalstothePL.
ThesesignalsareasynchronoustoPSclocks.
ThePLlogicresetblockinthisdesignreceivesinputfromFCLK_RESET0_NandgeneratesnecessaryresetsignalsforthedesignimplementedinPL.
ProgrammableLogicClockingTheFPGAlogicdesignhasthreeclockdomains:AXIMM(memory-mapped)interconnect,AXIregisterinterface,andvideoclock.
Thesedomainsrunat150MHz,75MHz,and148.
5MHz,respectively.
Theclockgeneratormodulereceivesa100MHzinputclockfromthePSFCLK_CLK0andgenerates75MHzand150MHz.
TheAXILiteinterconnectworkson75MHz.
ApartfromtheAXILiteinterconnect,theregisterinterfaceofAXIVDMA,AXITPG,logiCVC-ML,VTC,perf_monitor,andclk_detectcoresaredrivenbythe75MHzclock.
TwoinstancesoftheAXI_MMinterconnectconnectedtotheHPportofthePSrunon150MHz.
TheS2MM(streamtomemorymap)andMM2S(memorymaptostream)channelsofVDMAsarerunningat150MHz.
The150MHzclockdrivesthelogiCVC-MLmemoryreadinterfaceandalsotheAXIslaveinterfaceoftheSobelfilter.
ThevideoclockcomesfromtheonboardclocksynthesizerorfromtheFMC-IMAGEONcard.
BUFGMUXdynamicallyselectswhichvideoclocksourcedriveslogicrunningonthevideoclockdomain.
TheAXITPG,VTC,dvi2axi,andlogiCVC-MLblocksrunonthevideoclock.
Table2-5listssystemclocks.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com19UG925(v3.
0)January31,2013HardwareArchitectureBasedonuserclockconfigurationinputs,theclockgeneratordeterminesthecorrectconfigurationofthePLLs.
Table2-6showsclockrequirementsofmasterandslaveperipheralsconnectedinsystemandtheirconnection.
Table2-5:SystemClocksClockSignalSourceFrequencyUseFPGA_CLKPS-FCLK_CLK0100MHzInputclocktoclockgeneratorclk_75mhzInternalmixed-modeclockmanager(MMCM)75MHzClockforAXILiteinterconnect,generatedbyclockgeneratorclk_150mhzInternalMMCM150MHzClockforAXIMMinterconnect,generatedbyclockgeneratorVIDEO_CLK_P,VIDEO_CLK_NExternaldifferentialvideoclockcomingfromclocksynthesizeronboard148.
5MHzClockfordisplaycontrollerandvideoreceivingblocksfmc_imageon_in_0_clk_pinExternalvideoclockcomingfromImageonFMC148.
5MHzClockforvideoreceivingmodulesTable2-6:PLClockConfigurationComponentFrequency(MHz)PhaseBufferedConnectionclock_generator_0CLKIN100YesFPGA_CLKCLKOUT075Yesclk_75mhzCLKOUT1150Yesclk_150mhzVIDEO_MUX_0video_clk_1148.
50YesVIDEO_CLKvideo_clk_2148.
50Yesfmc_imageon_hdmi_in_0_clk_pinvideo_clk148.
50Yesvideo_clk_intProcessorps7_0FCLK_CLK01000YesFPGA_CLKM_AXI_GP0_ACLK750Yesclk_75mhzS_AXI_HP0_ACLK1500Yesclk_150mhzS_AXI_HP2_ACLK1500Yesclk_150mhzBusesaxi4_0INTERCONNECT_ACLK1500Yesclk_150mhzZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com20UG925(v3.
0)January31,2013HardwareArchitectureaxi4_1INTERCONNECT_ACLK1500Yesclk_150mhzaxi4_liteINTERCONNECT_ACLK750Yesclk_75mhzPeripheralsproc_sys_reset_1Slowest_sync_clk750Yesclk_75mhzLOGICVC_0S_AXI_ACLK750Yesclk_75mhzmclk1500Yesclk_150mhzvclk148.
50YesVIDEO_CLKFILTER_ENGINESYS_CLK1500Yesclk_150mhzs_axi_CONTROL_BUS_ACLK1500Yesclk_150mhzSOBEL_SWRST_FFClk750Yesclk_75mhzFILTER_VDMAm_axi_mm2s_aclk1500Yesclk_150mhzm_axi_s2mm_aclk1500Yesclk_150mhzm_axis_mm2s_aclk1500Yesclk_150mhzs_axi_lite_aclk750Yesclk_75mhzs_axis_s2mm_aclk1500Yesclk_150mhzTPG_SWRST_FFClk750Yesclk_75mhzTPG_VDMAm_axi_s2mm_aclk1500Yesclk_150mhzs_axi_lite_aclk750Yesclk_75mhzs_axis_s2mm_aclk1500Yesclk_150mhzPERF_MON_HP0_HP2SLOT_0_AXI_ACLK1500Yesclk_150mhzSLOT_1_AXI_ACLK1500Yesclk_150mhzS_AXI_ACLK750Yesclk_75mhzCORE_ACLK1500Yesclk_150mhzVTC_0Table2-6:PLClockConfiguration(Cont'd)ComponentFrequency(MHz)PhaseBufferedConnectionZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com21UG925(v3.
0)January31,2013HardwareArchitectureProcessorSystemResetModuleInstance:proc_sys_reset_1Theproc_sys_resetmoduleimplementsaresetscheme.
Inputtotheproc_sys_resetcoreisgeneratedbyPSProc_sys_reset_1_N.
ThepolarityofinputresettothisblockisindicatedbyparameterC_EXT_RESET_HIGH.
Inthisdesign,C_EXT_RESET_HIGHissetto0asresetgeneratedbyPSisactive-Low.
Thisblockgeneratesvarioustypesofresets,suchasresetforinterconnect,peripheralreset,andsoon.
AlltheblocksinthePLaredrivenbyinterconnectreset,whichisactive-Lowinpolarity.
Fordetailedinformationaboutthecompletefeaturesetandafunctionaldescriptionoftheproc_sys_resetIP,refertoDS406,LogiCOREIPProcessorSystemResetModuleProductSpecification.
clk148.
50Yesvideo_clk_intS_AXI_ACLK750Yesclk_75mhzTPG_0aclk1500Yesclk_150mhzs_axi_aclk750Yesclk_75mhzCLK_DETECT_0DUT_CLK148.
50Yesvideo_clk_intS_AXI_ACLK750Yesclk_75mhzHDMI_INclk148.
50Yesfmc_imageon_hdmi_in_0_clk_pinVID_IN_AXI4Svid_in_clk148.
50Yesvideo_clk_intaclk1500Yesclk_150mhzCRESAMPLE_0aclk1500Yesclk_150mhzs_axi_aclk750Yesclk_75mhzYUV2RGB_0aclk1500Yesclk_150mhzs_axi_aclk750Yesclk_75mhzTable2-6:PLClockConfiguration(Cont'd)ComponentFrequency(MHz)PhaseBufferedConnectionZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com22UG925(v3.
0)January31,2013HardwareArchitectureAXIInterconnectInstances:axi4_0,axi4_1,axi4_liteFPGAlogicdesignhastwointerconnectsforAXImemory-mappedmastersandoneinterconnectfortheAXIregisterinterface.
AXImemory-mappedinterconnectsareconnectedtomasterslikeAXI_VDMAandlogiCVC-ML.
SlavesconnectedtotheseinterconnectsincludesHP0andHP2portsofZynq-7000APSoCPS.
Thisinterconnectoperatesat150MHzandthedatawidthis64-bitwide.
Theread/writeacceptanceandissuancearesetto8.
Theacceptanceandissuancehelpsimprovesystemperformance.
ThePSHPportcanacceptamaximumburstlengthof16.
Thisimposesalimitationongettingminimumacceptablebandwidthforeverymasterinamulti-mastersystem.
Theoptimumsettingofissuanceandacceptancereducesthrottleonthebusandcompensatesforlonglatencies.
TheAXIregisterinterfaceisclockedat75MHz.
TheZynq-7000APSoCPSGP0portactsasmasteronthisinterconnectandconnectedslaveshaveregistermaps.
AXITPGandVTCareexamplesofslavesconnectedtothisinterconnect.
TheoperationsofthevideopipelinearecontrolledbyregistersinsideeveryIP.
Dependingupondataflowrequiredinthevideopipeline,theprocessorwritestheseregistersthroughtheAXILiteinterconnect.
TheAXILiteinterconnectacceptswriteorreadtransfersfromtheCPU,performsaddressdecoding,selectsaparticularslave,andestablishesacommunicationchannelbetweentheCPUandtheslavedevice.
FordetailedinformationaboutthecompletefeaturesetandafunctionaldescriptionoftheAXIInterconnectIP,refertoDS768,LogiCOREIPAXIInterconnect.
AXIVideoDirectMemoryAccessInstances:TPG_VDMA,FILTER_VDMAAXIVDMAhasanAXIstreaminginterfaceononesideandanAXImemory-mappedinterfaceontheotherside.
TheVDMAhastwochannels:MM2S(memory-mappedtostreaming)andS2MM(streamingtomemory-mapped).
TheMM2SchannelreadsthenumberofdatabeatsprogrammedthroughtheC_MM2S_MAX_BURST_LENGTHparameterandpresentsittotheslavedeviceconnectedthroughthestreaminginterface.
Thedatawidthofthestreaminginterfacecanbedifferentthanthememory-mappedinterfaceandcontrolledthroughC_M_AXIS_MM2S_TDATA_WIDTH.
ThedatawidthoftheS2MMmemory-mappedinterfaceiscontrolledbytheC_M_AXI_MM2S_DATA_WIDTHparameter.
TheS2MMchannelreceivesdatafromthemasterdeviceconnectedthroughthestreaminginterface.
TheC_S_AXIS_S2MM_TDATA_WIDTHparameterdecidesthewidthofthestreaminginterface.
Datareceivedonthestreaminginterfaceisthenwrittenintothesystemmemorythroughthememory-mappedinterface.
TheC_M_AXI_S2MM_DATA_WIDTHparameterdecidesthedatawidthofthememory-mappedinterfaceandC_S2MM_MAX_BURST_LENGTHgovernstheburstlengthofthewritetransaction.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com23UG925(v3.
0)January31,2013HardwareArchitectureInthisdesign,thestreaminginterfacedatawidthissetto32-bitwideandthememory-mappedinterfaceisconfiguredas64-bitwide.
TheAXIVDMAisusedinsimpleregisterdirectmode,whichremovestheareacostofthescattergatherfeature.
Initialization,status,andmanagementregistersintheAXIVDMAcoreareaccessedthroughanAXI4-Liteslaveinterface.
TogetthebestpossiblethroughputforAXIVDMAinstances,themaximumburstlengthissetto16.
Inaddition,themasterinterfaceshaveareadandwriteissuanceof8andareadandwriteFIFOdepthof512tomaximizethroughput.
ThelinebuffersinsidetheAXIVDMAforthereadandwritesidesaresetto4KdeepandthestoreandforwardfeatureoftheAXIVDMAareenabledonbothchannelstoimprovesystemperformanceandreducetheriskofsystemthrottling.
FordetailedinformationonthecompletefeaturesetandafunctionaldescriptionofAXIVDMAIP,refertoPG020,LogiCOREIPAXIVideoDirectMemoryAccessProductGuide.
VideoTimingControllerInstance:VTC_0TheVTCisageneralpurposevideotiminggeneratoranddetector.
Theinputsideofthiscoreautomaticallydetectshorizontalandverticalsynchronizationpulses,polarity,blankingtiming,andactivevideopixels.
Thisinformationcanbeusedbyapplicationsoftwaretotakevariousdecisionsandforconfigurationofthevideopipeline.
Inthecurrentdesign,applicationsoftwaremeasuresresolutionofexternalvideoandthendecideswhethertoswitchtotheexternalvideosourceornot.
Thesamefeaturecanbeexpandedinthefuturetoconfigurethevideopipelinebasedoninputresolution.
Theoutputsideofthecoregeneratesthehorizontalandverticalblankingandsynchronizationpulses.
ThewidthandintervalofthesepulsesareconfiguredthroughtheAXILiteinterface.
TheAXITPGblockgeneratesavideotestpatternbasedonvideotimingpulsesgeneratedbyVTC.
Inthisdesign,VTCisusedtogeneratevideotimingsignalstomatchFullHD(1080p60)videoformat.
Thevideotiminggenerator/detectorblockandAXILiteinterfaceofthiscoreworkonasingleclockdomain,thatis,thevideoclock.
Fordetailedinformationonthecompletefeatureset,afunctionaldescription,andlicensinginformationforVideoTimingControllerIP,refertoPG016,LogiCOREIPVideoTimingControllerProductGuide.
ClockDetectInstance:CLK_DETECT_0Thevideopipelineinthisdesigncantakevideoinputeitherfromanexternalvideosourceorfromtheinternallygeneratedvideotestpattern.
ThereisapossibilitythattheuserselectsexternalvideomodeandtheFMC-IMAGEONisnotpresent.
Thisscenariocanleadtoapplicationfailureandmightdragthedesignintoanunrecoverablestate.
ThiscoregivesZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com24UG925(v3.
0)January31,2013HardwareArchitectureprovisiontotheapplicationtoavoidsuchascenario.
Thecoredeterminesthefrequencyoftheincomingvideosignal,andbasedonthisvalue,theapplicationdecideswhethertheincomingvideorateissuitablefortheapplication'sfunctioningornot.
ThemanagementandconfigurationofcoreiscontrolledthroughtheAXIregisterinterface.
ThesamplingdurationregisterholdsthenumberofcyclesforwhichtheinternalcyclecounterisOn.
Thiscorehastwocounters:ThesamplingcounterworksontheAXILiteclockandthecyclecounterrunsonthevideoclock.
BothcountersstartcountingaftertheENbitinthecontrolregisterisset.
Thesamplingcountergeneratesloadpulseuponreachingtheterminalcountspecifiedbythesamplingdurationregister.
Thecyclecounterstateisthenloadedintothecyclecounterregister.
BothcounterscleartheirstatesandstartcountingagainuntiltheENbitinthecontrolregisterissetto0.
Theregistervalueofthecyclecountcanbeusedbytheapplicationtodecidewhetheravideoclocksourceispresentornot,andifpresent,whatthefrequencyofthevideoclockis.
Thevalueofcyclecountreadfromtheregisteralsohelpsdeterminetheinputvideostandard,forexample,ifthecyclecountisaround25MHz,itisVGAmode.
Ifitis75MHz,itisinHDready(720p)mode,andif148MHz,itisFullHD(1080p).
TestPatternGeneratorInstance:TPG_0TheTestPatternGeneratorcontainsanAXIregisterinterfacetoaccessslavecontrolregistersfromaprocessor.
ThisIPcangeneratepatternslikecolorbars,horizontalandverticalburstpatterns,andzoneplates.
Thegenerationofpatterniscontrolledthroughthepatterncontrolregister.
Italsoenablestheoverlayofaboxonaselectedpattern.
Themotioncontrolregistercontrolsthespeedatwhichtheboxmovesoveraselectedpattern.
Inthisdesign,azoneplatepatternisusedwithamovingbox.
Thesizeofthezoneplateiscontrolledthroughzplatehdeltaandzplatevdeltaregisters.
Theboxsizeregistercontrolsthesizeofthebox,andthecoloroftheboxisselectedbytheboxcolorregister.
Thewidthandheightofthepatternisequalto1920x1080,selectedthroughthelinelengthandframeheightregister.
FordetailedinformationonthecompletefeaturesetandafunctionaldescriptionofTestPatternGenerator,refertoPG103,LogiCOREIPTestPatternGeneratorProductGuide.
logiCVC-MLInstance:LOGICVC_0ThelogiCVC-MLisamulti-layervideodisplaycontrollerfromXylon[Ref1].
ThelogiCVC-MLcontrollerrefreshesthedisplayimagebyreadingthevideomemoryandconvertingthereaddataintoadatastreamacceptableforthedisplayinterface.
Itgeneratescontrolsignalsforthedisplay,andsupportsmultiplelayerswithvideoprocessingfunctionssuchasalphablending,transparency,andmovearound.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com25UG925(v3.
0)January31,2013HardwareArchitectureFordetailedinformationaboutthecompletefeatureset,afunctionaldescription,andlicenseinformationforlogiCVC-MLIP,refertotheXylondatasheet[Ref1].
AXIPerformanceMonitorInstance:PERF_MON_HP0_HP2TheAXIPerformanceMonitorcanmonitorandanalyzesystembehaviorontheAXIinterface.
ThiscoreisusedintheBaseTRDtomeasurereadandwritethroughputonAXIslaveportsofthePS(HP0andHP2),whichareusedtoaccessDDRmemoryfromPL.
ThecoreconsistsoftheAXI4-Liteinterfacetoconfigureandcontrolthecore.
Thiscoreisconfiguredtomeasurethereadandwritethroughputbycountingthenumberoftransactionspersecond.
Whentheconfiguredtimeintervalexpires,measuredthroughputinbytesisloadedintoaregisterandreadbythesoftwareapplication.
TwoslotsofAXIPerformanceMonitorsareusedtomeasurereadandwritethroughputofHP0andHP2simultaneously.
FordetailedinformationonthecompletefeaturesetandafunctionaldescriptionofAXIPerformanceMonitor,refertoPG037,LogiCOREIPAXIPerformanceMonitorProductGuide.
fmcimageonhdmiinInstance:HDMI_INThisIPcorereceivesvideofromFMC-IMAGEON,inYCrCb4:2:2format,withembeddedvblankandhblanksignals,andextractsblankinginformation.
ChromaResamplerInstance:CRESAMPLE_0ThisIPisachromaresampler,whichisconfiguredtoconvertthevideofromYCrCb4:2:2toYCrCb4:4:4.
ThisIPhasanAXI4slaveinterfacetoconfigure,control,andreadstatusfromtheapplicationsoftware.
Fordetailedinformationonthecompletefeatureset,afunctionaldescription,andlicenseinformationforChromaResampler,refertoPG012,LogiCOREIPChromaResamplerProductGuide.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com26UG925(v3.
0)January31,2013HardwareArchitectureYCrCbtoRGBColor-SpaceConverterInstance:YUV2RGB_0ThisIPisacolorspaceconverter,whichconvertsthevideofromYCrCbtoRGBformatastherestofvideoIPsinthepipelineworkonRGBvideo.
ThisIPhasanAXI4slaveinterfacetoconfigure,control,andreadstatusfromtheapplicationsoftware.
Fordetailedinformationonthecompletefeatureset,afunctionaldescription,andlicenseinformationforYCrCbtoRGBColor-SpaceConverterIP,refertoPG014,LogiCOREIPYCrCbtoRGBColor-SpaceConverterProductGuide.
VideoMultiplexerInstance:VIDEO_MUX_0ThisIPmultiplexesthesyncsignalsfromtimebasegenerator(VTC_0)andfmc_imageon_hdmi_inandfeedstheVideoIntoAXI4-Stream(VID_IN_AXI4S).
TheselectionisdonebyPSGPIO(ps7_0_GPIO_O[3]).
FordetailedinformationonthecompletefeaturesetandafunctionaldescriptionofVideointoAXI4-StreamIP,refertoPG043,VideointoAXI4-StreamIPProductGuide.
SobelFilterInstance:FILTER_ENGINEThisIPhastheAXI4-LiteinterfacethroughwhichtheIPisconfiguredandcontrolled.
ThenumberofrowsandcolumnsareconfiguredusingAXIinterface,andthefilteringprocessstartswhentheStartregisteriswrittenthroughtheSobelinterface.
TheSobelfilterdetectstheedgeinthevideoframeandtheprocessedframeissentoutonAXIstreaminterface.
ThisIPgeneratesaninterruptafterprocessingeveryframe,thenthesoftwareinitiatestheprocessforthenextframebywritingtothecontrolregister.
VideoIntoAXI4-StreamInstance:VID_IN_AXI4SThisIPinterfacesavideosourcetotheAXI4-Streaminterface.
ItalsohandlesvideodataclockboundarycrossingbetweenthevideoclockdomainandAXI4-Streamclockdomain.
FordetailedinformationonthecompletefeaturesetandafunctionaldescriptionofVideointoAXI4-StreamIP,refertoPG043,VideointoAXI4-StreamIPProductGuide.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com27UG925(v3.
0)January31,2013SoftwareArchitectureSoftwareArchitectureThissectionexplainsthesoftwarearchitecturefortheZynq-7000APSoCZC702BaseTRD.
Figure2-2illustratesatoplevelviewofthesoftwarearchitecture.
Amulti-threadedLinuxapplicationisresponsibleforrunningtheTRDdemonstration.
ThisapplicationusestheQt-basedGUI,whichisdisplayedthroughDisplayMonitor,toobtainuserinputs.
Dependingontheinputs,itcallsdevicedriverstoconfigurethehardwareandtoenableaparticulardatapath.
ThreemajorsoftwarecomponentsareinvolvedintheBaseTRD:BootloaderXilinxLinuxkernelApplicationX-RefTarget-Figure2-2Figure2-2:SoftwareArchitecture:TopLevelViewUserSpaceLibrariesZynq-7000APSoCTRDApplicationCLibrariesFrameBufferUSBIICGPIODeviceDriversOSServicesProcessorSubsystemClockSynthesizerSobelFilterClockDetectorSobelVDMAVTCTPGTPGVDMALogiCVC-MLLinuxUserSpaceLinuxKernelHardwarexvdmaDirectHardwareAccessHWAccessXilinxAXIVDMASystemCallsandDriverInterfacesUG925_c2_02_011813xFilterZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com28UG925(v3.
0)January31,2013SoftwareArchitectureBootLoaderAtwo-stagebootloaderisusedfortheZynq-7000APSoCLinuxboot-up.
TheFSBLisresponsibleforinitializingrequiredhardwareandloadsthesecond-stagebootloader,U-Boot,whichisresponsibleforloadingkernelimageintheDDRmemory.
TheFSBLsourcecodeisgeneratedthroughtheXilinxSDKtool,dependingonthehardwaredesignspecification.
ThatsourcecodeismodifiedfortheBaseTRDtoinitializetheHDMIinandHDMIoutchips.
U-Bootisanopensourceuniversalbootloaderusedacrossvariousembeddedplatforms.
Thesourcecode,customizedforZynq-7000APSoCLinux,isavailableontheXilinxOpenSourceARMgitRepository:git.
xilinx.
com/.
RefertotheZynq-7000BaseTargetedReferenceDesignwikipage(wiki.
xilinx.
com/zc702-base-trd)tobuildtheFSBLandU-Boot.
XilinxLinuxKernelTheXilinxLinuxkernelisbasedonthemainlineopensourcekernelgittree,addingsupportforavarietyofXilinxIPcoredriversandreferenceboards.
ThesourcecodeisavailableontheXilinxOpenSourceARMgitRepository:git.
xilinx.
com/.
.
.
TheXilinxLinuxkernelisextended(patched)tosupportIPsspecifictothisBaseTRD.
PatchingandbuildingtheLinuxkernelisexplainedintheZynq-7000BaseTargetedReferenceDesignwikipageatwiki.
xilinx.
com/zc702-base-trd.
Table2-7listskerneldriversusedfortheBaseTRD.
AllofthedriversinTable2-7excepttheXVDMAandxFilterdriverscomewiththestandardXilinxLinuxkernel.
TheXVDMAandxFilterdriversarepatchedintothekernel.
Table2-7:LinuxKernelDriversUsedbytheBaseTRDLinuxDriverFunctionCalledByFramebufferDrivesthedisplaycontroller(logiCVC-ML)todisplaytheapplicationUIandcontroldatapathApplicationFramebufferFramebufferconsoledisplayLinuxconsolePS-GPIOProvidesResetsignalstoVDMAIPsApplicationXVDMAControlsVDMAIPforvariousdataflowsApplicationXilinxAXIVDMAProvidescoreAXIVDMAfunctionalityandtheactualhardwareinterfaceXVDMAdriverxFilterControlandconfigurefilterIP(Sobelfilter)ApplicationZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com29UG925(v3.
0)January31,2013SoftwareArchitectureFrameBufferDriverLinuxprovidesastandardframebuffer,whichishardware-independent,andtheapplicationcanusethisbufferwithoutknowingtheunderlyingdisplaycontroller.
TheXylonframebufferdriverforCVCIPisregisteredwiththestandardframebufferdrivertoprovidesupportforthelogiCVC-MLdisplaycontroller.
TheXylonframebufferdriveriscompiledwiththekernelandprobesforthehardwareandresolutionspecificationbyscanningthedtbfileatboot.
IfthereisnoentryforlogiCVC-MLIPinthedtbfile,thenthedriverdoesnotloaditself.
TheapplicationusesthestandardLinuxframebufferdriver,whichhasacharacterdriverinterface.
ForthisBaseTRD,/dev/fb0isthenodethatispopulated.
Tofindtheexactdevicenode,iterativelymatchtheidfieldofstructurefb_fix_screeninfoacquiredbytheFBIOGET_FSCREENINFOIOCTLcallforeachdevicenodepopulated.
IftheidfieldisXylonFB,theframebufferdriverisforXylonlogiCVC-ML.
Note:AnIOCTL(input/outputcontrol)isageneralpurposeLinuxsystemcallusedforimplementingtheinterfacebetweenauserapplicationandadevicedriver.
Moredetailsontheframebufferdriverisavailableinkerneldocumentationat/Documentation/fb/framebuffer.
txt.
PS-GPIODriverTheGPIOSYSFSinterfaceisusedforGPIOconfiguration.
TheGPIOSYSFSinterfaceallowstheusertocontrolI/Opinsusingfilesunderthe/sysdirectory.
Whenthesystemboots,allGPIOpinsareownedbythekernel.
ThepinsdonotshowupintheSYSFSsystemuntiltheyareexported.
Toexportthem,writethepinnumber(say54)tothefile/sys/class/gpio/export.
Thisresultsinthepseudofilesforpin54showingupunder/sys/class/gpio/gpio54as:/sys/class/gpio/gpio54/direction/sys/class/gpio/gpio54/valueTheusercansetthedirectionbywritinginorouttothedirectionfile.
Fortheoutdirection,writing0or1onthecorrespondingvaluefileresetsorsetsthepin,respectively.
Similarly,theusercanreadthevaluefilefortheindirection.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com30UG925(v3.
0)January31,2013SoftwareArchitectureXVDMADriverXVDMAisacharacterdriverusedforconfiguringandcontrollingvideoDMAtransactionsforbothTPGandSobelhardware.
XVDMAinternallycallstheXilinxAXIVDMAdrivertocompletethetaskandinterrupthandling.
ThedevicenodethatusestheXVDMAdriveris/dev/xvdma.
ThefollowingIOCTLsaredefinedfortheXVDMAdriverandcontainthecorrespondingIOCTLargumentstobeused:XVDMA_GET_NUM_DEVICES°ThiscallobtainsthenumberofVDMAprobedandavailableforuse.
°Argument:Addressofunsignedint[unsignedint*].
-ThisgetsfilledupwiththenumberofVDMAwhenthecallreturns.
XVDMA_GET_DEV_INFO°Thiscallgivesdeviceinformationlikechannelnumber,forthegivenVDMAID.
°Argument:Addressofstructurexvdma_dev[structxvdma_dev*].
-Beforecalling,thedevice_idfieldofthisstructureshouldbefilledwithVDMAID.
Onreturntherestofthestructureisfilledbythedriver.
XVDMA_DEVICE_CONTROL°ThiscallsetstheVDMAchannelconfiguration.
°Argument:Addressofstructurexvdma_chan_cfg[structxvdma_chan_cfg*].
-Beforecalling,thisstructureshouldbefilledwithrequiredchannelconfigurations.
-ToresetVDMA,onlyfillchan=andconfig.
reset=1fieldsofstructure.
XVDMA_PREP_BUF°Thiscallsetsthebufferconfigurations.
°Argument:Addressofstructurexvdma_buf_info[structxvdma_buf_info*].
-Beforecalling,thisstructureshouldbefilledwithrequiredbufferconfigurations.
XVDMA_START_TRANSFER°ThiscalltriggerstheVDMAtransfer.
°Argument:Addressofstructurexvdma_transfer[structxvdma_transfer*].
-Beforecalling,thisstructureshouldbefilled.
ThestructurespecifiesthechannelIDandwhetherthecallissynchronousorasynchronous.
XVDMA_STOP_TRANSFERZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com31UG925(v3.
0)January31,2013SoftwareArchitecture°ThiscallstopstheVDMA.
°Argument:Addressoftheunsignedintvariable[unsignedint*].
-Beforecalling,thisintvariableshouldbefilledwiththechannelID.
StructuresusedfortheaboveIOCTLaredefinedinthedriver_include.
hfile,whichispartoftheapplicationsourcecodeprovidedwiththeBaseTRD.
Thefilecontainscommentsexplainingeachfieldofthestructure.
XilinxAXIVDMAThisdriverisnotusedbytheapplication.
ItisinternallycalledbyXVDMAtoperformoperationsonvideoDMAhardware.
xFilterxFilterisacharacterdriverusedforconfiguringandcontrollingafilterIP,theSobelfilterinthiscase.
ThisdrivertakesinputfromthedtsfileforregistermapandinterruptID.
xFilterworksintwomodes—ContinuousmodeandOndemandmode.
InContinuousmode,afterthestartioctlcall(XFILTER_START)isissued,xFilterrunsuntilthestopioctlcall(XFILTER_STOP)isissued.
InOndemandmode,eachstartioctlcallrepresentsthefilteringofasingleframe.
Thestartioctlcallisalwaysasynchronous.
Theusercanconfirmcompletionofthefilteroperationonthecurrentframebycallingthewaitioctlcall(XFILTER_WAIT_FOR_COMPLETION),whichisablockingcall.
ThedevicenodethatusesthexFilterdriveris/dev/xfilter.
ThefollowingIOCTLsaredefinedforthexFilterdriverandcontainthecorrespondingIOCTLargumentstobeused:XFILTER_INIT°Initializestheresolutionandotherparametersforthefilter.
°Argument:AddressofstructurexFilterConfig[structxFilterConfig*]-Beforecalling,thisstructureshouldbefilledwithresolutionandfiltermodeinformation.
XFILTER_START°Startsthefilterengine-InContinuousmode,thiscallisautomaticallyrepeatedoneachframedoneinterruptuntiltheXFILTER_STOPcallismade.
-InOndemandmode,thiscallstartsthefilterengineforoneframe.
°Argument:NULLZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com32UG925(v3.
0)January31,2013SoftwareArchitectureXFILTER_STOP°StopsthefilterengineforContinuousmode.
ThiscallhasnoeffectforOn-demandmode.
-Afterthiscall,itismandatorytohavetheXFILTER_INITcallbeforedoingXFILTER_START°Argument:NULLXFILTER_WAIT_FOR_COMPLETION°InOndemandmode,thisblockingcallreturnsafterthecompletionofcurrentframeprocessing.
°Argument:NULLStructuresusedfortheaboveIOCTLaredefinedinthedriver_include.
hfile,whichispartoftheapplicationsourcecodeprovidedwiththeBaseTRD.
Thefilecontainscommentsexplainingeachfieldofthestructure.
ApplicationFigure2-3describesvariouscomponentsoftheapplication.
Theapplicationisdividedintothefollowingfunctionalblocks:X-RefTarget-Figure2-3Figure2-3:ApplicationFunctionalBlocksUG925_c2_03_061312UserSpaceDeviceControlPthreadLibrariesQtLibrariesControlandDecisionMakingGraphicalUserInterfaceSoftwareSobelFilterProcessingUserSpaceApplicationKernelSpaceDriversHardwareKernelDriverCallsKernelDriverCallsAccessingMemory-MappedHardwareHWAccessZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com33UG925(v3.
0)January31,2013SoftwareArchitectureGUIControlanddecisionmakingUserspacedevicecontrolSoftwareSobelfilterprocessingThefirstthreecomponentsruninonethreadoftheapplication,whilethesoftwareSobelfilterrunsinasecondseparatethread.
TheLinuxkernelisinSMPmodeandboththecoresareutilizedforrunningdifferentthreads.
Atruntime,thekernelassignsoneofthecoresforsoftwareSobelfilterprocessingandothercoreforrunningrestoftheapplicationandtheoperatingsystem.
GraphicalUserInterfaceTheGUIforthisBaseTRDisdesignedusingtheQtframework(seeFigure2-4).
InFigure2-4,thegreyscreenatthebottomistheGUI.
TheGUIcanbeminimizedormaximizedwiththeMIN/MAXbuttonontherightside.
ThecompletescreenistheVideo(ordisplay)area,wherethepatternorvideoisdisplayed.
ThereisaTransparencysliderthatmakestheGUIsemi-transparent.
ThebottomportionoftheGUIconsistsoftheZYNQX-RefTarget-Figure2-4Figure2-4:GUIforTRDApplicationUG925_c2_04_011813Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com34UG925(v3.
0)January31,2013SoftwareArchitecturebanner,apictorialviewofOperationModeandtwographs,whichareonlyavailableintheMAXGUImode.
AllothercontrolsareavailableinboththeMAXandMINGUImode.
Figure2-5showstheminimized(MIN)GUImode.
ThemainfunctionalityoftheGUIincludes:GettinguserinputsPlottinggraphsDisplayingthevideoareaGetUserInputsTheQtframeworkprovidesforhavingthemouseasinputdevice(itinternallyusesLinuxUSB-HIDclassdrivers).
TheinputfromtheuserincludesvideoEnable/Disable,InputSourceSelect,andModeSelectforthevideopipeline.
X-RefTarget-Figure2-5Figure2-5:MinimizedGUIModeUG925_c2_05_011813Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com35UG925(v3.
0)January31,2013SoftwareArchitecturePlotGraphTwographsareplottedusingtheQtframework.
ThefirstgraphdemonstratesCPUutilizationforeachARMcore,andtheseconddemonstratesAXImemorybandwidthutilizationonHP0andHP2portsIntheCPUutilizationgraph,thehorizontalaxisisfortimeandtheverticalaxisisforthepercentageofCPUutilization.
Inthememorybandwidthgraph,thehorizontalaxisisfortimeandtheverticalaxisisfortheGb/sofreadandwritetransactionsonAXI.
Alongwiththegraphs,theutilizationandbandwidthnumbersarealsodisplayedabovethegraphs.
ThesenumbersareavailableinbothMINandMAXGUImode.
DisplayVideoAreaThisisthefullscreenarea,wheretheoutputofthevideopipelineisdisplayed.
ControlandDecisionMakingThisblockreceivesinputfromtheGUIandmaintainsthestatetransitionforthecompleteapplication.
Itcommunicateswithallotherblocksoftheapplicationandwiththekerneldriverstochangethestateofhardware.
ThefollowinghardwareisconfiguredthroughthiscontrolblockusingthekerneldriversmentionedinXilinxLinuxKernel:VDMA(usingtheXVDMAdriver)VDMAresetandmultiplexerswitchingforexternalvideo(usingtheGPIOdriver)logiCVC-MLcontrol(usingtheframebufferdriver)SobelFilter(usingthexFilterdriver)SobelFilter(usingthexFilterdriver)DataFlowUseCasesThevideosourcecanbeeitherthevideoTPG(internal)oranexternalvideosource(HDMIIN).
Thesixcombinationsofdataflowusecasesarelistedbelow.
Usecases1,2,and3usetheTPGandusecases4,5,and6useexternalvideoasvideosource.
TheSobelfiltercaneitherbeasoftwareorhardwareimplementationoritisbypassedentirely(turnedoff).
Usecases1and4havethefilterturnedoff,usecases2and5refertothesoftwareimplementation,andusecases3and6refertothehardwareimplementation.
Figure2-6combinesTPG/externalvideoinonefunctionalblock.
Figure2-7combinessoftwareandhardwareimplementationinonefunctionalblock,therefore,usecases4,5,and6refertobothFigure2-6andFigure2-7.
Therearesixcombinationsofthedataflow:Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com36UG925(v3.
0)January31,2013SoftwareArchitecture1.
TheTPGcreatesandwritesthepatterninreservedvideomemoryinDDR.
Thedisplaycontrollerdisplaysvideomemory(TPGpattern)asshowninFigure2-6.
2.
Figure2-7showsthesoftwareSobelfilterconfiguration.
TheTPGcreatesandwritesthepatterninintermediateDDRmemory.
ThesoftwareSobelfilterreadstheintermediateDDRmemory,detectstheedges,andwritesthefilteredimageinthereservedvideomemoryinDDR.
Thedisplaycontrollerdisplaysvideomemory(filteredTPGpattern)asshowninFigure2-7.
3.
Figure2-7showsthehardwareSobelfilterconfiguration.
TheTPGcreatesandwritesthepatterninintermediateDDRmemory.
ThehardwareSobelfilterreadstheintermediateDDRmemory(usingVDMA),detectstheedge,andwritesthefilteredimageinthereservedvideomemoryinDDR(usingVDMA).
Thedisplaycontrollerdisplaysvideomemory(filteredTPGpattern).
Similarly,therearethreemorecases(4,5,and6)whereinsteadofaninternallygeneratedpattern,externalvideoisused.
SeeFigure2-6andFigure2-7withexternalvideo(HDMIIN)usedinsteadofTPGforthevideosource.
Cases4,5,and6arethesameascases1,2,and3withtheonlydifferencebeingtheinputsource.
Incases1,2,and3,theinputcomesfromTPG,whereasincases4,5,and6,theinputcomesfromexternalvideo.
UserSpaceDeviceControlAlltheIPsneednothaveakernelspacedriver,especiallywhentheyarememory-mappedanddonotuseinterrupt.
SuchIPscanbeconfiguredandcontrolledfromtheuserspacebymappingthephysicaladdressrangetothevirtualaddressspaceintheuserspace.
TheseIPsareconfiguredandcontrolledfromtheuserspace:TPGX-RefTarget-Figure2-6Figure2-6:VideoDisplayPipelineDataFlowX-RefTarget-Figure2-7Figure2-7:VideoProcessingandDisplayPipelineDataFlowUG925_c2_06_110412InternalVideoPattern(TPG)VideoMemoryDisplayControllerOutputtoMonitorUG925_c2_07_110412InternalVideoTPG/ExternalVideo(HDMIIN)VideoMemoryDisplayControllerSoftware/HardwareSobelFilterOutputtoMonitorIntermediateMemoryZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com37UG925(v3.
0)January31,2013SoftwareArchitectureClockdetectorVideotimingcontrollerTheAPIstoconfiguretheseIPsareexplainedintheudriver.
hfile,whichispartoftheapplicationsourcecodeprovidedwiththeBaseTRD.
SoftwareSobelFilterProcessingThissectiondescribestheimplementationofthesoftwareSobelfilteralgorithmforedgedetection.
ThealgorithmrunsinaseparatethreadandisturnedOnandOffbythecontrollingblock.
Theapplicationiscompiledwiththehighestcompileroptimizationlevel(O3),sothatthealgorithmgivesbestperformance.
Thisalgorithmtakesthebufferaddressoftheoriginalframeasinputandwritesthefilterimageonthebufferaddressprovidedasoutput.
ThefollowingAPIisusedforsoftwareSobelfilterprocessing:voidimg_process(ZNQ_S32*rgb_in_strm32,ZNQ_S32*rgb_out_strm32,intheight,intwidth,intstride);Anobject'sedgedetectionfilteralgorithmforimaging/videolooksforgradientmagnitudechangesintheimagebackgroundandprocessingisperformedinboththehorizontalandverticaldirections.
ThealgorithmtakestheRGBrawformattedimageanddetectstheimageobject'sedgesbasedonthepixelluminancevalues.
Input:ZNQ_S32*rgb_data_inTheimplementedSobelfilteralgorithmexpectseachpixelisa32-bitARGBintegerwitheachcoloras8-bitdepth.
ApointertotheARGBpixelarrayisprovidedonaperframebasis.
Output:ZNQ_S32*rgb_data_outTheimplementedalgorithmcomputeseachoutputpixel'svalueoftheframeusingtheSobelfilteredgedetectionalgorithm.
Thisfunctionreturnsa32-bitedge-detectedARGBarrayoftheframewitheachcoloras8-bitdepth.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com38UG925(v3.
0)January31,2013AppendixARegisterDescriptionThisappendixdescribesthedetailsaboutconfigurationandcontrolregistersmostcommonlyaccessedbytheLinuxdriverandapplication.
Theregistersimplementedinhardwarearememory-mappedtothePSaddressrangedirectly.
ClockDetectRegistersTheclockdetector'sregistersareusedtodetectthevideoclock.
EventCountEnableRegisterTherelativeaddressoftheclockdetector'seventcountenableregisteris0x00.
TableA-1describesthisregister'sstructure.
ClockCountRegisterTherelativeaddressoftheclockdetector'sclockcountregisteris0x08.
TableA-2describesthisregister'sstructure.
Baseaddress0x40060000Version2.
0.
0aRelativeaddress0x00TableA-1:EventCountEnableRegisterBitPositionModeDefaultValueDescription31:1--Reserved0RW0x0EventcountenableRelativeaddress0x08Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com39UG925(v3.
0)January31,2013SobelFilterRegistersEventDurationRegisterTherelativeaddressoftheclockdetector'seventdurationregisteris0x18.
TableA-3describesthisregister'sstructure.
SobelFilterRegistersTheSobelfilterregistersareusedtoconfigureandcontrolvariousinternalfeatureswithintheSobelfilterlogic.
ControlandStatusRegisterTherelativeaddressoftheControlandStatusregisteris0x00.
TableA-4describesthisregister'sstructure.
TableA-2:ClockCountRegisterBitPositionModeDefaultValueDescription31:0R0x0ClockcountervalueRelativeaddress0x18TableA-3:EventDurationRegisterBitPositionModeDefaultValueDescription31:0RW0x0Afterreachingthisvalue,theeventcounterstartsre-countingfromzero.
Duringthere-count,theclockcounterisenabled.
Baseaddress0x400D0000VersionN/ARelativeaddress0x00TableA-4:ControlandStatusRegisterBitPositionModeDefaultValueDescription31:8-6:3--Reserved.
7RW0x0AutoRestart2R0x1IPisidle.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com40UG925(v3.
0)January31,2013SobelFilterRegistersGlobalInterruptEnableRegisterTherelativeaddressoftheGlobalInterruptEnableregisteris0x04.
TableA-5describesthisregister'sstructure.
InterruptEnableRegisterTherelativeaddressoftheInterruptEnableregisteris0x08.
TableA-6describesthisregister'sstructure.
InterruptStatusRegisterTherelativeaddressoftheInterruptStatusregisteris0x0C.
TableA-7describesthisregister'sstructure.
1COR0x0Frameprocessisdone.
0RW/SC0x0Startprocessingtheframe.
Relativeaddress0x04TableA-5:GlobalInterruptEnableRegisterBitPositionModeDefaultValueDescription31:1--Reserved.
0RW0x0Globalinterruptenable.
Relativeaddress0x08TableA-6:InterruptEnableRegisterBitPositionModeDefaultValueDescription31:1--Reserved.
0RW0x0Frameprocessingdoneinterruptenable.
Relativeaddress0x0CTableA-4:ControlandStatusRegister(Cont'd)BitPositionModeDefaultValueDescriptionZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com41UG925(v3.
0)January31,2013SobelFilterRegistersNumberofRowsRegisterTherelativeaddressoftheNumberofRowsregisteris0x14.
TableA-8describesthisregister'sstructure.
NumberofColumnsRegisterTherelativeaddressoftheNumberofColumnsregisteris0x1C.
TableA-9describesthisregister'sstructure.
TableA-7:InterruptStatusRegisterBitPositionModeDefaultValueDescription31:1--Reserved.
0RW0x0Frameprocessingdoneinterruptstatus.
Relativeaddress0x14TableA-8:NumberofRowsRegisterBitPositionModeDefaultValueDescription31:0RW-Numberofrowsinaframe.
Relativeaddress0x1CTableA-9:NumberofColumnsRegisterBitPositionModeDefaultValueDescription31:0RW-Numberofcolumnsinaframe.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com42UG925(v3.
0)January31,2013AppendixBDirectoryStructureThisappendixdescribesthedirectorystructureandorganizationofthefilesandfoldersdeliveredwiththepackage.
IncludedFilesandSystemsFigureB-1givesatoplevelviewofthedirectoriesandfilesincludedintheZynq-7000APSoCZC702BaseTRDpackage.
TableB-1summarizeshowthedirectoriesprovidedrelatetothisuserguide.
ThisuserguideusesthedirectoriesintheextractedBaseTRDzippedpackageandassumesthatthedirectoriesandfilesareplacedorcopiedontotheuser'slocalcomputer.
X-RefTarget-FigureB-1FigureB-1:DirectoryStructureUG925_aB_01_011813Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com43UG925(v3.
0)January31,2013IncludedFilesandSystemsTableB-1:ExplanationofDirectoriesintheZynq-7000APSoCZC702BaseTRDFileSystemDirectoryPurposedocThisdirectorycontainsthedocumentsprovidedwiththeZynq-7000APSoCZC702BaseTRD,includingthisuserguide.
sd_imageThisdirectorycontainsapre-builthardwaredesignandsoftwareexecutableswhichprovideaquickwaytorunthevideodemonstration.
TheapplicationbinaryimagesarecompatibletobootfromtheSDMMCandruntheLinuxapplication.
hwThisdirectoryincludestheZynq-7000APSoCZC702BaseTRDhardwaredesign.
swThisdirectoryincludestheBaseTRDapplicationssourcecodeandhardwareplatformexportedfromthePlanAheadtool.
TheincludedISE-SDKprojectcanbeusedtobuildtheapplication.
boot_imageThisdirectoryincludesthehardwaredesignbitfileandotherZynq-7000systemconfigurationexecutablesinbinary.
patchesThisdirectoryincludesBaseTRDLinuxpatchestotheXilinxstandardZynq-7000APSoCLinuxkernel.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com44UG925(v3.
0)January31,2013AppendixCInstalltheZynq-7000APSoCDesignandDevelopmentEnvironmentInstalltheXilinxISEDesignSuiteTheuserneedstoinstalltheEmbeddedEditionandSystemEditionofXilinxISEDesignSuite.
RefertoUG798,XilinxDesignTools:InstallationandLicensingGuidetoinstallandlicenseISEDesignSuite.
SetUpLinuxSystemSoftwareDevelopmentToolsTodownloadandsetuptheARMGNUtoolchainfortheZynq-7000APSoCLinuxsystemsoftwareandapplicationdevelopment,refertotheXilinxARMGNUToolswikiatwiki.
xilinx.
com/zynq-tools.
Thetoolsuitedownloadrequiresavalid,registeredXilinxuserloginnameandpassword.
SetUpgitToolsGitisafreesoftwaretoolformanagingdistributedversioncontrolandthedevelopmentofsoftwareprojectfiles.
Agitcloneisafull-fledgedrepositorywithcompletehistoryandfullrevisiontrackingcapabilities.
Gitgivesthedeveloperalocalcopyoftheentiredevelopmentprojectfilesandtheirexisting(published)historyonagitserverwithinarepositoryorganizedasasetofdirectories.
Ausermustcloneafileorfolderbeforeusingthesameitemsfromtheprojectrepository.
TheuserneedstohaveagitclientinstalledontheLinuxdevelopmentPC.
RefertotheUsingGitwebsitewiki.
xilinx.
com/using-gitforworkingwithXilinxgitandtosection5.
1ofUG821,Zynq-7000AllProgrammableSoCSoftwareDevelopersGuideforworkingwithXilinxgitLinuxrepositories.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com45UG925(v3.
0)January31,2013AppendixDAdditionalResourcesXilinxResourcesForsupportresourcessuchasAnswers,Documentation,Downloads,andForums,seetheXilinxSupportwebsiteat:www.
xilinx.
com/support.
Forcontinualupdates,addtheAnswerRecordtoyourmyAlerts:www.
xilinx.
com/support/myalerts.
ForaglossaryoftechnicaltermsusedinXilinxdocumentation,see:www.
xilinx.
com/company/terms.
htm.
SolutionCentersSeetheXilinxSolutionCentersforsupportondevices,softwaretools,andintellectualpropertyatallstagesofthedesigncycle.
Topicsincludedesignassistance,advisories,andtroubleshootingtips.
FurtherResourcesThemostuptodateinformationrelatedtotheZC702boardanditsdocumentationisavailableonthefollowingwebsites.
TheXilinxZynq-7000SoCZC702EvaluationKitProductPage:www.
xilinx.
com/zc702TheZynq-7000SoCZC702EvaluationKitMasterAnswerRecord:www.
xilinx.
com/support/answers/47864.
htmZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com46UG925(v3.
0)January31,2013FurtherResourcesTheseXilinxdocumentsprovidesupplementalmaterialusefulwiththisguide:UG926,Zynq-7000AllProgrammableSoC:ZC702EvaluationKitandVideoandImagingKitGettingStartedGuideZynq-7000AllProgrammableSoC:ZC702EvaluationKitandVideoandImagingKitGettingStartedGuideUG585,Zynq-7000AllProgrammableSoCTechnicalReferenceManualDS406,LogiCOREIPProcessorSystemResetModuleProductSpecificationDS768,LogiCOREIPAXIInterconnectPG020,LogiCOREIPAXIVideoDirectMemoryAccessProductGuidePG037,LogiCOREIPAXIPerformanceMonitorProductGuidePG016,LogiCOREIPVideoTimingControllerProductGuideXilinxOpenSourceARMgitRepository:git.
xilinx.
com/UG798,XilinxDesignTools:InstallationandLicensingGuideXilinxARMGNUTools:wiki.
xilinx.
com/zynq-toolsUsingGit:wiki.
xilinx.
com/using-gitgit:thefastversioncontrolsystemhomepage:git-scm.
com/UG821,Zynq-7000AllProgrammableSoCSoftwareDevelopersGuideXilinxZynq-7000AllProgrammableSoCwebsitewww.
xilinx.
com/products/silicon-devices/soc/zynq-7000/index.
htmZynq-7000AllProgrammableSoCproducttablewww.
xilinx.
com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.
pdfDS190,Zynq-7000AllProgrammableSoCOverviewZynqLinux:DownloadingtheKernelTree:xilinx.
wikidot.
com/zynq-linux#toc7ZynqLinux:ConfiguringandBuildingtheLinuxKernel:xilinx.
wikidot.
com/zynq-linux#toc8XilinxOpenSourceLinux:wiki.
xilinx.
com/open-source-linuxXilinxDeviceTreeGenerator:xilinx.
wikidot.
com/device-tree-generatorXilinxPlanAheadDesignandAnalysisToolwebsitewww.
xilinx.
com/tools/planahead.
htmZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com47UG925(v3.
0)January31,2013ReferencesUG873,Zynq-7000AllProgrammableSoC:Concepts,Tools,andTechniquesGuideUG673,QuickFront-to-BackOverviewTutorial:PlanAheadDesignToolPG012,LogiCOREIPChromaResamplerProductGuidePG014,LogiCOREIPYCrCbtoRGBColor-SpaceConverterProductGuidePG043LogiCOREIPVideoIntoAXI4-Streamv1.
0PG103LogiCOREIPTestPatternGeneratorMoreinformationonZynq-7000familyboards,FMCextensioncards,andotherkitsbasedonZynq-7000architectureisavailablehere.
XilinxZynq-7000AllProgrammableSoCBoardsandKitswww.
xilinx.
com/products/boards_kits/zynq-7000.
htmXilinxZynq-7000BaseTargetedReferenceDesignwikipage:wiki.
xilinx.
com/zc702-base-trdReferencesThefollowingwebsitesprovidesupplementalmaterialusefulwiththisguide:1.
XylonIPCores-logiCVC-MLCompactMultilayerVideoControllerdescriptionwww.
logicbricks.
com/Products/logiCVC-ML.
aspx2.
QtOnlineReferenceDocumentation.
QtisatoolkitforcreatingGUIs.
doc.
qt.
nokia.
com/3.
DeviceTreegeneralinformationdevicetree.
org/Main_Page4.
AMBAAXI4-StreamProtocolSpecificationinfocenter.
arm.
com/help/index.
jsptopic=/com.
arm.
doc.
ihi0051a/index.
html5.
PCI-SIGDocumentationwww.
pcisig.
com/specifications6.
logiCVC-MLCompactMultilayerVideoControllerDataSheetwww.
logicbricks.
com/Documentation/Datasheets/IP/logiCVC-ML_hds.
pdf7.
SiliconLabsCP210xUSBtoUARTBridgeVCPDriverswww.
silabs.
com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.
aspxZynq-7000APSoCZC702BaseTRDwww.
xilinx.
com48UG925(v3.
0)January31,2013AppendixERegulatoryandComplianceInformationThisproductisdesignedandtestedtoconformtotheEuropeanUniondirectivesandstandardsdescribedinthissection.
DeclarationofConformityToviewtheDeclarationofConformityonline,pleasevisit:http://www.
xilinx.
com/support/documentation/boards_and_kits/ce-declarations-of-conformity-xtp251.
zipDirectives2006/95/EC,LowVoltageDirective(LVD)2004/108/EC,ElectromagneticCompatibility(EMC)DirectiveStandardsENstandardsaremaintainedbytheEuropeanCommitteeforElectrotechnicalStandardization(CENELEC).
IECstandardsaremaintainedbytheInternationalElectrotechnicalCommission(IEC).
ElectromagneticCompatibilityEN55022:2010,InformationTechnologyEquipmentRadioDisturbanceCharacteristics–LimitsandMethodsofMeasurementEN55024:2010,InformationTechnologyEquipmentImmunityCharacteristics–LimitsandMethodsofMeasurementThisisaClassAproduct.
Inadomesticenvironment,thisproductcancauseradiointerference,inwhichcasetheusermightberequiredtotakeadequatemeasures.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com49UG925(v3.
0)January31,2013MarkingsSafetyIEC60950-1:2005,Informationtechnologyequipment–Safety,Part1:GeneralrequirementsEN60950-1:2006,Informationtechnologyequipment–Safety,Part1:GeneralrequirementsMarkingsThisproductcomplieswithDirective2002/96/EConwasteelectricalandelectronicequipment(WEEE).
Theaffixedproductlabelindicatesthattheusermustnotdiscardthiselectricalorelectronicproductindomestichouseholdwaste.
ThisproductcomplieswithDirective2002/95/EContherestrictionofhazardoussubstances(RoHS)inelectricalandelectronicequipment.
ThisproductcomplieswithCEDirectives2006/95/EC,LowVoltageDirective(LVD)and2004/108/EC,ElectromagneticCompatibility(EMC)Directive.
Zynq-7000APSoCZC702BaseTRDwww.
xilinx.
com50UG925(v3.
0)January31,2013AppendixFWarrantyTHISLIMITEDWARRANTYappliessolelytostandardhardwaredevelopmentboardsandstandardhardwareprogrammingcablesmanufacturedbyoronbehalfofXilinx("DevelopmentSystems").
Subjecttothelimitationsherein,XilinxwarrantsthatDevelopmentSystems,whendeliveredbyXilinxoritsauthorizeddistributor,forninety(90)daysfollowingthedeliverydate,willbefreefromdefectsinmaterialandworkmanshipandwillsubstantiallyconformtoXilinxpubliclyavailablespecificationsforsuchproductsineffectatthetimeofdelivery.
Thislimitedwarrantyexcludes:(i)engineeringsamplesorbetaversionsofDevelopmentSystems(whichareprovided"ASIS"withoutwarranty);(ii)designdefectsorerrorsknownas"errata";(iii)DevelopmentSystemsprocuredthroughunauthorizedthirdparties;and(iv)DevelopmentSystemsthathavebeensubjecttomisuse,mishandling,accident,alteration,neglect,unauthorizedrepairorinstallation.
Furthermore,thislimitedwarrantyshallnotapplytotheuseofcoveredproductsinanapplicationorenvironmentthatisnotwithinXilinxspecificationsorintheeventofanyact,error,neglectordefaultofCustomer.
ForanybreachbyXilinxofthislimitedwarranty,theexclusiveremedyofCustomerandthesoleliabilityofXilinxshallbe,attheoptionofXilinx,toreplaceorrepairtheaffectedproducts,ortorefundtoCustomerthepriceoftheaffectedproducts.
TheavailabilityofreplacementproductsissubjecttoproductdiscontinuationpoliciesatXilinx.
Customermaynotreturnproductwithoutfirstobtainingacustomerreturnmaterialauthorization(RMA)numberfromXilinx.
THEWARRANTIESSETFORTHHEREINAREEXCLUSIVE.
XILINXDISCLAIMSALLOTHERWARRANTIES,WHETHEREXPRESS,IMPLIEDORSTATUTORY,INCLUDING,WITHOUTLIMITATION,ANYWARRANTYOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ORNON-INFRINGEMENT,ANDANYWARRANTYTHATMAYARISEFROMCOURSEOFDEALING,COURSEOFPERFORMANCE,ORUSAGEOFTRADE.
(2008.
10)DonotthrowXilinxproductsmarkedwiththe"crossedoutwheeledbin"inthetrash.
Directive2002/96/EConwasteelectricalandelectronicequipment(WEEE)requirestheseparatecollectionofWEEE.
YourcooperationisessentialinensuringthepropermanagementofWEEEandtheprotectionoftheenvironmentandhumanhealthfrompotentialeffectsarisingfromthepresenceofhazardoussubstancesinWEEE.
ReturnthemarkedproductstoXilinxforproperdisposal.
Furtherinformationandinstructionsforfree-of-chargereturnavailableat:http:\\www.
xilinx.
com\ehs\weee.
htm.