2.5avtt4.com

ADS7841-Q1www.
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comSBAS469C–MARCH2009–REVISEDOCTOBER201212-BIT4-CHANNELSERIAL-OUTPUTSAMPLINGANALOG-TO-DIGITALCONVERTERCheckforSamples:ADS7841-Q11FEATURESQualifiedforAutomotiveApplicationsSingleSupply:2.
7VTo5VFour-ChannelSingle-EndedOrTwo-ChannelDifferentialInputUpTo200-kHzConversionRate±2LSBMaxINLandDNLNoMissingCodes71-dBTypSINADSerialInterfaceAlternateSourceForMAX1247DESCRIPTIONTheADS7841isa4-channel12-bitsamplinganalog-to-digitalconverter(ADC)withasynchronousserialinterface.
Theresolutionisprogrammabletoeither8bitsor12bits.
Typicalpowerdissipationis2mWata200-kHzthroughputrateanda5-Vsupply.
Thereferencevoltage(VREF)canbevariedbetween100mVandVCC,providingacorrespondinginputvoltagerangeof0VtoVREF.
Thedeviceincludesashutdownmodethatreducespowerdissipationtounder15μW.
TheADS7841isspecifieddownto2.
7-Voperation.
Lowpower,highspeed,andon-boardmultiplexermaketheADS7841idealforbattery-operatedsystems.
Theserialinterfacealsoprovideslow-costisolationforremotedataacquisition.
TheADS7841isavailableinaSSOP-16package.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2009–2012,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
ti.
comThisintegratedcircuitcanbedamagedbyESD.
TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwithappropriateprecautions.
Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.
Precisionintegratedcircuitsmaybemoresusceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
ORDERINGINFORMATION(1)TAORDERABLEPARTNUMBERTOP-SIDEMARKING–40°Cto85°CADS7841EIDBQRQ1S7841E–40°Cto125°CADS7841ESQDBQRQ1S7841S(1)Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTIwebsiteatwww.
ti.
com.
TERMINALFUNCTIONSTERMINALI/ODESCRIPTIONNAMENO.
VCC1PowersupplyCH02IAnaloginputchannel0CH13IAnaloginputchannel1CH24IAnaloginputchannel2CH35IAnaloginputchannel3Groundreferenceforanaloginputs.
Setszerocodevoltageinsingle-endedmode.
ConnectthispintogroundCOM6Iorgroundreferencepoint.
SHDN7IShutdown.
Whenlow,thedeviceentersaverylowpowershutdownmode.
VREF8IVoltagereferenceVCC9PowersupplyGND10GroundConversionmode.
Whenlow,thedevicealwaysperformsa12-bitconversion.
Whenhigh,theresolutionisMODE11IsetbytheMODEbitintheCONTROLbyte.
Serialdataoutput.
DataisshiftedonthefallingedgeofDCLK.
Thisoutputishigh-impedancewhenCSisDOUT12Ohigh.
BUSY13OBusyoutput.
Thisoutputishigh-impedancewhenCSishigh.
DIN14ISerialdatainput.
IfCSislow,dataislatchedonrisingedgeofDCLK.
CS15IChipselectinput.
Controlsconversiontimingandenablestheserialinput/outputregister.
DCLK16IExternalclockinput.
ThisclockrunstheSARconversionprocessandsynchronizesserialdataI/O.
2SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1ADS7841-Q1www.
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comSBAS469C–MARCH2009–REVISEDOCTOBER2012ABSOLUTEMAXIMUMRATINGS(1)overoperatingfree-airtemperaturerange(unlessotherwisenoted)VCCSupplyvoltage–0.
3Vto6VAnaloginputstoGND–0.
3Vto(VCC+0.
3V)VINInputvoltageDigitalinputstoGND–0.
3Vto6VPDPowerdissipation250mWTJMaximumvirtual-junctiontemperature150°CADS7841EIDBQRQ1–40°Cto85°CTAOperatingfree-airtemperaturerangeADS7841ESQDBQRQ1–40°Cto125°CTstgStoragetemperaturerange–65°Cto150°C(1)Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperatingconditionsisnotimplied.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
ELECTROSTATICDISCHARGERATINGSRATINGHuman-BodyModel(HBM)2000VESDElectrostaticdischargeratingMachineModel(MM)150VCharged-DeviceModel(CDM)1000VRECOMMENDEDOPERATINGCONDITIONSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)MINMAXUNITVCC=5V(nom)4.
755.
25VCCSupplyvoltageVVCC=2.
7V(nom)2.
73.
6VREFReferencevoltage,VREFterminal0.
1VCCVDifferential,full-scale0VREFPositiveinput–0.
2VCC+0.
2VINInputvoltage,analoginputsVVCC=5V(nom)–0.
21.
25NegativeinputVCC=2.
7V(nom)–0.
20.
2VCC=5V(nom)35.
5VIHHigh-levelinputvoltage,digitalinputs|IIH|≤5μAVVCC=2.
7V(nom)0.
7VCC5.
5VCC=5V(nom)–0.
30.
8VILLow-levelinputvoltage,digitalinputs|IIL|≤5μAVVCC=2.
7V(nom)–0.
30.
8ADS7841EIDBQRQ1–4085TAOperatingfree-airtemperature°CADS7841ESQDBQRQ1–40125Copyright2009–2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:ADS7841-Q1ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
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comELECTRICALCHARACTERISTICSVCC=5V,VREF=5V,fSAMPLE=200kHz,fCLK=16*fSAMPLE=3.
2MHz,overoperatingtemperature–40°Cto125°C(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITAnalogInputCIInputcapacitance25pFIleakLeakagecurrent200nASystemPerformanceResolution12bitsADS7841EIDBQRQ112NomissingcodesbitsADS7841ESQDBQRQ111LSB(INLIntegrallinearityerror±21)DNLDifferentiallinearityerror±0.
8LSBOffseterror±3LSBOffseterrormatch0.
151LSBGainerror±4LSBGainerrormatch0.
11LSBμVrmVnNoise30sPSRRPower-supplyripplerejection70dBSamplingDynamicsCLKtconvConversiontime12cyclesCLKtacqAcquisitiontime3cyclesThroughputrate200kHztsettleMultiplexersettlingtime500nstdAperturedelay30nstjitterAperturejitter100psDynamicCharacteristicsTHDTotalharmonicdistortion(2)VIN=5Vp-pat10kHz–78–72dBSINADSignaltonoise+distortionratioVIN=5Vp-pat10kHz6871dBSpurious-freedynamicrangeVIN=5Vp-pat10kHz7279dBChannel-to-channelisolationVIN=5Vp-pat50kHz120dBReferenceInputRIResistanceDCLKstatic5G40100IIInputcurrentfSAMPLE=12.
5kHz2.
5μADCLKstatic0.
0013DigitalInput/OutputVOHHigh-leveloutputvoltageIOH=–250μA3.
5VVOLLow-leveloutputvoltageIOL=250μA0.
4VPowerSupply550900IQQuiescentcurrentfSAMPLE=12.
5kHz300μAPower-downmode(3),CS=VCC3(1)LSB=leastsignificantbit.
WithVREF=5V,oneLSBis1.
22mV.
(2)Firstfiveharmonicsofthetestfrequency(3)Autopower-downmode(PD1=PD0=0)activeorSHDN=GND4SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1ADS7841-Q1www.
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comSBAS469C–MARCH2009–REVISEDOCTOBER2012ELECTRICALCHARACTERISTICSVCC=2.
7V,VREF=2.
5V,fSAMPLE=125kHz,fCLK=16*fSAMPLE=2MHz,overoperatingtemperature–40°Cto85°C(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITAnalogInputCIInputcapacitance25pFIleakLeakagecurrent±1μASystemPerformanceResolution12bitsNomissingcodes12bitsINLIntegrallinearityerror±2LSB(1)DNLDifferentiallinearityerror±0.
8LSBOffseterror±3LSBOffseterrormatch0.
151LSBGainerror±4LSBGainerrormatch0.
11LSBVnNoise30μVrmsPSRRPower-supplyripplerejection70dBSamplingDynamicsCLKtconvConversiontime12cyclesCLKtacqAcquisitiontime3cyclesThroughputrate125kHztsettleMultiplexersettlingtime500nstdAperturedelay30nstjitterAperturejitter100psDynamicCharacteristicsTHDTotalharmonicdistortion(2)VIN=2.
5Vp-pat10kHz–77–72dBSINADSignaltonoise+distortionratioVIN=2.
5Vp-pat10kHz6871dBSpurious-freedynamicrangeVIN=2.
5Vp-pat10kHz7278dBChannel-to-channelisolationVIN=2.
5Vp-pat50kHz100dBReferenceInputRIResistanceDCLKstatic5G1340IIInputcurrentfSAMPLE=12.
5kHz2.
5μADCLKstatic0.
0013DigitalInput/OutputVOHHigh-leveloutputvoltageIOH=–250μA0.
8VCCVVOLLow-leveloutputvoltageIOL=250μA0.
4VPowerSupply280650IQQuiescentcurrentfSAMPLE=12.
5kHz220μAPower-downmode(3),CS=VCC3(1)LSB=leastsignificantbit.
WithVREF=2.
5V,oneLSBis0.
61mV.
(2)Firstfiveharmonicsofthetestfrequency(3)Autopower-downmode(PD1=PD0=0)activeorSHDN=GNDCopyright2009–2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:ADS7841-Q1ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
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comTYPICALCHARACTERISTICS,VCC=5VVCC=5V,TA=25°C,VREF=5V,fSAMPLE=200kHz,fCLK=16*fSAMPLE=3.
2MHz(unlessotherwisenoted)6SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1ADS7841-Q1www.
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comSBAS469C–MARCH2009–REVISEDOCTOBER2012TYPICALCHARACTERISTICS,VCC=2.
7VVCC=2.
7V,TA=25°C,VREF=2.
5V,fSAMPLE=125kHz,fCLK=16*fSAMPLE=2MHz(unlessotherwisenoted)Copyright2009–2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:ADS7841-Q1ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
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comTYPICALCHARACTERISTICS,VCC=2.
7V(continued)VCC=2.
7V,TA=25°C,VREF=2.
5V,fSAMPLE=125kHz,fCLK=16*fSAMPLE=2MHz(unlessotherwisenoted)8SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1ADS7841-Q1www.
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comSBAS469C–MARCH2009–REVISEDOCTOBER2012TYPICALCHARACTERISTICS,VCC=2.
7V(continued)VCC=2.
7V,TA=25°C,VREF=2.
5V,fSAMPLE=125kHz,fCLK=16*fSAMPLE=2MHz(unlessotherwisenoted)Copyright2009–2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:ADS7841-Q1ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
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comAPPLICATIONINFORMATIONTheADS7841isaclassicsuccessiveapproximationregister(SAR)ADC.
Thearchitectureisbasedoncapacitiveredistributionthatinherentlyincludesasample-and-holdfunction.
Theconverterisfabricatedona0.
6-μsCMOSprocess.
ThebasicoperationoftheADS7841isshowninFigure1.
Thedevicerequiresanexternalreferenceandanexternalclock.
Itoperatesfromasinglesupplyof2.
7Vto5.
25V.
Theexternalreferencecanbeanyvoltagebetween100mVandVCC.
Thevalueofthereferencevoltagedirectlysetstheinputrangeoftheconverter.
TheaveragereferenceinputcurrentdependsontheconversionrateoftheADS7841.
Figure1.
BasicOperationoftheADS7841Theanaloginputtotheconverterisdifferentialandisprovidedviaafour-channelmultiplexer.
TheinputcanbeprovidedinreferencetoavoltageontheCOMpin(whichisgenerallyground)ordifferentiallybyusingtwoofthefourinputchannels(CH0-CH3).
Theparticularconfigurationisselectableviathedigitalinterface.
AnalogInputFigure2showsablockdiagramoftheinputmultiplexerontheADS7841.
ThedifferentialinputoftheconverterisderivedfromoneofthefourinputsinreferencetotheCOMpinortwoofthefourinputs.
Table1andTable2showtherelationshipbetweentheA2,A1,A0,andSGL/DIFcontrolbitsandtheconfigurationoftheanalogmultiplexer.
ThecontrolbitsareprovidedseriallyviatheDINpin,seetheDigitalInterfacesectionofthisdatasheetformoredetails.
Figure2.
SimplifiedDiagramoftheAnalogInput10SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1ADS7841-Q1www.
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comSBAS469C–MARCH2009–REVISEDOCTOBER2012Table1.
Single-EndedChannelSelection(SGL/DIFhigh)A2A1A0CH0CH1CH2CH3COM001+IN–IN101+IN–IN010+IN–IN110+IN–INTable2.
DifferentialChannelControl(SGL/DIFlow)A2A1A0CH0CH1CH2CH3COM001+IN–IN101–IN+IN010+IN–IN110–IN+INWhentheconverterenterstheholdmode,thevoltagedifferencebetweenthe+INand–INinputs(asshowninFigure2)iscapturedontheinternalcapacitorarray.
Thevoltageonthe–INinputislimitedbetween–0.
2Vand1.
25V,allowingtheinputtorejectsmallsignalsthatarecommontoboththe+INand–INinput.
The+INinputhasarangeof–0.
2VtoVCC+0.
2V.
Theinputcurrentontheanaloginputsdependsontheconversionrateofthedevice.
Duringthesampleperiod,thesourcemustchargetheinternalsamplingcapacitor(typically25pF).
Afterthecapacitorhasbeenfullycharged,thereisnofurtherinputcurrent.
Therateofchargetransferfromtheanalogsourcetotheconverterisafunctionofconversionrate.
ReferenceInputTheexternalreferencesetstheanaloginputrange.
TheADS7841operateswithareferenceintherangeof100mVtoVCC.
Keepinmindthattheanaloginputisthedifferencebetweenthe+INinputandthe–INinput,seeFigure2.
Forexample,inthesingle-endedmode,a1.
25-Vreference,andwiththeCOMpingrounded,theselectedinputchannel(CH0-CH3)digitizesasignalintherangeof0Vto1.
25V.
IftheCOMpinisconnectedto0.
5V,theinputrangeontheselectedchannelis0.
5Vto1.
75V.
Thereareseveralcriticalitemsconcerningthereferenceinputanditswidevoltagerange.
Asthereferencevoltageisreduced,theanalogvoltageweightofeachdigitaloutputcodeisalsoreduced.
ThisisoftenreferredtoastheLSB(leastsignificantbit)sizeandisequaltothereferencevoltagedividedby4096.
AnyoffsetorgainerrorinherentintheADCappearstoincrease,intermsofLSBsize,asthereferencevoltageisreduced.
Forexample,iftheoffsetofagivenconverteris2LSBswitha2.
5-Vreference,thenitistypically10LSBswitha0.
5-Vreference.
Ineachcase,theactualoffsetofthedeviceisthesame,1.
22mV.
Likewise,thenoiseoruncertaintyofthedigitizedoutputincreaseswithlowerLSBsize.
Withareferencevoltageof100mV,theLSBsizeis24μV.
Thislevelisbelowtheinternalnoiseofthedevice.
Asaresult,thedigitaloutputcodeisnotstableandvariesaroundameanvaluebyanumberofLSBs.
Thedistributionofoutputcodesisgaussian,andthenoisecanbereducedbysimplyaveragingconsecutiveconversionresultsorapplyingadigitalfilter.
Withalowerreferencevoltage,careshouldbetakentoprovideacleanlayoutincludingadequatebypassing,aclean(low-noise,low-ripple)powersupply,alow-noisereference,andalow-noiseinputsignal.
BecausetheLSBsizeislower,theconverterisalsomoresensitivetonearbydigitalsignalsandelectromagneticinterference.
ThevoltageintotheVREFinputisnotbufferedanddirectlydrivestheCapacitorDigital-to-AnalogConverter(CDAC)portionoftheADS7841.
Typically,theinputcurrentis13μAwitha2.
5-Vreference.
Thisvaluevariesbymicroampsdependingontheresultoftheconversion.
Thereferencecurrentdiminishesdirectlywithbothconversionrateandreferencevoltage.
Asthecurrentfromthereferenceisdrawnoneachbitdecision,clockingtheconvertermorequicklyduringagivenconversionperioddoesnotreduceoverallcurrentdrainfromthereference.
Copyright2009–2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11ProductFolderLinks:ADS7841-Q1ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
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comDigitalInterfaceFigure3showsthetypicaloperationoftheADS7841'sdigitalinterface.
Thisdiagramassumesthatthesourceofthedigitalsignalsisamicrocontrollerordigitalsignalprocessorwithabasicserialinterface(notethatthedigitalinputsareover-voltagetolerantupto5.
5V,regardlessofVCC).
Eachcommunicationbetweentheprocessorandtheconverterconsistsofeightclockcycles.
Onecompleteconversioncanbeaccomplishedwiththreeserialcommunications,foratotalof24clockcyclesontheDCLKinput.
A.
24clockcyclesperconversion,8-bitbusinterface.
NoDCLKdelayrequiredwithdedicatedserialport.
Figure3.
ConversionTimingThefirsteightclockcyclesareusedtoprovidethecontrolbyteviatheDINpin.
Whentheconverterhasenoughinformationaboutthefollowingconversiontosettheinputmultiplexerappropriately,itenterstheacquisition(sample)mode.
Afterthreemoreclockcycles,thecontrolbyteiscompleteandtheconverterenterstheconversionmode.
Atthispoint,theinputsample-and-holdgoesintotheholdmode.
ThenexttwelveclockcyclesaccomplishtheactualAnalog-to-Digitalconversion.
Athirteenthclockcycleisneededforthelastbitoftheconversionresult.
Threemoreclockcyclesareneededtocompletethelastbyte(DOUTislow).
Theseareignoredbytheconverter.
ControlByteAlsoshowninFigure3istheplacementandorderofthecontrolbitswithinthecontrolbyte.
Table3andTable4givedetailedinformationaboutthesebits.
Thefirstbit,the'S'bit,mustalwaysbehighandindicatesthestartofthecontrolbyte.
TheADS7841ignoresinputsontheDINpinuntilthestartbitisdetected.
Thenextthreebits(A2-A0)selecttheactiveinputchannelorchannelsoftheinputmultiplexer(seeTable1,Table2,andFigure2).
Table3.
OrderofControlBitsinControlByteBit7Bit0Bit6Bit5Bit4Bit3Bit2Bit1(MSB)(LSB)SA2A1A0MODESGL/DIFPD1PD0Table4.
DescriptionsofControlBitsWithinControlByteBITNAMEDESCRIPTIONStartbit.
ControlbytestartswithfirsthighbitonDIN.
Anewcontrolbytecanstartevery15thclock7Scyclein12-bitconversionmodeorevery11thclockcyclein8-bitconversionmode.
Channelselectbits.
AlongwiththeSGL/DIFbit,thesebitscontrolthesettingofthemultiplexerinput,6-4A2-A0seeTable1andTable2.
12-bit/8-bitconversionselectbit.
IftheMODEpinishigh,thisbitcontrolsthenumberofbitsforthe3MODEnextconversion:12-bits(low)or8-bits(high).
IftheMODEpinislow,thisbithasnofunctionandtheconversionisalways12bits.
Single-ended/differentialselectbit.
AlongwithbitsA2-A0,thisbitcontrolsthesettingofthemultiplexer2SGL/DIFinput,seeTable1andTable2.
1-0PD1-PD0Power-downmodeselectbits.
SeeTable5fordetails.
12SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1ADS7841-Q1www.
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comSBAS469C–MARCH2009–REVISEDOCTOBER2012TheMODEbitandtheMODEpinworktogethertodeterminethenumberofbitsforagivenconversion.
IftheMODEpinislow,theconverteralwaysperformsa12-bitconversionregardlessofthestateoftheMODEbit.
IftheMODEpinishigh,thentheMODEbitdeterminesthenumberofbitsforeachconversion,either12bits(low)or8bits(high).
TheSGL/DIFbitcontrolsthemultiplexerinputmode:eithersingle-ended(high)ordifferential(low).
Insingle-endedmode,theselectedinputchannelisreferencedtotheCOMpin.
Indifferentialmode,thetwoselectedinputsprovideadifferentialinput.
SeeTable1,Table2,andFigure2formoreinformation.
Thelasttwobits(PD1-PD0)selectthepowerdownmode,asshowninTable5.
Ifbothinputsarehigh,thedeviceisalwayspoweredup.
Ifbothinputsarelow,thedeviceentersapower-downmodebetweenconversions.
Whenanewconversionisinitiated,thedeviceresumesnormaloperationinstantly—nodelayisneededtoallowthedevicetopowerupandtheveryfirstconversionisvalid.
Table5.
Power-DownSelectionPD1PD0DESCRIPTIONPower-downbetweenconversions.
Wheneachconversionisfinished,theconverterentersalowpowermode.
At00thestartofthenextconversion,thedeviceinstantlypowersuptofullpower.
Thereisnoneedforadditionaldelaystoassurefulloperationandtheveryfirstconversionisvalid.
01Reserved10Reserved11Nopower-downbetweenconversions,devicealwayspowered.
16ClockCyclesPerConversionThecontrolbitsforconversionn+1canbeoverlappedwithconversion'n'toallowforaconversionevery16clockcycles,asshowninFigure4.
Thisfigurealsoshowspossibleserialcommunicationoccurringwithotherserialperipheralsbetweeneachbytetransferbetweentheprocessorandtheconverter.
Thisispossibleprovidedthateachconversioncompleteswithin1.
6msofstarting.
Otherwise,thesignalthathasbeencapturedontheinputsample-and-holdmaydroopenoughtoaffecttheconversionresult.
Inaddition,theADS7841isfullypoweredwhileotherserialcommunicationsaretakingplace.
A.
16clockcyclesperconversion,8-bitbusinterface.
NoDCLKdelayrequiredwithdedicatedserialport.
Figure4.
ConversionTimingCopyright2009–2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLinks:ADS7841-Q1ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
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comDigitalTimingFigure5,Table6,andTable7providedetailedtimingforthedigitalinterfaceoftheADS7841.
Figure5.
DetailedTimingDiagramTable6.
TimingSpecifications,VCC=2.
7Vto3.
6V,TA=–40°Cto85°C,CLOAD=50pFSYMBOLDESCRIPTIONMINMAXUNITtACQAcquisitiontime1500nstDSDINvalidpriortoDCLKrising100nstDHDINholdafterDCLKhigh10nstDODCLKfallingtoDOUTvalid200nstDVCSfallingtoDOUTenabled200nstTRCSrisingtoDOUTdisabled200nstCSSCSfallingtofirstDCLKrising100nstCSHCSrisingtoDCLKignored0nstCHDCLKhigh200nstCLDCLKlow200nstBDDCLKfallingtoBUSYrising200nstBDVCSfallingtoBUSYenabled200nstBTRCSrisingtoBUSYdisabled200nsTable7.
TimingSpecifications,VCC=4.
75Vto5.
25V,TA=–40°Cto85°C,CLOAD=50pFSYMBOLDESCRIPTIONMINMAXUNITtACQAcquisitiontime900nstDSDINvalidpriortoDCLKrising50nstDHDINholdafterDCLKhigh10nstDODCLKfallingtoDOUTvalid100nstDVCSfallingtoDOUTenabled70nstTRCSrisingtoDOUTdisabled70nstCSSCSfallingtofirstDCLKrising50nstCSHCSrisingtoDCLKignored0nstCHDCLKhigh150nstCLDCLKlow150nstBDDCLKfallingtoBUSYrising100nstBDVCSfallingtoBUSYenabled70nstBTRCSrisingtoBUSYdisabled70ns14SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1ADS7841-Q1www.
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comSBAS469C–MARCH2009–REVISEDOCTOBER201215ClockCyclesPerConversionFigure6providesthefastestwaytoclocktheADS7841.
Thismethoddoesnotworkwiththeserialinterfaceofmostmicrocontrollersanddigitalsignalprocessorsastheyaregenerallynotcapableofproviding15clockcyclesperserialtransfer.
However,thismethodcouldbeusedwithfieldprogrammablegatearrays(FPGAs)orapplicationspecificintegratedcircuits(ASICs).
Notethatthiseffectivelyincreasesthemaximumconversionrateoftheconverterbeyondthevaluesgiveninthespecificationtables,whichassume16clockcyclesperconversion.
Figure6.
MaximumConversionRate,15ClockCyclesPerConversionDataFormatTheADS7841outputdataisinstraightbinaryformat,asshowninFigure7.
Thisfigureshowstheidealoutputcodeforthegiveninputvoltageanddoesnotincludetheeffectsofoffset,gain,ornoise.
A.
Voltageatconverterinput,aftermultiplexer:+IN–(–IN).
SeeFigure2.
Figure7.
IdealInputVoltagesandOutputCodes8-BitConversionTheADS7841providesan8-bitconversionmodethatcanbeusedwhenfasterthroughputisneededandthedigitalresultisnotascritical.
Byswitchingtothe8-bitmode,aconversioniscompletefourclockcyclesearlier.
Thiscouldbeusedinconjunctionwithserialinterfacesthatprovidea12-bittransferortwoconversionscouldbeaccomplishedwiththree8-bittransfers.
Notonlydoesthisshorteneachconversionbyfourbits(25%fasterthroughput),buteachconversioncanactuallyoccuratafasterclockrate.
ThisisbecausetheinternalsettlingtimeoftheADS7841isnotascritical,settlingtobetterthan8bitsisallthatisneeded.
Theclockratecanbeasmuchas50%faster.
Thefasterclockrateandfewerclockcyclescombinetoprovidea2xincreaseinconversionrate.
Copyright2009–2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:ADS7841-Q1ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
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comPowerDissipationTherearethreepowermodesfortheADS7841:fullpower(PD1-PD0=11b),autopower-down(PD1-PD0=00b),andshutdown(SHDNlow).
TheaffectsofthesemodesvariesdependingonhowtheADS7841isbeingoperated.
Forexample,atfullconversionrateand16clocksperconversion,thereisverylittledifferencebetweenfullpowermodeandautopower-down.
Likewise,ifthedevicehasenteredautopower-down,ashutdown(SHDNlow)doesnotlowerpowerdissipation.
Whenoperatingatfull-speedand16-clocksperconversion(seeFigure4),theADS7841spendsmostofitstimeacquiringorconverting.
Thereislittletimeforautopower-down,assumingthatthismodeisactive.
Thus,thedifferencebetweenfullpowermodeandautopower-downisnegligible.
IftheconversionrateisdecreasedbysimplyslowingthefrequencyoftheDCLKinput,thetwomodesremainapproximatelyequal.
However,iftheDCLKfrequencyiskeptatthemaximumrateduringaconversion,butconversionaresimplydonelessoften,thenthedifferencebetweenthetwomodesisdramatic.
Figure8showsthedifferencebetweenreducingtheDCLKfrequency("scaling"DCLKtomatchtheconversionrate)ormaintainingDCLKatthehighestfrequencyandreducingthenumberofconversionpersecond.
Inthelatercase,theconverterspendsanincreasingpercentageofitstimeinpower-downmode(assumingtheautopower-downmodeisactive).
A.
DirectlyscalingthefrequencyofDCLKwithsamplerateorkeepingDCLKatthemaximumpossiblefrequencyFigure8.
SupplyCurrentvsSampleRateIfDCLKisactiveandCSislowwhiletheADS7841isinautopower-downmode,thedevicecontinuestodissipatesomepowerinthedigitallogic.
ThepowercanbereducedtoaminimumbykeepingCShigh.
ThedifferencesinsupplycurrentforthesetwocasesareshowninFigure9.
A.
VariedwithstateofCSFigure9.
SupplyCurrentvsSampleRate16SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1ADS7841-Q1www.
ti.
comSBAS469C–MARCH2009–REVISEDOCTOBER2012OperatingtheADS7841inautopower-downmoderesultsinthelowestpowerdissipation,andthereisnoconversiontime"penalty"onpower-up.
Theveryfirstconversionisvalid.
SHDNcanbeusedtoforceanimmediatepower-down.
PCBLayoutForoptimumperformance,careshouldbetakenwiththephysicallayoutoftheADS7841circuitry.
Thisisparticularlytrueifthereferencevoltageislowand/ortheconversionrateishigh.
ThebasicSARarchitectureissensitivetoglitchesorsuddenchangesonthepowersupply,reference,groundconnections,anddigitalinputsthatoccurjustpriortolatchingtheoutputoftheanalogcomparator.
Thus,duringanysingleconversionforann-bitSARconverter,therearen"windows"inwhichlargeexternaltransientvoltagescaneasilyaffecttheconversionresult.
Suchglitchesmightoriginatefromswitchingpowersupplies,nearbydigitallogic,andhighpowerdevices.
Thedegreeoferrorinthedigitaloutputdependsonthereferencevoltage,layout,andtheexacttimingoftheexternalevent.
TheerrorcanchangeiftheexternaleventchangesintimewithrespecttotheDCLKinput.
Withthisinmind,powertotheADS7841shouldbecleanandwellbypassed.
A0.
1-μFceramicbypasscapacitorshouldbeplacedasclosetothedeviceaspossible.
Inaddition,a1-μFto10-μFcapacitoranda5or10seriesresistormaybeusedtolow-passfilteranoisysupply.
Thereferenceshouldbesimilarlybypassedwitha0.
1-μFcapacitor.
Again,aseriesresistorandlargecapacitorcanbeusedtolow-passfilterthereferencevoltage.
Ifthereferencevoltageoriginatesfromanopamp,makesurethatitcandrivethebypasscapacitorwithoutoscillation(theseriesresistorcanhelpinthiscase).
TheADS7841drawsverylittlecurrentfromthereferenceonaverage,butitdoesplacelargerdemandsonthereferencecircuitryovershortperiodsoftime(oneachrisingedgeofDCLKduringaconversion).
TheADS7841architectureoffersnoinherentrejectionofnoiseorvoltagevariationinregardstothereferenceinput.
Thisisofparticularconcernwhenthereferenceinputistiedtothepowersupply.
Anynoiseandripplefromthesupplyappearsdirectlyinthedigitalresults.
Whilehigh-frequencynoisecanbefilteredoutasdiscussedinthepreviousparagraph,voltagevariationduetolinefrequency(50Hzor60Hz)canbedifficulttoremove.
TheGNDpinshouldbeconnectedtoacleangroundpoint.
Inmanycases,thisisthe"analog"ground.
Avoidconnectionsthataretoonearthegroundingpointofamicrocontrollerordigitalsignalprocessor.
Ifneeded,runagroundtracedirectlyfromtheconvertertothepowersupplyentrypoint.
Theideallayoutincludesananaloggroundplanededicatedtotheconverterandassociatedanalogcircuitry.
Copyright2009–2012,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:ADS7841-Q1ADS7841-Q1SBAS469C–MARCH2009–REVISEDOCTOBER2012www.
ti.
comREVISIONHISTORYChangesfromRevisionB(September,2011)toRevisionCPageDeletedpackagecolumnfromOrderingInformationtable;changedtop-sidemarkingofADS7841EIDBQRQ1fromADS7841EtoS7841Eandchangedtop-sidemarkingforADS7841ESQDBQRQ1fromADS7841StoS7841S.
218SubmitDocumentationFeedbackCopyright2009–2012,TexasInstrumentsIncorporatedProductFolderLinks:ADS7841-Q1PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesADS7841EIDBQRQ1ACTIVESSOPDBQ162500RoHS&GreenNIPDAULevel-3-260C-168HRS7841EADS7841ESQDBQRQ1ACTIVESSOPDBQ162500RoHS&GreenNIPDAULevel-3-260C-168HR-40to125S7841S(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
PACKAGEOPTIONADDENDUMwww.
ti.
com10-Dec-2020Addendum-Page2OTHERQUALIFIEDVERSIONSOFADS7841-Q1:Catalog:ADS7841NOTE:QualifiedVersionDefinitions:Catalog-TI'sstandardcatalogproductTAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantADS7841EIDBQRQ1SSOPDBQ162500330.
012.
46.
45.
22.
18.
012.
0Q1ADS7841ESQDBQRQ1SSOPDBQ162500330.
012.
46.
45.
22.
18.
012.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com28-Sep-2012PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)ADS7841EIDBQRQ1SSOPDBQ162500367.
0367.
035.
0ADS7841ESQDBQRQ1SSOPDBQ162500367.
0367.
035.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com28-Sep-2012PackMaterials-Page2www.
ti.
comPACKAGEOUTLINECTYP-.
244.
228-6.
195.
80[].
069MAX[1.
75]14X.
0250[0.
635]16X-.
012.
008-0.
300.
21[]2X.
175[4.
45]TYP-.
010.
005-0.
250.
13[]0-8-.
010.
004-0.
250.
11[](.
041)[1.
04].
010[0.
25]GAGEPLANE-.
035.
016-0.
880.
41[]ANOTE3-.
197.
189-5.
004.
81[]BNOTE4-.
157.
150-3.
983.
81[]SSOP-1.
75mmmaxheightDBQ0016ASHRINKSMALL-OUTLINEPACKAGE4214846/A03/2014NOTES:1.
Lineardimensionsareininches[millimeters].
Dimensionsinparenthesisareforreferenceonly.
Controllingdimensionsareininches.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thisdimensiondoesnotincludemoldflash,protrusions,orgateburrs.
Moldflash,protrusions,orgateburrsshallnotexceed.
006inch,perside.
4.
Thisdimensiondoesnotincludeinterleadflash.
5.
ReferenceJEDECregistrationMO-137,variationAB.
116.
007[0.
17]CAB98PIN1IDAREASEATINGPLANE.
004[0.
1]CSEEDETAILADETAILATYPICALSCALE2.
800www.
ti.
comEXAMPLEBOARDLAYOUT.
002MAX[0.
05]ALLAROUND.
002MIN[0.
05]ALLAROUND(.
213)[5.
4]14X(.
0250)[0.
635]16X(.
063)[1.
6]16X(.
016)[0.
41]SSOP-1.
75mmmaxheightDBQ0016ASHRINKSMALL-OUTLINEPACKAGE4214846/A03/2014NOTES:(continued)6.
PublicationIPC-7351mayhavealternatedesigns.
7.
Soldermasktolerancesbetweenandaroundsignalpadscanvarybasedonboardfabricationsite.
METALSOLDERMASKOPENINGNONSOLDERMASKDEFINEDSOLDERMASKDETAILSOPENINGSOLDERMASKMETALSOLDERMASKDEFINEDLANDPATTERNEXAMPLESCALE:8XSYMM18916SEEDETAILSwww.
ti.
comEXAMPLESTENCILDESIGN16X(.
063)[1.
6]16X(.
016)[0.
41]14X(.
0250)[0.
635](.
213)[5.
4]SSOP-1.
75mmmaxheightDBQ0016ASHRINKSMALL-OUTLINEPACKAGE4214846/A03/2014NOTES:(continued)8.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
9.
Boardassemblysitemayhavedifferentrecommendationsforstencildesign.
SOLDERPASTEEXAMPLEBASEDON.
005INCH[0.
127MM]THICKSTENCILSCALE:8XSYMMSYMM18916IMPORTANTNOTICEANDDISCLAIMERTIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
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