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DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013DS90LV8044-Channel800MbpsLVDSBuffer/RepeaterCheckforSamples:DS90LV804Inordertomaximizesignalintegrity,theDS90LV8041FEATURESfeaturesbothaninternalinputandoutput(source)23800MbpsDataRateperChannelterminationtoeliminatetheseextracomponentsfromLowOutputSkewandJittertheboard,andtoalsoplacetheterminationsascloseaspossibletoreceiverinputsanddriveroutput.
ThisLVDS/CML/LVPECLCompatibleInput,LVDSisespeciallysignificantwhendrivinglongercables.
OutputTheDS90LV804,availableintheWQFN(LeadlessOn-Chip100InputandOutputTerminationLeadframePackage)package,minimizesthe12kVESDProtectiononLVDSOutputsfootprint,andimprovessystemperformance.
Single3.
3VSupplyAnoutputenablepinisprovided,whichallowstheVeryLowPowerConsumptionusertoplacetheLVDSoutputsandinternalbiasingIndustrial-40to+85°CTemperatureRangegeneratorsinaTRI-STATE,lowpowermode.
SmallWQFNPackageFootprintThedifferentialinputsinterfacetoLVDS,andBusLVDSsignalssuchasthoseonTI's10-,16-,and18-DESCRIPTIONbitBusLVDSSerDes,aswellasCMLandLVPECL.
TheDS90LV804isafourchannel800MbpsLVDSThedifferentialinputsareinternallyterminatedwithabuffer/repeater.
Inmanylargesystems,signalsare100resistortoimproveperformanceandminimizedistributedacrosscablesandsignalintegrityishighlyboardspace.
Thisfunctionisespeciallyusefulfordependentonthedatarate,cabletype,length,andboostingsignalsoverlossycablesorpoint-to-pointtheterminationscheme.
backplaneconfigurations.
BlockandConnectionDiagramsFigure1.
DS90LV804BlockDiagram1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2TRI-STATEisaregisteredtrademarkofNationalSemiconductorCorporation.
3Allothertrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2005–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
DS90LV804SNLS195L–SEPTEMBER2005–REVISEDAPRIL2013www.
ti.
comDS90LV804WQFNPinout(TopView)Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
AbsoluteMaximumRatings(1)SupplyVoltage(VDD)0.
3Vto+4.
0VCMOSInputVoltage(EN)0.
3Vto(VDD+0.
3V)LVDSInputVoltage(2)0.
3Vto(VDD+0.
3V)LVDSOutputVoltage0.
3Vto(VDD+0.
3V)LVDSOutputShortCircuitCurrent+90mAJunctionTemperature+150°CStorageTemperature65°Cto+150°CLeadTemperature(Solder,4sec)260°CMaxPkgPowerCapacity@25°C4.
16WθJA29.
5°C/WThermalResistanceθJC3.
5°C/WPackageDeratingabove+25°C33.
3mW/°CHBM,1.
5k,100pF12kVESDLastPassingVoltage(LVDSoutputpins)EIAJ,0,200pF250VChargedDeviceModel1000VHBM,1.
5k,100pF8kVESDLastPassingVoltage(Allotherpins)EIAJ,0,200pF250VChargedDeviceModel1000V(1)Absolutemaximumratingsarethosevaluesbeyondwhichdamagetothedevicemayoccur.
Thedatabookspecificationsshouldbemet,withoutexception,toensurethatthesystemdesignisreliableoveritspowersupply,temperature,andoutput/inputloadingvariables.
TIdoesnotrecommendoperationofproductsoutsideofrecommendedoperationconditions.
(2)VIDmax<2.
4V2SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS90LV804DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013RecommendedOperatingConditionsSupplyVoltage(VCC)3.
15Vto3.
45VInputVoltage(VI)(1)0VtoVDDOutputVoltage(VO)0VtoVDDOperatingTemperature(TA)Industrial40°Cto+85°C(1)VIDmax<2.
4VElectricalCharacteristicsOverrecommendedoperatingsupplyandtemperaturerangesunlessotherspecified.
SymbolParameterConditionsMinTyp(1)MaxUnitsLVTTLDCSPECIFICATIONS(EN)VIHHighLevelInputVoltage2.
0VDDVVILLowLevelInputVoltageGND0.
8VIIHHighLevelInputCurrentVIN=VDD=VDDMAX10+10AIILLowLevelInputCurrentVIN=VSS,VDD=VDDMAX10+10ACIN1InputCapacitanceAnyDigitalInputPintoVSS3.
5pFVCLInputClampVoltageICL=18mA1.
50.
8VLVDSINPUTDCSPECIFICATIONS(INn±)VTHVCM=0.
8Vto3.
4V,DifferentialInputHighThreshold(2)0100mVVDD=3.
45VVTLVCM=0.
8Vto3.
4V,DifferentialInputLowThreshold(2)1000mVVDD=3.
45VVIDDifferentialInputVoltageVCM=0.
8Vto3.
4V,VDD=3.
45V1002400mVVCMRCommonModeVoltageRangeVID=150mV,VDD=3.
45V0.
053.
40VCIN2InputCapacitanceIN+orINtoVSS3.
5pFIINVIN=3.
45V,VDD=VDDMAX10+10AInputCurrentVIN=0V,VDD=VDDMAX10+10ALVDSOUTPUTDCSPECIFICATIONS(OUTn±)VODDifferentialOutputVoltage(2)250500600mVΔVODChangeinVODbetween3535mVComplementaryStatesRL=100externalresistorbetweenOUT+andOUTVOSOffsetVoltage(3)1.
051.
181.
475VΔVOSChangeinVOSbetween3535mVComplementaryStatesIOSOutputShortCircuitCurrentOUT+orOUTShorttoGND6090mACOUT2OutputCapacitanceOUT+orOUTtoGNDwhenTRI-STATE5.
5pFSUPPLYCURRENT(Static)ICCAllinputsandoutputsenabledandactive,TotalSupplyCurrentterminatedwithexternaldifferentialloadof100117140mAbetweenOUT+andOUT-.
ICCZTRI-STATESupplyCurrentEN=0V2.
76mA(1)TypicalparametersaremeasuredatVDD=3.
3V,TA=25°C.
Theyareforreferencepurposes,andarenotproduction-tested.
(2)DifferentialoutputvoltageVODisdefinedasABS(OUT+–OUT).
DifferentialinputvoltageVIDisdefinedasABS(IN+–IN).
(3)OutputoffsetvoltageVOSisdefinedastheaverageoftheLVDSsingle-endedoutputvoltagesatlogichighandlogiclowstates.
Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:DS90LV804DS90LV804SNLS195L–SEPTEMBER2005–REVISEDAPRIL2013www.
ti.
comElectricalCharacteristics(continued)Overrecommendedoperatingsupplyandtemperaturerangesunlessotherspecified.
SymbolParameterConditionsMinTyp(1)MaxUnitsSWITCHINGCHARACTERISTICS—LVDSOUTPUTStLHTDifferentialLowtoHighTransition210300psTimeUseanalternating1and0patternat200Mbps,measurebetween20%and80%ofVOD(4)tHLTDifferentialHightoLowTransition210300psTimetPLHDDifferentialLowtoHigh2.
03.
2nsPropagationDelayUseanalternating1and0patternat200Mbps,measureat50%VODbetweeninputtooutput.
tPHLDDifferentialHightoLow2.
03.
2nsPropagationDelaytSKD1PulseSkew|tPLHD–tPHLD|(4)2580pstSKCCDifferenceinpropagationdelay(tPLHDortPHLD)OutputChanneltoChannelSkew50125psamongalloutputchannels(4)tSKPParttoPartSkewCommonedge,partsatsametempandVCC(4)1.
1nstJITRJ-Alternating1and0at400MHz(6)1.
11.
5psrmsJitter(5)DJ-K28.
5Pattern,800Mbps(7)1535psp-pTJ-PRBS223-1Pattern,800Mbps(8)3055psp-ptONTimefromENtoOUT±changefromTRI-STATEtoLVDSOutputEnableTime300nsactive.
tOFFTimefromENtoOUT±changefromactivetoTRI-LVDSOutputDisableTime12nsSTATE.
(4)Notproductiontested.
Ensuredbystatisticalanalysisonasamplebasisatthetimeofcharacterization.
(5)Jitterisnotproductiontested,butensuredthroughcharacterizationonasamplebasis.
(6)RandomJitter,orRJ,ismeasuredRMSwithahistogramincluding1500histogramwindowhits.
Theinputvoltage=VID=500mV,50%dutycycleat400MHz,tr=tf=50ps(20%to80%).
(7)DeterministicJitter,orDJ,ismeasuredtoahistogrammeanwithasamplesizeof350hits.
Theinputvoltage=VID=500mV,K28.
5patternat800Mbps,tr=tf=50ps(20%to80%).
TheK28.
5patternisrepeatingbitstreamsof(00111110101100000101).
(8)TotalJitter,orTJ,ismeasuredpeaktopeakwithahistogramincluding3500windowhits.
StimulusandfixtureJitterhasbeensubtracted.
Theinputvoltage=VID=500mV,223-1PRBSpatternat800Mbps,tr=tf=50ps(20%to80%).
TypicalApplication4SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS90LV804DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013APPLICATIONINFORMATIONINTERNALTERMINATIONSTheDS90LV804hasintegratedterminationresistorsonboththeinputandoutputs.
Theinputshavea100resistoracrossthedifferentialpair,placingthereceiverterminationascloseaspossibletotheinputstageofthedevice.
TheLVDSoutputsalsocontainanintegrated100ohmterminationresistor,thisresistorisusedtoreducetheeffectsofNearEndCrosstalk(NEXT)anddoesnottaketheplaceofthe100ohmterminationattheinputstothereceivingdevice.
Theintegratedterminationsimprovesignalintegrityanddecreasetheexternalcomponentcountresultinginspacesavings.
OUTPUTCHARACTERISTICSTheoutputcharacteristicsoftheDS90LV804havebeenoptimizedforpoint-to-pointbackplaneandcableapplications,andarenotintendedformultipointormultidropsignaling.
TRI-STATEMODETheENinputactivatesahardwareTRI-STATEmode.
WhentheTRI-STATEmodeisactive(EN=L),allinputandoutputbuffersandinternalbiascircuitryarepoweredoffanddisabled.
Outputsaretri-statedinTRI-STATEmode.
WhenexitingTRI-STATEmode,thereisadelayassociatedwithturningonbandgapreferencesandinput/outputbuffercircuitsasindicatedintheLVDSOutputSwitchingCharacteristicsINPUTFAILSAFEBIASINGExternalpullupandpulldownresistorsmaybeusedtoprovideenoughofanoffsettoenableaninputfailsafeunderopen-circuitconditions.
ThisconfigurationtiesthepositiveLVDSinputpintoVDDthruapullupresistorandthenegativeLVDSinputpinistiedtoGNDbyapulldownresistor.
Thepullupandpulldownresistorsshouldbeinthe5kto15krangetominimizeloadingandwaveformdistortiontothedriver.
Thecommon-modebiaspointideallyshouldbesettoapproximately1.
2V(lessthan1.
75V)tobecompatiblewiththeinternalcircuitry.
PleaserefertoapplicationnoteAN-1194"FailsafeBiasingofLVDSInterfaces"formoreinformation.
INPUTINTERFACINGTheDS90LV804acceptsdifferentialsignalsandallowsimpleACorDCcoupling.
Withawidecommonmoderange,theDS90LV804canbeDC-coupledwithallcommondifferentialdrivers(thatis,LVPECL,LVDS,CML).
Figure2,Figure3,andFigure4illustratetypicalDC-coupledinterfacetocommondifferentialdrivers.
NotethattheDS90LV804inputsareinternallyterminatedwitha100Ωresistor.
Figure2.
TypicalLVDSDriverDC-CoupledInterfacetoDS90LV804InputCopyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:DS90LV804DS90LV804SNLS195L–SEPTEMBER2005–REVISEDAPRIL2013www.
ti.
comFigure3.
TypicalCMLDriverDC-CoupledInterfacetoDS90LV804InputFigure4.
TypicalLVPECLDriverDC-CoupledInterfacetoDS90LV804InputOUTPUTINTERFACINGTheDS90LV804outputssignalsthatarecomplianttotheLVDSstandard.
TheiroutputscanbeDC-coupledtomostcommondifferentialreceivers.
Figure5illustratestypicalDC-coupledinterfacetocommondifferentialreceiversandassumesthatthereceivershavehighimpedanceinputs.
WhilemostdifferentialreceivershaveacommonmodeinputrangethatcanaccommodateLVDScompliantsignals,itisrecommendedtocheckrespectivereceiver'sdatasheetpriortoimplementingthesuggestedinterfaceimplementation.
Figure5.
TypicalDS90LV804OutputDC-CoupledInterfacetoanLVDS,CMLorLVPECLReceiver6SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS90LV804DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013PINDESCRIPTIONSPinWQFNPinI/O,TypeDescriptionNameNumberDIFFERENTIALINPUTSIN0+9I,LVDSChannel0invertingandnon-invertingdifferentialinputs.
IN010IN1+11I,LVDSChannel1invertingandnon-invertingdifferentialinputs.
IN112IN2+13I,LVDSChannel2invertingandnon-invertingdifferentialinputs.
IN214IN3+15I,LVDSChannel3invertingandnon-invertingdifferentialinputs.
IN316DIFFERENTIALOUTPUTSOUT0+32O,LVDSChannel0invertingandnon-invertingdifferentialoutputs(1)OUT031OUT1+30O,LVDSChannel1invertingandnon-invertingdifferentialoutputs(1)OUT129OUT2+28O,LVDSChannel2invertingandnon-invertingdifferentialoutputs(1)OUT227OUT3+26O,LVDSChannel3invertingandnon-invertingdifferentialoutputs(1)OUT3-25DIGITALCONTROLINTERFACEEN8I,LVTTLEnablepin.
WhenENisLOW,thedriverisdisabledandtheLVDSoutputsareinTRI-STATE.
WhenENisHIGH,thedriverisenabled.
LVCMOS/LVTTLlevelinput.
POWERVDD3,4,6,7,19,20,21,22I,PowerVDD=3.
3V,±5%GND1,2,5,17,18(2)I,PowerGroundreferenceforLVDSandCMOScircuitry.
FortheWQFNpackage,theDAPisusedastheprimaryGNDconnectiontothedevice.
TheDAPistheexposedmetalcontactatthebottomoftheWQFN-32package.
Itshouldbeconnectedtothegroundplanewithatleast4viasforoptimalACandthermalperformance.
Thepinnumberslistedshouldalsobetiedtogroundforproperbiasing.
N/C23,24NoConnect(1)TheLVDSoutputsdonotsupportamultidrop(BLVDS)environment.
TheLVDSoutputcharacteristicsoftheDS90LV804devicehavebeenoptimizedforpoint-to-pointbackplaneandcableapplications.
(2)NotethatfortheWQFNpackagetheGNDisconnectedthrutheDAPonthebacksideoftheWQFNpackageinadditiontogroundingactualpinsonthepackageaslisted.
Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:DS90LV804DS90LV804SNLS195L–SEPTEMBER2005–REVISEDAPRIL2013www.
ti.
comTypicalPerformanceCharacteristicsA.
DynamicpowersupplycurrentwasmeasuredwhilerunningaclockorPRBS223-1patternwithall4channelsactive.
VCC=3.
3V,TA=+25°C,VID=0.
5V,VCM=1.
2VFigure6.
PowerSupplyCurrentvsBitDataRatePACKAGINGINFORMATIONTheLeadlessLeadframePackage(WQFN)isaleadframebasedchipscalepackage(CSP)thatmayenhancechipspeed,reducethermalimpedance,andreducetheprintedcircuitboardarearequiredformounting.
ThesmallsizeandverylowprofilemakethispackageidealforhighdensityPCBsusedinsmall-scaleelectronicapplicationssuchascellularphones,pagers,andhandheldPDAs.
TheWQFNpackageisofferedinthenoPullbackconfiguration.
InthenoPullbackconfigurationthestandardsolderpadsextendandterminateattheedgeofthepackage.
Thisfeatureoffersavisiblesolderfilletafterboardmounting.
TheWQFNhasthefollowingadvantages:LowthermalresistanceReducedelectricalparasiticsImprovedboardspaceefficiencyReducedpackageheightReducedpackagemassFormoredetailsaboutWQFNpackagingtechnology,refertoapplicationsnoteAN-1187,"LeadlessLeadframePackage".
8SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS90LV804DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013REVISIONHISTORYChangesfromRevisionK(April2013)toRevisionLPageChangedlayoutofNationalDataSheettoTIformat8Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:DS90LV804PACKAGEOPTIONADDENDUMwww.
ti.
com11-Jan-2021Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesDS90LV804TSQNRNDWQFNRTV321000Non-RoHS&GreenCallTICallTI-40to85804TSQDS90LV804TSQ/NOPBACTIVEWQFNRTV321000RoHS&GreenSNLevel-3-260C-168HR-40to85804TSQDS90LV804TSQX/NOPBACTIVEWQFNRTV324500RoHS&GreenSNLevel-3-260C-168HR-40to85804TSQ(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
PACKAGEOPTIONADDENDUMwww.
ti.
com11-Jan-2021Addendum-Page2InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantDS90LV804TSQWQFNRTV321000178.
012.
45.
35.
31.
38.
012.
0Q1DS90LV804TSQ/NOPBWQFNRTV321000178.
012.
45.
35.
31.
38.
012.
0Q1DS90LV804TSQX/NOPBWQFNRTV324500330.
012.
45.
35.
31.
38.
012.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com29-Sep-2019PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)DS90LV804TSQWQFNRTV321000210.
0185.
035.
0DS90LV804TSQ/NOPBWQFNRTV321000210.
0185.
035.
0DS90LV804TSQX/NOPBWQFNRTV324500367.
0367.
035.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com29-Sep-2019PackMaterials-Page2www.
ti.
comPACKAGEOUTLINEC5.
154.
855.
154.
850.
80.
70.
050.
002X3.
528X0.
52X3.
532X0.
50.
332X0.
300.
183.
10.
1(0.
1)TYPWQFN-0.
8mmmaxheightRTV0032APLASTICQUADFLATPACK-NOLEAD4224386/B04/20190.
08C0.
1CAB0.
05NOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thepackagethermalpadmustbesolderedtotheprintedcircuitboardforthermalandmechanicalperformance.
PIN1INDEXAREASEATINGPLANEPIN1IDSYMMEXPOSEDTHERMALPADSYMM189161724253233SCALE2.
500ABwww.
ti.
comEXAMPLEBOARDLAYOUT28X(0.
5)(1.
3)(1.
3)(R0.
05)TYP0.
07MAXALLAROUND0.
07MINALLAROUND32X(0.
6)32X(0.
24)(4.
8)(4.
8)(3.
1)(3.
1)(0.
2)TYPVIAWQFN-0.
8mmmaxheightRTV0032APLASTICQUADFLATPACK-NOLEAD4224386/B04/2019NOTES:(continued)4.
Thispackageisdesignedtobesolderedtoathermalpadontheboard.
Formoreinformation,seeTexasInstrumentsliteraturenumberSLUA271(www.
ti.
com/lit/slua271).
5.
Viasareoptionaldependingonapplication,refertodevicedatasheet.
Ifanyviasareimplemented,refertotheirlocationsshownonthisview.
Itisrecommendedthatviasunderpastebefilled,pluggedortented.
SYMMSYMMSEESOLDERMASKDETAILLANDPATTERNEXAMPLEEXPOSEDMETALSHOWNSCALE:15X189161724253233METALEDGESOLDERMASKOPENINGEXPOSEDMETALMETALUNDERSOLDERMASKSOLDERMASKOPENINGEXPOSEDMETALNONSOLDERMASKDEFINED(PREFERRED)SOLDERMASKDEFINEDSOLDERMASKDETAILSwww.
ti.
comEXAMPLESTENCILDESIGN32X(0.
6)32X(0.
24)28X(0.
5)(4.
8)(4.
8)(0.
775)TYP(0.
775)TYP4X(1.
35)4X(1.
35)(R0.
05)TYPWQFN-0.
8mmmaxheightRTV0032APLASTICQUADFLATPACK-NOLEAD4224386/B04/2019NOTES:(continued)6.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
SOLDERPASTEEXAMPLEBASEDON0.
125MMTHICKSTENCILSCALE:20XEXPOSEDPAD3376%PRINTEDSOLDERCOVERAGEBYAREAUNDERPACKAGESYMMSYMM189161724253233IMPORTANTNOTICEANDDISCLAIMERTIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
TheseresourcesareintendedforskilleddevelopersdesigningwithTIproducts.
Youaresolelyresponsiblefor(1)selectingtheappropriateTIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicablestandards,andanyothersafety,security,orotherrequirements.
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IMPORTANTNOTICEMailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265Copyright2021,TexasInstrumentsIncorporated
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013DS90LV8044-Channel800MbpsLVDSBuffer/RepeaterCheckforSamples:DS90LV804Inordertomaximizesignalintegrity,theDS90LV8041FEATURESfeaturesbothaninternalinputandoutput(source)23800MbpsDataRateperChannelterminationtoeliminatetheseextracomponentsfromLowOutputSkewandJittertheboard,andtoalsoplacetheterminationsascloseaspossibletoreceiverinputsanddriveroutput.
ThisLVDS/CML/LVPECLCompatibleInput,LVDSisespeciallysignificantwhendrivinglongercables.
OutputTheDS90LV804,availableintheWQFN(LeadlessOn-Chip100InputandOutputTerminationLeadframePackage)package,minimizesthe12kVESDProtectiononLVDSOutputsfootprint,andimprovessystemperformance.
Single3.
3VSupplyAnoutputenablepinisprovided,whichallowstheVeryLowPowerConsumptionusertoplacetheLVDSoutputsandinternalbiasingIndustrial-40to+85°CTemperatureRangegeneratorsinaTRI-STATE,lowpowermode.
SmallWQFNPackageFootprintThedifferentialinputsinterfacetoLVDS,andBusLVDSsignalssuchasthoseonTI's10-,16-,and18-DESCRIPTIONbitBusLVDSSerDes,aswellasCMLandLVPECL.
TheDS90LV804isafourchannel800MbpsLVDSThedifferentialinputsareinternallyterminatedwithabuffer/repeater.
Inmanylargesystems,signalsare100resistortoimproveperformanceandminimizedistributedacrosscablesandsignalintegrityishighlyboardspace.
Thisfunctionisespeciallyusefulfordependentonthedatarate,cabletype,length,andboostingsignalsoverlossycablesorpoint-to-pointtheterminationscheme.
backplaneconfigurations.
BlockandConnectionDiagramsFigure1.
DS90LV804BlockDiagram1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2TRI-STATEisaregisteredtrademarkofNationalSemiconductorCorporation.
3Allothertrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2005–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
DS90LV804SNLS195L–SEPTEMBER2005–REVISEDAPRIL2013www.
ti.
comDS90LV804WQFNPinout(TopView)Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
AbsoluteMaximumRatings(1)SupplyVoltage(VDD)0.
3Vto+4.
0VCMOSInputVoltage(EN)0.
3Vto(VDD+0.
3V)LVDSInputVoltage(2)0.
3Vto(VDD+0.
3V)LVDSOutputVoltage0.
3Vto(VDD+0.
3V)LVDSOutputShortCircuitCurrent+90mAJunctionTemperature+150°CStorageTemperature65°Cto+150°CLeadTemperature(Solder,4sec)260°CMaxPkgPowerCapacity@25°C4.
16WθJA29.
5°C/WThermalResistanceθJC3.
5°C/WPackageDeratingabove+25°C33.
3mW/°CHBM,1.
5k,100pF12kVESDLastPassingVoltage(LVDSoutputpins)EIAJ,0,200pF250VChargedDeviceModel1000VHBM,1.
5k,100pF8kVESDLastPassingVoltage(Allotherpins)EIAJ,0,200pF250VChargedDeviceModel1000V(1)Absolutemaximumratingsarethosevaluesbeyondwhichdamagetothedevicemayoccur.
Thedatabookspecificationsshouldbemet,withoutexception,toensurethatthesystemdesignisreliableoveritspowersupply,temperature,andoutput/inputloadingvariables.
TIdoesnotrecommendoperationofproductsoutsideofrecommendedoperationconditions.
(2)VIDmax<2.
4V2SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS90LV804DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013RecommendedOperatingConditionsSupplyVoltage(VCC)3.
15Vto3.
45VInputVoltage(VI)(1)0VtoVDDOutputVoltage(VO)0VtoVDDOperatingTemperature(TA)Industrial40°Cto+85°C(1)VIDmax<2.
4VElectricalCharacteristicsOverrecommendedoperatingsupplyandtemperaturerangesunlessotherspecified.
SymbolParameterConditionsMinTyp(1)MaxUnitsLVTTLDCSPECIFICATIONS(EN)VIHHighLevelInputVoltage2.
0VDDVVILLowLevelInputVoltageGND0.
8VIIHHighLevelInputCurrentVIN=VDD=VDDMAX10+10AIILLowLevelInputCurrentVIN=VSS,VDD=VDDMAX10+10ACIN1InputCapacitanceAnyDigitalInputPintoVSS3.
5pFVCLInputClampVoltageICL=18mA1.
50.
8VLVDSINPUTDCSPECIFICATIONS(INn±)VTHVCM=0.
8Vto3.
4V,DifferentialInputHighThreshold(2)0100mVVDD=3.
45VVTLVCM=0.
8Vto3.
4V,DifferentialInputLowThreshold(2)1000mVVDD=3.
45VVIDDifferentialInputVoltageVCM=0.
8Vto3.
4V,VDD=3.
45V1002400mVVCMRCommonModeVoltageRangeVID=150mV,VDD=3.
45V0.
053.
40VCIN2InputCapacitanceIN+orINtoVSS3.
5pFIINVIN=3.
45V,VDD=VDDMAX10+10AInputCurrentVIN=0V,VDD=VDDMAX10+10ALVDSOUTPUTDCSPECIFICATIONS(OUTn±)VODDifferentialOutputVoltage(2)250500600mVΔVODChangeinVODbetween3535mVComplementaryStatesRL=100externalresistorbetweenOUT+andOUTVOSOffsetVoltage(3)1.
051.
181.
475VΔVOSChangeinVOSbetween3535mVComplementaryStatesIOSOutputShortCircuitCurrentOUT+orOUTShorttoGND6090mACOUT2OutputCapacitanceOUT+orOUTtoGNDwhenTRI-STATE5.
5pFSUPPLYCURRENT(Static)ICCAllinputsandoutputsenabledandactive,TotalSupplyCurrentterminatedwithexternaldifferentialloadof100117140mAbetweenOUT+andOUT-.
ICCZTRI-STATESupplyCurrentEN=0V2.
76mA(1)TypicalparametersaremeasuredatVDD=3.
3V,TA=25°C.
Theyareforreferencepurposes,andarenotproduction-tested.
(2)DifferentialoutputvoltageVODisdefinedasABS(OUT+–OUT).
DifferentialinputvoltageVIDisdefinedasABS(IN+–IN).
(3)OutputoffsetvoltageVOSisdefinedastheaverageoftheLVDSsingle-endedoutputvoltagesatlogichighandlogiclowstates.
Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:DS90LV804DS90LV804SNLS195L–SEPTEMBER2005–REVISEDAPRIL2013www.
ti.
comElectricalCharacteristics(continued)Overrecommendedoperatingsupplyandtemperaturerangesunlessotherspecified.
SymbolParameterConditionsMinTyp(1)MaxUnitsSWITCHINGCHARACTERISTICS—LVDSOUTPUTStLHTDifferentialLowtoHighTransition210300psTimeUseanalternating1and0patternat200Mbps,measurebetween20%and80%ofVOD(4)tHLTDifferentialHightoLowTransition210300psTimetPLHDDifferentialLowtoHigh2.
03.
2nsPropagationDelayUseanalternating1and0patternat200Mbps,measureat50%VODbetweeninputtooutput.
tPHLDDifferentialHightoLow2.
03.
2nsPropagationDelaytSKD1PulseSkew|tPLHD–tPHLD|(4)2580pstSKCCDifferenceinpropagationdelay(tPLHDortPHLD)OutputChanneltoChannelSkew50125psamongalloutputchannels(4)tSKPParttoPartSkewCommonedge,partsatsametempandVCC(4)1.
1nstJITRJ-Alternating1and0at400MHz(6)1.
11.
5psrmsJitter(5)DJ-K28.
5Pattern,800Mbps(7)1535psp-pTJ-PRBS223-1Pattern,800Mbps(8)3055psp-ptONTimefromENtoOUT±changefromTRI-STATEtoLVDSOutputEnableTime300nsactive.
tOFFTimefromENtoOUT±changefromactivetoTRI-LVDSOutputDisableTime12nsSTATE.
(4)Notproductiontested.
Ensuredbystatisticalanalysisonasamplebasisatthetimeofcharacterization.
(5)Jitterisnotproductiontested,butensuredthroughcharacterizationonasamplebasis.
(6)RandomJitter,orRJ,ismeasuredRMSwithahistogramincluding1500histogramwindowhits.
Theinputvoltage=VID=500mV,50%dutycycleat400MHz,tr=tf=50ps(20%to80%).
(7)DeterministicJitter,orDJ,ismeasuredtoahistogrammeanwithasamplesizeof350hits.
Theinputvoltage=VID=500mV,K28.
5patternat800Mbps,tr=tf=50ps(20%to80%).
TheK28.
5patternisrepeatingbitstreamsof(00111110101100000101).
(8)TotalJitter,orTJ,ismeasuredpeaktopeakwithahistogramincluding3500windowhits.
StimulusandfixtureJitterhasbeensubtracted.
Theinputvoltage=VID=500mV,223-1PRBSpatternat800Mbps,tr=tf=50ps(20%to80%).
TypicalApplication4SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS90LV804DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013APPLICATIONINFORMATIONINTERNALTERMINATIONSTheDS90LV804hasintegratedterminationresistorsonboththeinputandoutputs.
Theinputshavea100resistoracrossthedifferentialpair,placingthereceiverterminationascloseaspossibletotheinputstageofthedevice.
TheLVDSoutputsalsocontainanintegrated100ohmterminationresistor,thisresistorisusedtoreducetheeffectsofNearEndCrosstalk(NEXT)anddoesnottaketheplaceofthe100ohmterminationattheinputstothereceivingdevice.
Theintegratedterminationsimprovesignalintegrityanddecreasetheexternalcomponentcountresultinginspacesavings.
OUTPUTCHARACTERISTICSTheoutputcharacteristicsoftheDS90LV804havebeenoptimizedforpoint-to-pointbackplaneandcableapplications,andarenotintendedformultipointormultidropsignaling.
TRI-STATEMODETheENinputactivatesahardwareTRI-STATEmode.
WhentheTRI-STATEmodeisactive(EN=L),allinputandoutputbuffersandinternalbiascircuitryarepoweredoffanddisabled.
Outputsaretri-statedinTRI-STATEmode.
WhenexitingTRI-STATEmode,thereisadelayassociatedwithturningonbandgapreferencesandinput/outputbuffercircuitsasindicatedintheLVDSOutputSwitchingCharacteristicsINPUTFAILSAFEBIASINGExternalpullupandpulldownresistorsmaybeusedtoprovideenoughofanoffsettoenableaninputfailsafeunderopen-circuitconditions.
ThisconfigurationtiesthepositiveLVDSinputpintoVDDthruapullupresistorandthenegativeLVDSinputpinistiedtoGNDbyapulldownresistor.
Thepullupandpulldownresistorsshouldbeinthe5kto15krangetominimizeloadingandwaveformdistortiontothedriver.
Thecommon-modebiaspointideallyshouldbesettoapproximately1.
2V(lessthan1.
75V)tobecompatiblewiththeinternalcircuitry.
PleaserefertoapplicationnoteAN-1194"FailsafeBiasingofLVDSInterfaces"formoreinformation.
INPUTINTERFACINGTheDS90LV804acceptsdifferentialsignalsandallowsimpleACorDCcoupling.
Withawidecommonmoderange,theDS90LV804canbeDC-coupledwithallcommondifferentialdrivers(thatis,LVPECL,LVDS,CML).
Figure2,Figure3,andFigure4illustratetypicalDC-coupledinterfacetocommondifferentialdrivers.
NotethattheDS90LV804inputsareinternallyterminatedwitha100Ωresistor.
Figure2.
TypicalLVDSDriverDC-CoupledInterfacetoDS90LV804InputCopyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:DS90LV804DS90LV804SNLS195L–SEPTEMBER2005–REVISEDAPRIL2013www.
ti.
comFigure3.
TypicalCMLDriverDC-CoupledInterfacetoDS90LV804InputFigure4.
TypicalLVPECLDriverDC-CoupledInterfacetoDS90LV804InputOUTPUTINTERFACINGTheDS90LV804outputssignalsthatarecomplianttotheLVDSstandard.
TheiroutputscanbeDC-coupledtomostcommondifferentialreceivers.
Figure5illustratestypicalDC-coupledinterfacetocommondifferentialreceiversandassumesthatthereceivershavehighimpedanceinputs.
WhilemostdifferentialreceivershaveacommonmodeinputrangethatcanaccommodateLVDScompliantsignals,itisrecommendedtocheckrespectivereceiver'sdatasheetpriortoimplementingthesuggestedinterfaceimplementation.
Figure5.
TypicalDS90LV804OutputDC-CoupledInterfacetoanLVDS,CMLorLVPECLReceiver6SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS90LV804DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013PINDESCRIPTIONSPinWQFNPinI/O,TypeDescriptionNameNumberDIFFERENTIALINPUTSIN0+9I,LVDSChannel0invertingandnon-invertingdifferentialinputs.
IN010IN1+11I,LVDSChannel1invertingandnon-invertingdifferentialinputs.
IN112IN2+13I,LVDSChannel2invertingandnon-invertingdifferentialinputs.
IN214IN3+15I,LVDSChannel3invertingandnon-invertingdifferentialinputs.
IN316DIFFERENTIALOUTPUTSOUT0+32O,LVDSChannel0invertingandnon-invertingdifferentialoutputs(1)OUT031OUT1+30O,LVDSChannel1invertingandnon-invertingdifferentialoutputs(1)OUT129OUT2+28O,LVDSChannel2invertingandnon-invertingdifferentialoutputs(1)OUT227OUT3+26O,LVDSChannel3invertingandnon-invertingdifferentialoutputs(1)OUT3-25DIGITALCONTROLINTERFACEEN8I,LVTTLEnablepin.
WhenENisLOW,thedriverisdisabledandtheLVDSoutputsareinTRI-STATE.
WhenENisHIGH,thedriverisenabled.
LVCMOS/LVTTLlevelinput.
POWERVDD3,4,6,7,19,20,21,22I,PowerVDD=3.
3V,±5%GND1,2,5,17,18(2)I,PowerGroundreferenceforLVDSandCMOScircuitry.
FortheWQFNpackage,theDAPisusedastheprimaryGNDconnectiontothedevice.
TheDAPistheexposedmetalcontactatthebottomoftheWQFN-32package.
Itshouldbeconnectedtothegroundplanewithatleast4viasforoptimalACandthermalperformance.
Thepinnumberslistedshouldalsobetiedtogroundforproperbiasing.
N/C23,24NoConnect(1)TheLVDSoutputsdonotsupportamultidrop(BLVDS)environment.
TheLVDSoutputcharacteristicsoftheDS90LV804devicehavebeenoptimizedforpoint-to-pointbackplaneandcableapplications.
(2)NotethatfortheWQFNpackagetheGNDisconnectedthrutheDAPonthebacksideoftheWQFNpackageinadditiontogroundingactualpinsonthepackageaslisted.
Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:DS90LV804DS90LV804SNLS195L–SEPTEMBER2005–REVISEDAPRIL2013www.
ti.
comTypicalPerformanceCharacteristicsA.
DynamicpowersupplycurrentwasmeasuredwhilerunningaclockorPRBS223-1patternwithall4channelsactive.
VCC=3.
3V,TA=+25°C,VID=0.
5V,VCM=1.
2VFigure6.
PowerSupplyCurrentvsBitDataRatePACKAGINGINFORMATIONTheLeadlessLeadframePackage(WQFN)isaleadframebasedchipscalepackage(CSP)thatmayenhancechipspeed,reducethermalimpedance,andreducetheprintedcircuitboardarearequiredformounting.
ThesmallsizeandverylowprofilemakethispackageidealforhighdensityPCBsusedinsmall-scaleelectronicapplicationssuchascellularphones,pagers,andhandheldPDAs.
TheWQFNpackageisofferedinthenoPullbackconfiguration.
InthenoPullbackconfigurationthestandardsolderpadsextendandterminateattheedgeofthepackage.
Thisfeatureoffersavisiblesolderfilletafterboardmounting.
TheWQFNhasthefollowingadvantages:LowthermalresistanceReducedelectricalparasiticsImprovedboardspaceefficiencyReducedpackageheightReducedpackagemassFormoredetailsaboutWQFNpackagingtechnology,refertoapplicationsnoteAN-1187,"LeadlessLeadframePackage".
8SubmitDocumentationFeedbackCopyright2005–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS90LV804DS90LV804www.
ti.
comSNLS195L–SEPTEMBER2005–REVISEDAPRIL2013REVISIONHISTORYChangesfromRevisionK(April2013)toRevisionLPageChangedlayoutofNationalDataSheettoTIformat8Copyright2005–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:DS90LV804PACKAGEOPTIONADDENDUMwww.
ti.
com11-Jan-2021Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesDS90LV804TSQNRNDWQFNRTV321000Non-RoHS&GreenCallTICallTI-40to85804TSQDS90LV804TSQ/NOPBACTIVEWQFNRTV321000RoHS&GreenSNLevel-3-260C-168HR-40to85804TSQDS90LV804TSQX/NOPBACTIVEWQFNRTV324500RoHS&GreenSNLevel-3-260C-168HR-40to85804TSQ(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
Effortsareunderwaytobetterintegrateinformationfromthirdparties.
TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.
TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.
PACKAGEOPTIONADDENDUMwww.
ti.
com11-Jan-2021Addendum-Page2InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantDS90LV804TSQWQFNRTV321000178.
012.
45.
35.
31.
38.
012.
0Q1DS90LV804TSQ/NOPBWQFNRTV321000178.
012.
45.
35.
31.
38.
012.
0Q1DS90LV804TSQX/NOPBWQFNRTV324500330.
012.
45.
35.
31.
38.
012.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com29-Sep-2019PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)DS90LV804TSQWQFNRTV321000210.
0185.
035.
0DS90LV804TSQ/NOPBWQFNRTV321000210.
0185.
035.
0DS90LV804TSQX/NOPBWQFNRTV324500367.
0367.
035.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com29-Sep-2019PackMaterials-Page2www.
ti.
comPACKAGEOUTLINEC5.
154.
855.
154.
850.
80.
70.
050.
002X3.
528X0.
52X3.
532X0.
50.
332X0.
300.
183.
10.
1(0.
1)TYPWQFN-0.
8mmmaxheightRTV0032APLASTICQUADFLATPACK-NOLEAD4224386/B04/20190.
08C0.
1CAB0.
05NOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thepackagethermalpadmustbesolderedtotheprintedcircuitboardforthermalandmechanicalperformance.
PIN1INDEXAREASEATINGPLANEPIN1IDSYMMEXPOSEDTHERMALPADSYMM189161724253233SCALE2.
500ABwww.
ti.
comEXAMPLEBOARDLAYOUT28X(0.
5)(1.
3)(1.
3)(R0.
05)TYP0.
07MAXALLAROUND0.
07MINALLAROUND32X(0.
6)32X(0.
24)(4.
8)(4.
8)(3.
1)(3.
1)(0.
2)TYPVIAWQFN-0.
8mmmaxheightRTV0032APLASTICQUADFLATPACK-NOLEAD4224386/B04/2019NOTES:(continued)4.
Thispackageisdesignedtobesolderedtoathermalpadontheboard.
Formoreinformation,seeTexasInstrumentsliteraturenumberSLUA271(www.
ti.
com/lit/slua271).
5.
Viasareoptionaldependingonapplication,refertodevicedatasheet.
Ifanyviasareimplemented,refertotheirlocationsshownonthisview.
Itisrecommendedthatviasunderpastebefilled,pluggedortented.
SYMMSYMMSEESOLDERMASKDETAILLANDPATTERNEXAMPLEEXPOSEDMETALSHOWNSCALE:15X189161724253233METALEDGESOLDERMASKOPENINGEXPOSEDMETALMETALUNDERSOLDERMASKSOLDERMASKOPENINGEXPOSEDMETALNONSOLDERMASKDEFINED(PREFERRED)SOLDERMASKDEFINEDSOLDERMASKDETAILSwww.
ti.
comEXAMPLESTENCILDESIGN32X(0.
6)32X(0.
24)28X(0.
5)(4.
8)(4.
8)(0.
775)TYP(0.
775)TYP4X(1.
35)4X(1.
35)(R0.
05)TYPWQFN-0.
8mmmaxheightRTV0032APLASTICQUADFLATPACK-NOLEAD4224386/B04/2019NOTES:(continued)6.
Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
SOLDERPASTEEXAMPLEBASEDON0.
125MMTHICKSTENCILSCALE:20XEXPOSEDPAD3376%PRINTEDSOLDERCOVERAGEBYAREAUNDERPACKAGESYMMSYMM189161724253233IMPORTANTNOTICEANDDISCLAIMERTIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
TheseresourcesareintendedforskilleddevelopersdesigningwithTIproducts.
Youaresolelyresponsiblefor(1)selectingtheappropriateTIproductsforyourapplication,(2)designing,validatingandtestingyourapplication,and(3)ensuringyourapplicationmeetsapplicablestandards,andanyothersafety,security,orotherrequirements.
Theseresourcesaresubjecttochangewithoutnotice.
TIgrantsyoupermissiontousetheseresourcesonlyfordevelopmentofanapplicationthatusestheTIproductsdescribedintheresource.
Otherreproductionanddisplayoftheseresourcesisprohibited.
NolicenseisgrantedtoanyotherTIintellectualpropertyrightortoanythirdpartyintellectualpropertyright.
TIdisclaimsresponsibilityfor,andyouwillfullyindemnifyTIanditsrepresentativesagainst,anyclaims,damages,costs,losses,andliabilitiesarisingoutofyouruseoftheseresources.
TI'sproductsareprovidedsubjecttoTI'sTermsofSale(https:www.
ti.
com/legal/termsofsale.
html)orotherapplicabletermsavailableeitheronti.
comorprovidedinconjunctionwithsuchTIproducts.
TI'sprovisionoftheseresourcesdoesnotexpandorotherwisealterTI'sapplicablewarrantiesorwarrantydisclaimersforTIproducts.
IMPORTANTNOTICEMailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265Copyright2021,TexasInstrumentsIncorporated
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