dVLDO2ddd27

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Datasheet:AS8650BHigh-efficientPowerManagementDevicewithHigh-speedCANInterfacePleasebepatientwhileweupdateourbrandimageasaustriamicrosystemsandTAOSarenowams.
AS8650BHigh-efficientPowerManagementDevicewithHigh-speedCANInterfacewww.
ams.
com/AS8650Revision1.
11-461GeneralDescriptionTheAS8650BisacompanionICwhichcombinespowermanagementfunctionsandafullyconforminghigh-speedCANTransceiverinonehighperformanceanalogdeviceforautomotiveapplications.
TheAS8650Bispoweredbythebattery,provides4outputvoltagelevelsofwhich3outputsintherangeof1.
8Vto3.
3Vwithamaximumcurrentconsumptionupto120mAattheLDOvoltageregulatoroutputs.
AnintegratedDCDCconverterwithaveryhighefficiencyforthe5Voutputsuppliesthe3voltageregulatorsandensuresavoltagestabilityof±2.
5%.
ThecombinationofDCDCconverterwithlow-drop-outvoltageregulatorsmakestheAS8650BsuitableforallAutomotiveControlUnitswherepowerefficiencyisamust.
TheAS8650Bprovidesahigh-speedCANinterfaceupto1MbpscommunicationrateconformingtoISO11898-5.
TheAS8650Bprovideswake-upviaremotewake-upatCANbuslinesandalocalwakepin.
Thewatchdogunitprovidesthreedifferenttimingfunctions:start-up,window-andtimeoutwatchdog;configurableviatheSPIandICinterface.
Voltagemonitoringisimplementedforthebatterysupply,DCDCoutputandthe3LDOregulatoroutputs.
UndervoltagewillbesignalledontheINTNpintothemicrocontroller.
AlldiagnosticsandstatusflagscanbeaccessedwiththeSPIinterface.
Theproductisavailableina36-pinQFN(6x6x0.
9)package.
2KeyFeaturesDCDCconverterfor5VoutputwithveryhighefficiencyThreevoltageregulatorsproviding3.
3V,2.
8Vand1.
8Vwithaccuracybetterthan2.
5%(Twoareadjustablethroughfactorysettings).
High-speedCANinterface(ISO11898-5)withremotewake-upComprehensivevoltagemonitoringConfigurablewatchdogfunctionsforstart-up,operation,andstandbyAutomaticthermalshutdownprotectionExcellentEMCperformancewithoutstandingswitchingtechnologyfortheDCDCconverterAmbienttemperaturerangefrom-40°Cto+105°CinmaximumloadconditionsLead-free36-pinQFN(6x6x0.
9)package3ApplicationsTheAS8650Bprovideshighefficientandflexiblepowersupplytogetherwithstate-of-the-arthigh-speedCANInterfaceforautomotivecontrolunits.
ThedeviceispincompatiblewithAS8550(LINinterface)inordertochangefromCANtoLINeasy.
DC/DCConverter5VI2CSPIHigh-speedCANTransceiverWatchdogCSSPISCLKI2C/SCLKSPII2C_ENCANHRxDTxDRESETFBConfigurableVoltageRegulatorConfigurableVoltageRegulatorConfigurableVoltageRegulatorVREGDigitalLogicINTNWAKEV5V_LDO1V5V_LDO2V5V_LDO3GNDVSUPLXVREGVREGSPLITCANLSDAI2C/SDISPISDOSPIAS8650BFigure1.
AS8650BBlockDiagramwww.
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12-46AS8650BDatasheet-ContentsContents1GeneralDescription.
12KeyFeatures.
13Applications.
14PinAssignments.
44.
1PinDescriptions.
45AbsoluteMaximumRatings.
66ElectricalCharacteristics.
76.
1ElectricalSystemSpecification.
86.
2DCDCConverter86.
3LowDropOutRegulators.
96.
4CANTransceiver106.
4.
1TimingDiagrams.
126.
5UndervoltageDetection.
136.
6DigitalTimingSpecification136.
6.
1SystemSpecificationandTimings.
167DetailedDescription.
177.
1OperatingModesandStates.
177.
1.
1NormalMode177.
1.
2Receive-OnlyMode177.
1.
3StandbyMode.
177.
1.
4SleepMode.
177.
2PowerManagementStrategy.
177.
3StateDiagram.
207.
4InitializationSequence.
207.
5DCDCConverter227.
6VoltageRegulatorLDO1.
227.
7VoltageRegulatorLDO2.
227.
8VoltageRegulatorLDO3.
227.
9Over-TemperatureMonitor227.
10UndervoltageReset.
227.
11ResetBlock.
237.
12CANTransceiver247.
12.
1BUSDriver.
247.
12.
2NormalReceiver.
247.
12.
3LowPowerReceiver.
247.
12.
4OperatingModes247.
12.
5LocalWake-upEvent.
247.
12.
6RemoteWake-up.
257.
13InternalFlags.
267.
13.
1VSUP_UV_flag267.
13.
2VSUP_POK_flag.
267.
13.
3V5V_UV_flag267.
13.
4V5V_POK_flag.
267.
13.
5VLDO2_UV_flag267.
13.
6VLDO2_POK_flag.
26www.
ams.
com/AS8650Revision1.
13-46AS8650BDatasheet-Contents7.
13.
7VLDO3_UV_flag267.
13.
8VLDO3_POK_flag.
267.
13.
9BUSWake_upFlag277.
13.
10LocalWake_upFlag.
277.
13.
11OVT_WarningFlag.
277.
13.
12OVT_RecoverFlag.
277.
13.
13BusFailureFlags.
277.
13.
14LocalFailureFlags277.
14Watchdog(WD)287.
14.
1Start-upWatchdogBehavior.
287.
14.
2WindowWatchdogBehavior.
287.
14.
3TimeoutWatchdogBehavior297.
15InterruptGeneration297.
16StatusRegisters.
308ApplicationInformation318.
1SerialPeripheralInterface.
318.
1.
1SPIWriteOperation.
328.
1.
2SPIReadOperation.
338.
1.
3SPITimingDiagram.
348.
2Inter-IntegratedCircuit(IC)Interface.
358.
2.
1ICSlaveAddress.
358.
2.
2ICWriteOperation.
358.
2.
3ICReadOperation.
368.
3RegisterSpace.
389PackageDrawingsandMarkings4310OrderingInformation.
45www.
ams.
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14-46AS8650BDatasheet-PinAssignments4PinAssignmentsFigure2.
PinAssignments(TopView)4.
1PinDescriptionsTable1.
PinDescriptionsPinPinNamePinTypeDescription1,2,3VSUPPowerSupplyInputPowerSupply4GND_DCDC5GND6WAKEAnalogInput/Outputhigh-voltageLocalwakerequest(high-voltageinput)7CANHHighlevelCANbusline8CANLLowlevelCANbusline9GND_CANPowerSupplyInputPowersupply10SPLITAnalogInput/Outputhigh-voltageCommon-modestabilizationoutputWAKECANHCANLVSUPRxDSDOSPICSSPIAS8650BTxD27SCLKI2C(SCLKSPI)SDAI2C/SDISPI2625242322212019302928363534333231QFN6x6x0.
9123456789161718101112131415LXFBV5V_LDO2VLDO1VLDO2VLDO3INTNRESETGND(Exposedpad)RESERVEDRESERVEDRESERVEDVLDO3FBSPLITVSUPVSUPGND_CANLXLXV5V_LDO3VLDO2FBVLDO1FBV5V_LDO1GND_DCDCGNDI2C_ENwww.
ams.
com/AS8650Revision1.
15-46AS8650BDatasheet-PinAssignments11I2C_ENDigitalInputIC/SPIselectsignal(High=IC,Low=SPI)12SDAI2C/SDISPIDigitalInput/Output/DigitalInputUnidirectionalforSPI,BidirectionalforIC13SDOSPIDigitalOutputSPIdataout14SCLKI2C/SCLKSPIDigitalInputSerialclock(MultiplexedforICandSPI)unidirectional15CSSPIDigitalinputwithpull-upSPIchipselect16RxDDigitaloutputwithpull-upCANTransceiverreceivesignal17INTNDigitalOutputActivelowinterrupttoC.
Generatedifstatus/diagnosticisupdated.
18TxDDigitalinputwithpull-upCANTransceivertransmitsignal19RESETDigitalOutputDigitalOutputreferencedtoVLDO1,activelow20ReservedPinwithDigital/AnalogInput/Open-Drain-OutputReserved21AnalogInput/Output2223VLDO1PowerSupplyInputRegulatedvoltageoutput24VLDO1FBPinwithDigital/AnalogInput/Open-Drain-OutputRegulatedvoltagefeedback25VLDO2FBPinwithDigital/AnalogInput/Open-Drain-OutputRegulatedvoltagefeedback26VLDO2PowerSupplyInputRegulatedvoltageoutput27VLDO3FBPinwithDigital/AnalogInput/Open-Drain-OutputRegulatedvoltagefeedback28VLDO3PowerSupplyInputRegulatedvoltageoutput29V5V_LDO1Step-downconverter5Voutput,supplyforLDO130V5V_LDO3Step-downconverter5Voutput,supplyforLDO331V5V_LDO2Step-downconverter5Voutput,supplyforLDO232FB(DCDC)AnalogInputDCDCoutputvoltagefeedback33,34,35LX(DCDC)PowerSupplyInputDCDCoutput0GNDExposedpad(GND)Table1.
PinDescriptionsPinPinNamePinTypeDescriptionwww.
ams.
com/AS8650Revision1.
16-46AS8650BDatasheet-AbsoluteMaximumRatings5AbsoluteMaximumRatingsStressesbeyondthoselistedinTable2maycausepermanentdamagetothedevice.
Thesearestressratingsonly.
FunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedinElectricalCharacteristicsonpage7isnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
Table2.
AbsoluteMaximumRatings11.
AllvoltagesmentionedabovearereferredwithrespecttogroundreferencevoltageVGND.
ParameterMinMaxUnitsNotesElectricalParametersVoltageatpositivesupplypin(VVSUP)-0.
340VVoltageatpinV5V_LDO1,V5V_LDO2,V5V_LDO3,VLDO1,VLDO2,VLDO3,FB,VLDO1FB,VLDO2FB,VLDO3FB-0.
37VVoltageatpinCANH,CANL,SPLIT-40+40VVoltageatpinLX,WAKE-0.
3VVSUP+0.
3VVoltageatpinRESET,INTN,RxD,TxD,CS,SCLK,SDO,SDA/SDI,I2C_EN-0.
34.
5VInputSupplyslew-rate(Vsup_slew)1V/sInputpowersupplyramprateElectrostaticDischargeElectrostaticdischargevoltageAEC-Q100-002humanbodymodelstandard(ESD)±2kVAllpinsexceptVSUP,GND,CANH,CANL,WAKE,SPLIT±4VSUP,GND,WAKE,SPLIT±8CANH,CANLLatch-UpImmunity-100+100mAAEC-Q100-004ContinuousPowerDissipationMaximumpowerdissipation(Ptot)1.
2WTemperatureRangesandStorageConditionsJunctiontemperature(TJ)170CStoragetemperature(Tstg)-55+150CThermalresistanceMLFpackage(Rthj_36)30C/WSEMIG42-88Packagebodytemperature(TBODY)260CThereflowpeaksolderingtemperature(bodytemperature)specifiedisinaccordancewithIPC/JEDECJ-STD-020"Moisture/ReflowSensitivityClassificationforNon-HermeticSolidStateSurfaceMountDevices".
TheleadfinishforPb-freeleadedpackagesismattetin(100%Sn).
MoistureSensitivityLevel3Representsamaximumfloorlifetimeof168hwww.
ams.
com/AS8650Revision1.
17-46AS8650BDatasheet-ElectricalCharacteristics6ElectricalCharacteristicsTable3.
ElectricalCharacteristicsSymbolParameterConditionsMinTypMaxUnitsOperatingConditionsVSUPPositivesupplyvoltageNormaloperatingcondition618VGNDGroundInreferencetoallthevoltages0VTAMBAmbienttemperatureJunctiontemperature(TJ)≤150C(atfull-load)-40105CIsuppSupplycurrent,NormalmodeVSUP=6V,LDOsatfullload,DCDCload=390mA,CANdominant425mAVSUP=18V,LDOsatfullload,DCDCload=390mA,CANdominant,notproductiontested.
150VSUP=16V,LDOsatfullload,CANdominant170CSVt-Negative-GoingThresholdVLDO1=3.
3V1.
121.
52VVt+Positive-GoingThreshold1.
772.
23VIlil_csPullupcurrentInCSpad,PulleduptoVLDO1-60-15ASDOVOHHighleveloutputvoltage2.
5VVOLLowleveloutputvoltageVSUP≥6V0.
4VIOOutputdrivecurrent4mASDA/SDIVIHHighlevelinputvoltage0.
7*VLDO1VVILLowlevelinputvoltage0.
3*VLDO1VVOLLowleveloutputvoltage0.
4VSCLKVIHHighlevelinputvoltageOpen-drain,external500Ωpull-up0.
7*VLDO1VVILLowlevelinputvoltage0.
3*VLDO1VRESET,INTNVOHHighleveloutputvoltage2.
5VVOLLowleveloutputvoltageVSUP≥6V0.
4VIOOutputdrivecurrent4mATxDVIHHighlevelinputvoltage2.
0VVILLowlevelinputvoltage0.
8VIOOutputdrivecurrentVSUP≥6V1mAIlilPull-upcurrentTxDpulleduptoVLDO1withcontrolRxDpulleduptoVLDO1-60-15Awww.
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18-46AS8650BDatasheet-ElectricalCharacteristics6.
1ElectricalSystemSpecification-40°Ccom/AS8650Revision1.
19-46AS8650BDatasheet-ElectricalCharacteristics6.
3LowDropOutRegulators-40°CILOAD>1mA),V5V=5V-0.
15+0.
15mV/mACL2OutputCapacitor(Ceramic)X7Rtype25FESR20.
020.
1ΩCL1X7Rtype100220nFESR10.
01ΩTable7.
VLDO21BlockSpecifications1.
Factorysetting:VOUT=2.
8V.
SymbolParameterConditionsMinTypMaxUnitsV5VInputVoltageRange4.
7555.
25VIOUTLDO2OutputcurrentGuaranteedbydesign.
Notproductiontested.
0120mAVLDO2OutputVoltageRangeVOUT(typ)dependsonthetrimcodeasinOTPregistermapping.
Defaultcodegives2.
8V0.
975*VOUTVOUT1.
025*VOUTVICC_SHOutputShortCircuitCurrentNormalmode300mAdVLDO2LineRegulationΔVLDO2/ΔV5V(static)fortheinputrange,ILOAD=100mA-88mV/VLOREG_NMLoadRegulationΔVLDO2(for120mA>ILOAD>1mA)-0.
15+0.
15mV/mACL2OutputCapacitor(Ceramic)X7Rtype25FESR20.
020.
1ΩCL1X7Rtype100220nFESR10.
01Ωwww.
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110-46AS8650BDatasheet-ElectricalCharacteristics6.
4CANTransceiver6VILOAD>1mA)-0.
15+0.
15mV/mACL2OutputCapacitor(Ceramic)X7Rtype25FESR20.
020.
1ΩCL1X7Rtype100220nFESR10.
01Ω1.
Factorysetting:VOUT=1.
8V.
Table9.
DCElectricalCharacteristicsSymbolParameterConditionsMinTypMaxUnitsDriverCANH_domDominantoutputvoltageV_TxD=0V34.
25VCANL_dom0.
51.
75VVO_dom_mMatchingdominantoutputvoltageV5V_LDO1-V_CANH-V_CANL-0.
10.
15VVO_diffDifferentialoutputvoltageV_CANH-V_CANL45Ωcom/AS8650Revision1.
111-46AS8650BDatasheet-ElectricalCharacteristicsV_RxD_hysDifferentialreceiverhysteresisvoltage-12VCommonmodeinputresistanceTestedinReceive-onlymode1535kΩR_IN_cm_mCommonmodeinputresistancematchingV_CANH=V_CANL(TestedinReceive-onlymode)-3+3%R_IN_diffDifferentialinputresistanceTestedinReceive-onlymode2575kΩVO_SPLITOutputvoltageonSPLITpinNormalmode-500Acom/AS8650Revision1.
112-46AS8650BDatasheet-ElectricalCharacteristics6.
4.
1TimingDiagramsFigure3.
TimingDiagramandHysteresisofCANReceiverTxDCANH_domCANL_domVo_recVin_diffRxD2.
5V0.
4V0.
9V0.
5Vt_TxD_BUS_ont_TxD_BUS_offt_BUS_on_RxDt_BUS_off_RxDt_TxD_RxDt_TxD_RxDV_RxDV_RxD_th(high)V_RxD_th(low)V_RxD_hysVin_diffwww.
ams.
com/AS8650Revision1.
113-46AS8650BDatasheet-ElectricalCharacteristics6.
5UndervoltageDetection6.
6DigitalTimingSpecificationSPIProtocol.
Table12.
UndervoltageDetectionSymbolParameterConditionsMinTypMaxUnitsVSUP_PORVSUPPoweronResetthresholdonRisingedgeofVSUP5.
095.
55.
91VVSUP_RESETVSUPPoweronResetthresholdoff(MasterResetforDevice)4.
494.
855.
21VVSUP_POKTHVSUPundervoltagethresholdoffVSUPrisingedge(Brownoutresetthreshold)4.
955.
355.
75VVSUP_UVTHVSUPundervoltagethresholdon(CANbusinrecessivestate)VSUPfallingedge(Brownoutresetthreshold)4.
6255.
05.
375VV5V_POKTHV5VundervoltagethresholdoffRisingedgeofV5V4.
164.
54.
84VV5V_UVTHV5VundervoltagethresholdonFallingedgeofV5V3.
84.
14.
4VVLDO_POKTHLDOundervoltagethresholdoff(VLDO1,VLDO2andVLDO3)PercentvalueiswithrespecttoLDOoutput.
RisingedgeofLDO878991%VLDO_UVTHLDOundervoltagethresholdon(VLDO1,VLDO2andVLDO3)PercentvalueiswithrespecttoLDOoutput.
FallingedgeofLDO788082%trrSpikefilteronVLDO1Toremovedisturbance248stResResetdelaytime4812msTable13.
SPITimingParametersSymbolParameterConditionsMinTypMaxUnitsGeneralBRSPIBitrate1MbpsTSCLKHClockhightime500nsTSCLKLClocklowtime500nsWriteOperationParameterstDISDatainsetuptime20nstDIHDatainholdtime10nsTCSHCSholdtime40nsReadOperationParameterstDODDataoutdelay80nstDOHZDataouttohighimpedancedelayTimefortheSPItoreleasetheSDObus80nsTimingParametersforSCLKPolarityIdentificationtCPSClocksetuptime(CLKpolarity)SetuptimeofSCLKwithrespecttoCSfallingedge20nstCPHDClockholdtime(CLKpolarity)HoldtimeofSCLKwithrespecttoCSfallingedge20nswww.
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114-46AS8650BDatasheet-ElectricalCharacteristicsICProtocol.
ElectricalcharacteristicsofSDA&SCLKbuslinesforF/Smode1.
Cb=capacitanceofonebuslineinpF.
2.
ThemaximumtffortheSDAandSCLKbuslinesquotedinTable15(300ns)islongerthanthespecifiedmaximumtoffortheoutputstages(250ns).
ThisallowsforanyseriesprotectionresistorstobeconnectedbetweentheSDA/SCLKpinsandtheSDA/SCLKbuslineswithoutexceedingthemaximumspecifiedtf.
3.
I/OpinsofFast-modedevicesmustnotobstructtheSDAandSCLKlinesifVLDO1isswitchedoff.
Table14.
ICElectricalParametersSymbolParameterStandardFastUnitsMinMaxMinMaxVILLowlevelinputvoltage:VLDO1relatedinputlevels0.
3V*LDO10.
3V*LDO1VVIHHighlevelinputvoltage:VLDO1-relatedinputlevels0.
7V*LDO10.
7V*LDO1VVhysHysteresisofSchmitttriggerinputn/an/a0.
05V*LDO1VVOL1Lowleveloutputvoltage(opendrainoropencollector)at3mAsinkcurrent0.
40.
4VtofOutputfalltimefromVIHmintoVILmaxwithabuscapacitancefrom10pFto400pF250(seeFootnote2)20+0.
1Cb(seeFootnote1)250(seeFootnote2)ns(labtestedonly)tSPPulsewidthofspikeswhichmustbesuppressedbytheinputfiltern/an/a50nsIiInputcurrentofeachI/Opinwithaninputvoltagebetween0.
1VLDO1and0.
9VLDO1maximum-1010-10(seeFootnote3)10(seeFootnote3)ACiCapacitanceforeachI/Opin1010pF(guaranteedbydesign)www.
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115-46AS8650BDatasheet-ElectricalCharacteristicsCharacteristicsoftheSDAandSCLKBusLinesforF/SModeICBus.
1.
AllvaluesreferredtoVIHminandVIlmaxlevels(seeTable14).
2.
AfastmodeICbusdevicecanbeusedinStandardmodeICbussystem,buttherequirementtSU_DAT≥250nsmustthenbemet.
ThiswillautomaticallybethecaseifthedevicedonotstretchthelowperiodoftheSCLKsignal.
IfsuchadevicedoesstretchthelowperiodoftheSCLKsignal,itmustoutputthenextdatabittotheSDAlinetrmax.
TSU_DAT=1000+250=1250ns(accordingtostandardmodeICbusspecification)beforetheSCLKlinereleased.
3.
ThemaximumtHD;DAThasonlytobemetifthedevicedoesnotstretchthelowperiod(tLOW)oftheSCLKsignal.
4.
Cb=totalcapacitanceofonebuslineinpF.
IfmixedwithHs-modedevices,fasterfall-timesaccordingtoTable14allowed.
5.
Thisdeviceinternallyprovidesaholdtimeofatleast300nsfortheSDAsignaltobridgetheundefinedregionofthefallingedgeoftheSCLK.
Table15.
ICTimingParametersSymbolParameterStandardFastUnitsMinMaxMinMax(seeFootnote1)fSCLKSCLKclockfrequency01000400kHztHD_STAHoldtime(repeated)STARTcondition.
Afterthisperiod,thefirstclockpulseisgenerated4-0.
6-stLOWLowperiodoftheSCLKclock4.
7-1.
3-stHIGHHighperiodoftheSCLKclock4.
0-0.
6-stSU_STASet-uptimeforarepeatedSTARTcondition4.
7-0.
6-stSU_DATDataset-uptime250-100(seeFootnote2)-nstHD_DATDatahold-time0(seeFootnote5)3450(seeFootnote3)0(seeFootnote5)900(seeFootnote3)nstrRisetimeofSDAandSCLKsignals-100020+0.
1Cb(seeFootnote4)300nstfFalltimeofSDAandSCLKsignals-30020+0.
1Cb(seeFootnote4)300nstSU_STOSet-uptimeforSTOPcondition4.
0-0.
6-stBUFBusfreetimebetweenaSTOPandSTARTcondition4.
7-1.
3-sCbCapacitiveloadforeachbusline-400-400pFVnLNoisemarginattheLowlevelforeachconnecteddevice(includinghysteresis)0.
1V*LDO1-0.
1V*LDO1-VnHNoisemarginattheHighlevelforeachconnecteddevice(includinghysteresis)0.
2V*LDO1-0.
2V*LDO1-www.
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116-46AS8650BDatasheet-ElectricalCharacteristics6.
6.
1SystemSpecificationandTimingsTable16.
SystemTimingParametersSymbolParameterConditionsMinTypMaxUnitsModeTransitionRelatedTimingTPOSTPower-uptoStandbymodeResettimeincluded,Start-upwatchdognotincluded70msTSTNOStandbytoNormalmode10msTSLSTSleeptoStandbymodeResettimeincluded50msWake-upTimingTdom(wake)MinimumdominantpulseforCANwake-updetection(remotewake)5sTrec(wake)MinimumrecessivepulseforCANwake-updetection(remotewake)5sTL_wakeTimebetweenedgeonWAKEpintolocalwakedetection32sTLW_filterTimebetweenedgeonWAKEpintoWAKE_LOCALsignal(FilteronWAKEpin)0.
755sTR_wakeRemotewakedetectiontimefromthevalidpatterndetection24sTINTNINTNpinhightime7sV_LWUTHLocalWAKEthresholdinput24VLocalFailureRelatedTimingTTxDC(dom)TxDdominanttimeoutperiod60010001400sTBUSC(dom)BUSdominantclampingtimeoutperiod60010001400sWatchdogTiming&TimeoutsTWD(init)Start-upWatchdogtimeout(initializationtime)300msTwd_trigWindowwatchdogTriggerwindowTwwd_periodisdefinedinWWDregister0.
3750.
50.
625Twwd_periodwww.
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117-46AS8650BDatasheet-DetailedDescription7DetailedDescriptionTheAS8650Bconsistsofthefollowingcomponentsonchip:DCDCconverterwith5VoutputsthatsuppliesthethreeLDOvoltageregulatorsandtheCANTransceiverThreevoltageregulatorswithoutputvoltages3.
3V,2.
8Vand1.
8Vandoutputaccuracyupto2.
5%High-speedCANbusTransceiveraccordingtoISO11898-5IntegratedRESETunitwithapower-on-resetdelayandaprogrammablewatchdogtime7.
1OperatingModesandStatesTheAS8650BprovidesfourmainoperatingmodesNormal,Receive-only,Standby,andSleep.
InNormalmode,theCANTransceivercanbedisabledincaseofover-temperaturecondition.
Thedetailedtransitiontableforeachmodeisshowninthesubsequentpages.
7.
1.
1NormalModeInNormalmodeDCDCconverter,thethreevoltageregulators,BUSTransceiver,andWindowWatchdogareturnedonwithfullfunctionality.
AlltheLDOregulatorsarecapableofdeliveringmaximumloadcurrentpossibleaspertheirrespectiveratings.
TheBUSTransceiveriscapableofsendingtheTxDdatafromthemicrocontrollertotheCANHatthemaximumrate.
7.
1.
2Receive-OnlyModeInthismode,theCANtransmitterisdisabled.
TheCANreceiver,thethreevoltageregulators,andover-temperaturemonitorcircuitareenabled.
7.
1.
3StandbyModeThisisthemodeafterpowerup.
TheStandbymodeisafunctionallow-powermodewheretheCANTransceiverisdisabled.
Thebuswake-up(lowpowerreceiver)circuit,LDO1,andover-temperaturemonitorcircuitareenabled.
BothLDO2andLDO3canbeenabledordisabled(defaultstate)usingthehostcommand.
TheAS8650BcanenterNormalmode,SleepmodeorReceive-onlymodethroughhostcommand.
7.
1.
4SleepModeSleepmodeisthecurrentsavingmodethatisenteredbyhostcommandorbyover-temperaturecondition.
TheDCDCconverter,thethreevoltageregulators,CANTransceiver,thereset,andwindowwatchdogunitareallswitchedoff.
Thebuswake-up(lowpowerreceiver)circuit,oscillator,andover-temperaturemonitorcircuitareactive.
Thebusisinrecessivestate(high).
Theonlywake-uppossibleisthroughremotewake-up(throughthebuslines)orlocalwakeup(throughtheWAKEpin)asdescribedintheWAKEspecification.
InthecaseofenteringSleepmodeduetoover-temperaturecondition(T>Tjshut),thedevicecancomeoutofSleeponlyafterthetemperaturefallsbackbelowthereturntemperatureTjrecvandanyoneofthewakeupeventsmentionedabove.
7.
2PowerManagementStrategyThedetailedblockdiagramandthepowermanagementstrategyareshowninFigure4.
InternalRegulator.
ThismoduleispoweredexternallybytheVSUP.
Allthecriticalmodulesthatneedstobekeptalwayson,workonthissupply.
SomeoftheimportantmodulesamongthemareOver-temperaturemonitor,LocalWakeblock,InternalPower-onResetmodule,InternalOscillator,completemode-controlunit,UndervoltagecomparatorsofthreeexternalLDOs.
DCDCConverter.
Thisisthemainsupplyregulatorforalltheinternalblocks.
Astep-downhystereticbuckconverterisusedtogenerate5VoutputfromVSUP.
This5VoutputisthenusedtogenerateallthethreeLDOs.
Thishigh-efficiencystep-downDCDCconvertercontainsthefollowingfeatures:CurrentlimitedoperationThermalshutdownLDO1.
ThisisthemainI/Osupply.
Thisisgeneratedinternallyfromthe5VDCDCconverteroutputandgivesaregulated3.
3Voutputtopower-uptheexternalmicro-controller.
AlltheI/Osthatinterfacewiththemicrocontrollerworkonthissupply.
LDO2.
Thisregulatorisgeneratedinternallyfromthe5VDCDCconverteroutputandgivesaregulated2.
8Voutput.
Thevoltagelevelcanbechangedthroughfactorysettings.
LDO3.
Thisregulatorisgeneratedinternallyfromthe5VDCDCconverteroutputandgivesaregulated1.
8Voutput.
Thevoltagelevelcanbechangedthroughfactorysettings.
www.
ams.
com/AS8650Revision1.
118-46AS8650BDatasheet-DetailedDescriptionFigure4.
PowerManagementStrategyModeControl/ResetGenerationDigitalInterfaceWindowWatchDogLDO1(100mA)LDO2(120mA)LDO3(100mA)UVCompUVCompUVCompOTPLevelShifterDefinerLevelShifterDefinerDefinerDefinerLevelShifterporclkosc_enstartdoneLevelShifterDefinerLXV5VVLDO1VLDO2VLDO3LevelShifterRESETINTNTxDRxDCSSPISCLKI2C/SCLKSPISDAI2C/SDISPISDOSPIldo1_enldo2_enldo3_enLocalWAKEOTMWAKECANHCANLSPLITldo1_uvbldo2_uvbldo3_uvbtx_entxrx_enrxflagsotm_160otm_170otm_enloc_wakeVSUPGNDFBLDO1Pre-regDCDC5VDefinerI2C_ENOscPre-Reg3.
3V&5.
0VDCDCConverter5VPORCANTransceiverwww.
ams.
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119-46AS8650BDatasheet-DetailedDescriptionTable17.
PowerManagementStrategyforAS8650BControlStatesPower-upNormalRxOnlyStandbySleepAnalogBlocksDCDCConverterONONONONOFF11.
CanbeturnedONusingDeviceConfigurationRegisterOscillatorONONONONONInternalRegulatorONONONONONOTMONONONONONLDO1ONONONONOFFLDO2OFFON22.
CanbeturnedOFFusingDeviceConfigurationRegisterON2OFF1OFFLDO3OFFON2ON2OFF1OFFCANTxOFFONOFFOFFOFFCANRxOFFONONOFFOFFLowPowerRxOFFOFFOFFONONLOCALWAKEOFFOFFOFFONONSPLITGenerationOFFONONONONDigitalBlocksWWDOFFONONONOFFDigitalInterfaceOFFONONONOFFwww.
ams.
com/AS8650Revision1.
120-46AS8650BDatasheet-DetailedDescription7.
3StateDiagramFigure5.
StateMachineModel7.
4InitializationSequenceTheDCDCconverterisswitched'ON'.
Subsequently,onreceivingpower-good(PG)signalfromtheDCDCconverter,theLDO1regulatorisswitched'ON'.
Duringtheinitializationsequence,theVLDO1issetto2.
5VifVLDO1>VLDO1_POKTHthreshold.
VLDO1_RESETisreleasedto'high'.
Then,active-lowPORN_2_OTPisgenerated.
InitiallytherisingedgeofPORN_2_OTPloadscontentsintotheOTPlatch.
NexttheLOAD_OTP_IN_PREREGsignalloadsthecontentofOTPlatchintothepre-regulatordomainregister.
OncetheVLDO1_POKTHthresholdisreached,theresettimeouttimeralsostarts.
TheRESETsignalexpiresafterResettimeoutperiodTRes.
AftertheRESETsignalis'high',thestartupwatchdogislaunched.
Ifthemicrocontrollergeneratesatriggerwithinthestartupwindow,thenthedeviceentersintoStandbymode.
Ifthemicrocontrollerfailstogeneratethetrigger,thentheRESETsignalisgeneratedandtheResettimeoutwillstart.
Ifthemicrocontrollerfailstogeneratethestartupwatchdogtriggerfor3consecutivetimes,thenthedeviceentersintoSleepmode.
OnreceivingNormalmodecommandfromthemicrocontroller,theLDO2andLDO3regulatorsareactivated.
BythetimeVLDO2andVLDO3reachtheirrespectivepower-ok(POK)thresholdvalues,aninterruptsignalisgenerated.
TheAS8650BsupportsveryslowVSUPrampupof0.
5V/min.
PowerOffNormalReceiveOnlyStandbySleepHostcommand(gotoReceiveOnly)Hostcommand(gotoNormal)Hostcommand(gotoStandby)Hostcommand(gotoReceiveOnly)Hostcommand(gotoNormal)Hostcommand(gotoStandby)Hostcommand(gotoSleep)BUSWakeORLocalWakeHostcommand(gotoSleep)Hostcommand(gotoSleep)TEMP>Tjshut→BUSwakedisabledTEMP>Tjwarn→BUStransmitterdisabledBUStransmitterwillbeenabledonTEMPcom/AS8650Revision1.
121-46AS8650BDatasheet-DetailedDescriptionThepowerinitializationsequencediagramisshowninFigure6.
AfteractivatingthepowersupplyonVSUPpin,theVSUP_POR_RESETflagbecomesinactive(high)whilethevoltageexceedstheVSUP_PORthreshold.
TheDCDCoutputvoltageV5VexceedstheV5V_POKTHthresholdsaftertheDCDCsettlingtimeandthefirstvoltageregulator(LDO1)willbeactivatedwiththeV5V_POKset.
IfthevoltageoutputatLDO1(setto2.
5Vonpower-up)reachestheVLDO1_POKTHthreshold,thePORN_2_OTPflagissetandOTPregistersettingfortheLDO1isread.
ConsequentlytheoutputvoltagewillberegulatedtotheactualOTPsettings.
Theinitializationphaseofthedeviceisterminatedafterthepresetoutputvoltagelevelthresholdisexceededandtheresettimeoutisexpired.
AfterenteringStandbymodethehostcontrollercanswitchthedeviceinanyoperationmodethroughtheICorSPIinterface.
Figure6.
InitializationSequenceVSUPVSUP_POR_RESETPORN_2_OTPLOAD_OTP_IN_PREREGRESETVLDO1_POKTHVSUP_PORTres=ResetTimeout6CyclesofRC-OscillatorV5VV5V_POKVLDO1VLDO1_RESETSTANDBYMODEINITIALIZATIONDEVICESTATENORMALMODESTARTUPWATCHDOGVLDO2VLDO3INTNV5V_POKTHVLDO2_POKTHVLDO3_POKTHTstno=StandbytoNormalmodetimeStart-upwatchdogdisabledbydefaultVLDO1_POKTHHostCommandTpost=Power-uptoStandbymodetimewww.
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122-46AS8650BDatasheet-DetailedDescription7.
5DCDCConverterThehigh-efficiency,high-voltage,hystereticstep-downDCDCconverter,operatesinasynchronousmodeanddelivers500mAofoutputloadtodrivethethreeinternalLDOsandtheCANTransceiver.
Thelow-powerarchitectureextendshold-uptimeinbattery-backedandcriticalapplicationswheremaximumup-timeoverawideinputsupplyvoltagerangeisneeded,whilestillprovidingforhighefficienciesofupto90%duringpeakcurrentdemands.
7.
6VoltageRegulatorLDO1Thestabilityofthevoltageoutputisbelow±2.
5%overthefullinputrangeandtemperatureforloadcurrentupto100mAat3.
3V.
PowerInputtothisLDOistheV5V_LDO1pin.
ThisLDOisactivatedinNormal,Receive-onlyorStandbymode.
ItisswitchedOFFinSleepmode.
7.
7VoltageRegulatorLDO2Thestabilityofthevoltageoutputisbelow±2.
5%overinputrangeandtemperatureforloadcurrentupto120mAat2.
8V.
PowerInputtothisLDOistheV5V_LDO2pin.
LDO2isactivatedinNormalandReceive-onlymode.
Theoutputvoltagelevelcanbechangedthroughfactorysettings.
Forfurtherinformation,pleasecontactamsregionalsalesperson.
7.
8VoltageRegulatorLDO3Thestabilityofthevoltageoutputisbelow±2.
5%overinputrangeandtemperatureforloadcurrentupto100mAat1.
8V.
PowerInputtothisLDOistheV5V_LDO3pin.
LDO3isactivatedinNormalandReceive-onlymode.
Theoutputvoltagelevelcanbechangedthroughfactorysettings.
Forfurtherinformation,pleasecontactamsregionalsalesperson.
7.
9Over-TemperatureMonitorInNormalmode,ifthejunctiontemperaturereachestheover-temperaturethresholdTjwarn,awarningflagissetinthediagnosticregisterwhichcanbeaccessedviatheICandtheSPIinterfaceandaninterruptissignalledonINTNpin.
TheCANtransmitterisdisabledandthedeviceremainsinNormalmode.
IfthejunctiontemperaturefallsbelowTjrecv,theCANtransmitterisenabled.
ThewarningflagisclearedinthediagnosticregisterandaninterruptissignalledattheINTNpin.
Ifthejunctiontemperatureexceedstheover-temperaturethresholdTjshut,thedeviceentersSleepmodeirrespectiveofthecurrentmodeandbuswakereceiver(Lowpowerreceiver)isdisabled.
AssoonasthetemperaturefallsbelowTjrecv(thermalrecovery),thedevicegoesthroughthepower-upsequencingwhileenteringPower-upmodeandentersStandbymodeiftheboundaryconditionsofthestatemachinearefulfilled.
7.
10UndervoltageResetUndervoltageonVSUP(BrownoutIndication).
IfVSUPvoltagefallsbelowVSUP_UVTHthreshold,theVSUP_UV_flagissetandaninterruptatINTNisgenerated.
InthiscasethedeviceentersintotheStandbymode.
TheLDO1voltageregulatorremainsactivated.
Twoscenariosarepossibleatthisstage:VSUPisrecovering:IfVSUPexceedstheVSUP_POKTHthreshold,theVSUP_POK_flagissetandthedeviceremainsinStandbymode.
VSUPisstillfalling:InthiscasethedevicecontinuestostayinStandbymode.
IfvoltagefallsbelowVSUP_RESETthreshold,thenthedeviceentersPower-Offandthelogicisreset.
UndervoltageonV5V.
IftheV5VfallsbelowV5V_UVTHthreshold,theV5V_UV_flagisset.
OnceV5VreturnstoV5V_POKTHthresholdvalue,V5V_POK_flagisset.
Incaseaflagisset,aninterruptisgeneratedattheINTNpin.
IfundervoltageonV5VoccursinNormalorReceive-onlymodesthenCANTransceiverisdisabledandthedeviceremainsinitsoperationmode.
UndervoltageonLDO1.
IfthevoltagelevelofLDO1fallsbelowtheVLDO1_UVTHthresholdvalueanddeviceisnotinSleepmode,thedeviceentersintopower-upstatewhileRESETsignalisassertedandthevoltageregulatorisstillactive.
OncetheVLDO1_POKTHthresholdisreached,RESETsignalisde-assertedafterresettimeoutperiodanddeviceentersintoStandbymode.
UndervoltageonLDO2.
IfthevoltageleveloftheLDO2fallsbelowtheVLDO2_UVTHthresholdvalueaVLDO2_UV_flagisset.
AnindicationisgiventomicrocontrollerbysettingabitininterruptregisterandgivinginterruptonINTNpin.
OnceVLDO2returnstoVLDO2_POKTHthresholdvalue,VLDO2_POK_flagisset.
AnindicationisgiventomicrocontrollerbysettingabitininterruptregisterandgivinginterruptonINTNpin.
UndervoltageonLDO3.
IfthevoltageleveloftheLDO3fallsbelowtheVLDO3_UVTHthresholdvalueaVLDO3_UV_flagisset.
AnindicationisgiventomicrocontrollerbysettingabitininterruptregisterandgivinginterruptonINTNpin.
OnceVLDO3returnstoVLDO3_POKTHthresholdvalue,VLDO3_POK_flagisset.
AnindicationisgiventomicrocontrollerbysettingabitininterruptregisterandgivinginterruptonINTNpin.
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123-46AS8650BDatasheet-DetailedDescriptionFigure7.
Power-upandUndervoltageSequence7.
11ResetBlockTheresetblockgeneratesanexternalRESETsignaltoresetthemicrocontrollerandallotherexternalcircuits.
TheresetfunctionalityisexplainedinFigure8.
Theresetblockconsistsofadigitalbufferattheoutput.
TheRESETsignalisaffectedbyVLDO1_RESET(duringoverload,resetonVLDO1)andwatchdogoutput.
AllconditionswhichcauseadropoftheVLDO1voltagewillbedetectedfromthelowvoltageresetunitwhichin-turngeneratesaresetsignal.
Figure8.
ResetBlockFunctionalWaveformV5V_POKTHV5VV5V_POK_flagV5V_UVTHV5V_UV_flagDCDCSupplyVLDO1_POKTHVLDO1VLDO1_RESETVLDO1_UVTHLDO1SupplyVSUP_PORVSUP_RESETVSUP_UVTHVSUP_POKTHVSUPVSUP_POR_RESETVSUP_UV_flagVSUPSupplyVSUPstillfallingVSUP_POK_flagVSUPrecoveringVSUPrecoveringVSUPstillfallingVLDO3_POKTHVLDO3VLDO3_POK_flagVLDO3_UVTHVLDO3_UV_flagLDO3SupplyVLDO2_POKTHVLDO2VLDO2_POK_flagVLDO2_UVTHVLDO2_UV_flagLDO2SupplyVLDO1VSUPVLDO1_PORtRestrrT>TjshutTTdom(wake)>Trec(wake)>Tdom(wake)>Trec(wake)DominantReccessiveDominantReccessivewww.
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127-46AS8650BDatasheet-DetailedDescription7.
13.
9BUSWake_upFlagTheBUSWake_upflagissetwhenthedevicedetectsaremotewake-up(BUSmessage)request.
Theremotewake-uprequestisdetectedwhenpatternshowninFigure11isfoundonwake_remoteportoflowpowerreceiver.
ThisindicatesthemicrocontrollerabouttheBuswakeevent.
7.
13.
10LocalWake_upFlagTheLocalWake_upflagissetwhenthedevicedetectsalocalwake-uprequestonWAKEpin.
Alocalwake-uprequestisdetectedwhenalogicstatechangeonpinWAKEasshowninFigure9.
Thisindicatesthemicrocontrolleraboutthelocalwakeevent.
7.
13.
11OVT_WarningFlagTheOVT_WarningflagissetwhentemperatureexceedsTjwarn.
Thisindicatesthemicrocontrollerabouttemperatureexceedingwarninglevels.
7.
13.
12OVT_RecoverFlagTheOVT_RecoverflagissetwhentemperaturefallsbackbelowTjrecv.
Thisindicatesthemicrocontrollerabouttemperaturefallingbackbelowrecoverylevels.
7.
13.
13BusFailureFlagsThebusfailureflagissetiftheCANTransceiverdetectsabuslineshort-circuitconditiontoVSUP,V5V_LDO1orGND.
Suchpossibleconditionsareindicatedtomicrocontrollerthroughtheseflags.
Alltheseflagsareclearedonmicrocontrollerread.
Ifthefaultconditionstillexistaftermicrocontrollerread,theparticularflagissetagain.
Thedevicestillbeworkinginthecurrentstate.
Themicrocontrollertakesappropriateactiononreadingoftheseflags.
CANH_short_GND.
ThisflagindicatesOverCurrentconditiononpinCANH.
ForexampleshorttogroundonpinCANH.
WhentheoutputcurrentonpinCANHexceedsthethresholdOC_CANH_ththentheoutputOC_CANHswitchesonhighlevelafterafiltertimet_OC_CANH.
CANH_short_VSUP.
ThisflagindicatesLowCurrentonpinCANH.
ForexampleopenloadorshorttoVSUPonpinCANH.
WhentheoutputcurrentonpinCANHfallsbelowthethresholdLC_CANH_ththentheoutputLC_CANHswitchesonhighlevelafterafiltertimet_LC_CANH.
CANL_short_VSUP.
ThisflagindicatesOverCurrentonpinCANL.
ForexampleshorttoVSUPonpinCANL.
WhentheoutputcurrentonpinCANLexceedsthethresholdOC_CANL_th,thentheoutputOC_CANLswitchesonhighlevelafterafiltertimet_OC_CANL.
CANL_short_GND.
ThisflagindicatesLowCurrentonpinCANL.
ForexampleopenloadorshorttogroundonpinCANL.
WhentheoutputcurrentonpinCANLfallsthethresholdLC_CANL_ththentheoutputLC_CANLswitchesonhighlevelafterafiltertimet_LC_CANL.
7.
13.
14LocalFailureFlagsTheAS8650BpreventsthesystemfromfourkindsoflocalfailureswithoutdisturbingtheBUSnetwork.
ThefourfailuresareTxDdominantclamping,RxDrecessiveclamping,TxD&RxDshort,andbusdominantclamping.
Allthesefailuresareindicatedtomicrocontrollerthroughflags.
TxD_Dom_Clampflag.
ApermanentLow-levelonpinTxD(duetoahardwareorsoftwareapplicationfailure)woulddrivetheBUSintoapermanentdominantstate,blockingBUSnetworkcommunication.
IfpinTxDremainsataLowlevelforlongerthantheTxDdominanttimeoutperiodTTxDC(dom),thedevicedisablesthetransmitterofBUSTransceiverandTxD_Dom_Clampflagisset.
ThedevicepreventssuchBUSnetworklock-upbydisablingthetransmitterofthetransceiver.
Thedevicewillnotchangethefunctionalstate.
Thetransmitterremainsdisableduntilthelocalfailurepersists.
Theflagisclearedwithmicrocontrollerreadrequest.
TxD_RxD_Shortflag.
TheTxD_RxDshortcircuitwouldresultinadead-locksituationclampingthebusdominant.
ForexampletheTransceiverreceivesadominantsignal,RxDoutputsadominantlevel.
Becauseoftheshortcircuit,TxDreflectsadominantsignal,retainingthedominantbusstate.
AsaresultTxDandthebusareclampedcontinuouslydominant.
TheresultingeffectisthesameasforthecontinuouslyclampeddominantTxDsignal.
TheTxDdominanttimeoutinterruptsthedeadlocksituationbydisablingthetransmitterandtheTxD_RxDshortconditionisdifferentiated.
ThebusbecomesrecessiveagainandTxDwillberecessiveifitisnotdrivenbymicrocontroller.
However,thefailurescenariomaystillexistandwiththenextdominantsignalonthebusthedescribedprocedurewillstartagain.
ThedevicekeepsthetransmitteroffafterdetectionofTxD_RxDshortfaultandkeepsupdatingthisflagstatus.
Themicrocontrollerhastosend2consecutivelowpulsesofduration500nswithhighperiodof500nsin-between,inregularintervalstocheckshortcircuitrecovery.
ThiswayalocalTxD/RxDshortcircuitwillnotdisturbthecommunicationoftheremainingbussystem.
BUS_Dom_Clampflag.
InthecaseofashortcircuitfromBUStoGND,thecircuitfortheBUSreceiversensesdominantsignalcontinuouslyevenifthereisnodominanttransmittingnode.
Theresultmaybeapermanentlydominantclampedbus.
ThedevicedetectsandreportsaBusDominantClampingsituationtomicrocontrollerthroughBUS_Dom_Clampflag.
IfthereceiverdetectsabusdominantphaseoflongerthanthebusdominanttimeoutTBUSC(dom)BUS_Dom_Clampflagisset.
Theflagisclearedonmicrocontrollerread.
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128-46AS8650BDatasheet-DetailedDescription7.
14Watchdog(WD)TheWDhasthefollowingthreemonitorytimingfunctions:Start-upwatchdog:Givesopportunitytomicrocontrollertoinitializethesystem.
Windowwatchdog:Detectstooearlyortoolatemicrocontrollersoftwareresponse(loopsandhangs).
Timeoutwatchdog:Detectstooverylongresponsefrommicrocontroller.
7.
14.
1Start-upWatchdogBehaviorFollowinganyreseteventthewatchdogisusedtomonitortheECUstart-upprocedure.
Oncetheresetisreleasedthewatchdogcounterwillstart.
Incasethewatchdogisnotproperlyserved(atriggerfrommicrocontroller)withinTWD(init),anotherresetisforcedonRESETpinandthemonitoringprocedureisrestarted.
Thewatchdogwillgivethreeopportunitiestomicrocontrollertoinitializethesystem.
Incasethewatchdogisnotproperlyservedforthreetimes,thenthesystementersintoSleepmode.
7.
14.
2WindowWatchdogBehaviorWheneverthedeviceentersNormalmode,theWindowmodeofthewatchdogisactivated.
Thisensuresthatthemicrocontrolleroperateswithintherequiredspeed;atoofastaswellasatooslowoperationwillbedetected.
WatchdogtriggeringusingtheWindowwatchdogisillustratedinFigure12.
Figure12.
WindowWatchdogTriggeringTheAS8650Bprovides8differentperiodtimings.
Thistimingcanbechangedthroughdigitalinterfacewhendesired.
Theperiodcanbechangedwithinanyvalidtriggerwindow.
WheneverthewatchdogistriggeredwithinthewindowtimeTwd_trig,thetimerwillberesettostartanewperiod.
Thewatchdogwindowisdefinedtobebetween50%and100%ofthenominalprogrammedwatchdogperiod.
Anytooearly(triggerinnon-triggerwindow)ortoolatewatchdogtriggerwillresultanimmediatesystemresetonRESETpinandwatchdogenteringStart-upwatchdogmode.
DuringundervoltageconditiononVLDO1thewatchdogtimerisdisabled.
TRIGGERWINDOWNON-TRIGGERWINDOWTwd_no_trigTwd_trigTwwd_periodTriggerrestartsperiod50%100%LastTriggerPointEarliestTriggerPointLatestTriggerPointTRIGGERWINDOWNON-TRIGGERWINDOW50%100%EarliestTriggerPointLatestTriggerPointTriggerrestartsperiod(withnewperiodifdesired)NewPeriodSPITRIGGERSPITRIGGERUnwantedTrigger(RESETgenerated,watchdogenterStart-upmode)www.
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129-46AS8650BDatasheet-DetailedDescription7.
14.
3TimeoutWatchdogBehaviorWhenevertheAS8650BoperatesinStandbymode,activewatchdogoperatesinTimeoutwatchdogmode.
ThewatchdoghastobetriggeredwithintheactualprogrammedperiodtimeTwd_tout_period.
Thedeviceprovides8differentpossibleperiodsforprogrammingthroughdigitalinterface.
IfthemicrocontrollerfailstotriggerthewatchdogwithintriggerrangethenthesystemresetisgeneratedonRESETpinandwatchdogentersintoStart-upwatchdogmode.
ThetimeoutwatchdogfunctionisillustratedinFigure13.
Figure13.
TimeoutWatchdogTriggering7.
15InterruptGenerationThepinINTNisaninterruptoutput.
TheINTNisforced'low'ifonebitintheInterruptregisterisset.
TheInterruptregisterbitsareclearedwhenthemicrocontrollerclearsthecorrespondinginterruptsourceregister.
TheInterruptregisterwillalsobeclearedduringasystemreset(RESETLOW).
Astherearemicrocontrollerswithlevelsensitiveoredgesensitiveinterruptport,pinINTNwillbe'high'foratleastTINTNafteranyoftheinterruptsourceregisteriscleared.
TheInterruptsourceregisterisclearedthroughwriteoperationbyoverwriting'1'intorespectivesetbitsposition.
WithoutfurtherinterruptswithinTINTNpinINTNstays'high',otherwiseitwillrevertto'low'again.
TheInterruptregisterindicatesthecauseofaninterruptevent.
Therearetwolevelsofinterruptregisters.
Firstlevelregisterindicatesthesourceregionofinterruptandthesecondlevelregisterindicatestheexactsourceofinterrupt.
Withthisstructuredinterrupt,themicrocontrollercantracesourceofinterruptbytworeadoperationsinsteadofpollingforsourceofinterruptandalsointerruptscanbeprioritizedbymicrocontroller.
TheinterruptregisterstructureisgiveninFigure14.
Theregisterisclearedthroughdigitalinterfacewriteoperationanduponanyresetevent.
Thehardwareensuresnointerrupteventislostincasethereisanewinterruptforcedwhilereadingtheregister.
TRIGGERWINDOWNON-TRIGGERWINDOWTwd_no_trigTwd_trigTwwd_periodTriggerrestartsperiod50%100%LastTriggerPointEarliestTriggerPointLatestTriggerPointTRIGGERWINDOWNON-TRIGGERWINDOW50%100%EarliestTriggerPointLatestTriggerPointTriggerrestartsperiod(withnewperiodifdesired)NewPeriodSPITRIGGERSPITRIGGERUnwantedTrigger(RESETgenerated,watchdogenterStart-upmode)www.
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130-46AS8650BDatasheet-DetailedDescriptionFigure14.
InterruptRegisterStructure7.
16StatusRegistersTheAS8650BhasthreeFlagstatusregistersandoneRESETReasonRegister.
TheFlagstatusregistersindicatethecurrentstatusofflagswhicharerelatedtorespectiveinterruptsourceregisters.
TheFlagstatusregistersareBUSStatusRegister,TemperatureStatusRegister,andSupplyStatusRegister.
Themicroprocessorcanreadtheseregistersanytimetocheckthestatusofdevice.
Thefunctionofeachflagislistedinregisterspacedescriptioninsubsequentsections.
ARESETReasonregisterindicatesthereasonsforRESETgeneration.
OncetheRESETpingoes'low',thereasonofthisreseteventisstoredinRESETReasonregister.
WhenRESETisreleasedmicroprocessorcanreadthisregistertoknowthecauseforlastRESETsignal.
TheRESETReasonregisterisclearedoncemicroprocessorreadsthisregisterthroughreadoperation.
Thebitsfunctionalityofthisregisterisexplainedinregisterspacedescriptiontable.
SupplyRelatedinterruptBUSandLocalfailureInterruptwake-up,temperatureandLDOtimeoutInterruptI1I2I3RRRRRInterruptRegisterVSUP_UV_flagVSUP_POK_flagD1D7D6D2D3D4D5D0V5V_UV_flagV5V_POK_flagV2P8_UV_flagV2P8_POK_flagV1P8_UV_flagV1P8_POK_flagInterruptSourceRegistersCANH_Short_GNDCANH_Short_VCCCANL_Short_VCCCANL_Short_GNDReservedTxD_Dom_ClampD1D7D6D2D3D4D5D0TxD_RxD_ShortBUS_Dom_ClampWake_upLocalWake_upOVT_WarningD1RRD2D0RRD3OVT_RecoveryReservedReservedReservedReservedwww.
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131-46AS8650BDatasheet-ApplicationInformation8ApplicationInformationDeviceInterfaces.
TherearetwowaystocommunicatewithAS8650B,oneis4wiresSPIandotherisIC.
TheselectionbetweenthesetwointerfacesisthroughI2C_ENpin,asshowninTable19.
ThepinsCS,SCLK,SDI,andSDOareusedforSPIinterface.
ForICinterface,SCLKisusedasICClockandSDAisusedasICdataline.
PinsSCLKI2C/SCLKSPIandSDAI2C/SDISPIaremultiplexedforbothSPIandICinterface.
SinceI2C_ENisadigitalinputpin,ithastobeconnectedeithertoVLDO1orGND.
Note:I2C_ENshouldnotbechangedduringaIC/SPIRead/Writeoperation.
MaximumswitchingdelaybetweenICandSPIis8s.
8.
1SerialPeripheralInterfaceTheSerialPeripheralInterface(SPI)providesthecommunicationlinkwiththemicrocontroller.
TheSPIisconfiguredforhalf-duplexdatatransfer.
TheSPIprovidesaccesstoconfigurationregisters,controlregisters,anddiagnosticregisters.
ThemodesoftheAS8650BarechangedbywritingrequiredcodeintoModeControlRegisterthroughSPI.
TheSPIisalsousedtoenterintotestandOTPmodes.
ThisinterfaceisonlyslaveinterfaceandonlymastercaninitiateSPIoperation.
TheSPIcanworkonboththeclockpolarities.
ThepolarityoftheclockdependsonthevalueofSCLKatthefallingedgeofCS.
AtthefallingedgeofCSifSCLKis"1"thentheSPIispositiveedgetriggeredandiftheSCLKis"0"thenSPIisnegativeedgetriggeredlogic(seeTable20).
TheSPIprotocolframeisdividedintotwofields,theheaderfieldandthedatafield.
Theheaderfieldis1bytelongcontainingaread/writecommandbit,5addressbitsand2reservedbits.
Thedatafieldisofonedatabyte.
TheSPIframeformatisshowninFigure15.
InthedataphaseMSBissentfirstandLSBissentlast.
Figure15.
SPIFrameFormatTable19.
DeviceInterfaceSelectionI2C_ENDescriptionLOWInterfaceis4-wireSPIHIGHInterfaceisICTable20.
SPIClockPolarityCSSCLKDescriptionLOWHIGHSerialdataistransferredatfallingedgeandsampledatrisingedgeofSCLKLOWLOWSerialdataistransferredatrisingedgeandsampledatfallingedgeofSCLKR/WA0A1A2A3A4HeaderFieldDataField1byteReservedBits5bitsAddress0–WRITE1–READ00D7D6D5D4D3D2D1D0www.
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132-46AS8650BDatasheet-ApplicationInformation8.
1.
1SPIWriteOperationTheSPIwriteoperationbeginswithclockpolarityselectionatnegativeedgeofCS,giveninTable20.
OncetheclockpolarityisselectedtheSPIwritecommandisgivenbyproviding'0'inR/WbitoftheheaderfieldinfirstsamplingedgeatSDIpin.
The5bitsaddressofregistertobewrittenisprovidedatSDIpininnextfiveconsecutivesamplingedgesofSCLK.
Thefirst2bitsinheaderfieldsarereservedandsetto'0'.
Thedatatobewrittenisfollowedbylastbitofheaderfield.
WitheachsamplingedgeabitissampledstartingfromMSBtoLSB.
DuringcompleteSPIwriteoperationtheCShastobe'low'.
TheSPIwriteoperationendswithpositiveedgeofCS.
ThewaveformforSPIwriteoperationwithsingledatabyteisshowninFigure16andFigure17.
Figure16.
SPIWriteOperationwithNegativeClockPolarityand1ByteofDataFieldFigure17.
SPIWriteOperationwithPositiveClockPolarityand1ByteofDataFieldR1R0A4A3A2A1A0D7D6D5D4D3D2D1D0SCLKSDISDOCSSamplingEdgeHighImpedanceSateSCLKSDISDOCSR1R0A4A3A2A1A0D7D6D5D4D3D2D1D0SamplingEdgeHighImpedanceSatewww.
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133-46AS8650BDatasheet-ApplicationInformation8.
1.
2SPIReadOperationTheSPIreadoperationalsobeginswithclockpolarityselectionatnegativeedgeofCS,giveninTable20.
OncetheclockpolarityisselectedtheSPIreadcommandisgivenbyproviding'1'inR/WbitoftheheaderfieldinfirstsamplingedgeatSDIpin.
The5bitsaddressofregistertobereadisprovidedatSDIpininnextfiveconsecutivesamplingedgesofSCLK.
Thefirst2bitsinheaderfieldsarereservedandsetto'0'.
ThereaddataisfollowedbylastbitofheaderfieldonSDOpin.
WitheachsamplingedgeabitcanbereadonSDOpinstartingfromMSBtoLSB.
DuringcompleteSPIreadoperationtheCShastobe'low'.
TheSPIreadoperationendswithpositiveedgeofCS.
ThewaveformforSPIreadoperationwithsingledatabyteisshowninFigure18andFigure19.
Figure18.
SPIReadOperationwithNegativeClockPolarityand1ByteofDataFieldFigure19.
SPIReadOperationwithPositiveClockPolarityand1ByteofDataFieldD7D6D5D4D3D2D1D0R1R0A4A3A2A1A0SCLKSDICSSDOSamplingEdgeHighImpedanceSateSCLKSDICSSDOR1R0A4A3A2A1A0D7D6D5D4D3D2D1D0SamplingEdgeHighImpedanceSatewww.
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134-46AS8650BDatasheet-ApplicationInformation8.
1.
3SPITimingDiagramFigure20.
TimingDiagramforSPIWriteOperationFigure21.
TimingDiagramforSPIReadOperationCSSDISDOSCLK.
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CLKpolarityDATAIDATAIDATAI.
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tSCLKLtSCLKHtCPHDtCPStDIStDIHtCSHCSSCLKSDISDODATAIDATAIDATAO(D7N)DATAO(D00)tSCLKLtSCLKHtDODtDOHZwww.
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135-46AS8650BDatasheet-ApplicationInformation8.
2Inter-IntegratedCircuit(IC)InterfaceICisabidirectional2linebusinterfacewithaserialdataline(SDA)andaserialclockline(SCLK)forinterICcontrol.
ThisinterfaceisonlyslaveinterfaceandonlymicrocontrollercanstartandstoptheICoperation.
TheoverviewofICprotocolisshowninFigure22.
A'high'to'low'transitiononSDAlinewhileSCLKis'high'istheSTART(S)conditionanda'low'to'high'transitiononSDAlinewhileSCLKis'high'istheSTOP(P)condition,asshowninFigure22.
TheSTARTandSTOPconditionsshouldalwaysbegeneratedbythemicrocontroller.
AftertheSTARTcondition,microcontrollerhastomakesurethatdataonSDAlinemustbestableduringthe'high'periodofSCLK.
ThedatashouldonlychangewhenSCLKlineis'low'.
TheBusisbusyaftertheSTARTconditionanditisfreeaftertheSTOPcondition.
AnynumberofdatabytescanbetransmittedbetweenSTARTandSTOP.
Eachbyteisfollowedbyanacknowledgement(whichistheninthbit).
Thedatatransmitteralwaysreceivesanacknowledgementfromthedatareceiveratendofeachbyte.
ThedatatransmitterreleasestheSDAbusatstartof'low'periodof8thclockpulseanddatareceiveracknowledgesbypullingtheSDAto'low'duringthe'low'periodoftheSCLK.
TheDatareceiverreleasesthebusatstartof'low'periodof9thclockpulseoftheSCLKanddatatransmittergetsthedatabus.
TheAS8650Bdoesnotsupportgeneralcalladdress,STARTbyteandhigh-speedmode.
Figure22.
ICBusProtocol8.
2.
1ICSlaveAddressThe7-bitslaveaddressofthedeviceisbydefaultsetto0000000.
Onrequesttheslaveaddresscanbechangedintherangefrom0000000to1111110throughfactorysettings.
8.
2.
2ICWriteOperationAftertheSTARTcondition,microcontrollerhastosend,inthefirstbyte,the7-bitslaveaddressand0intotheR/WbitasshowninFigure23.
Themicrocontrollerhastosendtheaddressoftheregistertobewritteninthesecondbyte.
Thefirst3MSBbitsarereservedandremaining5bitsareusedasaddressbits.
ThedataissentstartingfromMSBtoLSB.
TheAS8650Bsendsacknowledgementon9thclockpulse.
Inthenextbyte(3rdbyte)microcontrollerhastosendthedatatobewrittenintoaddressedregister.
Ifitisasinglewriteoperation,afterreceivingtheacknowledgmentfromAS8650B,microcontrollerhastosendSTARTorSTOPcondition,asshowninFigure23.
Incaseofautoincrementwriteoperation,microcontrollershouldnotgenerateSTARTorSTOPconditionafterthethirdbyte.
Ifmicrocontrollercontinuouslywritesthenaddresspointerrollsbacktothestartingregisteraddressafterreachingthelastregisteraddress.
Databytescomingfromthemicrocontrollerarewrittenattheconsecutiveaddresslocations,startingfromtheaddresssentinfirstdatabyte.
Aftereachdatabyte,directionofthebuslinechangesandAS8650BacknowledgesbypullingtheSDAline'low'.
ToterminatethewriteoperationmicrocontrollerhastogenerateSTOPorrepeatedSTARTcondition.
Fordetails,seeFigure24.
Figure23.
ICWriteOperationSDAS1289SCLKMSBACK34567128934567R/W7bitSlaveaddressLSB8bitData128934567SorP8bitDataACKACK1289SCLKMSBSDA34567128934567LSB128934567AAAacknowledgefromslaveacknowledgefromslaveacknowledgefromslaveregisteraddressdatatoregisterSorPR/WSlaveaddressSA0A1A2A3A4www.
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136-46AS8650BDatasheet-ApplicationInformationFigure24.
ICAuto-incrementWriteOperation8.
2.
3ICReadOperationAftertheSTARTcondition,microcontrollerhastosend,inthefirstbyte,the7-bitslaveaddressand0intotheR/WbitasshowninFigure25.
Themicrocontrollerhastosendtheaddressoftheregistertobewritteninthesecondbyte.
Thefirst3MSBbitsarereservedandremaining5bitsareusedasaddressbits.
ThedataissentstartingfromMSBtoLSB.
Afterreceivingtheacknowledgementonthe9thclockpulse,microcontrollerhastosendontheSDAlinerepeatedSTARTorSTOP,asshowninFigure25.
IfmicrocontrollersendsSTOPthenmicrocontrollerhastosendSTARTagain.
IfmicrocontrollersendsrepeatedSTARTthenthereisnoneedtogenerateSTARTagain.
Themicrocontrolleragainhastosendthe7-bitslaveaddressandwrites'1'intotheR/Wbit(8thbit).
NowAS8650Bsendsdataofthecorrespondingaddressedregisterinthenexteightclockcycles.
Incaseofsingleread,microcontrollerdoesnotacknowledgeonthe9thclockpulseandgeneratesSTARTorSTOPconditionaftertheninthclockpulse.
Ifitisanautoincrementreadoperation,microcontrolleracknowledgesonthe9thclockpulseandAS8650Bsendsdatafromtheconsecutiveaddresslocations,(seeFigure25).
Ifmicrocontrollercontinuouslyreadsthenaddresspointerrollsbacktothestartingregisteraddressafterreachingthelastregisteraddress.
InthedataphaseMSBissentfirstandLSBissentlast.
Aftereachdatabyte,microcontrollerhastosendtheacknowledgement.
ThemicrocontrollercanterminatetheautoreadoperationbynotgeneratingacknowledgementforthelastbytethatwassentbytheAS8650BandgeneratesSTOPorrepeatedSTARTconditionafterthe9thclockpulse.
Figure25.
ICReadOperation1289SCLKMSBSDAMastertransmitter34567128934567LSB128934567AAAacknowledgeFromslaveacknowledgeFromslaveacknowledgeFromslavedatatoregisterSorPdatatoregister+nR/WSlaveaddressSregisteraddressA0A1A2A3A41289SCLKMSBSDA34567128934567LSBAAacknowledgefromslaveacknowledgefromslaveregisteraddressSorPWSlaveaddress1289SCLKMSBSDA34567128934567LSBAAacknowledgefromslaveacknowledgefrommasterDatabyteRSlaveaddress01SSSorPA0A1A2A3A4www.
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com/AS8650Revision1.
137-46AS8650BDatasheet-ApplicationInformationFigure26.
ICAuto-incrementReadOperationFigure27.
DefinitionofICTimingParameters1289SCLKMSBSDA34567128934567LSBAAacknowledgefromslaveacknowledgefrommasterDatabyte1RSlaveaddress128934567ANoacknowledgefrommasterLastdatabyteDatabyten1289SCLKMSBSDA34567128934567LSBAAacknowledgefromslaveacknowledgefromslaveregisteraddressWSlaveaddress01SorPSSSorPA0A1A2A3A4tLOWSCLKSDAtftrtftHIGHtSU_DATStHD_STAtSU_STAtHD_DATtBUFtrtSU_STOSrPStSPwww.
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138-46AS8650BDatasheet-ApplicationInformation8.
3RegisterSpaceTheAS8650Bregisterspaceconsistsofconfigurationregisters,controlregistersanddiagnosticregisters.
AlloftheseregistersareaccessiblethroughSPIorICcommands.
Table21.
ConfigurationRegistersAddrRegisterNamePORValueBitTypeDescription0x00ReservedReserved0x01ReservedReserved0x02WDAccessControlRegister0000_0000POR_VLDO1D[7:0]R/W0101_1010WDConfigurationRegisteraccessEnabledElseWDConfigurationRegisteraccessdisabled0x03WDConfigurationRegister0000_1001POR_VSUPD[7:6]R/W01WDdisabledElseWDenabledD[5:3]TimeoutWatchdogmodeWindowperiodTwd_tout_period.
(Accuracyofthetimingsis±25%)00080ms001160ms010320ms011480ms100800ms1011000ms1102000ms1114000msD[2:0]WindowWatchdogmodeWindowperiodTwwd_period(50%ofabovevalueistriggerwindow)00010ms00140ms01080ms011120ms100160ms101240ms110320ms111400ms0x04WDTriggerRegister0000_0000POR_VLDO1D[7:1]WReservedD[0]Watchdogtriggerbit.
Themicrocontrollersetthisbitwithintherequiredwindowofwatchdogtimer.
Afterthisinternalcounterisresetandthisbitisclearedinternally.
www.
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139-46AS8650BDatasheet-ApplicationInformation0x05DeviceConfigurationRegister0110_1101POR_VSUPD[7]R/W0LDO3disableinStandbymode1LDO3enableinStandbymodeD[6]0LDO3disableinReceive-onlymode1LDO3enableinReceive-onlymodeD[5]0LDO3disableinNormalmode1LDO3enableinNormalmodeD[4]0LDO2disableinStandbymode1LDO2enableinStandbymodeD[3]0LDO2disableinReceive-onlymode1LDO2enableinReceive-onlymodeD[2]0LDO2disableinNormalmode1LDO2enableinNormalmodeD[1]0DCDCdisableinSleepmode1DCDCenableinSleepmode0x06ModeControlRegister0000_0000POR_VSUPD[7:6]R/WReservedD[5:4]Devicestate(Read-onlyvalues)0DeviceinStandbymode1DeviceinNormalmode10DeviceinReceive-onlymodeD[3:2]ReservedD[1:0]00Standbymode01Normalmode10Receive-onlymode11Sleepmode0x07InterruptRegister0000_0000POR_VSUPD[7:3]RReservedD[2]0NoInterrupt1SupplyRelatedInterrupt.
ThesourceofinterruptisknownbyreadingInterruptSourceRegister3D[1]0NoInterrupt1Wake-up&temperatureRelatedInterrupt.
ThesourceofinterruptisknownbyreadingInterruptSourceRegister2D[0]0NoInterrupt1BUS&LocalFailureRelatedInterrupt.
ThesourceofinterruptisknownbyreadingInterruptSourceRegister1Table21.
ConfigurationRegistersAddrRegisterNamePORValueBitTypeDescriptionwww.
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140-46AS8650BDatasheet-ApplicationInformation0x08InterruptSourceRegister10000_0000POR_VSUPD[7]R/W0NoInterrupt1InterruptduetoBUSclampedtodominantD[6]0NoInterrupt1InterruptduetoshortTxD&RxDpinsD[5]ReservedD[4]0NoInterrupt1InterruptduetoTxDpinclampedtoDominantD[3]0NoInterrupt1InterruptduetoCANLpinshortedtoVCCD[2]0NoInterrupt1InterruptduetoCANLpinshortedtoGNDD[1]0NoInterrupt1InterruptduetoCANHpinshortedtoGNDD[0]0NoInterrupt1InterruptduetoCANHpinshortedtoVCC0x09InterruptSourceRegister20000_0000POR_VSUPD[7:4]ReservedD[3]0NoInterrupt1InterruptduetojunctiontemperaturefallingbackbelowTjrecvD[2]0NoInterrupt1InterruptduetojunctiontemperatureexceedingTjwarnD[1]0NoInterrupt1InterruptduetoLocalWakeupeventonWAKEpinD[0]0NoInterrupt1InterruptduetoWakeupbyBUSmessage(remotewake)Table21.
ConfigurationRegistersAddrRegisterNamePORValueBitTypeDescriptionwww.
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141-46AS8650BDatasheet-ApplicationInformation0x0AInterruptSourceRegister30000_0000POR_VSUPD[7]R/W0NoInterrupt1InterruptduetoVLDO3_POK_flagsetD[6]0NoInterrupt1InterruptduetoVLDO3_UV_flagsetD[5]0NoInterrupt1InterruptduetoVLDO2_POK_flagsetD[4]0NoInterrupt1InterruptduetoVLDO2_UV_flagsetD[3]0NoInterrupt1InterruptduetoV5V_POK_flagsetD[2]0NoInterrupt1InterruptduetoV5V_UV_flagsetD[1]0NoInterrupt1InterruptduetoVSUP_POK_flagsetD[0]0NoInterrupt1InterruptduetoVSUP_UV_flagset0x0BReserved0000_0000POR_VSUPD[7:0]Reserved0x0CBUSStatusRegister0000_0000POR_VSUPD[7]RBUSclampedtodominantD[6]TxD&RxDpinsshortD[4]TxDpinclampedtoDominantD[3]CANLpinshortedtoVCCD[2]CANLpinshortedtoGNDD[1]CANHpinshortedtoGNDD[0]CANHpinshortedtoVCC0x0DTemperatureStatusRegister0000_0000POR_VSUPD[7:2]RReservedD[1]OTM140RecoveryflagD[0]OTM160Warningflag0x0ESupplyStatusRegister1010_1010POR_VSUPD[7]RVLDO3_POK_flagD[6]VLDO3_UV_flagD[5]VLDO2_POK_flagD[4]VLDO2_UV_flagD[3]V5V_POK_flagD[2]V5V_UV_flagD[1]VSUP_POK_flagD[0]VSUP_UV_flagTable21.
ConfigurationRegistersAddrRegisterNamePORValueBitTypeDescriptionwww.
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142-46AS8650BDatasheet-ApplicationInformation0x0FRESETReasonRegister0000_0000POR_VSUPRThesebitsareclearedonmicrocontrollerreadD[7]ReservedD[6]SleepmodeexitbyLocalWakeuponWAKEpinD[5]SleepmodeexitbyRemotewakeD[4]WindowWatchdogfailureD[3]TimeoutWatchdogfailureD[2]Start-upWatchdogfailureD[1]UndervoltageonVLDO1D[0]OTMShutdownflag0x10BackupRegister0000_0000POR_VSUPD[7:0]R/WOTP_BITS[32:25]/MCUBackupData0x11D[7:0]OTP_BITS[40:33]/MCUBackupData0x12D[7:0]OTP_BITS[48:41]/MCUBackupData0x13D[7:0]OTP_BITS[56:49]/MCUBackupData0x14D[7:0]{1'b0,OTP_BITS[63:57]}/MCUBackupData0x15D[7:0]{2'd0,Slaveaddress[6:1]}/MCUBackupData0x16D[7:0]10bit_slave_address[3:0]/MCUBackupData0x17D[7:0]MCUBackupDataTable21.
ConfigurationRegistersAddrRegisterNamePORValueBitTypeDescriptionwww.
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143-46AS8650BDatasheet-PackageDrawingsandMarkings9PackageDrawingsandMarkingsThedeviceisavailableina36-pinQFN(6x6x0.
9)package.
Figure28.
DrawingsandDimensionsMarkingDescription:YYWWXZZ@LasttwodigitsofthecurrentyearManufacturingWeekAssemblyplantidentifierAssemblytraceabilitycodeSublotidentifierSymbolMinNomMaxA0.
800.
901.
00A100.
020.
05A3-0.
20REF-L0.
350.
400.
45L10-0.
15b0.
180.
250.
30D6.
00BSCE6.
00BSCe0.
50BSCD24.
604.
704.
80E24.
604.
704.
80aaa-0.
15-bbb-0.
10-ccc-0.
10-ddd-0.
05-eee-0.
08-fff-0.
10-N36Notes:1.
DimensionsandtolerancingconformtoASMEY14.
5M-1994.
2.
Alldimensionsareinmillimeters,angleisindegrees.
3.
Dimensionbappliestometallizedterminalandismeasuredbetween0.
25mmand0.
30mmfromterminaltip.
DimensionL1representsterminalfullbackfrompackageedgeupto0.
15mmisacceptable.
4.
Coplanarityappliestotheexposedheatslugaswellastheterminal.
5.
Radiusonterminalisoptional.
6.
Nisthetotalnumberofterminals.
AS8650BYYWWXZZ18249-03@www.
ams.
com/AS8650Revision1.
144-46AS8650BDatasheet-RevisionHistoryRevisionHistoryNote:Typosmaynotbeexplicitlymentionedunderrevisionhistory.
RevisionDateOwnerDescription1.
028Mar,2012hglInitialreleaseforAS8650B1.
1Jan11,2013UpdatedOrderingInformationwww.
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145-46AS8650BDatasheet-OrderingInformation10OrderingInformationThedevicesareavailableasthestandardproductsshowninTable22.
Note:AllproductsareRoHScompliantandamsgreen.
Buyourproductsorgetfreesamplesonlineatwww.
ams.
com/ICdirectTechnicalSupportisavailableatwww.
ams.
com/Technical-SupportForfurtherinformationandrequests,emailusatsales@ams.
com(or)findyourlocaldistributoratwww.
ams.
com/distributorTable22.
OrderingInformation11.
TheAS8650Bprovidesvariousconfigurationoptionsduringproduction.
Formoreinformation,pleasecontactoursalesoffice.
OrderingCodeMarkingDescriptionDeliveryFormPackageAS8650B-ZQFP-01AS8650BAS8650BPowerManagementdevicewithhigh-speedCANInterface(standardconfiguration)Tape&ReelinDryPack(1reel=4000units)36-pinQFN(6x6x0.
9)AS8650B-ZQFM-01AS8650BTape&ReelinDryPack(1reel=1000units)36-pinQFN(6x6x0.
9)www.
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146-46AS8650BDatasheet-CopyrightsCopyrightsCopyright1997-2013,amsAG,Tobelbaderstrasse30,8141Unterpremstaetten,Austria-Europe.
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Allrightsreserved.
Thematerialhereinmaynotbereproduced,adapted,merged,translated,stored,orusedwithoutthepriorwrittenconsentofthecopyrightowner.
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Therefore,priortodesigningthisproductintoasystem,itisnecessarytocheckwithamsAGforcurrentinformation.
Thisproductisintendedforuseinnormalcommercialapplications.
Applicationsrequiringextendedtemperaturerange,unusualenvironmentalrequirements,orhighreliabilityapplications,suchasmilitary,medicallife-supportorlife-sustainingequipmentarespecificallynotrecommendedwithoutadditionalprocessingbyamsAGforeachapplication.
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