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Thisisinformationonaproductinfullproduction.
March2017DocID15274Rev101/108STM32F105xxSTM32F107xxConnectivityline,ARM-based32-bitMCUwith64/256KBFlash,USBOTG,Ethernet,10timers,2CANs,2ADCs,14communicationinterfacesDatasheet-productiondataFeaturesCore:ARM32-bitCortex-M3CPU–72MHzmaximumfrequency,1.
25DMIPS/MHz(Dhrystone2.
1)performanceat0waitstatememoryaccess–Single-cyclemultiplicationandhardwaredivisionMemories–64to256KbytesofFlashmemory–64Kbytesofgeneral-purposeSRAMClock,resetandsupplymanagement–2.
0to3.
6VapplicationsupplyandI/Os–POR,PDR,andprogrammablevoltagedetector(PVD)–3-to-25MHzcrystaloscillator–Internal8MHzfactory-trimmedRC–Internal40kHzRCwithcalibration–32kHzoscillatorforRTCwithcalibrationLowpower–Sleep,StopandStandbymodes–VBATsupplyforRTCandbackupregisters2*12-bit,1sA/Dconverters(16channels)–Conversionrange:0to3.
6V–Sampleandholdcapability–Temperaturesensor–upto2MSPSininterleavedmode2*12-bitD/AconvertersDMA:12-channelDMAcontroller–Supportedperipherals:timers,ADCs,DAC,I2Ss,SPIs,I2CsandUSARTsDebugmode–Serialwiredebug(SWD)&JTAGinterfaces–Cortex-M3EmbeddedTraceMacrocellUpto80fastI/Oports–51/80I/Os,allmappableon16externalinterruptvectorsandalmostall5V-tolerantCRCcalculationunit,96-bituniqueIDUpto10timerswithpinoutremapcapability–Uptofour16-bittimers,eachwithupto4IC/OC/PWMorpulsecounterandquadrature(incremental)encoderinput–1*16-bitmotorcontrolPWMtimerwithdead-timegenerationandemergencystop–2*watchdogtimers(IndependentandWindow)–SysTicktimer:a24-bitdowncounter–2*16-bitbasictimerstodrivetheDACUpto14communicationinterfaceswithpinoutremapcapability–Upto2*I2Cinterfaces(SMBus/PMBus)–Upto5USARTs(ISO7816interface,LIN,IrDAcapability,modemcontrol)–Upto3SPIs(18Mbit/s),2withamultiplexedI2SinterfacethatoffersaudioclassaccuracyviaadvancedPLLschemes–2*CANinterfaces(2.
0BActive)with512bytesofdedicatedSRAM–USB2.
0full-speeddevice/host/OTGcontrollerwithon-chipPHYthatsupportsHNP/SRP/IDwith1.
25KbytesofdedicatedSRAM–10/100EthernetMACwithdedicatedDMAandSRAM(4Kbytes):IEEE1588hardwaresupport,MII/RMIIavailableonallpackagesTable1.
DevicesummaryReferencePartnumberSTM32F105xxSTM32F105R8,STM32F105V8STM32F105RB,STM32F105VBSTM32F105RC,STM32F105VCSTM32F107xxSTM32F107RB,STM32F107VBSTM32F107RC,STM32F107VCLQFP10014*14mmLQFP6410*10mmFBGALFBGA10010*10mmwww.
st.
comContentsSTM32F105xx,STM32F107xx2/108DocID15274Rev10Contents1Introduction92Description102.
1Deviceoverview102.
2Fullcompatibilitythroughoutthefamily122.
3Overview132.
3.
1ARMCortex-M3corewithembeddedFlashandSRAM142.
3.
2EmbeddedFlashmemory142.
3.
3CRC(cyclicredundancycheck)calculationunit142.
3.
4EmbeddedSRAM142.
3.
5Nestedvectoredinterruptcontroller(NVIC)142.
3.
6Externalinterrupt/eventcontroller(EXTI)152.
3.
7Clocksandstartup152.
3.
8Bootmodes152.
3.
9Powersupplyschemes162.
3.
10Powersupplysupervisor162.
3.
11Voltageregulator162.
3.
12Low-powermodes162.
3.
13DMA172.
3.
14RTC(real-timeclock)andbackupregisters172.
3.
15Timersandwatchdogs182.
3.
16ICbus192.
3.
17Universalsynchronous/asynchronousreceivertransmitters(USARTs).
192.
3.
18Serialperipheralinterface(SPI)202.
3.
19Inter-integratedsound(I2S)202.
3.
20EthernetMACinterfacewithdedicatedDMAandIEEE1588support.
202.
3.
21Controllerareanetwork(CAN)212.
3.
22Universalserialbuson-the-gofull-speed(USBOTGFS)212.
3.
23GPIOs(general-purposeinputs/outputs)212.
3.
24Remapcapability222.
3.
25ADCs(analog-to-digitalconverters)222.
3.
26DAC(digital-to-analogconverter)222.
3.
27Temperaturesensor232.
3.
28SerialwireJTAGdebugport(SWJ-DP)23DocID15274Rev103/108STM32F105xx,STM32F107xxContents42.
3.
29EmbeddedTraceMacrocell233Pinoutsandpindescription244Memorymapping335Electricalcharacteristics345.
1Parameterconditions345.
1.
1Minimumandmaximumvalues345.
1.
2Typicalvalues345.
1.
3Typicalcurves345.
1.
4Loadingcapacitor345.
1.
5Pininputvoltage345.
1.
6Powersupplyscheme355.
1.
7Currentconsumptionmeasurement355.
2Absolutemaximumratings365.
3Operatingconditions375.
3.
1Generaloperatingconditions375.
3.
2Operatingconditionsatpower-up/power-down385.
3.
3Embeddedresetandpowercontrolblockcharacteristics385.
3.
4Embeddedreferencevoltage395.
3.
5Supplycurrentcharacteristics395.
3.
6Externalclocksourcecharacteristics475.
3.
7Internalclocksourcecharacteristics525.
3.
8PLL,PLL2andPLL3characteristics535.
3.
9Memorycharacteristics545.
3.
10EMCcharacteristics545.
3.
11Absolutemaximumratings(electricalsensitivity)565.
3.
12I/Ocurrentinjectioncharacteristics565.
3.
13I/Oportcharacteristics575.
3.
14NRSTpincharacteristics625.
3.
15TIMtimercharacteristics635.
3.
16Communicationsinterfaces645.
3.
1712-bitADCcharacteristics745.
3.
18DACelectricalspecifications795.
3.
19Temperaturesensorcharacteristics81ContentsSTM32F105xx,STM32F107xx4/108DocID15274Rev106Packageinformation826.
1LFBGA100packageinformation826.
2LQFP100packageinformation856.
3LQFP64packageinformation886.
4Thermalcharacteristics916.
4.
1Referencedocument916.
4.
2Selectingtheproducttemperaturerange927Partnumbering94AppendixAApplicationblockdiagrams95A.
1USBOTGFSinterfacesolutions.
95A.
2Ethernetinterfacesolutions.
97A.
3Completeaudioplayersolutions99A.
4USBOTGFSinterface+Ethernet/I2Sinterfacesolutions1008Revisionhistory103DocID15274Rev105/108STM32F105xx,STM32F107xxListoftables6ListoftablesTable1.
Devicesummary1Table2.
STM32F105xxandSTM32F107xxfeaturesandperipheralcounts10Table3.
STM32F105xxandSTM32F107xxfamilyversusSTM32F103xxfamily12Table4.
Timerfeaturecomparison.
18Table5.
Pindefinitions27Table6.
Voltagecharacteristics36Table7.
Currentcharacteristics36Table8.
Thermalcharacteristics.
37Table9.
Generaloperatingconditions37Table10.
Operatingconditionatpower-up/powerdown38Table11.
Embeddedresetandpowercontrolblockcharacteristics.
38Table12.
Embeddedinternalreferencevoltage.
39Table13.
MaximumcurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlash40Table14.
MaximumcurrentconsumptioninRunmode,codewithdataprocessingrunningfromRAM.
40Table15.
MaximumcurrentconsumptioninSleepmode,coderunningfromFlashorRAM.
41Table16.
TypicalandmaximumcurrentconsumptionsinStopandStandbymodes41Table17.
TypicalcurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlash44Table18.
TypicalcurrentconsumptioninSleepmode,coderunningfromFlashorRAM45Table19.
Peripheralcurrentconsumption46Table20.
High-speedexternaluserclockcharacteristics.
47Table21.
Low-speedexternaluserclockcharacteristics48Table22.
HSE3-25MHzoscillatorcharacteristics49Table23.
LSEoscillatorcharacteristics(fLSE=32.
768kHz)50Table24.
HSIoscillatorcharacteristics52Table25.
LSIoscillatorcharacteristics52Table26.
Low-powermodewakeuptimings53Table27.
PLLcharacteristics53Table28.
PLL2andPLL3characteristics53Table29.
Flashmemorycharacteristics54Table30.
Flashmemoryenduranceanddataretention54Table31.
EMScharacteristics55Table32.
EMIcharacteristics56Table33.
ESDabsolutemaximumratings56Table34.
Electricalsensitivities56Table35.
I/Ocurrentinjectionsusceptibility57Table36.
I/Ostaticcharacteristics57Table37.
Outputvoltagecharacteristics60Table38.
I/OACcharacteristics61Table39.
NRSTpincharacteristics62Table40.
TIMxcharacteristics63Table41.
I2Ccharacteristics.
64Table42.
SCLfrequency(fPCLK1=36MHz.
,VDD=3.
3V)65Table43.
SPIcharacteristics66Table44.
I2Scharacteristics.
69ListoftablesSTM32F105xx,STM32F107xx6/108DocID15274Rev10Table45.
USBOTGFSstartuptime71Table46.
USBOTGFSDCelectricalcharacteristics.
71Table47.
USBOTGFSelectricalcharacteristics.
72Table48.
EthernetDCelectricalcharacteristics.
72Table49.
Dynamiccharacteristics:EthernetMACsignalsforSMI.
72Table50.
Dynamiccharacteristics:EthernetMACsignalsforRMII73Table51.
Dynamiccharacteristics:EthernetMACsignalsforMII74Table52.
ADCcharacteristics74Table53.
RAINmaxforfADC=14MHz.
75Table54.
ADCaccuracy-limitedtestconditions76Table55.
ADCaccuracy76Table56.
DACcharacteristics79Table57.
TScharacteristics81Table58.
LFBGA100recommendedPCBdesignrules(0.
8mmpitchBGA)83Table59.
LQPF100-100-pin,14x14mmlow-profilequadflatpackagemechanicaldata85Table60.
LQFP64–10x10mm64pinlow-profilequadflatpackagemechanicaldata.
88Table61.
Packagethermalcharacteristics.
91Table62.
Orderinginformationscheme94Table63.
PLLconfigurations101Table64.
ApplicativecurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlash102Table65.
Documentrevisionhistory103DocID15274Rev107/108STM32F105xx,STM32F107xxListoffigures8ListoffiguresFigure1.
STM32F105xxandSTM32F107xxconnectivitylineblockdiagram13Figure2.
STM32F105xxandSTM32F107xxconnectivitylineBGA100ballouttopview24Figure3.
STM32F105xxandSTM32F107xxconnectivitylineLQFP100pinout25Figure4.
STM32F105xxandSTM32F107xxconnectivitylineLQFP64pinout26Figure5.
Memorymap.
33Figure6.
Pinloadingconditions.
34Figure7.
Pininputvoltage34Figure8.
Powersupplyscheme.
35Figure9.
Currentconsumptionmeasurementscheme35Figure10.
TypicalcurrentconsumptiononVBATwithRTConvs.
temperatureatdifferentVBATvalues42Figure11.
TypicalcurrentconsumptioninStopmodewithregulatorinRunmodeversustemperatureatdifferentVDDvalues42Figure12.
TypicalcurrentconsumptioninStopmodewithregulatorinLow-powermodeversustemperatureatdifferentVDDvalues43Figure13.
TypicalcurrentconsumptioninStandbymodeversustemperatureatdifferentVDDvalues43Figure14.
High-speedexternalclocksourceACtimingdiagram48Figure15.
Low-speedexternalclocksourceACtimingdiagram.
49Figure16.
Typicalapplicationwithan8MHzcrystal50Figure17.
Typicalapplicationwitha32.
768kHzcrystal51Figure18.
StandardI/Oinputcharacteristics-CMOSport58Figure19.
StandardI/Oinputcharacteristics-TTLport59Figure20.
5VtolerantI/Oinputcharacteristics-CMOSport59Figure21.
5VtolerantI/Oinputcharacteristics-TTLport59Figure22.
I/OACcharacteristicsdefinition62Figure23.
RecommendedNRSTpinprotection63Figure24.
I2CbusACwaveformsandmeasurementcircuit65Figure25.
SPItimingdiagram-slavemodeandCPHA=067Figure26.
SPItimingdiagram-slavemodeandCPHA=1(1)67Figure27.
SPItimingdiagram-mastermode(1)68Figure28.
I2Sslavetimingdiagram(Philipsprotocol)(1)70Figure29.
I2Smastertimingdiagram(Philipsprotocol)(1)70Figure30.
USBOTGFStimings:definitionofdatasignalriseandfalltime71Figure31.
EthernetSMItimingdiagram72Figure32.
EthernetRMIItimingdiagram73Figure33.
EthernetMIItimingdiagram73Figure34.
ADCaccuracycharacteristics.
77Figure35.
TypicalconnectiondiagramusingtheADC77Figure36.
Powersupplyandreferencedecoupling(VREF+notconnectedtoVDDA)78Figure37.
Powersupplyandreferencedecoupling(VREF+connectedtoVDDA)78Figure38.
12-bitbuffered/non-bufferedDAC80Figure39.
LFBGA100-10x10mmlowprofilefinepitchballgridarraypackageoutline82Figure40.
LFBGA100–100-balllowprofilefinepitchballgridarray,10x10mm,0.
8mmpitch,packagemechanicaldata83Figure41.
LFBGA100–100-balllowprofilefinepitchballgridarray,10x10mm,0.
8mmpitch,packagerecommendedfootprint83ListoffiguresSTM32F105xx,STM32F107xx8/108DocID15274Rev10Figure42.
LFBGA100markingexample(packagetopview)84Figure43.
LQFP100–14x14mm100pinlow-profilequadflatpackageoutline85Figure44.
LQFP100-100-pin,14x14mmlow-profilequadflatrecommendedfootprint.
86Figure45.
LQFP100markingexample(packagetopview)87Figure46.
LQFP64–10x10mm64pinlow-profilequadflatpackageoutline88Figure47.
LQFP64-64-pin,10x10mmlow-profilequadflatrecommendedfootprint89Figure48.
LQFP64markingexample(packagetopview)90Figure49.
LQFP100PDmaxvs.
TA93Figure50.
USBOTGFSdevicemode.
95Figure51.
Hostconnection95Figure52.
OTGconnection(anyprotocol)96Figure53.
MIImodeusinga25MHzcrystal97Figure54.
RMIIwitha50MHzoscillator97Figure55.
RMIIwitha25MHzcrystalandPHYwithPLL.
98Figure56.
RMIIwitha25MHzcrystal98Figure57.
Completeaudioplayersolution199Figure58.
Completeaudioplayersolution299Figure59.
USBO44TGFS+Ethernetsolution.
100Figure60.
USBOTGFS+I2S(Audio)solution.
100DocID15274Rev109/108STM32F105xx,STM32F107xxIntroduction1071IntroductionThisdatasheetprovidesthedescriptionoftheSTM32F105xxandSTM32F107xxconnectivitylinemicrocontrollers.
FormoredetailsonthewholeSTMicroelectronicsSTM32F10xxxfamily,refertoSection2.
2:Fullcompatibilitythroughoutthefamily.
TheSTM32F105xxandSTM32F107xxdatasheetshouldbereadinconjunctionwiththeSTM32F10xxxreferencemanual.
Forinformationonprogramming,erasingandprotectionoftheinternalFlashmemoryrefertotheSTM32F10xxxFlashprogrammingmanual.
ThereferenceandFlashprogrammingmanualsarebothavailablefromtheSTMicroelectronicswebsitewww.
st.
com.
ForinformationontheCortex-M3corerefertotheCortex-M3TechnicalReferenceManual,availablefromthewww.
arm.
comwebsite.
DescriptionSTM32F105xx,STM32F107xx10/108DocID15274Rev102DescriptionTheSTM32F105xxandSTM32F107xxconnectivitylinefamilyincorporatesthehigh-performanceARMCortex-M332-bitRISCcoreoperatingata72MHzfrequency,high-speedembeddedmemories(Flashmemoryupto256KbytesandSRAM64Kbytes),andanextensiverangeofenhancedI/OsandperipheralsconnectedtotwoAPBbuses.
Alldevicesoffertwo12-bitADCs,fourgeneral-purpose16-bittimersplusaPWMtimer,aswellasstandardandadvancedcommunicationinterfaces:uptotwoI2Cs,threeSPIs,twoI2Ss,fiveUSARTs,anUSBOTGFSandtwoCANs.
EthernetisavailableontheSTM32F107xxonly.
TheSTM32F105xxandSTM32F107xxconnectivitylinefamilyoperatesinthe–40to+105°Ctemperaturerange,froma2.
0to3.
6Vpowersupply.
Acomprehensivesetofpower-savingmodeallowsthedesignoflow-powerapplications.
TheSTM32F105xxandSTM32F107xxconnectivitylinefamilyoffersdevicesinthreedifferentpackagetypes:from64pinsto100pins.
Dependingonthedevicechosen,differentsetsofperipheralsareincluded,thedescriptionbelowgivesanoverviewofthecompleterangeofperipheralsproposedinthisfamily.
ThesefeaturesmaketheSTM32F105xxandSTM32F107xxconnectivitylinemicrocontrollerfamilysuitableforawiderangeofapplicationssuchasmotordrivesandapplicationcontrol,medicalandhandheldequipment,industrialapplications,PLCs,inverters,printers,andscanners,alarmsystems,videointercom,HVACandhomeaudioequipment.
2.
1DeviceoverviewFigure1showsthegeneralblockdiagramofthedevicefamily.
Table2.
STM32F105xxandSTM32F107xxfeaturesandperipheralcountsPeripherals(1)STM32F105RxSTM32F107RxSTM32F105VxSTM32F107VxFlashmemoryinKbytes6412825612825664128256128256SRAMinKbytes64PackageLQFP64LQFP100LQFP100,BGA100LQFP100LQFP100LQFP100,BGA100EthernetNoYesNoYesTimersGeneral-purpose4Advanced-control1Basic2DocID15274Rev1011/108STM32F105xx,STM32F107xxDescription107CommunicationinterfacesSPI(I2S)(2)3(2)3(2)3(2)3(2)I2C2121USART5USBOTGFSYesCAN2GPIOs518012-bitADCNumberofchannels21612-bitDACNumberofchannels22CPUfrequency72MHzOperatingvoltage2.
0to3.
6VOperatingtemperaturesAmbienttemperatures:–40to+85°C/–40to+105°CJunctiontemperature:–40to+125°C1.
RefertoTable5:PindefinitionsforperipheralavailabilitywhentheI/Opinsaresharedbytheperipheralsrequiredbytheapplication.
2.
TheSPI2andSPI3interfacesgivetheflexibilitytoworkineithertheSPImodeortheI2Saudiomode.
Table2.
STM32F105xxandSTM32F107xxfeaturesandperipheralcounts(continued)Peripherals(1)STM32F105RxSTM32F107RxSTM32F105VxSTM32F107VxDescriptionSTM32F105xx,STM32F107xx12/108DocID15274Rev102.
2FullcompatibilitythroughoutthefamilyTheSTM32F105xxandSTM32F107xxconstitutetheconnectivitylinefamilywhosemembersarefullypin-to-pin,softwareandfeaturecompatible.
TheSTM32F105xxandSTM32F107xxareadrop-inreplacementforthelow-density(STM32F103x4/6),medium-density(STM32F103x8/B)andhigh-density(STM32F103xC/D/E)performancelinedevices,allowingtheusertotrydifferentmemorydensitiesandperipheralsprovidingagreaterdegreeoffreedomduringthedevelopmentcycle.
Table3.
STM32F105xxandSTM32F107xxfamilyversusSTM32F103xxfamily(1)STM32deviceLow-densitySTM32F103xxdevicesMedium-densitySTM32F103xxdevicesHigh-densitySTM32F103xxdevicesSTM32F105xxSTM32F107xxFlashsize(KB)1632326412825638451264128256128256RAMsize(KB)6101020204864646464646464144pins5*USARTs4*16-bittimers,2*basictimers,3*SPIs,2*I2Ss,2*I2Cs,USB,CAN,2*PWMtimers3*ADCs,2*DACs,1*SDIO,FSMC(100-and144-pinpackages(2))100pins3*USARTs3*16-bittimers2*SPIs,2*I2Cs,USB,CAN,1*PWMtimer2*ADCs5*USARTs,4*16-bittimers,2*basictimers,3*SPIs,2*I2Ss,2*I2Cs,USBOTGFS,2*CANs,1*PWMtimer,2*ADCs,2*DACs5*USARTs,4*16-bittimers,2*basictimers,3*SPIs,2*I2S,1*I2C,USBOTGFS,2*CANs,1*PWMtimer,2*ADCs,2*DACs,Ethernet64pins2*USARTs2*16-bittimers1*SPI,1*I2C,USB,CAN,1*PWMtimer2*ADCs2*USARTs2*16-bittimers1*SPI,1*I2C,USB,CAN,1*PWMtimer2*ADCs48pins36pins1.
RefertoTable5:PindefinitionsforperipheralavailabilitywhentheI/Opinsaresharedbytheperipheralsrequiredbytheapplication.
2.
PortsFandGarenotavailableindevicesdeliveredin100-pinpackages.
DocID15274Rev1013/108STM32F105xx,STM32F107xxDescription1072.
3OverviewFigure1.
STM32F105xxandSTM32F107xxconnectivitylineblockdiagram1.
TA=–40°Cto+85°C(suffix6,seeTable62)or–40°Cto+105°C(suffix7,seeTable62),junctiontemperatureupto105°Cor125°C,respectively.
2.
AF=alternatefunctiononI/Oportpin.
PA[15:0]EXT.
ITWWDG12bitADC116ADC12_INscommontoADC1&ADC2JTDIJTCK/SWCLKJTMS/SWDIONJTRSTJTDONRSTVDD=2to3.
6V80AFPB[15:0]PC[15:0]AHBtoAPB2CAN1_RXasAF2x(8x16bit)WKUPGPIOportAPGPIOportBPFmax:72MHzVSSSCL,SDA,SMBAI2C2GPDMA1TIM2TIM3XTALosc3-25MHzXTAL32kHzOSC_INOSC_OUTC_OOSC32_OUTOSC32_INAPB1:Fmax=36MHzHCLKasAFFlash256KBVoltagereg.
3.
3Vto1.
8VVDD18PowerBackupinterfaceasAFTIM4BusMatrix64bitInterfaceRTCRCHSCortex-M3CPUIbusDbusoblFlashlSRAM512BUSART1USART2SPI2/I2S2(1)bxCAN17channelsBackupregister4ChannelsTIM14compl.
ChannelsSCL,SDA,SMBAI2C1asAFRX,TX,CTS,RTS,USART3TempsensorPD[15:0]PE[15:0]BKIN,ETRinputasAF4Channels,ETR4Channels,ETR4Channels,ETRFCLKRCLSStandbyIWDG@VDD@VBATPOR/PDRSupplysupervision@VDDAVDDAVSSA@VDDAVBAT=1.
8Vto3.
6VCKasAFRX,TX,CTS,RTS,CKasAFRX,TX,CTS,RTS,CKasAFAPB2:Fmax=72MHzNVICSPI1MOSI,MISO,SCK,NSSasAF12bitADC2IFIFinterfacePVDResetInt@VDDAHBtoAPB1AWUPORTAMPER-RTC/ALARM/SECONDOUTSystem2x(8x16bit)SPI3/I2S3UART4RX,TXasAFUART5RX,TXasAFTIM54Channels,ETRReset&clockcontrol12bitDAC1IFIFIF12bitDAC2@VDDAUSBOTGFSSOFVBUSIDDMDPSRAM64KBGPDMA25channelsTIM6TIM7CAN1_TXasAFSW/JTAGTPIUETMTrace/TrigTRACECLKTRACED[0:3]asAFasAFasAFasAFasAFEthernetMAC10/100SRAM1.
25KBDPRAM2KBDPRAM2KBMII_TXD[3:0]/RMII_TXD[1:0]MII_TX_CLK/RMII_TX_CLKMII_TX_EN/RMII_TX_ENMII_RXD[3:0]/RMII_RXD[1:0]MII_RX_ER/RMII_RX_ERMII_RX_CLK/RMII_REF_CLKMII_RX_DV/RMII_CRS_DVMII_CRSMII_COL/RMII_COLMDCMDIOPPS_OUTbxCAN2CAN2_RXasAFCAN2_TXasAFai15411DAC_OUT1asAFDAC_OUT2asAF@VDDAPLLGPIOportCGPIOportDGPIOportEVREF+VREF–MOSI/SD,MISO,MCK,SCK/CK,NSS/WSasAFMOSI/SD,MISO,MCK,SCK/CK,NSS/WSasAFPCLK1PCLK2PLL2PLL3PLL3DMAEthernetAHBDescriptionSTM32F105xx,STM32F107xx14/108DocID15274Rev102.
3.
1ARMCortex-M3corewithembeddedFlashandSRAMTheARMCortex-M3processoristhelatestgenerationofARMprocessorsforembeddedsystems.
Ithasbeendevelopedtoprovidealow-costplatformthatmeetstheneedsofMCUimplementation,withareducedpincountandlow-powerconsumption,whiledeliveringoutstandingcomputationalperformanceandanadvancedsystemresponsetointerrupts.
TheARMCortex-M332-bitRISCprocessorfeaturesexceptionalcode-efficiency,deliveringthehigh-performanceexpectedfromanARMcoreinthememorysizeusuallyassociatedwith8-and16-bitdevices.
WithitsembeddedARMcore,STM32F105xxandSTM32F107xxconnectivitylinefamilyiscompatiblewithallARMtoolsandsoftware.
Figure1showsthegeneralblockdiagramofthedevicefamily.
2.
3.
2EmbeddedFlashmemory64to256KbytesofembeddedFlashisavailableforstoringprogramsanddata.
2.
3.
3CRC(cyclicredundancycheck)calculationunitTheCRC(cyclicredundancycheck)calculationunitisusedtogetaCRCcodefroma32-bitdatawordandafixedgeneratorpolynomial.
Amongotherapplications,CRC-basedtechniquesareusedtoverifydatatransmissionorstorageintegrity.
InthescopeoftheEN/IEC60335-1standard,theyofferameansofverifyingtheFlashmemoryintegrity.
TheCRCcalculationunithelpscomputeasignatureofthesoftwareduringruntime,tobecomparedwithareferencesignaturegeneratedatlink-timeandstoredatagivenmemorylocation.
2.
3.
4EmbeddedSRAM64KbytesofembeddedSRAMaccessed(read/write)atCPUclockspeedwith0waitstates.
2.
3.
5Nestedvectoredinterruptcontroller(NVIC)TheSTM32F105xxandSTM32F107xxconnectivitylineembedsanestedvectoredinterruptcontrollerabletohandleupto67maskableinterruptchannels(notincludingthe16interruptlinesofCortex-M3)and16prioritylevels.
CloselycoupledNVICgiveslowlatencyinterruptprocessingInterruptentryvectortableaddresspasseddirectlytothecoreCloselycoupledNVICcoreinterfaceAllowsearlyprocessingofinterruptsProcessingoflatearrivinghigherpriorityinterruptsSupportfortail-chainingProcessorstateautomaticallysavedInterruptentryrestoredoninterruptexitwithnoinstructionoverheadThishardwareblockprovidesflexibleinterruptmanagementfeatureswithminimalinterruptlatency.
DocID15274Rev1015/108STM32F105xx,STM32F107xxDescription1072.
3.
6Externalinterrupt/eventcontroller(EXTI)Theexternalinterrupt/eventcontrollerconsistsof20edgedetectorlinesusedtogenerateinterrupt/eventrequests.
Eachlinecanbeindependentlyconfiguredtoselectthetriggerevent(risingedge,fallingedge,both)andcanbemaskedindependently.
Apendingregistermaintainsthestatusoftheinterruptrequests.
TheEXTIcandetectanexternallinewithapulsewidthshorterthantheInternalAPB2clockperiod.
Upto80GPIOscanbeconnectedtothe16externalinterruptlines.
2.
3.
7ClocksandstartupSystemclockselectionisperformedonstartup,however,theinternalRC8MHzoscillatorisselectedasdefaultCPUclockonreset.
Anexternal3-25MHzclockcanbeselected,inwhichcaseitismonitoredforfailure.
Iffailureisdetected,thesystemautomaticallyswitchesbacktotheinternalRCoscillator.
Asoftwareinterruptisgeneratedifenabled.
Similarly,fullinterruptmanagementofthePLLclockentryisavailablewhennecessary(forexamplewithfailureofanindirectlyusedexternaloscillator).
Asingle25MHzcrystalcanclocktheentiresystemincludingtheethernetandUSBOTGFSperipherals.
SeveralprescalersandPLLsallowtheconfigurationoftheAHBfrequency,thehighspeedAPB(APB2)andthelowspeedAPB(APB1)domains.
ThemaximumfrequencyoftheAHBandthehighspeedAPBdomainsis72MHz.
ThemaximumallowedfrequencyofthelowspeedAPBdomainis36MHz.
RefertoFigure59:USBO44TGFS+Ethernetsolutiononpage100.
Theadvancedclockcontrollerclocksthecoreandallperipheralsusingasinglecrystaloroscillator.
Inordertoachieveaudioclassperformance,anaudiocrystalcanbeused.
Inthiscase,theI2Smasterclockcangenerateallstandardsamplingfrequenciesfrom8kHzto96kHzwithlessthan0.
5%accuracyerror.
RefertoFigure60:USBOTGFS+I2S(Audio)solutiononpage100.
ToconfigurethePLLs,refertoTable63onpage101,whichprovidesPLLconfigurationsaccordingtotheapplicationtype.
2.
3.
8BootmodesAtstartup,bootpinsareusedtoselectoneofthreebootoptions:BootfromUserFlashBootfromSystemMemoryBootfromembeddedSRAMThebootloaderislocatedinSystemMemory.
ItisusedtoreprogramtheFlashmemorybyusingUSART1,USART2(remapped),CAN2(remapped)orUSBOTGFSindevicemode(DFU:devicefirmwareupgrade).
ForremappedsignalsrefertoTable5:Pindefinitions.
TheUSARTperipheraloperateswiththeinternal8MHzoscillator(HSI),howevertheCANandUSBOTGFScanonlyfunctionifanexternal8MHz,14.
7456MHzor25MHzclock(HSE)ispresent.
Forfulldetailsaboutthebootloader,refertoAN2606.
DescriptionSTM32F105xx,STM32F107xx16/108DocID15274Rev102.
3.
9PowersupplyschemesVDD=2.
0to3.
6V:externalpowersupplyforI/Osandtheinternalregulator.
ProvidedexternallythroughVDDpins.
VSSA,VDDA=2.
0to3.
6V:externalanalogpowersuppliesforADC,Resetblocks,RCsandPLL(minimumvoltagetobeappliedtoVDDAis2.
4VwhentheADCisused).
VDDAandVSSAmustbeconnectedtoVDDandVSS,respectively.
VBAT=1.
8to3.
6V:powersupplyforRTC,externalclock32kHzoscillatorandbackupregisters(throughpowerswitch)whenVDDisnotpresent.
2.
3.
10PowersupplysupervisorThedevicehasanintegratedpower-onreset(POR)/power-downreset(PDR)circuitry.
Itisalwaysactive,andensuresproperoperationstartingfrom/downto2V.
ThedeviceremainsinresetmodewhenVDDisbelowaspecifiedthreshold,VPOR/PDR,withouttheneedforanexternalresetcircuit.
Thedevicefeaturesanembeddedprogrammablevoltagedetector(PVD)thatmonitorstheVDD/VDDApowersupplyandcomparesittotheVPVDthreshold.
AninterruptcanbegeneratedwhenVDD/VDDAdropsbelowtheVPVDthresholdand/orwhenVDD/VDDAishigherthantheVPVDthreshold.
Theinterruptserviceroutinecanthengenerateawarningmessageand/orputtheMCUintoasafestate.
ThePVDisenabledbysoftware.
2.
3.
11VoltageregulatorTheregulatorhasthreeoperationmodes:main(MR),lowpower(LPR)andpowerdown.
MRisusedinthenominalregulationmode(Run)LPRisusedintheStopmodes.
PowerdownisusedinStandbymode:theregulatoroutputisinhighimpedance:thekernelcircuitryispowereddown,inducingzeroconsumption(butthecontentsoftheregistersandSRAMarelost)Thisregulatorisalwaysenabledafterreset.
ItisdisabledinStandbymode.
2.
3.
12Low-powermodesTheSTM32F105xxandSTM32F107xxconnectivitylinesupportsthreelow-powermodestoachievethebestcompromisebetweenlowpowerconsumption,shortstartuptimeandavailablewakeupsources:SleepmodeInSleepmode,onlytheCPUisstopped.
AllperipheralscontinuetooperateandcanwakeuptheCPUwhenaninterrupt/eventoccurs.
StopmodeStopmodeachievesthelowestpowerconsumptionwhileretainingthecontentofSRAMandregisters.
Allclocksinthe1.
8Vdomainarestopped,thePLL,theHSIRCandtheHSEcrystaloscillatorsaredisabled.
Thevoltageregulatorcanalsobeputeitherinnormalorinlow-powermode.
ThedevicecanbewokenupfromStopmodebyanyoftheEXTIline.
TheEXTIlinesourcecanbeoneofthe16externallines,thePVDoutput,theRTCalarmortheUSBOTGFSwakeup.
DocID15274Rev1017/108STM32F105xx,STM32F107xxDescription107StandbymodeTheStandbymodeisusedtoachievethelowestpowerconsumption.
Theinternalvoltageregulatorisswitchedoffsothattheentire1.
8Vdomainispoweredoff.
ThePLL,theHSIRCandtheHSEcrystaloscillatorsarealsoswitchedoff.
AfterenteringStandbymode,SRAMandregistercontentsarelostexceptforregistersintheBackupdomainandStandbycircuitry.
ThedeviceexitsStandbymodewhenanexternalreset(NRSTpin),anIWDGreset,arisingedgeontheWKUPpin,oranRTCalarmoccurs.
Note:TheRTC,theIWDG,andthecorrespondingclocksourcesarenotstoppedbyenteringStoporStandbymode.
2.
3.
13DMATheflexible12-channelgeneral-purposeDMAs(7channelsforDMA1and5channelsforDMA2)areabletomanagememory-to-memory,peripheral-to-memoryandmemory-to-peripheraltransfers.
ThetwoDMAcontrollerssupportcircularbuffermanagement,removingtheneedforusercodeinterventionwhenthecontrollerreachestheendofthebuffer.
EachchannelisconnectedtodedicatedhardwareDMArequests,withsupportforsoftwaretriggeroneachchannel.
Configurationismadebysoftwareandtransfersizesbetweensourceanddestinationareindependent.
TheDMAcanbeusedwiththemainperipherals:SPI,I2C,USART,general-purpose,basicandadvancedcontroltimersTIMx,DAC,I2SandADC.
IntheSTM32F107xx,thereisaDMAcontrollerdedicatedforusewiththeEthernet(seeSection2.
3.
20:EthernetMACinterfacewithdedicatedDMAandIEEE1588supportformoreinformation).
2.
3.
14RTC(real-timeclock)andbackupregistersTheRTCandthebackupregistersaresuppliedthroughaswitchthattakespowereitheronVDDsupplywhenpresentorthroughtheVBATpin.
Thebackupregistersareforty-two16-bitregistersusedtostore84bytesofuserapplicationdatawhenVDDpowerisnotpresent.
Theyarenotresetbyasystemorpowerreset,andtheyarenotresetwhenthedevicewakesupfromtheStandbymode.
Thereal-timeclockprovidesasetofcontinuouslyrunningcounterswhichcanbeusedwithsuitablesoftwaretoprovideaclockcalendarfunction,andprovidesanalarminterruptandaperiodicinterrupt.
Itisclockedbya32.
768kHzexternalcrystal,resonatororoscillator,theinternallowpowerRCoscillatororthehigh-speedexternalclockdividedby128.
Theinternallow-speedRChasatypicalfrequencyof40kHz.
TheRTCcanbecalibratedusinganexternal512Hzoutputtocompensateforanynaturalquartzdeviation.
TheRTCfeaturesa32-bitprogrammablecounterforlongtermmeasurementusingtheCompareregistertogenerateanalarm.
A20-bitprescalerisusedforthetimebaseclockandisbydefaultconfiguredtogenerateatimebaseof1secondfromaclockat32.
768kHz.
Formoreinformation,refertoAN2604:"STM32F101xxandSTM32F103xxRTCcalibration",availablefromwww.
st.
com.
DescriptionSTM32F105xx,STM32F107xx18/108DocID15274Rev102.
3.
15TimersandwatchdogsTheSTM32F105xxandSTM32F107xxdevicesincludeanadvanced-controltimer,fourgeneral-purposetimers,twobasictimers,twowatchdogtimersandaSysTicktimer.
Table4comparesthefeaturesofthegeneral-purposeandbasictimers.
Advanced-controltimer(TIM1)Theadvancedcontroltimer(TIM1)canbeseenasathree-phasePWMmultiplexedon6channels.
IthascomplementaryPWMoutputswithprogrammableinserteddead-times.
Itcanalsobeseenasacompletegeneral-purposetimer.
The4independentchannelscanbeusedfor:InputcaptureOutputcomparePWMgeneration(edgeorcenter-alignedmodes)One-pulsemodeoutputIfconfiguredasastandard16-bittimer,ithasthesamefeaturesastheTIMxtimer.
Ifconfiguredasthe16-bitPWMgenerator,ithasfullmodulationcapability(0-100%).
Thecountercanbefrozenindebugmode.
ManyfeaturesaresharedwiththoseofthestandardTIMtimerswhichhavethesamearchitecture.
TheadvancedcontroltimercanthereforeworktogetherwiththeTIMtimersviatheTimerLinkfeatureforsynchronizationoreventchaining.
General-purposetimers(TIMx)Thereareupto4synchronizablestandardtimers(TIM2,TIM3,TIM4andTIM5)embeddedintheSTM32F105xxandSTM32F107xxconnectivitylinedevices.
Thesetimersarebasedona16-bitauto-reloadup/downcounter,a16-bitprescalerandfeature4independentchannelseachforinputcapture/outputcompare,PWMoronepulsemodeoutput.
Thisgivesupto16inputcaptures/outputcompares/PWMsonthelargestpackages.
TheycanworktogetherwiththeAdvancedControltimerviatheTimerLinkfeatureforsynchronizationoreventchaining.
Thecountercanbefrozenindebugmode.
Table4.
TimerfeaturecomparisonTimerCounterresolutionCountertypePrescalerfactorDMArequestgenerationCapture/comparechannelsComplementaryoutputsTIM116-bitUp,down,up/downAnyintegerbetween1and65536Yes4YesTIMx(TIM2,TIM3,TIM4,TIM5)16-bitUp,down,up/downAnyintegerbetween1and65536Yes4NoTIM6,TIM716-bitUpAnyintegerbetween1and65536Yes0NoDocID15274Rev1019/108STM32F105xx,STM32F107xxDescription107AnyofthestandardtimerscanbeusedtogeneratePWMoutputs.
EachofthetimershasindependentDMArequestgenerations.
BasictimersTIM6andTIM7ThesetimersaremainlyusedforDACtriggergeneration.
Theycanalsobeusedasageneric16-bittimebase.
IndependentwatchdogTheindependentwatchdogisbasedona12-bitdowncounterand8-bitprescaler.
Itisclockedfromanindependent40kHzinternalRCandasitoperatesindependentlyfromthemainclock,itcanoperateinStopandStandbymodes.
Itcanbeusedeitherasawatchdogtoresetthedevicewhenaproblemoccurs,orasafreerunningtimerforapplicationtimeoutmanagement.
Itishardwareorsoftwareconfigurablethroughtheoptionbytes.
Thecountercanbefrozenindebugmode.
WindowwatchdogThewindowwatchdogisbasedona7-bitdowncounterthatcanbesetasfreerunning.
Itcanbeusedasawatchdogtoresetthedevicewhenaproblemoccurs.
Itisclockedfromthemainclock.
Ithasanearlywarninginterruptcapabilityandthecountercanbefrozenindebugmode.
SysTicktimerThistimerisdedicatedtoreal-timeoperatingsystems,butcouldalsobeusedasastandarddowncounter.
Itfeatures:A24-bitdowncounterAutoreloadcapabilityMaskablesysteminterruptgenerationwhenthecounterreaches0.
Programmableclocksource2.
3.
16ICbusUptotwoICbusinterfacescanoperateinmultimasterandslavemodes.
Theycansupportstandardandfastmodes.
Theysupport7/10-bitaddressingmodeand7-bitdualaddressingmode(asslave).
AhardwareCRCgeneration/verificationisembedded.
TheycanbeservedbyDMAandtheysupportSMBus2.
0/PMBus.
2.
3.
17Universalsynchronous/asynchronousreceivertransmitters(USARTs)TheSTM32F105xxandSTM32F107xxconnectivitylineembedsthreeuniversalsynchronous/asynchronousreceivertransmitters(USART1,USART2andUSART3)andtwouniversalasynchronousreceivertransmitters(UART4andUART5).
Thesefiveinterfacesprovideasynchronouscommunication,IrDASIRENDECsupport,multiprocessorcommunicationmode,single-wirehalf-duplexcommunicationmodeandhaveLINMaster/Slavecapability.
TheUSART1interfaceisabletocommunicateatspeedsofupto4.
5Mbit/s.
Theotheravailableinterfacescommunicateatupto2.
25Mbit/s.
DescriptionSTM32F105xx,STM32F107xx20/108DocID15274Rev10USART1,USART2andUSART3alsoprovidehardwaremanagementoftheCTSandRTSsignals,SmartCardmode(ISO7816compliant)andSPI-likecommunicationcapability.
AllinterfacescanbeservedbytheDMAcontrollerexceptforUART5.
2.
3.
18Serialperipheralinterface(SPI)UptothreeSPIsareabletocommunicateupto18Mbits/sinslaveandmastermodesinfull-duplexandsimplexcommunicationmodes.
The3-bitprescalergives8mastermodefrequenciesandtheframeisconfigurableto8bitsor16bits.
ThehardwareCRCgeneration/verificationsupportsbasicSDCard/MMC/SDHC(a)modes.
AllSPIscanbeservedbytheDMAcontroller.
2.
3.
19Inter-integratedsound(I2S)TwostandardI2Sinterfaces(multiplexedwithSPI2andSPI3)areavailable,thatcanbeoperatedinmasterorslavemode.
Theseinterfacescanbeconfiguredtooperatewith16/32bitresolution,asinputoroutputchannels.
Audiosamplingfrequenciesfrom8kHzupto96kHzaresupported.
WheneitherorbothoftheI2Sinterfacesis/areconfiguredinmastermode,themasterclockcanbeoutputtotheexternalDAC/CODECat256timesthesamplingfrequencywithlessthan0.
5%accuracyerrorowingtotheadvancedclockcontroller(seeSection2.
3.
7:Clocksandstartup).
Refertothe"Audiofrequencyprecision"tablesprovidedinthe"Serialperipheralinterface(SPI)"sectionoftheSTM32F10xxxreferencemanual.
2.
3.
20EthernetMACinterfacewithdedicatedDMAandIEEE1588supportPeripheralnotavailableonSTM32F105xxdevices.
TheSTM32F107xxdevicesprovideanIEEE-802.
3-2002-compliantmediaaccesscontroller(MAC)forethernetLANcommunicationsthroughanindustry-standardmedia-independentinterface(MII)orareducedmedia-independentinterface(RMII).
TheSTM32F107xxrequiresanexternalphysicalinterfacedevice(PHY)toconnecttothephysicalLANbus(twisted-pair,fiber,etc.
).
thePHYisconnectedtotheSTM32F107xxMIIportusingasmanyas17signals(MII)or9signals(RMII)andcanbeclockedusingthe25MHz(MII)or50MHz(RMII)outputfromtheSTM32F107xx.
TheSTM32F107xxincludesthefollowingfeatures:Supports10and100Mbit/sratesDedicatedDMAcontrollerallowinghigh-speedtransfersbetweenthededicatedSRAMandthedescriptors(seetheSTM32F105xx/STM32F107xxreferencemanualfordetails)TaggedMACframesupport(VLANsupport)Half-duplex(CSMA/CD)andfull-duplexoperationMACcontrolsublayer(controlframes)supporta.
SDHC=Securedigitalhighcapacity.
DocID15274Rev1021/108STM32F105xx,STM32F107xxDescription10732-bitCRCgenerationandremovalSeveraladdressfilteringmodesforphysicalandmulticastaddress(multicastandgroupaddresses)32-bitstatuscodeforeachtransmittedorreceivedframeInternalFIFOstobuffertransmitandreceiveframes.
ThetransmitFIFOandthereceiveFIFOareboth2Kbytes,thatis4KbytesintotalSupportshardwarePTP(precisiontimeprotocol)inaccordancewithIEEE1588withthetimestampcomparatorconnectedtotheTIM2triggerinputTriggersinterruptwhensystemtimebecomesgreaterthantargettime2.
3.
21Controllerareanetwork(CAN)ThetwoCANsarecompliantwiththe2.
0AandB(active)specificationswithabitrateupto1Mbit/s.
Theycanreceiveandtransmitstandardframeswith11-bitidentifiersaswellasextendedframeswith29-bitidentifiers.
EachCANhasthreetransmitmailboxes,tworeceiveFIFOSwith3stagesand28sharedscalablefilterbanks(allofthemcanbeusedevenifoneCANisused).
The256bytesofSRAMwhichareallocatedforeachCAN(512bytesintotal)arenotsharedwithanyotherperipheral.
2.
3.
22Universalserialbuson-the-gofull-speed(USBOTGFS)TheSTM32F105xxandSTM32F107xxconnectivitylinedevicesembedaUSBOTGfull-speed(12Mb/s)device/host/OTGperipheralwithintegratedtransceivers.
TheUSBOTGFSperipheraliscompliantwiththeUSB2.
0specificationandwiththeOTG1.
0specification.
Ithassoftware-configurableendpointsettingandsupportssuspend/resume.
TheUSBOTGfull-speedcontrollerrequiresadedicated48MHzclockthatisgeneratedbyaPLLconnectedtotheHSEoscillator.
Themajorfeaturesare:1.
25KBofSRAMusedexclusivelybytheendpoints(notsharedwithanyotherperipheral)4bidirectionalendpointsHNP/SNP/IPinside(noneedforanyexternalresistor)forOTG/Hostmodes,apowerswitchisneededincasebus-powereddevicesareconnectedtheSOFoutputcanbeusedtosynchronizetheexternalaudioDACclockinisochronousmodeinaccordancewiththeUSB2.
0Specification,thesupportedtransferspeedsare:–inHostmode:fullspeedandlowspeed–inDevicemode:fullspeed2.
3.
23GPIOs(general-purposeinputs/outputs)EachoftheGPIOpinscanbeconfiguredbysoftwareasoutput(push-pulloropen-drain),asinput(withorwithoutpull-uporpull-down)orasperipheralalternatefunction.
MostoftheGPIOpinsaresharedwithdigitaloranalogalternatefunctions.
AllGPIOsarehighcurrent-capable.
TheI/OsalternatefunctionconfigurationcanbelockedifneededfollowingaspecificsequenceinordertoavoidspuriouswritingtotheI/Osregisters.
I/OsonAPB2withupto18MHztogglingspeedDescriptionSTM32F105xx,STM32F107xx22/108DocID15274Rev102.
3.
24RemapcapabilityThisfeatureallowstheuseofamaximumnumberofperipheralsinagivenapplication.
Indeed,alternatefunctionsareavailablenotonlyonthedefaultpinsbutalsoonotherspecificpinsontowhichtheyareremappable.
Thishastheadvantageofmakingboarddesignandportusagemuchmoreflexible.
FordetailsrefertoTable5:Pindefinitions;itshowsthelistofremappablealternatefunctionsandthepinsontowhichtheycanberemapped.
SeetheSTM32F10xxxreferencemanualforsoftwareconsiderations.
2.
3.
25ADCs(analog-to-digitalconverters)Two12-bitanalog-to-digitalconvertersareembeddedintoSTM32F105xxandSTM32F107xxconnectivitylinedevicesandeachADCsharesupto16externalchannels,performingconversionsinsingle-shotorscanmodes.
Inscanmode,automaticconversionisperformedonaselectedgroupofanaloginputs.
AdditionallogicfunctionsembeddedintheADCinterfaceallow:SimultaneoussampleandholdInterleavedsampleandholdSingleshuntTheADCcanbeservedbytheDMAcontroller.
Ananalogwatchdogfeatureallowsveryprecisemonitoringoftheconvertedvoltageofone,someorallselectedchannels.
Aninterruptisgeneratedwhentheconvertedvoltageisoutsidetheprogrammedthresholds.
Theeventsgeneratedbythestandardtimers(TIMx)andtheadvanced-controltimer(TIM1)canbeinternallyconnectedtotheADCstarttriggerandinjectiontrigger,respectively,toallowtheapplicationtosynchronizeA/Dconversionandtimers.
2.
3.
26DAC(digital-to-analogconverter)Thetwo12-bitbufferedDACchannelscanbeusedtoconverttwodigitalsignalsintotwoanalogvoltagesignaloutputs.
Thechosendesignstructureiscomposedofintegratedresistorstringsandanamplifierininvertingconfiguration.
ThisdualdigitalInterfacesupportsthefollowingfeatures:twoDACconverters:oneforeachoutputchannel8-bitor12-bitmonotonicoutputleftorrightdataalignmentin12-bitmodesynchronizedupdatecapabilitynoise-wavegenerationtriangular-wavegenerationdualDACchannelindependentorsimultaneousconversionsDMAcapabilityforeachchannelexternaltriggersforconversioninputvoltagereferenceVREF+DocID15274Rev1023/108STM32F105xx,STM32F107xxDescription107EightDACtriggerinputsareusedintheSTM32F105xxandSTM32F107xxconnectivitylinefamily.
TheDACchannelsaretriggeredthroughthetimerupdateoutputsthatarealsoconnectedtodifferentDMAchannels.
2.
3.
27TemperaturesensorThetemperaturesensorhastogenerateavoltagethatvarieslinearlywithtemperature.
Theconversionrangeisbetween2V2.
3.
28SerialwireJTAGdebugport(SWJ-DP)TheARMSWJ-DPInterfaceisembedded,andisacombinedJTAGandserialwiredebugportthatenableseitheraserialwiredebugoraJTAGprobetobeconnectedtothetarget.
TheJTAGTMSandTCKpinsaresharedrespectivelywithSWDIOandSWCLKandaspecificsequenceontheTMSpinisusedtoswitchbetweenJTAG-DPandSW-DP.
2.
3.
29EmbeddedTraceMacrocellTheARMEmbeddedTraceMacrocellprovidesagreatervisibilityoftheinstructionanddataflowinsidetheCPUcorebystreamingcompresseddataataveryhighratefromtheSTM32F10xxxthroughasmallnumberofETMpinstoanexternalhardwaretraceportanalyzer(TPA)device.
TheTPAisconnectedtoahostcomputerusingUSB,Ethernet,oranyotherhigh-speedchannel.
Real-timeinstructionanddataflowactivitycanberecordedandthenformattedfordisplayonthehostcomputerrunningdebuggersoftware.
TPAhardwareiscommerciallyavailablefromcommondevelopmenttoolvendors.
Itoperateswiththirdpartydebuggersoftwaretools.
PinoutsandpindescriptionSTM32F105xx,STM32F107xx24/108DocID15274Rev103PinoutsandpindescriptionFigure2.
STM32F105xxandSTM32F107xxconnectivitylineBGA100ballouttopviewAI14601cPE10PC14-OSC32_INPC5PA5PC3PB4PE15PB2PC4PA4HPE14PE11PE7DPD4PD3PB8PE3CPD0PC12PE5PB5PC0PE2BPC11PD2PC15-OSC32_OUTPB7PB6A87654321VSS_5OSC_INOSC_OUTVDD_5GFEPC1VREF–PC13-TAMPER-RTCPB9PA15PB3PE4PE1PE0VSS_1PD1PE6NRSTPC2VSS_3VSS_4NCVDD_3VDD_4PB15VBATPD5PD6BOOT0PD7VSS_2VSSAPA1VDD_2VDD_1PB14PA0-WKUP109KJPD10PD11PA8PA9PA10PA11PA12PC10PA13PA14PC9PC7PC6PD15PC8PD14PE12PB1PA7PB11PE8PB0PA6PB10PE13PE9VDDAPB13VREF+PA3PB12PA2PD8PD9PD13PD12DocID15274Rev1025/108STM32F105xx,STM32F107xxPinoutsandpindescription107Figure3.
STM32F105xxandSTM32F107xxconnectivitylineLQFP100pinoutAI6$$633.
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,1&0PinoutsandpindescriptionSTM32F105xx,STM32F107xx26/108DocID15274Rev10Figure4.
STM32F105xxandSTM32F107xxconnectivitylineLQFP64pinoutsdWdDWZZdWK^/EWK^KhdWK^/EWK^KhdEZ^dWWWWs^^sWtY&WDLDocID15274Rev1027/108STM32F105xx,STM32F107xxPinoutsandpindescription107Table5.
PindefinitionsPinsPinnameType(1)I/OLevel(2)Mainfunction(3)(afterreset)Alternatefunctions(4)BGA100LQFP64LQFP100DefaultRemapA3-1PE2I/OFTPE2TRACECK-B3-2PE3I/OFTPE3TRACED0-C3-3PE4I/OFTPE4TRACED1-D3-4PE5I/OFTPE5TRACED2-E3-5PE6I/OFTPE6TRACED3-B216VBATS-VBAT--A227PC13-TAMPER-RTC(5)I/O-PC13(6)TAMPER-RTC-A138PC14-OSC32_IN(5)I/O-PC14(6)OSC32_IN-B149PC15-OSC32_OUT(5)I/O-PC15(6)OSC32_OUT-C2-10VSS_5S-VSS_5--D2-11VDD_5S-VDD_5--C1512OSC_INI-OSC_IN--D1613OSC_OUTO-OSC_OUT--E1714NRSTI/O-NRST--F1815PC0I/O-PC0ADC12_IN10-F2916PC1I/O-PC1ADC12_IN11/ETH_MII_MDC/ETH_RMII_MDC-E21017PC2I/O-PC2ADC12_IN12/ETH_MII_TXD2-F31118PC3I/O-PC3ADC12_IN13/ETH_MII_TX_CLK-G11219VSSAS-VSSA--H1-20VREF-S-VREF---J1-21VREF+S-VREF+--K11322VDDAS-VDDA--G21423PA0-WKUPI/O-PA0WKUP/USART2_CTS(7)ADC12_IN0/TIM2_CH1_ETRTIM5_CH1/ETH_MII_CRS_WKUP-PinoutsandpindescriptionSTM32F105xx,STM32F107xx28/108DocID15274Rev10H21524PA1I/O-PA1USART2_RTS(7)/ADC12_IN1/TIM5_CH2/TIM2_CH2(7)/ETH_MII_RX_CLK/ETH_RMII_REF_CLK-J21625PA2I/O-PA2USART2_TX(7)/TIM5_CH3/ADC12_IN2/TIM2_CH3(7)/ETH_MII_MDIO/ETH_RMII_MDIO-K21726PA3I/O-PA3USART2_RX(7)/TIM5_CH4/ADC12_IN3/TIM2_CH4(7)/ETH_MII_COL-E41827VSS_4S-VSS_4--F41928VDD_4S-VDD_4--G32029PA4I/O-PA4SPI1_NSS(7)/DAC_OUT1/USART2_CK(7)/ADC12_IN4SPI3_NSS/I2S3_WSH32130PA5I/O-PA5SPI1_SCK(7)/DAC_OUT2/ADC12_IN5-J32231PA6I/O-PA6SPI1_MISO(7)/ADC12_IN6/TIM3_CH1(7)TIM1_BKINK32332PA7I/O-PA7SPI1_MOSI(7)/ADC12_IN7/TIM3_CH2(7)/ETH_MII_RX_DV(8)/ETH_RMII_CRS_DVTIM1_CH1NG42433PC4I/O-PC4ADC12_IN14/ETH_MII_RXD0(8)/ETH_RMII_RXD0-H42534PC5I/O-PC5ADC12_IN15/ETH_MII_RXD1(8)/ETH_RMII_RXD1-J42635PB0I/O-PB0ADC12_IN8/TIM3_CH3/ETH_MII_RXD2(8)TIM1_CH2NK42736PB1I/O-PB1ADC12_IN9/TIM3_CH4(7)/ETH_MII_RXD3(8)TIM1_CH3NG52837PB2I/OFTPB2/BOOT1--H5-38PE7I/OFTPE7-TIM1_ETRJ5-39PE8I/OFTPE8-TIM1_CH1NTable5.
Pindefinitions(continued)PinsPinnameType(1)I/OLevel(2)Mainfunction(3)(afterreset)Alternatefunctions(4)BGA100LQFP64LQFP100DefaultRemapDocID15274Rev1029/108STM32F105xx,STM32F107xxPinoutsandpindescription107K5-40PE9I/OFTPE9-TIM1_CH1---VSS_7S-------VDD_7S----G6-41PE10I/OFTPE10-TIM1_CH2NH6-42PE11I/OFTPE11-TIM1_CH2J6-43PE12I/OFTPE12-TIM1_CH3NK6-44PE13I/OFTPE13-TIM1_CH3G7-45PE14I/OFTPE14-TIM1_CH4H7-46PE15I/OFTPE15-TIM1_BKINJ72947PB10I/OFTPB10I2C2_SCL(8)/USART3_TX(7)/ETH_MII_RX_ERTIM2_CH3K73048PB11I/OFTPB11I2C2_SDA(8)/USART3_RX(7)/ETH_MII_TX_EN/ETH_RMII_TX_ENTIM2_CH4E73149VSS_1S-VSS_1--F73250VDD_1S-VDD_1--K83351PB12I/OFTPB12SPI2_NSS(8)/I2S2_WS(8)/I2C2_SMBA(8)/USART3_CK(7)/TIM1_BKIN(7)/CAN2_RX/ETH_MII_TXD0/ETH_RMII_TXD0-J83452PB13I/OFTPB13SPI2_SCK(8)/I2S2_CK(8)/USART3_CTS(7)/TIM1_CH1N/CAN2_TX/ETH_MII_TXD1/ETH_RMII_TXD1-H83553PB14I/OFTPB14SPI2_MISO(8)/TIM1_CH2N/USART3_RTS(7)-G83654PB15I/OFTPB15SPI2_MOSI(8)/I2S2_SD(8)/TIM1_CH3N(7)-K9-55PD8I/OFTPD8-USART3_TX/ETH_MII_RX_DV/ETH_RMII_CRS_DVTable5.
Pindefinitions(continued)PinsPinnameType(1)I/OLevel(2)Mainfunction(3)(afterreset)Alternatefunctions(4)BGA100LQFP64LQFP100DefaultRemapPinoutsandpindescriptionSTM32F105xx,STM32F107xx30/108DocID15274Rev10J9-56PD9I/OFTPD9-USART3_RX/ETH_MII_RXD0/ETH_RMII_RXD0H9-57PD10I/OFTPD10-USART3_CK/ETH_MII_RXD1/ETH_RMII_RXD1G9-58PD11I/OFTPD11-USART3_CTS/ETH_MII_RXD2K10-59PD12I/OFTPD12-TIM4_CH1/USART3_RTS/ETH_MII_RXD3J10-60PD13I/OFTPD13-TIM4_CH2H10-61PD14I/OFTPD14-TIM4_CH3G10-62PD15I/OFTPD15-TIM4_CH4F103763PC6I/OFTPC6I2S2_MCK/TIM3_CH1E103864PC7I/OFTPC7I2S3_MCKTIM3_CH2F93965PC8I/OFTPC8-TIM3_CH3E94066PC9I/OFTPC9-TIM3_CH4D94167PA8I/OFTPA8USART1_CK/OTG_FS_SOF/TIM1_CH1(8)/MCO-C94268PA9I/OFTPA9USART1_TX(7)/TIM1_CH2(7)/OTG_FS_VBUS-D104369PA10I/OFTPA10USART1_RX(7)/TIM1_CH3(7)/OTG_FS_ID-C104470PA11I/OFTPA11USART1_CTS/CAN1_RX/TIM1_CH4(7)/OTG_FS_DM-B104571PA12I/OFTPA12USART1_RTS/OTG_FS_DP/CAN1_TX(7)/TIM1_ETR(7)-A104672PA13I/OFTJTMS-SWDIO-PA13F8-73Notconnected-E64774VSS_2S-VSS_2--F64875VDD_2S-VDD_2--A94976PA14I/OFTJTCK-SWCLK-PA14Table5.
Pindefinitions(continued)PinsPinnameType(1)I/OLevel(2)Mainfunction(3)(afterreset)Alternatefunctions(4)BGA100LQFP64LQFP100DefaultRemapDocID15274Rev1031/108STM32F105xx,STM32F107xxPinoutsandpindescription107A85077PA15I/OFTJTDISPI3_NSS/I2S3_WSTIM2_CH1_ETR/PA15SPI1_NSSB95178PC10I/OFTPC10UART4_TXUSART3_TX/SPI3_SCK/I2S3_CKB85279PC11I/OFTPC11UART4_RXUSART3_RX/SPI3_MISOC85380PC12I/OFTPC12UART5_TXUSART3_CK/SPI3_MOSI/I2S3_SDD8-81PD0I/OFTPD0-OSC_IN(9)/CAN1_RXE8-82PD1I/OFTPD1-OSC_OUT(9)/CAN1_TXB75483PD2I/OFTPD2TIM3_ETR/UART5_RXC7-84PD3I/OFTPD3-USART2_CTSD7-85PD4I/OFTPD4-USART2_RTSB6-86PD5I/OFTPD5-USART2_TXC6-87PD6I/OFTPD6-USART2_RXD6-88PD7I/OFTPD7-USART2_CKA75589PB3I/OFTJTDOSPI3_SCK/I2S3_CKPB3/TRACESWO/TIM2_CH2/SPI1_SCKA65690PB4I/OFTNJTRSTSPI3_MISOPB4/TIM3_CH1/SPI1_MISOC55791PB5I/O-PB5I2C1_SMBA/SPI3_MOSI/ETH_MII_PPS_OUT/I2S3_SDETH_RMII_PPS_OUTTIM3_CH2/SPI1_MOSI/CAN2_RXB55892PB6I/OFTPB6I2C1_SCL(7)/TIM4_CH1(7)USART1_TX/CAN2_TXA55993PB7I/OFTPB7I2C1_SDA(7)/TIM4_CH2(7)USART1_RXD56094BOOT0I-BOOT0--B46195PB8I/OFTPB8TIM4_CH3(7)/ETH_MII_TXD3I2C1_SCL/CAN1_RXA46296PB9I/OFTPB9TIM4_CH4(7)I2C1_SDA/CAN1_TXD4-97PE0I/OFTPE0TIM4_ETR-C4-98PE1I/OFTPE1--E56399VSS_3S-VSS_3--F564100VDD_3S-VDD_3--Table5.
Pindefinitions(continued)PinsPinnameType(1)I/OLevel(2)Mainfunction(3)(afterreset)Alternatefunctions(4)BGA100LQFP64LQFP100DefaultRemapPinoutsandpindescriptionSTM32F105xx,STM32F107xx32/108DocID15274Rev101.
I=input,O=output,S=supply,HiZ=highimpedance.
2.
FT=5Vtolerant.
AllI/OsareVDDcapable.
3.
Functionavailabilitydependsonthechosendevice.
4.
IfseveralperipheralssharethesameI/Opin,toavoidconflictbetweenthesealternatefunctionsonlyoneperipheralshouldbeenabledatatimethroughtheperipheralclockenablebit(inthecorrespondingRCCperipheralclockenableregister).
5.
PC13,PC14andPC15aresuppliedthroughthepowerswitch,andsotheiruseinoutputmodeislimited:theycanbeusedonlyinoutput2MHzmodewithamaximumloadof30pFandonlyonepincanbeputinoutputmodeatatime.
6.
Mainfunctionafterthefirstbackupdomainpower-up.
Lateron,itdependsonthecontentsoftheBackupregistersevenafterreset(becausetheseregistersarenotresetbythemainreset).
FordetailsonhowtomanagetheseIOs,refertotheBatterybackupdomainandBKPregisterdescriptionsectionsintheSTM32F10xxxreferencemanual,availablefromtheSTMicroelectronicswebsite:www.
st.
com.
7.
Thisalternatefunctioncanberemappedbysoftwaretosomeotherportpins(ifavailableontheusedpackage).
Formoredetails,refertotheAlternatefunctionI/OanddebugconfigurationsectionintheSTM32F10xxxreferencemanual,availablefromtheSTMicroelectronicswebsite:www.
st.
com.
8.
SPI2/I2S2andI2C2arenotavailablewhentheEthernetisbeingused.
9.
FortheLQFP64package,thepinsnumber5and6areconfiguredasOSC_IN/OSC_OUTafterreset,howeverthefunctionalityofPD0andPD1canberemappedbysoftwareonthesepins.
FortheLQFP100andBGA100packages,PD0andPD1areavailablebydefault,sothereisnoneedforremapping.
Formoredetails,refertoAlternatefunctionI/OanddebugconfigurationsectionintheSTM32F10xxxreferencemanual.
DocID15274Rev1033/108STM32F105xx,STM32F107xxMemorymapping1074MemorymappingThememorymapisshowninFigure5.
Figure5.
Memorymap512-Mbyteblock7Cortex-M3'sinternalperipherals512-Mbyteblock6Notused512-Mbyteblock5Notused512-Mbyteblock4Notused512-Mbyteblock3Notused512-Mbyteblock2Peripherals512-Mbyteblock1SRAM0x000000000x1FFFFFFF0x200000000x3FFFFFFF0x400000000x5FFFFFFF0x600000000x7FFFFFFF0x800000000xAFFFFFFF0xB00000000xBFFFFFFF0xC00000000xDFFFFFFF0xE00000000xFFFFFFFF512-Mbyteblock0CodeFlash0x080400000x1FFFAFFF0x1FFFB000-0x1FFFF7FF0x080000000x0803FFFF0x000400000x07FFFFFF0x000000000x0003FFFFSystemmemoryReservedReservedAliasedtoFlashorsystemmemorydependingonBOOTpinsSRAM(aliasedbybit-banding)Reserved0x200000000x2000FFFF0x200100000x3FFFFFFFRTCWWDG0x40002800-0x40002BFFIWDGReservedSPI2/I2S2SPI3/I2S3Reserved0x40002C00-0x40002FFF0x40003000-0x400033FF0x40003400-0x400037FF0x40003800-0x40003BFF0x40003C00-0x40003FFF0x40004000-0x400043FFUSART20x40004400-0x400047FFUSART30x40004800-0x40004BFFUART40x40004C00-0x40004FFFUART50x40005000-0x400053FFI2C10x40005400-0x400057FFI2C20x40005800-0x40005BFFReserved0x40005C00-0x400063FF0x40006400-0x400067FFbxCAN1bxCAN20x40006800-0x40006BFFBKP0x40006C00-0x40006FFFPWR0x40007000-0x400073FFDAC0x40007400-0x400077FFAFIO0x40010000-0x40013FFFEXTI0x40010400-0x400107FFPortA0x40010800-0x40010BFFPortB0x40010C00-0x40010FFFPortC0x40011000-0x400113FFPortD0x40011400-0x400117FFPortE0x40011800-0x40011BFFReserved0x40011C00-0x400123FFADC10x40012400-0x400127FFADC20x40012800-0x40012BFFTIM10x40012C00-0x40012FFFSPI10x40013000-0x400133FFReserved0x40013400-0x400137FFUSART10x40013800-0x40013BFFReserved0x40013C00-0x4001FFFFDMA20x40020400-0x400207FFReserved0x40021400-0x40021FFFFlashinterface0x40022000-0x400223FFReserved0x40022400-0x40022FFFCRC0x40023000-0x400233FFReserved0x40023400-0x40027FFFEthernet0x40028000-0x40029FFFReserved0x40030000-0x4FFFFFFFUSBOTGFS0x50000000-0x5003FFFFReserved0x50000400-0x5FFFFFFFai15412b0x40020800-0x40020FFF0x40021000-0x400213FFReservedRCCDMA10x40020000-0x400203FFReserved0x40007800-0x4000FFFFAPB2AHB0x40001800-0x400027FF0x40000800-0x40000BFF0x40000C00-0x40000FFF0x40001000-0x400013FF0x40001400-0x400017FF0x40000000-0x400003FF0x40000400-0x400007FFReservedTIM7TIM6TIM5TIM4TIM3TIM2APB1Optionbytes0x1FFFF800-0x1FFFFFFFElectricalcharacteristicsSTM32F105xx,STM32F107xx34/108DocID15274Rev105Electricalcharacteristics5.
1ParameterconditionsUnlessotherwisespecified,allvoltagesarereferencedtoVSS.
5.
1.
1MinimumandmaximumvaluesUnlessotherwisespecifiedtheminimumandmaximumvaluesareguaranteedintheworstconditionsofambienttemperature,supplyvoltageandfrequenciesbytestsinproductionon100%ofthedeviceswithanambienttemperatureatTA=25°CandTA=TAmax(givenbytheselectedtemperaturerange).
Databasedoncharacterizationresults,designsimulationand/ortechnologycharacteristicsareindicatedinthetablefootnotesandarenottestedinproduction.
Basedoncharacterization,theminimumandmaximumvaluesrefertosampletestsandrepresentthemeanvalueplusorminusthreetimesthestandarddeviation(mean±3Σ).
5.
1.
2TypicalvaluesUnlessotherwisespecified,typicaldataarebasedonTA=25°C,VDD=3.
3V(forthe2V≤VDD≤3.
6Vvoltagerange).
Theyaregivenonlyasdesignguidelinesandarenottested.
TypicalADCaccuracyvaluesaredeterminedbycharacterizationofabatchofsamplesfromastandarddiffusionlotoverthefulltemperaturerange,where95%ofthedeviceshaveanerrorlessthanorequaltothevalueindicated(mean±2Σ).
5.
1.
3TypicalcurvesUnlessotherwisespecified,alltypicalcurvesaregivenonlyasdesignguidelinesandarenottested.
5.
1.
4LoadingcapacitorTheloadingconditionsusedforpinparametermeasurementareshowninFigure6.
5.
1.
5PininputvoltageTheinputvoltagemeasurementonapinofthedeviceisdescribedinFigure7.
Figure6.
PinloadingconditionsFigure7.
Pininputvoltage06Y9670)[[[SLQ&S)06Y9670)[[[SLQ9,1DocID15274Rev1035/108STM32F105xx,STM32F107xxElectricalcharacteristics1075.
1.
6PowersupplyschemeFigure8.
PowersupplyschemeCaution:InFigure8,the4.
7FcapacitormustbeconnectedtoVDD3.
5.
1.
7CurrentconsumptionmeasurementFigure9.
CurrentconsumptionmeasurementschemeDLG9''$QDORJ5&V3//3RZHUVZLWFK*3,2V287,1.
HUQHOORJLF&38'LJLWDO0HPRULHV%DFNXSFLUFXLWU\26&.
57&%DFNXSUHJLVWHUV:DNHXSORJLFQ))95HJXODWRU9''$95()$'&'$&/HYHOVKLIWHU,2/RJLF9''Q))95()Q))95()966$9669''9%$7DL9%$79''9''$,''B9%$7,''ElectricalcharacteristicsSTM32F105xx,STM32F107xx36/108DocID15274Rev105.
2AbsolutemaximumratingsStressesabovetheabsolutemaximumratingslistedinTable6:Voltagecharacteristics,Table7:Currentcharacteristics,andTable8:Thermalcharacteristicsmaycausepermanentdamagetothedevice.
Thesearestressratingsonlyandfunctionaloperationofthedeviceattheseconditionsisnotimplied.
Exposuretomaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
Table6.
VoltagecharacteristicsSymbolRatingsMinMaxUnitVDD–VSSExternalmainsupplyvoltage(includingVDDAandVDD)(1)1.
Allmainpower(VDD,VDDA)andground(VSS,VSSA)pinsmustalwaysbeconnectedtotheexternalpowersupply,inthepermittedrange.
–0.
34.
0VVIN(2)2.
VINmaximummustalwaysberespected.
RefertoTable7:Currentcharacteristicsforthemaximumallowedinjectedcurrentvalues.
InputvoltageonfivevolttolerantpinVSS0.
3VDD+4.
0InputvoltageonanyotherpinVSS0.
34.
0|ΔVDDx|VariationsbetweendifferentVDDpowerpins-50mV|VSSXVSS|Variationsbetweenallthedifferentgroundpins-50VESD(HBM)Electrostaticdischargevoltage(humanbodymodel)seeSection5.
3.
11:Absolutemaximumratings(electricalsensitivity)-Table7.
CurrentcharacteristicsSymbolRatingsMax.
UnitIVDDTotalcurrentintoVDD/VDDApowerlines(source)(1)1.
Allmainpower(VDD,VDDA)andground(VSS,VSSA)pinsmustalwaysbeconnectedtotheexternalpowersupply,inthepermittedrange.
150mAIVSSTotalcurrentoutofVSSgroundlines(sink)(1)150IIOOutputcurrentsunkbyanyI/Oandcontrolpin25OutputcurrentsourcebyanyI/Osandcontrolpin25IINJ(PIN)(2)2.
Negativeinjectiondisturbstheanalogperformanceofthedevice.
SeeNote:onpage76.
Injectedcurrentonfivevolttolerantpins(3)3.
PositiveinjectionisnotpossibleontheseI/Os.
AnegativeinjectionisinducedbyVINVDDwhileanegativeinjectionisinducedbyVIN8MHz.
72MHz6868.
4mA48MHz4949.
236MHz38.
738.
924MHz27.
327.
916MHz20.
220.
58MHz10.
210.
8Externalclock(2),allperipheralsdisabled72MHz32.
732.
948MHz2525.
236MHz20.
320.
624MHz14.
815.
116MHz11.
211.
78MHz6.
67.
2Table14.
MaximumcurrentconsumptioninRunmode,codewithdataprocessingrunningfromRAMSymbolParameterConditionsfHCLKMax(1)1.
Basedoncharacterization,testedinproductionatVDDmax,fHCLKmax.
.
UnitTA=85°CTA=105°CIDDSupplycurrentinRunmodeExternalclock(2),allperipheralsenabled2.
Externalclockis8MHzandPLLisonwhenfHCLK>8MHz.
72MHz65.
566mA48MHz45.
44636MHz35.
536.
124MHz25.
225.
616MHz1818.
58MHz10.
511Externalclock(2),allperipheralsdisabled72MHz31.
431.
948MHz27.
828.
236MHz17.
618.
324MHz13.
113.
816MHz10.
210.
98MHz6.
17.
8DocID15274Rev1041/108STM32F105xx,STM32F107xxElectricalcharacteristics107Table15.
MaximumcurrentconsumptioninSleepmode,coderunningfromFlashorRAMSymbolParameterConditionsfHCLKMax(1)UnitTA=85°CTA=105°CIDDSupplycurrentinSleepmodeExternalclock(2),allperipheralsenabled72MHz48.
449mA48MHz33.
934.
436MHz26.
727.
224MHz19.
319.
816MHz14.
214.
88MHz8.
79.
1Externalclock(2),allperipheralsdisabled72MHz10.
110.
648MHz8.
38.
7536MHz7.
5824MHz6.
67.
116MHz66.
58MHz2.
531.
Basedoncharacterization,testedinproductionatVDDmaxandfHCLKmaxwithperipheralsenabled.
2.
Externalclockis8MHzandPLLisonwhenfHCLK>8MHz.
Table16.
TypicalandmaximumcurrentconsumptionsinStopandStandbymodesSymbolParameterConditionsTyp(1)MaxUnitVDD/VBAT=2.
0VVDD/VBAT=2.
4VVDD/VBAT=3.
3VTA=85°CTA=105°CIDDSupplycurrentinStopmodeRegulatorinRunmode,low-speedandhigh-speedinternalRCoscillatorsandhigh-speedoscillatorOFF(noindependentwatchdog)-32336001300ARegulatorinLowPowermode,low-speedandhigh-speedinternalRCoscillatorsandhigh-speedoscillatorOFF(noindependentwatchdog)-25265901280SupplycurrentinStandbymodeLow-speedinternalRCoscillatorandindependentwatchdogON-33.
8--Low-speedinternalRCoscillatorON,independentwatchdogOFF-2.
83.
6--Low-speedinternalRCoscillatorandindependentwatchdogOFF,low-speedoscillatorandRTCOFF-1.
92.
15(2)6.
5(2)IDD_VBATBackupdomainsupplycurrentLow-speedoscillatorandRTCON1.
11.
21.
42.
1(2)2.
3(2)1.
TypicalvaluesaremeasuredatTA=25°C.
2.
Basedoncharacterization,nottestedinproduction.
ElectricalcharacteristicsSTM32F105xx,STM32F107xx42/108DocID15274Rev10Figure10.
TypicalcurrentconsumptiononVBATwithRTConvs.
temperatureatdifferentVBATvaluesFigure11.
TypicalcurrentconsumptioninStopmodewithregulatorinRunmodeversustemperatureatdifferentVDDvalues00.
511.
522.
5–40°C25°C70°C85°C105°CTemperature(°C)Consumption(A)1.
8V2V2.
4V3.
3V3.
6Vai173290.
00100.
00200.
00300.
00400.
00500.
00600.
00700.
00800.
00900.
00–40°C25°C85°C105°CTemperature(°C)Consumption(A)3.
6V3.
3V3V2.
7V2.
4Vai17122DocID15274Rev1043/108STM32F105xx,STM32F107xxElectricalcharacteristics107Figure12.
TypicalcurrentconsumptioninStopmodewithregulatorinLow-powermodeversustemperatureatdifferentVDDvaluesFigure13.
TypicalcurrentconsumptioninStandbymodeversustemperatureatdifferentVDDvaluesTypicalcurrentconsumptionTheMCUisplacedunderthefollowingconditions:AllI/OpinsareininputmodewithastaticvalueatVDDorVSS(noload).
Allperipheralsaredisabledexceptifitisexplicitlymentioned.
TheFlashaccesstimeisadjustedtofHCLKfrequency(0waitstatefrom0to24MHz,1waitstatefrom24to48MHzand2waitstatesabove).
AmbienttemperatureandVDDsupplyvoltageconditionssummarizedinTable9.
PrefetchisON(Reminder:thisbitmustbesetbeforeclocksettingandbusprescaling)WhentheperipheralsareenabledfPCLK1=fHCLK/4,fPCLK2=fHCLK/2,fADCCLK=fPCLK2/40.
00100.
00200.
00300.
00400.
00500.
00600.
00700.
00800.
00900.
00–40°C25°C85°C105°CTemperature(°C)Consumption(A)3.
6V3.
3V3V2.
7V2.
4Vai171230.
000.
501.
001.
502.
002.
503.
003.
504.
004.
50–40°C25°C85°C105°CTemperature(°C)Consumption(A)3.
6V3.
3V3V2.
7V2.
4Vai17124ElectricalcharacteristicsSTM32F105xx,STM32F107xx44/108DocID15274Rev10Table17.
TypicalcurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlashSymbolParameterConditionsfHCLKTyp(1)1.
TypicalvaluesaremeasuresatTA=25°C,VDD=3.
3V.
UnitAllperipheralsenabled(2)2.
Addanadditionalpowerconsumptionof0.
8mAperADCfortheanalogpart.
Inapplications,thisconsumptionoccursonlywhiletheADCison(ADONbitissetintheADC_CR2register).
AllperipheralsdisabledIDDSupplycurrentinRunmodeExternalclock(3)3.
Externalclockis8MHzandPLLisonwhenfHCLK>8MHz.
72MHz47.
328.
3mA48MHz3219.
636MHz24.
615.
424MHz16.
810.
616MHz11.
87.
48MHz5.
93.
74MHz3.
72.
92MHz2.
521MHz1.
81.
53500kHz1.
51.
3125kHz1.
31.
2RunningonhighspeedinternalRC(HSI),AHBprescalerusedtoreducethefrequency36MHz23.
914.
8mA24MHz16.
19.
716MHz11.
16.
78MHz5.
63.
84MHz3.
12.
12MHz1.
81.
31MHz1.
160.
9500kHz0.
80.
67125kHz0.
60.
5DocID15274Rev1045/108STM32F105xx,STM32F107xxElectricalcharacteristics107On-chipperipheralcurrentconsumptionThecurrentconsumptionoftheon-chipperipheralsisgiveninTable19.
TheMCUisplacedunderthefollowingconditions:allI/OpinsareininputmodewithastaticvalueatVDDorVSS(noload)allperipheralsaredisabledunlessotherwisementionedthegivenvalueiscalculatedbymeasuringthecurrentconsumption–withallperipheralsclockedoff–withoneperipheralclockedon(withonlytheclockapplied)ambientoperatingtemperatureandVDDsupplyvoltageconditionssummarizedinTable6Table18.
TypicalcurrentconsumptioninSleepmode,coderunningfromFlashorRAMSymbolParameterConditionsfHCLKTyp(1)1.
TypicalvaluesaremeasuresatTA=25°C,VDD=3.
3V.
UnitAllperipheralsenabled(2)2.
Addanadditionalpowerconsumptionof0.
8mAperADCfortheanalogpart.
Inapplications,thisconsumptionoccursonlywhiletheADCison(ADONbitissetintheADC_CR2register).
AllperipheralsdisabledIDDSupplycurrentinSleepmodeExternalclock(3)3.
Externalclockis8MHzandPLLisonwhenfHCLK>8MHz.
72MHz28.
26mA48MHz194.
236MHz14.
73.
424MHz10.
12.
516MHz6.
728MHz3.
21.
34MHz2.
31.
22MHz1.
71.
161MHz1.
51.
1500kHz1.
31.
05125kHz1.
21.
05RunningonhighspeedinternalRC(HSI),AHBprescalerusedtoreducethefrequency36MHz13.
72.
624MHz9.
31.
816MHz6.
31.
38MHz2.
70.
64MHz1.
60.
52MHz10.
461MHz0.
80.
44500kHz0.
60.
43125kHz0.
50.
42ElectricalcharacteristicsSTM32F105xx,STM32F107xx46/108DocID15274Rev10Table19.
PeripheralcurrentconsumptionPeripheralTypicalconsumptionat25°CUnitAHB(upto72MHz)DMA114.
03A/MHzDMA29.
31OTG_fs111.
11ETH-MAC56.
25CRC1.
11BusMatrix(1)15.
97APB1(upto36MHz)APB1-Bridge9.
72A/MHzTIM233.
61TIM333.
06TIM432.
50TIM531.
94TIM66.
11TIM76.
11SPI2/I2S2(2)7.
50SPI3/I2S3(2)7.
50USART210.
83USART311.
11UART410.
83UART510.
56I2C111.
39I2C211.
11CAN119.
44CAN218.
33DAC(3)8.
61WWDG3.
33PWR2.
22BKP0.
83IWDG3.
89DocID15274Rev1047/108STM32F105xx,STM32F107xxElectricalcharacteristics1075.
3.
6ExternalclocksourcecharacteristicsHigh-speedexternaluserclockgeneratedfromanexternalsourceThecharacteristicsgiveninTable20resultfromtestsperformedusinganhigh-speedexternalclocksource,andunderambienttemperatureandsupplyvoltageconditionssummarizedinTable9.
APB2(upto72MHz)APB2-Bridge3.
47A/MHzGPIOA6.
39GPIOB6.
39GPIOC6.
11GPIOD6.
39GPIOE6.
11SPI13.
61USART112.
08TIM123.
47ADC1(4)18.
211.
TheBusMatrixisautomaticallyactivewhenatleastonemasterisON.
(CPU,ETH-MAC,DMA1orDMA2).
2.
WhenI2Sisenabledwehaveaconsumptionaddequalto0,02mA.
3.
WhenDAC_OUT1orDAC_OUT2isenabledwehaveaconsumptionaddequalto0,3mA.
4.
SpecificconditionsformeasuringADCcurrentconsumption:fHCLK=56MHz,fAPB1=fHCLK/2,fAPB2=fHCLK,fADCCLK=fAPB2/4.
WhenADONbitintheADC_CR2registerissetto1,acurrentconsumptionofanalogpartequalto0.
6mAmustbeadded.
Table19.
Peripheralcurrentconsumption(continued)PeripheralTypicalconsumptionat25°CUnitTable20.
High-speedexternaluserclockcharacteristicsSymbolParameterConditionsMinTypMaxUnitfHSE_extExternaluserclocksourcefrequency(1)-1850MHzVHSEHOSC_INinputpinhighlevelvoltage0.
7VDD-VDDVVHSELOSC_INinputpinlowlevelvoltageVSS-0.
3VDDtw(HSE)tw(HSE)OSC_INhighorlowtime(1)1.
Guaranteedbydesign,nottestedinproduction.
5--nstr(HSE)tf(HSE)OSC_INriseorfalltime(1)--20Cin(HSE)OSC_INinputcapacitance(1)--5-pFDuCy(HSE)Dutycycle-45-55%ILOSC_INInputleakagecurrentVSS≤VIN≤VDD--±1AElectricalcharacteristicsSTM32F105xx,STM32F107xx48/108DocID15274Rev10Low-speedexternaluserclockgeneratedfromanexternalsourceThecharacteristicsgiveninTable21resultfromtestsperformedusinganlow-speedexternalclocksource,andunderambienttemperatureandsupplyvoltageconditionssummarizedinTable9.
Figure14.
High-speedexternalclocksourceACtimingdiagramTable21.
Low-speedexternaluserclockcharacteristicsSymbolParameterConditionsMinTypMaxUnitfLSE_extUserExternalclocksourcefrequency(1)1.
Guaranteedbydesign,nottestedinproduction.
-32.
7681000kHzVLSEHOSC32_INinputpinhighlevelvoltage0.
7VDD-VDDVVLSELOSC32_INinputpinlowlevelvoltageVSS-0.
3VDDtw(LSE)tw(LSE)OSC32_INhighorlowtime(1)450--nstr(LSE)tf(LSE)OSC32_INriseorfalltime(1)--50Cin(LSE)OSC32_INinputcapacitance(1)--5pFDuCy(LSE)Dutycycle-30-70%ILOSC32_INInputleakagecurrentVSS≤VIN≤VDD--±1ADLF26&B,1([WHUQDOFORFNVRXUFH670)[[[9+6(+W:+6(,/7+6(WWU+6(W:+6(I+6(BH[W9+6(/DocID15274Rev1049/108STM32F105xx,STM32F107xxElectricalcharacteristics107Figure15.
Low-speedexternalclocksourceACtimingdiagramHigh-speedexternalclockgeneratedfromacrystal/ceramicresonatorThehigh-speedexternal(HSE)clockcanbesuppliedwitha3to25MHzcrystal/ceramicresonatoroscillator.
AlltheinformationgiveninthisparagrapharebasedoncharacterizationresultsobtainedwithtypicalexternalcomponentsspecifiedinTable22.
Intheapplication,theresonatorandtheloadcapacitorshavetobeplacedascloseaspossibletotheoscillatorpinsinordertominimizeoutputdistortionandstartupstabilizationtime.
Refertothecrystalresonatormanufacturerformoredetailsontheresonatorcharacteristics(frequency,package,accuracy).
Table22.
HSE3-25MHzoscillatorcharacteristics(1)(2)1.
Resonatorcharacteristicsgivenbythecrystal/ceramicresonatormanufacturer.
2.
Basedoncharacterization,nottestedinproduction.
SymbolParameterConditionsMinTypMaxUnitfOSC_INOscillatorfrequency-325MHzRFFeedbackresistor--200-kΩCRecommendedloadcapacitanceversusequivalentserialresistanceofthecrystal(RS)(3)3.
TherelativelylowvalueoftheRFresistoroffersagoodprotectionagainstissuesresultingfromuseinahumidenvironment,duetotheinducedleakageandthebiasconditionchange.
However,itisrecommendedtotakethispointintoaccountiftheMCUisusedintoughhumidityconditions.
RS=30Ω-30-pFi2HSEdrivingcurrentVDD=3.
3V,VIN=VSSwith30pFload--1mAgmOscillatortransconductanceStartup25--mA/VtSU(HSE(4)4.
tSU(HSE)isthestartuptimemeasuredfromthemomentitisenabled(bysoftware)toastabilized8MHzoscillationisreached.
ThisvalueismeasuredforastandardcrystalresonatoranditcanvarysignificantlywiththecrystalmanufacturerStartuptimeVDDisstabilized-2-msai14140cOSC32_INExternalSTM32F10xxxclocksourceVLSEHtf(LSE)tW(LSE)IL90%10%TLSEttr(LSE)tW(LSE)fLSE_extVLSELElectricalcharacteristicsSTM32F105xx,STM32F107xx50/108DocID15274Rev10ForCL1andCL2,itisrecommendedtousehigh-qualityexternalceramiccapacitorsinthe5pFto25pFrange(typ.
),designedforhigh-frequencyapplications,andselectedtomatchtherequirementsofthecrystalorresonator(seeFigure16).
CL1andCL2areusuallythesamesize.
ThecrystalmanufacturertypicallyspecifiesaloadcapacitancewhichistheseriescombinationofCL1andCL2.
PCBandMCUpincapacitancemustbeincluded(10pFcanbeusedasaroughestimateofthecombinedpinandboardcapacitance)whensizingCL1andCL2.
RefertotheapplicationnoteAN2867"OscillatordesignguideforSTmicrocontrollers"availablefromtheSTwebsitewww.
st.
com.
Figure16.
Typicalapplicationwithan8MHzcrystal1.
REXTvaluedependsonthecrystalcharacteristics.
Low-speedexternalclockgeneratedfromacrystal/ceramicresonatorThelow-speedexternal(LSE)clockcanbesuppliedwitha32.
768kHzcrystal/ceramicresonatoroscillator.
AlltheinformationgiveninthisparagrapharebasedoncharacterizationresultsobtainedwithtypicalexternalcomponentsspecifiedinTable23.
Intheapplication,theresonatorandtheloadcapacitorshavetobeplacedascloseaspossibletotheoscillatorpinsinordertominimizeoutputdistortionandstartupstabilizationtime.
Refertothecrystalresonatormanufacturerformoredetailsontheresonatorcharacteristics(frequency,package,accuracy).
DLE26&B28726&B,1I+6(&/5)670)[[[0+]UHVRQDWRU5HVRQDWRUZLWKLQWHJUDWHGFDSDFLWRUV%LDVFRQWUROOHGJDLQ5(;7&/Table23.
LSEoscillatorcharacteristics(fLSE=32.
768kHz)(1)SymbolParameterConditionsMinTypMaxUnitRFFeedbackresistor--5-MΩC(2)Recommendedloadcapacitanceversusequivalentserialresistanceofthecrystal(RS)(3)RS=30kΩ--15pFI2LSEdrivingcurrentVDD=3.
3V,VIN=VSS--1.
4AgmOscillatorTransconductance-5--A/VDocID15274Rev1051/108STM32F105xx,STM32F107xxElectricalcharacteristics107Note:ForCL1andCL2itisrecommendedtousehigh-qualityexternalceramiccapacitorsinthe5pFto15pFrangeselectedtomatchtherequirementsofthecrystalorresonator(seeFigure17).
CL1andCL2,areusuallythesamesize.
ThecrystalmanufacturertypicallyspecifiesaloadcapacitancewhichistheseriescombinationofCL1andCL2.
LoadcapacitanceCLhasthefollowingformula:CL=CL1xCL2/(CL1+CL2)+CstraywhereCstrayisthepincapacitanceandboardortracePCB-relatedcapacitance.
Typically,itisbetween2pFand7pF.
Caution:ToavoidexceedingthemaximumvalueofCL1andCL2(15pF)itisstronglyrecommendedtousearesonatorwithaloadcapacitanceCL≤7pF.
Neverusearesonatorwithaloadcapacitanceof12.
5pF.
Example:ifyouchoosearesonatorwithaloadcapacitanceofCL=6pF,andCstray=2pF,thenCL1=CL2=8pF.
Figure17.
Typicalapplicationwitha32.
768kHzcrystaltSU(LSE)(4)StartuptimeVDDisstabilizedTA=50°C-1.
5-sTA=25°C-2.
5-TA=10°C-4-TA=0°C-6-TA=-10°C-10-TA=-20°C-17-TA=-30°C-32-TA=-40°C-60-1.
Basedoncharacterization,nottestedinproduction.
2.
Refertothenoteandcautionparagraphsbelowthetable,andtotheapplicationnoteAN2867"OscillatordesignguideforSTmicrocontrollers".
3.
TheoscillatorselectioncanbeoptimizedintermsofsupplycurrentusinganhighqualityresonatorwithsmallRSvalueforexampleMSIV-TIN32.
768kHz.
Refertocrystalmanufacturerformoredetails4.
tSU(LSE)isthestartuptimemeasuredfromthemomentitisenabled(bysoftware)toastabilized32.
768kHzoscillationisreached.
ThisvalueismeasuredforastandardcrystalanditcanvarysignificantlywiththecrystalmanufacturerTable23.
LSEoscillatorcharacteristics(fLSE=32.
768kHz)(1)(continued)SymbolParameterConditionsMinTypMaxUnitDLE26&B28726&B,1I/6(&/5)670)[[[.
+]UHVRQDWRU5HVRQDWRUZLWKLQWHJUDWHGFDSDFLWRUV%LDVFRQWUROOHGJDLQ&/ElectricalcharacteristicsSTM32F105xx,STM32F107xx52/108DocID15274Rev105.
3.
7InternalclocksourcecharacteristicsTheparametersgiveninTable24arederivedfromtestsperformedunderambienttemperatureandVDDsupplyvoltageconditionssummarizedinTable9.
High-speedinternal(HSI)RCoscillatorLow-speedinternal(LSI)RCoscillatorWakeuptimefromlow-powermodeThewakeuptimesgiveninTable26ismeasuredonawakeupphasewitha8-MHzHSIRCoscillator.
Theclocksourceusedtowakeupthedevicedependsfromthecurrentoperatingmode:StoporStandbymode:theclocksourceistheRCoscillatorSleepmode:theclocksourceistheclockthatwassetbeforeenteringSleepmode.
Table24.
HSIoscillatorcharacteristics(1)1.
VDD=3.
3V,TA=–40to105°Cunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitfHSIFrequency--8MHzDuCy(HSI)Dutycycle-45-55%ACCHSIAccuracyoftheHSIoscillatorUser-trimmedwiththeRCC_CRregister(2)2.
RefertoapplicationnoteAN2868"STM32F10xxxinternalRCoscillator(HSI)calibration"availablefromtheSTwebsitewww.
st.
com.
--1(3)3.
Guaranteedbydesign,nottestedinproduction.
%Factory-calibrated(4)4.
Basedoncharacterization,nottestedinproduction.
TA=–40to105°C–2-2.
5%TA=–10to85°C–1.
5-2.
2%TA=0to70°C–1.
3-2%TA=25°C–1.
1-1.
8%tsu(HSI)(4)HSIoscillatorstartuptime-1-2sIDD(HSI)(4)HSIoscillatorpowerconsumption--80100ATable25.
LSIoscillatorcharacteristics(1)1.
VDD=3V,TA=–40to105°Cunlessotherwisespecified.
SymbolParameterMinTypMaxUnitfLSI(2)2.
Basedoncharacterization,nottestedinproduction.
Frequency304060kHztsu(LSI)(3)3.
Guaranteedbydesign,nottestedinproduction.
LSIoscillatorstartuptime--85sIDD(LSI)(3)LSIoscillatorpowerconsumption-0.
651.
2ADocID15274Rev1053/108STM32F105xx,STM32F107xxElectricalcharacteristics107AlltimingsarederivedfromtestsperformedunderambienttemperatureandVDDsupplyvoltageconditionssummarizedinTable9.
5.
3.
8PLL,PLL2andPLL3characteristicsTheparametersgiveninTable27andTable28arederivedfromtestsperformedundertemperatureandVDDsupplyvoltageconditionssummarizedinTable9.
Table26.
Low-powermodewakeuptimingsSymbolParameterTypUnittWUSLEEP(1)1.
Thewakeuptimesaremeasuredfromthewakeupeventtothepointinwhichtheuserapplicationcodereadsthefirstinstruction.
WakeupfromSleepmode1.
8stWUSTOP(1)WakeupfromStopmode(regulatorinrunmode)3.
6sWakeupfromStopmode(regulatorinlowpowermode)5.
4tWUSTDBY(1)WakeupfromStandbymode50sTable27.
PLLcharacteristicsSymbolParameterMin(1)1.
Basedoncharacterization,nottestedinproduction.
Max(1)UnitfPLL_INPLLinputclock(2)2.
TakecareofusingtheappropriatemultiplierfactorssoastohavePLLinputclockvaluescompatiblewiththerangedefinedbyfPLL_OUT.
312MHzPulsewidthathighlevel30-nsfPLL_OUTPLLmultiplieroutputclock1872MHzfVCO_OUTPLLVCOoutput36144MHztLOCKPLLlocktime-350sJitterCycle-to-cyclejitter-300psTable28.
PLL2andPLL3characteristicsSymbolParameterMin(1)1.
Basedoncharacterization,nottestedinproduction.
Max(1)UnitfPLL_INPLLinputclock(2)2.
TakecareofusingtheappropriatemultiplierfactorssoastohavePLLinputclockvaluescompatiblewiththerangedefinedbyfPLL_OUT.
35MHzPulsewidthathighlevel30-nsfPLL_OUTPLLmultiplieroutputclock4074MHzfVCO_OUTPLLVCOoutput80148MHztLOCKPLLlocktime-350sJitterCycle-to-cyclejitter-400psElectricalcharacteristicsSTM32F105xx,STM32F107xx54/108DocID15274Rev105.
3.
9MemorycharacteristicsFlashmemoryThecharacteristicsaregivenatTA=–40to105°Cunlessotherwisespecified.
5.
3.
10EMCcharacteristicsSusceptibilitytestsareperformedonasamplebasisduringdevicecharacterization.
FunctionalEMS(electromagneticsusceptibility)Whileasimpleapplicationisexecutedonthedevice(toggling2LEDsthroughI/Oports).
thedeviceisstressedbytwoelectromagneticeventsuntilafailureoccurs.
ThefailureisindicatedbytheLEDs:Electrostaticdischarge(ESD)(positiveandnegative)isappliedtoalldevicepinsuntilafunctionaldisturbanceoccurs.
ThistestiscompliantwiththeIEC61000-4-2standard.
FTB:Aburstoffasttransientvoltage(positiveandnegative)isappliedtoVDDandVSSthrougha100pFcapacitor,untilafunctionaldisturbanceoccurs.
ThistestiscompliantwiththeIEC61000-4-4standard.
Table29.
FlashmemorycharacteristicsSymbolParameterConditionsMin(1)TypMax(1)1.
Guaranteedbydesign,nottestedinproduction.
Unittprog16-bitprogrammingtimeTA=–40to+105°C4052.
570stERASEPage(1KB)erasetimeTA=–40to+105°C20-40mstMEMasserasetimeTA=–40to+105°C20-40msIDDSupplycurrentReadmodefHCLK=72MHzwith2waitstates,VDD=3.
3V--20mAWrite/ErasemodesfHCLK=72MHz,VDD=3.
3V--5mAPower-downmode/Halt,VDD=3.
0to3.
6V--50AVprogProgrammingvoltage-2-3.
6VTable30.
FlashmemoryenduranceanddataretentionSymbolParameterConditionsMin(1)TypMax(1)1.
Basedoncharacterization,nottestedinproduction.
UnitNENDEnduranceTA=–40to+85°C(6suffixversions)TA=–40to+105°C(7suffixversions)10--KcyclestRETDataretention1kcycle(2)atTA=85°C2.
Cyclingperformedoverthewholetemperaturerange.
30--Years1kcycle(2)atTA=105°C10--10kcycles(2)atTA=55°C20--DocID15274Rev1055/108STM32F105xx,STM32F107xxElectricalcharacteristics107Adeviceresetallowsnormaloperationstoberesumed.
ThetestresultsaregiveninTable31.
TheyarebasedontheEMSlevelsandclassesdefinedinapplicationnoteAN1709.
DesigninghardenedsoftwaretoavoidnoiseproblemsEMCcharacterizationandoptimizationareperformedatcomponentlevelwithatypicalapplicationenvironmentandsimplifiedMCUsoftware.
ItshouldbenotedthatgoodEMCperformanceishighlydependentontheuserapplicationandthesoftwareinparticular.
ThereforeitisrecommendedthattheuserappliesEMCsoftwareoptimizationandprequalificationtestsinrelationwiththeEMClevelrequestedforhisapplication.
SoftwarerecommendationsThesoftwareflowchartmustincludethemanagementofrunawayconditionssuchas:CorruptedprogramcounterUnexpectedresetCriticalDatacorruption(controlregisters.
.
.
)PrequalificationtrialsMostofthecommonfailures(unexpectedresetandprogramcountercorruption)canbereproducedbymanuallyforcingalowstateontheNRSTpinortheOscillatorpinsfor1second.
Tocompletethesetrials,ESDstresscanbeapplieddirectlyonthedevice,overtherangeofspecificationvalues.
Whenunexpectedbehaviorisdetected,thesoftwarecanbehardenedtopreventunrecoverableerrorsoccurring(seeapplicationnoteAN1015).
ElectromagneticInterference(EMI)Theelectromagneticfieldemittedbythedevicearemonitoredwhileasimpleapplicationisexecuted(toggling2LEDsthroughtheI/Oports).
ThisemissiontestiscompliantwithIEC61967-2standardwhichspecifiesthetestboardandthepinloading.
Table31.
EMScharacteristicsSymbolParameterConditionsLevel/ClassVFESDVoltagelimitstobeappliedonanyI/OpintoinduceafunctionaldisturbanceVDD=3.
3V,LQFP100,TA=+25°C,fHCLK=72MHz,conformstoIEC61000-4-22BVEFTBFasttransientvoltageburstlimitstobeappliedthrough100pFonVDDandVSSpinstoinduceafunctionaldisturbanceVDD=3.
3V,LQFP100,TA=+25°C,fHCLK=72MHz,conformstoIEC61000-4-44AElectricalcharacteristicsSTM32F105xx,STM32F107xx56/108DocID15274Rev105.
3.
11Absolutemaximumratings(electricalsensitivity)Basedonthreedifferenttests(ESD,LU)usingspecificmeasurementmethods,thedeviceisstressedinordertodetermineitsperformanceintermsofelectricalsensitivity.
Electrostaticdischarge(ESD)Electrostaticdischarges(apositivethenanegativepulseseparatedby1second)areappliedtothepinsofeachsampleaccordingtoeachpincombination.
Thesamplesizedependsonthenumberofsupplypinsinthedevice(3parts*(n+1)supplypins).
ThistestconformstotheJESD22-A114/C101standard.
Staticlatch-upTwocomplementarystatictestsarerequiredonsixpartstoassessthelatch-upperformance:AsupplyovervoltageisappliedtoeachpowersupplypinAcurrentinjectionisappliedtoeachinput,outputandconfigurableI/OpinThesetestsarecompliantwithEIA/JESD78AIClatch-upstandard.
5.
3.
12I/OcurrentinjectioncharacteristicsAsageneralrule,currentinjectiontotheI/Opins,duetoexternalvoltagebelowVSSoraboveVDD(forstandard,3V-capableI/Opins)shouldbeavoidedduringnormalproductTable32.
EMIcharacteristicsSymbolParameterConditionsMonitoredfrequencybandMaxvs.
[fHSE/fHCLK]Unit8/48MHz8/72MHzSEMIPeaklevelVDD=3.
3V,TA=25°C,LQFP100packagecompliantwithIEC61967-20.
1to30MHz99dBV30to130MHz2613130MHzto1GHz2531EMILevel44-Table33.
ESDabsolutemaximumratingsSymbolRatingsConditionsClassMaximumvalue(1)UnitVESD(HBM)Electrostaticdischargevoltage(humanbodymodel)TA=+25°CconformingtoJESD22-A11422000VVESD(CDM)Electrostaticdischargevoltage(chargedevicemodel)TA=+25°CconformingtoJESD22-C101II5001.
Basedoncharacterizationresults,nottestedinproduction.
Table34.
ElectricalsensitivitiesSymbolParameterConditionsClassLUStaticlatch-upclassTA=+105°CconformingtoJESD78AIIlevelADocID15274Rev1057/108STM32F105xx,STM32F107xxElectricalcharacteristics107operation.
However,inordertogiveanindicationoftherobustnessofthemicrocontrollerincaseswhenabnormalinjectionaccidentallyhappens,susceptibilitytestsareperformedonasamplebasisduringdevicecharacterization.
FunctionalsusceptibilitytoI/OcurrentinjectionWhileasimpleapplicationisexecutedonthedevice,thedeviceisstressedbyinjectingcurrentintotheI/Opinsprogrammedinfloatinginputmode.
WhilecurrentisinjectedintotheI/Opin,oneatatime,thedeviceischeckedforfunctionalfailures.
Thefailureisindicatedbyanoutofrangeparameter:ADCerroraboveacertainlimit(>5LSBTUE),outofspeccurrentinjectiononadjacentpinsorotherfunctionalfailure(forexamplereset,oscillatorfrequencydeviation).
ThetestresultsaregiveninTable355.
3.
13I/OportcharacteristicsGeneralinput/outputcharacteristicsUnlessotherwisespecified,theparametersgiveninTable36arederivedfromtestsperformedundertheconditionssummarizedinTable9.
AllI/OsareCMOSandTTLcompliant.
Table35.
I/OcurrentinjectionsusceptibilitySymbolDescriptionFunctionalsusceptibilityUnitNegativeinjectionPositiveinjectionIINJInjectedcurrentonOSC_IN32,OSC_OUT32,PA4,PA5,PC13-0+0mAInjectedcurrentonallFTpins-5+0Injectedcurrentonanyotherpin-5+5Table36.
I/OstaticcharacteristicsSymbolParameterConditionsMinTypMaxUnitVILStandardIOinputlowlevelvoltage-–0.
3-0.
28*(VDD-2V)+0.
8VVIOFT(1)inputlowlevelvoltage-–0.
3-0.
32*(VDD-2V)+0.
75VVVIHStandardIOinputhighlevelvoltage-0.
41*(VDD-2V)+1.
3V-VDD+0.
3VIOFT(1)inputhighlevelvoltageVDD>2V0.
42*(VDD-2V)+1V-5.
5VVDD≤2V5.
2VhysStandardIOSchmitttriggervoltagehysteresis(2)-200--mVIOFTSchmitttriggervoltagehysteresis(2)-5%VDD(3)--mVElectricalcharacteristicsSTM32F105xx,STM32F107xx58/108DocID15274Rev10AllI/OsareCMOSandTTLcompliant(nosoftwareconfigurationrequired).
TheircharacteristicscovermorethanthestrictCMOS-technologyorTTLparameters.
ThecoverageoftheserequirementsisshowninFigure18andFigure19forstandardI/Os,andinFigure20andFigure21for5VtolerantI/Os.
Figure18.
StandardI/Oinputcharacteristics-CMOSportIlkgInputleakagecurrent(4)VSS≤VIN≤VDDStandardI/Os--±1AVIN=5V,I/OFT--3RPUWeakpull-upequivalentresistor(5)AllpinsexceptforPA10VIN=VSS304050kΩPA1081115RPDWeakpull-downequivalentresistor(5)AllpinsexceptforPA10VIN=VDD304050kΩPA1081115CIOI/Opincapacitance--5-pF1.
FT=Five-volttolerant.
InordertosustainavoltagehigherthanVDD+0.
3theinternalpull-up/pull-downresistorsmustbedisabled.
2.
HysteresisvoltagebetweenSchmitttriggerswitchinglevels.
Basedoncharacterization,nottestedinproduction.
3.
Withaminimumof100mV.
4.
Leakagecouldbehigherthanmax.
ifnegativecurrentisinjectedonadjacentpins.
5.
Pull-upandpull-downresistorsaredesignedwithatrueresistanceinserieswithaswitchablePMOS/NMOS.
ThisMOS/NMOScontributiontotheseriesresistanceisminimum(~10%order).
Table36.
I/Ostaticcharacteristics(continued)SymbolParameterConditionsMinTypMaxUnitAIB6$$6)NPUTRANGENOTGUARANTEED6)(6$$#-/3STANDARDREQUIREMENT6)(6$$6)(6),6#-/3STANDARDREQUIREMENT6),6$$7),MAX7)(MIN6$$6),DocID15274Rev1059/108STM32F105xx,STM32F107xxElectricalcharacteristics107Figure19.
StandardI/Oinputcharacteristics-TTLportFigure20.
5VtolerantI/Oinputcharacteristics-CMOSportFigure21.
5VtolerantI/Oinputcharacteristics-TTLportAI)NPUTRANGENOTGUARANTEED6)(6),644,REQUIREMENTS6)(66)(6$$6),6$$44,REQUIREMENTS6),66$$67),MAX7)(MIN6$$#-/3STANDARDREQUIREMENTS6)(6$$#-/3STANDARDREQUIRMENT6),6$$6)(6),66$$6)NPUTRANGENOTGUARANTEEDAIB6)(6$$6),6$$NOTGUARANTEED)NPUTRANGE44,REQUIREMENT6)(66)(6$$6),6$$44,REQUIREMENTS6),66)(6),66$$67),MAX7)(MINAIElectricalcharacteristicsSTM32F105xx,STM32F107xx60/108DocID15274Rev10OutputdrivingcurrentTheGPIOs(generalpurposeinput/outputs)cansinkorsourceupto+/-8mA,andsinkorsourceupto+/-20mA(witharelaxedVOL/VOH).
Intheuserapplication,thenumberofI/OpinswhichcandrivecurrentmustbelimitedtorespecttheabsolutemaximumratingspecifiedinSection5.
2:ThesumofthecurrentssourcedbyalltheI/OsonVDD,plusthemaximumRunconsumptionoftheMCUsourcedonVDD,cannotexceedtheabsolutemaximumratingIVDD(seeTable7).
ThesumofthecurrentssunkbyalltheI/OsonVSSplusthemaximumRunconsumptionoftheMCUsunkonVSScannotexceedtheabsolutemaximumratingIVSS(seeTable7).
OutputvoltagelevelsUnlessotherwisespecified,theparametersgiveninTable37arederivedfromtestsperformedunderambienttemperatureandVDDsupplyvoltageconditionssummarizedinTable9.
AllI/OsareCMOSandTTLcompliant.
Table37.
OutputvoltagecharacteristicsSymbolParameterConditionsMinMaxUnitVOL(1)1.
TheIIOcurrentsunkbythedevicemustalwaysrespecttheabsolutemaximumratingspecifiedinTable7andthesumofIIO(I/Oportsandcontrolpins)mustnotexceedIVSS.
OutputlowlevelvoltageforanI/Opinwhen8pinsaresunkatsametimeTTLportIIO=+8mA2.
7V2)2.
TheIIOcurrentsourcedbythedevicemustalwaysrespecttheabsolutemaximumratingspecifiedinTable7andthesumofIIO(I/Oportsandcontrolpins)mustnotexceedIVDD.
OutputhighlevelvoltageforanI/Opinwhen8pinsaresourcedatsametimeVDD–0.
4-VOL(1)OutputlowlevelvoltageforanI/Opinwhen8pinsaresunkatsametimeCMOSportIIO=+8mA2.
7V2)OutputhighlevelvoltageforanI/Opinwhen8pinsaresourcedatsametime2.
4-VOL(1)(3)3.
Basedoncharacterizationdata,nottestedinproduction.
OutputlowlevelvoltageforanI/Opinwhen8pinsaresunkatsametimeIIO=+20mA2.
7V2)(3)OutputhighlevelvoltageforanI/Opinwhen8pinsaresourcedatsametimeVDD–1.
3-VOL(1)(3)OutputlowlevelvoltageforanI/Opinwhen8pinsaresunkatsametimeIIO=+6mA2V2.
7V-0.
4VVOH(2)(3)OutputhighlevelvoltageforanI/Opinwhen8pinsaresourcedatsametimeVDD–0.
4-DocID15274Rev1061/108STM32F105xx,STM32F107xxElectricalcharacteristics107Input/outputACcharacteristicsThedefinitionandvaluesofinput/outputACcharacteristicsaregiveninFigure22andTable38,respectively.
Unlessotherwisespecified,theparametersgiveninTable38arederivedfromtestsperformedundertheambienttemperatureandVDDsupplyvoltageconditionssummarizedinTable9.
Table38.
I/OACcharacteristics(1)1.
TheI/OspeedisconfiguredusingtheMODEx[1:0]bits.
RefertotheSTM32F10xxxreferencemanualforadescriptionofGPIOPortconfigurationregister.
MODEx[1:0]bitvalue(1)SymbolParameterConditionsMinMaxUnit10fmax(IO)outMaximumfrequency(2)2.
ThemaximumfrequencyisdefinedinFigure22.
CL=50pF,VDD=2Vto3.
6V-2MHztf(IO)outOutputhightolowlevelfalltimeCL=50pF,VDD=2Vto3.
6V-125(3)3.
Guaranteedbydesign,nottestedinproduction.
nstr(IO)outOutputlowtohighlevelrisetime-125(3)01fmax(IO)outMaximumfrequency(2)CL=50pF,VDD=2Vto3.
6V-10MHztf(IO)outOutputhightolowlevelfalltimeCL=50pF,VDD=2Vto3.
6V-25(3)nstr(IO)outOutputlowtohighlevelrisetime-25(3)11Fmax(IO)outMaximumfrequency(2)CL=30pF,VDD=2.
7Vto3.
6V-50MHzCL=50pF,VDD=2.
7Vto3.
6V-30MHzCL=50pF,VDD=2Vto2.
7V-20MHztf(IO)outOutputhightolowlevelfalltimeCL=30pF,VDD=2.
7Vto3.
6V-5(3)nsCL=50pF,VDD=2.
7Vto3.
6V-8(3)CL=50pF,VDD=2Vto2.
7V-12(3)tr(IO)outOutputlowtohighlevelrisetimeCL=30pF,VDD=2.
7Vto3.
6V-5(3)CL=50pF,VDD=2.
7Vto3.
6V-8(3)CL=50pF,VDD=2Vto2.
7V-12(3)-tEXTIpwPulsewidthofexternalsignalsdetectedbytheEXTIcontroller-10-nsElectricalcharacteristicsSTM32F105xx,STM32F107xx62/108DocID15274Rev10Figure22.
I/OACcharacteristicsdefinition5.
3.
14NRSTpincharacteristicsTheNRSTpininputdriverusesCMOStechnology.
Itisconnectedtoapermanentpull-upresistor,RPU(seeTable36).
Unlessotherwisespecified,theparametersgiveninTable39arederivedfromtestsperformedundertheambienttemperatureandVDDsupplyvoltageconditionssummarizedinTable9.
ai14131tr(IO)out50%90%Ttf(IO)outMaximumfrequencyisachievedif(t+t)2/3)Tandifthedutycycleis(45-55%)whenloadedby50pFrfEXTERNALOUTPUTON50pF10%50%90%10%Table39.
NRSTpincharacteristicsSymbolParameterConditionsMinTypMaxUnitVIL(NRST)(1)1.
Guaranteedbydesign,nottestedinproduction.
NRSTInputlowlevelvoltage-–0.
5-0.
8VVIH(NRST)(1)NRSTInputhighlevelvoltage-2-VDD+0.
5Vhys(NRST)NRSTSchmitttriggervoltagehysteresis--200-mVRPUWeakpull-upequivalentresistor(2)2.
Thepull-upisdesignedwithatrueresistanceinserieswithaswitchablePMOS.
ThisPMOScontributiontotheseriesresistancemustbeminimum(~10%order).
VIN=VSS304050kΩVF(NRST)(1)NRSTInputfilteredpulse---100nsVNF(NRST)(1)NRSTInputnotfilteredpulseVDD>2.
7V300--nsDocID15274Rev1063/108STM32F105xx,STM32F107xxElectricalcharacteristics107Figure23.
RecommendedNRSTpinprotection2.
Theresetnetworkprotectsthedeviceagainstparasiticresets.
3.
TheusermustensurethatthelevelontheNRSTpincangobelowtheVIL(NRST)maxlevelspecifiedinTable39.
Otherwisetheresetwillnotbetakenintoaccountbythedevice.
5.
3.
15TIMtimercharacteristicsTheparametersgiveninTable40areguaranteedbydesign.
RefertoSection5.
3.
12:I/Ocurrentinjectioncharacteristicsfordetailsontheinput/outputalternatefunctioncharacteristics(outputcompare,inputcapture,externalclock,PWMoutput).
ai14132dSTM32F10xxxRPUNRST(2)VDDFilterInternalReset0.
1FExternalresetcircuit(1)Table40.
TIMx(1)characteristics1.
TIMxisusedasageneraltermtorefertotheTIM1,TIM2,TIM3,TIM4andTIM5timers.
SymbolParameterConditionsMinMaxUnittres(TIM)Timerresolutiontime-1-tTIMxCLKfTIMxCLK=72MHz13.
9-nsfEXTTimerexternalclockfrequencyonCH1toCH4-0fTIMxCLK/2MHzfTIMxCLK=72MHz036MHzResTIMTimerresolution--16bittCOUNTER16-bitcounterclockperiodwheninternalclockisselected-165536tTIMxCLKfTIMxCLK=72MHz0.
0139910stMAX_COUNTMaximumpossiblecount--65536*65536tTIMxCLKfTIMxCLK=72MHz-59.
6sElectricalcharacteristicsSTM32F105xx,STM32F107xx64/108DocID15274Rev105.
3.
16CommunicationsinterfacesI2CinterfacecharacteristicsUnlessotherwisespecified,theparametersgiveninTable41arederivedfromtestsperformedundertheambienttemperature,fPCLK1frequencyandVDDsupplyvoltageconditionssummarizedinTable9.
TheSTM32F105xxandSTM32F107xxI2CinterfacemeetstherequirementsofthestandardI2Ccommunicationprotocolwiththefollowingrestrictions:theI/OpinsSDAandSCLaremappedtoarenot"true"open-drain.
Whenconfiguredasopen-drain,thePMOSconnectedbetweentheI/OpinandVDDisdisabled,butisstillpresent.
TheI2CcharacteristicsaredescribedinTable41.
ReferalsotoSection5.
3.
12:I/Ocurrentinjectioncharacteristicsformoredetailsontheinput/outputalternatefunctioncharacteristics(SDAandSCL).
Table41.
I2CcharacteristicsSymbolParameterStandardmodeI2C(1)1.
Guaranteedbydesign,nottestedinproduction.
FastmodeI2C(1)(2)2.
fPCLK1mustbeatleast2MHztoachievestandardmodeI2Cfrequencies.
Itmustbeatleast4MHztoachievethefastmodeI2Cfrequenciesanditmustbeamulitpleof10MHzinordertoreachI2Cfastmodemaximumclock400kHz.
UnitMinMaxMinMaxtw(SCLL)SCLclocklowtime4.
7-1.
3-stw(SCLH)SCLclockhightime4.
0-0.
6-tsu(SDA)SDAsetuptime250-100-nsth(SDA)SDAdataholdtime0(3)3.
ThemaximumholdtimeoftheStartconditionhasonlytobemetiftheinterfacedoesnotstretchthelowperiodofSCLsignal.
-0(4)4.
Thedevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignalinordertobridgetheundefinedregionofthefallingedgeofSCL.
900(3)tr(SDA)tr(SCL)SDAandSCLrisetime-100020+0.
1Cb300tf(SDA)tf(SCL)SDAandSCLfalltime-300-300th(STA)Startconditionholdtime4.
0-0.
6-stsu(STA)RepeatedStartconditionsetuptime4.
7-0.
6-tsu(STO)Stopconditionsetuptime4.
0-0.
6-μstw(STO:STA)StoptoStartconditiontime(busfree)4.
7-1.
3-μsCbCapacitiveloadforeachbusline-400-400pFDocID15274Rev1065/108STM32F105xx,STM32F107xxElectricalcharacteristics107Figure24.
I2CbusACwaveformsandmeasurementcircuit1.
MeasurementpointsaredoneatCMOSlevels:0.
3VDDand0.
7VDD.
Table42.
SCLfrequency(fPCLK1=36MHz.
,VDD=3.
3V)(1)(2)1.
RP=Externalpull-upresistance,fSCL=I2Cspeed,2.
Forspeedsaround200kHz,thetoleranceontheachievedspeedisof±5%.
Forotherspeedranges,thetoleranceontheachievedspeed±2%.
Thesevariationsdependontheaccuracyoftheexternalcomponentsusedtodesigntheapplication.
fSCL(kHz)I2C_CCRvalueRP=4.
7kΩ4000x801E3000x80282000x803C1000x00B4500x0168200x0384ai14133dStartSDA100Ω4.
7kΩICbus4.
7kΩ100ΩVDDVDDSTM32F10xSDASCLtf(SDA)tr(SDA)SCLth(STA)tw(SCLH)tw(SCLL)tsu(SDA)tr(SCL)tf(SCL)th(SDA)StartrepeatedStarttsu(STA)tsu(STO)Stoptsu(STO:STA)ElectricalcharacteristicsSTM32F105xx,STM32F107xx66/108DocID15274Rev10I2S-SPIinterfacecharacteristicsUnlessotherwisespecified,theparametersgiveninTable43forSPIorinTable44forI2Sarederivedfromtestsperformedundertheambienttemperature,fPCLKxfrequencyandVDDsupplyvoltageconditionssummarizedinTable9.
RefertoSection5.
3.
12:I/Ocurrentinjectioncharacteristicsformoredetailsontheinput/outputalternatefunctioncharacteristics(NSS,SCK,MOSI,MISOforSPIandWS,CK,SDforI2S).
Table43.
SPIcharacteristicsSymbolParameterConditionsMinMaxUnitfSCK1/tc(SCK)SPIclockfrequencyMastermode-18MHzSlavemode-18tr(SCK)tf(SCK)SPIclockriseandfalltimeCapacitiveload:C=30pF-8nsDuCy(SCK)SPIslaveinputclockdutycycleSlavemode3070%tsu(NSS)NSSsetuptimeSlavemode4tPCLK-nsth(NSS)NSSholdtimeSlavemode2tPCLK-tw(SCKH)tw(SCKL)SCKhighandlowtimeMastermode,fPCLK=36MHz,presc=45060tsu(MI)DatainputsetuptimeMastermode4-tsu(SI)Slavemode5-th(MI)DatainputholdtimeMastermode5-th(SI)Slavemode5-ta(SO)DataoutputaccesstimeSlavemode,fPCLK=20MHz-3*tPCLKtv(SO)DataoutputvalidtimeSlavemode(afterenableedge)-34tv(MO)DataoutputvalidtimeMastermode(afterenableedge)-8th(SO)DataoutputholdtimeSlavemode(afterenableedge)32-th(MO)Mastermode(afterenableedge)10-DocID15274Rev1067/108STM32F105xx,STM32F107xxElectricalcharacteristics107Figure25.
SPItimingdiagram-slavemodeandCPHA=0Figure26.
SPItimingdiagram-slavemodeandCPHA=1(1)1.
MeasurementpointsaredoneatCMOSlevels:0.
3VDDand0.
7VDD.
DLF6&.
,QSXW166LQSXWW68166WF6&.
WK166&3+$&32/&3+$&32/WZ6&.
+WZ6&.
/W962WK62WU6&.
WI6&.
WGLV62WD620,62287387026,,138706%287%,7287/6%287WVX6,WK6,06%,1%,7,1/6%,1DLE166LQSXWW68166WF6&.
WK1666&.
LQSXW&3+$&32/&3+$&32/WZ6&.
+WZ6&.
/WD62WY62WK62WU6&.
WI6&.
WGLV620,62287387026,,1387WVX6,WK6,06%28706%,1%,7287/6%287/6%,1%,7,1ElectricalcharacteristicsSTM32F105xx,STM32F107xx68/108DocID15274Rev10Figure27.
SPItimingdiagram-mastermode(1)1.
MeasurementpointsaredoneatCMOSlevels:0.
3VDDand0.
7VDD.
DLF6&.
2XWSXW&3+$026,2873870,62,1387&3+$/6%287/6%,1&32/&32/%,7287166LQSXWWF6&.
WZ6&.
+WZ6&.
/WU6&.
WI6&.
WK0,+LJK6&.
2XWSXW&3+$&3+$&32/&32/WVX0,WY02WK0206%,1%,7,106%287DocID15274Rev1069/108STM32F105xx,STM32F107xxElectricalcharacteristics107Table44.
I2ScharacteristicsSymbolParameterConditionsMinMaxUnitfCK1/tc(CK)I2SclockfrequencyMasterdata:16bits,audiofreq=48K1.
521.
54MHzSlave06.
5tr(CK)tf(CK)I2SclockriseandfalltimecapacitiveloadCL=50pF-8nstw(CKH)(1)I2SclockhightimeMasterfPCLK=16MHz,audiofreq=48K317320tw(CKL)(1)I2Sclocklowtime333336tv(WS)(1)WSvalidtimeMastermode3-th(WS)(1)WSholdtimeMastermodeI2S20-I2S30-tsu(WS)(1)WSsetuptimeSlavemodeI2S24-I2S39-th(WS)(1)WSholdtimeSlavemode0-DuCy(SCK)I2SslaveinputclockdutycycleSlavemode3070%tsu(SD_MR)(1)DatainputsetuptimeMasterreceiverI2S28-nsI2S310-tsu(SD_SR)(1)SlavereceiverI2S23-I2S38-th(SD_MR)(1)DatainputholdtimeMasterreceiverI2S22-I2S34-th(SD_SR)(1)SlavereceiverI2S22-I2S34-tv(SD_ST)(1)(3)DataoutputvalidtimeSlavetransmitter(afterenableedge)I2S223-I2S333-th(SD_ST)(1)DataoutputholdtimeSlavetransmitter(afterenableedge)I2S229-I2S327-tv(SD_MT)(1)DataoutputvalidtimeMastertransmitter(afterenableedge)I2S2-5I2S3-2th(SD_MT)(1)DataoutputholdtimeMastertransmitter(afterenableedge)I2S211-I2S34-1.
Basedondesignsimulationand/orcharacterizationresults,nottestedinproduction.
ElectricalcharacteristicsSTM32F105xx,STM32F107xx70/108DocID15274Rev10Figure28.
I2Sslavetimingdiagram(Philipsprotocol)(1)1.
MeasurementpointsaredoneatCMOSlevels:0.
3*VDDand0.
7*VDD.
2.
LSBtransmit/receiveofthepreviouslytransmittedbyte.
NoLSBtransmit/receiveissentbeforethefirstbyte.
Figure29.
I2Smastertimingdiagram(Philipsprotocol)(1)1.
Basedoncharacterization,nottestedinproduction.
2.
LSBtransmit/receiveofthepreviouslytransmittedbyte.
NoLSBtransmit/receiveissentbeforethefirstbyte.
DocID15274Rev1071/108STM32F105xx,STM32F107xxElectricalcharacteristics107USBOTGFScharacteristicsTheUSBOTGinterfaceisUSB-IFcertified(Full-Speed).
Figure30.
USBOTGFStimings:definitionofdatasignalriseandfalltimeTable45.
USBOTGFSstartuptimeSymbolParameterMaxUnittSTARTUP(1)1.
Guaranteedbydesign,nottestedinproduction.
USBOTGFStransceiverstartuptime1sTable46.
USBOTGFSDCelectricalcharacteristicsSymbolParameterConditionsMin.
(1)1.
Allthevoltagesaremeasuredfromthelocalgroundpotential.
Typ.
Max.
(1)UnitInputlevelsVDDUSBOTGFSoperatingvoltage-3.
0(2)2.
TheSTM32F105xxandSTM32F107xxUSBOTGFSfunctionalityisensureddownto2.
7VbutnotthefullUSBOTGFSelectricalcharacteristicswhicharedegradedinthe2.
7-to-3.
0VVDDvoltagerange.
-3.
6VVDI(3)3.
Guaranteedbydesign,nottestedinproduction.
DifferentialinputsensitivityI(USBDP,USBDM)0.
2--VVCM(3)DifferentialcommonmoderangeIncludesVDIrange0.
8-2.
5VSE(3)Singleendedreceiverthreshold-1.
3-2.
0OutputlevelsVOLStaticoutputlevellowRLof1.
5kΩto3.
6V(4)4.
RListheloadconnectedontheUSBOTGFSdrivers-0.
3VVOHStaticoutputlevelhighRLof15kΩtoVSS(4)2.
8-3.
6RPDPull-downresistanceonPA11,PA12VIN=VDD172124kΩPull-downresistanceonPA90.
651.
12.
0RPUPull-upresistanceonPA12VIN=VSS1.
51.
82.
1Pull-upresistanceonPA9VIN=VSS0.
250.
370.
55DLE&URVVRYHUSRLQWV'LIIHUHQWLDOGDWDOLQHV9&56966WIWUElectricalcharacteristicsSTM32F105xx,STM32F107xx72/108DocID15274Rev10EthernetcharacteristicsTable48shownstheEthernetoperatingvoltage.
Table49givesthelistofEthernetMACsignalsfortheSMI(stationmanagementinterface)andFigure31showsthecorrespondingtimingdiagram.
Figure31.
EthernetSMItimingdiagramTable47.
USBOTGFSelectricalcharacteristics(1)1.
Guaranteedbydesign,nottestedinproduction.
DrivercharacteristicsSymbolParameterConditionsMinMaxUnittrRisetime(2)2.
Measuredfrom10%to90%ofthedatasignal.
Formoredetailedinformations,refertoUSBSpecification-Chapter7(version2.
0).
CL=50pF420nstfFalltime(2)CL=50pF420nstrfmRise/falltimematchingtr/tf90110%VCRSOutputsignalcrossovervoltage-1.
32.
0VTable48.
EthernetDCelectricalcharacteristicsSymbolParameterMin.
(1)1.
Allthevoltagesaremeasuredfromthelocalgroundpotential.
Max.
(1)UnitInputlevelVDDEthernetoperatingvoltage3.
03.
6VTable49.
Dynamiccharacteristics:EthernetMACsignalsforSMISymbolRatingMinTypMaxUnittMDCMDCcycletime(1.
71MHz,AHB=72MHz)583583.
5584nstd(MDIO)MDIOwritedatavalidtime13.
514.
515.
5nstsu(MDIO)Readdatasetuptime35--nsth(MDIO)Readdataholdtime0--ns%4(-$#%4(-$)//%4(-$)/)T-$#TD-$)/TSU-$)/TH-$)/AICDocID15274Rev1073/108STM32F105xx,STM32F107xxElectricalcharacteristics107Table50givesthelistofEthernetMACsignalsfortheRMIIandFigure32showsthecorrespondingtimingdiagram.
Figure32.
EthernetRMIItimingdiagramTable51givesthelistofEthernetMACsignalsforMIIandFigure32showsthecorrespondingtimingdiagram.
Figure33.
EthernetMIItimingdiagramTable50.
Dynamiccharacteristics:EthernetMACsignalsforRMIISymbolRatingMinTypMaxUnittsu(RXD)Receivedatasetuptime4--nstih(RXD)Receivedataholdtime2--nstsu(DV)Carriersenseset-uptime4--nstih(DV)Carriersenseholdtime2--nstd(TXEN)Transmitenablevaliddelaytime81016nstd(TXD)Transmitdatavaliddelaytime71016ns2-))2%&#,+2-))48%.
2-))48$;=2-))28$;=2-))#23$6TD48%.
TD48$TSU28$TSU#23TIH28$TIH#23AIMII_RX_CLKMII_RXD[3:0]MII_RX_DVMII_RX_ERtd(TXEN)td(TXD)tsu(RXD)tsu(ER)tsu(DV)tih(RXD)tih(ER)tih(DV)ai15668MII_TX_CLKMII_TX_ENMII_TXD[3:0]ElectricalcharacteristicsSTM32F105xx,STM32F107xx74/108DocID15274Rev10CAN(controllerareanetwork)interfaceRefertoSection5.
3.
12:I/Ocurrentinjectioncharacteristicsformoredetailsontheinput/outputalternatefunctioncharacteristics(CANTXandCANRX).
5.
3.
1712-bitADCcharacteristicsUnlessotherwisespecified,theparametersgiveninTable52arederivedfromtestsperformedundertheambienttemperature,fPCLK2frequencyandVDDAsupplyvoltageconditionssummarizedinTable9.
Note:Itisrecommendedtoperformacalibrationaftereachpower-up.
Table51.
Dynamiccharacteristics:EthernetMACsignalsforMIISymbolRatingMinTypMaxUnittsu(RXD)Receivedatasetuptime10--nstih(RXD)Receivedataholdtime10--nstsu(DV)Datavalidsetuptime10--nstih(DV)Datavalidholdtime10--nstsu(ER)Errorsetuptime10--nstih(ER)Errorholdtime10--nstd(TXEN)Transmitenablevaliddelaytime141618nstd(TXD)Transmitdatavaliddelaytime131620nsTable52.
ADCcharacteristicsSymbolParameterConditionsMinTypMaxUnitVDDAPowersupply-2.
4-3.
6VVREF+Positivereferencevoltage-2.
4-VDDAVIVREFCurrentontheVREFinputpin--160(1)220(1)AfADCADCclockfrequency-0.
6-14MHzfS(2)Samplingrate-0.
05-1MHzfTRIG(2)ExternaltriggerfrequencyfADC=14MHz--823kHz---171/fADCVAINConversionvoltagerange(3)-0(VSSAorVREF-tiedtoground)-VREF+VRAIN(2)ExternalinputimpedanceSeeEquation1andTable53fordetails--50kΩRADC(2)Samplingswitchresistance---1kΩCADC(2)Internalsampleandholdcapacitor---8pFtCAL(2)CalibrationtimefADC=14MHz5.
9s-831/fADCDocID15274Rev1075/108STM32F105xx,STM32F107xxElectricalcharacteristics107Equation1:RAINmaxformulaTheformulaabove(Equation1)isusedtodeterminethemaximumexternalimpedanceallowedforanerrorbelow1/4ofLSB.
HereN=12(from12-bitresolution).
tlat(2)InjectiontriggerconversionlatencyfADC=14MHz--0.
214s---3(4)1/fADCtlatr(2)RegulartriggerconversionlatencyfADC=14MHz--0.
143s---2(4)1/fADCtS(2)SamplingtimefADC=14MHz0.
107-17.
1s-1.
5-239.
51/fADCtSTAB(2)Power-uptime-001stCONV(2)Totalconversiontime(includingsamplingtime)fADC=14MHz1-18s-14to252(tSforsampling+12.
5forsuccessiveapproximation)1/fADC1.
Basedoncharacterization,nottestedinproduction.
2.
Guaranteedbydesign,nottestedinproduction.
3.
VREF+isinternallyconnectedtoVDDAandVREF-isinternallyconnectedtoVSSA.
4.
Forexternaltriggers,adelayof1/fPCLK2mustbeaddedtothelatencyspecifiedinTable52.
Table52.
ADCcharacteristics(continued)SymbolParameterConditionsMinTypMaxUnitTable53.
RAINmaxforfADC=14MHz(1)1.
Basedoncharacterization,nottestedinproduction.
Ts(cycles)tS(s)RAINmax(kΩ)1.
50.
110.
47.
50.
545.
913.
50.
9611.
428.
52.
0425.
241.
52.
9637.
255.
53.
965071.
55.
11NA239.
517.
1NARAINTSfADCCADC2N2+()ln**-RADC–2F105xx,STM32F107xx76/108DocID15274Rev10Note:ADCaccuracyvs.
negativeinjectioncurrent:Injectinganegativecurrentonanyofthestandard(non-robust)analoginputpinsshouldbeavoidedasthissignificantlyreducestheaccuracyoftheconversionbeingperformedonanotheranaloginput.
ItisrecommendedtoaddaSchottkydiode(pintoground)tostandardanalogpinswhichmaypotentiallyinjectnegativecurrents.
AnypositiveinjectioncurrentwithinthelimitsspecifiedforIINJ(PIN)andΣIINJ(PIN)inSection5.
3.
12doesnotaffecttheADCaccuracy.
Table54.
ADCaccuracy-limitedtestconditions(1)1.
ADCDCaccuracyvaluesaremeasuredafterinternalcalibration.
SymbolParameterTestconditionsTypMax(2)2.
Basedoncharacterization,nottestedinproduction.
UnitETTotalunadjustederrorfPCLK2=56MHz,fADC=14MHz,RAIN25°CMeasurementsmadeafterADCcalibration±1.
3±2LSBEOOffseterror±1±1.
5EGGainerror±0.
5±1.
5EDDifferentiallinearityerror±0.
7±1ELIntegrallinearityerror±0.
8±1.
5Table55.
ADCaccuracy(1)(2)1.
ADCDCaccuracyvaluesaremeasuredafterinternalcalibration.
2.
BetterperformancecouldbeachievedinrestrictedVDD,frequencyandtemperatureranges.
SymbolParameterTestconditionsTypMax(3)3.
Basedoncharacterization,nottestedinproduction.
UnitETTotalunadjustederrorfPCLK2=56MHz,fADC=14MHz,RAIN2.
4Vto3.
6VMeasurementsmadeafterADCcalibration±2±5LSBEOOffseterror±1.
5±2.
5EGGainerror±1.
5±3EDDifferentiallinearityerror±1±2ELIntegrallinearityerror±1.
5±3DocID15274Rev1077/108STM32F105xx,STM32F107xxElectricalcharacteristics107Figure34.
ADCaccuracycharacteristicsFigure35.
TypicalconnectiondiagramusingtheADC1.
RefertoTable52forthevaluesofRAIN,RADCandCADC.
2.
CparasiticrepresentsthecapacitanceofthePCB(dependentonsolderingandPCBlayoutquality)plusthepadcapacitance(roughly7pF).
AhighCparasiticvaluewilldowngradeconversionaccuracy.
Toremedythis,fADCshouldbereduced.
AIC%/%',3")$%!
,%4%$%,6$$!
633!
62%&ORDEPENDINGONPACKAGE=6$$!
;,3")$%!
,DLG670)[[[9''$,1[,/$9975$,1&SDUDVLWLF9$,19975$'&&$'&ELWFRQYHUWHU6DPSOHDQGKROG$'&FRQYHUWHUElectricalcharacteristicsSTM32F105xx,STM32F107xx78/108DocID15274Rev10GeneralPCBdesignguidelinesPowersupplydecouplingshouldbeperformedasshowninFigure36orFigure37,dependingonwhetherVREF+isconnectedtoVDDAornot.
The10nFcapacitorsshouldbeceramic(goodquality).
Theyshouldbeplacedthemascloseaspossibletothechip.
Figure36.
Powersupplyandreferencedecoupling(VREF+notconnectedtoVDDA)1.
VREF+andVREF–inputsareavailableonlyon100-pinpackages.
Figure37.
Powersupplyandreferencedecoupling(VREF+connectedtoVDDA)1.
VREF+andVREF–inputsareavailableonlyon100-pinpackages.
VREF+STM32F10xxxVDDAVSSA/VREF-1F//10nF1F//10nFai14380c(Seenote1)(Seenote1)VREF+/VDDASTM32F10xxx1F//10nFVREF–/VSSAai14381c(Seenote1)(Seenote1)DocID15274Rev1079/108STM32F105xx,STM32F107xxElectricalcharacteristics1075.
3.
18DACelectricalspecificationsTable56.
DACcharacteristicsSymbolParameterMinTypMaxUnitCommentsVDDAAnalogsupplyvoltage2.
4-3.
6V-VREF+Referencesupplyvoltage2.
4-3.
6VVREF+mustalwaysbebelowVDDAVSSAGround0-0V-RLOAD(1)ResistiveloadwithbufferON5--kΩ-RO(1)ImpedanceoutputwithbufferOFF--15kΩWhenthebufferisOFF,theMinimumresistiveloadbetweenDAC_OUTandVSStohavea1%accuracyis1.
5MΩCLOAD(1)Capacitiveload--50pFMaximumcapacitiveloadatDAC_OUTpin(whenthebufferisON).
DAC_OUTmin(1)LowerDAC_OUTvoltagewithbufferON0.
2--VItgivesthemaximumoutputexcursionoftheDAC.
Itcorrespondsto12-bitinputcode(0x0E0)to(0xF1C)atVREF+=3.
6Vand(0x155)to(0xEAB)atVREF+=2.
4VDAC_OUTmax(1)HigherDAC_OUTvoltagewithbufferON--VDDA–0.
2VDAC_OUTmin(1)LowerDAC_OUTvoltagewithbufferOFF-0.
5-mVItgivesthemaximumoutputexcursionoftheDAC.
DAC_OUTmax(1)HigherDAC_OUTvoltagewithbufferOFF--VREF+–1LSBVIDDVREF+DACDCcurrentconsumptioninquiescentmode(Standbymode)--220AWithnoload,worstcode(0xF1C)atVREF+=3.
6VintermsofDCconsumptionontheinputsIDDADACDCcurrentconsumptioninquiescentmode(Standbymode)--380AWithnoload,middlecode(0x800)ontheinputs--480AWithnoload,worstcode(0xF1C)atVREF+=3.
6VintermsofDCconsumptionontheinputsDNL(2)DifferentialnonlinearityDifferencebetweentwoconsecutivecode-1LSB)--±0.
5LSBGivenfortheDACin10-bitconfiguration.
--±2LSBGivenfortheDACin12-bitconfiguration.
INL(2)Integralnonlinearity(differencebetweenmeasuredvalueatCodeiandthevalueatCodeionalinedrawnbetweenCode0andlastCode1023)--±1LSBGivenfortheDACin10-bitconfiguration.
--±4LSBGivenfortheDACin12-bitconfiguration.
ElectricalcharacteristicsSTM32F105xx,STM32F107xx80/108DocID15274Rev10Figure38.
12-bitbuffered/non-bufferedDAC1.
TheDACintegratesanoutputbufferthatcanbeusedtoreducetheoutputimpedanceandtodriveexternalloadsdirectlywithouttheuseofanexternaloperationalamplifier.
ThebuffercanbebypassedbyconfiguringtheBOFFxbitintheDAC_CRregister.
Offset(2)Offseterror(differencebetweenmeasuredvalueatCode(0x800)andtheidealvalue=VREF+/2)--±10mVGivenfortheDACin12-bitconfiguration--±3LSBGivenfortheDACin10-bitatVREF+=3.
6V--±12LSBGivenfortheDACin12-bitatVREF+=3.
6VGainerror(2)Gainerror--±0.
5%GivenfortheDACin12bitconfigurationtSETTLING(2)Settlingtime(fullscale:fora10-bitinputcodetransitionbetweenthelowestandthehighestinputcodeswhenDAC_OUTreachesfinalvalue±1LSB-34sCLOAD≤50pF,RLOAD≥5kΩUpdaterate(2)MaxfrequencyforacorrectDAC_OUTchangewhensmallvariationintheinputcode(fromcodeitoi+1LSB)--1MS/sCLOAD≤50pF,RLOAD≥5kΩtWAKEUP(2)Wakeuptimefromoffstate(SettingtheENxbitintheDACControlregister)-6.
510sCLOAD≤50pF,RLOAD≥5kΩinputcodebetweenlowestandhighestpossibleones.
PSRR+(1)Powersupplyrejectionratio(toVDDA)(staticDCmeasurement-–67–40dBNoRLOAD,CLOAD=50pF1.
Guaranteedbydesign,nottestedinproduction.
2.
Guaranteedbycharacterization,nottestedinproduction.
Table56.
DACcharacteristics(continued)SymbolParameterMinTypMaxUnitComments%XIIHUELWGLJLWDOWRDQDORJFRQYHUWHU%XIIHUHGQRQEXIIHUHG'$&'$&[B2875/2$'&/2$'DLGDocID15274Rev1081/108STM32F105xx,STM32F107xxElectricalcharacteristics1075.
3.
19TemperaturesensorcharacteristicsTable57.
TScharacteristicsSymbolParameterMinTypMaxUnitTL(1)1.
Basedoncharacterization,nottestedinproduction.
VSENSElinearitywithtemperature-±1±2°CAvg_Slope(1)Averageslope4.
04.
34.
6mV/°CV25(1)Voltageat25°C1.
341.
431.
52VtSTART(2)2.
Guaranteedbydesign,nottestedinproduction.
Startuptime4-10sTS_temp(3)(2)3.
Shortestsamplingtimecanbedeterminedintheapplicationbymultipleiterations.
ADCsamplingtimewhenreadingthetemperature--17.
1sPackageinformationSTM32F105xx,STM32F107xx82/108DocID15274Rev106PackageinformationInordertomeetenvironmentalrequirements,SToffersthesedevicesindifferentgradesofECOPACKpackages,dependingontheirlevelofenvironmentalcompliance.
ECOPACKspecifications,gradedefinitionsandproductstatusareavailableat:www.
st.
com.
ECOPACKisanSTtrademark.
6.
1LFBGA100packageinformationFigure39.
LFBGA100-10x10mmlowprofilefinepitchballgridarraypackageoutline+B0(B96HDWLQJSODQH$$H))'.
HHH=239,(:%277209,(:H$$=274Rev1083/108STM32F105xx,STM32F107xxPackageinformation107Figure41.
LFBGA100–100-balllowprofilefinepitchballgridarray,10x10mm,0.
8mmpitch,packagerecommendedfootprintFigure40.
LFBGA100–100-balllowprofilefinepitchballgridarray,10x10mm,0.
8mmpitch,packagemechanicaldataSymbolmillimetersinches(1)1.
Valuesininchesareconvertedfrommmandroundedto4decimaldigits.
MinTypMaxTypMinMaxA--1.
700--0.
0669A10.
270--0.
0106--A2-0.
300--0.
0118-A4--0.
800--0.
0315b0.
4500.
5000.
5500.
01770.
01970.
0217D9.
85010.
00010.
1500.
38780.
39370.
3996D1-7.
200--0.
2835-E9.
85010.
00010.
1500.
38780.
39370.
3996E1-7.
200--0.
2835-e-0.
800--0.
0315-F-1.
400--0.
0551-ddd--0.
120--0.
0047eee--0.
150--0.
0059fff--0.
080--0.
0031Table58.
LFBGA100recommendedPCBdesignrules(0.
8mmpitchBGA)DimensionRecommendedvaluesPitch0.
8Dpad0.
500mmDsm0.
570mmtyp.
(dependsonthesoldermaskregistrationtolerance)Stencilopening0.
500mmStencilthicknessBetween0.
100mmand0.
125mmPadtracewidth0.
120mm+B)3B9'SDG'VPPackageinformationSTM32F105xx,STM32F107xx84/108DocID15274Rev10DevicemarkingforLFBGA100ThefollowingfigureshowsthedevicemarkingfortheLQFP100package.
Otheroptionalmarkingorinset/upsetmarks,whichidentifythepartsthroughoutsupplychainoperations,arenotindicatedbelow.
Figure42.
LFBGA100markingexample(packagetopview)Partsmarkedas"ES","E"oraccompaniedbyanEngineeringSamplenotificationletter,arenotyetqualifiedandthereforenotyetreadytobeusedinproductionandanyconsequencesderivingfromsuchusagewillnotbeatSTcharge.
Innoevent,STwillbeliableforanycustomerusageoftheseengineeringsamplesinproduction.
STQualityhastobecontactedpriortoanydecisiontousetheseEngineeringsamplestorunqualificationactivity.
069^dD&s,3URGXFWLGHQWLILFDWLRQ$GGLWLRQDOLQIRUPDWLRQttz'DWHFRGH3LQLGHQWLILHUDocID15274Rev1085/108STM32F105xx,STM32F107xxPackageinformation1076.
2LQFP100packageinformationFigure43.
LQFP100–14x14mm100pinlow-profilequadflatpackageoutline1.
Drawingisnottoscale.
Dimensionareinmillimeter.
Table59.
LQPF100-100-pin,14x14mmlow-profilequadflatpackagemechanicaldataSymbolmillimetersinches(1)MinTypMaxMinTypMaxA--1.
600--0.
0630A10.
050-0.
1500.
0020-0.
0059A21.
3501.
4001.
4500.
05310.
05510.
0571b0.
1700.
2200.
2700.
00670.
00870.
0106c0.
090-0.
2000.
0035-0.
0079D15.
80016.
00016.
2000.
62200.
62990.
6378D113.
80014.
00014.
2000.
54330.
55120.
5591D3-12.
000--0.
4724-E15.
80016.
00016.
2000.
62200.
62990.
6378E113.
80014.
00014.
2000.
54330.
55120.
5591E)$%.
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PackageinformationSTM32F105xx,STM32F107xx86/108DocID15274Rev10Figure44.
LQFP100-100-pin,14x14mmlow-profilequadflatrecommendedfootprintE3-12.
000--0.
4724-e-0.
500--0.
0197-L0.
4500.
6000.
7500.
01770.
02360.
0295L1-1.
000--0.
0394-k0.
0°3.
5°7.
0°0.
0°3.
5°7.
0°ccc--0.
080--0.
00311.
Valuesininchesareconvertedfrommmandroundedto4decimaldigits.
Table59.
LQPF100-100-pin,14x14mmlow-profilequadflatpackagemechanicaldata(continued)Symbolmillimetersinches(1)MinTypMaxMinTypMaxAICDocID15274Rev1087/108STM32F105xx,STM32F107xxPackageinformation107DevicemarkingforLQFP100ThefollowingfigureshowsthedevicemarkingfortheLQFP100package.
Otheroptionalmarkingorinset/upsetmarks,whichidentifythepartsthroughoutsupplychainoperations,arenotindicatedbelow.
Figure45.
LQFP100markingexample(packagetopview)1.
Partsmarkedas"ES","E"oraccompaniedbyanEngineeringSamplenotificationletter,arenotyetqualifiedandthereforenotyetreadytobeusedinproductionandanyconsequencesderivingfromsuchusagewillnotbeatSTcharge.
Innoevent,STwillbeliableforanycustomerusageoftheseengineeringsamplesinproduction.
STQualityhastobecontactedpriortoanydecisiontousetheseEngineeringsamplestorunqualificationactivity.
06Y9^dD&sd3URGXFWLGHQWLILFDWLRQ5HYLVLRQFRGHttz'DWHFRGH2SWLRQDOJDWHPDUN3LQLGHQWLILHUPackageinformationSTM32F105xx,STM32F107xx88/108DocID15274Rev106.
3LQFP64packageinformationFigure46.
LQFP64–10x10mm64pinlow-profilequadflatpackageoutline1.
Drawingisnotinscale.
Table60.
LQFP64–10x10mm64pinlow-profilequadflatpackagemechanicaldataSymbolmillimetersinches(1)MinTypMaxMinTypMaxA--1.
600--0.
0630A10.
050-0.
1500.
0020-0.
0059A21.
3501.
4001.
4500.
05310.
05510.
0571b0.
1700.
2200.
2700.
00670.
00870.
0106c0.
090-0.
2000.
0035-0.
0079D-12.
000--0.
4724-D1-10.
000--0.
3937-D3-7.
500--0.
2953-E-12.
000--0.
4724-E1-10.
000--0.
3937-E3-7.
500--0.
2953-:B0(B9$$$6($7,1*3/$1(FFF&E&F$//.
,'(17,),&$7,213,1'''H(((*$8*(3/$1(PPDocID15274Rev1089/108STM32F105xx,STM32F107xxPackageinformation107Figure47.
LQFP64-64-pin,10x10mmlow-profilequadflatrecommendedfootprint1.
Dimensionsareinmillimeters.
e-0.
500--0.
0197-θ0°3.
5°7°0°3.
5°7°L0.
4500.
6000.
7500.
01770.
02360.
0295L1-1.
000--0.
0394-ccc--0.
080--0.
00311.
Valuesininchesareconvertedfrommmandroundedto4decimaldigits.
Table60.
LQFP64–10x10mm64pinlow-profilequadflatpackagemechanicaldataSymbolmillimetersinches(1)MinTypMaxMinTypMaxAICPackageinformationSTM32F105xx,STM32F107xx90/108DocID15274Rev10DevicemarkingforLQFP64ThefollowingfigureshowsthedevicemarkingfortheLQFP64package.
Otheroptionalmarkingorinset/upsetmarks,whichidentifythepartsthroughoutsupplychainoperations,arenotindicatedbelow.
Figure48.
LQFP64markingexample(packagetopview)1.
Partsmarkedas"ES","E"oraccompaniedbyanEngineeringSamplenotificationletter,arenotyetqualifiedandthereforenotyetreadytobeusedinproductionandanyconsequencesderivingfromsuchusagewillnotbeatSTcharge.
Innoevent,STwillbeliableforanycustomerusageoftheseengineeringsamplesinproduction.
STQualityhastobecontactedpriortoanydecisiontousetheseEngineeringsamplestorunqualificationactivity.
06Y9^dD&ztt5HYLVLRQFRGH'DWHFRGH3LQLGHQWLILHU3URGXFWLGHQWLILFDWLRQZdDocID15274Rev1091/108STM32F105xx,STM32F107xxPackageinformation1076.
4ThermalcharacteristicsThemaximumchipjunctiontemperature(TJmax)mustneverexceedthevaluesgiveninTable9:Generaloperatingconditionsonpage37.
Themaximumchip-junctiontemperature,TJmax,indegreesCelsius,maybecalculatedusingthefollowingequation:TJmax=TAmax+(PDmax*ΘJA)Where:TAmaxisthemaximumambienttemperaturein°C,ΘJAisthepackagejunction-to-ambientthermalresistance,in°C/W,PDmaxisthesumofPINTmaxandPI/Omax(PDmax=PINTmax+PI/Omax),PINTmaxistheproductofIDDandVDD,expressedinWatts.
Thisisthemaximumchipinternalpower.
PI/Omaxrepresentsthemaximumpowerdissipationonoutputpinswhere:PI/Omax=Σ(VOL*IOL)+Σ((VDD–VOH)*IOH),takingintoaccounttheactualVOL/IOLandVOH/IOHoftheI/Osatlowandhighlevelintheapplication.
6.
4.
1ReferencedocumentJESD51-2IntegratedCircuitsThermalTestMethodEnvironmentConditions-NaturalConvection(StillAir).
Availablefromwww.
jedec.
org.
Table61.
PackagethermalcharacteristicsSymbolParameterValueUnitΘJAThermalresistancejunction-ambientLQFP100-14*14mm/0.
5mmpitch46°C/WThermalresistancejunction-ambientLQFP64-10*10mm/0.
5mmpitch45ΘJAThermalresistancejunction-ambientLFBGA100-10*10mm/0.
8mmpitch40°C/WThermalresistancejunction-ambientLQFP100-14*14mm/0.
5mmpitch46Thermalresistancejunction-ambientLQFP64-10*10mm/0.
5mmpitch45PackageinformationSTM32F105xx,STM32F107xx92/108DocID15274Rev106.
4.
2SelectingtheproducttemperaturerangeWhenorderingthemicrocontroller,thetemperaturerangeisspecifiedintheorderinginformationschemeshowninTable62:Orderinginformationscheme.
Eachtemperaturerangesuffixcorrespondstoaspecificguaranteedambienttemperatureatmaximumdissipationand,toaspecificmaximumjunctiontemperature.
AsapplicationsdonotcommonlyusetheSTM32F103xxatmaximumdissipation,itisusefultocalculatetheexactpowerconsumptionandjunctiontemperaturetodeterminewhichtemperaturerangewillbebestsuitedtotheapplication.
Thefollowingexamplesshowhowtocalculatethetemperaturerangeneededforagivenapplication.
Example1:High-performanceapplicationAssumingthefollowingapplicationconditions:MaximumambienttemperatureTAmax=82°C(measuredaccordingtoJESD51-2),IDDmax=50mA,VDD=3.
5V,maximum20I/OsusedatthesametimeinoutputatlowlevelwithIOL=8mA,VOL=0.
4Vandmaximum8I/OsusedatthesametimeinoutputatlowlevelwithIOL=20mA,VOL=1.
3VPINTmax=50mA*3.
5V=175mWPIOmax=20*8mA*0.
4V+8*20mA*1.
3V=272mWThisgives:PINTmax=175mWandPIOmax=272mW:PDmax=175+272=447mWThus:PDmax=447mWUsingthevaluesobtainedinTable61TJmaxiscalculatedasfollows:–ForLQFP100,46°C/WTJmax=82°C+(46°C/W*447mW)=82°C+20.
6°C=102.
6°CThisiswithintherangeofthesuffix6versionparts(–402:Orderinginformationscheme).
Example2:High-temperatureapplicationUsingthesamerules,itispossibletoaddressapplicationsthatrunathighambienttemperatureswithalowdissipation,aslongasjunctiontemperatureTJremainswithinthespecifiedrange.
Assumingthefollowingapplicationconditions:MaximumambienttemperatureTAmax=115°C(measuredaccordingtoJESD51-2),IDDmax=20mA,VDD=3.
5V,maximum20I/OsusedatthesametimeinoutputatlowlevelwithIOL=8mA,VOL=0.
4VPINTmax=20mA*3.
5V=70mWPIOmax=20*8mA*0.
4V=64mWThisgives:PINTmax=70mWandPIOmax=64mW:PDmax=70+64=134mWThus:PDmax=134mWDocID15274Rev1093/108STM32F105xx,STM32F107xxPackageinformation107UsingthevaluesobtainedinTable61TJmaxiscalculatedasfollows:–ForLQFP100,46°C/WTJmax=115°C+(46°C/W*134mW)=115°C+6.
2°C=121.
2°CThisiswithintherangeofthesuffix7versionparts(–4025°C).
Inthiscase,partsmustbeorderedatleastwiththetemperaturerangesuffix7(seeTable62:Orderinginformationscheme).
Figure49.
LQFP100PDmaxvs.
TAD^s^^WtdΣPartnumberingSTM32F105xx,STM32F107xx94/108DocID15274Rev107PartnumberingForalistofavailableoptions(speed,package,etc.
)orforfurtherinformationonanyaspectofthisdevice,contactyournearestSTsalesoffice.
Table62.
OrderinginformationschemeExample:STM32F105RCT6VxxxTRDevicefamilySTM32=ARM-based32-bitmicrocontrollerProducttypeF=general-purposeDevicesubfamily105=connectivity,USBOTGFS107=connectivity,USBOTGFS&EthernetPincountR=64pinsV=100pinsFlashmemorysize8=64KbytesofFlashmemoryB=128KbytesofFlashmemoryC=256KbytesofFlashmemoryPackageH=BGAT=LQFPTemperaturerange6=Industrialtemperaturerange,–40to85°C.
7=Industrialtemperaturerange,–40to105°C.
SoftwareoptionInternalcodeorBlankOptionsxxx=programmedpartsPackingBlank=trayTR=tapeandreelDocID15274Rev1095/108STM32F105xx,STM32F107xxApplicationblockdiagrams107AppendixAApplicationblockdiagramsA.
1USBOTGFSinterfacesolutionsFigure50.
USBOTGFSdevicemode1.
Usearegulatorifyouwanttobuildabus-powereddevice.
Figure51.
Hostconnection1.
STMPS2141STRneededonlyiftheapplicationhastosupportbus-powereddevices.
53"/4'&ULLSPEEDCORE34-&XX34-&XX53"&ULLSPEEDTRANSCEIVER$053"-ICRO"CONNECTOR$-6"53633(.
0(.
03203206$$)$)$/4'0(9AIB$0$-6"536334OHOST6TO6$$2EGULATOR53"/4'&ULLSPEEDCORE34-&XX34-&XX53"FULLSPEEDLOWSPEEDTRANSCEIVER$053"3TD!
CONNECTOR$-6"53633(.
0(.
0320320)$)$/4'0(9AIB'0)/'0)/)21%.
/62#2FLAG#URRENTLIMITEDPOWERDISTRIBUTIONSWITCH34-033426$$6ApplicationblockdiagramsSTM32F105xx,STM32F107xx96/108DocID15274Rev10Figure52.
OTGconnection(anyprotocol)1.
STMPS2141STRneededonlyiftheapplicationhastosupportbus-powereddevices.
USBOTGFull-speedcoreSTM32F105xx/STM32F107xxUSBfull-speed/low-speedtransceiverDPUSBMicro-ABconnectorDMVBUSVSSHNPHNPSRPSRPIDIDOTGPHYai15655bGPIOGPIO+IRQENCurrent-limitedpowerdistributionswitchSTMPS2141STR(1)IDOVRCRflagVDD5VDocID15274Rev1097/108STM32F105xx,STM32F107xxApplicationblockdiagrams107A.
2EthernetinterfacesolutionsFigure53.
MIImodeusinga25MHzcrystal1.
HCLKmustbegreaterthan25MHz.
2.
PulsepersecondwhenusingIEEE1588PTP,optionalsignal.
Figure54.
RMIIwitha50MHzoscillator1.
HCLKmustbegreaterthan25MHz.
MCUEthernetMAC10/100EthernetPHY10/100PLLHCLKXT1PHY_CLK25MHzMII_RX_CLKMII_RXD[3:0]MII_RX_DVMII_RX_ERMII_TX_CLKMII_TX_ENMII_TXD[3:0]MII_CRSMII_COLMDIOMDCHCLK(1)PPS_OUT(2)XTAL25MHzSTM32F107xxOSCTIM2TimestampcomparatorTimerinputtriggerIEEE1588PTPMII=15pinsMII+MDC=17pinsai15656MCUEthernetMAC10/100EthernetPHY10/100PLLHCLKXT1PHY_CLK50MHzRMII_RXD[1:0]RMII_CRX_DVRMII_REF_CLKRMII_TX_ENRMII_TXD[1:0]MDIOMDCHCLK(1)STM32F107xxOSC50MHzTIM2TimestampcomparatorTimerinputtriggerIEEE1588PTPRMII=7pinsRMII+MDC=9pinsai15657/2or/20synchronous2.
5or25MHz50MHz50MHzApplicationblockdiagramsSTM32F105xx,STM32F107xx98/108DocID15274Rev10Figure55.
RMIIwitha25MHzcrystalandPHYwithPLL1.
HCLKmustbegreaterthan25MHz.
Figure56.
RMIIwitha25MHzcrystal1.
TheNSDP83848isrecommendedastheinputjitterrequirementofthisPHY.
ItiscompliantwiththeoutputjitterspecificationoftheMCU.
MCUEthernetMAC10/100EthernetPHY10/100PLLHCLKXT1PHY_CLK25MHzRMII_RXD[1:0]RMII_CRX_DVRMII_REF_CLKRMII_TX_ENRMII_TXD[1:0]MDIOMDCHCLK(1)STM32F107xxTIM2TimestampcomparatorTimerinputtriggerIEEE1588PTPRMII=7pinsRMII+MDC=9pinsai15658/2or/20synchronous2.
5or25MHz50MHzXTAL25MHzOSCPLLREF_CLKMCUEthernetMAC10/100EthernetPHY10/100PLLSXT1/XT2RMII_RXD[1:0]RMII_CRX_DVRMII_REF_CLKRMII_TX_ENRMII_TXD[1:0]MDIOMDCHCLKSTM32F107xxTIM2TimestampcomparatorTimerinputtriggerIEEE1588PTPRMII=7pinsRMII+MDC=9pinsai15659b50MHzXTAL25MHzOSCNSDP83848(1)50MHz50MHzDocID15274Rev1099/108STM32F105xx,STM32F107xxApplicationblockdiagrams107A.
3CompleteaudioplayersolutionsTwosolutionsareoffered,illustratedinFigure57andFigure58.
Figure57showsstoragemediatoaudioDAC/amplifierstreamingusingasoftwareCodec.
ThissolutionimplementsanaudiocrystaltoprovideaudioclassI2Saccuracyonthemasterclock(0.
5%errormaximum,seetheSerialperipheralinterfacesectioninthereferencemanualfordetails).
Figure57.
Completeaudioplayersolution1Figure58showsstoragemediatoaudioCodec/amplifierstreamingwithSOFsynchronizationofinput/outputaudiostreamingusingahardwareCodec.
Figure58.
Completeaudioplayersolution2Cortex-M3core72MHzOTG(hostmode)+PHYSPISPIGPIOI2SXTAL14.
7456MHzUSBMass-storagedeviceMMC/SDCardLCDtouchscreenControlbuttonsDAC+AudioampliFileSystemProgrammemoryAudioCODECUserapplicationSTM32F105/STM32F107ai15660Cortex-M3core72MHzOTG+PHYSPISPIGPIOI2SXTAL14.
7456MHzUSBMass-storagedeviceMMC/SDCardLCDtouchscreenControlbuttonsAudioampliFileSystemProgrammemoryAudioCODECUserapplicationSTM32F105/STM32F107ai15661SOFSOFsynchronizationofinput/outputaudiostreamingApplicationblockdiagramsSTM32F105xx,STM32F107xx100/108DocID15274Rev10A.
4USBOTGFSinterface+Ethernet/I2SinterfacesolutionsWiththeclocktreeimplementedontheSTM32F107xx,onlyonecrystalisrequiredtoworkwithboththeUSB(host/device/OTG)andtheEthernet(MII/RMII)interfaces.
Figure59illustratethesolution.
Figure59.
USBO44TGFS+EthernetsolutionWiththeclocktreeimplem1entedontheSTM32F107xx,onlyonecrystalisrequiredtoworkwithboththeUSB(host/device/OTG)andtheI2S(Audio)interfaces.
Figure60illustratethesolution.
Figure60.
USBOTGFS+I2S(Audio)solution34-&-#50,,-5,X0,,-5,X0,,-5,X%THERNET0(9)33EL3EL-(Z84!
,/3#$IVBY-#/393#,+5PTO-(Z0,,6#/X0,,#,+53"0(9/4'-(Z$IVBY$IVBY5PTO-(ZACCURACY-3634-&34-&-#50,,-5,X0,,-5,X0,,-5,X%THERNET0(9)33EL-(Z84!
,/3#$IVBY-#/393#,+5PTO-(Z0,,6#/X0,,#,+53"0(9/4'-(Z$IVBY$IVBY5PTO-(Z,ESSTHANACCURACYACCURACY-#,+3#,+ON-#,+AND3#,+0,,6#/X0,,#,+-36DocID15274Rev10101/108STM32F105xx,STM32F107xxApplicationblockdiagrams107Table64givetheIDDrunmodevaluesthatcorrespondtotheconditionsspecifiedinTable63.
Table63.
PLLconfigurationsApplicationCrystalvalueinMHz(XT1)PREDIV2PLL2MULPLLSRCPREDIV1PLLMULUSBprescaler(PLLVCOoutput)PLL3MULI2SnclockinputMCO(mainclockoutput)Ethernetonly25/5PLL2ONx8PLL2/5PLLONx9NAPLL3ONx10NAXT1(MII)PLL3(RMII)Ethernet+OTG25/5PLL2ONx8PLL2/5PLLONx9/3PLL3ONx10NAXT1(MII)PLL3(RMII)Ethernet+OTG+basicaudio25/5PLL2ONx8PLL2/5PLLONx9/3PLL3ONx10PLLXT1(MII)PLL3(RMII)Ethernet+OTG+AudioclassI2S(1)14.
7456/4PLL2ONx12PLL2/4PLLONx6.
5/3PLL3ONx20PLL3VCOOutNAETHPHYmustuseitsowncrystalOTGonly8NAPLL2OFFXT1/1PLLONx9/3PLL3OFFNANAOTG+basicaudio8NAPLL2OFFXT1/1PLLONx9/3PLL3OFFPLLNAOTG+AudioclassI2S(1)14.
7456/4PLL2ONx12PLL2/4PLLONx6.
5/3PLL3ONx20PLL3VCOOutNAAudioclassI2Sonly(1)14.
7456/4PLL2ONx12PLL2/4PLLONx6.
5NAPLL3ONx20PLL3VCOoutNA1.
SYSCLKissettobeat72MHzexceptinthiscasewhereSYSCLKisat71.
88MHz.
ApplicationblockdiagramsSTM32F105xx,STM32F107xx102/108DocID15274Rev10Table64.
ApplicativecurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlashSymbolparameterConditions(1)1.
VDD=3.
3V.
Typ(2)2.
Basedoncharacterization,nottestedinproduction.
Max(2)Unit85°C105°CIDDSupplycurrentinrunmodeExternalclock,allperipheralsenabledexceptethernet,HSE=8MHz,fHCLK=72MHz,noMCO576364mAExternalclock,allperipheralsenabledexceptethernet,HSE=14.
74MHz,fHCLK=72MHz,noMCO60.
56768Externalclock,allperipheralsenabledexceptOTG,HSE=25MHz,fHCLK=72MHz,MCO=25MHz5360.
761Externalclock,allperipheralsenabled,HSE=25MHz,fHCLK=72MHz,MCO=25MHz60.
565.
566Externalclock,allperipheralsenabled,HSE=25MHz,fHCLK=72MHz,MCO=50MHz6469.
770Externalclock,allperipheralsenabled,HSE=50MHz(3),fHCLK=72MHz,noMCO3.
Externaloscillator.
62.
567.
568Externalclock,onlyOTGenabled,HSE=8MHz,fHCLK=48MHz,noMCO26.
7NoneNoneExternalclock,onlyethernetenabled,HSE=25MHz,fHCLK=25MHz,MCO=25MHz14.
3NoneNoneDocID15274Rev10103/108STM32F105xx,STM32F107xxRevisionhistory1078RevisionhistoryTable65.
DocumentrevisionhistoryDateRevisionChanges18-Dec-20081Initialrelease.
20-Feb-20092I/Oinformationclarifiedonpage1.
Figure4:STM32F105xxxandSTM32F107xxxconnectivitylineBGA100ballouttopviewcorrected.
Section2.
3.
8:Bootmodesupdated.
PB4,PB13,PB14,PB15,PB3/TRACESWOmovedfromDefaultcolumntoRemapcolumn,plussmalladditionalchangesinTable5:Pindefinitions.
ConsumptionvaluesmodifiedinSection5.
3.
5:Supplycurrentcharacteristics.
NotemodifiedinTable13:MaximumcurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlashandTable15:MaximumcurrentconsumptioninSleepmode,coderunningfromFlashorRAM.
Table20:High-speedexternaluserclockcharacteristicsandTable21:Low-speedexternaluserclockcharacteristicsmodified.
Table27:PLLcharacteristicsmodifiedandTable28:PLL2andPLL3characteristicsadded.
RevisionhistorySTM32F105xx,STM32F107xx104/108DocID15274Rev1019-Jun-20093Section2.
3.
8:BootmodesandSection2.
3.
20:EthernetMACinterfacewithdedicatedDMAandIEEE1588supportupdated.
Section2.
3.
24:Remapcapabilityadded.
Figure1:STM32F105xxandSTM32F107xxconnectivitylineblockdiagramandFigure5:Memorymapupdated.
InTable5:Pindefinitions:–I2S3_WS,I2S3_CKandI2S3_SDdefaultalternatefunctionsadded–smallchangesinsignalnames–Note6modified–ETH_MII_PPS_OUTandETH_RMII_PPS_OUTreplacedbyETH_PPS_OUT–ETH_MII_MDIOandETH_RMII_MDIOreplacedbyETH_MDIO–ETH_MII_MDCandETH_RMII_MDCreplacedbyETH_MDCFigures:TypicalcurrentconsumptioninRunmodeversusfrequency(at3.
6V)-codewithdataprocessingrunningfromRAM,peripheralsenabledandTypicalcurrentconsumptioninRunmodeversusfrequency(at3.
6V)-codewithdataprocessingrunningfromRAM,peripheralsdisabledremoved.
Table13:MaximumcurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlash,Table14:MaximumcurrentconsumptioninRunmode,codewithdataprocessingrunningfromRAMandTable15:MaximumcurrentconsumptioninSleepmode,coderunningfromFlashorRAMaretobedetermined.
Figure12andFigure13showtypicalcurves.
PLL1renamedtoPLL.
IDDsupplycurrentinStopmodemodifiedinTable16:TypicalandmaximumcurrentconsumptionsinStopandStandbymodes.
Figure11:TypicalcurrentconsumptioninStopmodewithregulatorinRunmodeversustemperatureatdifferentVDDvalues,Figure13:TypicalcurrentconsumptioninStandbymodeversustemperatureatdifferentVDDvaluesandFigure13:TypicalcurrentconsumptioninStandbymodeversustemperatureatdifferentVDDvaluesupdated.
Table17:TypicalcurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlash,Table18:TypicalcurrentconsumptioninSleepmode,coderunningfromFlashorRAMandTable19:Peripheralcurrentconsumptionupdated.
fHSE_extmodifiedinTable20:High-speedexternaluserclockcharacteristics.
MinPLLinputclock(fPLL_IN),fPLL_OUTminandfPLL_VCOminmodifiedinTable27:PLLcharacteristics.
ACCHSImaxvaluesmodifiedinTable24:HSIoscillatorcharacteristics.
Table31:EMScharacteristicsandTable32:EMIcharacteristicsupdated.
Table43:SPIcharacteristicsupdated.
Modified:Figure28:I2Sslavetimingdiagram(Philipsprotocol)(1),Figure29:I2Smastertimingdiagram(Philipsprotocol)(1)andFigure31:EthernetSMItimingdiagram.
BGA100packageremoved.
Section6.
4:Thermalcharacteristicsadded.
Smalltextchanges.
Table65.
Documentrevisionhistory(continued)DateRevisionChangesDocID15274Rev10105/108STM32F105xx,STM32F107xxRevisionhistory10714-Sep-20094DocumentstatuspromotedfromPreliminarydatatofulldatasheet.
NumberofDACscorrectedinTable3:STM32F105xxandSTM32F107xxfamilyversusSTM32F103xxfamily.
Note5addedinTable5:Pindefinitions.
VRERINTandTCoeffaddedtoTable12:Embeddedinternalreferencevoltage.
ValuesaddedtoTable13:MaximumcurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlash,Table14:MaximumcurrentconsumptioninRunmode,codewithdataprocessingrunningfromRAMandTable15:MaximumcurrentconsumptioninSleepmode,coderunningfromFlashorRAM.
TypicalIDD_VBATvalueaddedinTable16:TypicalandmaximumcurrentconsumptionsinStopandStandbymodes.
Figure10:TypicalcurrentconsumptiononVBATwithRTConvs.
temperatureatdifferentVBATvaluesadded.
ValuesmodifiedinTable17:TypicalcurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlashandTable18:TypicalcurrentconsumptioninSleepmode,coderunningfromFlashorRAM.
fHSE_extminmodifiedinTable20:High-speedexternaluserclockcharacteristics.
CL1andCL2replacedbyCinTable22:HSE3-25MHzoscillatorcharacteristicsandTable23:LSEoscillatorcharacteristics(fLSE=32.
768kHz),notesmodifiedandmovedbelowthetables.
Note1modifiedbelowFigure16:Typicalapplicationwithan8MHzcrystal.
ConditionsremovedfromTable26:Low-powermodewakeuptimings.
StandardsmodifiedinSection5.
3.
10:EMCcharacteristicsonpage54,conditionsmodifiedinTable31:EMScharacteristics.
JittermaximumvaluesaddedtoTable27:PLLcharacteristicsandTable28:PLL2andPLL3characteristics.
RPUandRPDmodifiedinTable36:I/Ostaticcharacteristics.
ConditionaddedforVNF(NRST)parameterinTable39:NRSTpincharacteristics.
NoteremovedandRPD,RPUvaluesaddedinTable46:USBOTGFSDCelectricalcharacteristics.
Table48:EthernetDCelectricalcharacteristicsadded.
ParametervaluesaddedtoTable49:Dynamiccharacteristics:EthernetMACsignalsforSMI,Table50:Dynamiccharacteristics:EthernetMACsignalsforRMIIandTable51:Dynamiccharacteristics:EthernetMACsignalsforMII.
CADCandRAINparametersmodifiedinTable52:ADCcharacteristics.
RAINmaxvaluesmodifiedinTable53:RAINmaxforfADC=14MHz.
Table56:DACcharacteristicsmodified.
Figure38:12-bitbuffered/non-bufferedDACadded.
Table64:ApplicativecurrentconsumptioninRunmode,codewithdataprocessingrunningfromFlashadded.
Smalltextchanges.
Table65.
Documentrevisionhistory(continued)DateRevisionChangesRevisionhistorySTM32F105xx,STM32F107xx106/108DocID15274Rev1011-May-20105AddedBGApackage.
Table5:Pindefinitions:ETH_RMII_RXD0andETH_RMII_RXD1addedinremapcolumnforPD9andPD10,respectively.
NoteaddedtoETH_MII_RX_DV,ETH_MII_RXD0,ETH_MII_RXD1,ETH_MII_RXD2andETH_MII_RXD3UpdatedTable36:I/Ostaticcharacteristicsonpage57AddedFigure18:StandardI/Oinputcharacteristics-CMOSporttoFigure21:5VtolerantI/Oinputcharacteristics-TTLportUpdatedTable43:SPIcharacteristicsonpage66.
UpdatedTable44:I2Scharacteristicsonpage69.
UpdatedTable48:EthernetDCelectricalcharacteristicsonpage72.
UpdatedTable49:Dynamiccharacteristics:EthernetMACsignalsforSMIonpage72.
UpdatedTable50:Dynamiccharacteristics:EthernetMACsignalsforRMIIonpage73UpdatedFigure59:USBO44TGFS+Ethernetsolutiononpage100.
UpdatedFigure60:USBOTGFS+I2S(Audio)solutiononpage10001-Aug-20116ChangedSRAMsizeto64KBonallparts.
UpdatedPD0andPD1descriptioninTable5:Pindefinitionsonpage27UpdatedfootnotesbelowTable6:Voltagecharacteristicsonpage36andTable7:Currentcharacteristicsonpage36UpdatedtwmininTable20:High-speedexternaluserclockcharacteristicsonpage47UpdatedstartuptimeinTable23:LSEoscillatorcharacteristics(fLSE=32.
768kHz)onpage50AddedSection5.
3.
12:I/Ocurrentinjectioncharacteristicsonpage56UpdatedTable36:I/Ostaticcharacteristicsonpage57AddInternacodeVtoTable62:Orderinginformationschemeonpage9406-Mar-20147Addeda"Packing"entrytoTable62:Orderinginformationschemeincluding"Blank=tray"and"TR=Tapeandreel".
Referenced4Figures:Figure41,Figure49,Figure59andFigure60.
Updatedthe"Package"linewith"BGA100"inTable2:STM32F105xxandSTM32F107xxfeaturesandperipheralcounts.
Table65.
Documentrevisionhistory(continued)DateRevisionChangesDocID15274Rev10107/108STM32F105xx,STM32F107xxRevisionhistory10706-Mar-20158UpdatedTable40:LFBGA100–100-balllowprofilefinepitchballgridarray,10x10mm,0.
8mmpitch,packagemechanicaldata,Table59:LQPF100-100-pin,14x14mmlow-profilequadflatpackagemechanicaldataandTable60:LQFP64–10x10mm64pinlow-profilequadflatpackagemechanicaldataUpdatedFigure14:High-speedexternalclocksourceACtimingdiagram;Figure39:LFBGA100-10x10mmlowprofilefinepitchballgridarraypackageoutline,Figure43:LQFP100–14x14mm100pinlow-profilequadflatpackageoutline,Figure44:LQFP100-100-pin,14x14mmlow-profilequadflatrecommendedfootprint,Figure46:LQFP64–10x10mm64pinlow-profilequadflatpackageoutlineandFigure47:LQFP64-64-pin,10x10mmlow-profilequadflatrecommendedfootprintAddedFigure45:LQFP100markingexample(packagetopview),Figure48:LQFP64markingexample(packagetopview)3-Sept-20159Updated:–Table19:Peripheralcurrentconsumption–Figure44:LQFP100-100-pin,14x14mmlow-profilequadflatrecommendedfootprint–Table58:LFBGA100recommendedPCBdesignrules(0.
8mmpitchBGA)22-Mar-201710Updated:–Table5:Pindefinitions–Section6:PackageinformationAdded:–Figure42:LFBGA100markingexample(packagetopview)Table65.
Documentrevisionhistory(continued)DateRevisionChangesSTM32F105xx,STM32F107xx108/108DocID15274Rev10IMPORTANTNOTICE–PLEASEREADCAREFULLYSTMicroelectronicsNVanditssubsidiaries("ST")reservetherighttomakechanges,corrections,enhancements,modifications,andimprovementstoSTproductsand/ortothisdocumentatanytimewithoutnotice.
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