Thresholdflash10

DP83815DP8381510/100Mb/sIntegratedPCIEthernetMediaAccessControllerandPhysicalLayer(MacPhyter)LiteratureNumber:SNLS059EDP8381510/100Mb/sIntegratedPCIEthernetMediaAccessControllerandPhysicalLayer(MacPhyter)2005NationalSemiconductorCorporationwww.
national.
comSeptember2005DP8381510/100Mb/sIntegratedPCIEthernetMediaAccessControllerandPhysicalLayer(MacPhyter)GeneralDescriptionDP83815isasingle-chip10/100Mb/sEthernetControllerforthePCIbus.
Itistargetedatlow-cost,highvolumePCmotherboards,adaptercards,andembeddedsystems.
TheDP83815fullyimplementstheV2.
233MHzPCIbusinterfaceforhostcommunicationswithpowermanagementsupport.
Packetdescriptorsanddataaretransferredviabus-mastering,reducingtheburdenonthehostCPU.
TheDP83815cansupportfullduplex10/100Mb/stransmissionandreception,withminimuminterframegap.
TheDP83815deviceisanintegrationofanenhancedversionoftheNationalSemiconductorPCIMAC/BIU(MediaAccessController/BusInterfaceUnit)anda3.
3VCMOSphysicallayerinterface.
Features—IEEE802.
3Compliant,PCIV2.
2MAC/BIUsupportstraditionaldataratesof10Mb/sEthernetand100Mb/sFastEthernet(viainternalphy)—Busmaster-burstsizesofupto128dwords(512bytes)—BIUcompliantwithPC97andPC98HardwareDesignGuides,PC99HardwareDesignGuidedraft,ACPIv1.
0,PCIPowerManagementSpecificationv1.
1,OnNowDeviceClassPowerManagementReferenceSpecification-NetworkDeviceClassv1.
0a—WakeonLAN(WOL)supportcompliantwithPC98,PC99,SecureOn,andOnNow,includingdirectedpackets,MagicPacket,VLANpackets,ARPpackets,patternmatchpackets,andPhystatuschange—ClkrunfunctionforPCIMobileDesignGuide—VirtualLAN(VLAN)andlongframesupport—SupportforIEEE802.
3xFullduplexflowcontrol—ExtremelyflexibleRxpacketfiltrationincluding:singleaddressperfectfilterwithMSbmasking,broadcast,512entrymulticast/unicasthashtable,deeppacketpatternmatchingforupto4uniquepatterns—StatisticsgatheredforsupportofRFC1213(MIBII),RFC1398(Ether-likeMIB),IEEE802.
3LME,reducingCPUoverheadformanagement—Internal2KBTransmitand2KBReceivedataFIFOs—SerialEEPROMportwithauto-loadofconfigurationdatafromEEPROMatpower-on—Flash/PROMinterfaceforremotebootsupport—FullyintegratedIEEE802.
3/802.
3u3.
3VCMOSphysicallayer—IEEE802.
310BASE-Ttransceiverwithintegratedfilters—IEEE802.
3u100BASE-TXtransceiver—FullyintegratedANSIX3.
263compliantTP-PMDphysicalsublayerwithadaptiveequalizationandBaselineWandercompensation—IEEE802.
3uAuto-Negotiation-advertisedfeaturesconfigurableviaEEPROM—FullDuplexsupportfor10and100Mb/sdatarates—Single25MHzreferenceclock—144-pinLQFPand160-pinLBGApackages—Lowpower3.
3VCMOSdesignwithtypicalconsumptionof561mWoperating,380mWduringWOLmode,33mWsleepmode—IEEE802.
3uMIIforconnectingalternativeexternalPhysicalLayerDevicesSystemDiagramPCIBusDP83815EEPROMIsolation10/100TwistedPairBIOSROM(optional)(optional)MagicPacketisatrademarkofAdvancedMicroDevices,Inc.
2www.
national.
comDP83815TableofContents1.
0ConnectionDiagram41.
1144LQFPPackage(VNG)41.
2160pinLBGAPackage(UJB)52.
0PinDescription63.
0FunctionalDescription133.
1MAC/BIU143.
1.
1PCIBusInterface143.
1.
2TxMAC153.
1.
3RxMAC153.
2BufferManagement153.
2.
1TxBufferManager153.
2.
2RxBufferManager153.
2.
3PacketRecognition153.
2.
4MIB163.
3InterfaceDefinitions163.
3.
1PCISystemBus163.
3.
2BootPROM163.
3.
3EEPROM163.
3.
4Clock163.
4PhysicalLayer183.
4.
1Auto-Negotiation183.
4.
2Auto-NegotiationRegisterControl183.
4.
3Auto-NegotiationParallelDetection183.
4.
4Auto-NegotiationRestart193.
4.
5EnablingAuto-NegotiationviaSoftware193.
4.
6Auto-NegotiationCompleteTime193.
5LEDInterfaces193.
6HalfDuplexvs.
FullDuplex203.
7PhyLoopback203.
8StatusInformation203.
9100BASE-TXTRANSMITTER203.
9.
1Code-groupEncodingandInjection213.
9.
2Scrambler213.
9.
3NRZtoNRZIEncoder223.
9.
4BinarytoMLT-3Convertor/CommonDriver.
.
.
.
223.
10100BASE-TXReceiver233.
10.
1InputandBaseLineWanderCompensation.
.
.
.
233.
10.
2SignalDetect233.
10.
3DigitalAdaptiveEqualization253.
10.
4LineQualityMonitor263.
10.
5MLT-3toNRZIDecoder263.
10.
6ClockRecoveryModule273.
10.
7NRZItoNRZ273.
10.
8SerialtoParallel273.
10.
9De-scrambler273.
10.
10Code-groupAlignment273.
10.
114B/5BDecoder273.
10.
12100BASE-TXLinkIntegrityMonitor273.
10.
13BadSSDDetection273.
1110BASE-TTransceiverModule283.
11.
1OperationalModes283.
11.
2SmartSquelch283.
11.
3CollisionDetection283.
11.
4NormalLinkPulseDetection/Generation283.
11.
5JabberFunction293.
11.
6AutomaticLinkPolarityDetection293.
11.
710BASE-TInternalLoopback293.
11.
8TransmitandReceiveFiltering293.
11.
9Transmitter293.
11.
10Receiver293.
11.
11FarEndFaultIndication293.
12802.
3uMII293.
12.
1MIIAccessConfiguration293.
12.
2MIISerialManagement293.
12.
3MIISerialManagementAccess303.
12.
4SerialManagementAccessProtocol303.
12.
5Nibble-wideMIIDataInterface303.
12.
6CollisionDetection313.
12.
7CarrierSense314.
0RegisterSet324.
1ConfigurationRegisters324.
1.
1ConfigurationIdentificationRegister324.
1.
2ConfigurationCommandandStatusRegister.
.
.
334.
1.
3ConfigurationRevisionIDRegister344.
1.
4ConfigurationLatencyTimerRegister354.
1.
5ConfigurationI/OBaseAddressRegister354.
1.
6ConfigurationMemoryAddressRegister364.
1.
7ConfigurationSubsystemIdentificationRegister.
364.
1.
8BootROMConfigurationRegister374.
1.
9CapabilitiesPointerRegister374.
1.
10ConfigurationInterruptSelectRegister384.
1.
11PowerManagementCapabilitiesRegister384.
1.
12PowerManagementControlandStatusRegister394.
2OperationalRegisters404.
2.
1CommandRegister414.
2.
2ConfigurationandMediaStatusRegister424.
2.
3EEPROMAccessRegister444.
2.
4EEPROMMap444.
2.
5PCITestControlRegister454.
2.
6InterruptStatusRegister464.
2.
7InterruptMaskRegister474.
2.
8InterruptEnableRegister494.
2.
9TransmitDescriptorPointerRegister494.
2.
10TransmitConfigurationRegister504.
2.
11ReceiveDescriptorPointerRegister514.
2.
12ReceiveConfigurationRegister524.
2.
13CLKRUNControl/StatusRegister534.
2.
14WakeCommand/StatusRegister554.
2.
15PauseControl/StatusRegister574.
2.
16ReceiveFilter/MatchControlRegister584.
2.
17ReceiveFilter/MatchDataRegister594.
2.
18ReceiveFilterLogic604.
2.
19BootROMAddressRegister644.
2.
20BootROMDataRegister644.
2.
21SiliconRevisionRegister644.
2.
22ManagementInformationBaseControlRegister654.
2.
23ManagementInformationBaseRegisters664.
3InternalPHYRegisters674.
3.
1BasicModeControlRegister674.
3.
2BasicModeStatusRegister684.
3.
3PHYIdentifierRegister#1694.
3.
4PHYIdentifierRegister#2694.
3.
5Auto-NegotiationAdvertisementRegister694.
3.
6Auto-NegotiationLinkPartnerAbilityRegister.
.
.
704.
3.
7Auto-NegotiateExpansionRegister714.
3.
8Auto-NegotiationNextPageTransmitRegister.
.
714.
3.
9PHYStatusRegister724.
3.
10MIIInterruptControlRegister744.
3.
11MIIInterruptStatusandMisc.
ControlRegister.
744.
3.
12FalseCarrierSenseCounterRegister754.
3.
13ReceiverErrorCounterRegister754.
3.
14100Mb/sPCSConfigurationandStatusRegister754.
3.
15PHYControlRegister764.
3.
1610BASE-TStatus/ControlRegister774.
4RecommendedRegistersConfiguration.
785.
0BufferManagement795.
1Overview795.
1.
1DescriptorFormat793www.
national.
comDP838155.
1.
2SingleDescriptorPackets815.
1.
3MultipleDescriptorPackets825.
1.
4DescriptorLists825.
2TransmitArchitecture835.
2.
1TransmitStateMachine835.
2.
2TransmitDataFlow855.
3ReceiveArchitecture865.
3.
1ReceiveStateMachine865.
3.
2ReceiveDataFlow886.
0PowerManagementandWake-On-LAN.
.
896.
1Introduction896.
2Definitions(forthisdocumentonly)896.
3PacketFiltering896.
4PowerManagement896.
4.
1D0State906.
4.
2D1State906.
4.
3D2State906.
4.
4D3hotState906.
4.
5D3coldState906.
5Wake-On-LAN(WOL)Mode906.
5.
1EnteringWOLMode906.
5.
2WakeEvents916.
5.
3ExitingWOLMode916.
6SleepMode916.
6.
1EnteringSleepMode916.
6.
2ExitingSleepMode916.
7PinConfigurationforPowerManagement917.
0DCandACSpecifications927.
1DCSpecifications927.
2ACSpecifications937.
2.
1PCIClockTiming937.
2.
2X1ClockTiming937.
2.
3PowerOnReset(PCIActive)947.
2.
4NonPowerOnReset947.
2.
5PORPCIInactive957.
2.
6PCIBusCycles967.
2.
7EEPROMAuto-Load1017.
2.
8BootPROM/FLASH1027.
2.
9100BASE-TXTransmit1037.
2.
1010BASE-TTransmitEndofPacket1047.
2.
1110Mb/sJabberTiming1047.
2.
1210BASE-TNormalLinkPulse1057.
2.
13Auto-NegotiationFastLinkPulse(FLP)1057.
2.
14MediaIndependentInterface(MII)106ListofFiguresFigure3-1DP83815FunctionalBlockDiagram13Figure3-2MAC/BIUFunctionalBlockDiagram14Figure3-3EthernetPacketFormat.
16Figure3-4DSPPhysicalLayerBlockDiagram.
17Figure3-5LEDLoadingExample19Figure3-6100BASE-TXTransmitBlockDiagram21Figure3-7BinarytoMLT-3conversion.
22Figure3-8100M/bsReceiveBlockDiagram24Figure3-9100BASE-TXBLWEventDiagram25Figure3-10EIA/TIAAttenuationvs.
Frequencyfor0,50,100,130&150metersofCATVcable26Figure3-11MLT-3SignalMeasuredatAIIafter0metersofCATVcable.
26Figure3-12MLT-3SignalMeasuredatAIIafter50metersofCATVcable.
26Figure3-13MLT-3SignalMeasuredatAIIafter100metersofCATVcable.
26Figure3-1410BASE-TTwistedPairSmartSquelchOperation28Figure3-15TypicalMDC/MDIOReadOperation30Figure3-16TypicalMDC/MDIOWriteOperation31Figure4-1PatternBufferMemory-180hwords(word=18bits)61Figure4-2HashTableMemory-40hbytesaddressedonwordboundaries63Figure5-1SingleDescriptorPackets81Figure5-2MultipleDescriptorPackets82Figure5-3ListandRingDescriptorOrganization82Figure5-4TransmitArchitecture.
83Figure5-5TransmitStateDiagram.
84Figure5-6ReceiveArchitecture86Figure5-7ReceiveStateDiagram88ListofTablesTable3-14B5BCode-GroupEncoding/Decoding22Table3-2TypicalMDIOFrameFormat30Table4-1ConfigurationRegisterMap32Table4-2OperationalRegisterMap.
40Table4-3MIBRegisters66Table5-1DP83815DescriptorFormat79Table5-2cmdstsCommonBitDefinitions79Table5-3TransmitStatusBitDefinitions80Table5-4ReceiveStatusBitDefinitions81Table5-5TransmitStateTables.
84Table5-6ReceiveStateTables87Table6-1PowerManagementModes89Table6-2PMPinConfiguration914www.
national.
comDP838151.
0ConnectionDiagram1.
1144LQFPPackage(VNG)OrderNumberDP83815DVNGSeeNSPackageNumberVNG144A1211221231241251261271281291301311329998979695949392919089888786858483828180797877767574736665646362616059585756555453525150494847464544434241123456789101112131415161718192021222324252627283031323329IdentificationPin137383940120119118117116115114113112110109111DEVSELNTRDYNIRDYNFRAMENCBEN2AD16AD17AD18STOPNPERRNSERRNPARCBEN1AD15AD14AD13AD12AD11AD10AD9PCIVSS4AD8AD19AD20AD21AD22AD23IDSELPCIVSS2PCIVDD3VSSIO4PCIVDD4VDDIO4PCIVSS3PCIVDD2CBEN3AD24AD25AD26CBEN0MACVSS1MACVDD1RESERVEDVREFPCIVDD1AD29AD31PCIVSS1REQNGNTNRSTNINTANAD28PCICLKAD30PMEN/CLKRUNNTXIOVSS2TXIOVSS1TPTDPTPTDMNCRXAVDD2RXAVSS2TPRDPTPRDMSUBGND2AD27AD7AD6AD5PCIVSS5MA1/LED10NMA2/LED100NMA3/EEDIMA4/EECLKMA5MWRNMD4/EEDOMD3EESELAD0AD1AD2AD3AD4MD0MCSNMD1/CFGDISNMD2MD5MD6MD7MA0/LEDACTNPCIVDD5VSSIO2VDDIO2MACVSS2MACVDD2VDDIO5VSSIO5MDIOMDCRXCLKRXD0/MA6RXD1/MA7RXD2/MA8RXD3/MA9RXOERXER/MA10RXDV/MA11TXD3/MA15COL/MA16CRSTXENTXCLKTXD2/MA14TXD1/MA13TXD0/MA12VSSIO3VDDIO3VSSIO1VDDIO1X2X1DP83815SUBGND3PHYVSS1PHYVDD1NC3VAUX363534676869707172100101102103104105106107108144143142141140139138137136135134133RXAVSS1RXAVDD1PWRGOODMRDNTXDVDDFXVDDFXVSSPHYVSS2PHYVDD2SUBGND1RESERVEDNCNCRESERVEDTXDVSS5www.
national.
com1.
0ConnectionDiagram(Continued)DP838151.
2160pinLBGAPackage(UJB)TopViewOrderNumberDP83815DUJBSeeNSPackageNumberUJB160AIdentificationPinA1ABCDEFGHJKLMNP1234567891011121314(MarkedonTop)6www.
national.
comDP838152.
0PinDescriptionPCIBusInterfaceSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionAD[31-0]66,67,68,70,71,72,73,74,78,79,81,82,83,86,87,88,101,102,104,105,106,108,109,110,112,113,115,116,118,119,120,121K3,K2,K4,L3,L2,M1,N3,P3,L4N5,M5,L5,N6,L6,N7,P7,N10,L10,M11,N11,P12,N12,M13,M14,L12,L14,K13,K14,K11,J13,J14,J12I/OAddressandData:Multiplexedaddressanddatabus.
Asabusmaster,theDP83815willdriveaddressduringthefirstbusphase.
Duringsubsequentphases,theDP83815willeitherreadorwritedataexpectingthetargettoincrementitsaddresspointer.
Asabustarget,theDP83815willdecodeeachaddressonthebusandrespondifitisthetargetbeingaddressed.
CBEN[3-0]75,89,100,111N4,L7,M10,L13I/OBusCommand/ByteEnable:Duringtheaddressphasethesesignalsdefinethe"buscommand"orthetypeofbustransactionthatwilltakeplace.
Duringthedataphasethesepinsindicatewhichbytelanescontainvaliddata.
CBEN[0]appliestobyte0(bits7-0)andCBEN[3]appliestobyte3(bits31-24)intheLittleEndianMode.
InBigEndianMode,CBEN[3]appliestobyte0(bits31-24)andCBEN[0]appliestobyte3(bits7-0).
PCICLK60H4IClock:ThisPCIBusclockprovidestimingforallbusphases.
Therisingedgedefinesthestartofeachphase.
Theclockfrequencyrangesfrom0to33MHz.
DEVSELN95P9I/ODeviceSelect:Asabusmaster,theDP83815samplesthissignaltoinsurethatthedestinationaddressforthedatatransferisrecognizedbyaPCItarget.
Asatarget,theDP83815assertsthissignallowwhenitrecognizesitsaddressafterFRAMENisasserted.
FRAMEN91M7I/OFrame:Asabusmaster,thissignalisassertedlowtoindicatethebeginninganddurationofabustransaction.
Datatransfertakesplacewhenthissignalisasserted.
Itisde-assertedbeforethetransactionisinitsfinalphase.
Asatarget,thedevicemonitorsthissignalbeforedecodingtheaddresstocheckifthecurrenttransactionisaddressedtoit.
GNTN63J2IGrant:ThissignalisassertedlowtoindicatetotheDP83815thatithasbeengrantedownershipofthebusbythecentralarbiter.
ThisinputisusedwhentheDP83815isactingasabusmaster.
IDSEL76M4IInitializationDeviceSelect:ThispinissampledbytheDP83815toidentifywhenconfigurationreadandwriteaccessesareintendedforit.
INTAN61J1OInterruptA:ThissignalisassertedlowwhenaninterruptconditionoccursasdefinedintheInterruptStatusRegister,InterruptMask,andInterruptEnableregisters.
IRDYN92P8I/OInitiatorReady:Asabusmaster,thissignalwillbeassertedlowwhentheDP83815isreadytocompletethecurrentdataphasetransaction.
ThissignalisusedinconjunctionwiththeTRYDNsignal.
DatatransactiontakesplaceattherisingedgeofPCICLKwhenbothIRDYNandTRDYNareassertedlow.
Asatarget,thissignalindicatesthatthemasterhasputthedataonthebus.
PAR99P10I/OParity:ThissignalindicatesevenparityacrossAD[31-0]andCBEN[3-0]includingthePARpin.
Asamaster,PARisassertedduringaddressandwritedataphases.
Asatarget,PARisassertedduringreaddataphases.
7www.
national.
com2.
0PinDescription(Continued)DP83815PERRN97N9I/OParityError:TheDP83815asamasterortargetwillassertthissignallowtoindicateaparityerroronanyincomingdata(exceptforspecialcycles).
Asabusmaster,itwillmonitorthissignalonallwriteoperations(exceptforspecialcycles).
REQN64J4ORequest:TheDP83815willassertthissignallowtorequestownershipofthebusfromthecentralarbiter.
RSTN62J3IReset:WhenthissignalisassertedallPCIbusoutputsofDP83815willbetri-statedandthedevicewillbeputintoaknownstate.
SERRN98L9I/OSystemError:ThissignalisassertedlowbyDP83815duringaddressparityerrorsandsystemerrorsifenabled.
STOPN96M9I/OStop:Thissignalisassertedlowbythetargetdevicetorequestthemasterdevicetostopthecurrenttransaction.
TRDYN93N8I/OTargetReady:Asamaster,thissignalindicatesthatthetargetisreadyforthedataduringwriteoperationandwiththedataduringreadoperation.
Asatarget,thissignalwillbeassertedlowwhenthe(target)deviceisreadytocompletethecurrentdataphasetransaction.
ThissignalisusedinconjunctionwiththeIRDYNsignal.
DatatransactiontakesplaceattherisingedgeofPCICLKwhenbothIRDYNandTRDYNareassertedlow.
PMEN/CLKRUNN59H2I/OPowerManagementEvent/ClockRunFunction:Thispinisadualfunctionpin.
ThefunctionofthispinisdeterminedbytheCLKRUN_ENbit0oftheCLKRUNControlandStatusregister(CCSR).
DefaultoperationofthispinisPMEN.
PowerManagementEvent:ThissignalisassertedlowbyDP83815toindicatethatapowermanagementeventhasoccurred.
ForpinconnectionpleaserefertoSection6.
7.
ClockRunFunction:Inthismode,thispinisusedtoindicatewhenthePCICLKwillbestopped.
3VAUX122J11IPCIAuxiliaryVoltageSense:Thispinisusedtosensethepresenceofa3.
3VauxiliarysupplyinordertodefinethePMESupportavailable.
ForpinconnectionpleaserefertoSection6.
7.
Thispinhasaninternalweakpulldown.
PWRGOOD123H13IPCIbuspowergood:ConnectedtoPCIbus3.
3Vpower(not3.
3Vaux),thispinisusedtosensethepresenceofPCIbuspower.
Thispinhasaninternalweakpulldown.
PCIBusInterfaceSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescription8www.
national.
com2.
0PinDescription(Continued)DP83815Note:MIIisnormallytri-stated,unlessenabledbyCFG:EXT_PHY.
SeeSection4.
2.
2.
MediaIndependentInterface(MII)SymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionCOL28C5ICollisionDetect:TheCOLsignalisassertedhighasynchronouslybytheexternalPMDupondetectionofacollisiononthemedium.
Itwillremainassertedaslongasthecollisionconditionpersists.
CRS29B5ICarrierSense:ThissignalisassertedhighasynchronouslybytheexternalPMDupondetectionofanon-idlemedium.
MDC5A11OManagementDataClock:Clocksignalwithamaximumrateof2.
5MHzusedtotransfermanagementdatafortheexternalPMDontheMDIOpin.
MDIO4C11I/OManagementDataI/O:BidirectionalsignalusedtotransfermanagementinformationfortheexternalPMD.
(SeeSection3.
12.
4fordetailsonconnectionswhenMIIisused.
)RXCLK6D11IReceiveClock:Acontinuousclock,sourcedbyanexternalPMDdevice,thatisrecoveredfromtheincomingdata.
During100Mb/soperationRXCLKis25MHzandduring10Mb/sthisis2.
5MHz.
RXD3/MA9,RXD2/MA8,RXD1/MA7,RXD0/MA612,11,10,7A9,B9,D10,B10IOReceiveData:SourcedfromanexternalPMD,thatcontainsdataalignedonnibbleboundariesandaredrivensynchronoustoRXCLK.
RXD[3]isthemostsignificantbitandRXD[0]istheleastsignificantbit.
BIOSROMAddress:DuringexternalBIOSROMaccess,thesesignalsbecomepartoftheROMaddress.
RXDV/MA1115B8IOReceiveDataValid:IndicatesthattheexternalPMDispresentingrecoveredanddecodednibblesontheRXDsignals,andthatRXCLKissynchronoustotherecovereddatain100Mb/soperation.
Thissignalwillencompasstheframe,startingwiththeStart-of-Framedelimiter(JK)andexcludinganyEnd-of-Framedelimiter(TR).
BIOSROMAddress:DuringexternalBIOSROMaccess,thissignalbecomespartoftheROMaddress.
RXER/MA1014D9IOReceiveError:AssertedhighsynchronouslybytheexternalPMDwheneveritdetectsamediaerrorandRXDVisassertedin100Mb/soperation.
BIOSROMAddress:DuringexternalBIOSROMaccess,thissignalbecomespartoftheROMaddress.
RXOE13C9OReceiveOutputEnable:UsedtodisableanexternalPMDwhiletheBIOSROMisbeingaccessed.
TXCLK31A4ITransmitClock:AcontinuousclockthatissourcedbytheexternalPMD.
During100Mb/soperationthisis25MHz+/-100ppm.
During10Mb/soperationthisclockis2.
5MHz+/-100ppm.
TXD3/MA15,TXD2/MA14,TXD1/MA13,TXD0/MA1225,24,23,22B6,C6,A6,D7OOTransmitData:SignalswhicharedrivensynchronoustotheTXCLKfortransmissiontotheexternalPMD.
TXD[3]isthemostsignificantbitandTXD[0]istheleastsignificantbit.
BIOSROMAddress:DuringexternalBIOSROMaccess,thesesignalsbecomepartoftheROMaddress.
TXEN30D5OTransmitEnable:ThissignalissynchronoustoTXCLKandprovidespreciseframingfordatacarriedonTXD[3-0]fortheexternalPMD.
ItisassertedwhenTXD[3-0]containsvaliddatatobetransmitted.
9www.
national.
com2.
0PinDescription(Continued)DP83815Note:DP83815supportsNM27LV010fortheBIOSROMinterfacedevice.
100BASE-TX/10BASE-TInterfaceSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionTPTDP,TPTDM54,53G1,F1A-OTransmitData:Differentialcommonoutputdriver.
Thisdifferentialcommonoutputisconfigurabletoeither10BASE-Tor100BASE-TXsignaling:10BASE-T:TransmissionofManchesterencoded10BASE-TpacketdataaswellasLinkPulses(includingFastLinkPulsesforAuto-Negotiationpurposes).
100BASE-TX:TransmissionofANSIX3T12compliantMLT-3data.
TheDP83815willautomaticallyconfigurethiscommonoutputdriverforthepropersignaltypeasaresultofeitherforcedconfigurationorAuto-Negotiation.
TPRDP,TPRDM46,45D1,C1A-IReceiveData:Differentialcommoninputbuffer.
Thisdifferentialcommoninputcanbeconfiguredtoaccepteither100BASE-TXor10BASE-Tsignaling:10BASE-T:ReceptionofManchesterencoded10BASE-TpacketdataaswellasnormalLinkPulsesandFastLinkPulsesforAuto-Negotiationpurposes.
100BASE-TX:ReceptionofANSIX3T12compliantscrambledMLT-3data.
TheDP83815willautomaticallyconfigurethiscommoninputbuffertoacceptthepropersignaltypeasaresultofeitherforcedconfigurationorAuto-Negotiation.
BIOSROM/FlashInterfaceSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionMCSN129G13OBIOSROM/FlashChipSelect:DuringaBIOSROM/Flashaccess,thissignalisusedtoselecttheROMdevice.
MD7,MD6,MD5,MD4/EEDO,MD3,MD2,MD1/CFGDISN,MD0141,140,139,138,135,134,133,132D13,D12,D14,E11,E14,F11,F13,F12I/OBIOSROM/FlashDataBus:DuringaBIOSROM/FlashaccessthesesignalsareusedtotransferdatatoorfromtheROM/Flashdevice.
MD[5:0]pinshaveinternalweakpullups.
MD6andMD7pinshaveinternalweakpulldowns.
MA5,MA4/EECLK,MA3/EEDI,MA2/LED100LNK,MA1/LED10LNK,MA0/LEDACT3,2,1,144,143,142B11,A12,B12,C13,C12,C14OBIOSROM/FlashAddress:DuringaBIOSROM/Flashaccess,thesesignalsareusedtodrivetheROM/Flashaddress.
MWRN131F14OBIOSROM/FlashWrite:DuringaBIOSROM/Flashaccess,thissignalisusedtoenabledatatobewrittentotheFlashdevice.
MRDN130G11OBIOSROM/FlashRead:DuringaBIOSROM/Flashaccess,thissignalisusedtoenabledatatobereadfromtheFlashdevice.
10www.
national.
com2.
0PinDescription(Continued)DP83815Note:DP83815supportsFM93C46fortheEEPROMdevice.
ClockInterfaceSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionX117D8ICrystal/OscillatorInput:ThispinistheprimaryclockreferenceinputfortheDP83815andmustbeconnectedtoa25MHz0.
005%(50ppm)clocksource.
TheDP83815devicesupportseitheranexternalcrystalresonatorconnectedacrosspinsX1andX2,oranexternalCMOS-leveloscillatorsourceconnectedtopinX1only.
X218C7OCrystalOutput:ThispinisusedinconjunctionwiththeX1pintoconnecttoanexternal25MHzcrystalresonatordevice.
ThispinmustbeleftunconnectedifanexternalCMOSoscillatorclocksourceisutilized.
FormoreinformationseethedefinitionforpinX1.
LEDInterfaceSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionLEDACTN/MA0142C14OTX/RXActivity:Thispinisanoutputindicatingtransmit/receiveactivity.
Thispinisdrivenlowtoindicateactivetransmissionorreception,andcanbeusedtodrivealowcurrentLED(2144C13O100Mb/sLink:Thispinisanoutputindicatingthe100Mb/sLinkstatus.
ThispinisdrivenlowtoindicateGoodLinkstatusfor100Mb/soperation,andcanbeusedtodrivealowcurrentLED(2O10Mb/sLink:Thispinisanoutputindicatingthe10Mb/sLinkstatus.
ThispinisdrivenlowtoindicateGoodLinkstatusfor10Mb/soperation,andcanbeusedtodrivealowcurrentLED(28G14OEEPROMChipSelect:ThissignalisusedtoenableanexternalEEPROMdevice.
EECLK/MA42A12OEEPROMClock:DuringanEEPROMaccess(EESELasserted),thispinisanoutputusedtodrivetheserialclocktoanexternalEEPROMdevice.
EEDI/MA31B12OEEPROMDataIn:DuringanEEPROMaccess(EESELasserted),thispinisanoutputusedtodriveopcode,address,anddatatoanexternalserialEEPROMdevice.
EEDO/MD4138E11IEEPROMDataOut:DuringanEEPROMaccess(EESELasserted),thispinisaninputusedtoretrieveEEPROMserialreaddata.
Thispinhasaninternalweakpullup.
MD1/CFGDISN133F13I/OConfigurationDisable:Whenpulledlowatpower-ontime,disablesloadofconfigurationdatafromtheEEPROM.
Use1Ktogroundtodisableconfigurationload.
11www.
national.
com2.
0PinDescription(Continued)DP83815ExternalReferenceInterfaceSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionVREF40A2IBandgapReference:ExternalcurrentreferenceresistorforinternalPhybandgapcircuitry.
Thevalueofthisresistoris9.
31K1%metalfilm(100ppm/oC)whichmustbeconnectedfromtheVREFpintoanalogground.
NoConnectsSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionNC34,42,43,48A1,A13,A14,B3,B13,B14,D4,F3,F4,G2,M2,M3,N1,N2,N13,N14,P1,P2,P13,P14NoConnectReserved41,50,127D2,E3,H12Thesepinsarereservedandcannotbeconnectedtoanyexternallogicornet.
12www.
national.
com2.
0PinDescription(Continued)DP83815SupplyPinsSymbolLQFPPinNo(s)LBGAPinNo(s)DirDescriptionSUBGND1,SUBGND2,SUBGND337,49,126B2,E1,G12SSubstrateGNDRXAVDD1,RXAVDD239,47C2,E2SRXAnalogVDD-connecttoisolatedAux3.
3VsupplyVDDRXAVSS1,RXAVSS238,44B1,D3SRXAnalogGNDTXIOVSS1,TXIOVSS252,55F2,G4STXOutputdriverVSSTXDVDD56H3STXDigitalVDD-connecttoAux3.
3VsupplyVDDTXDVSS51E4STXDigitalVSSMACVDD1,MACVDD258,125H1,H11SMac/BIUdigitalcoreVDD-connecttoAux3.
3VsupplyVDDMACVSS1,MACVSS257,124G3,H14SMac/BIUdigitalcoreVSSPCIVDD1,PCIVDD2,PCIVDD3,PCIVDD4,PCIVDD569,80,94,107,117L1,P5,L8,M12,K12SPCIIOVDD-connecttoPCIbus3.
3VVDDPCIVSS1,PCIVSS2,PCIVSS3,PCIVSS4,PCIVSS565,77,90,103,114K1,P4,M8,P11,L11SPCIIOVSSVDDIO2,VDDIO419,85C8,M6SMisc.
IOVDD-connecttoAux3.
3VsupplyVDDVDDIO1,VDDIO3,VDDIO59,27,137C10,A5,E13SMisc.
IOVDD-connecttoAux3.
3VsupplyVDDVSSIO2,VSSIO416,84A8,P6SMisc.
IOVSSVSSIO1,VSSIO3,VSSIO58,26,136A10,D6,E12SMisc.
IOVSSPHYVDD1,PHYVDD221,33B7,B4SPhydigitalcoreVDD-connecttoAux3.
3VsupplyVDDPHYVSS1,PHYVSS220,32A7,C4SPhydigitalcoreVSSFSVDD36C3SFrequencySynthesizerVDD-connecttoisolatedAux3.
3VsupplyVDDFSVSS35A3SFrequencySynthesizerVSS13www.
national.
comDP838153.
0FunctionalDescriptionDP83815consistsofaMAC/BIU(MediaAccessController/BusInterfaceUnit),aphysicallayerinterface,SRAM,andmiscellaneoussupportlogic.
TheMAC/BIUincludesthePCIbus,BIOSROMandEEPROMinterfaces,andan802.
3MAC.
Thephysicallayerinterfaceusedisasingle-portversionofthe3.
3VDsPhyter.
Internalmemoryconsistsofone-0.
5KBandtwo-2KBSRAMblocks.
Figure3-1DP83815FunctionalBlockDiagramMAC/BIUInterfaceSRAM25MHzClkMIIRXMIITXMIIMgtBIOSROMCntlBIOSROMDataBROM/EEPCIADPCICNTLPCICLK3VDSPPhysicalLayerLogicRX-2KBSRAMTX-2KBTPRDP/MEEPROM/LEDsMIITXMIIRXMIIMgtTestdatainTestdataoutMIITXMIIRXMIIMgtTPTDP/MDP83815TxAddrTxwrdataRxAddrRxwrdataRxrddataTxrddataRAMBISTLogicSRAMRXFilter.
5KB3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
14RevOwww.
national.
comDP83815Figure3-2MAC/BIUFunctionalBlockDiagram3.
1MAC/BIUTheMAC/BIUisaderivativedesignfromtheDP83810(Euphrates).
TheoriginalMAC/BIUdesignhasbeenoptimizedtoimprovelogicefficiencyandenhancedtoaddfeaturesconsistentwithcurrentmarketneedsandspecificationcompliance.
TheMAC/BIUdesignblocksarediscussedinthissection.
3.
1.
1PCIBusInterfaceThisblockimplementsPCIv2.
2busprotocols,andconfigurationspace.
SupportsbusmasterreadsandwritestoCPUmemory,andCPUaccesstoon-chipregisterspace.
Additionalfunctionsprovidedinclude:configurationcontrol,serialEEPROMaccesswithautoconfigurationload,interruptcontrol,powermanagementcontrolwithsupportforPMEorCLKRUNfunction.
3.
1.
1.
1ByteOrderingTheDP83815canbeconfiguredtoorderthebytesofdataontheAD[31:0]bustoconformtolittleendianorbigendianorderingthroughtheuseoftheConfigurationRegister,bit0(CFG:BEM).
Bydefault,thedeviceisinlittleendianordering.
ByteorderingonlyaffectsdataFIFOs.
Registerinformationremainsbitaligned(i.
e.
AD[31]mapstobit31inanyregisterspace,AD[0]mapstobit0,etc.
).
TxBufferManagerMIBTxMACRxMACPCIBusDataFIFOPhysicalLayerInterface93C46SerialEEPROMMAC/BIU321532323232321632324432RxFilterPktRecogLogicSRAMRxBufferManagerDataFIFOBootROM/FlashPCIBusInterface3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
15RevOwww.
national.
comDP83815LittleEndian(CFG:BEM=0):Thebyteorientationforreceiveandtransmitdatainsystemmemoryisasfollows:BigEndian(CFG:BEM=1):Thebyteorientationforreceiveandtransmitdatainsystemmemoryisasfollows:3.
1.
1.
2PCIBusInterruptControlPCIbusinterruptsfortheDP83815areasynchronouslyperformedbyassertingpinINTAN.
Thispinisanopendrainoutput.
ThesourceoftheinterruptcanbedeterminedbyreadingtheInterruptStatusRegister(ISR).
OneormorebitsintheISRwillbeset,denotingallcurrentlypendinginterrupts.
Caution:ReadingoftheISRclearsALLbits.
MaskingofspecifiedinterruptscanbeaccomplishedbyusingtheInterruptMaskRegister(IMR).
3.
1.
1.
3TimerTheLatencyTimerdescribedinCFGLAT:LATdefinestheminimumnumberofbusclocksthatthedevicewillholdthebus.
OncethedevicegainscontrolofthebusandissuesFRAMEN,theLatencyTimerwillbegincountingdown.
IfGNTNisde-assertedbeforetheDP83815hasfinishedwiththebus,thedevicewillmaintainownershipofthebusuntilthetimerreacheszero(orhasfinishedthebustransfer).
Thetimerisan8-bitcounter.
3.
1.
2TxMACThisblockimplementsthetransmitportionof802.
3MediaAccessControl.
TheTxMACretrievespacketdatafromtheTxBufferManagerandsendsitoutthroughthetransmitportion.
Additionally,theTxMACprovidesMIBcontrolinformationfortransmitpackets.
3.
1.
3RxMACThisblockimplementsthereceiveportionof802.
3MediaAccessControl.
TheRxMACretrievespacketdatafromthereceiveportionandsendsittotheRxBufferManager.
Additionally,theRxMACprovidesMIBcontrolinformationandpacketaddressdatafortheRxFilter.
3.
2BufferManagementThebuffermanagementschemeusedontheDP83815allowsquick,simpleandefficientuseoftheframebuffermemory.
Framesaresavedinsimilarformatsforbothtransmitandreceive.
Thebuffermanagementschemealsousesseparatebuffersanddescriptorsforpacketinformation.
Thisallowseffectivetransfersofdatafromthereceivebuffertothetransmitbufferbysimplytransferringthedescriptorfromthereceivequeuetothetransmitqueue.
Theformatofthedescriptorsallowsthepacketstobesavedinanumberofconfigurations.
Apacketcanbestoredinmemorywithasingledescriptorpersinglepacket,ormultipledescriptorspersinglepacket.
ThisflexibilityallowstheusertoconfiguretheDP83815tomaximizeefficiency.
Architectureofthespecificsystem'sbuffermemory,aswellasthenatureofnetworktraffic,willdeterminethemostsuitableconfigurationofpacketdescriptorsandfragments.
RefertotheBufferManagementSection(Section5.
0)formoreinformation.
3.
2.
1TxBufferManagerThisblockDMAspacketdatafromPCImemoryspaceandplacesitinthe2KBtransmitFIFO,andpullsdatafromtheFIFOtosendtotheTxMAC.
Multiplepackets(4)maybepresentintheFIFO,allowingpacketstobetransmittedwithminimuminterframegap.
ThewayinwhichtheFIFOisemptiedandfillediscontrolledbytheFIFOthresholdvaluesintheTXCFGregister:FLTH(TxFillThreshold)andDRTH(TxDrainThreshold).
ThesevaluesdeterminehowfulloremptytheFIFOmustbebeforethedevicerequeststhebus.
Additionally,oncetheDP83815requeststhebus,itwillattempttoemptyorfilltheFIFOasallowedbytheMXDMAsettingintheTXCFGregister.
3.
2.
2RxBufferManagerThisblockretrievespacketdatafromtheRxMACandplacesitinthe2KBreceivedataFIFO,andpullsdatafromtheFIFOforDMAtoPCImemoryspace.
TheRxBufferManagermaintainsastatusFIFO,allowingupto4packetstoresideintheFIFOatonce.
SimilartothetransmitFIFO,thereceiveFIFOiscontrolledbytheFIFOthresholdvalueintheRXCFGregister:DRTH(RxDrainThreshold).
ThisvaluedeterminesthenumberoflongwordswrittenintotheFIFOfromtheMACunitbeforeaDMArequestforsystemmemoryaccessoccurs.
OncetheDP83815getsthebus,itwillcontinuetotransferthelongwordsfromtheFIFOuntilthedataintheFIFOislessthanonelongword,orhasreachedtheendofthepacket,orthemaxDMAburstsizeisreached(RXCFG:MXDMA).
3.
2.
3PacketRecognitionTheReceivepacketfilterandrecognitionlogicallowssoftwaretocontrolwhichpacketsareacceptedbasedondestinationaddressandpackettype.
Addressrecognitionlogicincludessupportforbroadcast,multicasthash,andunicastaddresses.
ThepacketrecognitionlogicincludessupportforWOL,Pause,andprogrammablepatternrecognition.
Byte0Byte1Byte2Byte30781516232431LSBC/BE[0]C/BE[1]C/BE[2]C/BE[3]MSBByte3Byte2Byte1Byte00781516232431MSBC/BE[0]C/BE[1]C/BE[2]C/BE[3]LSB3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
16RevOwww.
national.
comDP83815Thestandard802.
3Ethernetpacketconsistsofthefollowingfields:Preamble(PA),StartofFrameDelimiter(SFD),DestinationAddress(DA),SourceAddress(SA),Length(LEN),DataandFrameCheckSequence(FCS).
Allfieldsarefixedlengthexceptforthedatafield.
Duringreception,thePA,SFDandFCSarestripped.
Duringtransmission,theDP83815generatesandappendsthePA,SFDandFCS.
3.
2.
4MIBTheMIBblockcontainscounterstotrackcertainmediaeventsrequiredbythemanagementspecificationsRFC1213(MIBII),RFC1398(Ether-likeMIB),andIEEE802.
3LME.
Thecountersprovidedareforeventswhichareeitherdifficultorimpossibletobeintercepteddirectlybysoftware.
Notallcountersareimplemented,howeverrequiredcounterscanbecalculatedfromthecountersprovided.
3.
3InterfaceDefinitions3.
3.
1PCISystemBusThisinterfaceallowsdirectconnectionoftheDP83815toa33MHzPCIsystembus.
TheDP83815supportszerowaitstatedatatransferswithburstsizesupto128dwords.
TheDP83815conformsto3.
3VAC/DCspecifications,buthas5Vtolerantinputs.
3.
3.
2BootPROMTheBIOSROMinterfaceallowstheDP83815toreadfromandwritedatatoanexternalROM/Flashdevice.
3.
3.
3EEPROMTheDP83815supportstheattachmentofanexternalEEPROM.
TheEEPROMinterfaceprovidestheabilityfortheDP83815toreadfromandwritedatatoanexternalserialEEPROMdevice.
TheDP83815willauto-loadvaluesfromtheEEPROMtocertainfieldsinPCIconfigurationspaceandoperationalspaceandperformachecksumtoverifythatthedataisvalid.
ValuesintheexternalEEPROMallowdefaultfieldsinPCIconfigurationspaceandI/Ospacetobeoverriddenfollowingahardwarereset.
IftheEEPROMisnotpresent,theDP83815initializationusesdefaultvaluesfortheappropriateConfigurationandOperationalRegisters.
SoftwarecanreadandwritetotheEEPROMusing"bit-bang"accessesviatheEEPROMAccessRegister(MEAR).
3.
3.
4ClockTheclockinterfaceprovidesthe25MHzclockreferenceinputfortheDP83815IC.
TheX1andX2pincapacitancesare4.
5+1.
0pF.
TheX1inputsignalamplitudeshouldbeapproximately1V.
Thisinterfacesupportsoperationfroma25MHz,50ppmCMOSoscillator,ora25MHz,50ppm,parallel,20pFload,20pFcrystalresonatorwouldrequireC1andC2loadcapacitorsof27-33pFeach.
Figure3-3EthernetPacketFormat60b4b6B2B46B-1500B4BFCSDataLENSADAPA6BSFDNote:B=Bytesb=bits3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
17RevOwww.
national.
comDP83815Figure3-4DSPPhysicalLayerBlockDiagramTRANSMITCHANNELS&100MB/S10MB/SNRZTOMANCHESTERENCODERSTATEMACHINESTRANSMITFILTERLINKPULSEGENERATOR4B/5BENCODERSCRAMBLERPARALLELTOSERIALNRZTONRZIENCODERBINARYTOMLT-3ENCODER10/100COMMONRECEIVECHANNELS&100MB/S10MB/SMANCHESTERTONRZDECODERSTATEMACHINESRECEIVEFILTERLINKPULSEDETECTOR4B/5BDECODERDESCRAMBLERSERIALTOPARALLELNRZITONRZDECODERMLT-3TO10/100COMMONAUTO-NEGOTIATIONSTATEMACHINEFAR-END-FAULTSTATEMACHINEREGISTERSAUTO100BASE-X10BASE-TMIIBASICMODEPCSCONTROLPHYADDRESSNEGOTIATIONCLOCKCLOCKRECOVERYCLOCKRECOVERYCODEGROUPALIGNMENTSMARTSQUELCHRX_DATARXCLKRX_DATARXCLKTX_DATATX_DATATXCLKSYSTEMCLOCKREFERENCERD±TD±OUTPUTDRIVERINPUTBUFFERBINARYDECODERADAPTIVEEQANDBLWCOMP.
(ALSOFX_RD±)LEDDRIVERSLEDSPOWERONCONFIGURATIONPINSGENERATIONCONTROLNCLK_50MTXCLKTXD(3:0)TXERTXENMDIOMDCCOLCRSRXENRXERRXDVRXD(3:0)RXCLKMACINTERFACESERIALMANAGEMENT3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
18RevOwww.
national.
comDP838153.
4PhysicalLayerTheDP83815hasafullfeaturedphysicallayerdevicewithintegratedPMDsub-layerstosupportboth10BASE-Tand100BASE-TXEthernetprotocols.
Thephysicallayerisdesignedforeasyimplementationof10/100Mb/sEthernethomeorofficesolutions.
Itinterfacesdirectlytotwistedpairmediaviaanexternaltransformer.
ThephysicallayerutilizesonchipDigitalSignalProcessing(DSP)technologyanddigitalPLLsforrobustperformanceunderalloperatingconditions,enhancednoiseimmunity,andlowerexternalcomponentcountwhencomparedtoanalogsolutions.
3.
4.
1Auto-NegotiationTheAuto-Negotiationfunctionprovidesamechanismforexchangingconfigurationinformationbetweentwoendsofalinksegmentandautomaticallyselectingthehighestperformancemodeofoperationsupportedbybothdevices.
FastLinkPulse(FLP)BurstsprovidethesignallingusedtocommunicateAuto-Negotiationabilitiesbetweentwodevicesateachendofalinksegment.
ForfurtherdetailregardingAuto-Negotiation,refertoClause28oftheIEEE802.
3uspecification.
TheDP83815supportsfourdifferentEthernetprotocols(10Mb/sHalfDuplex,10Mb/sFullDuplex,100Mb/sHalfDuplex,and100Mb/sFullDuplex),sotheinclusionofAuto-NegotiationensuresthatthehighestperformanceprotocolwillbeselectedbasedontheadvertisedabilityoftheLinkPartner.
TheAuto-NegotiationfunctionwithintheDP83815iscontrolledbyinternalregisteraccess.
Auto-Negotiationwillbesetatpower-up/reset,andalsowhenalinkstatus(up/valid)changeoccurs.
3.
4.
2Auto-NegotiationRegisterControlWhenAuto-Negotiationisenabled,theDP83815transmitstheabilitiesprogrammedintotheAuto-NegotiationAdvertisementregister(ANAR)viaFLPBursts.
Anycombinationof10Mb/s,100Mb/s,Half-Duplex,andFullDuplexmodesmaybeselected.
Thedefaultsettingofbits[8:5]intheANARandbit12intheBMCRregisteraredeterminedatpower-up.
TheBMCRprovidessoftwarewithamechanismtocontroltheoperationoftheDP83815.
Bits1&2ofthePHYSTSregisterareonlyvalidifAuto-NegotiationisdisabledorafterAuto-Negotiationiscomplete.
TheAuto-NegotiationprotocolcomparesthecontentsoftheANLPARandANARregistersandusestheresultstoautomaticallyconfiguretothehighestperformanceprotocolcommontothelocalandfar-endport.
TheresultsofAuto-NegotiationmaybeaccessedinregisterC0h(PHYSTS),bit4:Auto-NegotiationComplete,bit2:DuplexStatusandbit1:SpeedStatus.
Auto-NegotiationPriorityResolution:—(1)100BASE-TXFullDuplex(HighestPriority)—(2)100BASE-TXHalfDuplex—(3)10BASE-TFullDuplex—(4)10BASE-THalfDuplex(LowestPriority)TheBasicModeControlRegister(BMCR)providescontrolforenabling,disabling,andrestartingtheAuto-Negotiationprocess.
WhenAuto-NegotiationisdisabledtheSpeedSelectionbitintheBCMR(bit13)controlsswitchingbetween10Mb/sor100Mb/soperation,andtheDuplexModebit(bit8)controlsswitchingbetweenfullduplexoperationandhalfduplexoperation.
TheSpeedSelectionandDuplexModebitshavenoeffectonthemodeofoperationwhentheAuto-NegotiationEnablebit(bit12)isset.
TheBasicModeStatusRegister(BMSR)indicatesthesetofavailableabilitiesfortechnologytypes,Auto-Negotiationability,andExtendedRegisterCapability.
ThesebitsarepermanentlysettoindicatethefullfunctionalityoftheDP83815(onlythe100BASE-T4bitisnotsetsincetheDP83815doesnotsupportthatfunction).
TheBMSRalsoprovidesstatuson:—Auto-Negotiationcomplete(bit5)—LinkPartneradvertisingthataremotefaulthasoccurred(bit4)—Validlinkhasbeenestablished(bit2)—SupportforManagementFramePreamblesuppression(bit6)TheAuto-NegotiationAdvertisementRegister(ANAR)indicatestheAuto-NegotiationabilitiestobeadvertisedbytheDP83815.
Allavailableabilitiesaretransmittedbydefault,butanyabilitycanbesuppressedbywritingtotheANAR.
UpdatingtheANARtosuppressanabilityisonewayforamanagementagenttochange(force)thetechnologythatisused.
TheAuto-NegotiationLinkPartnerAbilityRegister(ANLPAR)isusedtoreceivethebaselinkcodewordaswellasallnextpagecodewordsduringthenegotiation.
Furthermore,theANLPARwillbeupdatedtoeither0081hor0021hforparalleldetectiontoeither100Mb/sor10Mb/srespectively.
TheAuto-NegotiationExpansionRegister(ANER)indicatesadditionalAuto-Negotiationstatus.
TheANERprovidesstatuson:—ParallelDetectFaultoccurrence(bit4)—LinkPartnersupportoftheNextPagefunction(bit3)—DP83815supportoftheNextPagefunction(bit2).
TheDP83815supportstheNextPagefunction.
—CurrentpagebeingexchangedbyAuto-Negotiationhasbeenreceived(bit1)—LinkPartnersupportofAuto-Negotiation(bit0)3.
4.
3Auto-NegotiationParallelDetectionTheDP83815supportstheParallelDetectionfunctionasdefinedintheIEEE802.
3uspecification.
ParallelDetectionrequiresboththe10Mb/sand100Mb/sreceiverstomonitorthereceivesignalandreportlinkstatustotheAuto-Negotiationfunction.
Auto-NegotiationusesthisinformationtoconfigurethecorrecttechnologyintheeventthattheLinkPartnerdoesnotsupportAuto-Negotiationyetistransmittinglinksignalsthatthe100BASE-TXor10BASE-TPMAs(PhysicalMediumAttachments)recognizeasvalidlinksignals.
IftheDP83815completesAuto-NegotiationasaresultofParallelDetection,bits5and7withintheANLPARregisterwillbeupdatedtoreflectthemodeofoperationpresentintheLinkPartner.
Notethatbits4:0oftheANLPARwillalsobesetto00001basedonasuccessfulparalleldetectiontoindicateavalid802.
3selectorfield.
SoftwaremaydeterminethatnegotiationcompletedviaParallelDetectionbyreadingtheANER(98h)registerwithbit0,LinkPartnerAuto-NegotiationAblebit,beingresettoazero,oncetheAuto-NegotiationCompletebit,bit5oftheBMSR(84h)3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
19RevOwww.
national.
comDP83815registerissettoaone.
Ifconfiguredforparalleldetectmode,andanyconditionotherthanasinglegoodlinkoccurs,thentheparalleldetectfaultbitwillsettoaone,bit4oftheANERregister(98h).
3.
4.
4Auto-NegotiationRestartOnceAuto-Negotiationhascompleted,itmayberestartedatanytimebysettingbit9(RestartAuto-Negotiation)oftheBMCRtoone.
IfthemodeconfiguredbyasuccessfulAuto-Negotiationlosesavalidlink,thentheAuto-Negotiationprocesswillresumeandattempttodeterminetheconfigurationforthelink.
Thisfunctionensuresthatavalidconfigurationismaintainedifthecablebecomesdisconnected.
Arenegotiationrequestfromanyentity,suchasamanagementagent,willcausetheDP83815tohaltanytransmitdataandlinkpulseactivityuntilthebreak_link_timerexpires(~1500ms).
Consequently,theLinkPartnerwillgointolinkfailandnormalAuto-Negotiationresumes.
TheDP83815willresumeAuto-Negotiationafterthebreak_link_timerhasexpiredbyissuingFLP(FastLinkPulse)bursts.
3.
4.
5EnablingAuto-NegotiationviaSoftwareItisimportanttonotethatiftheDP83815hasbeeninitializeduponpower-upasanon-auto-negotiatingdevice(forcedtechnology),anditisthenrequiredthatAuto-Negotiationorre-Auto-Negotiationbeinitiatedviasoftware,bit12(Auto-NegotiationEnable)oftheBasicModeControlRegistermustfirstbeclearedandthensetforanyAuto-Negotiationfunctiontotakeeffect.
3.
4.
6Auto-NegotiationCompleteTimeParalleldetectionandAuto-Negotiationtakeapproximately2-3secondstocomplete.
Inaddition,Auto-Negotiationwithnextpageshouldtakeapproximately2-3secondstocomplete,dependingonthenumberofnextpagessent.
RefertoClause28oftheIEEE802.
3ustandardforafulldescriptionoftheindividualtimersrelatedtoAuto-Negotiation.
3.
5LEDInterfacesTheDP83815hasparalleloutputstoindicatethestatusofActivity(TransmitorReceive),100Mb/sLink,and10Mb/sLink.
TheLEDACTNpinindicatesthepresenceoftransmitorreceiveactivity.
ThestandardCMOSdrivergoeslowwhenRXorTXactivityisdetectedineither10Mb/sor100Mb/soperation.
TheLED100Npinindicatesagoodlinkat100Mb/sdatarate.
ThestandardCMOSdrivergoeslowwhenthisoccurs.
In100BASE-Tmode,linkisestablishedasaresultofinputreceiveamplitudecompliantwithTP-PMDspecificationswhichwillresultininternalgenerationofsignaldetect.
ThissignalwillassertaftertheinternalSignalDetecthasremainedassertedforaminimumof500us.
Thesignalwillde-assertimmediatelyfollowingthede-assertionoftheinternalsignaldetect.
TheLED10Npinindicatesagoodlinkat10Mb/sdatarate.
ThestandardCMOSdrivergoeslowwhenthisoccurs.
10Mb/sLinkisestablishedasaresultofthereceptionofatleastsevenconsecutivenormalLinkPulsesorthereceptionofavalid10BASE-Tpacket.
Thiswillcausetheassertionofthissignal.
thesignalwillde-assertinaccordancewiththeLinkLossTimerasspecifiedinIEEE802.
3.
TheDP83815LEDpinsarecapableof6mA.
ConnectionoftheseLEDpinsshouldensurethisisnotoverloaded.
Using2mALEDdevicestheconnectionfortheLEDscouldbeasshowninFigure3-5.
Figure3-5LEDLoadingExampleVDDLED10N453LEDACTN453LED100N4533.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
20RevOwww.
national.
comDP838153.
6HalfDuplexvs.
FullDuplexTheDP83815supportsbothhalfandfullduplexoperationatboth10Mb/sand100Mb/sspeeds.
Half-duplexisthestandard,traditionalmodeofoperationwhichreliesontheCSMA/CDprotocoltohandlecollisionsandnetworkaccess.
InHalf-Duplexmode,CRSrespondstobothtransmitandreceiveactivityinordertomaintaincompliancewithIEEE802.
3specification.
SincetheDP83815isdesignedtosupportsimultaneoustransmitandreceiveactivityitiscapableofsupportingfull-duplexswitchedapplicationswithathroughputofupto200Mb/sperportwhenoperatingin100BASE-TXmode.
BecausetheCSMA/CDprotocoldoesnotapplytofull-duplexoperation,theDP83815disablesitsowninternalcollisionsensingandreportingfunctions.
ItisimportanttounderstandthatwhilefullAuto-NegotiationwiththeuseofFastLinkPulsecodewordscaninterpretandconfiguretosupportfull-duplex,paralleldetectioncannotrecognizethedifferencebetweenfullandhalf-duplexfromafixed10Mb/sor100Mb/slinkpartnerovertwistedpair.
Therefore,asspecifiedin802.
3u,ifafar-endlinkpartneristransmittingforcedfullduplex100BASE-TXforexample,theparalleldetectionstatemachineinthereceivingstationwouldbeunabletodetectthefullduplexcapabilityofthefar-endlinkpartnerandwouldnegotiatetoahalfduplex100BASE-TXconfiguration(samescenariofor10Mb/s).
Forfullduplexoperation,thefollowingregisterbitsmustalsobeset:—TXCFG:CSI(CarrierSenseIgnore)—TXCFG:HBI(HeartBeatIgnore)—RXCFG:ATX(AcceptTransmitPackets)Additionally,theAuto-NegotiationSelectbitsintheConfigurationregistermustshowfullduplexsupport:—CFG:ANEG_SEL3.
7PhyLoopbackTheDP83815includesaPhyLoopbackTestmodeforeasyboarddiagnostics.
TheLoopbackmodeisselectedthroughbit14(Loopback)oftheBasicModeControlRegister(BMCR).
Writing1tothisbitenablestransmitdatatoberoutedtothereceivepathearlyinthephysicallayercell.
Loopbackstatusmaybecheckedinbit3ofthePHYStatusRegister(C0h).
WhileinLoopbackmodethedatawillnotbetransmittedontothemedia.
Thisistrueforeither10Mb/saswellas100Mb/sdata.
In100BASE-TXLoopbackmodethedataisroutedthroughthePCSandPMAlayersintothePMDsublayerbeforeitisloopedback.
Therefore,inadditiontoservingasaboarddiagnostic,thismodeservesasquickfunctionalverificationofthedevice.
Note:AMacLoopbackcanbeperformedviasettingbit29(MacLoopback)intheTxConfigurationRegister.
3.
8StatusInformationThereare3pinsthatareavailabletoconveystatusinformationtotheuserthroughLEDstoindicatethespeed(10Mb/sor100Mb/s)linkstatusandreceiveortransmitactivity.
10Mb/sLinkisestablishedasaresultofthereceptionofatleastsevenconsecutiveNormalLinkPulsesorthereceptionofavalid10BASE-Tpacket.
LED10Nwillde-assertinaccordancewiththeLinkLossTimerspecifiedinIEEE802.
3.
100BASE-TLinkisestablishedasaresultofaninputreceiveamplitudecompliantwithTP-PMDspecificationswhichwillresultininternalgenerationofSignalDetect.
LED100NwillassertaftertheinternalSignalDetecthasremainedassertedforaminimumof500s.
LED100Nwillde-assertimmediatelyfollowingthede-assertionoftheinternalSignalDetect.
ActivityLEDstatusindicatesReceiveorTransmitactivity.
3.
9100BASE-TXTRANSMITTERThe100BASE-TXtransmitterconsistsofseveralfunctionalblockswhichconvertsynchronous4-bitnibbledata,toascrambledMLT-3125Mb/sserialdatastream.
Becausethe100BASE-TXTP-PMDisintegrated,thedifferentialoutputpins,TD±,canbedirectlyroutedtothemagnetics.
TheblockdiagraminFigure3-6providesanoverviewofeachfunctionalblockwithinthe100BASE-TXtransmitsection.
TheTransmittersectionconsistsofthefollowingfunctionalblocks:—Code-groupEncoderandInjectionblock(bypassoption)—Scramblerblock(bypassoption)—NRZtoNRZIencoderblock—BinarytoMLT-3converter/CommonDriverThebypassoptionforthefunctionalblockswithinthe100BASE-TXtransmitterprovidesflexibilityforapplicationssuchas100Mb/srepeaterswheredataconversionisnotalwaysrequired.
TheDP83815implementsthe100BASE-TXtransmitstatemachinediagramasspecifiedintheIEEE802.
3uStandard,Clause24.
3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
21RevOwww.
national.
comDP83815Figure3-6100BASE-TXTransmitBlockDiagram3.
9.
1Code-groupEncodingandInjectionThecode-groupencoderconverts4-bit(4B)nibbledatageneratedbytheMACinto5-bit(5B)code-groupsfortransmission.
Thisconversionisrequiredtoallowcontroldatatobecombinedwithpacketdatacode-groups.
RefertoTable3-1for4Bto5Bcode-groupmappingdetails.
Thecode-groupencodersubstitutesthefirst8-bitsoftheMACpreamblewithaJ/Kcode-grouppair(1100010001)upontransmission.
Thecode-groupencodercontinuestoreplacesubsequent4Bpreambleanddatanibbleswithcorresponding5Bcode-groups.
Attheendofthetransmitpacket,uponthede-assertionofTransmitEnablesignalfromtheMAC,thecode-groupencoderinjectstheT/Rcode-grouppair(0110100111)indicatingtheendofframe.
AftertheT/Rcode-grouppair,thecode-groupencodercontinuouslyinjectsIDLEsintothetransmitdatastreamuntilthenexttransmitpacketisdetected(re-assertionofTransmitEnable).
3.
9.
2ScramblerThescramblerisrequiredtocontroltheradiatedemissionsatthemediaconnectorandonthetwistedpaircable(for100BASE-TXapplications).
Byscramblingthedata,thetotalenergylaunchedontothecableisrandomlydistributedoverawidefrequencyrange.
Withoutthescrambler,energylevelsatthePMDandonthecablecouldpeakbeyondFCClimitationsatfrequenciesrelatedtorepeating5Bsequences(i.
e.
,continuoustransmissionofIDLEs).
Thescramblerisconfiguredasaclosedlooplinearfeedbackshiftregister(LFSR)withan11-bitpolynomial.
TheoutputoftheclosedloopLFSRisX-ORdwiththeserialNRZdatafromthecode-groupencoder.
Theresultisascrambleddatastreamwithsufficientrandomizationtodecreaseradiatedemissionsatcertainfrequenciesbyasmuchas20dB.
FROMCGMBP_4B5BBP_SCR4B5BCODE-MUX5BPARALLELSCRAMBLERMUXMUXNRZTONRZIBINARYTD+/-100BASE-TXGROUPENABLERTXD(3:0)/TXERTXCLKTOSERIALENCODERTOMLT-3/COMMONDRIVERLOOPBACK3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
22RevOwww.
national.
comDP838153.
9.
3NRZtoNRZIEncoderAfterthetransmitdatastreamhasbeenserializedandscrambled,thedatamustbeNRZIencodedinordertocomplywiththeTP-PMDstandardfor100BASE-TXtransmissionoverCategory-5un-shieldedtwistedpaircable.
ThereisnoabilitytobypassthisblockwithintheDP83815.
3.
9.
4BinarytoMLT-3Convertor/CommonDriverTheBinarytoMLT-3conversionisaccomplishedbyconvertingtheserialbinarydatastreamoutputfromtheNRZIencoderintotwobinarydatastreamswithalternatelyphasedlogiconeevents.
Thesetwobinarystreamsarethenfedtothetwistedpairoutputdriverwhichconvertsthevoltagetocurrentandalternatelydriveseithersideofthetransmittransformerprimarywinding,resultinginaminimalcurrent(20mAmax)MLT-3signal.
RefertoFigure3-7Figure3-7BinarytoMLT-3conversionDQQbinary_inbinary_plusbinary_minusbinary_inbinary_plusbinary_minusCOMMONDRIVERMLT-3differentialMLT-3Table3-14B5BCode-GroupEncoding/DecodingNamePCS5BCode-groupDescription/4BValueDATACODES0111100000101001000121010000103101010011401010010050101101016011100110701111011181001010009100111001A101101010B101111011C110101100D110111101E111001110F111011111IDLEANDCONTROLCODESH00100HALTcode-group-ErrorcodeI11111Inter-PacketIDLE-0000J11000FirstStartofPacket-0101K10001SecondStartofPacket-0101T01101FirstEndofPacket-0000R00111SecondEndofPacket-00003.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
23RevOwww.
national.
comDP83815The100BASE-TXMLT-3signalsourcedbytheTD±commondriveroutputpinsisslewratecontrolled.
ThisshouldbeconsideredwhenselectingACcouplingmagneticstoensureTP-PMDStandardcomplianttransitiontimes(3ns25Mb/sserialdatastreamtosynchronous4-bitnibbledatathatisprovidedtotheMAC.
Becausethe100BASE-TXTP-PMDisintegrated,thedifferentialinputpins,RD±,canbedirectlyroutedfromtheACcouplingmagnetics.
SeeFigure3-8forablockdiagramofthe100BASE-TXreceivefunction.
Thisprovidesanoverviewofeachfunctionalblockwithinthe100BASE-TXreceivesection.
TheReceivesectionconsistsofthefollowingfunctionalblocks:—ADC—InputandBLWCompensation—SignalDetect—DigitalAdaptiveEqualization—MLT-3toBinaryDecoder—ClockRecoveryModule—NRZItoNRZDecoder—SerialtoParallel—De-scrambler(bypassoption)—CodeGroupAlignment—4B/5BDecoder(bypassoption)—LinkIntegrityMonitor—BadSSDDetectionThebypassoptionforthefunctionalblockswithinthe100BASE-TXreceiverprovidesflexibilityforapplicationssuchas100Mb/srepeaterswheredataconversionisnotalwaysrequired.
3.
10.
1InputandBaseLineWanderCompensationUnliketheDP83223VTwister,theDP83815requiresnoexternalattenuationcircuitryatitsreceiveinputs,RD+/.
ItacceptsTP-PMDcompliantwaveformsdirectly,requiringonlya100terminationplusasimple1:1transformer.
TheDP83815iscompletelyANSITP-PMDcompliantandincludesBaseLineWander(BLW)compensation.
TheBLWcompensationblockcansuccessfullyrecovertheTP-PMDdefined"killer"patternandpassittothedigitaladaptiveequalizationblock.
BLWcangenerallybedefinedasthechangeintheaverageDCcontent,overtime,ofanACcoupleddigitaltransmissionoveragiventransmissionmedium.
(i.
e.
copperwire).
BLWresultsfromtheinteractionbetweenthelowfrequencycomponentsofatransmittedbitstreamandthefrequencyresponseoftheACcouplingcomponent(s)withinthetransmissionsystem.
IfthelowfrequencycontentofthedigitalbitstreamgoesbelowthelowfrequencypoleoftheACcouplingtransformersthenthedroopcharacteristicsofthetransformerswilldominateresultinginpotentiallyseriousBLW.
ThedigitaloscilloscopeplotprovidedinFigure3-9illustratestheseverityoftheBLWeventthatcantheoreticallybegeneratedduring100BASE-TXpackettransmission.
Thiseventconsistsofapproximately800mVofDCoffsetforaperiodof120us.
Leftuncompensated,eventssuchasthiscancausepacketloss.
3.
10.
2SignalDetectThesignaldetectfunctionoftheDP83815isincorporatedtomeetthespecificationsmandatedbytheANSIFDDITP-PMDStandardaswellastheIEEE802.
3100BASE-TXStandardforbothvoltagethresholdsandtimingparameters.
Notethatthereceptionofnormal10BASE-TlinkpulsesandfastlinkpulsesperIEEE802.
3uAuto-Negotiationbythe100BASE-TXreceiverdonotcausetheDP83815toassertsignaldetect.
INVALIDCODESV00000V00001V00010V00011V00101V00110V01000V01100V10000V11001Table3-14B5BCode-GroupEncoding/DecodingNamePCS5BCode-groupDescription/4BValue3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
24RevOwww.
national.
comDP83815Figure3-8100M/bsReceiveBlockDiagramBP_4B5BBP_SCRBP_RXCLOCKMUXMUX4B/5BDECODERSERIALTOCODEGROUPMUXDESCRAMBLERNRZITONRZMLT-3TOBINARYDIGITALCLOCKLINKINTEGRITYRX_DATAVALIDAGCINPUTBLWADCSIGNALCOMPENSATIONADAPTIVEEQUALIZATIONDECODERDECODERALIGNMENTRECOVERYMODULEPARALLELMONITORSSDDETECTRXCLKSDRXD(3:0)/RXERRD+/-DETECT3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
25RevOwww.
national.
comDP838153.
10.
3DigitalAdaptiveEqualizationWhentransmittingdataathighspeedsovercoppertwistedpaircable,frequencydependentattenuationbecomesaconcern.
Inhigh-speedtwistedpairsignalling,thefrequencycontentofthetransmittedsignalcanvarygreatlyduringnormaloperationbasedprimarilyontherandomnessofthescrambleddatastream.
Thisvariationinsignalattenuationcausedbyfrequencyvariationsmustbecompensatedfortoensuretheintegrityofthetransmission.
InordertoensurequalitytransmissionwhenemployingMLT-3encoding,thecompensationmustbeabletoadapttovariouscablelengthsandcabletypesdependingontheinstalledenvironment.
Theselectionoflongcablelengthsforagivenimplementation,requiressignificantcompensationwhichwillover-compensateforshorter,lessattenuatinglengths.
Conversely,theselectionofshortorintermediatecablelengthsrequiringlesscompensationwillcauseseriousunder-compensationforlongerlengthcables.
Therefore,thecompensationorequalizationmustbeadaptivetoensureproperconditioningofthereceivedsignalindependentofthecablelength.
TheDP83815utilizesanextremelyrobustequalizationschemereferredtohereinas'DigitalAdaptiveEqualization'.
Traditionaldesignsuseapseudoadaptiveequalizationschemethatdeterminestheapproximatecablelengthbymonitoringsignalattenuationatcertainfrequencies.
Thisattenuationvaluewascomparedtotheinternalreceiveinputreferencevoltage.
Thiscomparisonwouldindicatetheamountofequalizationtouse.
AlthoughthisschemeisusedsuccessfullyontheDP83223Vtwister,itissensitivetotransformermismatch,resistorvariationandprocessinducedoffset.
TheDP83223Valsorequiredanexternalattenuationnetworktohelpmatchtheincomingsignalamplitudetotheinternalreference.
TheDigitalEqualizerremovesISI(InterSymbolInterference)fromthereceivedatastreambycontinuouslyadaptingtoprovideafilterwiththeinversefrequencyresponseofthechannel.
Whenusedinconjunctionwithagainstage,thisenablesthereceive'eyepattern'tobeopenedsufficientlytoallowveryreliabledatarecovery.
Traditionally'adaptive'equalizersselected1ofNfiltersinanattempttomatchthecablescharacteristics.
Thisapproachwilltypicallyleaveholesatcertaincablelengths,wheretheperformanceoftheequalizerisnotoptimized.
TheDP83815equalizeristrulyadaptive.
ThecurvesgiveninFigure3-10illustrateattenuationatcertainfrequenciesforgivencablelengths.
Thisisderivedfromtheworstcasefrequencyvs.
attenuationfiguresasspecifiedintheEIA/TIABulletinTSB-36.
Thesecurvesindicatethesignificantvariationsinsignalattenuationthatmustbecompensatedforbythereceiveadaptiveequalizationcircuit.
Figure3-11representsascrambledIDLEtransmittedoverzerometersofcableasmeasuredattheAII(ActiveInputInterface)ofthereceiver.
Figure3-12andFigure3-13representthesignaldegradationover50and100metersofcategoryVcablerespectively,alsomeasuredattheAII.
Theseplotsshowtheextremedegradationofsignalintegrityandindicatetherequirementforarobustadaptiveequalizer.
Figure3-9100BASE-TXBLWEventDiagram3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
26RevOwww.
national.
comDP838153.
10.
4LineQualityMonitorItispossibletodeterminetheamountofEqualizationbeingusedbyaccessingcertaintestregisterswiththeDSPengine.
Thisprovidesacrudeindicationofconnectedcablelength.
Thisfunctionallowsforaquickandsimpleverificationofthelinequalityinthatanysignificantdeviationfromanexpectedregistervalue(basedonaknowncablelength)wouldindicatethatthesignalqualityhasdeviatedfromtheexpectednominalcase.
3.
10.
5MLT-3toNRZIDecoderTheDP83815decodestheMLT-3informationfromtheDigitalAdaptiveEqualizerblocktobinaryNRZIdata.
Figure3-10EIA/TIAAttenuationvs.
Frequencyfor0,50,100,130&150metersofCATVcableFigure3-11MLT-3SignalMeasuredatAIIafter0metersofCATVcable2ns/divFigure3-12MLT-3SignalMeasuredatAIIafter50metersofCATVcableFigure3-13MLT-3SignalMeasuredatAIIafter100metersofCATVcable2ns/div2ns/div3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
27RevOwww.
national.
comDP838153.
10.
6ClockRecoveryModuleTheClockRecoveryModule(CRM)accepts125Mb/sMLT3datafromtheequalizer.
TheDPLLlocksontothe125Mb/sdatastreamandextractsa125MHzrecoveredclock.
TheextractedandsynchronizedclockanddataareusedasrequiredbythesynchronousreceiveoperationsasgenerallydepictedinFigure3-8.
TheCRMisimplementedusinganadvancedalldigitalPhaseLockedLoop(PLL)architecturethatreplacessensitiveanalogcircuitry.
UsingdigitalPLLcircuitryallowstheDP83815tobemanufacturedandspecifiedtotightertolerances.
3.
10.
7NRZItoNRZInatypicalapplication,theNRZItoNRZdecoderisrequiredinordertopresentNRZformatteddatatothede-scrambler(ortothecode-groupalignmentblock,ifthede-scramblerisbypassed,ordirectlytothePCS,ifthereceiverisbypassed).
3.
10.
8SerialtoParallelThe100BASE-TXreceiverincludesaSerialtoParallelconverterwhichsupplies5-bitwidedatasymbolstothePCSRxstatemachine.
3.
10.
9De-scramblerAserialde-scramblerisusedtode-scramblethereceivedNRZdata.
Thede-scramblerhastogenerateanidenticaldatascramblingsequence(N)inordertorecovertheoriginalunscrambleddata(UD)fromthescrambleddata(SD)asrepresentedintheequations:Synchronizationofthede-scramblertotheoriginalscramblingsequence(N)isachievedbasedontheknowledgethattheincomingscrambleddatastreamconsistsofscrambledIDLEdata.
Afterthede-scramblerhasrecognized12consecutiveIDLEcode-groups,whereanunscrambledIDLEcode-groupin5BNRZisequaltofiveconsecutiveones(11111),itwillsynchronizetothereceivedatastreamandgenerateunscrambleddataintheformofunaligned5Bcode-groups.
Inordertomaintainsynchronization,thede-scramblermustcontinuouslymonitorthevalidityoftheunscrambleddatathatitgenerates.
Toensurethis,alinestatemonitorandaholdtimerareusedtoconstantlymonitorthesynchronizationstatus.
Uponsynchronizationofthede-scramblertheholdtimerstartsa722scountdown.
UpondetectionofsufficientIDLEcode-groups(58bittimes)withinthe722speriod,theholdtimerwillresetandbeginanewcountdown.
Thismonitoringoperationwillcontinueindefinitelygivenaproperlyoperatingnetworkconnectionwithgoodsignalintegrity.
IfthelinestatemonitordoesnotrecognizesufficientunscrambledIDLEcode-groupswithinthe722speriod,theentirede-scramblerwillbeforcedoutofthecurrentstateofsynchronizationandresetinordertore-acquiresynchronization.
3.
10.
10Code-groupAlignmentThecode-groupalignmentmoduleoperatesonunaligned5-bitdatafromthede-scrambler(or,ifthede-scramblerisbypassed,directlyfromtheNRZI/NRZdecoder)andconvertsitinto5Bcode-groupdata(5bits).
Code-groupalignmentoccursaftertheJ/Kcode-grouppairisdetected.
OncetheJ/Kcode-grouppair(1100010001)isdetected,subsequentdataisalignedonafixedboundary.
3.
10.
114B/5BDecoderThecode-groupdecoderfunctionsasalookuptablethattranslatesincoming5Bcode-groupsinto4Bnibbles.
Thecode-groupdecoderfirstdetectstheJ/Kcode-grouppairprecededbyIDLEcode-groupsandreplacestheJ/KwithMACpreamble.
Specifically,theJ/K10-bitcode-grouppairisreplacedbythenibblepair(01010101).
Allsubsequent5Bcode-groupsareconvertedtothecorresponding4Bnibblesforthedurationoftheentirepacket.
ThisconversionceasesuponthedetectionoftheT/Rcode-grouppairdenotingtheEndofStreamDelimiter(ESD)orwiththereceptionofaminimumoftwoIDLEcode-groups.
3.
10.
12100BASE-TXLinkIntegrityMonitorThe100Base-TXLinkmonitorensuresthatavalidandstablelinkisestablishedbeforeenablingboththeTransmitandReceivePCSlayer.
Signaldetectmustbevalidfor395stoallowthelinkmonitortoenterthe'LinkUp'state,andenablethetransmitandreceivefunctions.
SignaldetectcanbeforcedactivebysettingBit1ofthePCSR.
SignaldetectcanbeoptionallyANDedwiththede-scramblerlockedindicationbysettingbit8ofthePCSR.
Whenthisoptionisenabled,thenDe-scrambler'locked'isrequiredtoentertheLinkUpstate,butonlySignaldetectisrequiredtomaintainthelinkinthelinkUpstate.
3.
10.
13BadSSDDetectionABadStartofStreamDelimiter(BadSSD)isanytransitionfromconsecutiveidlecode-groupstonon-idlecode-groupswhichisnotprefixedbythecode-grouppairJ/K.
Ifthisconditionisdetected,theDP83815willassertRXERandpresentRXD[3:0]=1110totheMACforthecyclesthatcorrespondtoreceived5Bcode-groupsuntilatleasttwoIDLEcodegroupsaredetected.
Inaddition,theFalseCarrierEventCounterwillbeincrementedbyone.
OnceatleasttwoIDLEcodegroupsaredetected,theerrorisreportedtotheMAC.
UDSDN()=SDUDN()=3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
28RevOwww.
national.
comDP838153.
1110BASE-TTransceiverModuleThe10BASE-TTransceiverModuleisIEEE802.
3compliant.
Itincludesthereceiver,transmitter,collision,heartbeat,loopback,jabber,andlinkintegrityfunctions,asdefinedinthestandard.
Anexternalfilterisnotrequiredonthe10BASE-TinterfacesincethisisintegratedinsidetheDP83815.
Thissectionfocusesonthegeneral10BASE-Tsystemleveloperation.
3.
11.
1OperationalModesTheDP83815hastwobasic10BASE-Toperationalmodes:—HalfDuplexmode-functionsasastandardIEEE802.
310BASE-TtransceiversupportingtheCSMA/CDprotocol.
—FullDuplexmode-capableofsimultaneouslytransmittingandreceivingwithoutreportingacollision.
TheDP83815's10Mb/sENDECisdesignedtoencodeanddecodesimultaneously.
3.
11.
2SmartSquelchThesmartsquelchisresponsiblefordeterminingwhenvaliddataispresentonthedifferentialreceiveinputs(RD±).
TheDP83815implementsanintelligentreceivesquelchtoensurethatimpulsenoiseonthereceiveinputswillnotbemistakenforavalidsignal.
Smartsquelchoperationisindependentofthe10BASE-Toperationalmode.
Thesquelchcircuitryemploysacombinationofamplitudeandtimingmeasurements(asspecifiedintheIEEE802.
310BASE-Tstandard)todeterminethevalidityofdataonthetwistedpairinputs(refertoFigure3-14).
Thesignalatthestartofpacketischeckedbythesmartsquelchandanypulsesnotexceedingthesquelchlevel(eitherpositiveornegative,dependinguponpolarity)willberejected.
Oncethisfirstsquelchlevelisovercomecorrectly,theoppositesquelchlevelmustthenbeexceededwithin150ns.
Finallythesignalmustagainexceedtheoriginalsquelchlevelwithina150nstoensurethattheinputwaveformwillnotberejected.
Thischeckingprocedureresultsinthelossoftypicallythreepreamblebitsatthebeginningofeachpacket.
Onlyafteralltheseconditionshavebeensatisfiedwillacontrolsignalbegeneratedtoindicatetotheremainderofthecircuitrythatvaliddataispresent.
Atthistime,thesmartsquelchcircuitryisreset.
Validdataisconsideredtobepresentuntilthesquelchlevelhasnotbeengeneratedforatimelongerthan150ns,indicatingtheEndofPacket.
OncegooddatahasbeendetectedthesquelchlevelsarereducedtominimizetheeffectofnoisecausingprematureEndofPacketdetection.
3.
11.
3CollisionDetectionWheninHalfDuplex,a10BASE-Tcollisionisdetectedwhenthereceiveandtransmitchannelsareactivesimultaneously.
CollisionsarereportedtotheMAC.
Collisionsarealsoreportedwhenajabberconditionisdetected.
IftheENDECisreceivingwhenacollisionisdetecteditisreportedimmediately(throughtheCOLsignal).
Whenheartbeatisenabled,approximately1safterthetransmissionofeachpacket,aSignalQualityError(SQE)signalofapproximately10bittimesisgeneratedtoindicatesuccessfultransmission.
TheSQEtestisinhibitedwhenthephysicallayerissetinfullduplexmode.
SQEcanalsobeinhibitedbysettingtheHEARTBEAT_DISbitintheTBTSCRregister.
3.
11.
4NormalLinkPulseDetection/GenerationThelinkpulsegeneratorproducespulsesasdefinedintheIEEE802.
310BASE-Tstandard.
Eachlinkpulseisnominally100nsindurationandtransmittedevery16msintheabsenceoftransmitdata.
Linkpulsesareusedtochecktheintegrityoftheconnectionwiththeremoteend.
Ifvalidlinkpulsesarenotreceived,thelinkdetectordisablesthe10BASE-Ttwistedpairtransmitter,receiverandcollisiondetectionfunctions.
Whenthelinkintegrityfunctionisdisabled(FORCE_LINK_10oftheTBTSCRregister),goodlinkisforcedandthe10BASE-Ttransceiverwilloperateregardlessofthepresenceoflinkpulses.
Figure3-1410BASE-TTwistedPairSmartSquelchOperationendofpacketstartofpacketVSQ-(reduced)VSQ-VSQ+(reduced)VSQ+150ns3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
29RevOwww.
national.
comDP838153.
11.
5JabberFunctionThejabberfunctionmonitorstheDP83815'soutputanddisablesthetransmitterifitattemptstotransmitapacketoflongerthanlegalsize.
Ajabbertimermonitorsthetransmitteranddisablesthetransmissionifthetransmitterisactiveforapproximately20-30ms.
Oncedisabledbythejabberfunction,thetransmitterstaysdisabledfortheentiretimethattheENDECmodule'sinternaltransmitenableisasserted.
Thissignalhastobede-assertedforapproximately400-600ms(the"unjab"time)beforethejabberfunctionre-enablesthetransmitoutputs.
TheJabberfunctionisonlymeaningfulin10BASE-Tmode.
3.
11.
6AutomaticLinkPolarityDetectionTheDP83815's10BASE-Ttransceivermoduleincorporatesanautomaticlinkpolaritydetectioncircuit.
WhensevenconsecutivelinkpulsesorthreeconsecutivereceivepacketswithinvertedEnd-of-Packetpulsesarereceived,badpolarityisreported.
Apolarityreversalcanbecausedbyawiringerrorateitherendofthecable,usuallyattheMainDistributionFrame(MDF)orpatchpanelinthewiringcloset.
Thebadpolarityconditionislatched.
TheDP83815's10BASE-Ttransceivermodulecorrectsforthiserrorinternallyandwillcontinuetodecodereceiveddatacorrectly.
Thiseliminatestheneedtocorrectthewiringerrorimmediately.
3.
11.
710BASE-TInternalLoopbackWhentheLOOPBACKbitintheBMCRregisterisset,10BASE-TtransmitdataisloopedbackintheENDECtothereceivechannel.
Thetransmitdriversandreceiveinputcircuitryaredisabledintransceiverloopbackmode,isolatingthetransceiverfromthenetwork.
Loopbackisusedfordiagnostictestingofthedatapaththroughthetransceiverwithouttransmittingonthenetworkorbeinginterruptedbyreceivetraffic.
Thisloopbackfunctioncausesthedatatoloopbackjustpriortothe10BASE-Toutputdriverbufferssuchthattheentiretransceiverpathistested.
3.
11.
8TransmitandReceiveFilteringExternal10BASE-TfiltersarenotrequiredwhenusingtheDP83815,astherequiredsignalconditioningisintegratedintothedevice.
Onlyisolation/step-uptransformersandimpedancematchingresistorsarerequiredforthe10BASE-Ttransmitandreceiveinterface.
Theinternaltransmitfilteringensuresthatalltheharmonicsinthetransmitsignalareattenuatedbyatleast30dB.
3.
11.
9TransmitterTheencoderbeginsoperationwhenthetransmitenableinputtothephysicallayerisassertedandconvertsNRZdatatopre-emphasizedManchesterdataforthetransceiver.
Forthedurationofassertion,theserializedtransmitdataisencodedforthetransmit-driverpair(TD±).
Thelasttransitionisalwayspositive;itoccursatthecenterofthebitcellifthelastbitisaone,orattheendofthebitcellifthelastbitisazero.
3.
11.
10ReceiverThedecoderconsistsofadifferentialreceiverandaPLLtoseparateaManchesterencodeddatastreamintointernalclocksignalsanddata.
Thedifferentialinputmustbeexternallyterminatedwithadifferential100terminationnetworktoaccommodateUTPcable.
TheinternalimpedanceofRD±(typically1.
1Kohms)isinparallelwithtwo54.
9resistorstoapproximatethe100termination.
Thedecoderdetectstheendofaframewhennomoremid-bittransitionsaredetected.
3.
11.
11FarEndFaultIndicationAuto-NegotiationprovidesamechanismfortransferringinformationfromtheLocalStationtotheLinkPartnerthataremotefaulthasoccurredfor100BASE-TX.
Aremotefaultisanerrorinthelinkthatonestationcandetectwhiletheothercannot.
Anexampleofthisisadisconnectedfiberatastation'stransmitter.
ThisstationwillbereceivingvaliddataanddetectthatthelinkisgoodviatheLinkIntegrityMonitor,butwillnotbeabletodetectthatitstransmissionisnotpropagatingtotheotherstation.
IfthreeormoreFEFIIDLEpatternsaredetectedbytheDP83815,thenbit4oftheBasicModeStatusregisterissettooneuntilreadbymanagement,additionallybit7ofthePHYStatusregisterisalsoset.
ThefirstFEFIIDLEpatternmaycontainmorethan84onesasthepatternmayhavestartedduringanormalIDLEtransmissionwhichisactuallyquitelikelytooccur.
However,sinceFEFIisarepeatingpattern,thiswillnotcauseaproblemwiththeFEFIfunction.
ItshouldbenotedthatreceiptoftheFEFIIDLEpatternwillnotcauseaCarrierSenseerrortobereported.
IftheFEFIfunctionhasbeendisabledviaFEFI_EN(bit3)ofthePCSRConfigurationregister,thentheDP83815willnotsendtheFEFIIDLEpattern.
3.
12802.
3uMIITheDP83815incorporatestheMediaIndependentInterface(MII)asspecifiedinClause22oftheIEEE802.
3ustandard.
ThisinterfacemaybeusedtoconnectPHYdevices.
ThissectiondescribestheMIIconfigurationstepsaswellastheserialMIImanagementinterfaceandnibblewideMIIdatainterface.
3.
12.
1MIIAccessConfigurationTheDP83815mustbespecificallyconfiguredforaccessingtheMII.
Thisisdonebyfirstconnectingpin133(MD1/CFGDISN)toGNDthrougha1Kresistor.
Thensettingbit12(EXT_PHY)oftheCFGregister(offset04h)to1.
SeeSection4.
2.
2.
Whenthisbitisset,theinternalPhyisautomaticallydisabled,asreportedbybit9(PHY_DIS)oftheCFGregister.
TheMIImustthenberesetbeforetheexternalPHYcanbedetected.
IfexternalMIIisnotselectedasdescribedthentheinternalPhyisusedandtheMIIpinsoftheMacPhytercanbeleftunconnected.
3.
12.
2MIISerialManagementTheMIIserialmanagementinterfaceallowsfortheconfigurationandcontrolofPHYregisters,gatheringofstatus,errorinformation,andthedeterminationofthetypeandcapabilitiesoftheattachedPHY(s).
TheMIIserialmanagementspecificationdefinesasetofthirty-two16-bitstatusandcontrolregistersthatareaccessiblethroughthemanagementinterfacepinsMDCandMDIO.
Adescriptionoftheserialmanagementinterfaceaccessandaccessprotocolfollows.
3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
30RevOwww.
national.
comDP838153.
12.
3MIISerialManagementAccessManagementaccesstothePHY(s)isdoneviaManagementDataClock(MDC)andManagementDataInput/Output(MDIO).
MDChasamaximumclockrateof25MHzandnominimumrate.
TheMDIOlineisbi-directionalandmaybesharedbyupto32devices.
TheinternalPHYcountsasoneofthese32devices.
TheinternalPHYhastheadvantageofhavingdirectregisteraccessbutcanalsobecontrolledexactlylikeaPHY,withadefaultaddressof1Fh,connectedtotheMII.
AccessandcontroloftheMDCandMDIOpinsisdoneviatheMII/EEPROMAccessRegister(MEAR).
Theclock(MDC)iscreatedbyalternatingwritesof0then1totheMDCbit(bit6).
ControlofdatadirectionisdonebytheMDDIRbit(bit5).
DataiseitherrecordedorwrittenbytheMDIObit(bit4).
SettingtheMDDIRbittoa1allowstheDP83815todrivetheMDIOpin.
SettingtheMDDIRbittoa0allowstheMDIObittoreflectthevalueoftheMDIOpin.
SeeSection4.
2.
3Thisbit-bangaccessoftheMDCandMDIOpinsthusrequires64accessestotheMEARregistertocompleteasinglePHYregistertransaction.
SinceaPHYdeviceistypicallyselfconfiguringandadaptivethisserialmanagementaccessisusuallyonlyrequiredatinitializationtimeandthereforeisnottimecritical.
3.
12.
4SerialManagementAccessProtocolTheserialcontrolinterfaceclock(MDC)hasamaximumclockrateof25MHzandnominimumrate.
TheMDIOlineisbi-directionalandmaybesharedbyupto32devices.
TheMDIOframeformatisshowninTable3-2.
IfexternalPHYdevicesmaybeattachedandremovedfromtheMIIthereshouldbea15Kpull-downresistorontheMDIOsignal.
IfthePHYwillalwaysbeconnectedthenthereshouldbea1.
5kpull-upresistorwhich,duringIDLEandturnaround,willpullMDIOhigh.
InordertoinitializetheMDIOinterface,theDP83815sendsasequenceof32contiguouslogiconesonMDIOprovidesthePHY(s)withasequencethatcanbeusedtoestablishsynchronization.
ThispreamblemaybegeneratedeitherbydrivingMDIOhighfor32consecutiveMDCclockcycles,orbysimplyallowingtheMDIOpull-upresistortopulltheMDIOpinhighduringwhichtime32MDCclockcyclesareprovided.
Inaddition32MDCclockcyclesshouldbeusedtore-syncthedeviceifaninvalidstart,opcode,orturnaroundbitisdetected.
TheStartcodeisindicatedbyapattern.
ThisassurestheMDIOlinetransitionsfromthedefaultidlelinestate.
TurnaroundisdefinedasanidlebittimeinsertedbetweentheRegisterAddressfieldandtheDatafield.
Toavoidcontentionduringareadtransaction,nodeviceshallactivelydrivetheMDIOsignalduringthefirstbitofTurnaround.
TheaddressedPHYdrivestheMDIOwithazeroforthesecondbitofturnaroundandfollowsthiswiththerequireddata.
Figure3-15showsthetimingrelationshipbetweenMDCandtheMDIOasdriven/receivedbytheDP83815andaPHYforatypicalregisterreadaccess.
Forwritetransactions,theDP83815writesdatatotheaddressedPHYthuseliminatingtherequirementforMDIOTurnaround.
TheTurnaroundtimeisfilledbytheDP83815byinserting.
Figure3-16showsthetimingrelationshipforatypicalMIIregisterwriteaccess.
3.
12.
5Nibble-wideMIIDataInterfaceClause22oftheIEEE802.
3uspecificationdefinestheMediaIndependentInterface.
Thisinterfaceincludeseparatededicatedreceiveandtransmitbusses.
Thesetwodatabuses,alongwithvariouscontrolandindicationsignals,allowforthesimultaneousexchangeofdatabetweentheDP83815andPHY(s).
Table3-2TypicalMDIOFrameFormatMIIManagementSerialProtocolReadOperationWriteOperationFigure3-15TypicalMDC/MDIOReadOperationMDCMDIO00011110000000(STA)IdleStartOpcode(Read)PHYAddress(PHYAD=0Ch)RegisterAddress(00h=BMCR)TARegisterDataZMDIO(PHY)ZZZ00011000100000000ZIdleZZ3.
0FunctionalDescription(Continued)Subjecttochangewithoutnotice.
31RevOwww.
national.
comDP83815ThereceiveinterfaceconsistsofanibblewidedatabusRXD[3:0],areceiveerrorsignalRXER,areceivedatavalidflagRXDV,andareceiveclockRXCLKforsynchronoustransferofthedata.
Thereceiveclockcanoperateat2.
5MHztosupport10Mb/soperationmodesorat25MHztosupport100Mb/soperationalmodes.
ThetransmitinterfaceconsistsofanibblewidedatabusTXD[3:0],atransmitenablecontrolsignalTXEN,andatransmitclockTXCLKwhichrunsat2.
5MHzor25MHz.
Additionally,theMIIincludesthecarriersensesignalCRS,aswellasacollisiondetectsignalCOL.
TheCRSsignalassertstoindicatethereceptionofdatafromthenetworkorasafunctionoftransmitdatainHalfDuplexmode.
TheCOLsignalassertsasanindicationofacollisionwhichcanoccurduringhalf-duplexoperationwhenbothatransmitandreceiveoperationoccursimultaneously.
3.
12.
6CollisionDetectionForHalfDuplex,a10BASE-Tor100BASE-TXcollisionisdetectedwhenthereceiveandtransmitchannelsareactivesimultaneously.
CollisionsarereportedbytheCOLsignalontheMII.
IfthePHYistransmittingin10Mb/smodewhenacollisionisdetected,thecollisionisnotreporteduntilsevenbitshavebeenreceivedwhileinthecollisionstate.
Thispreventsacollisionbeingreportedincorrectlyduetonoiseonthenetwork.
TheCOLsignalremainssetforthedurationofthecollision.
Ifacollisionoccursduringareceiveoperation,itisimmediatelyreportedbytheCOLsignal.
Whenheartbeatisenabled(onlyapplicableto10Mb/soperation),approximately1safterthetransmissionofeachpacket,aSignalQualityError(SQE)signalofapproximately10bittimesisgenerated(internally)toindicatesuccessfultransmission.
SQEisreportedasapulseontheCOLsignaloftheMII.
3.
12.
7CarrierSenseCarrierSense(CRS)isassertedduetoreceiveactivity,oncevaliddataisdetected,during10Mb/soperation.
During100Mb/soperationCRSisassertedwhenavalidlink(SD)andtwonon-contiguouszerosaredetected.
For10or100Mb/sHalfDuplexoperation,CRSisassertedduringeitherpackettransmissionorreception.
For10or100Mb/sFullDuplexoperation,CRSisassertedonlyduetoreceiveactivity.
CRSisde-assertedfollowinganendofpacket.
Figure3-16TypicalMDC/MDIOWriteOperationMDCMDIO00011110000000(STA)IdleStartOpcode(Write)PHYAddress(PHYAD=0Ch)RegisterAddress(00h=BMCR)TARegisterDataZ00000000000000ZIdle1000ZZ32www.
national.
comDP838154.
0RegisterSet4.
1ConfigurationRegistersTheDP83815implementsaPCIversion2.
2configurationregisterspace.
ThisallowsaPCIBIOSto"soft"configuretheDP83815.
SoftwareResethasnoeffectonconfigurationregisters.
HardwareResetreturnsallconfigurationregisterstotheirhardwareresetstate.
Forallunusedregisters,writesareignored,andreadsreturn0.
Table4-1ConfigurationRegisterMap4.
1.
1ConfigurationIdentificationRegisterThisregisteridentifiestheDP83815ControllertoPCIsystemsoftware.
OffsetTagDescriptionAccess00hCFGIDConfigurationIdentificationRegisterRO04hCFGCSConfigurationCommandandStatusRegisterR/W08hCFGRIDConfigurationRevisionIDRegisterRO0ChCFGLATConfigurationLatencyTimerRegisterRO10hCFGIOAConfigurationIOBaseAddressRegisterR/W14hCFGMAConfigurationMemoryAddressRegisterR/W18h-28hReserved(readsreturnzero)2ChCFGSIDConfigurationSubsystemIdentificationRegisterRO30hCFGROMBootROMconfigurationregisterR/W34hCAPPTRCapabilitiesPointerRegisterRO38hReserved(readsreturnzero)3ChCFGINTConfigurationInterruptSelectRegisterR/W40hPMCAPPowerManagementCapabilitiesRegisterRO44hPMCSRPowerManagementControlandStatusRegisterR/W48-FFhReserved(readsreturnzero)Tag:CFGIDSize:32bitsHardReset:0020100BhOffset:00hAccess:ReadOnlySoftReset:UnchangedBitBitNameDescription31-16DEVIDDeviceIDThisfieldisread-onlyandissettothedeviceIDassignedbyNationalSemiconductortotheDP83815,whichis0020h.
15-0VENIDVendorIDThisfieldisread-onlyandissettoavalueof100BhwhichisNationalSemiconductor'sPCIVendorID.
33www.
national.
com4.
0RegisterSet(Continued)DP838154.
1.
2ConfigurationCommandandStatusRegisterTheCFGCSregisterhastwoparts.
Theupper16-bits(31-16)aredevotedtodevicestatus.
Astatusbitisresetwhenevertheregisteriswritten,andthecorrespondingbitlocationisa1.
Thelower16-bits(15-0)aredevotedtocommandandareusedtoconfigureandcontrolthedevice.
Tag:CFGCSSize:32bitsHardReset:02900000hOffset:04hAccess:ReadWriteSoftReset:UnchangedBitBitNameDescription31DPERRDetectedParityErrorRefertothedescriptioninthePCIV2.
2specification.
30SSERRSignaledSERRRefertothedescriptioninthePCIV2.
2specification.
29RMABTReceivedMasterAbortRefertothedescriptioninthePCIV2.
2specification.
28RTABTReceivedTargetAbortRefertothedescriptioninthePCIV2.
2specification.
27STABTSentTargetAbortRefertothedescriptioninthePCIV2.
2specification.
26-25DSTIMDEVSELNTimingThisfieldwillalwaysbesetto01indicatingthatDP83815supports"medium"DEVSELNtiming.
24DPDDataParityDetectedRefertothedescriptioninthePCIV2.
2specification.
23FBBFastBack-to-BackCapableDP83815willsetthisbitto1.
22-21unused(readsreturn0)20NCPENNewCapabilitiesEnableWhenset,thisbitindicatesthattheCapabilitiesPointercontainsavalidvalueandnewcapabilitiessuchaspowermanagementaresupported.
Whenclear,newcapabilities(CAPPTR,PMCAP,PMCS)aredisabled.
ThevalueinthisregisterwilleitherbeloadedfromtheEEPROMor,iftheEEPROMisdisabled,fromastrapoptionatreset.
19-16Unused(readsreturn0)15-10Unused(readsreturn0)9FBBENFastBack-to-BackEnableSetto1bythePCIBIOStoenabletheDP83815todoFastBack-to-Backtransfers(FBBtransfersasamasterisnotimplementedinthecurrentrevision).
8SERRENSERRNEnableWhenSERRENandPERRSPareset,DP83815willgenerateSERRNduringtargetcycleswhenanaddressparityerrorisdetectedfromthesystem.
Also,whenSERRENandPERRSParesetandCFG:PESELisreset,mastercyclesdetectingdataparityerrorswillgenerateSERRN.
7Unused(readsreturn0)34www.
national.
com4.
0RegisterSet(Continued)DP838154.
1.
3ConfigurationRevisionIDRegisterThisregisterstoresthesiliconrevisionnumber,revisionnumberofsoftwareinterfacespecificationandletstheconfigurationsoftwareknowthatitisanEthernetcontrollerintheclassofnetworkcontrollers.
BitBitNameDescription6PERRSPParityErrorResponseWhenset,DP83815willassertPERRNonthedetectionofadataparityerrorwhenactingasthetarget,andwillsamplePERRNwhenactingastheinitiator.
Also,settingPERRSPallowsSERRENtoenabletheassertionofSERRN.
Whenreset,alladdressanddataparityerrorsareignoredandneitherSERRNnorPERRNareasserted.
5-3Unused(readsreturn0)2BMENBusMasterEnableWhenset,DP83815isallowedtoactasaPCIbusmaster.
Whenreset,DP83815isprohibitedfromactingasaPCIbusmaster.
1MSENMemorySpaceAddressWhenset,DP83815respondstomemoryspaceaccesses.
Whenreset,DP83815ignoresmemoryspaceaccesses.
0I/OSENI/OSpaceAccessWhenset,DP83815respondstoI/Ospaceaccesses.
Whenreset,DP83815ignoresI/Ospaceaccesses.
Tag:CFGRIDSize:32bitsHardReset:02000000hOffset:08hAccess:ReadOnlySoftReset:UnchangedBitBitNameDescription31-24BASECLBaseClassReturns02hwhichspecifiesanetworkcontroller.
23-16SUBCLSubClassReturns00hwhichspecifiesanEthernetcontroller.
15-8PROGIFProgrammingIFReturns00hwhichspecifiesthefirstreleaseoftheDP83815SoftwareInterfaceSpecification.
7-0REVIDSiliconRevisionReturns00hwhichspecifiesthesiliconrevision.
35www.
national.
com4.
0RegisterSet(Continued)DP838154.
1.
4ConfigurationLatencyTimerRegisterThisregistergivesstatusandcontrolssuchmiscellaneousfunctionsasBIST,LatencytimerandCachelinesize.
DP83815BusMasterOperations:Independentofcachelinesize,theDP83815willusethefollowingPCIcommandsforbusmasteredtransfers:0110-MemReadforallreadcycles,0111-MemWriteforallwritecycles.
4.
1.
5ConfigurationI/OBaseAddressRegisterThisregisterspecifiestheBaseI/Oaddresswhichisrequiredtobuildanaddressmapduringconfiguration.
ItalsospecifiesthenumberofbytesrequiredaswellasanindicationthatitcanbemappedintoI/Ospace.
Tag:CFGLATSize:32bitsHardReset:00000000hOffset:0ChAccess:ReadWriteSoftReset:UnchangedBitBitNameDescription31BISTCAPBISTCapableReadswillalwaysreturn0.
30BISTENBISTEnableReadswillreturna0,writesareignored.
29-16ReservedReadswillreturna0,writesareignored.
15-8LATLatencyTimerSetbysoftwaretothenumberofPCIclocksthatDP83815mayholdthePCIbus.
7-0CLSCacheLineSizeIgnoredbyDP83815.
Tag:CFGIOASize:32bitsHardReset:00000001hOffset:10hAccess:ReadWriteSoftReset:UnchangedBitBitNameDescription31-8IOBASEBaseI/OAddressThisissetbysoftwaretothebaseI/OaddressfortheOperationalRegisterMap.
7-2IOSIZESizeindicationReadbackas0.
ThisallowsthePCIbridgetodeterminethattheDP83815requires256bytesofI/Ospace.
1Unused(readsreturn0).
0IOINDI/OSpaceIndicatorSetto1byDP83815toindicatethatDP83815iscapableofbeingmappedintoI/Ospace.
ReadOnly.
36www.
national.
com4.
0RegisterSet(Continued)DP838154.
1.
6ConfigurationMemoryAddressRegisterThisregisterspecifiestheBaseMemoryaddresswhichisrequiredtobuildanaddressmapduringconfiguration.
Italsospecifiesthenumberofbytesrequiredaswellasanindicationthatitcanbemappedintomemoryspace.
4.
1.
7ConfigurationSubsystemIdentificationRegisterTheCFGSIDallowssystemsoftwaretodistinguishbetweendifferentsubsystemsbasedonthesamePCIsilicon.
ThevaluesinthisregistercanbeloadedfromtheEEPROMifconfigurationisenabled.
Tag:CFGMASize:32bitsHardReset:00000000hOffset:14hAccess:ReadWriteSoftReset:unchangedBitBitNameDescription31-12MEMBASEMemoryBaseAddressThisissetbysoftwaretothebaseaddressfortheOperationalRegisterMap.
11-4MEMSIZEMemorySizeThesebitsreturn0,whichindicatesthattheDP83815requires4096bytesofMemorySpace(theminimumrecommendedallocation).
3MEMPFPrefetchableSetto0byDP83815.
ReadOnly.
2-1MEMLOCLocationSelectionSetto00byDP83815.
Thisindicatesthatthebaseregisteris32-bitswideandcanbeplacedanywhereinthe32-bitmemoryspace.
ReadOnly.
0MEMINDMemorySpaceIndicatorSetto0byDP83815toindicatethatDP83815iscapableofbeingmappedintomemoryspace.
ReadOnly.
Tag:CFGSIDSize:32bitsHardReset:00000000hOffset:2ChAccess:ReadOnlySoftReset:unchangedBitBitNameDescription31-16SDEVIDSubsystemDeviceIDSetto0byDP83815.
15-0SVENIDSubsystemVendorIDSetto0byDP83815.
37www.
national.
com4.
0RegisterSet(Continued)DP838154.
1.
8BootROMConfigurationRegister4.
1.
9CapabilitiesPointerRegisterThisregisterstoresthecapabilitieslinkedlistoffsetintothePCIconfigurationspace.
Tag:CFGROMSize:32bitsHardReset:00000000hOffset:30hAccess:ReadWriteSoftReset:unchangedBitBitNameDescription31-16ROMBASEROMBaseAddressSettothebaseaddressforthebootROM.
15-11ROMSIZEROMSizeSetto0indicatingarequirementfor64KbytesofBootROMspace.
Readonly.
10-1unused(readsreturn0)0ROMENROMEnableThisisusedbythePCIBIOStoenableaccessestobootROM.
ThisallowstheDP83815tosharetheaddressdecodelogicbetweenthebootROManditself.
TheBIOSwillcopythecontentsofthebootROMtosystemRAMbeforeexecutingit.
Setto1enablestheaddressdecodeforbootROMdisablingaccesstooperationaltargetregisters.
Tag:CAPPTRSize:32bitsHardReset:00000040hOffset:34hAccess:ReadOnlySoftReset:unchangedBitBitNameDescription31-8unused(readsreturn0)7-0CLOFSCapabilitiesListOffsetOffsetintoPCIconfigurationspaceforthelocationofthefirstitemintheCapabilitiesLinkedList,setto40htopointtothePMCAPregister.
38www.
national.
com4.
0RegisterSet(Continued)DP838154.
1.
10ConfigurationInterruptSelectRegisterThisregisterstorestheinterruptlinenumberasidentifiedbythePOSTsoftwarethatisconnectedtotheinterruptcontrolleraswellasDP83815desiredsettingsformaximumlatencyandminimumgrant.
MaxlatencyandMinlatencycanbeloadedfromtheEEPROM.
4.
1.
11PowerManagementCapabilitiesRegisterThisregisterprovidesinformationonthecapabilitiesofthefunctionsrelatedtopowermanagement.
ThisregisteralsocontainsapointertothenextiteminthecapabilitieslistandthecapabilityIDforPowerManagement.
ThisregisterisonlyvisibleifCFGCS[4]isset.
Tag:CFGINTSize:32bitsHardReset:340b0100hOffset:3ChAccess:ReadWriteSoftReset:unchangedBitBitNameDescription31-24MXLATMaximumLatencyTheDP83815desiredsettingforMaxLatency.
TheDP83815willinitializethisfieldto52d(13sec).
ThevalueinthisregistercanbeloadedfromtheEEPROM.
23-16MNGNTMinimumGrantTheDP83815desiredsettingforMinimumGrant.
TheDP83815willinitializethisfieldto11d(2.
75usec).
ThevalueinthisregistercanbeloadedfromtheEEPROM.
15-8IPINInterruptPinReadOnly,alwaysreturn00000001(INTA).
7-0ILINEInterruptLineSettowhichlineontheinterruptcontrollerthattheDP83815'sinterruptpinisconnectedto.
Tag:PMCAPSize:32bitsHardReset:FF820001Offset:40hAccess:ReadOnlySoftReset:unchangedBitBitNameDescription31-27PMESPMESupportThis5bitfieldindicatesthepowerstatesinwhichDP83815mayassertPMEN.
A1indicatesPMENisenabledforthatstate,a0indicatesPMENisinhibitedinthatstate.
XXXX1-PMENcanbeassertedfromstateD0XXX1X-PMENcanbeassertedfromstateD1XX1XX-PMENcanbeassertedfromstateD2X1XXX-PMENcanbeassertedfromstateD3hot1XXXX-PMENcanbeassertedfromstateD3coldTheDP83815willonlyreportPMEsupportforD3coldifauxiliarypowerisdetectedonthe3VAUXpin,inadditionthisvaluecanbeloadedfromtheEEPROMwhenintheD3coldstate.
26D2SD2SupportThisbitissettoa1whentheDP83815supportstheD2state.
25D1SD1SupportThisbitissettoa1whentheDP83815supportstheD1state.
39www.
national.
com4.
0RegisterSet(Continued)DP838154.
1.
12PowerManagementControlandStatusRegisterThisregistercontainsPMcontrolandstatusinformation.
BitBitNameDescription24-22AUX_CURRENTAux_CurrentThis3bitfieldreportsthe3.
3VauxauxiliarycurrentrequirementsforthePCIfunction.
IfPMENgenerationfromD3coldisnotsupportedbythefunction(PMCAP[31]),thisfieldreturnsavalueof"000b"whenread.
Bit3.
3Vaux242322Max.
CurrentRequired110320mA0000(selfpowered)21DSIDeviceSpecificInitializationThisbitissetto1toindicatetothesystemthatinitializationoftheDP83815deviceisrequired(beyondthestandardPCIconfigurationheader)beforethegenericclassdevicedriverisabletouseit.
A1indicatesthatDP83815requiresaDSIsequencefollowingtransitiontotheD0uninitializedstate.
ThisbitcanbeloadedfromtheEEPROM.
20Reserved(readsreturn0)19PMECPMEClockReturns0toindicatePCIclocknotneededforPMEN.
18-16PMVPowerManagementVersionThisbitfieldindicatescompliancetoaspecificPMspecificationrevlevel.
Currentlysetto010b.
15-8NLIPTRNextListItemPointerOffsetintoPCIconfigurationspaceforthelocationofthenextitemintheCapabilitiesLinkedList.
Returns00hasnoothercapabilitiesareoffered.
7-0CAPIDCapabilityIDAlwaysreturns01hforPowerManagementID.
Tag:PMCSRSize:32bitsHardReset:00000000hOffset:44hAccess:ReadWriteSoftReset:unchangedBitBitNameDescription31-24Reserved(readsreturn0)23-16BSEBridgeSupportExtensionsunused(readsreturn0)15PMESTSPMEStatusStickybitwhichrepresentsthestateofthePMElogic,regardlessofthestateofthePMEENbit.
14-9Reserved(readsreturn0)8PMEENPMEEnableWhensetto1,thisbitenablestheassertionofthePMEfunctiononthePMENpin.
When0,thePMENpinisforcedtobeinactive.
ThisvaluecanbeloadedfromtheEEPROM.
7-2Unused(readsreturn0)1-0PSTATEPowerStateThis2bitfieldisusedtodeterminethecurrentpowerstateofDP83815,andtosetanewpowerstate.
00-D010-D201-D111-D3hot/cold40www.
national.
com4.
0RegisterSet(Continued)DP838154.
2OperationalRegistersTheDP83815providesthefollowingsetofoperationalregistersmappedintoPCImemoryspaceorI/Ospace.
Writestoreservedregisterlocationsareignored.
Readstoreservedregisterlocationsreturnundefinedvalues.
Table4-2OperationalRegisterMapOffsetTagDescriptionAccessMAC/BIURegisters00hCRCommandRegisterR/W04hCFGConfigurationRegisterR/W08hMEAREEPROMAccessRegisterR/W0ChPTSCRPCITestControlRegisterR/W10hISRInterruptStatusRegisterRO14hIMRInterruptMaskRegisterR/W18hIERInterruptEnableRegisterR/W1ChReserved20hTXDPTransmitDescriptorPointerRegisterR/W24hTXCFGTransmitConfigurationRegisterR/W28-2ChReserved30hRXDPReceiveDescriptorPointerRegisterR/W34hRXCFGReceiveConfigurationRegisterR/W38Reserved3ChCCSRCLKRUNControl/StatusRegisterR/W40hWCSRWakeonLANControl/StatusRegisterR/W44hPCRPauseControl/StatusRegisterR/W48hRFCRReceiveFilter/MatchControlRegisterR/W4ChRFDRReceiveFilter/MatchDataRegisterR/W50hBRARBootROMAddressR/W54hBRDRBootROMDataR/W58hSRRSiliconRevisionRegisterRO5ChMIBCManagementInformationBaseControlRegisterR/W60-78hMIBManagementInformationBaseDataRegistersRO7ChReservedInternalPhyRegisters80hBMCRBasicModeControlRegisterR/W84hBMSRBasicModeStatusRegisterRO88hPHYIDR1PHYIdentifierRegister#1RO8ChPHYIDR2PHYIdentifierRegister#2RO90hANARAuto-NegotiationAdvertisementRegisterR/W94hANLPARAuto-NegotiationLinkPartnerAbilityRegisterR/W98hANERAuto-NegotiationExpansionRegisterR/W9ChANNPTRAuto-NegotiationNextPageTXR/WA0-BChReservedReservedC0hPHYSTSPHYStatusRegisterROC4hMICRMIIInterruptControlRegisterRWC8hMISRMIIInterruptStatusRegisterRWCChReservedReservedD0hFCSCRFalseCarrierSenseCounterRegisterR/WD4hRECRReceiveErrorCounterRegisterR/WD8hPCSR100Mb/sPCSConfigurationandStatusRegisterR/WDCh-E0hReservedReservedE4hPHYCRPHYControlRegisterR/WE8hTBTSCR10Base-TStatus/ControlRegisterR/WECh-FChReservedReserved41www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
1CommandRegisterThisregisterisusedforissuingcommandstoDP83815.
Thesecommandsareissuedbysettingthecorrespondingbitsforthefunction.
Aglobalsoftwareresetalongwithindividualresetandenable/disablefortransmitterandreceiverareprovidedhere.
Tag:CRSize:32bitsHardReset:00000000hOffset:0000hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31-9unused8RSTResetSetto1toforcetheDP83815toasoftresetstatewhichdisablesthetransmitterandreceiver,reinitializestheFIFOs,andresetsallaffectedregisterstotheirsoftresetstate.
ThisoperationimpliesbothaTXRandaRXR.
Thisbitwillreadbacka1duringtheresetoperation,andbeclearedto0bythehardwarewhentheresetoperationiscomplete.
EEPROMconfigurationinformationisnotloadedhere.
7SWISoftwareInterruptSettingthisbittoa1forcestheDP83815togenerateahardwareinterrupt.
Thisinterruptismask-ableviatheIMR.
6unused5RXRReceiverResetWhensettoa1,thisbitcausesthecurrentpacketreceptiontobeaborted,thereceivedataandstatusFIFOstobeflushed,andthereceivestatemachinetoentertheidlestate(RXEgoesto0).
Thisisawrite-onlybitandisalwaysreadbackas0.
4TXRTransmitResetWhensettoa1,thisbitcausesthecurrenttransmissiontobeaborted,thetransmitdataandstatusFIFOstobeflushed,andthetransmitstatemachinetoentertheidlestate(TXEgoesto0).
Thisisawrite-onlybitandisalwaysreadbackas0.
3RXDReceiverDisableDisablethereceivestatemachineafteranycurrentpacketsinprogress.
WhenthisoperationhasbeencompletedtheRXEbitwillbeclearedto0.
Thisisawrite-onlybitandisalwaysreadbackas0.
ThedrivershouldnotsetbothRXDandRXEinthesamewrite,theRXEwillbeignored,andRXDwillhaveprecedence.
2RXEReceiverEnableWhensettoa1,andthereceivestatemachineisidle,thenthereceivemachinebecomesactive.
Thisbitwillreadbackasa1wheneverthereceivestatemachineisactive.
Afterinitialpower-up,softwaremustinsurethatthereceiverhascompletelyresetbeforesettingthisbit(SeeISR:RXRCMP).
1TXDTransmitDisableWhensettoa1,haltsthetransmitterafterthecompletionofthecurrentpacket.
Thisisawrite-onlybitandisalwaysreadbackas0.
ThedrivershouldnotsetbothTXDandTXEinthesamewrite,theTXEwillbeignored,andTXDwillhaveprecedence.
0TXETransmitEnableWhensettoa1,andthetransmitstatemachineisidle,thenthetransmitstatemachinebecomesactive.
Thisbitwillreadbackasa1wheneverthetransmitstatemachineisactive.
Afterinitialpower-up,softwaremustinsurethatthetransmitterhascompletelyresetbeforesettingthisbit(SeeISR:TXRCMP).
42www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
2ConfigurationandMediaStatusRegisterThisregisterallowsconfigurationofavarietyofdeviceandphyoptions,andprovidesphystatusinformation.
Tag:CFGSize:32bitsHardReset:00000000hOffset:0004hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31LNKSTSLinkStatusLinkstatusoftheinternalphy.
Assertedwhenlinkisgood.
RO30SPEED100Speed100Mb/sSpeed100Mb/sindicatorforinternalphy.
Assertedwhenspeedissetorhasnegotiatedto100Mb/s.
De-assertedwhenspeedhasbeensetornegotiatedto10Mb/s.
RO29FDUPFullDuplexFullDuplexindicatorforinternalphy.
AssertedwhenduplexmodeissetorhasnegotiatedtoFULL.
De-assertedwhenduplexmodehasbeensetornegotiatedtoHALF.
RO28POL10Mb/sPolarityIndicationTwistedpairpolarityindicatorforinternalphy.
Assertedwhenoperatingand10Mb/sandthepolarityhasbeendetectedasreversed.
De-assertedwhenpolarityisnormalorphyisoperatingat100Mb/s.
RO27ANEG_DNAuto-negotiationDoneAuto-negotiationdoneindicatorfrominternalphy.
Assertedwhenauto-negotiationprocesshascompletedorisnotactive.
RO26-24unused23-18PHY_CFGPhyConfigurationMiscellaneousinternalphyPower-On-Resetconfigurationcontrolbits.
17PINT_ACENPhyInterruptAutoClearEnableWhensettoa1,thisbitallowsthephyinterruptsourcetobeautomaticallyclearedwhenevertheISRisread.
Whenthisbitis0,thephyinterruptsourcemustbemanuallyclearedviaaccessofthephyregisters.
R/W16PAUSE_ADVPauseAdvertiseThisbitisloadedfromEEPROMatpower-upandisusedtoconfiguretheinternalphytoadvertisethecapabilityof802.
3xpauseduringauto-negotiation.
Settingthisbitto1willcausethepausefunctiontobeadvertisedifthephyhasalsobeenconfiguredtoadvertisefullduplexcapability(SeeANEG_SEL).
15-13ANEG_SELAuto-negotiationSelectThesebitsareloadedfromEEPROMatpower-upandareusedtodefinethedefaultstateoftheinternalphyauto-negotiationlogic.
R/WThesebitsareencodedasfollows:000Auto-negotiationdisabled,force10Mb/shalfduplex010Auto-negotiationdisabled,force100Mb/shalfduplex100Auto-negotiationdisabled,force10Mb/sfullduplex110Auto-negotiationdisabled,force100Mb/sfullduplex001Auto-negotiationenabled,advertise10Mb/shalf&fullduplex011Auto-negotiationenabled,advertise10/100Mb/shalfduplex101Auto-negotiationenabled,advertise100Mb/shalf&fullduplex111Auto-negotiationenabled,advertise10/100Mb/shalf&fullduplex12EXT_PHYExternalPhySupportActasastand-aloneMAC.
Whenset,thisbitenablestheMIIanddisablestheinternalPhy(setsbit9).
R/W11Reserved43www.
national.
com4.
0RegisterSet(Continued)DP83815BitBitNameDescription10PHY_RSTResetinternalPhyAssertsresettointernalphy.
CanbeusedtocausephytoreloadoptionsfromtheCFGregister.
Thisbitdoesnotselfclearwhenset.
R/W9PHY_DISDisableinternalPhyWhensettoa1,thisbitforcestheinternalphytoitslow-powerstate.
R/W8EUPHCOMPDP83810DescriptorCompatibilityWhenset,DP83815willuseDP83810compatible(butsinglefragment)descriptorformat.
Descriptorsarefour32-bitwordsinlength,butthefragmentcountfieldisignored.
Whenclear,DP83815willonlyfetch332-bitwordsindescriptorfetcheswiththethirdwordbeingthefragmentpointer.
R/W7REQALGPCIBusRequestAlgorithmSelectsmodeformakingrequestsforthePCIbus.
Whensetto0(default),DP83815willuseanaggressiveRequestscheme.
Whensettoa1,DP83815willuseamoreconservativescheme.
R/W6SBSingleBack-offSettingthisbitto1forcesthetransmitterback-offstatemachinetoalwaysback-offforasingle802.
3slottimeinsteadoffollowingthe802.
3randomback-offalgorithm.
A0(default)allowsnormaltransmitterback-offoperation.
R/W5POWProgramOutofWindowTimerThisbitcontrolswhentheOutofWindowcollisiontimerbeginscountingits512bitslottime.
A0causesthetimertostartaftertheSFDisreceived.
A1causesthetimertostartafterthefirstbitofthepreambleisreceived.
R/W4EXDExcessiveDeferralTimerdisableSettingthisbitto1willinhibittransmiterrorsduetoexcessivedeferral.
ThiswillinhibitthesettingoftheEDstatus,andtheloggingoftheTxExcessiveDeferralMIBcounter.
R/W3PESELParityErrorDetectionActionThisbitcontrolstheassertionofSERRwhenadataparityerrorisdetectedwhiletheDP83815isactingasthebusmaster.
Whenset,parityerrorswillnotresultintheassertionofSERR.
Whenreset,parityerrorswillresultintheassertionofSERR,indicatingasystemerror.
Thisbitshouldbesettoaonebysoftwareifthedrivercanhandlerecoveryfromandreportingofdataparityerrors.
R/W2BROM_DISDisableBootROMinterfaceWhensetto1,thisbitinhibitstheoperationoftheBootROMinterfacelogic.
R/W1Reserved(readsreturn0)0BEMBigEndianModeWhenset,DP83815willperformbus-mastereddatatransfersin"bigendian"mode.
Notethataccesstoregisterspaceisunaffectedbythesettingofthisbit.
R/W44www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
3EEPROMAccessRegisterTheEEPROMAccessRegisterprovidesaninterfaceforsoftwareaccesstotheNMC9306styleEEPROMThedefaultvaluesgivenassumethattheEEDOlinehasapullupresistortoVDD.
4.
2.
4EEPROMMapIntheabovetable:NdenotesthevalueisdependentontheethernetMACIDNumber.
Xdenotesthevalueisdependentonthechecksumvalue.
Tag:MEARSize:32bitsHardReset:00000002hOffset:0008hAccess:ReadWriteSoftReset:00000002hBitBitNameDescription31-7unused6MDCMIIManagementClockControlsthevalueoftheMDCpin.
Whenset,theMDCpinis1;whencleartheMDCpinis0.
R/W5MDDIRMIIManagementDirectionControlsthedirectionoftheMDIOpin.
Whenset,DP83815drivestheMDIOpin.
WhenclearMDIObitreflectsthecurrentstateoftheMDIOpin.
R/W4MDIOMIIManagementDataSoftwareaccesstotheMDIOpin(seeMDDIRabove).
R/W3EESELEEPROMChipSelectControlsthevalueoftheEESELpin.
Whenset,theEESELpinis1;whencleartheEESELpinis0.
R/W2EECLKEEPROMSerialClockControlsthevalueoftheEECLKpin.
Whenset,theEECLKpinis1;whencleartheEECLKpinis0.
R/W1EEDOEEPROMDataOutReturnsthecurrentstateoftheEEDOpin.
Whenset,theEEDOpinis1;whencleartheEEDOpinis0.
RO0EEDIEEPROMDataInControlsthevalueoftheEEDIpin.
R/WEEPROMAddressConfiguration/OperationRegisterBitsDefaultValue(16bits)0000hCFGSID[0:15]D008h0001hCFGSID[16:31]0400h0002hCFGINT[24:31],CFGINT[16:23]2CD0h0003hCFGCS[20],PMCAP[31],PMCAP[21],PMCSR[8],CFG[13:16],CFG[18:23],CR[2],SOPAS[0]CF82h0004hSOPAS[1:16]0000h0005hSOPAS[17:32]0000h0006hSOPAS[33:47],PMATCH[0]000Nh0007hPMATCH[1:16]NNNNh0008hPMATCH[17:32]NNNNh0009hPMATCH[33:47],WCSR[0]NNNNh000AhWCSR[1:4],WCSR[9:10],RFCR[20],RFCR[22],RFCR[27:31],000b(3bits)A098h000BhchecksumvalueXX5545www.
national.
com4.
0RegisterSet(Continued)DP83815PMATCH[47:0]canbeaccessedviathecombinationoftheRFCR(offset0048h)andRFDR(offset004Ch)registers.
PMATCHholdstheEthernetaddressinfo.
SeeSection3.
3.
3.
Thelower8bitsofthechecksumvalueshouldbe55h.
Fortheupper8bits,addthetop8databitstothelower8databitsforeachaddress.
Sumtheresultant8bitvaluesforalladdressesandthenadd55h.
Takethe2'scomplementofthefinalsum.
This2'scomplementnumbershouldbetheupper8bitsofthechecksumvalueinthelastaddress.
Asanexample,consideranEEPROMwithtwoaddresses.
EEPROMaddress0000hcontainsthedata1234h.
EEPROMaddress0001hcontainsthedata5678h.
12h+34h=46h56h+78h=CEh46h+CEh+55h=69hThe2'scomplementof69his97hsothechecksumvalueenteredintoEEPROMaddress0002hwouldbe9755h.
4.
2.
5PCITestControlRegisterTag:PTSCRSize:32bitsHardReset:00000000hOffset:000ChAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31-13unused12ReservedMustbewrittenasa0.
11Reserved10RBIST_RSTSRAMBISTResetSettingthisbitto1allowstheSRAMBISTenginetobereset.
R/W9-8ReservedMustbewrittenas0.
7RBIST_ENSRAMBISTEnableSettingthisbitto1startstheSRAMBISTengine.
R/W6RBIST_DONESRAMBISTDoneThisbitissettoonewhentheBISThascompleteditscurrenttest.
ItisclearedwheneithertheBISTisactiveordisabled.
RO5RBIST_RXFAILRXFIFOBISTFailThisbitissetto1iftheSRAMBISTdetectsafailureintheRXFIFOSRAM.
RO4RBIST_TXFAILTXFIFOFailThisbitissetto1iftheSRAMBISTdetectsafailureintheTXFIFOSRAM.
RO3RBIST_RXFFAILRXFilterRAMBISTFailThisbitissetto1iftheSRAMBISTdetectsafailureintheRXFilterSRAM.
RO2EELOAD_ENEnableEEPROMLoadThisbitissettoa1tomanuallyinitiatealoadofconfigurationinformationfromEEPROM.
A1isreturnedwhiletheconfigurationloadfromEEPROMisactive(approx.
1500us).
R/W1EEBIST_ENEnableEEPROMBISTThisbitissettoa1toinitiateEEPROMBIST,whichverifiestheEEPROMdataandchecksumwithoutreloadingconfigurationvaluestothedevice.
A1isreturnedwhiletheEEPROMBISTisactive.
R/W0EEBIST_FAILEEBISTFailindicationThisbitissettoa1uponcompletionoftheEEPROMBIST(EEBIST_ENreturns0)iftheBISTlogicencounteredaninvalidchecksum.
RO46www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
6InterruptStatusRegisterThisregisterindicatesthesourceofaninterruptwhentheINTApingoesactive.
EnablingthecorrespondingbitsintheInterruptMaskRegister(IMR)allowsbitsinthisregistertoproduceaninterrupt.
Whenaninterruptisactive,oneormorebitsinthisregisteraresettoa"1".
TheInterruptStatusRegisterreflectsallcurrentpendinginterrupts,regardlessofthestateofthecorrespondingmaskbitintheIMR.
ReadingtheISRclearsallinterrupts.
WritingtotheISRhasnoeffect.
Tag:ISRSize:32bitsHardReset:03008000hOffset:0010hAccess:ReadOnlySoftReset:03008000hBitBitNameDescription31-26Reserved25TXRCMPTransmitResetCompleteIndicatesthatarequestedtransmitresetoperationiscomplete.
24RXRCMPReceiveResetCompleteIndicatesthatarequestedreceiveresetoperationiscomplete.
23DPERRDetectedParityErrorThisbitissetwheneverCFGCS:DPERRisset,butcleared(likeallotherISRbits)whentheISRregisterisread.
22SSERRSignaledSystemErrorTheDP83815signaledasystemerroronthePCIbus.
21RMABTReceivedMasterAbortTheDP83815receivedamasterabortgeneratedasaresultoftargetnotresponding.
20RTABTReceivedTargetAbortTheDP83815receivedatargetabortonthePCIbus.
19-17unused16RXSOVRRxStatusFIFOOverrunSetwhenanoverrunconditionoccursontheRxStatusFIFO.
15HIBERRHighBitsErrorSetAlogicalORofbits25-16.
14PHYPhyinterruptSetto1wheninternalphygeneratesaninterrupt.
13PMEPowerManagementEventSetwhenWOLconditioneddetected.
12SWISoftwareInterruptSetwhenevertheSWIbitintheCRregisterisset.
11MIBMIBServiceSetwhenoneoftheenabledmanagementstatisticshasreacheditsinterruptthreshold.
(SeeSection4.
2.
23)10TXURNTxUnderrunSetwhenatransmitdataFIFOunderrunconditionoccurs.
9TXIDLETxIdleThiseventissignaledwhenthetransmitstatemachineenterstheidlestatefromanon-idlestate.
Thiswillhappenwheneverthestatemachineencountersan"end-of-list"condition(NULLlinkfieldoradescriptorwithOWNclear).
8TXERRTxPacketErrorThiseventissignaledafterthelasttransmitdescriptorinafailedtransmissionattempthasbeenupdatedwithvalidstatus.
47www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
7InterruptMaskRegisterThisregistermaskstheinterruptsthatcanbegeneratedfromtheISR.
Writinga"1"tothebitenablesthecorrespondinginterrupt.
Duringahardwarereset,allmaskbitsarecleared.
SettingamaskbitallowsthecorrespondingbitintheISRtocauseaninterrupt.
ISRbitsarealwayssetto1,however,iftheconditionispresent,regardlessofthestateofthecorrespondingmaskbit.
BitBitNameDescription7TXDESCTxDescriptorThiseventissignaledafteratransmitdescriptorwhentheINTRbitintheCMDSTSfieldhasbeenupdated.
6TXOKTxPacketOKThiseventissignaledafterthelasttransmitdescriptorinasuccessfultransmissionattempthasbeenupdatedwithvalidstatus.
5RXORNRxOverrunSetwhenareceivedataFIFOoverrunconditionoccurs.
4RXIDLERxIdleThiseventissignaledwhenthereceivestatemachineenterstheidlestatefromarunningstate.
Thiswillhappenwheneverthestatemachineencountersan"end-of-list"condition(NULLlinkfieldoradescriptorwithOWNset).
3RXEARLYRxEarlyThresholdIndicatesthattheinitialRxDrainThresholdhasbeenmetbytheincomingpacket,andthetransferofthenumberofbytesspecifiedbytheDRTHfieldintheRXCFGregisterhasbeencompletedbythereceiveDMAengine.
Thisinterruptconditionwilloccuronlyonceperpacket.
2RXERRRxPacketErrorThiseventissignaledafterthelastreceivedescriptorinafailedpacketreceptionhasbeenupdatedwithvalidstatus.
1RXDESCRxDescriptorThiseventissignaledafterareceivedescriptorwiththeINTRbitsetintheCMDSTSfieldhasbeenupdated.
0RXOKRxOKSetbythereceivestatemachinefollowingtheupdateofthelastreceivedescriptorinagoodpacket.
Tag:IMRSize:32bitsHardReset:00000000hOffset:0014hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31-26unused25TXRCMPTransmitResetCompleteWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
24RXRCMPReceiveResetCompleteWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
23DPERRDetectedParityErrorWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
22SSERRSignaledSystemErrorWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
21RMABTReceivedMasterAbortWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
48www.
national.
com4.
0RegisterSet(Continued)DP83815BitBitNameDescription20RTABTReceivedTargetAbortWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
19-17unused16RXSOVRRxStatusFIFOOverrunWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
15HIERRHighBitsErrorWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
14PHYPhyinterruptWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
13PMEPowerManagementEventWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
12SWISoftwareInterruptWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
11MIBMIBServiceWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
10TXURNTxUnderrunWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
9TXIDLETxIdleWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
8TXERRTxPacketErrorWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
7TXDESCTxDescriptorWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
6TXOKTxPacketOKWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
5RXORNRxOverrunWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
4RXIDLERxIdleWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
3RXEARLYRxEarlyThresholdWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
2RXERRRxPacketErrorWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
1RXDESCRxDescriptorWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
0RXOKRxOKWhenthisbitis0,thecorrespondingbitintheISRwillnotcauseaninterrupt.
49www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
8InterruptEnableRegisterTheInterruptEnableRegistercontrolsthehardwareINTRsignal.
4.
2.
9TransmitDescriptorPointerRegisterThisregisterpointstothecurrentTransmitDescriptor.
Tag:IERSize:32bitsHardReset:00000000hOffset:0018hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31-1unused0IEInterruptEnableWhensetto1,thehardwareINTRsignalisenabled.
Whensetto0,thehardwareINTRsignalwillbemasked,andnointerruptswillbegenerated.
ThesettingofthisbithasnoeffectontheISRorIMR.
Thisprovidestheabilitytodisablethehardwareinterrupttothehostwithasingleaccess(eliminatingtheneedforaread-modify-writecycle).
Tag:TXDPSize:32bitsHardReset:00000000hOffset:0020hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31-2TXDPTransmitDescriptorPointerThecurrentvalueofthetransmitdescriptorpointer.
Whenthetransmitstatemachineisidle,softwaremustsetTXDPtotheaddressofacompletedtransmitdescriptor.
Whilethetransmitstatemachineisactive,TXDPwillfollowthestatemachineasitadvancesthroughalinkedlistofactivedescriptors.
IfthelinkfieldofthecurrenttransmitdescriptorisNULL(signifyingtheendofthelist),TXDPwillnotadvance,butwillremainonthecurrentdescriptor.
AnysubsequentwritestotheTXEbitoftheCRregisterwillcausethetransmitstatemachinetorereadthelinkfieldofthecurrentdescriptortocheckfornewdescriptorsthatmayhavebeenappendedtotheendofthelist.
Transmitdescriptorsmustbealignedonaneven32-bitboundaryinhostmemory(A1-A0mustbe0).
1-0unused50www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
10TransmitConfigurationRegisterThisregisterdefinestheTransmitConfigurationforDP83815.
ItcontrolssuchfunctionsasLoopback,Heartbeat,AutoTransmitPadding,programmableInterframeGap,Fill&DrainThresholds,andmaximumDMAburstsize.
Tag:TXCFGSize:32bitsHardReset:00000102hOffset:0024hAccess:ReadWriteSoftReset:00000102hBitBitNameDescription31CSICarrierSenseIgnoreSettingthisbitto1causesthetransmittertoignorecarriersenseactivity,whichinhibitsreportingofCRSstatustothetransmitstatusregister.
Whenthisbitis0(default),thetransmitterwillmonitortheCRSsignalduringtransmissionandreflectvalidstatusinthetransmitstatusregisterandMIBcounterblock.
Thisbitmustbesettoenablefull-duplexoperation.
30HBIHeartBeatIgnoreSettingthisbitto1causesthetransmittertoignoretheheartbeat(CD)pulsewhichfollowsthepackettransmissionandinhibitsloggingofTXSQEErrorsintheMIBcounterblock.
Whenthisbitissetto0(default),thetransmitterwillmonitortheheartbeatpulseandlogTXSQEErrorstotheMIBcounterblock.
Thisbitmustbesettoenablefull-duplexoperation29MLBMACLoopbackSettingthisbittoa1placestheDP83815MACintoaloopbackstatewhichroutesalltransmittraffictothereceiver,anddisablesthetransmitandreceiveinterfacesoftheMII.
A0inthisbitallowsnormalMACoperation.
Thetransmitterandreceivermustbedisabledbeforeenablingtheloopbackmode.
(PacketsreceivedduringMLBmodewillreflectloopbackstatusinthereceivedescriptor'scmdsts.
LBPfield.
)28ATPAutomaticTransmitPaddingSettingthisbitto1causestheMACtoautomaticallypadsmall(runt)transmitpacketstotheEthernetminimumsizeof64bytes.
Thisallowsdriversoftwaretotransferonlyactualpacketdata.
Settingthisbitto0disablestheautomaticpaddingfunction,forcingsoftwaretocontrolruntpadding.
27-26IFGInterframeGapTimeThisfieldallowstheusertoadjusttheinterframegaptimebelowthestandard9.
6s@10Mb/sand960ns@100Mb/s.
Thetimecanbeprogrammedfrom9.
6sto8.
4s@10Mb/sand960nsto840ns@100Mb/s.
NotethatanyvalueotherthanzeromayviolatetheIEEE802.
3standard.
Theformulafortheinterframegapis:9.
6s-0.
4(IFG[1:0])s@10Mb/sand960ns-40(IFG[1:0])ns@100Mb/s25-24Reservedwritesareignored,readsreturn00.
23ECRETRYExcessiveCollisionRetryEnableThisbitenablesautomaticretriesofexcessivecollisions.
Ifset,thetransmitterwillretrythepacketupto4excessivecollisioncounts,foratotalof64attempts.
Ifthepacketstilldoesnotcompletesuccessfully,thenthetransmissionwillbeabortedafterthe64thattempt.
Ifthisbitisnotset,thenthetransmitwillbeabortedafterthe16thattempt.
Notethatsettingthisbitwillchangehowcollisionsarereportedinthestatusfieldofthetransmitdescriptor.
51www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
11ReceiveDescriptorPointerRegisterThisregisterpointstothecurrentReceiveDescriptor.
BitBitNameDescription22-20MXDMAMaxDMABurstSizeperTxDMABurstThisfieldsetsthemaximumsizeoftransmitDMAdataburstsaccordingtothefollowingtable:000=12832-bitwords(512bytes)001=132-bitword(4bytes)010=232-bitwords(8bytes)011=432-bitwords(16bytes)100=832-bitwords(32bytes)101=1632-bitwords(64bytes)110=3232-bitwords(128bytes)111=6432-bitwords(256bytes)NOTE:TheMXDMAsettingvalueMUSTnotbegreaterthantheTXCFG:FLTH(TxFillThreshold)value.
19-14unused13-8FLTHTxFillThresholdSpecifiesthefillthresholdinunitsof32bytes.
WhenthenumberofavailablebytesinthetransmitFIFOreachesthislevel,thetransmitbusmasterstatemachinewillbeallowedtorequestthePCIbusfortransmitpacketfragmentreads.
Avalueof0inthisfieldwillproduceunexpectedresultsandmustnotbeused.
Note:TheFLTHvalueshouldbegreaterthantheTXCFG:MXDMAvalue,butlessthan(txFIFOsize-TXCFG:DRTH).
InordertopreventFIFOpointeroverlapinternaltothedevice,thesumoftheFLTHandTXCFG:DRTHvaluesshouldnotexceed2016Bytes.
7-6unused5-0DRTHTxDrainThresholdSpecifiesthedrainthresholdinunitsof32bytes.
WhenthenumberofbytesintheFIFOreachesthislevel(ortheFIFOcontainsatleastonecompletepacket)theMACtransmitstatemachinewillbeginthetransmissionofapacket.
NOTE:Inordertopreventadeadlockconditionfromoccurring,theDRTHvalueshouldalwaysbelessthan(txFIFOsize-TXCFG:FLTH).
Avalueof0inthisfieldwillproduceunexpectedresultsandmustnotbeused.
Also,inordertopreventFIFOpointeroverlapinternaltothedevice,thesumoftheDRTHandTXCFG:FLTHvaluesshouldnotexceed2016Bytes.
Tag:RXDPSize:32bitsHardReset:00000000hOffset:0030hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31-2RXDPReceiveDescriptorPointerThecurrentvalueofthereceivedescriptorpointer.
Whenthereceivestatemachineisidle,softwaremustsetRXDPtotheaddressofanavailablereceivedescriptor.
Whilethereceivestatemachineisactive,RXDPwillfollowthestatemachineasitadvancesthroughalinkedlistofavailabledescriptors.
IfthelinkfieldofthecurrentreceivedescriptorisNULL(signifyingtheendofthelist),RXDPwillnotadvance,butwillremainonthecurrentdescriptor.
AnysubsequentwritestotheRXEbitoftheCRregisterwillcausethereceivestatemachinetorereadthelinkfieldofthecurrentdescriptortocheckfornewdescriptorsthatmayhavebeenappendedtotheendofthelist.
Softwareshouldnotwritetothisregisterunlessthereceivestatemachineisidle.
Receivedescriptorsmustbealignedon32-bitboundaries(A1-A0mustbezero).
A0writtentoRXDPfollowedbyasubsequentwritetoRXEwillcausethereceivertoentersilentRXmode,foruseduringWOL.
InthismodepacketswillbereceivedandbufferedinFIFO,butnoDMAtosystemmemorywilloccur.
ThepacketdatamayberecoveredfromtheFIFObywritingavaliddescriptoraddresstoRXDPandthenstrobingRXE.
1-0unused52www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
12ReceiveConfigurationRegisterThisregisterisusedtosetthereceiveconfigurationforDP83815.
Receivepropertiessuchasacceptingerrorpackets,runtpackets,settingthereceivedrainthresholdetc.
arecontrolledhere.
Tag:RXCFGSize:32bitsHardReset:00000002hOffset:0034hAccess:ReadWriteSoftReset:00000002hBitBitNameDescription31AEPAcceptErroredPacketsWhensetto1,allpacketswithCRC,alignment,and/orcollisionerrorswillbeaccepted.
Whensetto0,allpacketswithCRC,alignment,and/orcollisionerrorswillberejectedifpossible.
Notethatdependingonthetypeoferror,somepacketsmaybereceivedwitherrors,regardlessofthesettingofAEP.
TheseerrorswillbeindicatedintheCMDSTSfieldofthelastdescriptorinthepacket.
30ARPAcceptRuntPacketsWhensetto1,allpacketsunder64bytesinlengthwithouterrorsareaccepted.
Whenthisbitis0,allpacketslessthan64bytesinlengthwillberejectedifpossible.
29unused28ATXAcceptTransmitPacketsWhensetto1,datareceivedsimultaneouslytoalocaltransmission(suchasduringaPMDloopbackorfullduplexoperation)willbeacceptedasvalidreceiveddata.
Additionally,whensetto1,thereceiverwillignorecollisionactivity.
Whensetto0(default),alldatareceivesimultaneoustoalocaltransmitwillberejected.
Thisbitmustbesetto1forPMDloopbackandfullduplexoperation.
27ALPAcceptLongPacketsWhensetto1,allpackets>1518bytesinlengthand2046byteswillbetreatedasnormalreceivepackets,andwillnotbetaggedaslongorerrorpackets.
Allpackets>2046bytesinlengthwillbetruncatedat2046bytesandeitherrejectedfromtheFIFO,ortaggedaslongpackets.
Caremustbetakenwhenacceptinglongpacketstoensurethatbuffersprovidedareofadequatelength.
WhenALPissetto0,packetslargerthan1518bytes(CRCinclusive)willbetruncatedat1514bytes,andrejectedifpossible.
26unused25-23unusedWritesareignored,readsreturn000b.
22-20MXDMAMaxDMABurstSizeperRxDMABurstThisfieldsetsthemaximumsizeofreceiveDMAdataburstsaccordingtothefollowingtable:000=12832-bitwords(512bytes)001=132-bitword(4bytes)010=232-bitwords(8bytes)011=432-bitwords(16bytes)100=832-bitwords(32bytes)101=1632-bitwords(64bytes)110=3232-bitwords(128bytes)111=6432-bitwords(256bytes)19-6unused53www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
13CLKRUNControl/StatusRegisterThisregistermirrorstheread/writecontrolofthePMESTSandPMEENfromthePCIConfigurationregisterPMCSRandcontrolswhetherthechipisintheCLKRUNNorPMENmode.
BitBitNameDescription5-1DRTHRxDrainThresholdSpecifiesthedrainthresholdinunitsof8bytes.
WhenthenumberofbytesinthereceiveFIFOreachesthisvalue(times8),ortheFIFOcontainsacompletepacket,thereceivebusmasterstatemachinewillbeginthetransferofdatafromtheFIFOtohostmemory.
CaremustbetakenwhensettingDRTHtoavaluelowerthanthenumberofbytesneededtodetermineifpacketshouldbeacceptedorrejected.
Inthiscase,thepacketmightberejectedafterthebusmasteroperationtobegintransferringthepacketintomemoryhasbegun.
Whenthisoccurs,neithertheOKbitoranyerrorstatusbitinthedescriptor'scmdstswillbeset.
Avalueof0isillegal,andtheresultsareundefined.
Thisvalueisalsousedtocomparewiththeaccumulatedpacketlengthforearlyreceiveindication.
WhentheaccumulatedpacketlengthmeetsorexceedstheDRTHvalue,theRXEARLYinterruptconditionisgenerated.
0ReservedTag:CCSRSize:32bitsHardReset:00000000hOffset:003ChAccess:ReadWriteSoftReset:unchangedBitBitNameDescription31-16reserved(readsreturn0)15PMESTSPMEStatusStickybitwhichrepresentsthestateofthePME/CLKRUNlogic,regardlessofthestateofthePMEENbit.
MirroredfromPCIconfigurationregisterPMCSR.
Writinga1tothisbitclearsit.
14-9reserved(readsreturn0)8PMEENPMEEnableWhensetto1,thisbitenablestheassertionofthePMEN/CLKRUNNpin.
When0,thePMEN/CLKRUNNpinisforcedtobeinactive.
ThisvaluecanbeloadedfromtheEEPROM.
MirroredfromPCIconfigurationregisterPMCSR.
7-1unused(readsreturn0)0CLKRUN_ENClkrunEnableWhensetto1,thisbitenablestheCLKRUNNfunctionalityofthePMEN/CLKRUNNpin.
When0,normalPMENfunctionalityisactive.
4.
0RegisterSet(Continued)Subjecttochangewithoutnotice.
54RevOwww.
national.
comDP838154.
2.
13.
1CLKRUNNFunctionCLKRUNNisadual-functionoptionalsignal.
ItisusedbythecentralPCIclockresourcetoindicateclockstatus(i.
e.
PCIclockrunningnormallyorslowed/stopped),anditisusedbyPCIdevicestorequestthatthecentralresourcerestartthePCIclockorkeepitrunningnormally.
IntheDP83815,CLKRUNNsharesapinwithPMEN(pin59).
ThismeansthechipcannotbesimultaneouslyPCIPowerManagementandPCIMobileDesignGuide-compliant;however,itisunlikelythatasystemwouldusebothofthesefunctionssimultaneously.
ThefunctionofthePMEN/CLKRUNNpinisselectedwiththeCLKRUN_ENbitofCCSR.
CCSRbits15and8(PMESTSandPMEEN)aremirroredfromPCIconfigurationspacetoallowthemtobeaccessedbysoftware.
ThefunctionalityofthesebitsisthesameasinthePCIconfigurationregisterPMCSR.
Asanoutput,CLKRUNNisopen-drainlikePMEN,i.
e.
itcanonlydrivelow.
CLKRUNNisaninputunlessoneofthefollowingtwoconditionsoccurs:1.
thesystemdrivesCLKRUNNhighbuttheDP83815isnotreadyforthePCIclocktobestoppedor2.
thePCIclockisstoppedorslowed(CLKRUNNispulledhighbythesystem)andtheDP83815requirestheuseofthePCIbus.
Situation1isa"clockcontinue"eventandcanoccuriftheDP83815hasnotcompletedapendingpackettransmitorreceive.
Situation2isa"clockstart"eventandcanoccuriftheDP83815hasbeenprogrammedtoaWOLstateanditreceivesawakepacket,orthePCIclockhassimplybeenstoppedandthereceiverhasdatareadytoDMA.
Ineitherofthesesituations,theDP83815assertsCLKRUNNuntilitdetectstworisingedgesofthePCIclock;itthenreleasesassertionofCLKRUNN.
Atthispoint,thecentralresourceisdrivingCLKRUNNlow,andcannotdriveithighagainuntilatleastfourrisingedgesofthePCIclockhaveoccurredsincetheinitialCLKRUNNassertionbytheDP83815.
Alsoineithersituation,theDP83815musthavedetectedCLKRUNNde-assertedfortwoconsecutiverisingedgesofthePCIclockbeforeitisallowedtoassertCLKRUNN.
NOTES:*IfaclockstartorcontinueeventhascompletedbutaPCIinterrupthasnotbeenservicedyet,theCLKRUNlogicwillnotpreventthesystemfromstoppingthePCIclock.
*IfPMEENisnotset,theDP83815cannotassertCLKRUNNtorequestaclockstartorcontinue.
Inthiscase,ifthesystemisgoingtostopthePCIclock,softwaremustshutdowntheinternalPHYtopreventreceiveerrors.
*IfanotherCLKRUN-enableddeviceinthesystemencountersaclockstartorcontinueevent,thecycleofassertionsandde-assertionsofCLKRUNNwillcausetheDP83815clockmuxtoswitchtheclocktotheRXblockbackandforthbetweenthePCIclockandtheX1clockuntiltheeventcompletes.
55www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
14WakeCommand/StatusRegisterTheWCSRregisterisusedtoconfigure/controlandmonitortheDP83815WakeOnLANlogic.
TheWakeOnLANlogicisusedtomonitortheincomingpacketstreamwhileinalow-powerstate,andprovideawakeeventtothesystemifthedesiredpackettype,contents,orLinkchangearedetected.
Tag:WCSRSize:32bitsHardReset:00000000hOffset:0040hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31MPRMagicPacketReceivedSetto1ifaMagicPackethasbeendetectedandtheWKMAGbitisset.
RO,clearedonread.
30PATM3Pattern3matchAssociatedbitsetto1ifapattern3matchisdetectedandtheWKPAT3bitisset.
RO,clearedonread.
29PATM2Pattern2matchAssociatedbitsetto1ifapattern2matchisdetectedandtheWKPAT2bitisset.
RO,clearedonread.
28PATM1Pattern1matchAssociatedbitsetto1ifapattern1matchisdetectedandtheWKPAT1bitisset.
RO,clearedonread.
27PATM0Pattern0matchAssociatedbitsetto1ifapattern0matchisdetectedandtheWKPAT0bitisset.
RO,clearedonread.
26ARPRARPReceivedSetto1ifanARPpackethasbeendetectedandtheWKARPbitisset.
RO,clearedonread.
25BCASTRBroadcastReceivedSetto1ifabroadcastpackethasbeendetectedandtheWKBCPbitisset.
RO,clearedonread.
24MCASTRMulticastReceivedSetto1ifamulticastpackethasbeendetectedandtheWKMCPbitisset.
RO,clearedonread.
23UCASTRUnicastReceivedSetto1ifaunicastpackethasbeendetectedtheWKUCPbitisset.
RO,clearedonread.
22PHYINTPhyInterruptSetto1ifaPhyinterruptwasdetectedandtheWKPHYbitisset.
RO,clearedonread.
21ReservedReservedRO,clearedonread.
20SOHACKSecureOnHackAttemptSetto1iftheMPSOEandWKMAGbitsareset,andaMagicPacketisreceivewithaninvalidSecureOnpasswordvalue.
RO,Clearedonread.
19-11unusedreturns010MPSOEMagicPacketSecureOnEnableEnableMagicPacketSecureOnfeature.
Onlyapplicablewhenbit9isset.
R/W9WKMAGWakeonMagicPacketEnablewakeonMagicPacketdetection.
R/W8WKPAT3WakeonPattern3matchEnablewakeonmatchofpattern3.
R/W7WKPAT2WakeonPattern2matchEnablewakeonmatchofpattern2.
R/W6WKPAT1WakeonPattern1matchEnablewakeonmatchofpattern1.
R/W4.
0RegisterSet(Continued)Subjecttochangewithoutnotice.
56RevOwww.
national.
comDP838154.
2.
14.
1WakeonLANTheWakeonLANlogicprovidesseveralmechanismsforbringingtheDP83815outofalow-powerstate.
WakeonARP,WakeonBroadcast,WakeonMulticastHashandWakeonPhyInterruptareenabledbysettingthecorrespondingbitintheWakeCommand/StatusRegister,WCSR.
Beforethehardwareisprogrammedtoalowpowerstate,thesoftwaremustwriteanullreceivedescriptorpointertotheReceiveDescriptorPointerRegister(RXDP)toensurewakepacketswillbebufferedintheRXfifo.
PleaserefertothedescriptionoftheRXDPregisterforthisprocedure.
Whenaqualifyingpacketisreceived,theWakeonLANlogicgeneratesaWakeeventandpulsesthePMENPCIsignaltorequestaPowerManagementstatechange.
Thesoftwaremustthenbringthehardwareoutoflowpowermodeand,ifthePowerManagementstatewasD3hot,reinitializeConfigurationRegisterspace.
AWakeinterruptcanalsobegeneratedwhichalertsthesoftwarethataWakeeventhasoccurredandapacketwasreceived.
ThesoftwaremustthenwriteavalidreceivedescriptorpointertoRXDP.
Theincomingpacketcanthenbetransferredintohostmemoryforprocessing.
Notethatthewakepacketisretainedforprocessing-thisisafeatureoftheDP83815.
InadditiontotheaboveWakeonLANfeatures,DP83815alsoprovidesWakeonPatternMatching,WakeonDAmatchandWakeonMagicPacket.
WakeonPatternMatchingWakeonPatternMatchingisanextensionofthePatternMatchingfeatureprovidedbytheReceiveFilterLogic.
WhenoneormoreoftheWakeonPatternMatchbitsaresetintheWCSR,apacketwillgenerateawakeeventifitmatchestheassociatedpatternbuffer.
ThepatterncountandthepatternbuffermemoryareaccessedinthesamewayasinPatternMatchingforpacketacceptance.
Theminimumpatterncountis2bytesandthemaximumpatterncountis64bytesforpatterns0and1,and128bytesforpatterns2and3.
Packetsarecomparedonabytebybytebasisandbytesmaybemaskedinpatternmemory,thusallowingfordon'tcares.
RefertoSection4.
2.
18ReceiveFilterLogicforprogrammingexamples.
BitBitNameDescription5WKPAT0WakeonPattern0matchEnablewakeonmatchofpattern0.
R/W4WKARPWakeonARPEnablewakeonARPpacketdetection.
R/W3WKBCPWakeonBroadcastEnablewakeonbroadcastpacketdetection.
R/W2WKMCPWakeonMulticastEnablewakeonmulticastpacketdetection.
R/W1WKUCPWakeonUnicastEnablewakeonunicastpacketdetection.
R/W0WKPHYWakeonPhyInterruptEnablewakeonPhyInterrupt.
ThePhyinterruptcanbeprogrammedforLinkChangeandavarietyofotherPhysicalLayerevents.
R/W57www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
15PauseControl/StatusRegisterThePCRregisterisusedtocontrolandmonitortheDP83815PauseFramereceptionlogic.
ThePauseFramereceptionLogicisusedtoaccept802.
3xPauseFrames,extractthepauselengthvalue,andinitiateaTXMACpauseintervalofthespecifiednumberofslottimes.
Tag:PCRSize:32bitsHardReset:00000000hOffset:0044hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31PSENPauseEnableManuallyenablesreceptionof802.
3xpauseframesThisbitisORedwiththePSNEGbittoenablepausereception.
IfpausereceptionhasbeenenabledviaPSENbit(PSEN=1),settingthisbitto0willcauseanyactivepauseintervaltobeterminated.
R/W30PS_MCASTPauseonMulticastWhensetto1,thisbitenablesreceptionof802.
3xpauseframeswhichusethe802.
3xdesignatedmulticastaddressintheDA(01-80-C2-00-00-01).
Whenthismodeisenabled,theRXfilterlogicperformsaperfectmatchontheabovemulticastaddress.
Nootheraddressfiltrationmodes(includingmulticasthash)arerequiredforpauseframereception.
R/W29PS_DAPauseonDAWhensetto1,thisbitenablesreceptionofapauseframebasedonaDAmatchwitheithertheperfectmatchregister,oroneofthepatternmatchbuffers.
R/W28-24unusedreturns023PS_ACTPauseActiveThisbitissettoa1whentheTXMAClogicisactivelytimingapauseinterval.
RO22PS_RCVDPauseFrameReceivedThisbitissettoa1whenapauseframehasbeenreceived.
ThisbitwillremainsetuntiltheTXMAChascompletedthepauseinterval.
RO21PSNEGPauseNegotiatedStatusbitindicatingthatthe802.
3xpausefunctionhasbeenenabledviaauto-negotiation.
ThisbitwillonlybesetifDP83815advertisespausecapablebysettingbit16intheCFGregister.
RO20-17unusedreturns016MLD_ENManualLoadEnableSettingthisbittoa1willcausethevalueofbits15-0tobewrittentothepausecountregister.
Thiswriteoperationcausespausecountintervalwillbemanuallyinitiated.
Thisbitisnotsticky,andreadswillalwaysreturn0.
WO15-0PAUSE_CNTPauseCounterValueREAD:Thesebitsrepresentthecurrentreal-timevalueoftheTXMACpausecounterregister.
WRITE:Ifnopausecountintervalisinprogress(PS_RCVD=0,PS_ACT=0),andMLD_EN=1thisvalueiswrittentothepausecountregister,andcausespausecountintervalwillbemanuallyinitiated.
58www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
16ReceiveFilter/MatchControlRegisterTheRFCRregisterisusedtocontrolandconfiguretheDP83815ReceiveFilterControllogic.
TheReceiveFilterControlLogicisusedtoconfiguredestinationaddressfilteringofincomingpackets.
Tag:RFCRSize:32bitsHardReset:00000000hOffset:0048hAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31RFENRxFilterEnableWhenthisbitissetto1,theRxFilterisenabledtoqualifyincomingpackets.
Whensettoa0,receivepacketfilteringisdisabled(i.
e.
allreceivepacketsarerejected).
Thisbitmustbe0fortheotherbitsinthisregistertobeconfigured.
30AABAcceptAllBroadcastWhensettoa1,thisbitcausesallbroadcastaddresspacketstobeaccepted.
Whensetto0,nobroadcastaddresspacketswillbeaccepted.
29AAMAcceptAllMulticastWhensettoa1,thisbitcausesallmulticastaddresspacketstobeaccepted.
Whensetto0,multicastdestinationaddressesmusthavetheappropriatebitsetinthemulticasthashtablemaskinorderforthepackettobeaccepted.
28AAUAcceptAllUnicastWhensettoa1,thisbitcausesallunicastaddresspacketstobeaccepted.
Whensetto0,thedestinationaddressmustmatchthenodeaddressvaluespecifiedthroughsomeothermeansinorderforthepackettobeaccepted.
27APMAcceptonPerfectMatchWhensetto1,thisbitallowstheperfectmatchregistertobeusedtocompareagainsttheDAforpacketacceptance.
Whenthisbitis0,theperfectmatchregistercontentswillnotbeusedforDAcomparison.
26-23APATAcceptonPatternMatchWhenoneormoreofthesebitsissetto1,apacketwillbeacceptedifthefirstnbytes(nisthevaluedefinedintheassociatedpatterncountregister)matchtheassociatedpatternbuffermemorycontents.
Whenabitissetto0,theassociatedpatternbufferwillnotbeusedforpacketacceptance.
22AARPAcceptARPPacketsWhensetto1,thisbitallowsallARPpackets(packetswithaTYPE/LENfieldsetto806h)tobeaccepted,regardlessoftheDAvalue.
Whensetto0,ARPpacketsaretreatedasnormalpacketsandmustmeetotherDAmatchcriteriaforacceptance.
21MHENMulticastHashEnableWhensetto1,thisbitallowshashtablecomparisonformulticastaddresses,i.
e.
ahashtablehitforamulticastaddressedpacketwillbeaccepted.
Whensetto0,multicasthashhitswillnotbeusedforpacketacceptance.
20UHENUnicastHashEnableWhensetto1,thisbitallowshashtablecomparisonforunicastaddresses,i.
e.
ahashtablehitforaunicastaddressedpacketwillbeaccepted.
Whensetto0,unicasthashhitswillnotbeusedforpacketacceptance.
19ULMU/LbitMaskWhensetto1,thisbitwillcausetheU/Lbit(2ndMSb)oftheDAtobeignoredduringcomparisonwiththeperfectmatchregister.
18-10Unusedreturns059www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
17ReceiveFilter/MatchDataRegisterTheRFDRregisterisusedforreadingfromandwritingtotheinternalreceivefilterregisters,thepatternbuffermemory,andthehashtablememory.
.
BitBitNameDescription9-0RFADDRReceiveFilterExtendedRegisterAddressSelectswhichinternalreceivefilterregisterisaccessibleviaRFDR:PerfectMatchRegister(PMATCH)000h-PMATCHoctets1-0002h-PMATCHoctets3-2004h-PMATCHoctets5-4PatternCountRegisters(PCOUNT)006h-PCOUNT1,PCOUNT0008h-PCOUNT3,PCOUNT2SecureOnPasswordRegister(SOPAS)00Ah-SOPASoctets1-000Ch-SOPASoctets3-200Eh-SOPASoctets5-4FilterMemory200h-3FE-Rxfiltermemory(Hashtable/patternbuffers)Tag:RFDRSize:32bitsHardReset:00000000hOffset:004ChAccess:ReadWriteSoftReset:00000000hBitBitNameDescription31-18unused17-16BMASKBytemaskUsedasbytemaskvaluesforpatternmatchtemplatedata.
15-0RFDATAReceiveFilterData4.
0RegisterSet(Continued)Subjecttochangewithoutnotice.
60RevOwww.
national.
comDP838154.
2.
18ReceiveFilterLogicTheReceiveFilterLogicsupportsavarietyoftechniquesforqualifyingincomingpackets.
ThemostbasicfilteringoptionsincludeAcceptAllBroadcast,AcceptAllMulticastandAcceptAllUnicastpackets.
TheseoptionsareenabledbysettingthecorrespondingbitintheReceiveFilterControlRegister,RFCR.
AcceptonPerfectMatch,AcceptonPatternMatch,AcceptonMulticastHashandAcceptonUnicastHasharemorerobustintheirfilteringcapabilities,butrequireadditionalprogrammingoftheReceiveFilterregistersandtheinternalfilterRAM.
AcceptonPerfectMatchWhenenabled,thePerfectMatchRegisterisusedtocompareagainsttheDAforpacketacceptance.
ThePerfectMatchRegisterisa6-byteregisteraccessedindirectlythroughtheRFCR.
Theaddressoftheinternalreceivefilterregistertobeaccessedisprogrammedthroughbits8:0oftheRFCR.
TheReceiveFilterDataRegister,RFDR,isusedforreading/writingtheactualdata.
RXFilterAddress:000h-PerfectMatchoctets1-0002h-PerfectMatchoctets3-2004h-PerfectMatchoctets5-4Octet0ofthePerfectMatchRegistercorrespondstothefirstoctetofthepacketasitappearsonthewire.
Octet5correspondstothelastoctetoftheDAasitappearsonthewire.
ThefollowingstepsarerequiredtoprogramtheRFCRtoacceptpacketsonaperfectmatchoftheDA.
Example:DestinationAddressof08-00-17-07-28-55iowl$RFCR(0000)perfectmatchregister,octets1-0iowl$RFDR(0008)writeaddress,octets1-0iowl$RFCR(0002)perfectmatchregister,octets3-2iowl$RFDR(0717)writeaddress,octets3-2iowl$RFCR(0004)perfectmatchregister,octets5-4iowl$RFDR(5528)writeaddress,octets5-4iowl$RFDR($RFEN|$APM)enablefiltering,perfectmatchAcceptonPatternMatchTheReceiveFilterLogicprovidesaccessto4separateinternalRAM-basedpatternbufferstobeusedasadditionalperfectmatchaddressregisters.
Patternbuffers0and1are64bytesdeep,allowingperfectmatchonthefirst64bytesofapacket,andpatternbuffers2and3are128bytesdeep,allowingperfectmatchonthefirst128bytesofapacket.
WhenoneormoreofthePatternMatchenablebitsaresetintheRFCR,apacketwillbeacceptedifitmatchestheassociatedpatternbuffer.
Asindicatedabove,thepatternbuffersare64and128bytesdeeporganizedas32or64words,whereawordis18bits.
Bits17and18ofarespectivewordaremaskbitsforbyte0andbyte1ofthe16-bitdataword(bits15:0).
Anincomingpacketiscomparedtoeachenabledpatternbufferonabytebybytebasisforaspecifiedcount.
Maskingapatternbyteresultsinabytematchregardlessofitsvalue(adon'tcare).
Acountvaluemustbeprogrammedforeachpatternbuffertobeusedforcomparison.
Theminimumvalidcountis2(2bytes)andthemaximumvalidcountis32forpatternbuffers0and1,and64forpatternbuffers2and3.
ThepatterncountregistersareinternalreceivefilterregistersaccessedthroughtheRFCRandtheRFDRTheReceiveFiltermemoryisalsoaccessedthroughtheRFCRandtheRFDR.
AmemorymapoftheinternalpatternRAMisshowninFigure4-1.
61www.
national.
com4.
0RegisterSet(Continued)DP83815Figure4-1PatternBufferMemory-180hwords(word=18bits)Byte1MaskBitByte0MaskBitPattern3Word7Fbyte1byte03FEPattern2Word7Fbyte1byte03FCPattern3Word7Ebyte1byte03FAPattern2Word7Ebyte1byte03F8Pattern3Word1byte1byte0306Pattern2Word1byte1byte0304Pattern3Word0byte1byte0302Pattern2Word0byte1byte0300Pattern1Word3Fbyte1byte02FEPattern0Word3Fbyte1byte02FCPattern1Word3Ebyte1byte02FAPattern0Word3Ebyte1byte02F8Pattern1Word1byte1byte0286Pattern0Word1byte1byte0284Pattern1Word0byte1byte0282Pattern0Word0byte1byte0280Bit#17161587062www.
national.
com4.
0RegisterSet(Continued)DP83815Example:Patternmatchonthefollowingdestinationaddresses:02-00-03-01-04-0212-10-13-11-14-1222-20-23-21-24-2232-30-33-31-34-32set$PATBUF01=280set$PATBUF23=300#writecountsiowl$RFCR(0006)#patterncountregisters1,0iowl$RFDR(0406)#count1=4,count0=6iowl$RFCR(0008)#patterncountregisters3,2iowl$RFDR(0406)#count3=4,count2=6#writedatapatternintobuffer0iowl$RFCR($PATBUF01)iowl$RFDR(0002)iowl$RFCR($PATBUF01+4)iowl$RFDR(0103)iowl$RFCR($PATBUF01+8)iowl$RFDR(0204)#writedatapatternintobuffer1iowl$RFCR($PATBUF01+2)iowl$RFDR(1012)iowl$RFCR($PATBUF01+6)iowl$RFDR(1113)iowl$RFCR($PATBUF01+a)iowl$RFDR(1214)#writedatapatternintobuffer2iowl$RFCR($PATBUF23)iowl$RFDR(2022)iowl$RFCR($PATBUF23+4)iowl$RFDR(2123)iowl$RFCR($PATBUF23+8)iowl$RFDR(2224)#writedatapatternintobuffer3iowl$RFCR($PATBUF23+2)iowl$RFDR(3032)iowl$RFCR($PATBUF23+6)iowl$RFDR(3133)iowl$RFCR($PATBUF23+a)iowl$RFDR(3234)#enablereceivefilteronallpatternsiowl$RFCR($RFEN|$APAT0|$APAT1|$APAT2|$APAT3)Exampleofhowtomaskoutabyteinapattern:#writedatapatternintobuffer0iowl$RFCR($PATBUF01)iowl$RFDR(10002)#maskbyte0(value=02)iowl$RFCR($PATBUF01+4)iowl$RFDR(20103)#maskbyte1(value=01)iowl$RFCR($PATBUF01+8)iowl$RFDR(30204)#maskbyte0and14.
0RegisterSet(Continued)Subjecttochangewithoutnotice.
63RevOwww.
national.
comDP83815AcceptonMulticastorUnicastHashMulticastandUnicastaddressesmaybefurtherqualifiedbyuseofthereceivefilterhashfunctions.
Aninternal512bit(64byte)RAM-basedhashtableisusedtoperformimperfectfilteringofmulticastorunicastpackets.
ByenablingeitherMulticastHashingorUnicastHashingintheRFCR,thereceivefilterlogicwillusethe9leastsignificantbitsofthedestinationaddresses'CRCasanindexintotheHashTablememory.
Theupper4bitsrepresentthewordaddressandthelower5bitsselectthebitwithintheword.
Ifthecorrespondingbitisset,thenthepacketisaccepted,otherwisethepacketisrejected.
ThehashtablememoryisaccessedthroughtheRFCRandtheRFDR.
RefertoFigure4-2foramemorymap.
Belowisexamplecodeforsetting/clearingabitinthehashtable.
Figure4-2HashTableMemory-40hbytesaddressedonwordboundariessetHASH_TABLE=200crc$DA#computetheCRCofthedestinationaddresssetindex=($crc>>3)setbit=($crc&01f)#lower5bitsselectwhichbitin32bitword#writewordaddressintoRFCRiowl$RFCR($HASH_TABLE+$index)#selectbittoset/clearif($bit>f)setbit=($bit-010h)#use16bitregisterinterfaceinto32bitRAMsethash_bit=(0001223EXXbyte61byte6023CXXbyte5byte4204XXbyte3byte2202XXbyte1byte0200Bit#17161587064www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
19BootROMAddressRegisterTheBRARisusedtosetuptheaddressforanaccesstoanexternalROM/FLASHdevice.
4.
2.
20BootROMDataRegisterTheBRDRisusedtoreadandwriteROM/FLASHdatafromthedatafrom/toanexternalROM/FLASHdevice.
4.
2.
21SiliconRevisionRegisterTag:BRARSize:32bitsHardReset:FFFFFFFFhOffset:0050hAccess:ReadWriteSoftReset:unchangedBitBitNameDescription31AUTOINCAuto-IncrementWhenset,thecontentsofADDRwillautoincrementwithevery32-bitaccesstotheBRDRregister.
30-16unused15-0ADDRBootROMAddress16-bitaddressusedtoaccesstheexternalBootROM.
Tag:BRDRSize:32bitsHardReset:undefinedOffset:0054hAccess:ReadWriteSoftReset:undefinedBitBitNameDescription31-0DATABootROMDataAccessporttoexternalBootROM.
SoftwarecanuseBRARandBRDRtoread(andwriteifFLASHmemoryisused)theexternalBootROM.
Allaccessesmustbe32-bitswideandalignedon32-bitboundaries.
Tag:SRRSize:32bitsHardReset:asdefinedOffset:0058hAccess:ReadOnlySoftReset:unchangedBitBitNameDescription31-16unused(readsreturn0)15-0RevRevisionLevelSRRregistervaluefortheDP83815silicon.
DP83815CVNG00000302hDP83815DVNG/UJB00000403h65www.
national.
com4.
0RegisterSet(Continued)DP838154.
2.
22ManagementInformationBaseControlRegisterTheMIBCregisterisusedtocontrolaccesstothestatisticsblockandthewarningbitsandtocontrolthecollectionofmanagementinformationstatistics.
Tag:MIBCSize:32bitsHardReset:00000002hOffset:005chAccess:ReadWriteSoftReset:00000002hBitBitNameDescription31-4unused3MIBSMIBCounterStrobeWritinga1tothisbitlocationcausesthecountersinallenabledblockstoincrementby1,providingasingle-steptestfunction.
TheMIBSbitisalwaysreadbackas0.
Thisbitisusedfortestpurposesonlyandshouldbesetto0fornormalcounteroperation.
2ACLRClearallcountersWhensettoa1,thisbitforcesallcounterstoberesetto0.
Thisbitisalwaysreadbackas0.
1FRZFreezeallcountersWhensettoa1,thisbitforcescountvaluestobefrozensuchthatareadofthestatisticblockwillrepresentmanagementstatisticsatagiveninstantintime.
Whensetto0,thecounterswillincrementnormallyandmaybereadindividuallywhilecounting.
Whilefrozeneventswillnotberecorded.
0WRNWarningTestIndicatorThisfieldisreadonly.
Thisbitissetto1whenstatisticcountershavereachedtheirrespectiveoverflowwarningcondition.
WRNwillbeclearedafteroneormoreofthestatisticcountershavebeencleared.
4.
0RegisterSet(Continued)Subjecttochangewithoutnotice.
66RevOwww.
national.
comDP838154.
2.
23ManagementInformationBaseRegistersThecountersprovideasetofstatisticscompliantwiththefollowingmanagementspecifications:MIBII,Ether-likeMIB,andIEEEMIB.
Thevaluesprovidedareaccessedthroughthevariousregistersasshownbelow.
AllMIBcountersareclearedto0whenread.
Duetocostandspacelimitations,thecounterbitwidthsprovidedintheDP83815MIBarelessthanthebitwidthscalledforintheabovespecifications.
Itisassumedthatmanagementagentsoftwarewillmaintainasetoffullycompliantstatisticvalues("software"counters),utilizingthehardwarecounterstoreducethefrequencyatwhichthese"software"countersmustbeupdated.
Sizesforspecifichardwarestatisticcounterswerechosensuchthatthecountvalueswillnotrolloverinlessthan15msifincrementedatthetheoreticalmaximumratesdescribedintheabovespecifications.
However,giventhatthetheoreticalmaximumcounterratesdonotrepresentrealisticnetworktrafficandevents,theactualrolloverratesforthehardwarecountersaremorelikelytobeontheorderofseveralseconds.
ThehardwarecountersareupdatedautomaticallybytheMAContheoccurrenceofeachevent.
Table4-3MIBRegistersOffsetTagSizewarning(MSbits)Description0060hRXErroredPkts168Packetsreceivedwitherrors.
Thiscounterisincrementedforeachpacketreceivedwitherrors.
ThiscountincludespacketswhichareautomaticallyrejectedfromtheFIFOduetobothwireerrorsandFIFOoverruns.
0064hRXFCSErrors84Packetsreceivedwithframechecksequenceerrors.
ThiscounterisincrementedforeachpacketreceivedwithaFrameCheckSequenceerror(badCRC).
Note:FortheMIIinterface,anFCSerrorisdefinedasaresultinginvalidCRCafterCRSgoesinvalidandanevennumberofbyteshavebeenreceived.
0068hRXMsdPktErrors84PacketsmissedduetoFIFOoverruns.
ThiscounterisincrementedforeachreceiveabortedduetodataorstatusFIFOoverruns(insufficientbufferspace).
006ChRXFAErrors84Packetsreceivedwithframealignmenterrors.
ThiscounterisincrementedforeachpacketreceivedwithaFrameCheckSequenceerror(badCRC).
Note:FortheMIIinterface,anFAEerrorisdefinedasaresultinginvalidCRConthelastfulloctet,andanoddnumberofnibbleshavebeenreceived(DribblenibbleconditionwithabadCRC).
0070hRXSymbolErrors84Packetsreceivedwithoneormoresymbolerrors.
Thiscounterisincrementedforeachpacketreceivedwithoneormoresymbolerrorsdetected.
Note:FortheMIIinterface,asymbolerrorisindicatedbytheRXERsignalbecomingactiveforoneormoreclockswhiletheRXDVsignalisactive(duringvaliddatareception).
0074hRXFrameTooLong42Packetsreceivedwithlengthgreaterthan1518bytes(toolongpackets).
Thiscounterisincrementedforeachpacketreceivedwithgreaterthanthe802.
3standardmaximumlengthof1518bytes.
0078hTXSQEErrors42Lossofcollisionheartbeatduringtransmission.
ThiscounterisincrementedwhenthecollisionheartbeatpulseisnotdetectedbythePMDafteratransmission.
67www.
national.
com4.
0RegisterSet(Continued)DP838154.
3InternalPHYRegistersTheInternalPhyRegistersareonly16bitswide.
Bits[31:16]arenotused.
Inthefollowingregisterdefinitionsunderthe'Default'heading,thefollowingdefinitionsholdtrue:—RW=ReadWriteaccess—RO=ReadOnlyaccess—LL=LatchedLowandhelduntilread,basedupontheoccurrenceofthecorrespondingevent—LH=LatchedHighandhelduntilread,basedupontheoccurrenceofthecorrespondingevent—SC=RegistersetsoneventoccurrenceandSelf-Clearswheneventends—P=RegisterbitisPermanentlysettoadefaultvalue—COR=ClearOnRead4.
3.
1BasicModeControlRegisterTag:BMCRSize:16bitsHardReset:XX00hOffset:0080hAccess:ReadWriteBitBitNameDescription15ResetReset:Default:0,RW/SC1=InitiatesoftwareReset/ResetinProcess0=NormaloperationThisbit,whichisself-clearing,returnsavalueofoneuntiltheresetprocessiscomplete.
Theconfigurationisre-strapped.
14LoopbackLoopback:Default:01=Loopbackenabled0=NormaloperationTheloopbackfunctionenablesMIItransmitdatatoberoutedtotheMIIreceivedatapath.
Settingthisbitmaycausethede-scramblertolosesynchronizationandproducea500s"deadtime"beforeanyvaliddatawillappearattheMIIreceiveoutputs.
13SpeedSelectionSpeedSelect:Default:dependentonthesettingoftheANEG_SELbitsintheCFGregisterWhenauto-negotiationisdisabledwritingtothisbitallowstheportspeedtobeselected.
1=100Mb/s0=10Mb/s12Auto-NegotiationEnableAuto-NegotiationEnable:Default:dependentonthesettingoftheANEG_SELbitsintheCFGregister1=Auto-NegotiationEnabled-bits8and13ofthisregisterareignoredwhenthisbitisset.
0=Auto-NegotiationDisabled-bits8and13determinetheportspeedandduplexmode.
11PowerDownPowerDown:Default:01=Powerdown0=NormaloperationSettingthisbitpowersdowntheport.
10IsolateIsolate:Default:01=IsolatestheportfromtheMIIwiththeexceptionoftheserialmanagement.
0=Normaloperation9RestartAuto-NegotiationRestartAuto-Negotiation:Default:0,RW/SC1=RestartAuto-Negotiation0=NormaloperationWhenthisbitisset,itre-initiatestheAuto-Negotiationprocess.
IfAuto-Negotiationisdisabled(bit12=0),thisbitisignored.
Thisbitisself-clearingandwillremainavalueof1untilAuto-Negotiationisinitiated,whereuponitwillself-clear.
OperationoftheAuto-Negotiationprocessisnotaffectedbythemanagemententityclearingthisbit.
8DuplexModeDuplexMode:Default:dependentonthesettingoftheANEG_SELbitsintheCFGregisterWhenauto-negotiationisdisabledwritingtothisbitallowstheportDuplexcapabilitytobeselected.
1=FullDuplexoperation0=HalfDuplexoperation68www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
2BasicModeStatusRegister7CollisionTestCollisionTest:Default:01=Collisiontestenabled0=NormaloperationWhenset,thisbitwillcausetheCOLsignaltobeassertedinresponsetotheassertionofTXENwithin512-bittimes.
TheCOLsignalwillbede-assertedwithin4-bittimesinresponsetothede-assertionofTXEN.
6:0ReservedReserved:Default:0,ROTag:BMSRSize:16bitsHardReset:7849hOffset:0084hAccess:ReadOnlyBitBitNameDescription15100BASE-T4100BASE-T4Capable:Default:00=Devicenotabletoperform100BASE-T4mode.
14100BASE-TXFullDuplex100BASE-TXFullDuplexCapable:Default:11=Deviceabletoperform100BASE-TXinfullduplexmode13100BASE-TXHalfDuplex100BASE-TXHalfDuplexCapable:Default:11=Deviceabletoperform100BASE-TXinhalfduplexmode.
1210BASE-TFullDuplex10BASE-TFullDuplexCapable:Default:11=Deviceabletoperform10BASE-Tinfullduplexmode1110BASE-THalfDuplex10BASE-THalfDuplexCapable:Default:11=Deviceabletoperform10BASE-Tinhalfduplexmode10:7ReservedReserved:Writeas0,readas06PreambleSuppressionPreamblesuppressionCapable:Default:11=Deviceabletoperformmanagementtransactionwithpreamblesuppressed,32-bitsofpreambleneededonlyonceafterreset,invalidopcodeorinvalidturnaround.
0=Normalmanagementoperation5Auto-NegotiationCompleteAuto-NegotiationComplete:Default:01=Auto-Negotiationprocesscomplete0=Auto-Negotiationprocessnotcomplete4RemoteFaultRemoteFault:Default:0/L(H)1=RemoteFaultconditiondetected(clearedonreadorbyreset).
Faultcriteria:FarEndFaultIndicationornotificationfromLinkPartnerofRemoteFault.
0=Noremotefaultconditiondetected3Auto-NegotiationAbilityAutoConfigurationAbility:Default:11=DeviceisabletoperformAuto-Negotiation0=DeviceisnotabletoperformAuto-Negotiation2LinkStatusLinkStatus:Default:0/L(L)1=Validlinkestablished(foreither10or100Mb/soperation)0=LinknotestablishedThecriteriaforlinkvalidityisimplementationspecific.
TheoccurrenceofalinkfailureconditionwillcausetheLinkStatusbittoclear.
Oncecleared,thisbitmayonlybesetbyestablishingagoodlinkconditionandareadviathemanagementinterface.
1JabberDetectJabberDetect:Default:0/LH1=Jabberconditiondetected0=NoJabberThisbitisimplementedwithalatchingfunction,suchthattheoccurrenceofajabberconditioncausesittosetuntilitisclearedbyareadtothisregisterbythemanagementinterfaceorbyareset.
Thisbitonlyhasmeaningin10Mb/smode.
0ExtendedCapabilityExtendedCapability:Default:11=Extendedregistercapabilities0=BasicregistersetcapabilitiesonlyBitBitNameDescription69www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
3PHYIdentifierRegister#1ThePHYIdentifierRegisters#1and#2togetherformauniqueidentifierforthePHYsectionofthisdevice.
TheIdentifierconsistsofaconcatenationoftheOrganizationallyUniqueIdentifier(OUI),thevendor'smodelnumberandthemodelrevisionnumber.
APHYmayreturnavalueofzeroineachofthe32bitsofthePHYIdentifierifdesired.
ThePHYIdentifierisintendedtosupportnetworkmanagement.
NationalSemiconductor'sIEEEassignedOUIis080017h.
4.
3.
4PHYIdentifierRegister#24.
3.
5Auto-NegotiationAdvertisementRegisterThisregistercontainstheadvertisedabilitiesofthisdeviceastheywillbetransmittedtoitslinkpartnerduringAuto-Negotiation.
Tag:PHYIDR1Size:16bitsHardReset:2000hOffset:0088hAccess:ReadOnlyBitBitNameDescription15:0OUI_MSBOUIMostSignificantBits:Default:Bits3to18oftheOUI(080017h)arestoredinbits15to0ofthisregister.
ThemostsignificanttwobitsoftheOUIareignored(theIEEEstandardreferstotheseasbits1and2).
Tag:PHYIDR2Size:16bitsHardReset:5C21hOffset:008ChAccess:ReadOnlyBitBitNameDescription15:10OUI_LSBOUILeastSignificantBits:Default:Bits19to24oftheOUI(080017h)aremappedtobits15to10ofthisregisterrespectively.
9:4VNDR_MDLVendorModelNumber:Default:Thesixbitsofvendormodelnumberaremappedtobits9to4(mostsignificantbittobit9).
3:0MDL_REVModelRevisionNumber:Default:Fourbitsofthevendormodelrevisionnumberaremappedtobits3to0(mostsignificantbittobit3).
Thisfieldwillbeincrementedforallmajordevicechanges.
Tag:ANARSize:16bitsHardReset:05E1hOffset:0090hAccess:ReadWriteBitBitNameDescription15NPNextPageIndication:Default:00=NextPageTransfernotdesired1=NextPageTransferdesired14ReservedReservedbyIEEE:Writesignored,Readas013RFRemoteFault:Default:01=AdvertisesthatthisdevicehasdetectedaRemoteFault0=NoRemoteFaultdetected12:11ReservedReservedforFutureIEEEuse:Writeas0,Readas010PAUSEPAUSE:Default:dependentonthesettingofthePAUSE_ADVintheCFGregister1=AdvertisethattheDTE(MAC)hasimplementedboththeoptionalMACcontrolsublayerandthepausefunctionasspecifiedinclause31andannex31Bof802.
3u.
0=NoMACbasedfullduplexflowcontrol70www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
6Auto-NegotiationLinkPartnerAbilityRegisterThisregistercontainstheadvertisedabilitiesoftheLinkPartnerasreceivedduringAuto-Negotiation.
Thecontentchangesafterthesuccessfulauto-negotiationifNext-pagesaresupported.
9T4100BASE-T4Support:Default:0/RO1=100BASE-T4issupportedbythelocaldevice0=100BASE-T4notsupported8TX_FD100BASE-TXFullDuplexSupport:Default:dependentonsettingoftheANEG_SELintheCFGregister1=100BASE-TXFullDuplexissupportedbythelocaldevice0=100BASE-TXFullDuplexnotsupported7TX100BASE-TXSupport:Default:dependentonthesettingoftheANEG_SELbitsintheCFGregister1=100BASE-TXissupportedbythelocaldevice0=100BASE-TXnotsupported610_FD10BASE-TFullDuplexSupport:Default:dependentonsettingoftheANEG_SELintheCFGregister1=10BASE-TFullDuplexissupportedbythelocaldevice0=10BASE-TFullDuplexnotsupported51010BASE-TSupport:Default:dependentonthesettingoftheANEG_SELbitsintheCFGregister1=10BASE-Tissupportedbythelocaldevice0=10BASE-Tnotsupported4:0SelectorProtocolSelectionBits:Default:Thesebitscontainthebinaryencodedprotocolselectorsupportedbythisport.
indicatesthatthisdevicesupportsIEEE802.
3u.
Tag:ANLPARSize:16bitsHardReset:0000hOffset:0094hAccess:ReadOnlyBitBitNameDescription15NPNextPageIndication:0=LinkPartnerdoesnotdesireNextPageTransfer1=LinkPartnerdesiresNextPageTransfer14ACKAcknowledge:1=LinkPartneracknowledgesreceptionoftheabilitydataword0=NotacknowledgedTheDevice'sAuto-NegotiationstatemachinewillautomaticallycontrolthisbitbasedontheincomingFLPbursts.
13RFRemoteFault:1=RemoteFaultindicatedbyLinkPartner0=NoRemoteFaultindicatedbyLinkPartner12:10ReservedReservedforFutureIEEEuse:Writeas0,readas09T4100BASE-T4Support:1=100BASE-T4issupportedbytheLinkPartner0=100BASE-T4notsupportedbytheLinkPartner8TX_FD100BASE-TXFullDuplexSupport:1=100BASE-TXFullDuplexissupportedbytheLinkPartner0=100BASE-TXFullDuplexnotsupportedbytheLinkPartner7TX100BASE-TXSupport:1=100BASE-TXissupportedbytheLinkPartner0=100BASE-TXnotsupportedbytheLinkPartner610_FD10BASE-TFullDuplexSupport:1=10BASE-TFullDuplexissupportedbytheLinkPartner0=10BASE-TFullDuplexnotsupportedbytheLinkPartnerBitBitNameDescription71www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
7Auto-NegotiateExpansionRegisterThisregistercontainsadditionalLocalDeviceandLinkPartnerstatusinformation.
4.
3.
8Auto-NegotiationNextPageTransmitRegisterThisregistercontainsthenextpageinformationsentbythisdevicetoitsLinkPartnerduringAuto-Negotiation.
51010BASE-TSupport:1=10BASE-TissupportedbytheLinkPartner0=10BASE-TnotsupportedbytheLinkPartner4:0SelectorProtocolSelectionBits:LinkPartners'sbinaryencodedprotocolselector.
Tag:ANERSize:16bitsHardReset:0004hOffset:0098hAccess:ReadOnlyBitBitNameDescription15:5ReservedReserved:Writesignored,Readas0.
4PDFParallelDetectionFault:1=AfaulthasbeendetectedviatheParallelDetectionfunction0=Afaulthasnotbeendetected3LP_NP_ABLELinkPartnerNextPageAble:1=LinkPartnerdoessupportNextPage0=LinkPartnerdoesnotsupportNextPage2NP_ABLENextPageAble:1=Indicateslocaldeviceisabletosendadditional"NextPages"1PAGE_RXLinkCodeWordPageReceived:RO/COR1=LinkCodeWordhasbeenreceived,clearedonaread0=LinkCodeWordhasnotbeenreceived0LP_AN_ABLELinkPartnerAuto-NegotiationAble:1=IndicatesthattheLinkPartnersupportsAuto-Negotiation0=IndicatesthattheLinkPartnerdoesnotsupportAuto-NegotiationTag:ANNPTRSize:16bitsHardReset:2001hOffset:009ChAccess:ReadWriteBitBitNameDescription15NPNextPageIndication:Default:00=NootherNextPageTransferdesired1=AnotherNextPagedesired14ReservedReserved:Writesignored,readas013MPMessagePage:Default:11=MessagePage0=Un-formattedPageBitBitNameDescription72www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
9PHYStatusRegisterThisregisterprovidesasinglelocationwithintheregistersetforquickaccesstocommonlyaccessedinformation.
12ACK2Acknowledge2:Default:01=Willcomplywithmessage0=CannotcomplywithmessageAcknowledge2isusedbythenextpagefunctiontoindicatethatLocalDevicehastheabilitytocomplywiththemessagereceived.
11TOG_TXToggle:Default:0,RO1=ValueoftogglebitinpreviouslytransmittedLinkCodeWordwas00=ValueoftogglebitinpreviouslytransmittedLinkCodeWordwas1ToggleisusedbytheArbitrationfunctionwithinAuto-NegotiationtoensuresynchronizationwiththeLinkPartnerduringNextPageexchange.
ThisbitshallalwaystaketheoppositevalueoftheTogglebitinthepreviouslyexchangedLinkCodeWord.
10:0CODECodeField:Default:Thisfieldrepresentsthecodefieldofthenextpagetransmission.
IftheMPbitisset(bit13ofthisregister),thenthecodeshallbeinterpretedasa"MessagePage",asdefinedinannex28CofIEEE802.
3u.
Otherwise,thecodeshallbeinterpretedasan"Un-formattedPage",andtheinterpretationisapplicationspecific.
ThedefaultvalueoftheCODErepresentsaNullPageasdefinedinAnnex28CofIEEE802.
3u.
Tag:PHYSTSSize:16bitsHardReset:0000hOffset:00C0hAccess:ReadOnlyBitBitNameDescription15:14ReservedReserved:Writeignored,readas0.
13ReceiveErrorLatchReceiveErrorLatch:ThisbitwillbecleareduponareadoftheRECRregister.
1=ReceiveerroreventhasoccurredsincelastreadofRXERCNT(address0xD4)0=Noreceiveerroreventhasoccurred12PolarityStatusPolarityStatus:Thisbitisaduplicationofbit4intheTBTSCRregister.
ThisbitwillbecleareduponareadoftheTBTSCRregister,butnotuponareadofthePHYSTSregister.
1=InvertedPolaritydetected0=CorrectPolaritydetected11FalseCarrierSenseLatchFalseCarrierSenseLatch:Default:0,RO/LHThisbitwillbecleareduponareadoftheFCSRregister.
1=FalseCarriereventhasoccurredsincelastreadofFCSCR(address0xD0)0=NoFalseCarriereventhasoccurred10SignalDetectSignalDetect:Default:0,RO/LL100BASE-TXunconditionalSignalDetectfromPMD.
9De-scramblerLockDe-scramblerLock:Default:0,RO/LL100BASE-TXDe-scramblerLockfromPMD.
8PageReceivedLinkCodeWordPageReceived:ThisisaduplicateofthePageReceivedbitintheANERregister,butthisbitwillnotbecleareduponareadofthePHYSTSregister.
1=AnewLinkCodeWordPagehasbeenreceived.
ClearedonreadoftheANER(address0x06,bit1)0=LinkCodeWordPagehasnotbeenreceived7MIIInterruptMIIInterruptPending:Default:0,RO/LH1=Indicatesthataninternalinterruptispending,clearedbythecurrentread0=NointerruptpendingBitBitNameDescription73www.
national.
com4.
0RegisterSet(Continued)DP838156RemoteFaultRemoteFault:1=RemoteFaultconditiondetected(clearedonreadofBMSR(address0x84h)registerorbyreset).
Faultcriteria:notificationfromLinkPartnerofRemoteFaultviaAuto-Negotiation0=Noremotefaultconditiondetected5JabberDetectJabberDetect:Thisbitonlyhasmeaningin10Mb/smodeThisbitisaduplicateoftheJabberDetectbitintheBMSRregister,exceptthatitisnotcleareduponareadofthePHYSTSregister.
1=Jabberconditiondetected0=NoJabber4Auto-Neg.
CompleteAuto-NegotiationComplete:1=Auto-Negotiationcomplete0=Auto-Negotiationnotcomplete3LoopbackStatusLoopback:1=Loopbackenabled0=Normaloperation2DuplexStatusDuplex:ThisbitindicatesduplexstatusandisdeterminedfromAuto-NegotiationorForcedModes.
1=Fullduplexmode0=HalfduplexmodeNote:ThisbitisonlyvalidifAuto-NegotiationisenabledandcompleteandthereisavalidlinkorifAuto-Negotiationisdisabledandthereisavalidlink.
1SpeedStatusSpeed10:ThisbitindicatesthestatusofthespeedandisdeterminedfromAuto-NegotiationorForcedModes.
1=10Mb/smode0=100Mb/smodeNote:ThisbitisonlyvalidifAuto-NegotiationisenabledandcompleteandthereisavalidlinkorifAuto-Negotiationisdisabledandthereisavalidlink.
0LinkStatusLinkStatus:ThisbitisaduplicateoftheLinkStatusbitintheBMSRregister,exceptthatitwillnotbecleareduponareadofthePHYSTSregister.
1=Validlinkestablished(foreither10or100Mb/soperation)0=LinknotestablishedBitBitNameDescription74www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
10MIIInterruptControlRegisterThisregisterimplementstheMIIInterruptPHYSpecificControlregister.
Sourcesforinterruptgenerationinclude:LinkStateChange,JabberEvent,RemoteFault,Auto-NegotiationCompleteoranyofthecountersbecominghalf-full.
NotethattheTINTbitoperatesindependentlyoftheINTENbit.
Inotherwords,INTENdoesnotneedtobeactivetogeneratethetestinterrupt.
4.
3.
11MIIInterruptStatusandMisc.
ControlRegisterThisregisterimplementstheMIIInterruptPHYControlandStatusinformation.
TheseInterruptsarePHYbasedevents.
Whenanyoftheseeventsoccuranditsrespectivebitisnotmasked,andMICR:INTENisenabled,theinterruptwillbesignalledinISR:PHY.
Tag:MICRSize:16bitsHardReset:0000hOffset:00C4hAccess:ReadWriteBitBitNameDescription15:2ReservedReserved:Writesignored,Readas01INTENInterruptEnable:1=Enableeventbasedinterrupts0=Disableeventbasedinterrupts0TINTTestInterrupt:ForcesthePHYtogenerateaninterruptattheendofeachmanagementreadtofacilitateinterrupttesting.
1=Generateaninterrupt0=DonotgenerateinterruptTag:MISRSize:16bitsHardReset:0000hOffset:00C8hAccess:ReadWriteBitBitNameDescription15MINTMIIInterruptPending:Default:0,RO/COR1=Indicatesthataninterruptispendingandisclearedbythecurrentread.
0=nointerruptpending14MSK_LINKMaskLink:Whenthisbitis0,thechangeoflinkstatuseventwillcausetheinterrupttobeseenbytheISR.
13MSK_JABMaskJabber:Whenthisbitis0,theJabbereventwillcausetheinterrupttobeseenbytheISR.
12MSK_RFMaskRemoteFault:Whenthisbitis0,theRemoteFaulteventwillcausetheinterrupttobeseenbytheISR.
11MSK_ANCMaskAuto-Neg.
Complete:Whenthisbitis0,theAuto-negotiationcompleteeventwillcausetheinter-rupttobeseenbytheISR.
10MSK_FHFMaskFalseCarrierHalfFull:Whenthisbitis0,theFalseCarrierCounterRegisterhalf-fulleventwillcausetheinterrupttobeseenbytheISR.
9MSK_RHFMaskRxErrorHalfFull:Whenthisbitis0,theReceiveErrorCounterRegisterhalf-fulleventwillcausetheinterrupttobeseenbytheISR.
8:0ReservedReserved:Default:0,RO75www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
12FalseCarrierSenseCounterRegisterThiscounterprovidesinformationrequiredtoimplementthe"FalseCarriers"attributewithintheMAUmanagedobjectclassofClause30oftheIEEE802.
3uspecification.
4.
3.
13ReceiverErrorCounterRegisterThiscounterprovidesinformationrequiredtoimplementthe"SymbolErrorDuringCarrier"attributewithinthePHYmanagedobjectclassofClause30oftheIEEE802.
3uspecification.
4.
3.
14100Mb/sPCSConfigurationandStatusRegisterTag:FCSCRSize:16bitsHardReset:0000hOffset:00D0hAccess:ReadWriteBitBitNameDescription15:8ReservedReserved:Writesignored,Readas07:0FCSCNT[7:0]FalseCarrierEventCounter:Default:0,RW/CORThis8-bitcounterincrementsoneveryfalsecarrierevent.
Thiscounterstickswhenitreachesitsmaxcount(FFh).
Tag:RECRSize:16bitsHardReset:0000hOffset:00D4hAccess:ReadWriteBitBitNameDescription15:8ReservedReserved:Writesignored,Readas07:0RXERCNT[7:0]RXERCounter:Default:0,RW/CORThis8-bitcounterincrementsforeachreceiveerrordetected.
whenavalidcarrierispresentandthereisatleastoneoccurrenceofaninvaliddatasymbol.
Thiseventcanincrementonlyoncepervalidcarrierevent.
Ifacollisionispresent,theattributewillnotincrement.
Thecounterstickswhenitreachesitsmaxcount.
Tag:PCSRSize:16bitsHardReset:0100hOffset:00D8hAccess:ReadWriteBitBitNameDescription15:13ReservedReserved:Writesignored,Readas012BYP_4B5BBypass4B/5BEncoding:1=4B5Bencoderfunctionsbypassed0=Normal4B5Boperation11FREE_CLKReceiveClock:1=RX_CKisfree-running0=RX_CKphaseadjustedbasedonalignment10TQ_EN100Mb/sTrueQuietModeEnable:1=TransmitTrueQuietMode0=NormalTransmitMode9SD_FORCE_BSignalDetectForce:1=ForcesSignalDetection0=NormalSDoperation76www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
15PHYControlRegister8SD_OPTIONSignalDetectOption:1=Enhancedsignaldetectalgorithm0=Reducedsignaldetectalgorithm7:6ReservedReserved:Readas05FORCE_100_OKForce100Mb/sGoodLink:OR'edwithMAC_FORCE_LINK_100signal.
1=Forces100Mb/sGoodLink0=Normal100Mb/soperation4:3ReservedReserved:Readas02NRZI_BYPASSNRZIBypassEnable:1=NRZIBypassEnabled0=NRZIBypassDisabled1:0ReservedReserved:Readas0Tag:PHYCRSize:16bitsHardReset:003FhOffset:00E4hAccess:ReadWriteBitBitNameDescription15:12ReservedReserved11PSR_15BISTSequenceselect:SelectslengthofLFSRusedinBIST1=PSR15selected0=PSR9selected10BIST_STATUSBISTTestStatus:Default:0,LL/RO1=BISTpass0=BISTfail.
Latched,clearedbywritetoBISTstartbit.
9BIST_STARTBISTStart:BISTrunscontinuouslyuntilstopped.
Minimumtimetorunshouldbe1ms.
1=BISTstart0=BISTstop8BP_STRETCHBypassLEDStretching:ThiswillbypasstheLEDstretchingandtheLEDswillreflecttheinternalvalue.
1=BypassLEDstretching0=Normaloperation7PAUSE_STSPauseCompareStatus:Default:0,RO0=LocalDeviceandtheLinkPartnerarenotPausecapable1=LocalDeviceandtheLinkPartnerarebothPausecapable6:5ReservedReserved4:0PHYADDR[4:0]PHYAddress:Default:,RWPHYaddressfortheport.
BitBitNameDescription77www.
national.
com4.
0RegisterSet(Continued)DP838154.
3.
1610BASE-TStatus/ControlRegisterTag:TBTSCRSize:16bitsHardReset:0004hOffset:00E8hAccess:ReadWriteBitBitNameDescription15:9Unused8LOOPBACK_10_DIS10BASE-TLoopbackDisable:ThisbitisOR'edwithbit14(Loopback)intheBMCR.
1=10Mb/sLoopbackisenabled0=10Mb/sLoopbackisdisabled7LP_DISNormalLinkPulseDisable:ThisbitisOR'edwiththeMAC_FORCE_LINK_10signal.
1=TransmissionofNLPsisdisabled0=TransmissionofNLPsisenabled6FORCE_LINK_10Force10Mb/sGoodLink:ThisbitisOR'edwiththeMAC_FORCE_LINK_10signal.
1=ForcedGood10Mb/sLink0=NormalLinkStatus5FORCE_POL_CORForce10Mb/sPolarityCorrection:1=Forceinvertedpolarity0=Normalpolarity4POLARITY10Mb/sPolarityStatus:RO/LHThisbitisaduplicationofbit12inthePHYSTSregister.
Bothbitswillbecleareduponareadofeitherregister.
1=InvertedPolaritydetected0=CorrectPolaritydetected3AUTOPOL_DISAutoPolarityDetection&CorrectionDisable:1=PolaritySense&Correctiondisabled0=PolaritySense&Correctionenabled2ReservedReservedThisbitmustbewrittenasaone.
1HEARTBEAT_DISHeartbeatDisable:Thisbitonlyhasinfluenceinhalf-duplex10Mb/smode.
1=Heartbeatfunctiondisabled0=HeartbeatfunctionenabledWhenthedeviceisoperatingat100Mb/sorconfiguredforfullduplex,thisbitwillbeignored-theheartbeatfunctionisdisabled.
0JABBER_DISJabberDisable:Applicableonlyin10BASE-TFullDuplex.
1=Jabberfunctiondisabled0=Jabberfunctionenabled4.
0RegisterSet(Continued)Subjecttochangewithoutnotice.
78RevOwww.
national.
comDP838154.
4RecommendedRegistersConfigurationForoptimumperformanceoftheDP83815,versionnotedasDP83815CVNG(SRR=302h),thelistedregistermodificationsmustbefollowedinsequence.
Thetablebelowcontainstheregister'soffsetaddressvalue.
Theregisteraddressconsistsof:I/OBaseAddress+OffsetAddress.
Allvaluesaregiveninhex.
Allotherregisterscanremainattheirdefaultvalues,ordesiredconfigurationsettings.
RegisterOffsetAddressRegisterTagRegisterValue1.
00CChPGSEL0001h2.
00E4hPMDCSR189Ch3.
00FChTSTDAT0000h4.
00F4hDSPCFG5040h5.
00F8hSDCFG008Ch79www.
national.
comDP838155.
0BufferManagementThebuffermanagementschemeusedontheDP83815allowsquick,simpleandefficientuseoftheframebuffermemory.
Framesaresavedinsimilarformatsforbothtransmitandreceive.
Thebuffermanagementschemealsousesseparatebuffersanddescriptorsforpacketinformation.
Thisallowseffectivetransfersofdatafromthereceivebuffertothetransmitbufferbysimplytransferringthedescriptorfromthereceivequeuetothetransmitqueue.
Theformatofthedescriptorsallowsthepacketstobesavedinanumberofconfigurations.
Apacketcanbestoredinmemorywithasingledescriptorandasinglepacketfragment,ormultipledescriptorseachwithasinglefragment.
ThisflexibilityallowstheusertoconfiguretheDP83815tomaximizeefficiency.
Architectureofthespecificsystem'sbuffermemory,aswellasthenatureofnetworktraffic,willdeterminethemostsuitableconfigurationofpacketdescriptorsandfragments.
5.
1OverviewThebuffermanagementdesignhasthefollowinggoals:—simplicity,—efficientuseofthePCIbus(theoverheadofthebuffermanagementtechniqueisminimal),—lowCPUutilization,—flexibility.
Descriptorsmaybeeitherper-packetorper-packet-fragment.
Eachdescriptormaydescribeonepacketfragment.
Receiveandtransmitdescriptorsaresymmetrical.
5.
1.
1DescriptorFormatDP83815usesasymmetricalformatfortransmitandreceivedescriptors.
InbridgingandswitchingapplicationsthissymmetryallowssoftwaretoforwardpacketsbysimplymovingthelistofdescriptorsthatdescribeasinglereceivedpacketfromthereceivelistofoneMACtothetransmitlistofanother.
Descriptorsmustbealignedonanevenlongword(32-bit)boundary.
Table5-1DP83815DescriptorFormatTheoriginalDP83810ADescriptorformatsupportedmultiplefragmentsperdescriptor.
DP83815onlysupportsasinglefragmentperdescriptor.
Bydefault,DP83815willusethedescriptorformatshownabove.
BysettingCFG:EUPHCOMP,softwaremayforcecompatibilitywiththepreviousDP83810ADescriptorformat(althoughstillonlysinglefragmentdescriptorsaresupported).
WhenCFG:EUPHCOMPisset,thenbufptrisatoffset0Ch,andthe32-bitbufcntfieldatoffset08hisignored.
Someofthebitdefinitionsinthecmdstsfieldarecommontobothreceiveandtransmitdescriptors:Table5-2cmdstsCommonBitDefinitionsOffsetTagDescription0000hlink32-bit"link"fieldtothenextdescriptorinthelinkedlist.
Bits1-0mustbe0,asdescriptorsmustbealignedon32-bitboundaries.
0004hcmdsts32-bitCommand/StatusField(bit-encoded).
0008hbufptr32-bitpointertothefirstfragmentorbuffer.
Intransmitdescriptors,thebuffercanbeginonanybyteboundary.
Inreceivedescriptors,thebuffermustbealignedona32-bitboundary.
BitTagDescriptionUsage31OWNDescriptorOwnershipSetto1bythedataproducerofthedescriptortotransferownershiptothedataconsumerofthedescriptor.
Setto0bythedataconsumerofthedescriptortoreturnownershiptothedataproducerofthedescriptor.
Fortransmitdescriptors,thedriveristhedataproducer,andtheDP83815isthedataconsumer.
Forreceivedescriptors,theDP83815isthedataproducer,andthedriveristhedataconsumer.
30MOREMoredescriptorsSetto1toindicatethatthisisNOTthelastdescriptorinapacket(thereareMOREtofollow).
When0,thisdescriptoristhelastdescriptorinapacket.
Completionstatusbitsareonlyvalidwhenthisbitiszero.
29INTRInterruptSetto1bysoftwaretorequesta"descriptorinterrupt"whenDP83815transferstheownershipofthisdescriptorbacktosoftware.
28SUPCRCINCCRCSuppressCRC/IncludeCRCIntransmitdescriptors,thisindicatesthatCRCshouldnotbeappendedbytheMAC.
Onreceives,thisbitisalwaysset,astheCRCisalwayscopiedtotheendofthebufferbythehardware.
80www.
national.
com5.
0BufferManagement(Continued)DP83815Table5-3TransmitStatusBitDefinitions27OKPacketOKInthelastdescriptorinapacket,thisbitindicatesthatthepacketwaseithersentorreceivedsuccessfully.
26-16---Theusageofthesebitsdifferinreceiveandtransmitdescriptors.
Seebelowfordetails.
15-12(reserved)11-0SIZEDescriptorByteCountSettothesizeinbytesofthedata.
BitTagDescriptionUsage26TXATransmitAbortTransmissionofthispacketwasaborted.
25TFUTransmitFIFOUnderrunTransmitFIFOwasexhaustedduringthetransmissionofthispacket.
24CRSCarrierSenseLostCarrierwaslostduringthetransmissionofthispacket.
ThisconditionisnotreportedifTXCFG:CSIisset.
23TDTransmitDeferredTransmissionofthispacketwasdeferred.
22EDExcessiveDeferralThelengthofdeferralduringthetransmissionofthispacketwasexcessive(>3.
2ms),indicatingtransmissionfailure.
21OWCOutofWindowCollisionTheMACencounteredan"outofwindow"collisionduringthetransmissionofthispacket.
20ECExcessiveCollisionsThenumberofcollisionsduringthetransmissionofthispacketwasexcessive,indicatingtransmissionfailure.
IfTXCFGregisterECRETRY=0,thisbitissetafter16collisions.
IfTXCFGregisterECRETRY=1,thisbitissetafter4ExcessiveCollisionevents(64collisions).
19-16CCNTCollisionCountIfTXCFGregisterECRETRY=0,thisfieldindicatesthenumberofcollisionsencounteredduringthetransmissionofthispacket.
IfTXCFGregisterECRETRY=1,CCNT[3:2]=ExcessiveCollisions(0-3)CCNT[1]=MultipleCollisionsCCNT[0]=SingleCollisionNotethatExcessiveCollisionsindicate16attemptsfailed,whilemultipleandsinglecollisionsindicatecollisionsinadditiontoanyexcessivecollisions.
Forexampleacollisioncountof33includes2ExcessiveCollisionsandwillalsosettheSingleCollisionbit.
81www.
national.
com5.
0BufferManagement(Continued)DP83815Table5-4ReceiveStatusBitDefinitions5.
1.
2SingleDescriptorPacketsTorepresentapacketinasingledescriptor,theMOREbitinthecmdstsfieldissetto0.
Figure5-1SingleDescriptorPacketsBitTagDescriptionUsage26RXAReceiveAbortedSetto1byDP83815whenthereceivewasaborted,thevalueofthisbitalwaysequalsRXO.
Existsforbackwardcompatibility.
25RXOReceiveOverrunSetto1byDP83815toindicatethatareceiveoverrunconditionoccurred.
RXAwillalsobeset.
24-23DESTDestinationClassWhenthereceivefilterisenabled,thesebitswillindicatethedestinationaddressclassasfollows:00-Packetwasrejected01-DestinationisaUnicastaddress10-DestinationisaMulticastaddress11-DestinationisaBroadcastaddressIftheReceiveFilterisenabled,00indicatesthatthepacketwasrejected.
Normallypacketsthatarerejecteddonotcauseanybusactivity,nordotheyconsumereceivedescriptors.
However,thisconditioncouldoccurifthepacketisrejectedbytheReceiveFilterlaterinthepacketthanthereceivedrainthreshold(RXCFG:DRTH).
Note:TheDESTbitsmaynotrepresentacorrectDAclassforruntpacketsreceivedwithlessthan6bytes.
22LONGTooLongPacketReceivedIfRXCFG:ALP=0,thisflagindicatesthatthesizeofthereceivepacketexceeded1518bytes.
IfRXCFG:ALP=1,thisflagindicatesthatthesizeofthereceivepacketexceeded2046bytes.
21RUNTRuntPacketReceivedThesizeofthereceivepacketwaslessthan64bytes(inc.
CRC).
20ISEInvalidSymbolError(100Mb/sonly)Aninvalidsymbolwasencounteredduringthereceptionofthispacket.
19CRCECRCErrorTheCRCappendedtotheendofthispacketwasinvalid.
18FAEFrameAlignmentErrorThepacketdidnotcontainanintegralnumberofoctets.
17LBPLoopbackPacketThepacketistheresultofaloopbacktransmission.
16COLCollisionActivityThereceivepackethadacollisionduringreception.
linkptrMAChdrnetwkhdrdata064singledescriptor/singlefragment5.
0BufferManagement(Continued)Subjecttochangewithoutnotice.
82RevOwww.
national.
comDP838155.
1.
3MultipleDescriptorPacketsAsinglepacketmayalsocrossdescriptorboundaries.
ThisisindicatedbysettingtheMOREbitinalldescriptorsexceptthelastoneinthepacket.
Ethernetapplications(bridges,switches,routers,etc.
)canoptimizememoryutilizationbyusingasinglesmallbufferperreceivedescriptor,andallowingtheDP83815hardwaretousetheminimumnumberofbuffersnecessarytostoreanincomingpacket.
5.
1.
4DescriptorListsDescriptorsareorganizedinlinkedlistsusingthelinkfield.
Thesystemdesignermayalsochoosetoimplementa"ring"ofdescriptorsbylinkingthelastdescriptorinthelistbacktothefirst.
Alistofdescriptorsmayrepresentanynumberofpacketsorpacketfragments.
Figure5-2MultipleDescriptorPacketsFigure5-3ListandRingDescriptorOrganizationlinkptrMAChdrnetwkhdrdata114multipledescriptor/singlefragmentlinkptr120linkptr03010180addr1014010140addr10100101C0addr1018010100addr101C0DescriptorsOrganizedinaRing10180addr1014010140addr10100101C0addr1018000000addr101C0DescriptorsOrganizedinaLinkedList5.
0BufferManagement(Continued)Subjecttochangewithoutnotice.
83RevOwww.
national.
comDP838155.
2TransmitArchitectureThefollowingfigureillustratesthetransmitarchitectureoftheDP8381510/100EthernetController.
Figure5-4TransmitArchitectureWhentheCR:TXEbitissetto1(regardlessofthecurrentstate),andtheDP83815transmitterisidle,thenDP83815willreadthecontentsofthecurrenttransmitdescriptorintotheTxDescCache.
TheDP83815'sTxDescCachecanholdasinglefragmentpointer/countcombination.
5.
2.
1TransmitStateMachineThetransmitstatemachinehasthefollowingstates:Thetransmitstatemachinemanipulatesthefollowinginternaldataspaces:Inputstothetransmitstatemachineincludethefollowingevents:TransmitDescriptorCurrentTxDescPtrSoftware/MemoryHardwareTxDataFIFOlinkcmdstsptrptrTxDMAcmdstsPacketTxHeadlinkTxDescCachetxIdleThetransmitstatemachineisidle.
txDescRefrWaitingforthe"refresh"transferofthelinkfieldofacompleteddescriptorfromthePCIbus.
txDescReadWaitingforthetransferofacompletedescriptorfromthePCIbusintotheTxDescriptorCache.
txFifoBlockWaitingforfreespaceintheTxDataFIFOtoreachTxFillThreshold.
txFragReadWaitingforthetransferofafragment(orportionofafragment)fromthePCIbustotheTxDataFIFO.
txDescWriteWaitingforthecompletionofthewriteofthecmdstsfieldofanintermediatetransmitdescriptor(cmdsts.
MORE==1)tohostmemory.
txAdvance(transitorystate)ExaminethelinkfieldofthecurrentdescriptorandadvancetothenextdescriptoriflinkisnotNULL.
TXDPA32-bitregisterthatpointstothecurrenttransmitdescriptor.
CTDDAninternalbitflagthatissetwhenthecurrenttransmitdescriptorhasbeencompleted,andownershiphasbeenreturnedtothedriver.
ItisclearedwheneverTXDPisloadedwithanewvalue(eitherbythestatemachine,orthedriver).
TxDescCacheAninternaldataspaceequaltothesizeofthemaximumtransmitdescriptorsupported.
descCntCountofbytesremaininginthecurrentdescriptor.
fragPtrPointertothenextunreadbyteinthecurrentfragment.
txFifoCntCurrentamountofdatainthetxDataFifoinbytes.
txFifoAvailCurrentamountoffreespaceinthetxDataFifoinbytes(sizeofthetxDataFifo-txFifoCnt).
CR:TXEDriverassertstheTXEbitinthecommandregister(similartoSONIC).
XferDoneCompletionofaPCIbustransferrequest.
FifoAvailTxFifoAvailisgreaterthanTxFillThreshold.
84www.
national.
com5.
0BufferManagement(Continued)DP83815Table5-5TransmitStateTablesFigure5-5TransmitStateDiagramStateEventNextStateActionstxIdleCR:TXE&&!
CTDDtxDescReadStartabursttransferataddressTXDPandalengthderivedfromTXCFG.
CR:TXE&&CTDDtxDescRefrStartabursttransfertorefreshthelinkfieldofthecurrentdescriptor.
txDescRefrXferDonetxAdvancetxDescReadXferDone&&OWNtxFIFOblockXferDone&&!
OWNtxIdleSetISR:TXIDLE.
txFIFOblockFifoAvailtxFragReadStartabursttransferintotheTxDataFIFOfromfragPtr.
ThelengthwillbetheminimumoftxFifoAvailanddescCnt.
DecrementdescCntaccordingly.
(descCnt==0)&&MOREtxDescWriteStartabursttransfertowritethestatusbacktothedescriptor,clearingtheOWNbit.
(descCnt==0)&&!
MOREtxAdvanceWritethevalueofTXDPtothetxDataFIFOasahandle.
txFragReadXferDonetxFIFOblocktxDescWriteXferDonetxAdvancetxAdvancelink!
=NULLtxDescReadTXDP2.
2TransmitDataFlowIntheDP83815transmitarchitecture,packettransmissioninvolvesthefollowingsteps:1.
Thedevicedriverreceivespacketsfromanupperlayer.
2.
AnavailableDP83815transmitdescriptorisallocated.
ThefragmentinformationiscopiedfromtheNOSspecificdatastructure(s)totheDP83815transmitdescriptor.
3.
Thedriveraddsthisdescriptortoit'sinternallistoftransmitdescriptorsawaitingtransmission.
4.
Iftheinternallistwasempty(thisdescriptorrepresentstheonlyoutstandingtransmitpacket),thenthedrivermustsettheTXDPregistertotheaddressofthisdescriptor,elsethedriverwillappendthisdescriptortotheendofthelist.
5.
ThedriversetstheTXEbitintheCRregistertoinsurethatthetransmitstatemachineisactive.
6.
Ifidle,thetransmitstatemachinereadsthedescriptorintotheTxDescriptorCache.
7.
Thestatemachinethenmovesthroughthefragmentdescribedwithinthedescriptor,fillingtheTxDataFifowithdata.
Thehardwarehandlesallaspectsofbytealignment;noalignmentisassumed.
Fragmentsmaystartand/orendonanybyteaddress.
ThetransmitstatemachineusesthefragmentpointerandtheSIZEfieldfromthecmdstsfieldofthecurrentdescriptortokeeptheTxDataFifofull.
ItalsousestheMOREbitandtheSIZEfieldfromthecmdstsfieldofthecurrentdescriptortoknowwhenpacketboundariesoccur.
8.
Whenapackethascompletedtransmission(successfulorunsuccessful),thestatemachineupdatestheupperhalfofthecmdstsfieldofthecurrentdescriptorinmainmemory,relinquishingownership,andindicatingthepacketcompletionstatus.
Thisupdateisdonebyabusmastertransactionthattransfersonlytheupper2bytestothedescriptorbeingupdated.
Ifmorethanonedescriptorwasusedtodescribethepacket,thencompletionstatusisupdatedonlyinthelastdescriptor.
IntermediatedescriptorsonlyhavetheOWNbitsmodified.
9.
Ifthelinkfieldofthedescriptorisnon-zero,thestatemachineadvancestothenextdescriptorandcontinues.
10.
IfthelinkfieldisNULL,thetransmitstatemachinesuspends,waitingfortheTXEbitintheCRregistertobeset.
IftheTXDPregisteriswrittento,theCTDDflagwillbecleared.
WhentheTXEbitisset,thestatemachinewillexamineCTDD.
IfCTDDisset,thestatemachinewill"refresh"thelinkfieldofthecurrentdescriptor.
Itwillthenfollowthelinkfieldtoanynewdescriptorsthathavebeenaddedtotheendofthelist.
IfCTDDisclear(implyingthatTXDPhasbeenwrittento),thestatemachinewillstartbyreadinginthedescriptorpointedtobyTXDP.
5.
0BufferManagement(Continued)Subjecttochangewithoutnotice.
86RevOwww.
national.
comDP838155.
3ReceiveArchitectureThereceivearchitectureisas"symmetrical"tothetransmitarchitectureaspossible.
Thereceivebuffermanagerprefetchesreceivedescriptorstoprepareforincomingpackets.
WhentheamountofreceivedataintheRxDataFIFOismorethantheRxDrainThreshold,ortheRxDataFIFOcontainsacompletepacket,thenthestatemachinebeginsfillingreceivedbuffersinhostmemory.
Figure5-6ReceiveArchitectureWhentheRXEbitissetto1intheCRregister(regardlessofthecurrentstate),andtheDP83815receivestatemachineisidle,thenDP83815willreadthecontentsofthedescriptorreferencedbyRXDPintotheRxDescriptorCache.
TheRxDescriptorCacheallowstheDP83815toreadanentiredescriptorinasingleburst,andreducesthenumberofbusaccessesrequiredforfragmentinformationto1.
TheDP83815RxDescriptorCacheholdsasinglebufferpointer/countcombination.
5.
3.
1ReceiveStateMachineThereceivestatemachinehasthefollowingstates:Thereceivestatemachinemanipulatesthefollowinginternaldataspaces:Inputstothereceivestatemachineincludethefollowingevents:ReceiveDescriptorListRxDescriptorCacheSoftware/MemoryHardwareRxDataFIFOlinkcmdstsptrptrRxDMAcmdstsRxHeadlinklinkcmdstsptrlinkcmdstsptrrxIdleThereceivestatemachineisidle.
rxDescRefrWaitingforthe"refresh"transferofthelinkfieldofacompleteddescriptorfromthePCIbus.
rxDescReadWaitingforthetransferofadescriptorfromthePCIbusintotheRxDescCache.
rxFifoBlockWaitingfortheamountofdataintheRxDataFifotoreachtheRxDrainThresholdortorepresentacompletepacket.
rxFragWriteWaitingforthetransferofdatafromtheRxDataFIFOviathePCIbustohostmemory.
rxDescWriteWaitingforthecompletionofthewriteofthecmdstsfieldofareceivedescriptor.
RXDPA32-bitregisterthatpointstothecurrentreceivedescriptor.
CRDDAninternalbitflagthatissetwhenthecurrentreceivedescriptorhasbeencompleted,andownershiphasbeenreturnedtothedriver.
ItisclearedwheneverRXDPisloadedwithanewvalue(eitherbythestatemachine,orthedriver).
RxDescCacheAninternaldataspaceequaltothesizeofthemaximumreceivedescriptorsupported.
descCntCountofbytesavailableforstoringreceivedatainallfragmentsdescribedbythecurrentdescriptor.
fragPtrPointertothenextunwrittenbyteinthecurrentfragment.
rxPktCntNumberofpacketsintherxDataFifo.
IncrementedbytheMAC(thefillsideoftheFIFO).
Decrementedbythereceivestatemachineaspacketsareprocessed.
rxPktBytesNumberofbytesinthecurrentpacketbeingdrainedfromtherxDataFifo,thatareinfactcurrentlyintherxDataFifo(Note:packetslargerthanFIFOsize,thisnumberwillneverbegreaterthantheFIFOsize).
CR:RXETheRXEbitintheCommandRegisterhasbeenset.
XferDonecompletionofaPCIbustransferrequest.
FifoReady(rxPktCnt>0)or(rxPktBytes>rxDrainThreshold).
.
.
inotherwords,ifwehaveacompletepacketintheFIFO(regardlessofsize),orthenumberofbytesthatwedohaveisgreaterthantherxDrainThreshold,thenwearereadytobegindrainingtherxDataFifo.
87www.
national.
com5.
0BufferManagement(Continued)DP83815Table5-6ReceiveStateTablesStateEventNextStateActionsrxIdleCR:RXE&&!
CRDDrxDescReadStartabursttransferataddressRXDPandalengthderivedfromRXCFG.
CR:RXE&&CRDDrxDescRefrStartabursttransfertorefreshthelinkfieldofthecurrentdescriptor.
rxDescRefrXferDonerxAdvancerxDescReadXferDone&&!
OWNrxFIFOblockXferDone&&OWNrxIdleSetISR:RXIDLE.
rxFIFOblockFifoReadyrxFragWriteStartabursttransferfromtheRxDataFIFOtohostmemoryatfragPtr.
ThelengthwillbetheminimumofrxPktBytesanddescCnt.
DecrementdescCntaccordingly.
(descCnt==0)&&(rxPktBytes>0)rxDescWriteStartabursttransfertowritethestatusbacktothedescriptor,settingtheOWNbit,andsettingtheMOREbit.
We'llcontinuethepacketinthenextdescriptor.
rxPktBytes==0rxDescWriteStartatransfertowritethecmdstsbacktothedescriptor,settingtheOWNbitandclearingtheMOREbit,andfillinginthefinalreceivestatus(CRC,FAE,SIZE,etc.
).
rxFragWriteXferDonerxFIFOblockrxDescWriteXferDonerxAdvancerxAdvancelink!
=NULLrxDescReadRXDP2ReceiveDataFlowWithabusmasteringarchitecture,somenumberofbuffersanddescriptorsforreceivedpacketsmustbepre-allocatedwhentheDP83815isinitialized.
Thenumberallocatedwilldirectlyaffectthesystem'stolerancetointerruptlatency.
Themorebuffersthatyoupre-allocate,thelongerthesystemwillsurviveanincomingburstwithoutlosingreceivepackets,ifreceivedescriptorprocessingisdelayedorpreempted.
Bufferssizesshouldbeallocatedin32bytemultiples.
1.
Priortopacketreception,receivebuffersmustbedescribedinareceivedescriptorlist(orring,ifpreferred).
Ineachdescriptor,thedriverassignsownershiptothehardwarebyclearingtheOWNbit.
Receivedescriptorsmaydescribeasinglebuffer.
2.
TheaddressofthefirstdescriptorinthislististhenwrittentotheRXDPregister.
Aspacketsarrive,theyareplacedinavailablebuffers.
Asinglepacketmayoccupyoneormorereceivedescriptors,asrequiredbytheapplication.
ThedevicereadsinthefirstdescriptorintotheRxDescCache.
3.
AsdataarrivesintheRxDataFIFO,thereceivebuffermanagementstatemachineplacesthedatainthereceivebufferdescribedbythedescriptor.
Thiscontinuesuntileithertheendofpacketisreached,orthedescriptorbytecountforthisdescriptorisreached.
4.
Ifendofpacketwasreached,thestatusinthedescriptor(inmainmemory)isupdatedbysettingtheOWNbitandclearingtheMOREbit,byupdatingthereceivestatusbitsasindicatedbytheMAC,andbyupdatingtheSIZEfield.
Thestatusbitsincmdstsareonlyvalidinthelastdescriptorofapacket(withtheMOREbitclear).
Alsoforthelastdescriptorofapacket,theSIZEfieldwillbeupdatedtoreflecttheactualamountofdatawrittentothebuffer(whichmaybelessthefullbuffersizeallocatedbythedescriptor).
Ifthereceivebuffermanagementstatemachinerunsoutofdescriptorswhilereceivingapacket,datawillbufferinthereceiveFIFO.
IftheFIFOoverflows,thedriverwillbeinterruptedwithanRxOVRerror.
rxDescRefrrxIdlerxDescReadrxFifoBlockrxDescWriterxAdvancerxFragWriteCR:RXE&&CRDDCR:RXE&&!
CRDDlink=NULLXferDoneXferDoneXferDoneXferDone&&!
OWNXferDone&&OWNlink!
=NULL(descCnt==0)&&(rxPktBytes>0)FifoReadyrxPktBytes==089www.
national.
comDP838156.
0PowerManagementandWake-On-LAN6.
1IntroductionTheDP83815supportsWake-On-LAN(WOL)andthePCIPowerManagementSpecificationversion1.
1.
Thesefeaturesallowthedevicetoenterapowersavingmode,andtosignalthesystemtoreturntoanormaloperatingstatewhenawakeeventoccurs.
ThissectiondescribesthepowermanagementoperationontheDP83815.
6.
2Definitions(forthisdocumentonly)PowerManagement-aPCIspecificationthatdefinespower-savingstatesofPCIdevicesandsystems.
Aspec-compliantdeviceimplementstwoPCIConfigu-rationregisterstocontrolandreportstatusforitsPowerManagementfunction.
Wakeevent-AneventthatcausesaPCIdeviceinPowerManagementmodetosignalthesystem.
PMEEnable(PMEEN)-bit8ofthePowerManage-mentControl/StatusRegister(PMCSR-offset44hinthePCIconfigurationspace).
Settingthisbitto1al-lowsthedevicetoassertthePMENpinwhenitde-tectsawakeevent.
Sleepmode-Adeviceisinsleepmodeifitispro-grammedtoaPowerManagementstateotherthanthefullyoperationalstateandisnotallowedtosignalawakeeventtothesystem.
Inthismode,thePMEEnablebitis0.
Wake-On-LANmode-AdeviceisinWake-On-LAN(WOL)modeifitisprogrammedtoaPowerManage-mentstateotherthanthefullyoperationalstateandisallowedtosignalawakeeventtothesystem.
Inthismode,thePMEEnablebitis1.
PMEN(pin59)-thispinissimilarinfunctiontoasys-teminterrupt(INTANpin).
Whenasserted,itsignalsthesystemthatawakeeventhasoccurred.
PMEStatus-bit15ofPMCSR.
When1,indicatesthedevicedetectedawakeevent.
IfPMEEnableisalsosetto1,thedevicewillassertPMENwheneverPMEStatusis1.
Softwarewritesa1tothisbittoclearit.
MagicPacket:"AspecificpacketofinformationsenttoremotelywakeupasleepingorpoweredoffPConanetwork,itishandledintheLANcontroller.
TheMagicPacketmustcontainaspecificdatase-quencewhichcanbelocatedanywherewithinthepacketbutmustbeprecededbyasynchronizationstream.
Thepacketmustalsomeetthebasicrequire-mentsfortheLANtechnologychosen(e.
g.
ethernetframe).
Thespecificdatasequenceconsistsof16du-plicationsoftheMACaddressofthemachinetobeawakened.
Thesynchronizationstreamisdefinedas6bytesofFFh.
"ACPI-compatibleoperatingsystem-AnoperatingsystemthattakesadvantageofthePCIPowerMan-agementinterface.
TheseincludeWindows98(wheninstalledwithACPI),Windows2000,andWindowsME(wheninstalledwithACPI).
6.
3PacketFilteringWhenthePMEEnablebitissetto1,incomingpacketsarefilteredbasedonsettingsintheReceiveFilterControlRegister(RFCR-offset48hinoperationalregisters)andtheWakeCommand/StatusRegister(WCSR-offset40hinoperationalregisters).
Inotherwords,apacketmustpassbothfilterstobeaccepted.
ThisisadesirablefeatureinWOLmodesinceitpreventsnon-wakepacketsfromfillingthereceiveFIFO.
However,itisnotdesirableinnormaloperatingmodesinceitwillnotallownon-wakepacketsfrombeingreceived.
Therefore,thedrivershouldensurethatthePMEEnablebitissetto0fornormaloperation.
6.
4PowerManagementThePowerManagementSpecificationpresentsalow-levelhardwareinterfacetoPCIdevicesforthepurposeofsavingpower.
TheDP83815supportspowerstatesD0,D1,D2,D3hot,andD3coldasdefinedinthePCIPowerManagementSpecification.
Thesestatesprovideincreasingpowerreductionintheordertheyarelisted.
Table6-1liststhedifferentPowerManagementmodesandthemethodsofpowerreductioninDP83815devices.
Table6-1PowerManagementModesPowerStatePMEEnable(PMEEN)WakeConditionsPowerManagementModePCICLKPhysicalLayerCellD0(SWsetsto0)UnconfiguredNormalOnOnD1Don'tCareDon'tCareWOLOnOnD2Don'tCareDon'tCareWOLMaybeOffOnD3hotOffDon'tCareSleepMaybeOffOffD3hotDon'tCareUnconfiguredSleepMaybeOffOffD3hotOnConfiguredWOLMaybeOffOnD3coldOffDon'tCareSleepOffOffD3coldDon'tCareUnconfiguredSleepOffOffD3coldOnConfiguredWOLOffOn6.
0PowerManagementandWake-On-LAN(Continued)Subjecttochangewithoutnotice.
90RevOwww.
national.
comDP838156.
4.
1D0StateTheD0stateisthenormaloperationalstateofthedevice.
ThePMEEnablebitshouldbesetto0topreventpacketfilteringbasedonthesettingsintheWakeControl/StatusRegister(WCSR).
ItisalsoadvisabletoturnoffallWOLconditionsinWCSRtopreventunnecessaryPMEinterrupts.
6.
4.
2D1StateTheD1stateistheleastpower-savingPowerManagementstate,andmightnotbeusedbytheoperatingsystem.
ThedevicewillonlyrespondtoPCIconfigurationtransactionsandthereforewillnottransmitdata.
TheonlybusactivitythedevicecaninitiateistheassertionofthePMENpin(assumingthePMEEnablebitissetto1);noDMAactivityorinterruptswilloccur.
ThedevicewillcontinuetoreceivepacketsuptothelimitofthereceiveFIFOsize.
UponreturningtotheD0state,thesystemmustre-enableI/Oandmemoryspaceinthedeviceandturnonbusmastercapability.
6.
4.
3D2StateTheD2statehasthesamefeaturesastheD1state,andthesystemmayturnoffthePCIclock,furtherreducingpower.
ThedevicewillcontinuetoreceivepacketsuptothelimitofthereceiveFIFOsize.
LiketheD1state,theD2statemightnotbeusedbytheoperatingsystem.
6.
4.
4D3hotStateTheD3hotstateisoftenknownastheStandbystate.
IfthePMEEnablebitis0,orWOLisunconfigured,thedevicesavespowerbyturningoffthePhysicalLayerCell(PHY).
ThesystemmayturnoffthePCIclock.
InordertoreceivepacketsintheD3hotstate,bothWOLmodeandPMEEnablemustbeturnedon.
LiketheD2andD1states,thedevicewillrespondtoPCIconfigurationtransactionsaslongasthePCIclockisrunning.
WhenthedeviceexitstheD3hotstate,allPCIconfigurationregistersexceptforthePMEEnableandPMEStatusbitsareresettotheirdefaultvalues.
Thismeanstheoperatingsystemmustreinitializethedevice'sPCIconfigurationregisterswithvalidbaseaddresses,etc.
IfPMEEnableorWOLmodewerenotturnedon,thedevicemustbefullyreinitialized.
6.
4.
5D3coldStateTheD3coldstateisthehighestpower-savingstate;itisoftenknownastheHibernatestate.
ThePCIbusisturnedoff,asisthePCIclock.
IfthePMEEnablebitorWOListurnedoff,thePHYisturnedoff.
Thisallowsthedevicetoconsumetheleastamountofpower.
Thedevicemustbefullyreinitializedafterexitingthismode.
6.
5Wake-On-LAN(WOL)ModeWake-On-LANModeisasystem-levelfunctionthatallowsanetworkdevicetoalertthesystemthatawakeeventhasoccurred.
ItworksinconjunctionwiththePCIPowerManagementstatesdetailedintheprevioussection.
TheDP83815supportsseveralwakeeventsincluding,butnotlimitedto,WakeonPHYInterrupt(i.
e.
linkchange),WakeonMagicPacket,andWakeonPatternMatch.
Thesupportedwakeeventsappearinthedevice'sWakeCommand/StatusRegister(WCSR).
6.
5.
1EnteringWOLModeThefollowingstepsarerequiredtoplacetheDP83815intoWOLmode:1.
Disablethereceiverbywritinga1totheReceiverDis-ablebit3(RXD)intheCommandRegister(CR-offset00hinoperationalregisters).
2.
Write0totheReceiveDescriptorPointerRegister(RXDP-offset30hinoperationalregisters)toresetthereceivepointer.
3.
Enablethereceiver(nowin"silentreceive"mode)bywritinga1totheReceiverEnablebit2intheCom-mandRegister(CR:RXE).
4.
ConfiguretheReceiveFilterControlRegister(RFCR)toenablethereceivefilter(RFCR:RFEN-bit31)andacceptthedesiredtypeofwakeuppackets.
NotethattheReceiveFilterEnablebitmustbesetto1forWakeonPHYInterruptaswell.
5.
IfWakeonPHYInterruptisdesired,additionallycon-figureregistersMICR(offsetC4hinoperationalregis-ters)andMISR(offsetC8hinoperationalregisters).
6.
ConfiguretheWakeCommand/StatusRegister(WCSR)withthedesiredtypeofwakeevents.
AnACPI-compatibleoperatingsystemshouldnotifythedriveroftheseevents.
7.
Writea1toPMEEnable,andsetthedesiredPowerStateinPMCSR.
Thesecanbedoneinoneoperation,orPMEEnablecanbewrittenfirst.
AnACPI-compati-bleoperatingsystemshouldhandlethisstep.
8.
IfthePowerManagementstateisD3cold,thesystemwillassertPCIreset,stopthePCIclock,andremovepowerfromthePCIbus.
ThefollowingtwoexamplesshowthecorrespondingregistersettingsforWakeonMagicPacketmodeandWakeonPHYInterruptmoderespectively:EnteringWakeonMagicPacketmode:1.
CR=00000008h(disablethereceiver)2.
RXDP=00000000h(resetthereceivepointer)3.
CR=00000004h(enablethereceiver)4.
RFCR=F0000000h(enablesthereceivefilterandallowsBroadcast,MulticastandUnicastpacketstobereceived-aMagicPacketcouldbeanyofthose.
)5.
WCSR=00000200h(setstheWakeonMagicPacketbit)6.
PMCSR=00008103h(clearsthePMEstatusbit15,setsthePMEEnablebit8andsetsthePowerStatebits[1:0]toD3hot)EnteringWakeonPHYInterruptmode:1.
CR=00000008h(disablethereceiver)2.
RXDP=00000000h(resetthereceivepointer)3.
CR=00000004h(enablethereceiver)4.
RFCR=80000000h(enablesthereceivefilter)5.
MICR=00000002h(setstheInterruptEnablebit1)6.
MISR=00000000h(unmasksthechangeoflinksta-tusevent)7.
WCSR=00000001h(setstheWakeonPHYinterruptbit)8.
PMCSR=00008103h(clearsthePMEstatusbit15,setsthePMEEnablebit8andsetsthePowerStatebits[1:0]toD3hot)6.
0PowerManagementandWake-On-LAN(Continued)Subjecttochangewithoutnotice.
91RevOwww.
national.
comDP838156.
5.
2WakeEventsIfthedevicedetectsawakeeventwhileinWOLmode,itwillassertthePMENpinlowtosignalthesystemthatawakeeventhasoccurred.
ThesystemshouldthenbringthedeviceoutofWOLmodeasdescribedbelow.
6.
5.
3ExitingWOLModeThefollowingstepsarerequiredtobringthedeviceoutofWOLmode(withorwithoutanaccompanyingwakeevent):1.
IfthePowerManagementstateisD3cold,thesystemwillassertPCIreset,restorePCIbuspower,andrestartthePCIclock.
ThiswillalsoreturnthePowerStatetoD0.
ThePCIconfigurationregisters(i.
e.
baseaddresses,busmasterenable,etc.
)mustbereinitial-ized.
2.
Writea0toPowerStatebits[0:1]inthePMCSR(incasetheWOLPowerStatewasnotD3hotorD3cold)andPMEEnable.
Thesecanbedoneinoneopera-tion,orPowerStatecanbewrittenfirst.
TurningoffPMEEnablewillcausethedevicetode-assertthePMENpin,ifitwasasserted.
3.
IftheWOLPowerStatewasD3hotorD3cold,reinitial-izethePCIconfigurationregisters(i.
e.
baseaddresses,busmasterenable,etc.
).
AnACPI-com-patibleoperatingsystemshouldhandlethisstep.
Notethatoperationalregisterswillnotbeaccessibleuntilthisstepiscompleted.
4.
Ifawakeeventoccurred,readtheWCSRtodeter-minewhattheeventwas.
5.
Writea1toPMEStatus.
Thiswillclearanywakeeventinthedevice.
AnACPI-compatibleoperatingsystemwillperformthiswritetothePMCSR;adrivercanperformthiswriteusingtheClockrunControl/Sta-tusRegister(CCSR).
6.
IfthewakeeventwasaPHYinterruptfromaninternalPHY,cleartheeventinthePHYregisters.
RefertotheMISRinSection4.
3.
11.
7.
ClearallbitsinWCSR.
8.
Disablethereceiverbywritinga1totheReceiverDis-ablebitintheCommandRegister(CR:RXD).
9.
ReconfigureRFCRasappropriatefornormalopera-tion.
10.
WriteavalidreceivedescriptorpointertotheReceiveDescriptorPointerRegister(RXDP)11.
Enablethereceiverbywritinga1totheReceiverEnablebitintheCommandRegister(CR:RXE).
Ifthewakeeventwasapacket,thiswillnowbeemptiedfromthereceiveFIFOviaDMA.
6.
6SleepModeSleepModeisasystem-levelfunctionthatallowsadevicetobeplacedinalowerpowermodethanWOLmode.
Insleepmode,thedevicewillnotbeabletodetectwakeeventsorsignalthesystemthatitneedsservice.
6.
6.
1EnteringSleepModeThefollowingstepsarerequiredtoenterSleepMode:1.
Disablethereceiverbywritinga1totheReceiverDis-ablebitintheCommandRegister(CR:RXD).
2.
Write0totheReceiveDescriptorPointerRegister(RXDP)3.
Forcethereceivertorereadthedescriptorpointerbywritinga1totheReceiverEnablebitintheCommandRegister(CR:RXE).
4.
DonotconfigureanywakeeventsinWCSR.
5.
Writea0toPMEEnable,andsetthedesiredPowerStateinPMCSR.
Thesecanbedoneinoneoperation.
AnACPI-compatibleoperatingsystemshouldhandlethisstep.
6.
IfthePowerManagementstateisD3cold,thesystemwillassertPCIreset,stopthePCIclock,andremovepowerfromthePCIbus.
6.
6.
2ExitingSleepModeThefollowingstepsarerequiredtobringtheDP83815outofSleepMode:1.
IfthePowerManagementstateisD3cold,thesystemwillassertPCIreset,restorePCIbuspower,andrestartthePCIclock.
ThiswillalsoreturnthePowerStatetoD0.
ThePCIconfigurationregisters(i.
e.
baseaddresses,busmasterenable,etc.
)mustbereinitial-ized.
2.
Writea0toPowerStatebits[0:1]inthePMCSR(incasethesleepPowerStatewasnotD3hotorD3cold).
3.
IfthesleepPowerStatewasD3hotorD3cold,reinitial-izethePCIconfigurationregisters(i.
e.
baseaddresses,busmasterenable,etc.
).
AnACPI-com-patibleoperatingsystemshouldhandlethisstep.
Notethatoperationalregisterswillnotbeaccessibleuntilthisstepiscompleted.
4.
Disablethereceiverbywritinga1totheReceiverDis-ablebitintheCommandRegister(CR:RXD).
5.
WriteavalidreceivedescriptorpointertotheReceiveDescriptorPointerRegister(RXDP)6.
Enablethereceiverbywritinga1totheReceiverEnablebitintheCommandRegister(CR:RXE).
6.
7PinConfigurationforPowerManagementRefertoTable6-2forproperpinconnectionforpowermanagementconfiguration:Note3:*RefertoDemoBoardschematicsforadditionalinformation.
Table6-2PMPinConfigurationPinNamePinNo.
PowerMgtNoPowerMgtPMEN59*PME#3.
3V3VAUX122*3.
3VauxGNDPWRGOOD1233.
3V3.
3V92www.
national.
comAbsoluteMaximumRatingsSupplyVoltage(VDD)3.
3VPCIsignaling,5.
0Vtolerant-0.
5Vto3.
6VDCInputVoltage(VIN)-0.
5Vto7.
0VDCOutputVoltage(VOUT)-0.
5VtoVDD+0.
5VStorageTemperatureRange(TSTG)-65°Cto150°CPowerDissipation(PD)743mWBodyTemp.
(TB)(Soldering,10sec)220°CESDRating(RZAP=1.
5k,CZAP=120pF)2.
0KVForLQFPPackage:θja(@0cfm,1Watt)44.
5°C/Wθjc(@1Watt)9.
5°C/WRecommendedOperatingConditionsNote:Absolutemaximumratingsarevaluesbeyondwhichoperationisnotrecommendedorguaranteed.
Extendedexposurebeyondtheselimitsmayaffectdevicereliability.
Theyarenotmeanttoimplythatthedeviceshouldbeoperatedattheselimits.
ForLBGAPackage:θja(@0cfm,1Watt)45°C/WSupplyvoltage(VDD)3.
3Volts+0.
3VAmbientTemperature(TA)0to70°CMax.
JunctionTemperature150°CMax.
CaseTemperature95°CDP838157.
0DCandACSpecifications7.
1DCSpecificationsTA=0oCto70oC,VDD=3.
3V±0.
3V,unlessotherwisespecifiedNote1:IDDforWOLStandbyTyp:typicalismeasuredusingawakeenabledD3Hotstate.
IDDforWOLStandbyMax:maximumismeasuredusingawakeenabledD1state.
SymbolParameterConditionsMinTypMaxUnitsVOHMinimumHighLevelOutputVoltageIOH=-6mA2.
4VVOLMaximumLowLevelOutputVoltageIOL=6mA,IOL=4mAforLEDxxx,PMEN/CLKRUNN0.
4VVIHMinimumHighLevelInputVoltageNominalVDD2.
0VVILMaximumLowLevelInputVoltage0.
8VIINInputCurrentVIN=VDDorGND-1010AIOZTRI-STATEOutputLeakageCurrentVOUT=VDDorGND-1010AIDDOperatingSupplyCurrentIOUT=0mA,FREQ=FMAX170225mAWOLstandbySeenote1below.
115200mASleepmode1020mARINdiffDifferentialInputResistanceRD+/1.
1kVTPTD_100100Mb/sTransmitVoltageTD+/0.
9511.
05VVTPTDsym100Mb/sTransmitVoltageSymmetryTD+/±2%VTPTD_1010Mb/sTransmitVoltageTD+/2.
22.
52.
8VCINCMOSInputCapacitance8pFCOUTCMOSOutputCapacitance8pFSDTHon100BASE-TXSignaldetectturn-onthresholdRD+/1000mVdiffpk-pkSDTHoff100BASE-TXSignaldetectturn-offthresholdRD+/200mVdiffpk-pkVTH110BASE-TReceiveThresholdRD+/300585mV7.
0DCandACSpecifications(Continued)93www.
national.
comDP838157.
2ACSpecifications7.
2.
1PCIClockTiming7.
2.
2X1ClockTimingNumberParameterMinMaxUnits7.
2.
1.
1PCICLKLowTime12ns7.
2.
1.
2PCICLKHighTime12ns7.
2.
1.
3PCICLKCycleTime30nsNumberParameterMinMaxUnits7.
2.
2.
1X1LowTime16ns7.
2.
2.
2X1HighTime16ns7.
2.
2.
3X1CycleTime4040nsT2T1T2T3T3T1PCICLK∞T2T1T2T3T3T1X17.
0DCandACSpecifications(Continued)94www.
national.
comDP838157.
2.
3PowerOnReset(PCIActive)Note1:MinimumresetcompletetimeisafunctionofthePCI,transmit,andreceiveclockfrequencies.
Note2:MinimumaccessafterresetisdependentonPCIclockfrequency.
AccessestoDP83815duringthisperiodwillbeignored.
Note3:EEisdisabledfornonpoweronreset.
7.
2.
4NonPowerOnResetNote4:MinimumresetcompletetimeisafunctionofthePCI,transmit,andreceiveclockfrequencies.
NumberParameterMinMaxUnits7.
2.
3.
1RSTNActiveDurationfromPCICLKstable1ms7.
2.
3.
2ResetDisableto1stPCICycleEEEnabledEEDisabled15001ususNumberParameterMinMaxUnits7.
2.
4.
1RSTNtoOutputFloat40nsT21stPCICycleResetCompletePowerStableRSTNPCICLKT11stPCICycleRSTNT1Output7.
0DCandACSpecifications(Continued)95www.
national.
comDP838157.
2.
5PORPCIInactiveNumberParameterMinMaxUnits7.
2.
5.
1VDDstabletoEEaccessVDDindicatesthedigitalsupply(AUXpowerplane,exceptPCIbuspower.
)Guaranteedbydesign.
60us7.
2.
5.
2EEConfigurationloadduration2000us7.
2.
5.
3EECfg.
loadcompletetoRXready:-100Mb-Auto-Negor10Mb600TBDusT3EESELTPRDVDDT2T17.
0DCandACSpecifications(Continued)96www.
national.
comDP838157.
2.
6PCIBusCyclesThefollowingtableparametersapplytoALLthePCIBusCycleTimingDiagramscontainedinthissection.
PCIConfigurationReadNumberParameterMinMaxUnits7.
2.
6.
1InputSetupTime7ns7.
2.
6.
2InputHoldTime0ns7.
2.
6.
3OutputValidDelay211ns7.
2.
6.
4OutputFloatDelay(tofftime)28ns7.
2.
6.
5OutputValidDelayforREQN-pointtopoint212ns7.
2.
6.
6InputSetupTimeforGNTN-pointtopoint10nsPCICLKFRAMENAD[31:0]C/BEN[3:0]IRDYNTRDYNDEVSELNPARPERRNAddrDataIDSELT1T2T1T2T4T1T1T1T2T2T2T3T4T4T4T3T1T2T1T2T3T3T1CmdBET2T3T3T17.
0DCandACSpecifications(Continued)97www.
national.
comDP83815PCIConfigurationWritePCIBusMasterReadPCICLKFRAMENAD[31:0]C/BEN[3:0]IRDYNTRDYNDEVSELNPARPERRNAddrDataIDSELCmdBET1T1T1T1T2T2T1T2T2T2T1T2T3T4T3T4T1T2T4T2T3T1T2PCICLKFRAMENAD[31:0]C/BEN[3:0]IRDYNTRDYNDEVSELNPARPERRNAddrDataT3T3T3T3T3T4CmdBET1T4T2T4T1T1T2T1T2T3T4T1T2T3T3T4T4T3T37.
0DCandACSpecifications(Continued)98www.
national.
comDP83815PCIBusMasterWritePCITargetReadPCICLKFRAMENAD[31:0]C/BEN[3:0]IRDYNTRDYNDEVSELNPARPERRNAddrDataCmdBET3T3T3T3T3T4T4T3T3T3T4T1T2T1T2T3T4T1T2T4T3T4PCICLKFRAMENAD[31:0]C/BEN[3:0]IRDYNTRDYNDEVSELNPARPERRNAddrDataT1T2T1T2T4T1T1T2T2T3T4T4T4T3T1T2T1T2T3T3T1CmdBET2T1T3T3T47.
0DCandACSpecifications(Continued)99www.
national.
comDP83815PCITargetWritePCIBusMasterBurstReadPCICLKFRAMENAD[31:0]C/BEN[3:0]IRDYNTRDYNDEVSELNPARPERRNAddrDataCmdBET1T1T1T2T2T1T2T2T1T2T3T4T3T4T1T2T4T2T3T1PCICLKFRAMENAD[31:0]C/BEN[3:0]IRDYNTRDYNDEVSELNPARPERRNAddrT3T3T3T3T3T4CmdBET1T4T2T4T1T2T1T2T3T4T1T2T3T4T4T3T3DataDataData7.
0DCandACSpecifications(Continued)100www.
national.
comDP83815PCIBusMasterBurstWritePCIBusArbitrationPCICLKFRAMENAD[31:0]C/BEN[3:0]IRDYNTRDYNDEVSELNPARPERRNAddrDataCmdBET3T3T3T3T3T4T4T3T3T3T4T1T2T1T2T3T4T1T2T4T3DataDataPCICLKREQNGNTNT5T6T2T57.
0DCandACSpecifications(Continued)101www.
national.
comDP838157.
2.
7EEPROMAuto-LoadNumberParameterMinMaxUnits7.
2.
7.
1EECLKCycleTime4us7.
2.
7.
2EECLKDelayfromEESELValid1us7.
2.
7.
3EECLKLowtoEESELInvalid2us7.
2.
7.
4EECLKtoEEDOValid2us7.
2.
7.
5EEDISetupTimetoEECLK2us7.
2.
7.
6EEDIHoldTimefromEECLK2usRefertoFM93C46datasheetT1T1T2T5T6T3T4EECLKEESELEEDOEEDI7.
0DCandACSpecifications(Continued)102www.
national.
comDP838157.
2.
8BootPROM/FLASHNote5:T10isguaranteedbydesign.
Note6:Timingsarebasedona30nsPCIclockperiod.
NumberParameterMinTypUnits7.
2.
8.
1DataSetupTimetoMRDNInvalid20ns7.
2.
8.
2AddressSetupTimetoMRDNValid30ns7.
2.
8.
3AddressHoldTimefromMRDNInvalid0ns7.
2.
8.
4AddressInvalidfromMWRNValid180ns7.
2.
8.
5MRDNPulseWidth180ns7.
2.
8.
6DataHoldTimefromMRDNInvalid0ns7.
2.
8.
7DataInvalidfromMWRNInvalid60ns7.
2.
8.
8DataValidtoMWRNValid30ns7.
2.
8.
9AddressSetupTimetoMWRNValid30ns7.
2.
8.
10MRDNInvalidtoMWRNValid150ns7.
2.
8.
11MWRNPulseWidth150ns7.
2.
8.
12Address/MRDNCycleTime210ns7.
2.
8.
13MCSNValidtoMRDNValid30ns7.
2.
8.
14MCSNInvalidtoMRDNInvalid0ns7.
2.
8.
15MCSNValidtoMWRNValid30ns7.
2.
8.
16MWRNInvalidtoMCSNInvalid30ns7.
2.
8.
17MCSNValidtoaddressValid0nsMCSNMRDNMA[15:0]MD[7:0]MWRNT1T3T4T5T6T7T8T9T10T11T12T13T2T15T16T14T177.
0DCandACSpecifications(Continued)103www.
national.
comDP838157.
2.
9100BASE-TXTransmitNote:NormalMismatchisthedifferencebetweenthemaximumandminimumofallriseandfalltimes.
Note:Riseandfalltimestakenat10%and90%ofthe+1or-1amplitude.
Note:CarrierSenseOnDelayisdeterminedbymeasuringthetimefromthefirstbitofthe"J"codegrouptotheassertionofCarrierSense.
Note:1bittime=10nsin100Mb/smode.
Note:TheIdealwindowrecognitionregionis±4ns.
ParameterDescriptionNotesMinTypMaxUnits7.
2.
9.
1100Mb/sTPTD+/RiseandFallTimesseeTestConditionssection346ns100Mb/sRise/FallMismatch500ps7.
2.
9.
2100Mb/sTPTD+/TransmitJitter1.
4nsTPTD+/TPTD+/eyepattern+1RISE+1FALL-1FALL-1RISET2T1T1T1T17.
0DCandACSpecifications(Continued)104www.
national.
comDP838157.
2.
1010BASE-TTransmitEndofPacket7.
2.
1110Mb/sJabberTimingParameterDescriptionNotesMinTypMaxUnits7.
2.
10.
1EndofPacketHighTime(with'0'endingbit)10Mb/s300ns7.
2.
10.
2EndofPacketHighTime(with'1'endingbit)10Mb/s250nsParameterDescriptionNotesMinTypMaxUnits7.
2.
11.
1JabberActivationTime10Mb/s85ms7.
2.
11.
2JabberDeactivationTime10Mb/s500msTPTD+/-TPTD+/-T1T20011TXE(Internal)TPTD+/COL(Internal)T3T27.
0DCandACSpecifications(Continued)105www.
national.
comDP838157.
2.
1210BASE-TNormalLinkPulseNote:Thesespecificationsrepresentbothtransmitandreceivetimings7.
2.
13Auto-NegotiationFastLinkPulse(FLP)Note:ThesespecificationsrepresentbothtransmitandreceivetimingsParameterDescriptionNotesMinTypMaxUnits7.
2.
12.
1PulseWidth100ns7.
2.
12.
2PulsePeriod16msParameterDescriptionNotesMinTypMaxUnits7.
2.
13.
1Clock,DataPulseWidth100ns7.
2.
13.
2ClockPulsetoClockPulsePeriod125s7.
2.
13.
3ClockPulsetoDataPulsePeriodData=162.
5s7.
2.
13.
4BurstWidth2ms7.
2.
13.
5FLPBursttoFLPBurstPeriod16msT2T1clockpulsedatapulseclockpulseFLPBurstFLPBurstFastLinkPulse(s)T2T3T1T4T57.
0DCandACSpecifications(Continued)106www.
national.
comDP838157.
2.
14MediaIndependentInterface(MII)NumberParameterMinMaxUnits7.
2.
14.
1MDCtoMDIOValid0300ns7.
2.
14.
2MDIOtoMDCSetup1010ns7.
2.
14.
3MDIOfromMDCHold10ns7.
2.
14.
4RXDtoRXCLKSetup10ns7.
2.
14.
5RXDfromRXCLKHold10ns7.
2.
14.
6RXDV,RXERtoRXCLKSetup10ns7.
2.
14.
7RXDV,RXERfromRXCLKHold10ns7.
2.
14.
8TXCLKtoTXDValid025ns7.
2.
14.
9TXCLKtoTXENValid025nsMDCMDIO(output)MDIO(input)RXCLKRXD[3:0]RXDV,RXERTXCLKTXD[3:0]TXENT1T2T3T4T6T5T7T8T9107www.
national.
comDP83815PHYSICALDIMENSIONSinches(millimeters)unlessotherwisenotedOrderNumber:DP83815DVNGNSPackageNumber:VNG144ADP8381510/100Mb/sIntegratedPCIEthernetMediaAccessControllerandPhysicalLayer(MacPhyter)Nationaldoesnotassumeanyresponsibilityforuseofanycircuitrydescribed,nocircuitpatentlicensesareimpliedandNationalreservestherightatanytimewithoutnoticetochangesaidcircuitryandspecifications.
Forthemostcurrentproductinformationvisitusatwww.
national.
com.
LIFESUPPORTPOLICYNATIONAL'SPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESORSYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFTHEPRESIDENTANDGENERALCOUNSELOFNATIONALSEMICONDUCTORCORPORATION.
Asusedherein:1.
Lifesupportdevicesorsystemsaredevicesorsystemswhich,(a)areintendedforsurgicalimplantintothebody,or(b)supportorsustainlife,andwhosefailuretoperform,whenproperlyusedinaccordancewithinstructionsforuseprovidedinthelabeling,canbereasonablyexpectedtoresultinasignificantinjurytotheuser.
2.
Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailureofthelifesupportdeviceorsystem,ortoaf-fectitssafetyoreffectiveness.
NationalSemiconductorAmericasCustomerSupportCenterEmail:new.
feedback@nsc.
comTel:1-800-272-9959NationalSemiconductorEuropeCustomerSupportCenterFax:+49(0)180-5308586Email:europe.
support@nsc.
comDeutschTel:+49(0)6995086208EnglishTel:+44(0)8702402171FrancaisTel:+33(0)141918790NationalSemiconductorJapanCustomerSupportCenterFax:81-3-5639-7507Email:jpn.
feedback@nsc.
comTel:81-3-5639-7560www.
national.
comNationalSemiconductorAsiaPacificCustomerSupportCenterEmail:ap.
support@nsc.
comBANNEDSUBSTANCECOMPLIANCENationalSemiconductorcertifiesthattheproductsandpackingmaterialsmeettheprovisionsoftheCustomerProductsStewardshipSpecification(CSP-9-111C2)andtheBannedSubstancesandMaterialsofInterestSpecification(CSP-9-111S2)andcontainno"BannedSubstances"asdefinedinCSP-9-111S2.
LeadfreeproductsareRoHScompliant.
PHYSICALDIMENSIONSinches(millimeters)unlessotherwisenoted(continued)OrderNumber:DP83815DUJBNSPackageNumber:UJB160AIMPORTANTNOTICETexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,modifications,enhancements,improvements,andotherchangestoitsproductsandservicesatanytimeandtodiscontinueanyproductorservicewithoutnotice.
Customersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentandcomplete.
AllproductsaresoldsubjecttoTI'stermsandconditionsofsalesuppliedatthetimeoforderacknowledgment.
TIwarrantsperformanceofitshardwareproductstothespecificationsapplicableatthetimeofsaleinaccordancewithTI'sstandardwarranty.
TestingandotherqualitycontroltechniquesareusedtotheextentTIdeemsnecessarytosupportthiswarranty.
Exceptwheremandatedbygovernmentrequirements,testingofallparametersofeachproductisnotnecessarilyperformed.
TIassumesnoliabilityforapplicationsassistanceorcustomerproductdesign.
CustomersareresponsiblefortheirproductsandapplicationsusingTIcomponents.
Tominimizetherisksassociatedwithcustomerproductsandapplications,customersshouldprovideadequatedesignandoperatingsafeguards.
TIdoesnotwarrantorrepresentthatanylicense,eitherexpressorimplied,isgrantedunderanyTIpatentright,copyright,maskworkright,orotherTIintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservicesareused.
InformationpublishedbyTIregardingthird-partyproductsorservicesdoesnotconstitutealicensefromTItousesuchproductsorservicesorawarrantyorendorsementthereof.
Useofsuchinformationmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI.
ReproductionofTIinformationinTIdatabooksordatasheetsispermissibleonlyifreproductioniswithoutalterationandisaccompaniedbyallassociatedwarranties,conditions,limitations,andnotices.
Reproductionofthisinformationwithalterationisanunfairanddeceptivebusinesspractice.
TIisnotresponsibleorliableforsuchaltereddocumentation.
Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.
ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatproductorservicevoidsallexpressandanyimpliedwarrantiesfortheassociatedTIproductorserviceandisanunfairanddeceptivebusinesspractice.
TIisnotresponsibleorliableforanysuchstatements.
TIproductsarenotauthorizedforuseinsafety-criticalapplications(suchaslifesupport)whereafailureoftheTIproductwouldreasonablybeexpectedtocauseseverepersonalinjuryordeath,unlessofficersofthepartieshaveexecutedanagreementspecificallygoverningsuchuse.
Buyersrepresentthattheyhaveallnecessaryexpertiseinthesafetyandregulatoryramificationsoftheirapplications,andacknowledgeandagreethattheyaresolelyresponsibleforalllegal,regulatoryandsafety-relatedrequirementsconcerningtheirproductsandanyuseofTIproductsinsuchsafety-criticalapplications,notwithstandinganyapplications-relatedinformationorsupportthatmaybeprovidedbyTI.
Further,BuyersmustfullyindemnifyTIanditsrepresentativesagainstanydamagesarisingoutoftheuseofTIproductsinsuchsafety-criticalapplications.
TIproductsareneitherdesignednorintendedforuseinmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsarespecificallydesignatedbyTIasmilitary-gradeor"enhancedplastic.
"OnlyproductsdesignatedbyTIasmilitary-grademeetmilitaryspecifications.
BuyersacknowledgeandagreethatanysuchuseofTIproductswhichTIhasnotdesignatedasmilitary-gradeissolelyattheBuyer'srisk,andthattheyaresolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsinconnectionwithsuchuse.
TIproductsareneitherdesignednorintendedforuseinautomotiveapplicationsorenvironmentsunlessthespecificTIproductsaredesignatedbyTIascompliantwithISO/TS16949requirements.
Buyersacknowledgeandagreethat,iftheyuseanynon-designatedproductsinautomotiveapplications,TIwillnotberesponsibleforanyfailuretomeetsuchrequirements.
FollowingareURLswhereyoucanobtaininformationonotherTexasInstrumentsproductsandapplicationsolutions:ProductsApplicationsAudiowww.
ti.
com/audioCommunicationsandTelecomwww.
ti.
com/communicationsAmplifiersamplifier.
ti.
comComputersandPeripheralswww.
ti.
com/computersDataConvertersdataconverter.
ti.
comConsumerElectronicswww.
ti.
com/consumer-appsDLPProductswww.
dlp.
comEnergyandLightingwww.
ti.
com/energyDSPdsp.
ti.
comIndustrialwww.
ti.
com/industrialClocksandTimerswww.
ti.
com/clocksMedicalwww.
ti.
com/medicalInterfaceinterface.
ti.
comSecuritywww.
ti.
com/securityLogiclogic.
ti.
comSpace,AvionicsandDefensewww.
ti.
com/space-avionics-defensePowerMgmtpower.
ti.
comTransportationandAutomotivewww.
ti.
com/automotiveMicrocontrollersmicrocontroller.
ti.
comVideoandImagingwww.
ti.
com/videoRFIDwww.
ti-rfid.
comOMAPMobileProcessorswww.
ti.
com/omapWirelessConnectivitywww.
ti.
com/wirelessconnectivityTIE2ECommunityHomePagee2e.
ti.
comMailingAddress:TexasInstruments,PostOfficeBox655303,Dallas,Texas75265Copyright2011,TexasInstrumentsIncorporated