response华为p40pro限量套装

40-Channel,16-Bit,SerialInput,VoltageOutputDACAD5370Rev.
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FEATURES40-channelDACina64-leadLFCSPanda64-leadLQFPGuaranteedmonotonicto16bitsMaximumoutputvoltagespanof4*VREF(20V)Nominaloutputvoltagespanof4Vto+8VMultiple,independentoutputspansavailableSystemcalibrationfunctionallowinguser-programmableoffsetandgainChannelgroupingandaddressingfeaturesThermalshutdownfunctionDSP/microcontroller-compatibleserialinterfaceSPIserialinterface2.
5Vto5.
5VdigitalinterfaceDigitalreset(RESET)Clearfunctiontouser-definedSIGGNDxSimultaneousupdateofDACoutputsAPPLICATIONSLevelsettinginautomatictestequipment(ATE)Variableopticalattenuators(VOA)OpticalswitchesIndustrialcontrolsystemsInstrumentationFUNCTIONALBLOCKDIAGRAMAD5370VREF0SIGGND0SIGGND4SIGGND3SIGGND2VOUT0VOUT1VOUT2VOUT3VOUT4VOUT5VOUT6VOUT7VOUT16TOVOUT39LDACDVCCVDDVSSAGNDDGNDX1AREGISTERX1BREGISTERCREGISTERMREGISTERBUFFERGROUP0SYNCSDISCLKSDOBUSYRESETCLRSTATEMACHINEOUTPUTBUFFERANDPOWER-DOWNCONTROLOUTPUTBUFFERANDPOWER-DOWNCONTROLDAC7OFFSETDAC0DAC0BUFFEROFS0REGISTER16161616161616161616168816DAC0REGISTER16DAC7REGISTERMUX2MUX1MUX1MUX1MUX1TOMUX2A/BSELECTREGISTERCONTROLREGISTERX1AREGISTERX1BREGISTERCREGISTERMREGISTER16161616X2AREGISTERX2BREGISTER1616161616MUX2VREF1VOUT8VOUT9VOUT10VOUT11VOUT12VOUT13VOUT14VOUT15X1AREGISTERX1BREGISTERCREGISTERMREGISTERBUFFERGROUP1OUTPUTBUFFERANDPOWER-DOWNCONTROLOUTPUTBUFFERANDPOWER-DOWNCONTROLDAC7OFFSETDAC1DAC0BUFFEROFS1REGISTER16161616161616161616161688DAC0REGISTER16DAC7REGISTERMUX2TOMUX2A/BSELECTREGISTERX1AREGISTERX1BREGISTERCREGISTERMREGISTER1616161616161616MUX2SIGGND1GROUP2TOGROUP4ARETHESAMEASGROUP1X2AREGISTERX2BREGISTER16X2AREGISTERX2BREGISTER16X2AREGISTERX2BREGISTER16SERIALINTERFACE05813-001Figure1.
AD5370Rev.
0|Page2of28TABLEOFCONTENTSFeatures1Applications.
1FunctionalBlockDiagram1RevisionHistory2GeneralDescription.
3Specifications.
4PerformanceSpecifications.
4ACCharacteristics.
5TimingCharacteristics6TimingDiagrams.
6AbsoluteMaximumRatings.
9ESDCaution.
9PinConfigurationsandFunctionDescriptions10TypicalPerformanceCharacteristics12Terminology.
14TheoryofOperation15DACArchitecture.
15ChannelGroups.
15A/BRegistersandGain/OffsetAdjustment.
16LoadDAC.
16OffsetDACChannels16OutputAmplifier.
17TransferFunction.
17ReferenceSelection17Calibration.
18AdditionalCalibration.
18ResetFunction.
19ClearFunction.
19BUSYandLDACFunctions.
19Power-DownMode.
19ThermalShutdownFunction19ToggleMode.
20SerialInterface21SPIWriteMode21SPIReadbackMode21RegisterUpdateRates.
21ChannelAddressingandSpecialModes.
21SpecialFunctionMode.
23PowerSupplyDecoupling.
25PowerSupplySequencing25InterfacingExamples26OutlineDimensions.
27OrderingGuide27REVISIONHISTORY4/08—Revision0:InitialVersionAD5370Rev.
0|Page3of28GENERALDESCRIPTIONTheAD53701containsforty16-bitDACsinasingle64-leadLFCSPanda64-leadLQFP.
Thedeviceprovidesbufferedvoltageoutputswithaspanthatis4*thereferencevoltage.
ThegainandoffsetofeachDACchannelcanbeindependentlytrimmedtoremoveerrors.
Forevengreaterflexibility,thedeviceisdividedintofivegroupsofeightDACs.
ThreeoffsetDACchannelsallowtheoutputrangeofblockstobeadjusted.
Group0canbeadjustedbyOffsetDAC0,Group1canbeadjustedbyOffsetDAC1,andGroup2toGroup4canbeadjustedbyOffsetDAC2.
TheAD5370offersguaranteedoperationoverawidesupplyrange,withVSSfrom16.
5Vto4.
5VandVDDfrom+9Vto+16.
5V.
Theoutputamplifierheadroomrequirementis1.
4Voperatingwithaloadcurrentof1mA.
1ProtectedbyU.
S.
PatentNo.
5,969,657;otherpatentspending.
TheAD5370hasahighspeedserialinterfacethatiscompatiblewithSPI,QSPI,MICROWIRE,andDSPinterfacestandardsandcanhandleclockspeedsofupto50MHz.
TheDACregistersareupdatedonreceiptofnewdata.
AlltheoutputscanbeupdatedsimultaneouslybytakingtheLDACinputlow.
Eachchannelhasaprogrammablegainandanoffsetadjustregistertoallowremovalofgainandoffseterrors.
EachDACoutputisgainedandbufferedonchipwithrespecttoanexternalSIGGNDxinput.
TheDACoutputscanalsobeswitchedtoSIGGNDxviatheCLRpin.
Table1.
HighChannelCountBipolarDACsModelResolutionNominalOutputSpanOutputChannelsLinearityError(LSB)AD536016bits4*VREF(20V)16±4AD536114bits4*VREF(20V)16±1AD536216bits4*VREF(20V)8±4AD536314bits4*VREF(20V)8±1AD537016bits4*VREF(12V)40±4AD537114bits4*VREF(12V)40±1AD537216bits4*VREF(12V)32±4AD537314bits4*VREF(12V)32±1AD537814bits±8.
75V32±3AD537914bits±8.
75V40±3AD5370Rev.
0|Page4of28SPECIFICATIONSPERFORMANCESPECIFICATIONSDVCC=2.
5Vto5.
5V;VDD=9Vto16.
5V;VSS=16.
5Vto8V;VREF=3V;AGND=DGND=SIGGND=0V;CL=opencircuit;RL=opencircuit;gain(M),offset(C),andDACoffsetregistersatdefaultvalues;allspecificationsTMINtoTMAX,unlessotherwisenoted.
Table2.
ParameterMinTypeMaxUnitTestConditions/Comments1ACCURACYResolution16BitsIntegralNonlinearity4+4LSBDifferentialNonlinearity1+1LSBGuaranteedmonotonicbydesignZero-ScaleError10+10mVBeforecalibrationFull-ScaleError10+10mVBeforecalibrationGainError0.
1%FSRZero-ScaleError21LSBAftercalibrationFull-ScaleError21LSBAftercalibrationSpanErrorofOffsetDAC35+35mVSeetheOffsetDACChannelssectionfordetailsVOUTTemperatureCoefficient(VOUT0toVOUT39)5ppmFSR/°CIncludeslinearity,offset,andgaindriftDCCrosstalk2120μVTypically20μV;measuredchannelatmidscale,full-scalechangeonanyotherchannelREFERENCEINPUTS(VREF0,VREF1)2VREFInputCurrent10+10μAPerinput,typically±30nAVREFRange25V±2%forspecifiedoperationSIGGNDINPUT(SIGGND0toSIGGND4)2DCInputImpedance50kΩTypically55kΩInputRange0.
5+0.
5VSIGGNDGain0.
9951.
005OUTPUTCHARACTERISTICS2OutputVoltageRangeVSS+1.
4VDD1.
4VILOAD=1mANominalOutputVoltageRange4+8VShort-CircuitCurrent15mAVOUTxtoDVCC,VDD,orVSSLoadCurrent1+1mACapacitiveLoad2200pFDCOutputImpedance0.
5DIGITALINPUTSInputHighVoltage1.
7VDVCC=2.
5Vto3.
6V2.
0VDVCC=3.
6Vto5.
5VInputLowVoltage0.
8VDVCC=2.
5Vto5.
5VInputCurrent1+1μAExcludingtheCLRpinCLRHighImpedanceLeakageCurrent20+20μAInputCapacitance210pFDIGITALOUTPUTS(SDO,BUSY)OutputLowVoltage0.
5VSinking200μAOutputHighVoltage(SDO)DVCC0.
5VSourcing200μASDOHighImpedanceLeakageCurrent5+5μAHighImpedanceOutputCapacitance210pFAD5370Rev.
0|Page5of28ParameterMinTypeMaxUnitTestConditions/Comments1POWERREQUIREMENTSDVCC2.
55.
5VVDD916.
5VVSS16.
54.
5VPowerSupplySensitivity2FullScale/VDD75dBFullScale/VSS75dBFullScale/DVCC90dBDICC2mADVCC=5.
5V,VIH=DVCC,VIL=GND;normaloperatingconditionsIDD18mAOutputsunloaded,DACoutputs=0V20mAOutputsunloaded,DACoutputs=fullscaleISS18mAOutputsunloaded,DACoutputs=0V20mAOutputsunloaded,DACoutputs=fullscalePowerDissipationUnloaded(P)280mWVSS=8V,VDD=+9.
5V,DVCC=2.
5VPower-DownModeControlregisterpower-downbitsetDICC5μAIDD35μAISS35μAJunctionTemperature3130°CTJ=TA+PTOTAL*θJA1TemperaturerangefortheAD5370is40°Cto+85°C.
Typicalspecificationsareat25°C.
2Guaranteedbydesignandcharacterization,notproductiontested.
3WhereθJArepresentsthepackagethermalimpedance.
ACCHARACTERISTICSDVCC=2.
5V;VDD=15V;VSS=15V;VREF0=VREF1=3V;AGND=DGND=SIGGND=0V;CL=200pF;RL=10kΩ;gain(M),offset(C),andDACoffsetregistersatdefaultvalues;allspecificationsTMINtoTMAX,unlessotherwisenoted.
Table3.
ACCharacteristics1ParameterMinTypMaxUnitTestConditions/CommentsDYNAMICPERFORMANCEOutputVoltageSettlingTime20μsSettlingto1LSBfromafull-scalechange30μsDAClatchcontentsalternatelyloadedwithall0sandall1sSlewRate1V/μsDigital-to-AnalogGlitchEnergy5nV-sGlitchImpulsePeakAmplitude10mVChannel-to-ChannelIsolation100dBVREF0=VREF1=2Vp-p,1kHzDAC-to-DACCrosstalk20nV-sDigitalCrosstalk0.
2nV-sDigitalFeedthrough0.
02nV-sEffectofinputbusactivityonDACoutputundertestOutputNoiseSpectralDensity@10kHz250nV/√HzVREF0=VREF1=0V1Guaranteedbydesignandcharacterization,notproductiontested.
AD5370Rev.
0|Page6of28TIMINGCHARACTERISTICSDVCC=2.
5Vto5.
5V;VDD=9Vto16.
5V;VSS=16.
5Vto4.
5V;VREF=3V;AGND=DGND=SIGGND=0V;CL=200pFtoGND;RL=opencircuit;gain(M),offset(C),andDACoffsetregistersatdefaultvalues;allspecificationsTMINtoTMAX,unlessotherwisenoted.
Table4.
SPIInterfaceLimitatTMIN,TMAXParameter1,2,3MinTypMaxUnitDescriptiont120nsSCLKcycletimet28nsSCLKhightimet38nsSCLKlowtimet411nsSYNCfallingedgetoSCLKfallingedgesetuptimet520nsMinimumSYNChightimet610ns24thSCLKfallingedgetoSYNCrisingedget75nsDatasetuptimet85nsDataholdtimet9442nsSYNCrisingedgetoBUSYfallingedget101.
5μsBUSYpulsewidthlow(single-channelupdate);seeTable8t11600nsSingle-channelupdatecycletimet1220nsSYNCrisingedgetoLDACfallingedget1310nsLDACpulsewidthlowt143μsBUSYrisingedgetoDACoutputresponsetimet150nsBUSYrisingedgetoLDACfallingedget163μsLDACfallingedgetoDACoutputresponsetimet172030μsDACoutputsettlingtimet18140nsCLR/RESETpulseactivationtimet1930nsRESETpulsewidthlowt20400μsRESETtimeindicatedbyBUSYlowt21270nsMinimumSYNChightimeinreadbackmodet22525nsSCLKrisingedgetoSDOvalidt2380nsRESETrisingedgetoBUSYfallingedge1Guaranteedbydesignandcharacterization,notproductiontested.
2AllinputsignalsarespecifiedwithtR=tF=2ns(10%to90%ofDVCC)andtimedfromavoltagelevelof1.
2V.
3SeeFigure4andFigure5.
4ThisismeasuredwiththeloadcircuitshowninFigure2.
5ThisismeasuredwiththeloadcircuitshowninFigure3.
TIMINGDIAGRAMSTOOUTPUTPINCL50pFRL2.
2kVOLDVCC05813-002VOH(MIN)–VOL(MAX)2200AIOL200AIOHTOOUTPUTPINCL50pF05813-003Figure2.
LoadCircuitforBUSYTimingDiagramFigure3.
LoadCircuitforSDOTimingDiagramAD5370Rev.
0|Page7of28SCLKSYNCSDIBUSYVOUTx1VOUTx2VOUTxRESETVOUTxCLR1224t8t12t10t13t17t14t15t13t17t9t7t5t4t2t6DB23DB0t161LDACACTIVEDURINGBUSY.
2LDACACTIVEAFTERBUSY.
BUSYLDAC1LDAC21t3t20t23t18t18t1924t11t105813-004Figure4.
SPIWriteTimingAD5370Rev.
0|Page8of28SDISDO48INPUTWORDSPECIFIESREGISTERTOBEREADNOPCONDITIONSELECTEDREGISTERDATACLOCKEDOUTt22t21LSBFROMPREVIOUSWRITESCLKSYNCDB0DB0DB0DB0DB23DB23DB2305813-005Figure5.
SPIReadTimingAD5370Rev.
0|Page9of28ABSOLUTEMAXIMUMRATINGSTA=25°C,unlessotherwisenoted.
Transientcurrentsofupto60mAdonotcauseSCRlatch-up.
Table5.
ParameterRatingVDDtoAGND0.
3Vto+17VVSStoAGND17Vto+0.
3VDVCCtoDGND0.
3Vto+7VDigitalInputstoDGND0.
3VtoDVCC+0.
3VDigitalOutputstoDGND0.
3VtoDVCC+0.
3VVREF0,VREF1toAGND0.
3Vto+5.
5VVOUT0throughVOUT39toAGNDVSS0.
3VtoVDD+0.
3VSIGGND0throughSIGGND4toAGND1Vto+1VAGNDtoDGND0.
3Vto+0.
3VOperatingTemperatureRange(TA)Industrial(BVersion)40°Cto+85°CStorage65°Cto+150°COperatingJunctionTemperature(TJmax)130°CθJAThermalImpedance64-LeadLFCSP25°C/W64-LeadLQFP45.
5°C/WReflowSolderingPeakTemperature230°CTimeatPeakTemperature10secto40secStressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thisisastressratingonly;functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
ESDCAUTIONAD5370Rev.
0|Page10of28PINCONFIGURATIONSANDFUNCTIONDESCRIPTIONS05813-007PIN1INDICATOR17181920212223242526272829303132VSSVREF1VOUT38VOUT39VOUT8VOUT9VOUT10VOUT11SIGGND1VOUT12VOUT13VOUT14VOUT15VOUT16VOUT17VOUT1864636261605958575655545352515049CLRVOUT26VOUT25VOUT24AGNDDGNDDVCCSDOSDISCLKDVCCDGNDVOUT7VOUT612345678910111213141516RESETBUSYVOUT27SIGGND3VOUT28VOUT29VOUT30VOUT31VOUT32VOUT33VOUT34VOUT35SIGGND4VOUT36VOUT37VDDVOUT5VOUT4SIGGND0VOUT3VOUT2VOUT1VOUT0VREF0VOUT23VOUT22VOUT21VOUT20VSSVDDSIGGND2VOUT1948474645444342414039383736353433AD5370TOPVIEW(NottoScale)LDACSYNC05813-025VSSVREF1VOUT38VOUT39VOUT8VOUT9VOUT10VOUT11SIGGND1VOUT12VOUT13VOUT14VOUT15VOUT16VOUT17VOUT18VOUT5VOUT4SIGGND0VOUT3VOUT2VOUT1VOUT0VREF0VOUT23VOUT22VOUT21VOUT20VSSVDDSIGGND2VOUT19VOUT27SIGGND3VOUT28VOUT29VOUT30VOUT31VOUT32VOUT33VOUT34VOUT35SIGGND4VOUT36VOUT37VDDRESETBUSYVOUT26VOUT25VOUT24AGNDDGNDDVCCSDOSDISCLKDVCCDGNDVOUT7VOUT6CLRLDACSYNC64636261605958575655545352515049474645424344484140393736353433382347651891012131415161117181920212223242526272829303132AD5370TOPVIEW(NottoScale)PIN1INDICATORFigure6.
64-LeadLFCSPPinConfigurationFigure7.
64-LeadLQFPPinConfigurationTable6.
PinFunctionDescriptionsPinNo.
MnemonicDescription1RESETDigitalResetInput.
2BUSYBUSYInput/Output(ActiveLow).
BUSYisopen-drainwhenanoutput.
SeetheBUSYandLDACFunctionssectionformoreinformation.
3,5to12,14,15,19to24,26to33,37to40,42to45,47to50,60to62VOUT0toVOUT39DACOutputs.
Bufferedanalogoutputsforeachofthe40DACchannels.
Eachanalogoutputiscapableofdrivinganoutputloadof10kΩtoground.
Typicaloutputimpedanceoftheseamplifiersis0.
5Ω.
46SIGGND0ReferenceGroundforDAC0toDAC7.
VOUT0toVOUT7arereferencedtothisvoltage.
25SIGGND1ReferenceGroundforDAC8toDAC15.
VOUT8toVOUT15arereferencedtothisvoltage.
34SIGGND2ReferenceGroundforDAC16toDAC23.
VOUT16toVOUT23arereferencedtothisvoltage.
4SIGGND3ReferenceGroundforDAC24andDAC31.
VOUT24toVOUT31arereferencedtothisvoltage.
13SIGGND4ReferenceGroundforDAC32toDAC39.
VOUT32toVOUT39arereferencedtothisvoltage.
41VREF0ReferenceInputforDAC0toDAC7.
ThisreferencevoltageisreferredtoAGND.
18VREF1ReferenceInputforDAC8toDAC39.
ThisreferencevoltageisreferredtoAGND.
AD5370Rev.
0|Page11of28PinNo.
MnemonicDescription16,35VDDPositiveAnalogPowerSupply;+9Vto+16.
5Vforspecifiedperformance.
Thesepinsshouldbedecoupledwith0.
1μFceramiccapacitorsand10μFcapacitors.
17,36VSSNegativeAnalogPowerSupply;16.
5Vto8Vforspecifiedperformance.
Thesepinsshouldbedecoupledwith0.
1μFceramiccapacitorsand10μFcapacitors.
51,58DGNDGroundforAllDigitalCircuitry.
BothDGNDpinsshouldbeconnectedtotheDGNDplane.
52,57DVCCLogicPowerSupply;2.
5Vto5.
5V.
Thesepinsshouldbedecoupledwith0.
1μFceramiccapacitorsand10μFcapacitors.
53SYNCActiveLowInput.
Thisistheframesynchronizationsignalfortheserialinterface.
SeetheTimingCharacteristicssectionformoredetails.
54SCLKSerialClockInput.
DataisclockedintotheshiftregisteronthefallingedgeofSCLK.
Thispinoperatesatclockspeedsupto50MHz.
SeetheTimingCharacteristicssectionformoredetails.
55SDISerialDataInput.
DatamustbevalidonthefallingedgeofSCLK.
SeetheTimingCharacteristicssectionformoredetails.
56SDOSerialDataOutputforSPIInterface.
CMOSoutput.
SDOcanbeusedforreadback.
DataisclockedoutonSDOontherisingedgeofSCLKandisvalidonthefallingedgeofSCLK.
59AGNDGroundforAllAnalogCircuitry.
TheAGNDpinshouldbeconnectedtotheAGNDplane.
63LDACLoadDACLogicInput(ActiveLow).
64CLRAsynchronousClearInput(LevelSensitive,ActiveLow).
SeetheClearFunctionsectionformoreinformation.
ExposedPaddleThelead-freechipscalepackage(LFCSP)hasanexposedpaddleontheunderside.
ThepaddleshouldbeconnectedtoVSS.
AD5370Rev.
0|Page12of28TYPICALPERFORMANCECHARACTERISTICS–2265535DACCODE010–1163843276849152INL(LSB)05813-009Figure8.
TypicalINLPlot76543210NUMBEROFUNITSINL(LSB)VDD=+15VVSS=–15VTA=25°C–0.
6–0.
300.
30.
605813-010Figure9.
TypicalINLDistribution–4–2024INLERROR(LSB)VDD=+15VVSS=–15VDVCC=+5VVREF=+3V806040200TEMPERATURE(°C)05813-011Figure10.
TypicalINLErrorvs.
Temperature–0.
02–0.
010AMPLITUDE(V)02468TIME(s)10TA=25°CVSS=–15VVDD=+15VVREF=+4.
096V05813-012Figure11.
AnalogCrosstalkDuetoLDAC–0.
005000.
0050AMPLITUDE(V)012345TIME(s)–0.
00250.
0025TA=25°CVSS=–15VVDD=+15VVREF=+4.
096V05813-013Figure12.
DigitalCrosstalk–4465535DACCODE020–2163843276849152DNL(LSB)05813-014Figure13.
TypicalDNLPlotAD5370Rev.
0|Page13of280600100400500200OUTPUTNOISE(nV/Hz)012345300FREQUENCY(Hz)05813-015Figure14.
NoiseSpectralDensity0.
250.
300.
350.
400.
450.
50DICC(mA)–40–20020406080TEMPERATURE(°C)VSS=–12VVDD=+12VVREF=+3VDVCC=+5.
5VDVCC=+3.
6VDVCC=+2.
5V05813-016Figure15.
DICCvs.
Temperature12.
012.
513.
013.
514.
0IDD/ISS(|mA|)–40–20020406080TEMPERATURE(°C)VSS=–12VVDD=+12VVREF=+3VISSIDD05813-017Figure16.
IDD/ISSvs.
Temperature14121086420NUMBEROFUNITS14.
0013.
7513.
5013.
2513.
00IDD(mA)VDD=15VVSS=15VTA=25°C05813-018Figure17.
TypicalIDDDistribution14121086420NUMBEROFUNITS0.
500.
450.
400.
350.
30ICC(mA)DVCC=5VTA=25°C05813-019Figure18.
TypicalDICCDistributionAD5370Rev.
0|Page14of28TERMINOLOGYIntegralNonlinearity(INL)Integralnonlinearity,orendpointlinearity,isameasureofthemaximumdeviationfromastraightlinepassingthroughtheendpointsoftheDACtransferfunction.
Itismeasuredafteradjustingforzero-scaleerrorandfull-scaleerrorandisexpressedinleastsignificantbits(LSB).
DifferentialNonlinearity(DNL)Differentialnonlinearityisthedifferencebetweenthemeasuredchangeandtheideal1LSBchangebetweenanytwoadjacentcodes.
Aspecifieddifferentialnonlinearityof1LSBmaximumensuresmonotonicity.
Zero-ScaleErrorZero-scaleerroristheerrorintheDACoutputvoltagewhenall0sareloadedintotheDACregister.
Zero-scaleerrorisameasureofthedifferencebetweenVOUT(actual)andVOUT(ideal),expressedinmillivolts,whenthechannelisatitsminimumvalue.
Zero-scaleerrorismainlyduetooffsetsintheoutputamplifier.
Full-ScaleErrorFull-scaleerroristheerrorinDACoutputvoltagewhenall1sareloadedintotheDACregister.
Full-scaleerrorisameasureofthedifferencebetweenVOUT(actual)andVOUT(ideal),expressedinmillivolts,whenthechannelisatitsmaximumvalue.
Itdoesnotincludezero-scaleerror.
GainErrorGainerroristhedifferencebetweenfull-scaleerrorandzero-scaleerror.
Itisexpressedinmillivolts.
GainError=Full-ScaleErrorZero-ScaleErrorVOUTTemperatureCoefficientThisincludesoutputerrorcontributionsfromlinearity,offset,andgaindrift.
DCOutputImpedanceDCoutputimpedanceistheeffectiveoutputsourceresistance.
Itisdominatedbypackageleadresistance.
DCCrosstalkTheDACoutputsarebufferedbyopampsthatsharecommonVDDandVSSpowersupplies.
Ifthedcloadcurrentchangesinonechannel(duetoanupdate),thiscanresultinafurtherdcchangeinoneormorechanneloutputs.
Thiseffectismoresignificantathighloadcurrentsandreducesastheloadcurrentsarereduced.
Withhighimpedanceloads,theeffectisvirtuallyimmeasurable.
MultipleVDDandVSSterminalsareprovidedtominimizedccrosstalk.
OutputVoltageSettlingTimeTheamountoftimeittakesfortheoutputofaDACtosettletoaspecifiedlevelforafull-scaleinputchange.
Digital-to-AnalogGlitchEnergyTheamountofenergyinjectedintotheanalogoutputatthemajorcodetransition.
ItisspecifiedastheareaoftheglitchinnV-s.
ItismeasuredbytogglingtheDACregisterdatabetween0x1FFFand0x2000.
Channel-to-ChannelIsolationChannel-to-channelisolationreferstotheproportionofinputsignalfromthereferenceinputofoneDACthatappearsattheoutputofanotherDACoperatingfromanotherreference.
Itisexpressedindecibelsandmeasuredatmidscale.
DAC-to-DACCrosstalkDAC-to-DACcrosstalkistheglitchimpulsethatappearsattheoutputofoneconverterduetoboththedigitalchangeandsubsequentanalogoutputchangeatanotherconverter.
ItisspecifiedinnV-s.
DigitalCrosstalkTheglitchimpulsetransferredtotheoutputofoneconverterduetoachangeintheDACregistercodeofanotherconverterisdefinedasthedigitalcrosstalkandisspecifiedinnV-s.
DigitalFeedthroughWhenthedeviceisnotselected,highfrequencylogicactivityonthedigitalinputsofthedevicecanbecapacitivelycoupledbothacrossandthroughthedevicetoappearasnoiseontheVOUTxpins.
Itcanalsobecoupledalongthesupplyandgroundlines.
Thisnoiseisdigitalfeedthrough.
OutputNoiseSpectralDensityOutputnoisespectraldensityisameasureofinternallygener-atedrandomnoise.
Randomnoiseischaracterizedasaspectraldensity(voltageper√Hz).
ItismeasuredbyloadingallDACstomidscaleandmeasuringnoiseattheoutput.
ItismeasuredinnV/√Hz.
AD5370Rev.
0|Page15of28THEORYOFOPERATIONDACARCHITECTURETheAD5370contains40DACchannelsand40outputamplifiersinasinglepackage.
ThearchitectureofasingleDACchannelconsistsofa16-bitresistor-stringDACfollowedbyanoutputbufferamplifier.
Theresistor-stringsectionissimplyastringofresistors,ofequalvalue,fromVREFtoAGND.
ThistypeofarchitectureguaranteesDACmonotonicity.
The16-bitbinarydigitalcodeloadedtotheDACregisterdeterminesatwhichnodeonthestringthevoltageistappedoffbeforebeingfedintotheoutputamplifier.
TheoutputamplifiermultipliestheDACoutputvoltageby4.
Thenominaloutputspanis12Vwitha3Vreferenceand20Vwitha5Vreference.
CHANNELGROUPSThe40DACchannelsoftheAD5370arearrangedintofivegroupsofeightchannels.
TheeightDACsofGroup0derivetheirreferencevoltagefromVREF0.
Group1toGroup4derivetheirreferencevoltagefromVREF1.
Eachgrouphasitsownsignalgroundpin.
Table7.
AD5370RegistersRegisterNameWordLength(Bits)DefaultValueDescriptionX1A160x1555InputDataRegisterA.
OneforeachDACchannel.
X1B160x1555InputDataRegisterB.
OneforeachDACchannel.
M160x3FFFGaintrimregister.
OneforeachDACchannel.
C160x2000Offsettrimregister.
OneforeachDACchannel.
X2A16NotuseraccessibleOutputDataRegisterA.
OneforeachDACchannel.
TheseregistersstorethefinalcalibratedDACdataaftergainandoffsettrimming.
Theyarenotreadableordirectlywritable.
X2B16NotuseraccessibleOutputDataRegisterB.
OneforeachDACchannel.
TheseregistersstorethefinalcalibratedDACdataaftergainandoffsettrimming.
Theyarenotreadableordirectlywritable.
DACNotuseraccessibleDataregistersfromwhichtheDACchannelstaketheirfinalinputdata.
TheDACregistersareupdatedfromtheX2AorX2Bregister.
Theyarenotreadableordirectlywritable.
OFS0140x1555OffsetDAC0dataregister.
SetstheoffsetforGroup0.
OFS1140x1555OffsetDAC1dataregister.
SetstheoffsetforGroup1toGroup4.
Control30x00Bit2=A/B.
0=globalselectionofX1Ainputdataregisters.
1=X1Bregisters.
Bit1=enabletemperatureshutdown.
0=disabletemperatureshutdown.
1=enable.
Bit0=softpower-down.
0=softpower-up.
1=softpower-down.
A/BSelect080x00EachbitinthisregisterdeterminesifaDACchannelinGroup0takesitsdatafromRegisterX2AorX2B.
0=X2A.
1=X2B.
A/BSelect180x00EachbitinthisregisterdeterminesifaDACchannelinGroup1takesitsdatafromRegisterX2AorX2B.
0=X2A.
1=X2B.
A/BSelect280x00EachbitinthisregisterdeterminesifaDACchannelinGroup2takesitsdatafromRegisterX2AorX2B.
0=X2A.
1=X2B.
A/BSelect380x00EachbitinthisregisterdeterminesifaDACchannelinGroup3takesitsdatafromRegisterX2AorX2B.
0=X2A.
1=X2B.
A/BSelect480x00EachbitinthisregisterdeterminesifaDACchannelinGroup4takesitsdatafromRegisterX2AorX2B.
0=X2A.
1=X2B.
AD5370Rev.
0|Page16of28A/BREGISTERSANDGAIN/OFFSETADJUSTMENTEachDACchannelhassevendataregisters.
TheactualDACdata-wordcanbewrittentoeithertheX1AorX1Binputregister,dependingonthesettingoftheA/BbitintheControlregister.
IftheA/Bbitis0,dataiswrittentotheX1Aregister.
IftheA/Bbitis1,dataiswrittentotheX1Bregister.
NotethatthissinglebitisaglobalcontrolandaffectseveryDACchannelinthedevice.
Itisnotpossibletosetupthedeviceonaper-channelbasissothatsomewritesaretoX1AregistersandsomewritesaretoX1Bregisters.
MUXDACDACREGISTERMUXX1AREGISTERX1BREGISTERMREGISTERCREGISTERX2AREGISTERX2BREGISTER05813-020Figure19.
DataRegistersAssociatedwithEachDACChannelEachDACchannelalsohasagain(M)registerandanoffset(C)register,whichallowtrimmingoutofthegainandoffseterrorsoftheentiresignalchain.
DatafromtheX1AregisterisoperatedonbyadigitalmultiplierandanaddercontrolledbythecontentsoftheMandCregisters.
ThecalibratedDACdataisthenstoredintheX2Aregister.
Similarly,datafromtheX1BregisterisoperatedonbythemultiplierandadderandstoredintheX2Bregister.
AlthoughFigure19indicatesamultiplierandanadderforeachchannel,thereisonlyonemultiplierandoneadderinthedevice,andtheyaresharedamongallchannels.
Thishasimplicationsfortheupdatespeedwhenseveralchannelsareupdatedatonce,asdescribedintheRegisterUpdateRatessection.
EachtimedataiswrittentotheX1Aregister,ortotheMorCregisterwiththeA/Bcontrolbitsetto0,theX2Adataisrecal-culatedandtheX2Aregisterisautomaticallyupdated.
Similarly,X2BisupdatedeachtimedataiswrittentoX1BortoMorCwithA/Bsetto1.
TheX2AandX2Bregistersarenotreadableordirectlywritablebytheuser.
DataoutputfromtheX2AandX2BregistersisroutedtothefinalDACregisterbyamultiplexer.
WhethereachindividualDACtakesitsdatafromtheX2AorX2Bregisteriscontrolledbyan8-bitA/BselectregisterassociatedwitheachgroupofeightDACs.
Ifabitinthisregisteris0,theDACtakesitsdatafromtheX2Aregister;if1,theDACtakesitsdatafromtheX2Bregister(Bit0throughBit7controlDAC0toDAC7).
Notethat,becausethereare40bitsinfiveregisters,itispossibletosetup,onaper-channelbasis,whethereachDACtakesitsdatafromtheX2AorX2Bregister.
Aglobalcommandisalsoprovided,whichsetsallbitsintheA/Bselectregistersto0orto1.
LOADDACAllDACchannelsintheAD5370canbeupdatedsimultane-ouslybytakingLDAClowwheneachDACregisterisupdatedfromeitheritsX2AorX2Bregister,dependingonthesettingoftheA/Bselectregisters.
TheDACregisterisnotreadableordirectlywritablebytheuser.
OFFSETDACCHANNELSInadditiontothegainandoffsettrimforeachDACchannel,therearetwo14-bitoffsetDACchannels,oneforGroup0andoneforGroup1toGroup4.
TheseallowtheoutputrangeofallDACchannelsconnectedtothemtobeoffsetwithinadefinedrange.
Thus,subjecttothelimitationsofheadroom,itispossibletosettheoutputrangeofGroup0orGroup1toGroup4tobeunipolarpositive,unipolarnegative,orbipolar,eithersymmetricalorasymmetricalabout0V.
TheDACchannelsintheAD5370arefactorytrimmedwiththeoffsetDACchannelssetattheirdefaultvalues.
Thisresultsinoptimumoffsetandgainperformanceforthedefaultoutputrangeandspan.
WhentheoutputrangeisadjustedbychangingthevalueoftheoffsetDACchannel,anextraoffsetisintroducedduetothegainerroroftheoffsetDACchannel.
TheamountofoffsetisdependentonthemagnitudeofthereferenceandhowmuchtheoffsetDACchanneldeviatesfromitsdefaultvalue.
ThisoffsetisquotedintheSpecificationssection.
Theworst-caseoffsetoccurswhentheoffsetDACchannelisatpositiveornegativefullscale.
ThisvaluecanbeaddedtotheoffsetpresentinthemainDACchanneltogiveanindicationoftheoveralloffsetforthatchannel.
Inmostcases,theoffsetcanberemovedbyprogrammingthechannel'sCregisterwithanappropriatevalue.
TheextraoffsetcausedbytheoffsetDACsonlyneedstobetakenintoaccountwhenanoffsetDACchannelischangedfromitsdefaultvalue.
Figure20showstheallowablecoderangethatcanbeloadedtotheoffsetDACchannel;thisisdependentonthereferencevalueused.
Thus,fora5Vreference,theoffsetDACchannelshouldnotbeprogrammedwithavaluegreaterthan8192(0x2000).
0409681921228816383OFFSETDACCODE01234VREF(V)5RESERVED05813-021Figure20.
OffsetDACCodeRangeAD5370Rev.
0|Page17of28OUTPUTAMPLIFIERTheoutputamplifierscanswingto1.
4Vbelowthepositivesupplyand1.
4Vabovethenegativesupply,whichlimitshowmuchtheoutputcanbeoffsetforagivenreferencevoltage.
Forexample,itisnotpossibletohaveaunipolaroutputrangeof20Vbecausethemaximumsupplyvoltageis±16.
5V.
CLRCLRCLRDACCHANNELOFFSETDACVOUTR610kR220kS3S2S1R460kR320kSIGGNDSIGGNDR560kR120k05813-022Figure21.
OutputAmplifierandOffsetDACFigure21showsdetailsofaDACoutputamplifieranditsconnectionstoitscorrespondingoffsetDAC.
Onpower-up,S1isopen,disconnectingtheamplifierfromtheoutput.
S3isclosed;thus,theoutputispulledtothecorrespondingSIGGND(R1andR2aremuchgreaterthanR6).
S2isalsoclosedtopreventtheoutputamplifierbeingopen-loop.
IfCLRislowatpower-up,theoutputremainsinthisconditionuntilCLRistakenhigh.
TheDACregisterscanbeprogrammed,andtheoutputsassumetheprogrammedvalueswhenCLRistakenhigh.
EvenifCLRishighatpower-up,theoutputremainsinthepreviouslydescribedconditionuntilVDD>6VandVSSMaximumPositiveGainError=+3%=>OutputRangeIncludingGainError=12+0.
03(12)=12.
36VOffsetError=±70mV=>MaximumOffsetErrorSpan=2(70mV)=0.
14V=>OutputRangeIncludingGainErrorandOffsetError=12.
36V+0.
14V=12.
5VVREFCalculationActualOutputRange=12.
5V,thatis,4.
25Vto+8.
25V;VREF=(8.
25V+4.
25V)/4=3.
125VIftheequationyieldsaninconvenientreferencelevel,theusercanadoptoneofthefollowingapproaches:Usearesistordividertodividedownaconvenient,higherreferenceleveltotherequiredlevel.
SelectaconvenientreferencelevelaboveVREF,andmodifythegainandoffsetregisterstodownsizethereferencedigitally.
Inthisway,theusercanusealmostanyconvenientreferencelevelbutmayreducetheperformancebyovercompactionofthetransferfunction.
Useacombinationofthesetwoapproaches.
CALIBRATIONTheusercanperformasystemcalibrationontheAD5370toreducegainandoffseterrorstobelow1LSB.
ThisisachievedbycalculatingnewvaluesfortheMandCregistersandreprogram-mingthem.
ReducingZero-ScaleErrorZero-scaleerrorcanbereducedasfollows:1.
Settheoutputtothelowestpossiblevalue.
2.
Measuretheactualoutputvoltageandcompareitwiththerequiredvalue.
Thisgivesthezero-scaleerror.
3.
CalculatethenumberofLSBsequivalenttotheerrorandaddthisfromthedefaultvalueoftheCregister.
Notethatonlynegativezero-scaleerrorcanbereduced.
ReducingFull-scaleErrorFull-scaleerrorcanbereducedasfollows:1.
Measurethezero-scaleerror.
2.
Settheoutputtothehighestpossiblevalue.
3.
Measuretheactualoutputvoltageandcompareitwiththerequiredvalue.
Addthiserrortothezero-scaleerror.
Thisisthespanerror,whichincludesthefull-scaleerror.
4.
CalculatethenumberofLSBsequivalenttothefull-scaleerrorandsubtractitfromthedefaultvalueoftheMregister.
Notethatonlypositivefull-scaleerrorcanbereduced.
5.
TheMandCregistersshouldnotbeprogrammeduntilbothzero-scaleandfull-scaleerrorshavebeencalculated.
AD5370CalibrationExampleThisexampleassumesthata4Vto+8Voutputisrequired.
TheDACoutputissetto4Vbutmeasuredat4.
03V.
Thisgivesazero-scaleerrorof30mV.
1.
1LSB=12V/65,536=183.
11μV2.
30mV=164LSBThefull-scaleerrorcannowbecalculated.
Theoutputissetto+8Vandavalueof+8.
02Vismeasured.
Thefull-scaleerroris+20mV–(–30mV)=+50mV.
50mV=273LSBsTheerrorscannowberemoved.
1.
164LSBshouldbeaddedtothedefaultCregistervalue,thatis(32,768+164)=32,932.
2.
273LSBshouldbesubtractedfromthedefaultMregistervalue;thatis,(65,535273)=65,262.
3.
65,262shouldbeprogrammedtotheMregisterand32,932shouldbeprogrammedtotheCregister.
ADDITIONALCALIBRATIONThetechniquesdescribedintheprevioussectionareusuallyenoughtoreducethezero-scaleandfull-scaleerrorsinmostapplications.
However,therearelimitationswherebytheerrorsmaynotbesufficientlyremoved.
Forexample,theoffset(C)registercanonlybeusedtoreducetheoffsetcausedbythenegativezero-scaleerror.
Apositiveoffsetcannotbereduced.
Likewise,ifthemaximumvoltageisbelowtheidealvalue,thatis,anegativefull-scaleerror,thegain(M)registercannotbeusedtoincreasethegaintocompensatefortheerror.
Theselimitationscanbeovercomebyincreasingthereferencevalue.
Witha3Vreference,a12Vspanisachieved.
TheidealvoltagerangefortheAD5370is4Vto+8V.
Usinga3.
1Vreferenceincreasestherangeto4.
133Vto+8.
2667V.
Clearly,inthiscase,theoffsetandgainerrorsareinsignificant,andtheMandCregisterscanbeusedtoraisethenegativevoltageto4Vandthenreducethemaximumvoltageto+8Vtogivethemostaccuratevaluespossible.
AD5370Rev.
0|Page19of28RESETFUNCTIONTheresetfunctionisinitiatedbytheRESETpin.
OntherisingedgeofRESET,theAD5370statemachineinitiatesaresetsequencetoresettheX,M,andCregisterstotheirdefaultvalues.
Thissequencetypicallytakes300μs,andtheusershouldnotwritetothepartduringthistime.
Onpower-up,itisrecom-mendedthattheuserbringRESEThighassoonaspossibletoproperlyinitializetheregisters.
Whentheresetsequenceiscomplete(andprovidedthatCLRishigh),theDACoutputisatapotentialspecifiedbythedefaultregistersettings,whichareequivalenttoSIGGNDx.
TheDACoutputsremainatSIGGNDxuntiltheX,M,orCregisterisupdatedandLDACistakenlow.
TheAD5370canbereturnedtothedefaultstatebypulsingRESETlowforatleast30ns.
Notethat,becausetheresetfunctionistriggeredontherisingedge,bringingRESETlowhasnoeffectontheoperationoftheAD5370.
CLEARFUNCTIONCLRisanactivelowinputthatshouldbehighfornormaloperation.
TheCLRpinhasininternal500kΩpull-downresistor.
WhenCLRislow,theinputtoeachoftheDACoutputbufferstages,VOUT0toVOUT39,isswitchedtotheexternallysetpotentialontherelevantSIGGNDpin.
WhileCLRislow,allLDACpulsesareignored.
WhenCLRistakenhighagain,theDACoutputsremaincleareduntilLDACistakenlow.
ThecontentsoftheinputregistersandDACregistersarenotaffectedbytakingCLRlow.
Topreventglitchesfromappearingontheoutputs,CLRshouldbebroughtlowbywritingtotheoffsetDACwhenevertheoutputspanisadjusted.
BUSYANDLDACFUNCTIONSThevalueofanX2(AorB)registeriscalculatedeachtimetheuserwritesnewdatatothecorrespondingX1,C,orMregister.
DuringthecalculationofX2,theBUSYoutputgoeslow.
WhileBUSYislow,theusercancontinuewritingnewdatatotheX1,M,orCregister(seetheRegisterUpdateRatessectionformoredetails),butnoDACoutputupdatescantakeplace.
TheBUSYpinisbidirectionalandhasa50kΩinternalpull-upresistor.
IncaseswheremultipleAD5370devicesareusedinonesystem,theBUSYpinscanbetiedtogether.
ThisisusefulwhenitisrequiredthatnoDACchannelinanydevicebeupdateduntilallotherDACchannelsarereadytobeupdated.
WheneachdevicefinishesupdatingtheX2(AorB)register,itreleasestheBUSYpin.
IfanotherdevicehasnotfinishedupdatingitsX2register,itholdsBUSYlow,thusdelayingtheeffectofLDACgoinglow.
TheDACoutputsareupdatedbytakingtheLDACinputlow.
IfLDACgoeslowwhileBUSYisactive,theLDACeventisstoredandtheDACoutputsupdateimmediatelyafterBUSYgoeshigh.
AusercanalsoholdtheLDACinputpermanentlylow.
Inthiscase,theDACoutputsupdateimmediatelyafterBUSYgoeshigh.
WhenevertheA/Bselectregistersarewrittento,BUSYalsogoeslow,forapproximately600ns.
TheAD5370hasflexibleaddressingthatallowswritingofdatatoasinglechannel,allchannelsinagroup,thesamechannelinGroup0toGroup4orthesamechannelinGroup1toGroup4,orallchannelsinthedevice.
Thismeansthat1,4,5,8,or40DACregistervaluesmayneedtobecalculatedandupdated.
Becausethereisonlyonemultipliersharedamong40channels,thistaskmustbedonesequentiallysothatthelengthoftheBUSYpulsevariesaccordingtothenumberofchannelsbeingupdated.
Table8.
BUSYPulseWidthsActionBUSYPulseWidth1(μsmax)LoadingX1A,X1B,C,orMto1channel21.
5LoadingX1A,X1B,C,orMto4channels3.
3LoadingX1A,X1B,C,orMto5channels3.
9LoadingX1A,X1B,C,orMto8channels5.
7LoadingX1A,X1B,C,orMto40channels24.
91BUSYPulseWidth=((NumberofChannels+1)*600ns)+300ns.
2Asinglechannelupdateistypically1μs.
TheAD5370containsanextrafeaturewherebyaDACregisterisnotupdatedunlessitsX2AorX2BregisterhasbeenwrittentosincethelasttimeLDACwasbroughtlow.
Normally,whenLDACisbroughtlow,theDACregistersarefilledwiththecontentsoftheX2AorX2Bregister,dependingonthesettingoftheA/Bselectregisters.
However,theAD5370updatestheDACregisteronlyiftheX2datahaschanged,therebyremovingunnecessarydigitalcrosstalk.
POWER-DOWNMODETheAD5370canbepowereddownbysettingBit0inthecontrolregisterto1.
ThisturnsofftheDACchannels,thusreducingthecurrentconsumption.
TheDACoutputsareconnectedtotheirrespectiveSIGGNDpotentials.
Thepower-downmodedoesnotchangethecontentsoftheregisters,andtheDACchannelsreturntotheirpreviousvoltagewhenthepower-downbitisclearedto0.
THERMALSHUTDOWNFUNCTIONTheAD5370canbeprogrammedtopowerdowntheDACsifthetemperatureonthedieexceeds130°C.
SettingBit1inthecontrolregisterto1(seetheSpecialFunctionModesection)enablesthisfunction.
Ifthedietemperatureexceeds130°C,theAD5370entersatemperaturepower-downmode,whichisequivalenttosettingthepower-downbitinthecontrolregister.
ToindicatethattheAD5370hasenteredtemperatureshutdownmode,Bit4ofthecontrolregisterissetto1.
TheAD5370remainsintemperatureshutdownmode,evenifthedietemperaturefalls,untilBit1inthecontrolregisterisclearedto0.
AD5370Rev.
0|Page20of28TOGGLEMODETheAD5370hastwoX2registersperchannel,X2AandX2B,thatcanbeusedtoswitchtheDACoutputbetweentwolevelswithease.
Thisapproachgreatlyreducestheoverheadrequiredbyamicroprocessorthatwouldotherwisehavetowritetoeachchannelindividually.
WhentheuserwritestotheX1A,X2A,M,orCregister,thecalculationenginetakesacertainamountoftimetocalculatetheappropriateX2AorX2Bvalue.
IftheapplicationonlyrequiresthattheDACoutputswitchbetweentwolevels,asisthecasewithadatagenerator,anymethodthatreducestheamountofcalculationtimenecessaryisadvantageous.
Forthedatageneratorexample,theuserneedonlysetthehighandlowlevelsforeachchanneloncebywritingtotheX1AandX1Bregisters.
ThevaluesofX2AandX2Barecalculatedandstoredintheirrespectiveregisters.
Thecalculationdelaythereforehappensonlyduringthesetupphase,thatis,whenprogrammingtheinitialvalues.
TotoggleaDACoutputbetweenthetwolevels,itisonlyrequiredtowritetotherelevantA/BselectregistertosettheMUX2registerbit.
Further-more,becausethereareeightMUX2controlbitsperregister,itispossibletoupdateeightchannelswithasinglewrite.
Table15showsthebitsthatcorrespondtoeachDACoutput.
AD5370Rev.
0|Page21of28SERIALINTERFACETheAD5370containsahighspeedSPI-compatibleserialinterfaceoperatingatclockfrequenciesupto50MHz(20MHzforreadoperations).
Tominimizeboththepowerconsumptionofthedeviceandon-chipdigitalnoise,theinterfacepowersupfullyonlywhenthedeviceisbeingwrittento,thatis,onthefallingedgeofSYNC.
Theserialinterfaceis2.
5VLVTTL-compatiblewhenoperatingfroma2.
5Vto3.
6VDVCCsupply.
Itiscon-trolledbyfourpins:SYNC(framesynchronizationinput),SDI(serialdatainputpin),SCLK(clocksdatainandoutofthedevice),andSDO(serialdataoutputpinfordatareadback).
SPIWRITEMODETheAD5370allowswritingofdataviatheserialinterfacetoeveryregisterdirectlyaccessibletotheserialinterface,whichisallregistersexcepttheX2AandX2BregistersandtheDACregisters.
TheX2AandX2BregistersareupdatedwhentheuserwritestotheX1A,X1B,M,orCregister,andtheDACregistersareupdatedbyLDAC.
Theserialword(seeTable10)is24bitslong;16ofthesebitsaredatabits,sixbitsareaddressbits,andtwobitsaremodebitsthatdeterminewhatisdonewiththedata.
Theserialinterfaceworkswithbothacontinuousandaburst(gated)serialclock.
SerialdataappliedtoSDIisclockedintotheAD5370byclockpulsesappliedtoSCLK.
ThefirstfallingedgeofSYNCstartsthewritecycle.
Atleast24fallingclockedgesmustbeappliedtoSCLKtoclockin24bitsofdatabeforeSYNCistakenhighagain.
IfSYNCistakenhighbeforethe24thfallingclockedge,thewriteoperationisaborted.
Ifacontinuousclockisused,SYNCmustbetakenhighbeforethe25thfallingclockedge.
ThisinhibitstheclockwithintheAD5370.
Ifmorethan24fallingclockedgesareappliedbeforeSYNCistakenhighagain,theinputdatabecomescorrupted.
Ifanexternallygatedclockofexactly24pulsesisused,SYNCcanbetakenhighanytimeafterthe24thfallingclockedge.
TheinputregisteraddressedisupdatedontherisingedgeofSYNC.
Foranotherserialtransfertotakeplace,SYNCmustbetakenlowagain.
SPIREADBACKMODETheAD5370allowsdatareadbackviatheserialinterfacefromeveryregisterdirectlyaccessibletotheserialinterface,whichisallregistersexcepttheX2A,X2B,andDACregisters.
Toreadbackaregister,itisfirstnecessarytotelltheAD5370whichregistertoread.
ThisisachievedbywritingawordwhosefirsttwobitsaretheSpecialFunctionCode00tothedevice.
Theremainingbitsthendeterminewhichregisteristobereadback.
Ifareadbackcommandiswrittentoaspecialfunctionregister,datafromtheselectedregisterisclockedoutoftheSDOpinduringthenextSPIoperation.
TheSDOpinisnormallythree-statedbutbecomesdrivenassoonasareadcommandisissued.
Thepinremainsdrivenuntiltheregisterdataisclockedout.
SeeFigure5forthereadtimingdiagram.
Notethat,duetothetimingrequirementsoft5(25ns),themaximumspeedoftheSPIinterfaceduringareadoperationshouldnotexceed20MHz.
REGISTERUPDATERATESThevalueoftheX2AorX2BregisteriscalculatedeachtimetheuserwritesnewdatatothecorrespondingX1,C,orMregister.
Thecalculationisperformedbyathree-stageprocess.
Thefirsttwostagestakeapproximately600nseach,andthethirdstagetakesapproximately300ns.
WhenthewritetotheX1,C,orMregisteriscomplete,thecalculationprocessbegins.
IfthewriteoperationinvolvestheupdateofasingleDACchannel,theuserisfreetowritetoanotherregister,providedthatthewriteoperationdoesnotfinishuntilthefirststagecalculationiscomplete,thatis,600nsaftercompletionofthefirstwriteoperation.
Ifagroupofchannelsisbeingupdatedbyasinglewriteoperation,thefirststagecalculationisrepeatedforeachchannel,taking600nsperchannel.
Inthiscase,theusershouldnotcompletethenextwriteoperationuntilthistimehaselapsed.
CHANNELADDRESSINGANDSPECIALMODESIfthemodebitsarenot00,thedata-wordforD13toD0iswrittentothedevice.
AddressBitA5toAddressBitA0determinewhichchannelsarewrittento,whereasthemodebitsdeterminetheregister(X1A,X1B,C,orM)towhichthedataiswritten,asshowninTable9.
IfdataistobewrittentotheX1AorX1Bregister,thesettingoftheA/Bbitinthecontrolregisterdeterminestheregistertowhichthedataiswritten(thatis,0→X1A,1→X1B).
Table9.
ModeBitsM1M0Action11WritestotheDACinputdata(X)register,dependingonthecontrolregisterA/Bbit10WritestotheDACoffset(C)register01WritestotheDACgain(M)register00Specialfunction,usedincombinationwithotherbitsofthedata-wordTable10.
SerialWordBitAssignmentI23I22I21I20I19I18I17I16I15I14I13I12I11I10I9I8I7I6I5I4I3I2I1I0M1M0A5A4A3A2A1A0D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0AD5370Rev.
0|Page22of28Table11showsthegroupsandchannelsthatareaddressedforeverycombinationofAddressBitA5toAddressBitA0.
Table11.
GroupandChannelAddressingAddressBitA5toAddressBitA3AddressBitA2toAddressBitA0000001010011100101110111000Allgroups,allchannelsGroup0,Channel0Group1,Channel0Group2,Channel0Group3,Channel0Group4,Channel0Group0,Group1,Group2,Group3,Group4;Channel0Group1,Group2,Group3,Group4;Channel0001Group0,allchannelsGroup0,Channel1Group1,Channel1Group2,Channel1Group3,Channel1Group4,Channel1Group0,Group1,Group2,Group3,Group4;Channel1Group1,Group2,Group3,Group4;Channel1010Group1,allchannelsGroup0,Channel2Group1,Channel2Group2,Channel2Group3,Channel2Group4,Channel2Group0,Group1,Group2,Group3,Group4;Channel2Group1,Group2,Group3,Group4;Channel2011Group2,allchannelsGroup0,Channel3Group1,Channel3Group2,Channel3Group3,Channel3Group4,Channel3Group0,Group1,Group2,Group3,Group4;Channel3Group1,Group2,Group3,Group4;Channel3100Group3,allchannelsGroup0,Channel4Group1,Channel4Group2,Channel4Group3,Channel4Group4,Channel4Group0,Group1,Group2,Group3,Group4;Channel4Group1,Group2,Group3,Group4;Channel4101Group4,allchannelsGroup0,Channel5Group1,Channel5Group2,Channel5Group3,Channel5Group4,Channel5Group0,Group1,Group2,Group3,Group4;Channel5Group1,Group2,Group3,Group4;Channel5110ReservedGroup0,Channel6Group1,Channel6Group2,Channel6Group3,Channel6Group4,Channel6Group0,Group1,Group2,Group3,Group4;Channel6Group1,Group2,Group3,Group4;Channel6111ReservedGroup0,Channel7Group1,Channel7Group2,Channel7Group3,Channel7Group4,Channel7Group0,Group1,Group2,Group3,Group4;Channel7Group1,Group2,Group3,Group4;Channel7AD5370Rev.
0|Page23of28SPECIALFUNCTIONMODEIfthemodebitsare00,thespecialfunctionmodeisselected,asshowninTable12.
BitI21toBitI16oftheserialdata-wordselectthespecialfunction,andtheremainingbitsaredatarequiredforexecutionofthespecialfunction,forexample,thechanneladdressfordatareadback.
ThecodesforthespecialfunctionsareshowninTable13.
Table14showstheaddressesfordatareadback.
Table12.
SpecialFunctionModeI23I22I21I20I19I18I17I16I15I14I13I12I11I10I9I8I7I6I5I4I3I2I1I000S5S4S3S2S1S0F15F14F13F12F11F10F9F8F7F6F5F4F3F2F1F0Table13.
SpecialFunctionCodesSpecialFunctionCodeS5S4S3S2S1S0Data(F15toF0)Action0000000000000000000000NOP.
000001XXXXXXXXXXXXX[F2:F0]WritetotheControlregister.
F4=overtemperatureindicator(read-onlybit).
Thisbitshouldbe0whenwritingtotheControlregister.
F3=reserved.
Thisbitshouldbe0whenwritingtotheControlregister.
F2=1:selectregisterX1Bforinput.
F2=0:selectregisterX1Aforinput.
F1=1:enabletemperatureshutdown.
F1=0:disabletemperatureshutdown.
F0=1:softpower-down.
F0=0:softpower-up.
000010XX[F13:F0]WritedatainF13:F0toOFS0register.
000011XX[F13:F0]WritedatainF13:F0toOFS1register.
000100ReservedReserved.
000101SeeTable14Selectregisterforreadback.
000110XXXXXXXX[F7:F0]WritedatainF7:F0toA/BSelectRegister0.
000111XXXXXXXX[F7:F0]WritedatainF7:F0toA/BSelectRegister1.
001000XXXXXXXX[F7:F0]WritedatainF7:F0toA/BSelectRegister2.
001001XXXXXXXX[F7:F0]WritedatainF7:F0toA/BSelectRegister3.
001010XXXXXXXX[F7:F0]WritedatainF7:F0toA/BSelectRegister4.
001011XXXXXXXX[F7:F0]BlockwriteA/Bselectregisters.
F7:F0=0,writeall0s(allchannelsuseX2Aregister).
F7:F0=1,writeall1s(allchannelsuseX2Bregister).
011100ReservedAD5370Rev.
0|Page24of28Table14.
AddressCodesforDataReadback1F15F14F13F12F11F10F9F8F7RegisterRead000X1Aregister001X1Bregister010Cregister011BitF12toBitF7selectthechanneltobereadbackfrom;Channel0=001000toChannel39=101111Mregister100000001Controlregister100000010OFS0dataregister100000011OFS1dataregister100000100Reserved100000110A/BSelectRegister0100000111A/BSelectRegister1100001000A/BSelectRegister2100001001A/BSelectRegister3100001010A/BSelectRegister41F6toF0aredon'tcaresforthedatareadbackfunction.
Table15.
DACChannelsSelectedbyA/BSelectRegistersBits1A/BSelectRegisterF7F6F5F4F3F2F1F00VOUT7VOUT6VOUT5VOUT4VOUT3VOUT2VOUT1VOUT01VOUT15VOUT14VOUT13VOUT12VOUT11VOUT10VOUT9VOUT82VOUT23VOUT22VOUT21VOUT20VOUT19VOUT18VOUT17VOUT163VOUT31VOUT30VOUT29VOUT28VOUT27VOUT26VOUT25VOUT244VOUT39VOUT38VOUT37VOUT36VOUT35VOUT34VOUT33VOUT321Ifthebitis0,RegisterAisselected.
Ifthebitis1,RegisterBisselected.
AD5370Rev.
0|Page25of28POWERSUPPLYDECOUPLINGInanycircuitwhereaccuracyisimportant,carefulconsiderationofthepowersupplyandgroundreturnlayouthelpstoensuretheratedperformance.
TheprintedcircuitboardonwhichtheAD5370ismountedshouldbedesignedsothattheanaloganddigitalsectionsareseparatedandconfinedtocertainareasoftheboard.
IftheAD5370isinasystemwheremultipledevicesrequireanAGND-to-DGNDconnection,theconnectionshouldbemadeatonepointonly.
Thestargroundpointshouldbeestablishedascloseaspossibletothedevice.
Forsupplieswithmultiplepins(VSS,VDD,DVCC),itisrecommendedtotiethesepinstogetherandtodecoupleeachsupplyonce.
TheAD5370shouldhaveamplesupplydecouplingof10μFinparallelwith0.
1μFoneachsupplylocatedasclosetothepackageaspossible,ideallyrightupagainstthedevice.
The10μFcapacitorsarethetantalumbeadtype.
The0.
1μFcapacitorshouldhaveloweffectiveseriesresistance(ESR)andloweffectiveseriesinductance(ESI)—suchasistypicalofthecommonceramictypesthatprovidealowimpedancepathtogroundathighfrequencies—tohandletransientcurrentsduetointernallogicswitching.
Digitallinesrunningunderthedeviceshouldbeavoidedbecausetheycancouplenoiseontothedevice.
TheanaloggroundplaneshouldbeallowedtorunundertheAD5370toavoidnoisecoupling.
ThepowersupplylinesoftheAD5370shoulduseaslargeatraceaspossibletoprovidelowimpedancepathsandreducetheeffectsofglitchesonthepowersupplyline.
Fast-switchingdigitalsignalsshouldbeshieldedwithdigitalgroundtoavoidradiatingnoisetootherpartsoftheboard,andtheyshouldneverberunnearthereferenceinputs.
ItisessentialtominimizenoiseonallVREFlines.
Avoidcrossoverofdigitalandanalogsignals.
Tracesonoppositesidesoftheboardshouldrunatrightanglestoeachother.
Thisreducestheeffectsoffeedthroughthroughtheboard.
Amicrostriptechniqueisbyfarthebestapproach,butitisnotalwayspossiblewithadouble-sidedboard.
Inthistechnique,thecomponentsideoftheboardisdedicatedtogroundplane,andsignaltracesareplacedonthesolderside.
Asisthecaseforallthinpackages,caremustbetakentoavoidflexingthepackageandtoavoidapointloadonthesurfaceofthispackageduringtheassemblyprocess.
POWERSUPPLYSEQUENCINGWhenthesuppliesareconnectedtotheAD5370,itisimportantthattheAGNDandDGNDpinsbeconnectedtotherelevantgroundplanebeforethepositiveornegativesuppliesareapplied.
Inmostapplications,thisisnotanissuebecausethegroundpinsforthepowersuppliesareconnectedtothegroundpinsoftheAD5370viagroundplanes.
WhentheAD5370isusedinahotswapcard,careshouldbetakentoensurethatthegroundpinsareconnectedtothesupplygroundsbeforethepositiveornegativesupplyisconnected.
Thisisrequiredtopreventcurrentsfromflowingindirectionsotherthantowardananalogordigitalground.
AD5370Rev.
0|Page26of28INTERFACINGEXAMPLESTheAnalogDevicesADSP-21065LisafloatingpointDSPwithtwoserialports(SPORTs).
Figure24showshowoneSPORTcanbeusedtocontroltheAD5370.
Inthisexample,thetransmitframesynchronization(TFS)pinisconnectedtothereceiveframesynchronization(RFS)pin.
Thetransmitandreceiveclocks(TCLKandRCLK)arealsoconnectedtogether.
TheusercanwritetotheAD5370bywritingtothetransmitregister.
AreadoperationcanbeaccomplishedbyfirstwritingtotheAD5370totellthepartthatareadoperationisrequired.
AsecondwriteoperationwithanNOPinstructioncausesthedatatobereadfromtheAD5370.
TheDSPreceiveinterruptcanbeusedtoindicatewhenthereadoperationiscomplete.
TheSPIinterfaceoftheAD5370isdesignedtoallowthepartstobeeasilyconnectedtoindustry-standardDSPsandmicrocontrollers.
Figure23showshowtheAD5370canbeconnectedtotheAnalogDevices,Inc.
,BlackfinDSP.
TheBlackfinhasanintegratedSPIportthatcanbeconnecteddirectlytotheSPIpinsoftheAD5370,aswellasprogrammableinput/outputpinsthatcanbeusedtosetorreadthestateofthedigitalinputoroutputpinsassociatedwiththeinterface.
SPISELxADSP-BF531AD5370SCKMOSIMISOPF10PF8PF9PF7SYNCSCLKSDISDORESETCLRLDACBUSY05813-023SYNCSCLKSDISDORESETCLRLDACBUSYAD5370ADSP-21065LTFSxRFSxTCLKxRCLKxDTxADRxAFLAG0FLAG1FLAG2FLAG305813-024Figure23.
InterfacingtoaBlackfinDSPFigure24.
InterfacingtoanADSP-21065LDSPAD5370Rev.
0|Page27of28OUTLINEDIMENSIONSCOMPLIANTTOJEDECSTANDARDSMO-220-VMMD-4051007-C0.
25MINTOPVIEW8.
75BSCSQ9.
00BSCSQ1641617494832330.
500.
400.
300.
50BSC0.
20REF12°MAX0.
80MAX0.
65TYP1.
000.
850.
807.
50REF0.
05MAX0.
02NOM0.
60MAX0.
60MAXEXPOSEDPAD(BOTTOMVIEW)SEATINGPLANEPIN1INDICATOR7.
257.
10SQ6.
95PIN1INDICATOR0.
300.
230.
18Figure25.
64-LeadLeadFrameChipScalePackage[LFCSP_VQ]9mm*9mmBody,VeryThinQuad(CP-64-3)DimensionsshowninmillimetersCOMPLIANTTOJEDECSTANDARDSMS-026-BCD051706-ATOPVIEW(PINSDOWN)1161733324849640.
270.
220.
170.
50BSCLEADPITCH12.
2012.
00SQ11.
80PIN11.
60MAX0.
750.
600.
4510.
2010.
00SQ9.
80VIEWA0.
200.
091.
451.
401.
350.
08COPLANARITYVIEWAROTATED90°CCWSEATINGPLANE0.
150.
057°3.
5°0°Figure26.
64-LeadLowProfileQuadFlatPackage[LQFP](ST-64-2)DimensionsshowninmillimetersORDERINGGUIDEModelTemperatureRangePackageDescriptionPackageOptionAD5370BCPZ40°Cto+85°C164-LeadLeadFrameChipScalePackage(LFCSP_VQ)CP-64-3AD5370BCPZ-REEL740°Cto+85°C64-LeadLeadFrameChipScalePackage(LFCSP_VQ)CP-64-31AD5370BSTZ40°Cto+85°C64-LeadLowProfileQuadFlatPackage(LQFP)ST-64-21AD5370BSTZ-REEL40°Cto+85°C64-LeadLowProfileQuadFlatPackage(LQFP)ST-64-211Z=RoHSCompliantPart.
AD5370Rev.
0|Page28of28NOTES2008AnalogDevices,Inc.
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