Output789rt.com

DS100RT410www.
ti.
comSNLS448–JANUARY2013DS100RT410LowPower10GbEQuadChannelRetimerCheckforSamples:DS100RT4101FEATURES–DS100RT410(EQ+CDR+DE):10.
3125Gbps–DS100DF410(EQ+DFE+CDR+DE):10.
31252Eachchannelindependentlylocksto10.
3125GbpsGbps–DS110RT410(EQ+CDR+DE):8.
5-11.
3GbpsLocktimeoperation(typicallyunder15ms)–DS110DF410(EQ+DFE+CDR+DE):8.
5-11.
3Lowlatency(~300ps)GbpsAdaptiveequalizationupto34dBboostat5–DS125RT410(EQ+CDR+DE):9.
8-12.
5GbpsGHz–DS125DF410(EQ+DFE+CDR+DE):9.
8-12.
5AdjustabletransmitVOD:600to1300mVp-pGbpsAdjustabletransmitde-emphasisto-12dB–DS100BR410(EQ+DE):Upto10.
3125GbpsTypicalPowerDissipation(EQ+CDR+DE):150mW/channelAPPLICATIONSProgrammableoutputpolarityinversionFrontportSFF8431(SFP+)opticalanddirectInputsignaldetection,CDRlockattachcopperdetection/indicatorBackplanereachextension,dataretimerOn-chipEyeMonitor(EOM),PRBSgeneratorEthernet:10GbE,1GbESingle2.
5V±5%powersupplyForotherdataratesanddatatransmissionSMBus/EEPROMconfigurationmodesprotocols,otherpin-compatibledevicesintheOperatingtemperaturerangeof-40to85°Cretimerfamilycanbeused.
RHS48-pin,7mmx7mmpackageEasypincompatibleupgradebetweenrepeaterandretimersDESCRIPTIONTheDS100RT410isafourchannelretimerswithintegratedsignalconditioning.
Eachchannelcanindependentlylockto10.
3125Gbpsdataratetosupport10GbE.
ThedeviceincludesafullyadaptiveContinuous-TimeLinearEqualizer(CTLE),ClockandDataRecovery(CDR)andtransmitDe-Emphasis(DE)drivertoenabledatatransmissionoverlong,lossyandcrosstalk-impairedhighspeedseriallinkstoachieveBERIneitherSMBusmasterorSMBusslavemodetheDS100RT410mustbeassignedanSMBusaddress.
AuniqueaddressmustbeassignedtoeachdeviceontheSMBus.
TheSMBusaddressislatchedintotheDS100RT410onpower-up.
Theaddressisreadinfromthestateofthelines(pins16,21,40,and45respectively)uponpower-up.
IneitherSMBusmodetheseaddresslinesareinputpinsonpower-up.
Copyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
ti.
comTheDS100RT410canbeconfiguredwithanyof16SMBusaddresses.
TheSMBusaddressingschemeusestheleast-significantbitoftheSMBusaddressastheRead/Write_Naddressbit.
WhenanSMBusdeviceisaddressedforwriting,thisbitissetto0;forreading,to1.
Table2belowshowsthewriteaddresssettingfortheDS100RT410versusthevalueslatchedinontheaddresslinesatpower-up.
TheaddressbytesentbytheSMBusmasterovertheSMBusisalways8bitslong.
Theleast-significantbitindicateswhethertheaddressisforawriteoperation,inwhichthemasterwilloutputdatatotheSMBustobereadbytheslave,orareadoperation,inwhichtheslavewilloutputdatatotheSMBustobereadbythemaster.
iftheleast-significantbitisa0,theaddressisforawriteoperation.
Ifitisa1,theaddressisforareadoperation.
Accordingly,SMBusaddressesaresometimesreferredtoasseven-bitaddresses.
ToproducethewriteaddressfortheSMBus,theseven-bitaddressisleft-shiftedbyonebit.
Toproducethereadaddress,itisleftshiftedbyonebitandtheleast-significantbitissetto1.
Table2showstheseven-bitaddressescorrespondingtoeachsetofaddresslinevalues.
WhentheDS100RT410isusedinSMBusslavemode,theREAD_ENpinmustbetiedlow.
Ifitistiedhighorfloating,theDS100RT410willnotlatchinitsaddressfromtheaddresslinesonpower-up.
WhentheREAD_ENpinistiedhighinSMBusslavemodei.
e.
whentheEN_SMBpin(pin20)istiedhigh,theDS100RT410willreverttoanSMBuswriteaddressof0x30.
Thisisatestfeature.
IftherearemultipleDS100RT410sonthesameSMBus,theywillallreverttoanSMBuswriteaddressof0x30,whichcancauseSMBuscollisionsandfailuretoaccesstheDS100RT410sovertheSMBus.
Table2.
DS100RT410SMBusWriteAddressAssignmentADDR_3ADDR_2ADDR_1ADDR_0SMBusWriteSeven-bitSMBusAddressAddress00000x300x1800010x320x1900100x340x1a00110x360x1b01000x380x1c01010x3a0x1d01100x3c0x1e01110x3e0x1f10000x400x2010010x420x2110100x440x2210110x460x2311000x480x2411010x4a0x2511100x4c0x2611110x4e0x27OncetheDS100RT410haslatchedinitsSMBusaddress,itsregisterscanbereadandwrittenusingthetwopinsoftheSMBusinterface,SerialData(SDA)andSerialDataClock(SDC).
SDAandSDCInbothSMBusmasterandSMBusslavemode,theDS100RT410isconfiguredusingtheSMBus.
TheSMBusconsistsoftwolines,theSDAorSerialDataline(pin18)andtheSDCorSerialDataClockline(pin17).
IntheDS100RT410thesepinsare3.
3Vtolerant.
TheSDAandSDClinesarebothopen-drain.
Theyrequireapull-upresistortoasupplyvoltage,whichmaybeeither2.
5Vor3.
3V.
Apull-upresistorinthe2KΩto5KΩrangewillprovidereliableSMBusoperation.
TheSMBusisastandardcommunicationsbusforconfiguringsimplesystems.
ForaspecificationoftheSMBusandescriptionofitsoperation,seehttp://smbus.
org/specs/.
16SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
ti.
comSNLS448–JANUARY2013REGISTERINFORMATIONTherearetwotypesofdeviceregistersintheDS100RT410.
Thesearethecontrol/sharedregistersandthechannelregisters.
Thecontrol/sharedregisterscontrolorallowobservationofsettingswhichaffecttheoperationofallchannelsoftheDS100RT410.
Theyarealsousedtoselectwhichchannelofthedeviceistobethetargetchannelforreadsfromandwritestothechannelregisters.
ThechannelregistersareusedtosetalltheconfigurationsettingsoftheDS100RT410.
TheyprovideindependentcontrolforeachchanneloftheDS100RT410forallthesettabledevicecharacteristics.
Anyregistersnotdescribedinthetablesthatfollowshouldbetreatedasreserved.
Theusershouldnottrytowritenewvaluestotheseregisters.
Theuser-accessibleregistersdescribedinthetablesthatfollowprovideacompletecapabilityforcustomizingtheoperationoftheDS100RT410onachannel-by-channelbasis.
BitFieldsintheRegisterSetManyoftheregistersintheDS100RT410aredividedintobitfields.
Thisallowsasingleregistertoservemultiplepurposes,whichmaybeunrelated.
OftenconfiguringtheDS100RT410requireswritingabitfieldthatmakesuponlypartofaregistervaluewhileleavingtheremainderoftheregistervalueunchanged.
Theprocedureforaccomplishingthisistoreadinthecurrentvalueoftheregistertobewritten,modifyonlythedesiredbitsinthisvalue,andwritethemodifiedvaluebacktotheregister.
Ofcourse,iftheentireregisteristobechanged,ratherthanjustabitfieldwithintheregister,itisnotnecessarytoreadinthecurrentvalueoftheregisterfirst.
Inalltheregisterconfigurationproceduresdescribedinthefollowingsections,thisprocedureshouldbekeptinmind.
Insomecases,theentireregisteristobemodified.
Whenonlyapartoftheregisteristobechanged,however,theproceduredescribedaboveshouldbeused.
WritingtoandReadingfromtheControl/SharedRegistersAnywriteoperationtargetingregister0xffwritestothecontrol/sharedregister0xff.
ThisistheonlyregisterintheDS100RT410withanaddressof0xff.
Bit2ofregister0xffisusedtoselecteitherthecontrol/sharedregistersetorachannelregisterset.
Ifbit2ofregister0xffiscleared(writtenwitha0),thenallsubsequentreadandwriteoperationsovertheSMBusaredirectedtothecontrol/sharedregisterset.
Thissituationpersistsuntilbit2ofregister0xffisset(writtenwitha1).
Thereisaregisterwithaddress0x00inthecontrol/sharedregisterset,andthereisalsoaregisterwithaddress0x00ineachchannelregisterset.
Ifyoureadthevalueinregister0x00whenbit2ofregister0xffisclearedto0,thenthevaluereturnedbytheDS100RT410isthevalueinregister0x00ofthecontrol/sharedregisterset.
Ifyoureadthevalueinregister0x00whenbit2ofregister0xffissetto1,thenthevaluereturnedbytheDS100RT410isthevalueinregister0x00oftheselectedchannelregisterset.
Thechannelregistersetisselectedbybits1:0ofregister0xff.
Ifbit3ofregister0xffissetto1andbit2ofregister0xffisalsosetto1,thenanywriteoperationtoanyregisteraddresswillwriteallthechannelregistersetsintheDS100RT410simultaneously.
Thissituationwillpersistuntileitherbit3ofregister0xfforbit2ofregister0xffiscleared.
Notethatwhenyouwritetoregister0xff,independentofthecurrentsettingsinregister0xff,thewriteoperationALWAYStargetsthecontrol/sharedregister0xff.
Thischannelselectregister,register0xff,isuniqueinthisregard.
Table3belowshowsthecontrol/sharedregisterset.
Anyregisteraddressesorregisterbitsinthecontrol/sharedregistersetnotshowninthistableshouldbeconsideredreserved.
Inthistable,themodeiseitherRforRead-Only,R/WforRead-Write,orR/W/SCforRead-Write-Self-Clearing.
IfyoutrytowritetoaRead-Onlyregister,theDS100RT410willignoreit.
Copyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback17ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
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comTable3.
Control/SharedRegistersAddress(Hex)BitsDefaultValue(Hex)ModeDescription0x007:40x0RSMBusAddressStrapObservation0x017:50x6RDeviceRevision4:00x10RDeviceID0x0460x0R/W/SCSelf-ClearingResetforControl/SharedRegisters50x0R/WResetforSMBusMasterMode40x0R/WForceEEPROMConfiguration0x0570x0R/WDisableMasterModeEEPROMConfiguration4(1)REEPROMReadComplete30x0RSetonChannel0Interrupt20x0RSetonChannel1Interrupt10x0RSetonChannel2Interrupt00x0RSetonChannel3Interrupt0x063:00X0R/WDiagnosticTestControlSetto0xatoreadSMBusstrapvaluesfromregister0x000xff30x0R/WSelectsAllChannelsforRegisterWriteSeeTable420x0R/WEnablesRegisterWritetoOneorAllChannelsandRegisterReadfromOneChannelSeeTable41:00x0R/WSelectsTargetChannelforRegisterReadsandWritesSeeTable4(1)Thereisnodefaultvalue.
ThisbitalwaysindicateswhethertheEEPROMreadiscompleteornot.
SMBusStrapObservationRegister0x00,bits7:4andregister0x06,bits3:0InordertocommunicatewiththeDS100RT410overtheSMBus,itisnecessaryfortheSMBuscontrollertoknowtheaddressoftheDS100RT410.
Theaddressstrapobservationbitsincontrol/sharedregister0x00areprimarilyusefulasatestofSMBusoperation.
ThereisnowaytogettheDS100RT410totellyouwhatitsSMBusaddressisunlessyoualreadyknowwhatitis.
Inordertousetheaddressstrapobservationbitsofcontrol/sharedregister0x00,itisnecessaryfirsttosetthediagnostictestcontrolbitsofcontrol/sharedregister0x06.
Thisfour-bitfieldshouldbewrittenwithavalueof0xa.
Whenthisvalueiswrittentobits3:0ofcontrol/sharedregister0x06,thenthevalueoftheSMBusaddressstrapscanbereadinregister0x00,bits7:4.
ThevaluereadwillbethesameasthevaluepresentontheADDR3:ADDR0lineswhentheDS100RT410waspoweredup.
Forexample,ifavalueof0x1isreadfromcontrol/sharedregister0x00,bits7:4,thenatpower-uptheADDR0linewassetto1andtheotheraddresslines,ADDR3:ADDR1,wereallsetto0.
TheDS100RT410issettoanSMBusWriteaddressof0x32.
18SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
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comSNLS448–JANUARY2013DeviceRevisionandDeviceIDRegister0x01Control/sharedregister0x01containsthedevicerevisionanddeviceID.
ThedevicerevisionshowninTable3isthecurrentrevisionfortheDS100RT410.
ThedeviceIDwillbedifferentforthedifferentdevicesintheretimerfamily.
Thevalueshownin"FortheDS100RT410,Register0x01,bits4:0=0x10"isthecorrectvaluefortheDS100RT410.
Thisregisterisusefulbecauseitcanbeinterrogatedbysoftwaretodeterminethedevicevariantandrevisioninstalledinaparticularsystem.
Thesoftwaremightthenconfigurethedevicewithappropriatesettingsdependinguponthedevicevariantandrevision.
Control/SharedRegisterResetRegister0x04,bit6Register0x04,bit6,clearsallthecontrol/sharedregistersbacktotheirfactorydefaults.
Thisbitisself-clearing,soitisclearedafteritiswrittenandthecontrol/sharedregistersareresettotheirfactorydefaultvalues.
InterruptChannelFlagBitsRegister0x05,bits3:0Register0x05,bits3:0canbeusedtoreadwhichchannelcausedtheINTinterruptsignaltogolow.
Whenoneofthefourbitsissetto1inthisregister,thechannelassociatedwiththebithasfallenoutofCDRlockorbecausetheinputsignalisnolongerdetected.
SMBusMasterModeControlBitsRegister0x04,bits5and4andregister0x05,bits7and4Register0x04,bit5,canbeusedtoresettheSMBusmastermode.
ThisbitshouldnotbesetiftheDS100RT410isinSMBusslavemode.
Thisisanundefinedcondition.
Whenthisbitisset,iftheEN_SMBpinisfloating(meaningthattheDS100RT410isinSMBusmastermode),thentheDS100RT410willreadthecontentsoftheexternalEEPROMwhentheREAD_ENpinispulledlow.
Thisbitisnotself-clearing,soitshouldbeclearedafteritisset.
WhentheDS100RT410EN_SMBpinisfloating(meaningthattheDS100RT410isinSMBusmastermode),itwillreadfromitsexternalEEPROMwhenitsREAD_ENpingoeslow.
AftertheEEPROMreadoperationiscomplete,register0x05,bit4willbeset.
Alternatively,theDS100RT410willreadfromitsexternalEEPROMwhentriggeredbyregister0x04,bit4,asdescribedbelow.
Whenregister0x04,bit4,isset,theDS100RT410readsitsconfigurationfromanexternalEEPROMovertheSMBusimmediately.
Whenthisbitisset,theDS100RT410doesnotwaituntiltheREAD_ENpinispulledlowtoreadfromtheEEPROM.
ThisEEPROMreadoccurswhethertheDS100RT410isinSMBusmastermodeornot.
IfthereadfromtheEEPROMisnotsuccessful,forexamplebecausethereisnoEEPROMpresent,thentheDS100RT410mayhangupandapower-upresetmaybenecessarytoreturnittoproperoperation.
YoushouldonlysetthisbitifyouknowthattheEEPROMispresentandproperlyconfigured.
IftheEEPROMreadhasalreadycompleted,thensettingregister0x04,bit4,willnothaveanyeffect.
TocausetheDS100RT410toreadfromtheEEPROMagainitisnecessarytosetbit5ofregister0x04,resettingtheSMBusmastermode.
IftheDS100RT410isnotinSMBusmastermode,donotsetthisbit.
Aftersettingthisbit,itshouldbeclearedbeforefurtherSMBusoperations.
AfterSMBusmastermodehasbeenreset,theEEPROMreadmaybeinitiatedeitherbypullingtheREAD_ENpinloworbythensettingregister0x04,bit4.
Register0x05,bit7,disablesSMBusmastermode.
ThispreventstheDS100RT410fromtryingtotakecommandoftheSMBustoreadfromtheexternalEEPROM.
ObviouslythisbitwillhavenoeffectiftheEEPROMreadhasalreadytakenplace.
ItalsohasnoeffectifanEEPROMreadiscurrentlyinprogress.
TheonlysituationsinwhichdisablingEEPROMmastermodereadisvalidare(1)whentheDS100RT410isinSMBusmastermode,buttheREAD_ENpinhasnotyetgonelow,and(2)whenregister0x04,bit5,hasbeenusedtoresetSMBusmastermodebuttheEEPROMreadoperationhasnotyetoccurred.
Donotsetthisbitandbit4ofregister0x04simultaneously.
ThisisanundefinedconditionandcancausetheDS100RT410tohangup.
Copyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback19ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
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comChannelSelectRegisterRegister0xff,bits3:0Register0xff,asdescribedabove,selectsthechannelorchannelsforchannelregisterreadsandwrites.
Itisworthdescribingtheoperationofthisregisteragainforclarity.
Ifbit3ofregister0xffisset,thenanychannelregisterwriteappliestoallchannels.
Channelregisterreadoperationsalwaystargetonlythechannelspecifiedinbits1:0ofregister0xffregardlessofthestateofbit3ofregister0xff.
Readandwriteoperationstargetthechannelregistersetsonlywhenbit2ofregister0xffisset.
Bit2ofregister0xffistheuniversalchannelregisterenable.
Thisbitmustbesetinorderforanychannelregisterreadsandwritestooccur.
Ifthisbitisset,thenreadoperationsfromorwriteoperationstoregister0x00,forexample,targetchannelregister0x00fortheselectedchannelratherthanthecontrol/sharedregister0x00.
Inordertoaccessthecontrol/sharedregistersagain,bit2ofregister0xffshouldbecleared.
Thenthecontrol/sharedregisterscanagainbeaccessedusingtheSMBus.
Writeoperationstoregister0xffalwaystargettheregisterwithaddress0xffinthecontrol/sharedregisterset.
Thereisnootherregister,andspecifically,nochannelregister,withaddress0xff.
Thecontentsofthechannelselectregister,register0xff,cannotbereadbackovertheSMBus.
Readoperationsonthisregisterwillalwaysyieldaninvalidresult.
Alleightbitsofthisregistershouldalwaysbesettothedesiredvalueswheneverthisregisteriswritten.
Alwayswrite0x0tothefourMSBsofregister0xff.
TheregistersettargetselectedbyeachvalidvaluewrittentothechannelselectregisterisshowninTable4Table4.
ChannelSelectRegisterValuesMappedtoRegisterSetTargetRegister0xffValue(hex)Shared/ChannelBroadcastChannelTargetedChannelCommentsRegisterSelectionRegisterSelectionSelection0x00SharedN/AN/AAllreadsandwritestargetsharedregisterset0x04ChannelNo0Allreadsandwritestargetchannel0registerset0x05ChannelNo1Allreadsandwritestargetchannel1registerset0x06ChannelNo2Allreadsandwritestargetchannel2registerset0x07ChannelNo3Allreadsandwritestargetchannel3registerset0x0cChannelYes0Allwritestargetallchannelregistersets,allreadstargetchannel0registerset0x0dChannelYes1Allwritestargetallchannelregistersets,allreadstargetchannel1registerset0x0eChannelYes2Allwritestargetallchannelregistersets,allreadstargetchannel2registerset0x0fChannelYes3Allwritestargetallchannelregistersets,allreadstargetchannel3registersetReadingtoandWritingfromtheChannelRegistersEachofthefourchannelshasacompletesetofchannelregistersassociatedwithit.
Thechannelregistersorthecontrol/sharedregistersareselectedbychannelselectregister0xff.
Thesettingsinthisregistercontrolthetargetforsubsequentregisterreadsandwritesuntilthecontentsofregister0xffareexplicitlychangedbyaregisterwritetoregister0xff.
Asnoted,thereisonlyoneregisterwithanaddressof0xff,thechannelselectregister.
20SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
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comSNLS448–JANUARY2013Table5.
ChannelRegistersAddress(Hex)BitsDefaultValue(Hex)ModeFieldNameDescription0x0020x0R/W/SCrst_regsResetChannelRegisterstoDefaults(Self-clearing)0x0140x0Rcdr_lock_loss_intCDRLockLossInterrupt00x0Rsignal_detect_loss_intSignalDetectLossInterrupt0x037:60x0R/Weq_BST0[1:0]CTLEBoostStage05:40x0R/Weq_BST1[1:0]CTLEBoostStage13:20x0R/Weq_BST2[1:0]CTLEBoostStage21:00x0R/Weq_BST3[1:0]CTLEBoostStage30x084:00x00R/Wcdr_cap_dac_start[4:OverrideStarting0]VCOCapDACSetting00x0970x0R/Wreg_divsel_vco_cap_EnableOverrideVCO0vCapDAC(Registers0x08and0x0b)50x0R/Wreg_bypass_pfd_ovEnableOverrideOutputMux(Register0x1e)20x0R/Wreg_divsel_ovEnableOverrideDividerSelect(Register0x18)0x0a30x0R/Wreg_cdr_reset_ovEnableCDRResetOverride(Register0x0a)20x0R/Wreg_cdr_reset_smCDRResetOverrideBit0x0b4:00x0fR/Wcdr_cap_dac_start1[4OverrideVCOCap:0]DACSetting10x0d50x0R/WPRBS_PATT_SHIFT_PRBSGeneratorENClockEnable0x117:60x0R/Weom_sel_vrange[1:0]EyeOpeningMonitorVoltageRange50x1R/Weom_PDEyeOpeningMonitorPowerDown0x1320x0RWeq_BST3[2]CTLEBoostStage3,Bit2(LimitingBit)0x1470x0R/Weq_sd_presetForceSignalDetectOn60x0R/Weq_sd_resetForceSignalDetectOff0x1560x0R/Wdrv_dem_rangeDriverDe-emphasisRange2:00x0R/Wdrv_dem[2:0]DriverDe-emphasisSetting0x186:40x4R/Wpdiq_sel_div[2:0]VCODividerRatio(EnablefromRegister0x09,Bit2)20x0R/Wdrv_sel_slowEnableSlowRise/FallTimeonOutputDriverCopyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback21ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
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comTable5.
ChannelRegisters(continued)Address(Hex)BitsDefaultValue(Hex)ModeFieldNameDescription0x1e7:50x7R/Wpfd_sel_data_mux[2:0OutputMux](EnablefromRegister0x09,Bit5)40x0R/Wprbs_enEnablePRBSGenerator0x1f70x0R/Wdrv_sel_invSelectOutputPolarityInverted0x2470x0R/Wfast_eomEnableFastEyeOpeningMonitorMode00x0R/W/SCeom_startStartEyeOpeningMonitorCounter(Self-Clearing)0x257:00x0Reom_count[15:8]EyeOpeningMonitorCount0x267:00x0Reom_count[7:0]EyeOpeningMonitorCount0x277:00x0Rheo[7:0]HEOValue0x287:00x0Rveo[7:0]VEOValue0x296:50x0Reom_vrange_setting[EyeOpeningMonitor1:0]VoltageRangeSetting0x2a7:00x30R/Weom_timer_thr[7:0]EyeOpeningMonitorTimerThreshold0x2d2:00x0R/Wdrv_sel_vod[2:0]DriverVOD0x2f7:60x0R/WRATE[1:0]Rate5:40x0R/WSUBRATE[1:0]Subrate30x0R/Windex_ovCTLEAdaptationIndexOverride(Register0x13)20x1R/Wen_ppm_checkEnableFrequencyCounterforLockDetect10x1R/Wen_fld_checkFalseLockDetectorforlockdetectisdisabledbydefault.
Mustsetbitto0toenabletheFLD.
00x0R/Wctle_adaptStartCTLEAdaptation0x3040x0Rheo_veo_interruptGoesHighifInterruptfromCDRGoesHigh30x0R/Wprbs_en_dig_clkPRBSGeneratorEnable1:00x0R/Wprbs_pattern_sel[1:0]PRBSGeneratorPatternSelect0x316:50x1R/Wadapt_mode[1:0]AdaptationMode4:30x0R/Weq_sm_fom[1:0]CTLEAdaptationFigureofMeritType0x327:40x1R/Wheo_int_thresh[3:0]HEOInterruptThreshold3:00x1R/Wveo_int_thresh[3:0]VEOInterruptThreshold22SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
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comSNLS448–JANUARY2013Table5.
ChannelRegisters(continued)Address(Hex)BitsDefaultValue(Hex)ModeFieldNameDescription0x337:40x8R/Wheo_thresh[3:0]HEOThresholdforCTLEAdaptationHandoff3:00x8R/Wveo_thresh[3:0]VEOThresholdforCTLEAdaptationHandoff0x3660x0R/Wheo_veo_int_enableEnableHEO/VEOInterrupt5:40x3R/Wref_mode[1:0]ReferenceClockMode20x0R/Wmr_cdr_cap_dac_rngEnableOverridefor_ovVCOCapDACRange1:00x1R/Wmr_cdr_cap_dac_rng[CapDACRange1:0]0x394:00x0R/Wstart_index[4:0]StartIndexforCTLEAdaptation(EnablefromRegister0x2f,Bit3)0x3a7:60x2R/Wfixed_eq_BST0[1:0]FixedCTLEStage0BoostSettingforLowerDataRates5:40x2R/Wfixed_eq_BST1[1:0]FixedCTLEStage1BoostSettingforLowerDataRates3:20x1R/Wfixed_eq_BST2[1:0]FixedCTLEStage2BoostSettingforLowerDataRates1:00x1R/Wfixed_eq_BST3[1:0]FixedCTLEStage3BoostSettingforLowerDataRates0x3e70x1R/WHEO_VEO_LOCKMOEnableHEO/VEON_ENLockMonitoring0x40–0x5fCTLESettingsforAdaptation–seeTable60x6a7:40x4R/Wveo_lck_thrsh[3:0]VerticalEyeOpeningLockThreshold3:00x4R/Wheo_lck_thrsh[3:0]HorizontalEyeOpeningLockThreshold0x6b7:00x0R/Wfom_a[7:0]AdaptationFigureofMeritTerma0x6c7:00x0R/Wfom_b[7:0]AdaptationFigureofMeritTermb0x6d7:00x0R/Wfom_c[7:0]AdaptationFigureofMeritTermc0x6e70x0R/Wen_new_fom_ctleEnableAlternateFigureofMeritforCTLEAdaptation0x702:00x3R/Weq_lb_cnt[2:0]CTLEAdaptationLook-BeyondCountCopyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
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comResettingIndividualChannelsoftheRetimerRegister0x00,bit2,andregister0x0a,bits3:2Bit2ofchannelregister0x00areusedtoresetalltheregistersforthecorrespondingchanneltotheirfactorydefaultsettings.
Thisbitisself-clearing.
WritingthisbitwillclearanyregisterchangesyouhavemadeintheDS100RT410sinceitwaspowered-up.
ToresetjusttheCDRstatemachinewithoutresettingtheregistervalues,whichwillre-initiatethelockandadaptationsequenceforaparticularchannel,usechannelregister0x0a.
Setbit3ofthisregistertoenabletheresetoverride,thensetbit2toforcetheCDRstatemachineintoreset.
Thesebitscanbesetinthesameoperation.
Whenbit2issubsequentlycleared,theCDRstatemachinewillresumenormaloperation.
Ifasignalispresentattheinputtotheselectedchannel,theDS100RT410willattempttolocktoitandwilladaptitsCTLE.
InterruptStatusControl/SharedRegister0x05,bits3:0,Register0x01,bits4and0,Register0x30,bit4,Register0x32,andRegister0x36,bit6EachchanneloftheDS100RT410willgenerateaninterruptunderseveraldifferentconditions.
TheDS100RT410willalwaysgenerateaninterruptwhenitlosesCDRlockorwhenasignalisnolongerdetectedatitsinput.
IftheHEO/VEOinterruptisenabledbysettingbit6ofregister0x36,thentheretimerwillgenerateaninterruptwhenthehorizontalorverticaleyeopeningfallsbelowthepresetvalueseveniftheretimerremainslocked.
Whenoneoftheseinterruptconditionsoccurs,theretimeralertsthesystemcontrollerviahardwareandprovidesadditionaldetailsviaregisterreadsovertheSMBus.
First,theopen-draininterruptlineINTispulledlow.
Thisindicatesthatoneormoreofthechannelsoftheretimerhasgeneratedaninterrupt.
Theinterruptlinesfrommultipleretimerscanbewire-ANDedtogethersothatifanyretimergeneratesaninterruptthesystemcontrollercanbenotifiedusingasingleinterruptinput.
iftheinterrupthasoccurredbecausethehorizontalorverticaleyeopeninghasdroppedbelowthepre-setthreshold,whichissetinchannelregister0x32,thenbit4ofregister0x30willgohigh.
ThisindicatesthatthesourceoftheinterruptwastheHEOorVEO.
IftheinterrupthasoccurredbecausetheCDRhasfallenoutoflock,orbecausethesignalisnolongerdetectedattheinput,thenbit4and/orbit0ofregister0x01willgohigh,indicatingthecauseoftheinterrupt.
Ineithercase,thecontrol/sharedregistersetwillindicatewhichchannelcausedtheinterrupt.
Thisisreadfrombits3:0ofcontrol/sharedregister0x05.
Whenaninterruptisdetectedbythecontrollerontheinterruptinput,thecontrollershouldtakethefollowingstepstodeterminethecauseoftheinterruptandclearit.
1.
ThecontrollerdetectstheinterruptbydetectingthattheINTlinehasbeenpulledlowbyoneoftheretimerstowhichitisconnected.
2.
Thecontrollerreadscontrol/sharedregister0x05fromalltheDS100RT410sconnectedtotheINTline.
Foratleastoneofthesedevices,atleastoneofthebits3:0willbesetinthisregister.
3.
Foreachdevicewithabitsetinbits3:0ofcontrol/sharedregister0x05,thecontrollerdetermineswhichchannelorchannelsproducedaninterrupt.
RefertoTable3foramappingofthebitsinthisbitfieldtothechannelproducingtheinterrupt.
4.
Whenthecontrollerdetectsthatoneoftheretimershasa1inoneofthefourLSBsofthisregister,thecontrollerselectsthechannelregistersetforthatchannelofthatretimerbywritingtothechannelselectregister,0xff,aspreviouslydescribed.
5.
Foreachchannelthatgeneratedaninterrupt,thecontrollerreadschannelregister0x01.
Ifbit4ofthisregisterisset,thentheinterruptwascausedbyalossofCDRlock.
Ifbit0isset,thentheinterruptwascausedbyalossofsignal.
itispossiblethatbothbits0and4couldbeset.
Readingthisregisterwillclearthesebits.
6.
Optionally,foreachchannelthatgeneratedaninterrupt,thecontrollerreadschannelregister0x30.
Ifbit4ofthisregisterisset,thentheinterruptwascausedbyHEOand/orVEOfallingoutoftheconfiguredrange.
Thisinterruptwillonlyoccurifbit6ofchannelregister0x36isset,enablingtheHEO/VEOinterrupt.
Readingregister0x30willclearthisinterruptbit.
7.
Oncethecontrollerhasdeterminedwhatconditioncausedtheinterrupt,thecontrollercanthentaketheappropriateaction.
Forexample,thecontrollermightresettheCDRtocausetheretimertore-adapttothe24SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
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comSNLS448–JANUARY2013incomingsignal.
Ifthereisnolongeranincomingsignal(indicatedbyalossofsignalinterrupt,bit0ofchannelregister0x01),thenthecontrollermightalertanoperatororchangethechannelconfiguration.
Thisissystemdependent.
8.
Readingtheinterruptstatusregisterswillcleartheinterrupt.
ifthisdoesnotcausetheinterruptinputtogohigh,thenanotherdeviceonthesameinputhasgeneratedaninterrupt.
Thecontrollercanaddressthenextdeviceusingtheprocedureabove.
9.
OncealltheinterruptregistersforallchannelsforallDS100RT410sthatgeneratedinterruptshavebeenread,clearingalltheinterruptindications,theINTlineshouldgohighagain.
Thisindicatesthatalltheexistinginterruptconditionshavebeenserviced.
Thechannelregistersreferredtoabove,registers0x01,0x30,0x32,and0x36,aredescribedinthechannelregisterstable,Table5.
OverridingtheCTLEBoostSettingRegister0x03,Register0x13,bit2,andRegister0x3aTooverridetheCTLEboostsettings,register0x03isused.
Thisregistercontainsthecurrently-appliedCTLEboostsettings.
Theboostvaluescanbeoverriddenbyusingthetwo-bitfieldsinthisregisterasshowninthetable.
ThefinalstageoftheCTLEhasanadditionalcontrolbitwhichsetsittoalimitingmode.
Forsomechannels,thisadditionalsettingimprovesthebiterrorrateperformance.
Thisbitisbit2ofregister0x13.
IftheDS100RT410loseslockbecauseofachangeintheCTLEsettings,theDS100RT410willinitiateitslockandadaptationsequenceagain.
Thus,ifyouwritenewCTLEboostvaluestoregister0x03and0x13whichcausetheDS100RT410todropoutoflock,theDS100RT410may,intheprocessofreacquiringtheCDRlock,resettheCTLEsettingstodifferentvaluesthanthoseyousetinregister0x03and0x13.
Ifthisbehaviorisnotunderstood,itcanappearthattheDS100RT410didnotacceptthevaluesyouwrotetotheCTLEboostregisters.
What'sreallyhappening,however,isthatthelockandadaptationsequenceisoverridingtheCTLEvaluesyouwrotetotheCTLEboostregisters.
ThiswillnothappenunlesstheDS100RT410dropsoutoflock.
Iftheadaptmodeissetto0(bits6:5ofchannelregister0x31),thentheCTLEboostvalueswillnotbeoverridden,buttheDS100RT410maystillloselock.
Ifthishappens,theDS100RT410willattempttoreacquirelock.
ifthereferencemodeissetcorrectly,andiftherate/subratecodeissettopermitit,theDS100RT410willbeginsearchingforCDRlockatthehighestallowableVCOdividerratio–thatis,atthelowestconfiguredbitrate.
Atthislowestbitrate,theCTLEboostsettingsusedwillcomenotfromthevaluesinregister0x03,and0x13,butratherfromregister0x3a,thefixedCTLEboostsettingforlowerdatarates.
Thissettingwillbewrittenintoboostsettingregister0x03duringthelocksearchprocess.
Thisvaluemaybedifferentfromthevalueyousetinregister0x03,so,again,itmayappearthattheDS100RT410hasnotacceptedtheCTLEboostsettingsyousetinregisters0x03and0x13.
Theinteractionsofthelockandadaptationsequenceswiththemanually-setCTLEboostsettingscanbedifficulttounderstand.
TomanuallyoverridetheCTLEboostunderallconditions,performthefollowingsteps.
1.
SettheDS100RT410channeladaptmodeto0bywriting0x0tobits6:5ofchannelregister0x31.
2.
SetthedesiredCTLEboostsettinginregister0x3a.
IftheDS100RT410loseslockandattemptstolocktoalowerdatarate,itwillusethisCTLEboostsetting.
3.
SetthedesiredCTLEboostsettinginregister0x03.
ThismaycausetheDS100RT410toloselock.
4.
Ifdesired,settheCTLEstage3limitingbit,bit2ofregister0x13.
IftheDS100RT410loseslockwhentheCTLEboostsettingsaresetaccordingtothesequenceabove,theDS100RT410willtrytoreacquirelock,butitwillnotchangetheCTLEboostsettingsinordertodoso.
OverridingtheCTLESettingsUsedforCTLEAdaptationRegister0x2c,bits3:0,Register0x2f,bit3,Register0x39,bits4:0,andRegisters0x50-0x5fTheCTLEadaptationalgorithmoperatesbysettingtheCTLEbooststagecontrolstoasetofpre-determinedboostsettings,eachofwhichprovidesprogressivelymorehigh-frequencyboost.
Ateachstageintheadaptationprocess,theDS100RT410attemptstophaselocktotheequalizedsignal.
Ifthephaselocksucceeds,theDS100RT410measuresthehorizontalandverticaleyeopeningsusingtheinternaleyemonitorcircuit.
TheDS100RT410computesafigureofmeritfortheeyeopeningandcomparesittothepreviousbestvalueoftheCopyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
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comfigureofmerit.
Whilethefigureofmeritcontinuestoimprove,theDS100RT410continuestotryadditionalvaluesoftheCTLEboostsettinguntilthefigureofmeritceasestoimproveandbeginstodegrade.
Whenthefigureofmeritstartstodegrade,theDS100RT410stillcontinuestotryadditionalCTLEsettingsforapre-determinedtrialcountcalledthe"look-beyond"count,andifnoimprovementinthefigureofmeritresults,itresetstheCTLEboostvaluestothosethatproducedthebestfigureofmerit.
TheresultingCTLEboostvaluesarethenstoredinregister0x03.
The"look-beyond"countisconfiguredbythevalueinregister0x2c,bits3:0.
Thevalueis0x2bydefault.
ThesetofboostvaluesusedascandidatevaluesduringCTLEadaptationarestoredasbitfieldsinregisters0x40-0x5f.
ThedefaultvaluesforthesesettingsareshowninTable6.
ThesevaluesmaybeoverriddenbysettingthecorrespondingregistervaluesovertheSMBus.
Ifthesevaluesareoverridden,thenthenexttimetheCTLEadaptationisperformedthesetofCTLEboostvaluesstoredintheseregisterswillbeusedfortheadaptation.
Resettingthechannelregistersbysettingbit2ofchannelregister0x00willresettheCTLEboostsettingstotheirdefaults.
Sowillpower-cyclingtheDS100RT410.
Table6.
CTLESettingsforAdaptationRegister(Hex)Bits7:6(CTLEBits5:4(CTLEBits3:2(CTLEBits1:0(CTLECTLEBoostCTLEAdaptationStage0)Stage1)Stage2)Stage2)StringIndex400000000004100010001142001000102430100010034410001000445002000205460002000264720002000748000300038490030003094A03000300104B10011001114C11001100124D30003000134E12001200144F21002100155020202020165120022002175222002200185310121012195411021102205520302030215623002300225730203020235811131113245911311131255A12211221265B13111311275C31113111285D21212121295E21122112305F221122113126SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
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comSNLS448–JANUARY2013Asanalternativeto,orinconjunctionwith,writingtheCTLEboostsettingregisters0x40through0x5f,itispossibletosetthestartingCTLEboostsettingindex.
Tooverridethedefaultsetting,whichis0,setbit3ofregister0x2f.
Whenthisbitisset,thestartingindexforadaptationcomesfromregister0x39,bits4:0.
ThisistheindexintotheCTLEsettingstableinregisters0x40through0x5f.
Whenthisstartingindexis0,whichisthedefault,CTLEadaptationstartsatthefirstsettinginthetable,theoneinregister0x40,andcontinuesuntiltheoptimumFOMisreached.
OverridingtheOutputMultiplexerRegister0x09,bit5,Register0x14,bits7:6,andRegister0x1e,bits7:5Bydefault,theDS100RT410outputforeachchannelwillbeasshowninTable7.
Table7.
DefaultOutputStatusDescriptionInputSignalStatusChannelStatusOutputStatusNotPresentNoSignalDetectedMutedPresentNotLockedMutedPresentLockedRetimedDataThisdefaultbehaviorcanbemodifiedbyregisterwrites.
Register0x1e,bits7:5,containtheoutputmultiplexeroverridevalue.
Thevaluesofthisthree-bitfieldandthecorrespondingmeaningsofeachareshowninTable8.
OutputMultiplexerOverrideSettingsBitFieldValueOutputMultiplexerSettingComments0x7MuteDefaultwhennosignalispresentorwhentheretimerisunlocked0x6N/AInvalidSetting0x510MHzClockInternal10MHzclockClockfrequencymaynotbeprecise0x4PRBSGeneratorPRBSGeneratormustbeenabledtooutputPRBSsequence0x3VCOQ-ClockRegister0x09,bit4,andregister0x1e,bit0,mustbesettoenabletheVCOQ-Clock0x2VCOI-Clock0x1RetimedDataDefaultwhentheretimerislocked0x0RawDataIftheoutputmultiplexerisnotoverridden,thatis,ifbit5ofregister0x09isnotset,thenthevalueinregister0x1e,bits7:5,controlstheoutputproducedwhentheretimerhasasignalatitsinput,butisnotlockedtoit.
Thedefaultvalueforthisbitfield,0x7,causestheretimeroutputtomutewhentheretimerisnotlockedtoaninputsignal.
Writingavalueof0x0tothisbitfield,forexample,willcausetheretimertooutputrawdatawhenitisnotlockedtoitsinputsignal.
Settingtheoverridebit,bit5ofregister0x09,willcausetheretimertooutputthevalueselectedbythebitfieldinregister0x1e,bits7:5,evenwhentheretimerislocked.
WhennosignalispresentattheinputtotheselectedchanneloftheDS100RT410thesignaldetectcircuitrywillpowerdownthechannel.
Thisincludestheoutputdriverwhichisthereforemutedwhennosignalispresentattheinput.
Ifyouwanttogetanoutputwhennosignalispresentattheinput,forexampletoenableafree-runningPRBSsequence,thefirststepistooverridethesignaldetect.
Inordertoforcethesignaldetecton,setbit7andclearbit6ofchannelregister0x14.
Evenifthereisnosignalattheinputtothechannel,thechannelwillbeenabled.
Ifthechannelwasdisabledbefore,thecurrentdrainfromthesupplywillincreaseby100–150mAdependingupontheotherchannelsettingsinthedevice.
Thisincreasedcurrentdrainindicatesthatthechannelisnowenabled.
Copyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback27ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
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comThesecondstepistooverridetheoutputmultiplexersetting.
Thisisaccomplishedbysettingbit5ofregister0x09,theoutputmultiplexeroverride.
Oncethisbitisset,thevalueofregister0x1e,bits7:5willcontroltheoutputofthechannel.
Notethatifeitherretimedorrawdataisselected,theoutputwilljustbenoise.
Thedeviceoutputmaysaturatetoastatic1or0.
Ifthereisnosignal,theVCOclockwillbefree-running.
Itsfrequencywilldependuponthedividersettingsanditwillvaryfromparttopartandovertemperature.
IfthePRBSgeneratorisenabled,thePRBSgeneratoroutputcanbeselected.
Thiscaneitherbeatadataratedeterminedbythefree-runningVCOoratadataratedeterminedbytheinputsignal,ifoneispresent.
IfasignalispresentattheinputandtheDS100RT410canlocktoit,theoutputofthePRBSgeneratorwillbesynchronouswiththeinputsignal,butthebitstreamoutputwillbedeterminedbythePRBSgeneratorselection.
The10MHzclockisalwaysavailableattheoutputwhentheoutputmultiplexerisoverridden.
The10MHzclockisafree-runningoscillatorintheDS100RT410andisnotsynchronoustotheinputortoanythingelseinthesystem.
Theclockfrequencywillbeapproximately10MHz,butthiswillvaryfromparttopart.
Ifthereisasignalpresentattheinput,itisnotnecessarytooverridethesignaldetect.
Clearingbits7and6ofregister0x14willreturncontrolofthesignaldetecttotheDS100RT410.
Normally,whentheretimerislockedtoasignalatitsinput,itwilloutputretimeddata.
However,ifdesired,theoutputmultiplexercanbeoverriddeninthisconditiontooutputrawdata.
ItcanalsobesettooutputanyoftheothersignalsshowninTable8.
Ifthereisaninputsignal,andiftheDS100RT410islockedtoit,theVCOI-Clock,theVCOQ-Clock,andtheoutputofthePRBSgenerator,ifitisenabled,willbesynchronoustotheinputsignal.
Whenasignalispresentattheinput,itmightbedesiredtooutputtherawdatainordertoseetheeffectsoftheCTLEwithouttheCDR.
ItmightalsobedesiredtoenablethePRBSgeneratorandoutputthissignal,replacingthedatacontentoftheinputsignalwiththeinternally-generatedPRBSsequence.
OverridingtheVCODividerSelectionRegister0x09,bit2,andRegister0x18,bits6:4Innormaloperation,theDS100RT410setsitsVCOdividertothecorrectdivideratio,either1,2,4,8,or16,dependinguponthebitrateofthesignalatthechannelinput.
Itispossibletooverridethedividerselection.
ThismightbedesirediftheVCOissettofree-run,forexample,tooutputasignalatasub-harmonicoftheactualVCOfrequency.
InordertooverridetheVCOdividersettings,firstsetbit2ofregister0x09.
ThisistheVCOdivideroverrideenable.
Oncethisbitisset,theVCOdividersettingiscontrolledbythevalueinregister0x18,bits6:4.
Thevalidvaluesforthisthree-bitfieldare0x0to0x4.
ThemappingofthebitfieldvaluestothedividerratioisshowninTable9.
Table9.
DividerRatioMappingtoRegister0x18,Bits6:4BitFieldValueDividerRatio01122438416innormaloperation,theDS100RT410willdeterminetherequiredVCOdividerratioautomatically.
ThemostcommonapplicationforoverridingthedividerratioiswhentheVCOissettofree-run.
Normallythedividerratioshouldnotbeoverriddenexceptinthiscase.
UsingthePRBSGeneratorRegister0x0d,bit5,Register0x1e,bit4,andRegister0x30,bit3andbits1:0TheDS100RT410includesaninternalPRBSgeneratorwhichcangeneratestandardPRBS-9andPRBS-31bitsequences.
ThePRBSgeneratorcanproduceaPRBSsequencethatissynchronoustotheincomingdatasignal,oritcangenerateaPRBSsequenceusingtheinternalfree-runningVCOasaclock.
Bothmodesofoperationaredescribedintheparagraphsthatfollow.
28SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
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comSNLS448–JANUARY2013ToproduceaPRBSsequencethatissynchronizedtotheincomingdatasignal,theDS100RT410mustbelockedtotheincomingsignal.
Whenthisistrue,thesignaldetectissetandthechannelisactive.
Inaddition,theVCOislockedtotheincomingsignalTheVCOwillremainlockedtotheincomingsignalregardlessofthestateoftheoutputmultiplexer.
ToactivatethePRBSgenerator,firstsetbit4ofregister0x1e.
ThisbitenablesthePRBSgeneratordigitalcircuitry.
ThenresetthePRBSclockbyclearingbit3ofregister0x30.
SelecteitherPRBS-9orPRBS-31bysettingbits1:0ofregister0x30.
Setthisbitfieldto0x0forPRBS-9andto0x2forPRBS-31.
ThenloadthePRBSclockbysettingbit3ofregister0x30.
Finally,enablethePRBSclockbysettingbit5ofregister0x0d.
ThissequenceofregisterwriteswillenabletheinternalPRBSgenerator.
Asdescribedabove,toselectthePRBSgeneratorastheoutputfortheselectedchannel,setbit5ofregister0x09,theoutputmultiplexeroverride.
Thenwrite0x4tobits7:5ofregister0x1e.
ThisselectsthePRBSgeneratorforoutput.
Forthecasedescribedabove,theoutputPRBSsequencewillbesynchronoustotheincomingdata.
Therearetwoothercasesofinterest.
ThefirstiswhenthereisaninputsignalbutthePRBSsequenceshouldnotbesynchronoustoit.
Inotherwords,inthiscaseitisdesiredthattheVCOshouldfree-run.
Thesecondcaseiswhenthereisnoinputsignal,butthePRBSsequenceshouldstillbeoutput.
Again,inthiscase,theVCOisfree-running.
Theregistersettingsforthesetwocasesarealmostthesame.
Theonlydifferenceisthat,ifthereisnoinputsignal,thenthechannelwillbedisabledandpowered-downbydefault.
Inordertoforceenablethechannel,writea1tobit7anda0tobit6ofregister0x14.
Thisforcesthesignaldetecttobeactiveandenablestheselectedchannel.
Theremainderoftheregisterwritesequenceisdesignedtodisablethephase-lockedloopsothattheVCOcanfreerun.
Firstwritea1tobit3ofregister0x09,then0x0tobits1:0ofregister0x1b.
Thisdisablesthechargepumpforthephase-lockedloop.
Nextwritea1tobit2ofregister0x09.
ThisenablestheVCOdivideroverride.
ThensettheVCOdividerratiobywritingtoregister0x18asshowninTable9.
Foranoutputfrequencyofapproximately10.
3125GHz,setthedividerratioto1bywriting0x0tobits6:4ofregister0x18.
Donotclearbit3whenyouwritea1tobit2ofregister0x09.
Nowwritea1tobit7ofregister0x09.
ThisenablestheVCOCAPDACoverride.
WritethedesiredVCOcapcounttoregister0x08,bits4:0.
ThemappingofVCOfrequenciestocapcountwillvarysomewhatfromparttopart.
TheVCOcapcountshouldbesetto0x0ctoyieldanoutputVCOfrequencyofapproximately10.
3125GHz.
Donotclearbits3and2whenyouwritea1tobit7ofregister0x09.
Nowwritea1tobit6ofregister0x09.
ThisenablestheVCOLPFDACwhichcangenerateaVCOcontrolvoltageinternallytotheDS100RT410.
OncetheLPFDACisenabled,writethedesiredvalueoftheLPFDACoutputinregister0x1f,bits4:0.
ForanoutputVCOfrequencyofapproximately10.
3125GHz,settheLPFDACsettingto0x12.
Donotcleartheremainingbitsofregister0x09whenyouwritea1tobit6.
Now,asabove,enablethePRBSgeneratorandsetittothedesiredbitsequence,thenselecttheoutputtobethePRBSgeneratorbysettingtheoutputmultiplexer.
Noticethatwhenthisentiresequencehasbeencompleted,bits7:2ofregister0x09willallbeset.
Thedefaultvalueofregister0x09is0x00,soyoucanclearalltheoverrideswhenyouarereadytoreturntonormaloperationbywriting0x00toregister0x09.
TheVCOfrequencyinfree-runwillvarysomewhatfromparttopart.
InordertodetermineexactvaluesoftheCAPDACandLPFDACsettings,itwillbenecessarytodirectlymeasuretheVCOfrequencyusingsomesortoffrequency-measurementdevicesuchasafrequencycounteroraspectrumanalyzer.
WhentheVCOissettofree-runmodeasabove,youcanselecttheVCOI-clock(in-phaseclock)tobetheoutputasshowninTable8.
YoucanmeasurethefrequencyoftheVCOI-clockwhileadjustingtheCAPDACandLPFDACvaluesuntiltheVCOI-clockfrequencyisacceptableforyourapplication.
ThenyoucanonceagainselectthePRBSgeneratorastheoutputusingtheoutputmultiplexerselectionfield.
Copyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback29ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
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comUsingtheInternalEyeOpeningMonitorRegister0x11,bits7:6andbit5,Register0x22,bit7,Register0x24,bit7andbit0,Register0x25,Register0x26,Register0x27,Register0x28,andRegister0x2aTheDS100RT410includesaninternaleyeopeningmonitor.
TheeyeopeningmonitorisusedbytheretimertocomputeafigureofmeritforautomaticadaptationoftheCTLE.
ItcanalsobecontrolledandqueriedthroughtheSMBusbyasystemcontroller.
Theeyeopeningmonitorproduceserrorhitcountsforsettablephaseandvoltageoffsetsofthecomparatorintheretimer.
ThisissimilartothewaymanyBitErrorRateTestSetsmeasureeyeopening.
Ateachphaseandamplitudeoffsetsetting,theeyeopeningmonitordeterminesthenominalbitvalue("0"or"1")usingitsprimarycomparator.
ThisisthebitvaluethatisresynchronizedtotherecoveredclockandpresentedattheoutputoftheDS100RT410.
Theeyeopeningmonitoralsodeterminesthebitvaluedetectedbytheoffsetcomparator.
Thisinformationyieldsaneyecontour.
Here'showthisworks.
Iftheoffsetcomparatorisoffsetinvoltagebyanamountlargerthantheverticaleyeopening,forexample,thentheoffsetcomparatorwillalwaysdecidethatthecurrentbithasabitvalueof"0".
Whenthebitisreallya"1",asdeterminedbytheprimarycomparator,thisisconsideredabiterror.
Thenumberofbiterrorsiscountedforasettableintervalateachsettingoftheoffsetphaseandvoltageoftheoffsetcomparator.
Theseerrorcountscanbereadfromregisters0x25and0x26forsequentialphaseandvoltageoffsets.
Theseerrorcountsforeachphaseandvoltageoffsetsforma64X64pointarray.
Asurfaceorcontourplotoftheerrorhitcountversusphaseandvoltageoffsetproducesaneyediagram,whichcanbeplottedbyexternalsoftware.
Theeyeopeningmonitorworksintwomodes.
Inthefirst,onlythehorizontalandverticaleyeopeningsaremeasured.
Theeyeopeningmonitorfirstsweepsitsvariable-phaseclockthroughoneunitintervalwiththecomparisonvoltagesettothemidpointofthesignal.
Thisdeterminesthemidpointofthehorizontaleyeopening.
Theeyeopeningmonitorthensetsitsvariablephaseclocktothemidpointofthehorizontaleyeopeningandsweepsitscomparisonvoltage.
Thesetwomeasurementsdeterminethehorizontalandverticaleyeopenings.
Thehorizontaleyeopeningvalueisreadfromregister0x27andtheverticaleyeopeningfromregister0x28.
Bothvaluesaresinglebytevalues.
Themeasurementofhorizontalandverticaleyeopeningisveryfast.
Thespeedofthismeasurementmakesitusefulfordeterminingtheadaptationfigureofmerit.
Innormaloperation,theHEOandVEOareautomaticallymeasuredperiodicallytodeterminewhethertheDS100RT410isstillinlock.
Readingregisters0x27and0x28willyieldthemost-recentlymeasuredHEOandVEOvalues.
Innormaloperation,theeyemonitorcircuitryispowereddownmostofthetimetosavepower.
Whentheeyeistobemeasuredunderexternalcontrol,itmustfirstbeenabledbywritinga0tobit5ofregister0x11.
Thedefaultvalueofthisbitis1,whichpowersdowntheeyemonitorexceptwhenitispowered-upperiodicallybytheCDRstatemachineandusedtotestCDRlock.
TheeyemonitormustbepowereduptomeasuretheeyeunderexternalSMBuscontrol.
Bits7:6ofregister0x11arealsousedduringeyemonitoroperationtosettheEOMvoltagerange.
Thisisdescribedbelow.
Asinglewritetoregister0x11cansetbothbit5andbits7:6inoneoperation.
Register0x3e,bit7,enableshorizontalandverticaleyeopeningmeasurementsaspartofthelockvalidationsequence.
Whenthisbitisset,theCDRstatemachineperiodicallyusestheeyemonitorcircuitrytomeasurethehorizontalandverticaleyeopening.
Iftheeyeopeningsaretoosmall,accordingtothepre-determinedthresholdsinregister0x6a,thentheCDRstatemachinedeclareslocklossandbeginsthelockacquisitionprocessagain.
ForSMBusacquisitionoftheinternaleye,thislockmonitoringfunctionmustbedisabled.
PriortooverridingtheEOMbywritinga1tobit0ofregister0x24,disablethelockmonitoringfunctionbywritinga0tobit7ofregister0x3e.
Oncetheeyehasbeenacquired,youcanreinstateHEOandVEOlockmonitoringbyonceagainwritinga1tobit7ofregister0x3e.
UnderexternalSMBuscontrol,theeyeopeningmonitorcanbeprogrammedtosweepthroughallits64statesofphaseandvoltageoffsetautonomously.
Thismodeisinitiatedbysettingregister0x24,bit7,thefast_eommodebit.
Register0x22,bit7,theeom_ovbit,shouldbeclearedinthismode.
Whenthefast_eombitisset,theeyeopeningmonitoroperationisinitiatedbysettingbit0ofregister0x24,whichisself-clearing.
Assoonasthisbitisset,theeyeopeningmonitorbeginstoacquireeyedata.
Theresultsoftheeyeopeningmonitorerrorcounterarestoredinregister0x25and0x26.
Inthismodetheeyeopeningmonitorresultscanbeobtainedbyrepeatedmulti-bytereadsfromregister0x25.
Itisnotnecessarytoreadfromregister0x26foramulti-byteread.
Assoonastheeightmostsignificantbitsarereadfromregister0x25,theeightleastsignificantbitsforthecurrentsettingareloadedintoregister0x25andtheycanbereadimmediately.
30SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
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comSNLS448–JANUARY2013Assoonasthereadoftheeightmostsignificantbitshasbeeninitiated,theDS100RT410setsitsphaseandvoltageoffsetstothenextsettingandstartsitserrorcounteragain.
TheresultofthisisthatthedatafromtheeyeopeningmonitorisavailableasquicklyasitcanbereadovertheSMBuswithnofurtherregisterwritesrequired.
TheexternalcontrollerjustreadsthedatafromtheDS100RT410overtheSMBusasfastasitcan.
Whenallthedatahasbeenread,theDS100RT410clearstheeom_startbit.
Ifmulti-bytereadsarenotused,meaningthatthedeviceisaddressedeachtimeabyteisreadfromit,thenitisnecessarytoreadregister0x25togettheMSB(theeightmostsignificantbits)andregister0x26togettheLSB(theeightleastsignificantbits)ofthecurrenteyemonitormeasurement.
Again,assoonasthereadoftheMSBhasbeeninitiated,theDS100RT410setsitsphaseandvoltageoffsetstothenextsettingandstartsitserrorcounteragain.
Inthismodebothregisters0x25and0x26mustbereadinordertogettheeyemonitordata.
Theeyemonitordataforthenextsetofphaseandvoltageoffsetswillnotbeloadedintoregisters0x25and0x26untilbothregistershavebeenreadforthecurrentsetofphaseandvoltageoffsets.
Inalleyeopeningmonitormodes,theamountoftimeduringwhichtheeyeopeningmonitoraccumulateseyeopeningdatacanbesetbythevalueofregister0x2a.
Ingeneral,thegreaterthisvaluethelongertheaccumulationtime.
Whenthisvalueissettoitsmaximumpossiblevalueof0xff,themaximumnumberofsamplesacquiredateachphaseandamplitudeoffsetisapproximately218.
Evenwiththissetting,theeyeopeningmonitorvaluescanbereadfromtheSMBuswithnodelay.
TheeyeopeningmonitoroperationissufficientlyfastthattheSMBusreadoperationcannotoutrunit.
Theeyeopeningismeasuredattheinputtothedatacomparator.
Atthispointinthedatapath,asignificantamountofgainhasbeenappliedtothesignalbytheCTLE.
Inmanycases,theverticaleyeopeningasmeasuredbytheEOMwillbeontheorderof400to500mVpeak-to-peak.
Thesecondarycomparator,whichisusedtomeasuretheeyeopening,hasanadjustablevoltagerangefrom±100mVto±400mV.
TheEOMvoltagerangeisnormallysetbytheCDRstatemachineduringlockandadaptation,buttherangecanbeoverriddenbywritingatwo-bitcodetobits7:6ofregister0x11.
ThevaluesofthiscodeandthecorrespondingEOMvoltagerangesareshowninTable10.
Table10.
EOMVoltageRangevs.
Bits7:6ofRegister0x11ValueinBits7:6ofRegister0x11EOMVoltageRange(±mV)0x0±1000x1±2000x2±3000x3±400NotethatthevoltagerangesshowninTable10arethevoltagerangesofthesignalattheinputtothedatapathcomparator.
ThesevaluesarenotdirectlyequivalenttoanyobservablevoltagemeasurementsattheinputtotheDS100RT410.
NotealsothatiftheEOMvoltagerangeissettoosmallthevoltagesweepofthesecondarycomparatormaynotbesufficienttocapturetheverticaleyeopening.
Whenthishappenstheeyeboundarieswillbeoutsidetheverticalvoltagerangeoftheeyemeasurement.
EnablingSlowRise/FallTimeontheOutputDriverRegister0x18,bit2NormallytheriseandfalltimesoftheoutputdriveroftheDS100RT410aresetbytheslewrateoftheoutputtransistors.
Bydefault,theoutputtransistorsarebiasedtoprovidethemaximumpossibleslewrate,andhencetheminimumpossibleriseandfalltimes.
Insomeapplications,slowerriseandfalltimesmaybedesired.
Forexample,slowerriseandfalltimesmayreducetheamplitudeofelectromagneticinterference(EMI)producedbyasystem.
Settingbit2ofregister0x18willadjusttheoutputdrivercircuitrytoincreasetheriseandfalltimesofthesignal.
SettingthisbitwillapproximatelydoublethenominalriseandfalltimesoftheDS100RT410outputdriver.
Thisbitisclearedbydefault.
Copyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback31ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
ti.
comInvertingtheOutputPolarityRegister0x1f,bit7Insomesystems,thepolarityofthedatadoesnotmatter.
Insystemswhereitdoesmatter,itissometimesnecessary,forthepurposesoftracerouting,forexample,toinvertthenormalpolaritiesofthedatasignals.
TheDS100RT410caninvertthepolarityofthedatasignalsbymeansofaregisterwrite.
Writinga1tobit7ofregister0x1finvertsthepolarityoftheoutputsignalfortheselectedchannel.
Thiscanprovideadditionalflexibilityinsystemdesignandboardlayout.
OverridingtheFigureofMeritforAdaptationRegister0x2c,bits5:4,Register0x31,bits6:5,Register0x6b,Register0x6c,Register0x6d,andRegister0x6e,bits7and6ThedefaultfigureofmeritfortheCTLEadaptationissimple.
ThehorizontalandverticaleyeopeningsaremeasuredforeachCTLEboostsetting.
Theverticaleyeopeningisscaledtoaconstantreferenceverticaleyeopeningandthesmallerofthehorizontalorverticaleyeopeningistakenasthefigureofmeritforthatsetofequalizersettings.
Theobjectiveistoadapttheequalizertoapointwherethehorizontalandverticaleyeopeningsarebothaslargeaspossible.
Thisusuallyprovidesoptimumbiterrorrateperformanceformosttransmissionchannels.
Insomesystemstheadaptationcanreachabettersettingifonlythehorizontaloronlyverticaleyeopeningisusedtocomputethefigureofmeritratherthanusingboth.
Thiswillbesystem-dependentandtheusermustdeterminethroughexperimentwhetherthisprovidesbetteradaptationintheuser'ssystem.
FortheDS100RT410,theCTLEfigureofmerittypecanbesetusingregister0x31,bits4:3.
Thevalueofthistwo-bitfieldversustheconfiguredfigureofmerittypeisshowninTable11.
Table11.
FigureofMeritTypeSettingRegister0x31,bits4:3FigureofMeritType0x0BothHEOandVEOareused0x1OnlyHEOisused0x2OnlyVEOisused0x3BothHEOandVEOareused(default)Forsometransmissionmediatheadaptationcanreachabettersettingifadifferentfigureofmeritisused.
TheDS100RT410includesthecapabilityofadaptingbasedonaconfigurablefigureofmerit.
Theconfigurablefigureofmeritisstructuredasshownintheequationbelow.
FOM=(HEO–b)Xa+(VEO–c)x(1–a)Inthisequation,HEOishorizontaleyeopening,VEOisverticaleyeopening,FOMisthefigureofmerit,andthefactorsa,b,andcaresetusingregisters0x6b,0x6c,and0x6drespectively.
Inordertousetheconfigurablefigureofmerit,theenablebitsmustbeset.
TousetheconfigurablefigureofmeritfortheCTLEadaptation,setbit7ofregister0x6e,theen_new_fom_ctlebit.
SettingtheRateandSubrateforLockAcquisitionRegister0x2f,bits7:6and5:4Therateandsubratesettings,whichconfigurethesetofVCOfrequenciestowhichtheVCOcoarsetuningistobecalibratedaresetusingchannelregister0x2f.
Bits7:6areRATE,andbits5:4areSUBRATE.
SettingtheAdaptation/LockModeRegister0x31,bits6:5,Register0x3e,bit7,andRegister0x6aThereare2adaptationmodesavailableintheDS100RT410.
Mode0:TheuserisresponsibleforsettingtheCTLEvalues.
Thismodeisusedifthetransmissionchannelresponseisfixed.
Mode1:TheCTLEisadaptedtoequalizethetransmissionchannel.
Thismodeisprimarilyusedforsmoothly-varyinghigh-losstransmissionchannelssuchascablesandsimplePCBtraces.
32SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410DS100RT410www.
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comSNLS448–JANUARY2013Bits6:5ofregister0x31determinetheadaptationmodetobeused.
ThemappingoftheseregisterbitstotheadaptationalgorithmisshowninTable5.
Table12.
DS100RT410AdaptationAlgorithmSettingsRegister0x31,Bit6Register0x31,Bit5AdaptModeSettingAdaptationAlgorithmadapt_mode[1]adapt_mode[0]0000NoAdaptation0101AdaptCTLEUntilOptimum(Default)BydefaulttheDS100RT410requiresthattheequalizedinternaleyeexhibithorizontalandverticaleyeopeningsgreaterthanapre-setminimuminordertodeclareasuccessfullock.
Theminimumvaluesaresetinregister0x6a.
TheDS100RT410continuouslymonitorsthehorizontalandverticaleyeopeningswhileitisinlock.
Iftheeyeopeningfallsbelowthethresholdsetinregister0x6a,theDS100RT410willdeclarealossoflock.
InitiatingAdaptationRegister0x24,bit2,andRegister0x2f,bit0WhentheDS100RT410becomesunlocked,itwillautomaticallytrytoacquirelockandadaptitsCTLE.
Adaptationcanalsobeinitiatedbytheuser.
CTLEadaptationcanbeinitiatedbysettingandthenclearingregister0x2f,bit0.
SettingtheReferenceEnableModeRegister0x36,bits5:4Register0x36,bits5:4,aretheref_modebits.
Thesebitsshouldbesettoavalueof2'b11.
Notethatthisisnotthedefault.
ThereferencemodemustbesetpriortousingtheDS100RT410.
A25MHzreferenceclocksignalmustbeprovidedonthereferenceinpin(pin19).
TheuseofthereferenceclockintheDS100RT410isexplainedbelow.
First,thereferenceclockallowstheDS100RT410tocalibrateitsVCOfrequencyatpower-upanduponreset.
ThisenablestheDS100RT410todeterminetheoptimumcoarseVCOtuningsettinga-priori,whichmakesphaselockmuchfaster.
TheDS100RT410isnotrequiredtotunethroughtheavailablecoarseVCOtuningsettingsasittriestoacquirelocktoaninputsignal.
Itcanselectthecorrectsettingimmediately.
Second,iftheDS100RT410loseslockforsomereasonandtheVCOdriftsfromitsphase-lockedfrequency,theDS1010DF410candetectthisveryquicklyusingthereferenceclock.
Detectinganout-of-lockconditionquicklyallowstheDS100RT410toraiseaninterruptindicatingthatithaslostlockquickly,whichthesystemcontrollercanthenservicetocorrecttheproblemquickly.
Finally,somedatasignalswithlargejitterspursintheirfrequencyspectracancausetheDS1100DF410tofalselock.
Thisoccurswhenthedatapatternexhibitsstrongdiscretefrequencycomponentsinitsfrequencyspectrum,orwhenthedatapatternhasalotofperiodicjitterimposedonit.
Ifyoulookatsuchasignalinthefrequencydomainusingaspectrumanalyzer,itwillclearlyshow"spurs"closeintothefundamentaldataratefrequency.
ThesespurscancausetheDS100RT410tofalselock.
Usingthe25MHzreferenceclock,theDS100RT410candetectwhenitislockedtoajitterspur.
Whenthishappens,theDS100RT410willre-initiatetheadaptationandlocksequenceuntilitlockstothecorrectdatarate.
Thisprovidesimmunitytofalselockconditions.
Thereferenceclockmodeissetbyatwo-bitfield,register0x36,bits5:4.
Thisfieldshouldalwaysbesettoavalueof3or2'b11.
Copyright2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback33ProductFolderLinks:DS100RT410DS100RT410SNLS448–JANUARY2013www.
ti.
comSettingtheOutputDifferentialVoltageRegister0x2d,bits2:0ThereareeightlevelsofoutputdifferentialvoltageavailableintheDS100RT410,from0.
6Vto1.
3Vin0.
1Vincrements.
Thevaluesdrv_sel_vod[2:0]inbits2:0ofregister0x2dsettheoutputVOD.
TheavailableVODsettingsandthecorrespondingvaluesofthisbitfieldareshowninTable13.
Table13.
VODSettingsBit2,drv_sel_vod[2]Bit1,drv_sel_vod[1]Bit0,drv_sel_vod[0]SelectedVOD(V,peak-to-peak,differential)0000.
60010.
70100.
80110.
91001.
01011.
11101.
21111.
3SettingtheOutputDe-emphasisSettingRegister0x15,bits2:0andbit6Fifteenoutputde-emphasissettingsareavailableintheDS100RT410,rangingfrom0dBto-12dB.
Thede-emphasisvaluescomefromregister0x15,bits2:0,whichmakeupthebitfielddvr_dem,andregister0x15,bit6,whichisthede-emphasisrangebit.
Theavailabledriverde-emphasissettingsandthemappingtothesebitsareshowninTable14.
Table14.
DriverDe-EmphasisSettingsRegister0x15,Bit2,Register0x15,Bit1,Register15,Bit0,Register0x15,Bit6,De-emphasisSettingdvr_dem[2]drv_dem[1]drv_dem[0]drv_dem_range(dB)000X0.
00011-0.
90010-1.
50101-2.
00111-2.
81001-3.
30100-3.
51011-3.
91101-4.
50110-5.
01111-5.
61000-6.
01010-7.
51100-9.
01110-12.
034SubmitDocumentationFeedbackCopyright2013,TexasInstrumentsIncorporatedProductFolderLinks:DS100RT410PACKAGEOPTIONADDENDUMwww.
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com11-Apr-2013Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinishMSLPeakTemp(3)OpTemp(°C)Top-SideMarkings(4)SamplesDS100RT410SQ/NOPBACTIVEWQFNRHS481000Green(RoHS&noSb/Br)CUSNLevel-3-260C-168HR-40to85100RT410DS100RT410SQE/NOPBACTIVEWQFNRHS48250Green(RoHS&noSb/Br)CUSNLevel-3-260C-168HR-40to85100RT410(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
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TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)MultipleTop-SideMarkingswillbeinsideparentheses.
OnlyoneTop-SideMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireTop-SideMarkingforthatdevice.
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016.
47.
37.
31.
312.
016.
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016.
47.
37.
31.
312.
016.
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