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SemiconductorComponentsIndustries,LLC,2003November,2003Rev.
11PublicationOrderNumber:AND8090/DAND8090/DACCharacteristicsofECLDevicesAPPLICATIONNOTEUSAGEThisapplicationnoteprovidesageneraloverviewoftheACcharacteristicsthatarespecifiedontheONSemiconductordatasheetsforMECL10K,10H,100H,ECLinPS,ECLinPSLite,andGigaCommSiGedevices.
Datasheetinformationtakesprecedenceoverthisapplicationnoteiftherearedifferences.
Thisapplicationnoteincludesthefollowinginformation:ACTestBenchInformationACCharacteristicDefinitionsACCharacteristicTestMethodsACCharacteristicExamplesACCharacteristicSymbolsACCharacteristicReferencesTABLEOFCONTENTSLabTestingTestBenchOverview2TestInitialization2TestBenchEquipment3ACTestBoards4SignalLevelsACHIGHandLOWLevels5OscilloscopeAveraging5InputLevels5OutputLevels5OutputSwing6SignalTimingDutyCycle6MaximumInputFrequency6DifferentialCharacteristicsDifferentialInputApplication7UnusedOutputTermination7DifferentialCrosspoint7InputVoltageSwing7TestInputSwing7DifferentialCharacteristics(continued)CommonModeRange7DifferentialInputExample8SingleEndedCharacteristicsSingleEndedInputs8SingleEnded50%Points8Single–EndedInputVoltageRange8Single–EndedInputTestLevel8DifferentialInputs(Single–EndedMode)9TimingCharacteristicsOutputRiseandFallTimes9PropagationDelay10Skew(DutyCycle)11Skew(WithinDevice)11Skew(DevicetoDevice)11MinimumInputPulseWidth11SetupandHoldTime12SetandResetRecoveryTime14JitterJitterOverview15RandomJitter15RJConfidenceLevels15TotalRJTestSetup16TestEquipmentRJTestSetup16DUTRJCalculation16DeterministicJitter17TotalDJTestSetup17TestEquipmentDJTestSetup18DUTDJCalculation18SymbolsandAcronymsSymbolsandAcronymsTable19ReferencesACCharacteristicReferences20APPLICATIONNOTEhttp://onsemi.
comAND8090/Dhttp://onsemi.
com2LABTESTINGTestBenchOverviewSpecializedtestbenchesareusedtodeterminetheACcharacteristicsoftheDeviceUnderTest(DUT).
AtypicaltestbenchsetupforadifferentialdeviceisshowninFigure1.
TestInitializationThetestcablesareconnectedfromthepulsegeneratortotheappropriateDUTtestboardinputconnectors.
ThetestcablesareconnectedfromtheDUTtestboardoutputconnectorstotheappropriatedigitalsamplingoscilloscopeinputconnectors.
ThepowersupplycablesareconnectedtotheDUTtestboardpowersupplyconnectors.
Theairflowregulatorissetto500lfpmandthedesiredDUTambientairtemperature.
TheDUTisinthisenvironmentforaminimumof3minutesbeforetestingbegins.
Datasheetspecificationsaretypicallygivenfor40°C,25°C,and85°C.
QCHANNELA(50W)CHANNELB(50W)QTRIGGERCHANNELC(50W)CHANNELD(50W)TRIGGERPULSEGENERATOROSCILLOSCOPEVCCDDQQ50WCOAXVEE50WCOAX50WCOAX50WCOAX50WCOAX50WCOAXFigure1.
ACCharacterizationTestBenchSetupTestBoardAND8090/Dhttp://onsemi.
com3TestBenchEquipmentACcharacterizationequipmentiscarefullyselectedtoensurethatthetestequipmentissuitableforthedevicestobetested,andthatthemeasurementsareaccurateandrepeatable.
Forexample,samplingheadbandwidthmustbewideenoughforaccurateriseandfalltimemeasurements.
ThetestequipmentthatiscurrentlyusedbyONSemiconductorislistedinTable1.
Furtherinformationonthetestequipmentcanbefoundattherespectivemanufacturer'swebsite.
Table1.
ONSemiconductorTestBenchEquipmentTestEquipmentManufacturer/ModelEquipmentNotesDigitalSamplingOscilloscopeTektronix11801CSD24/2620GHzModuleCustomerscanuselowerperformanceequipmentforevaluation,butmaynotbeabletoduplicateallofONSemiconductormeasurements(e.
g.
,rise/fallandpropagationdelaytimes).
DigitalSamplingOscilloscopeTektronixTDS800080E0320GHzModule80E0150GHzModuleCustomerscanuselowerperformanceequipmentforevaluation,butmaynotbeabletoduplicateallofONSemiconductormeasurements(e.
g.
,rise/fallandpropagationdelaytimes).
Notethatthe50GHzsamplingmoduleisrequiredforGigaCommdevicesastheytypicallyhaveriseandfalltimesbetween20psand50ps.
Pulse/PatternGeneratorsTektronixHFS9009Maximumpulsefrequencyof630MHz.
Agilent8133AMaximumpulsefrequencyof3.
0GHz.
AdvantestD3186Maximumpulsefrequencyof12GHz.
DCPowerSuppliesAgilentHP6624AUsedtosupplyVCC,VEE,andspecializedbiasvoltages.
LowresistancesupplyvoltageconnectionsandRFqualitysupplyfiltercapacitorsaredesignedintotheACtestboardsthatareusedtomounttheDUT.
TestCablesVariousManufacturersHighbandwidth,lowlossmatchedcablesareusedtoensureaccuratemeasurements.
Eachcableofaninput/outputcablepairisthesamelengthandhasacharacteristicimpedanceof50ohms.
AirFlowRegulatorTemptronicsThermostreamEstablishestheDUTambienttemperature.
AND8090/Dhttp://onsemi.
com4ACTestBoardsEachtestdeviceismountedonacontrolledimpedancetestboardthatisspecificallydesignedtomeasureACcharacteristics.
Testboardstypicallyhavemultiplelayers.
AnexampleofanACcharacteristictestboardisshowninFigures2through4.
ThisparticulartestboardisusedtotestECLinPSLiteSOIC8devices.
Figure2.
TopPhotooftheACTestBoardFigure3.
TopSchematicoftheACTestBoardFigure4.
BottomSchematicoftheACTestBoardAND8090/Dhttp://onsemi.
com5SIGNALLEVELSACHIGHandLOWLevelsTheHIGHlevelreferredtointhisapplicationnotecorrespondstotheIEEE"topline,"andtheLOWlevelcorrespondstotheIEEE"baseline"asshowninFigure5.
The50%pointlieshalfwaybetweentheHIGHandLOWlevels.
RefertoIEEEStandard1941977forfurthervoltagelevelinformation.
Figure5.
HIGHandLOWWaveformDefinitionHIGHLOW50%(topline)(baseline)VIH/VOHVIL/VOLInputLevelsOperationaldifferentialinputlevelsarespecifiedbyVPPandtheVIHCMRrangeasdescribedinthe"DifferentialCharacteristics"section.
OperationalsingleendedinputlevelsarespecifiedbyVILandVIHasdescribedinthe"SingleEndedCharacteristics"section.
OutputLevelsOutputsignalsmaybedifferentialorsingleended.
ACcharacteristicsforONSemiconductordeviceswithECLoutputsaretypicallymeasuredforanoutputterminationof50WtoVTT(theterminationvoltageequaltoVCC2.
0V).
HIGHandLOWoutputlevelsrangebetweentheboundaryandthresholdvaluesfortherespectiveHIGHandLOWinputlevelsspecifiedondatasheets.
OutputlogiclevelsareshowninFigure6.
VOHmaxHIGHVOHminVOLmaxLOWVOLminBoundaryThresholdThresholdBoundaryFigure6.
OutputLogicLevelsOscilloscopeAveragingDigitalsamplingoscilloscopesuseanalgorithmtodeterminetheaverageleveloverapulsewidthtoestablishtheHIGHandLOWlevels.
AnexampleisshowninFigure7.
ThehorizontalcursorsattheHIGHandLOWlevelsindicatethedeterminedaveragelevels.
Figure7.
HIGHandLOWWaveformLevelsHIGHLOWAND8090/Dhttp://onsemi.
com6OutputSwingTheoutputswing(VOUTpp)ismeasuredbetweentheHIGHandLOWlevelsofeachindividualdifferentialorsingleendedoutput.
TheoutputvoltageswingforeachindividualoutputisdefinedbythefollowingequationandFigure8.
VOUTPP+VOH*VOLVOUTppVOHVOL50%Figure8.
OutputVoltageSwingTheVOUTppvalueisshownastheverticalaxisinthedatasheetmaximumfrequencyplots(refertothe"MaximumInputFrequency"section).
SIGNALTIMINGDutyCycleThedutycycleistheratiooftheHIGHpulsewidth(PW)tothesignalperiodandisdescribedbythefollowingequations:SignalPeriod=TimebetweenadjacentrisingedgesDutyCycle=(HIGHPulseWidth/SignalPeriod)*100%The50%pointsareusedtomeasuretheHIGHpulsewidthandthesignalperiod.
ACcharacteristicsforONSemiconductordevicesaretypicallymeasuredfora50%dutycycleinput.
A50%dutycycleinput/outputisshowninFigure9.
NotethattheHIGHandLOWpulsewidths(PWHandPWLrespectively)areequalfora50%dutycyclesignal.
PWHHIGHLOW50%PWLFiftyPercentDutyCycle:PWH=PWLFigure9.
Input/OutputDutyCycleMaximumInputFrequencyThisisatypicaldeviceperformancevalue.
Itisthehighestallowableinputfrequencyforproperdeviceoperation(fMAX).
Forshiftregisters,itisreferredtoastheMaximumShiftFrequency(fSHIFT).
Itisthefrequencywheretheoutputvoltageswing(VOUTpp)isequaltoaminimumvaluethatisdeterminedbythedevicetype,oritisthefrequencywherethedevicenolongerfunctionsproperly.
Anoutputvoltageswingversusinputfrequencyplotistypicallyincludedwithdatasheets.
FortheMC100EP90exampleshowninFigure10,themaximumlistedinputfrequencyof3.
0GHzoccursatanoutputvoltageswingofapproximately400mV.
ThejittershowninFigure10isdescribedinalatersection.
010020030040050060070080090001000200030004000Figure10.
OutputVoltagevs.
InputFrequencyExampleFREQUENCY(MHz)VOLTAGE(mV)12345678ps(RMS)(JITTER)9AND8090/Dhttp://onsemi.
com7DIFFERENTIALCHARACTERISTICSSectionNoteThissectionexplainsconceptsthatonlyapplyfordifferentialinputsand/oroutputs.
Differentialinputsandoutputshavetrueandinvertedpins,andareoftenreferredtoas"complimentary"inputsandoutputs.
Anexampleofadifferentialinputisatruedatainput(D),andaninverteddatainput(D).
DifferentialInputApplication–Trueandinvertedinputsignalsmustbeappliedinordertoobtainaccuratedifferentialtestmeasurementsfordifferentialinputdevices.
ThetrueoutputofthepulsegeneratorisconnectedtothetrueinputoftheDUT,andtheinvertedoutputofthepulsegeneratorisconnectedtotheinvertedinputoftheDUT.
UnusedOutputTermination–Anunusedoutputofadifferentialpairmustbeterminatedinthesamemannerastheusedoutputinordertoobtainaccuratemeasurements.
DifferentialCrosspoint–Differentialcrosspointsareusedasameasurementpointfordifferentialinputanddifferentialoutputsignals.
Adifferentialcrosspoint(Xpt)islocatedwherethetrueandinvertedinputsoroutputsintersectasshowninFigure11.
Figure11.
DifferentialInput/OutputCrosspointDorQDorQXptInputVoltageSwing–Theminimuminputvoltageswing(VPPmin)isfoundbydecreasingtheswingbetweenthetrueandinvertedinputsuntilthedevicenolongerperformsitsspecifiedfunction.
Themaximuminputvoltageswing(VPPmax)isdeterminedbytheinternalcircuitryofaspecificdevice.
ThedifferentialinputvoltageswingisdefinedbythefollowingequationsandFigure12.
Figure12.
DifferentialInputVoltageSwingDXptDVPP=|VIN(true)VIN(inverted)|VPP(min)vVPPvVPP(max)VPP(min)VPP(max)TestInputSwing–ThetypicalACtestinputswingfordifferentialinputsisshownbelow:VPP(ACTest)+|VIN(true)*VIN(inverted)|+750mVCommonModeRange–Themostpositiveofthetrueandinvertedinputvoltages(i.
e.
,theHIGHlevel)mustbewithinthedifferentialHIGHinputcommonmoderange(VIHCMR)forproperoperation.
Torestate,thecommonmoderangeplacesanupperandlowerboundaryonthedifferentialHIGHinputlevel.
TheHIGHinputcommonmoderangeisspecifiedinrelationtotheinputvoltageswing(VPP).
Therelationshipisdeterminedbythedevicetype,sorefertothedevicedatasheetforspecificinformation.
ThedifferentialHIGHinputcommonmoderangeisdefinedbythefollowingequations.
VIHCMR(min)vVIHvVIHCMR(max)VIHCMR(max)varies1:1withVCCVIHCMR(min)varies1:1withVEETheexampleshowninFigure13istypical,andspecifiesthecommonmoderangewithrespecttotheentireVPPrange.
Figure13.
CommonModeRangeVIHCMR(max)VIHforallVPPVIHCMR(min)TheMC100LVEL14exampleshowninFigure14specifiesthecommonmoderangewithrespecttotwoVPPranges.
Figure14.
MC100LVEL14CommonModeRange1.
2V2.
9VVIHforVPP<0.
5VVIHCMR(max)VIHCMR(min)VIHCMR(max)VIHforVPPw0.
5VVIHCMR(min)2.
9V1.
4VAND8090/Dhttp://onsemi.
com8DifferentialInputExample–TherelationshipbetweenVPPandVIHCMRisusedtocompletelydefinevaliddifferentialinputsignals.
ThefollowingMC100EP116exampleisforthe5.
0VPECLmode(VCC=5.
0V,VEE=GND),andillustratesthevalidinputvoltagesforanapplicationwhichusestheminimumandmaximuminputvoltageswingsforthedevice.
NotethatboththeVPPandtheVIHCMRconditionsaresatisfiedforeachofthetwowaveforms.
VIHCMR(min)+2.
0VvVIHvVIHCMR(max)+5.
0VVPP(min)+150mVvVPPvVPP(max)+1200mVThetopwaveforminFigure15representsthehighestpossibleLOWinputvaluewhere:VIL(max)+VIH(max)*VPP(min)+5.
0*0.
15+4.
85VThebottomwaveforminFigure15representsthelowestpossibleLOWinputvaluewhere:VIL(min)+VIH(min)*VPP(max)+2.
0*1.
2+0.
80VFigure15.
MC100EP116DifferentialInputVoltage5.
0V4.
8V3.
0V2.
0V1.
0VVIH=5.
0VVPP=0.
15VVIL=4.
85VVIHCMR(min)VIHCMR(max)VPP=1.
2VVIH=2.
0VVIL=0.
8VDDDDSINGLEENDEDCHARACTERISTICSSectionNote–Thissectionexplainsconceptsthatonlyapplytosingleendedinputsand/oroutputs.
SingleEndedInputs–Manyinputs/outputsaresingleendedinsteadofdifferential,i.
e.
theyhaveasingleinput/outputinsteadofapairoftrueandinvertedinputs/outputs.
SingleEnded50%Points–Singleended50%pointsareusedasameasurementpointforsingleendedinputandoutputsignals.
A50%pointisthesingleendedsignallevelwhichlieshalfwaybetweentheHIGHandLOWinput/outputlevelsasshowninFigure16.
Figure16.
SingleEndedInput/Output50%PointVIHorVOHVILorVOL50%NotefromthefollowingMC100EP116calculationsforthe5.
0VPECLmodethatthe50%pointvoltageisnotafixedvoltage.
The50%pointvarieswiththeinputvoltagerange.
50%Point(max)+[VIH(max))VIL(max)]ń2+(4120)3375)ń2+3748mV50%Point(min)+[VIH(min))VIL(min)]ń2+(3775)3190)ń2+3483mVSingleEndedInputVoltageRange–SingleendedinputHIGHandLOWlevelshaveaboundaryandathresholdasshowninFigure17.
Onceaninputcrossesalogicthreshold,thelogicstateisguaranteedtochangetothenewstate.
Figure17.
SingleEndedInputLogicLevelsVIHmaxHIGHVIHminVILmaxLOWVILminBoundaryThresholdThresholdBoundaryTheMC100EP116exampleshowninFigure18isforthe5.
0VPECLmode.
Figure18.
MC100EP116SingleEndedInputExampleVIHmaxHIGHVIHminVILmaxLOWVILmin4120mV3775mV3375mV3190mVSingleEndedInputTestLevel–TheACtestsingleendedinputswingistypicallygivenbythefollowingequation:VIN(swing)+|VIH*VIL|+750mVAND8090/Dhttp://onsemi.
com9DifferentialInputs(SingleEndedMode)–EitherinputofadifferentialpairmaybeusedindividuallyiftheunusedinputofthedifferentialpairisconnectedtoVBB(theswitchingreferencevoltage).
Theswitchingreferencevoltageisprovidedbymanydifferentialdevices.
Figure19illustratestheuseofthetrueinputasthesingleendedinput.
Notethattheunusedinvertedoutputisterminatedinthesamefashionasthetrueoutput.
Figure19.
DifferentialInputinSingleEndedModeVIHVIL50%50%VOHVOLD1D1VBBQ1Q1UseQ1TerminationTheswitchingreferencevoltageprovidesaswitchingpointthatisapproximatelyhalfwaybetweentheHIGHandLOWlevels.
Asanexample,theMC100EP116datasheetspecifiesthefollowingswitchingreferencevoltagerangeforthe5.
0VPECLmode.
TheMC100EP11650%pointrangepreviouslycalculatedislistedbelowtheVBBrange.
3475mVvVBBv3675mV3483mVv50%Pointv3748mVNotethattheVBBrangeisveryclosetothe50%pointrange.
Thisistruebecausetheswitchingreferencevoltageprovidesaswitchingpointforadifferentialinputinsingleendedmodethatisanalogoustothe50%pointrangefornormalsingleendedinputs.
TIMINGCHARACTERISTICSOutputRiseandFallTimesECLOutputDevices–TheoutputrisetimeforECLdevicesisthetimerequiredtorisefromthe20%leveltothe80%leveloftheoutputrisingedge.
TheoutputfalltimeforECLdevicesisthetimerequiredtofallfromthe80%leveltothe20%leveloftheoutputfallingedge.
TheoutputriseandfalltimesfordeviceswithECLoutputsisshowninFigure20.
Figure20.
ECLOutputRiseandFallTimestRtFHIGHLOW20%80%NonECLOutputDevices–Refertothetranslatordatasheetsasdifferentconditionsareusedtospecifytheoutputriseandfalltimes.
Onetypeofconditionspecifiesoutputriseandfalltimesbetweenthe10%and90%outputlevels.
Forexample,theriseandfalltimesfortheMC100ELT21PECLtoTTLtranslatorarespecifiedbetweenthe10%and90%outputlevelsasshowninFigure21.
Figure21.
TTLOutputRiseandFallTimePercentagestRtF90%10%HIGHLOWAnothertypeoftestconditionspecifiesnonECLoutputriseandfalltimesbetweenfixedoutputvoltagelevels.
Forexample,theriseandfalltimesfortheMC100EPT21LVPECLtoLVTTLtranslatorarespecifiedbetweenfixedoutputvoltagesof0.
8Vand2.
0VasshowninFigure22.
Figure22.
LVTTLOutputRiseandFallTimeLevelstRtFHIGHLOWVO=2.
0VVO=0.
8VAND8090/Dhttp://onsemi.
com10PropagationDelayRisingEdgePropagation–Therisingedge(LOWtoHIGHtransition)propagationdelay(tPLHortP++)isthetimeneededtopropagateaninputrisingedgetotheoutput.
FallingEdgePropagation–Thefallingedge(HIGHtoLOWtransition)propagationdelay(tPHLortP)isthetimeneededtopropagateaninputfallingedgetotheoutput.
SingleEndedECLDevices–Singleendedpropagationdelayismeasuredbetweenthe50%pointoftheinputrisingorfallingedge,andthe50%pointoftheidenticaloutputedge.
Therearemanytypesofsingleendedpropagationdelayssuchasaclockinputtodataoutput(CLKtoQ)propagationdelay.
SingleendedoutputpropagationdelayisshowninFigure23.
tPLHIN50%OUT50%50%50%Figure23.
SingleEndedPropagationDelaytPHLDifferentialECLDevices–Differentialpropagationdelayismeasuredbetweenthecrosspointoftheinputrisingorfallingedge,andthecrosspointoftheidenticaloutputedge.
Therearemanytypesofdifferentialinput/outputpairssuchasinvertedclockinputstoinverteddataoutputs(CLKtoQ).
DifferentialoutputpropagationdelayisshowninFigure24.
INXptXptFigure24.
DifferentialPropagationDelaytPLHOUTtPHLOUTXptXptINECLInputsandNonECLOutputs–Refertothedevicedatasheetasseveralmethodsareusedtomeasuretheoutputpropagationdelays.
OnemethodspecifiestheoutputpropagationdelaysfromanECLinputcrosspointtoanonECLfixedoutputvoltage.
Forexample,theoutputpropagationdelaysfortheMC100ELT21PECLtoTTLtranslatorarespecifiedbetweentheECLinputcrosspointandaTTLoutputfixedvoltageequalto1.
5VasshowninFigure25.
Figure25.
TTLOutputPropagationDelaytPLHOUT1.
5V1.
5VtPHLININXptXptNonECLInputandECLOutputs–Refertothedevicedatasheetasseveralmethodsareusedtomeasuretheoutputpropagationdelays.
OnemethodspecifiestheoutputpropagationdelaysfromanonECLinputfixedvoltagetoanECLoutput50%point.
Forexample,theoutputpropagationdelaysfortheMC10H352CMOStoPECLtranslatorarespecifiedbetweenaCMOSinputfixedvoltageequaltoVCC/2andtheECLoutput50%pointasshowninFigure26.
Figure26.
CMOSInputPropagationDelaytPLHINVCC/2OUT50%50%tPHLVCC/2AND8090/Dhttp://onsemi.
com11Skew(DutyCycle)Dutycycleskewisalsoreferredtoaspulseskew.
Dutycycleskewismathematicallycalculatedbytakingthedifferencebetweentherisingandfallingedgepropagationdelays.
UnequaltPLHandtPHLvaluescausepulsewidthdistortionwhichaffectsthedutycycle.
DutycycleskewisdefinedbythefollowingequationandFigures27and28foraninputanditsassociatedoutput.
tSKEW(DutyCycle)+|tPLHtPHL|Figure27.
SingleEndedDutyCycleSkewtPLHD2Q250%50%tPHL50%50%IN2tPLHIN2XptOUT2XpttPHLOUT2XptXptFigure28.
DifferentialDutyCycleSkewSkew(WithinDevice)Withindeviceskewisthedifferencebetweentheidenticaltransitionpropagationdelaysofasinglemultipleoutputdevicewithacommoninput.
Itismathematicallycalculatedbyobtainingtherisingandfallingoutputpropagationdelaysforeachindividualoutputofthedevice.
Theminimumoutputpropagationdelayfromthesetofdelaysisthensubtractedfromthemaximumoutputpropagationdelayfromthesetofdelaysasshowninthefollowingequations.
Thehigherofthetwoequationresultsistakenasthewithindeviceskewspecification.
tSKEW(WithinDeviceRisingEdge)+tPLH(maxfromset)*tPLH(minfromset)tSKEW(WithinDeviceFallingEdge)+tPHL(maxfromset)*tPHL(minfromset)TheexampleshowninFigure29definesthewithindeviceskewparametersforadevicewithtwoinputs(D1,D2)andtheirtwoassociatedoutputs(Q1,Q2).
Thewithindeviceskewforthisexamplewouldbethehigherofthefollowingtwoequationresults:tSKEW(WithinDevice)+tPLH2*tPLH1tSKEW(WithinDevice)+tPHL2*tPHL1Figure29.
WithinDeviceSkewtPLH1D1=D2Q150%50%tPHL150%50%tPLH2Q250%tPHL250%Skew(DevicetoDevice)Devicetodeviceskewisthedifferencebetweentheidenticaltransitionpropagationdelaysoftwodeviceswithacommoninputsignalunderidenticaloperatingconditions(identicalambienttemperature,VCC,VEE,etc).
Itismathematicallycalculatedfromdatasheetpropagationdelayvaluesasshownbelow.
tSKEW(DevicetoDevice)+tPLH(max)*tPLH(min)+tPHL(max)*tPHL(min)MinimumInputPulseWidthTheminimuminputpulsewidth(tPW)istheshortestpulsewidththatwillguaranteeproperdeviceoperation.
Itismeasuredbydecreasingthetestsignalgeneratorpulsewidth(i.
e.
,DUTinputpulsewidth)untiltheDUToutputsnolongerfunctionproperly.
Forsingleendedinputs,itismeasuredbetweenthe50%pointsoftheriseandfalltransitionsasshowninFigure30.
Figure30.
SingleEndedInputPulseWidthtPWVIHVIL50%tPWAND8090/Dhttp://onsemi.
com12Fordifferentialinputs,itismeasuredbetweenthecrosspointsoftheriseandfalltransitionsasshowninFigure31.
Figure31.
DifferentialInputPulseWidthtPWVIHVILXptXptSetupandHoldTimeApplicability–Onlysynchronousclockeddeviceshavesetup(tSortSETUP)andhold(tHortHOLD)times.
TimingWindow–Theminimumsetuprequirementandtheminimumholdrequirementspecifythetimingwindowwheretheinputmustnotchangeinordertosuccessfullyclocktheinput.
Thesetuptimespecifiestheleftedgeofthetimingwindow,andtheholdtimespecifiestherightedgeofthewindow.
Bothtimingrequirementsmustbemetinordertosuccessfullyclocktheinput.
MeasurementPoints–Differentialcrosspoints(refertothe"DifferentialCharacteristics"section)andsingleend50%points(refertothe"SingleEndedCharacteristics"section)areusedastimemeasurementpoints.
Notefromthefollowingfiguresthatthe50%pointoftheactiveclockedgeisthetimeoriginofallsetupandholdtimemeasurements.
MinimumSetupTime–Thefollowingistrueofminimumsetuptimes.
Minimumsetuptimesareusuallypositive,andtheyspecifytheminimumlengthoftimethattheinputmustremainunchangedbeforetheactiveclockedgeinordertosuccessfullyclocktheinput.
Positivesetuptimesthereforeindicatethattheleftedgeofthetimingwindowisbeforetheactiveclockedge.
Negativeminimumsetuptimesspecifytheminimumlengthoftimethattheinputmustremainunchangedaftertheactiveclockedgeinordertosuccessfullyclocktheinput.
Negativesetuptimesthereforeindicatethattheleftedgeofthetimingwindowisaftertheactiveclockedge.
MinimumHoldTime–Thefollowingistrueofminimumsetuptimes.
Minimumholdtimesareusuallypositive,andtheyspecifytheminimumlengthoftimethattheinputmustremainunchangedaftertheactiveclockedgeinordertosuccessfullyclocktheinput.
Positiveholdtimesthereforeindicatethattherightedgeofthetimingwindowisaftertheactiveclockedge.
Negativeholdtimesspecifytheminimumlengthoftimethattheinputmustremainunchangedbeforetheactiveclockedgeinordertosuccessfullyclocktheinput.
Negativeholdtimesthereforeindicatethattherightedgeofthetimingwindowisbeforetheactiveclockedge.
TypicalSetupandHoldTimes–Thetypicalsetupandholdtimesspecifiedondatasheetsarenotguaranteed,andtheyareonlyincludedforfailureanalysiscalculations.
Theyaremeasuredbyindependentlymovingtheleftandrightedgesofthetimingwindowabouttheactiveclockedgeuntiltheoutputsnolongerfunctionproperly.
PositiveSetupandPositiveHoldExample–TheMC100EP29datasheetspecifiesthefollowing:Theminimumsetuptimeofpositive100psindicatesthattheleftedgeofthetimingwindowis100psbeforetheactiverisingclockedge.
Theminimumholdtimeofpositive100psspecifiesthattherightedgeofthetimingwindowis100psaftertheactiverisingclockedge.
ThesetuptimerequirementandtheholdtimerequirementwerebothmetintheexampleshowninFigure32,thereforetheLOWtoHIGHoutputtransitionoccursaftertheCLKrisingedgepropagationdelayof420ps.
Notethattheinputcannotchangewithinthetimingwindowof200ps.
Onlyonesideofthedifferentialclocks,inputs,andoutputsareshowninFigure32.
Figure32.
PositiveSetupandPositiveHoldExamplet(ps)CLK50%50%50%INPUTOUTPUTtPHL420ps+100ts(min)+100th(min)AND8090/Dhttp://onsemi.
com13NegativeSetupandPositiveHoldExample–TheMC100E4454BitSerial/ParallelConverterdatasheetspecifiesthefollowing:Theminimumsetuptimeofnegative200psindicatesthattheleftedgeofthetimingwindowis200psaftertheactiverisingclockedge.
Theminimumholdtimeofpositive300psspecifiesthattherightedgeofthetimingwindowis300psaftertheactiverisingclockedge.
ThesetuptimerequirementandtheholdtimerequirementwerebothmetintheexampleshowninFigure33,thereforetheLOWtoHIGHoutputtransitionoccursaftertheCLKrisingedgepropagationdelayof1800ps.
Notethattheinputcannotchangewithinthetimingwindowof100ps.
OnlyoneofthedifferentialclocksanddifferentialinputsisshowninFigure33.
PositiveSetupandNegativeHoldExample–TheMC100E1366BitUniversalUp/DownCounterdatasheetspecifiesthefollowing:Theminimumsetuptimeofpositive400psindicatesthattheleftedgeofthetimingwindowis400psbeforetheactiverisingclockedge.
Theminimumholdtimeofnegative250psspecifiesthattherightedgeofthetimingwindowis250psbeforetheactiverisingclockedge.
ThesetuptimerequirementandtheholdtimerequirementwerebothmetintheexampleshowninFigure34,thereforetheLOWtoHIGHoutputtransitionoccursaftertheCLKrisingedgepropagationdelayof1150ps.
Notethattheinputcannotchangewithinthetimingwindowof150ps.
Figure33.
NegativeSetupandPositiveHoldExamplet(ps)CLK50%50%50%INPUTOUTPUTtPLH1800ps200ts(min)+300th(min)50%Figure34.
PositiveSetupandNegativeHoldExamplet(ps)CLK50%50%50%INPUTOUTPUTtPLH1150ps+400ts(min)250th(min)50%AND8090/Dhttp://onsemi.
com14NegativeSetupandNegativeHoldComment–Theleftedgeofthetimingwindowisthesetupedge,andtherightedgeofthewindowistheholdedge.
Anegativesetuptimewithanegativeholdtimecannotoccurasthisprinciplewouldbeviolated(i.
e.
,theholdedgewouldoccurbeforethesetedge).
SetandResetRecoveryTimeApplicability–OnlydeviceswithaSetinputhavesetrecoverytimes(tSR),andonlydeviceswithaResetinputhaveresetrecoverytimes(tRR).
MeasurementPoints–Differentialcrosspoints(refertothe"DifferentialCharacteristics"section)andsingleend50%points(refertothe"SingleEndedCharacteristics"section)areusedastimemeasurementpoints.
Notefromthefollowingfiguresthatthe50%pointoftheactiveclockedgeisthetimeoriginofallsetandresetrecoverytimemeasurements.
MinimumSetRecoveryTime–ThisparameterdefinestheminimumlengthoftimethatSethastobeinactivebeforeanactiveclockedgeinorderfortheoutputtoenterthenonSetstate.
InthenonSetstate,theoutputisnolongerdependentupontheSetstate.
IntheMC100EP29exampleshowninFigure35,theminimumsetrecoverytimeof150psspecifiesthatthesystemmustbedesignedsothatSettransitionsfromtheactiveHIGHstatetotheinactiveLOWstateatleast150psbeforetheactiverisingclockedge.
Thesetrecoverytimingrequirement(150ps)andtheinputsetuptimerequirement(100ps)werebothmetintheexampleshowninFigure35,thereforetheoutputtransitionsfromtheSetstate(HIGH)totheinputstate(LOW).
Thetransitiontakesplaceafterthespecified420psHIGHtoLOWCLKpropagationdelay.
MinimumResetRecoveryTime–ThisparameterdefinestheminimumlengthoftimethatResethastobeinactivebeforeanactiveclockedgeinorderfortheoutputtoenterthenonResetstate.
InthenonResetstate,theoutputisnolongerdependentupontheResetstate.
IntheMC100EP29exampleshowninFigure36,theminimumresetrecoverytimeof150psspecifiesthatthesystemmustbedesignedsothatResettransitionsfromtheactiveHIGHstatetotheinactiveLOWstateatleast150psbeforetheactiverisingclockedge.
Theresetrecoverytimingrequirement(150ps)andtheinputsetuptimerequirement(100ps)werebothmetintheexampleshowninFigure36,thereforetheoutputtransitionsfromtheSetstate(HIGH)totheinputstate(LOW).
Thetransitiontakesplaceafterthespecified420psHIGHtoLOWCLKpropagationdelay.
Figure35.
SetRecoveryTimeExampletSR(ps)CLK50%50%50%INPUTOUTPUT150tSR(min)tPHL420psSET100ts(min)ts(ps)50%0Figure36.
ResetRecoveryTimeExampletRR(ps)CLK50%50%50%INPUTOUTPUT150tRR(min)tPLH420psRESET100ts(min)ts(min)50%0AND8090/Dhttp://onsemi.
com15TypicalSetandResetRecoveryTimes–Thetypicalsetandresetrecoverytimesspecifiedondatasheetsarenotguaranteed,andtheyareonlyincludedforfailureanalysiscalculations.
TheyaremeasuredbymovingtheactivetoinactiveSetandResettransitionstowardstheactiveclockedgeuntiltheoutputsnolongerentertherespectivenonSetornonResetstate.
JITTERJitterDefinitionJitterisdefinedasthedeviationofanactualedgelocationfromitsideallocation.
Thepossibilityofadatatransmissionerrorincreasesasjitterincreases.
Totaljitterconsistsof"RandomJitter"and"DeterministicJitter"asdescribedinthefollowingsections.
RandomClockJitterRandomjitter(RJ,alsoreferredtoas"nonsystematic"jitter)ischaracterizedbyanunboundedGaussianprobabilitydensityfunctionasshowninFigure37.
RandomjitterisspecifiedondatasheetsasCycletoCycleJitter,andisspecifiedasanRMSvalue(theonesigmavalue).
Thefunctionisdescribedbelow,followedbyadescriptionoftheCycletoCycleJitterspecification.
Thecenterofthesymmetricalprobabilitydistributionisthemeanandrepresentsanidealedgelocation.
Theareaunderthedistributionrepresentstheprobabilitythatanactualedgelocationwillliewithintherangesurroundingtheidealedgelocation.
Forinstance,notefromFigure37thatadistributionrangeofplus/minusonesigmafromthemeanincludes68.
27%ofthetotaldistributionarea.
Thismeansthatthereisa68.
27%probabilitythattheactualedgelocationwillbewithintheplus/minusonesigmawindow.
RJConfidenceLevelsAssigmaincreases,theconfidencethattheactualedgelocationwillliewithinthedistributionrangesurroundingtheidealedgelocationincreases.
Thisiswhythesigmaleveliscommonlyreferredtoasthe"ConfidenceLevel.
"ConfidencelevelspersigmaarespecifiedinTable2where"Sigma"representsthedistributionrangeforonesideofthemean,and"TotalSigma"representsthedistributionrangeforbothsidesofthemean.
Table2.
ConfidenceLevelperSigmaSigmaTotalSigmaConfidenceLevelplus/minus1268.
27%plus/minus2495.
45%plus/minus3699.
73%plus/minus4899.
99%Figure37.
GaussianRandomClockJitterDistributionm$1s=68.
27%m$2s=95.
45%m$3s=99.
73%0.
40.
30.
20.
1321+1+2+3zy0AND8090/Dhttp://onsemi.
com16Asanexample,theNBSG14datasheetspecifiesthetypicalCycletoCycleJitteras0.
5psRMSwhichistheonesigmavalue.
TotalRJTestSetupThetestsetupshowninFigure38isusedtosampleedgelocationsoveralargenumberofperiods,andthenmeasurethetotalRMSrandomjitter.
TotalJitter(RJ)+[PatternGenerator(RJ)]2)[DUT(RJ)]2)[Oscilloscope(RJ)]2Figure38.
TotalRandomJitterTest50%DutyTriggerPatternGeneratorOscilloscopeRJ(RMS)50%DutyDUTCyclePulseCyclePulseTestEquipmentRJTestSetupThetestsetupshowninFigure39isusedtomeasurethetestequipmentRMSrandomjitter.
TestEquipmentJitter(RJ)+[PatternGenerator(RJ)]2)[Oscilloscope(RJ)]2Figure39.
TestEquipmentRandomJitterTest50%DutyCyclePulseTriggerPatternGeneratorOscilloscopeRJ(RMS)DUTRJCalculationTheDUTRMSrandomclockjitterdeterminedwiththefollowingequationisspecifiedasCycletoCycleJitter.
DUT(RJ)+[TotalJitter(RJ)]2*[TestEquipmentJitter(RJ)]2AND8090/Dhttp://onsemi.
com17DeterministicJitterDeterministicjitter(DJ,alsoreferredtoas"data"or"systematic"jitter)ischaracterizedbyboundednon–Gaussianprobabilitydensityfunctions.
DeterministicjitterincludesDutyCycleDistortion(DCD)whichisspecifiedasDutyCycleSkeworPulseSkewondatasheets(refertothe"DutyCycleSkew"section).
Determisticjitterisdefinedforaspecifictestpattern,andisspecifiedasapeaktopeakvalue.
TotalDJTestSetupThetotalDJtestsetupshowninFigure40isusedtoproduceaneyediagram.
Aneyediagramisusefulasitprovidesaqualitativeviewofpeaktopeakdeterministicjitter.
Toformaneyediagram,aPRBS(PseudoRandomBitSequence)signalissenttotheDUTinput,andtheDUToutput(theeyediagram)isobservedontheoscilloscope.
TheNBSG14eyediagraminFigure41wascreatedbyanAdvantestD3186generatinga2311PRBSdatapatternat10.
8Gbps.
TheTektronixTDS8000oscilloscopewithan80E0150GHzsamplingmoduleacquired7000samples.
Thetotaldeterministicjitterrepresentedbythehistogramatthetopleftoftheeyediagramis18.
00pspeaktopeak.
Asdeterministicjitterincreases,theeyecloses(i.
e.
,theeyewidthdecreases)whichincreasestheprobabilityofadatatransmissionerror.
Figure40.
TotalDeterministicJitterTest)Oscilloscope(DJ)TotalJitter(DJ)+PatternGenerator(DJ))DUT(DJ)PRBSTriggerPatternGeneratorOscilloscopeDJ(PP)PRBSDUTFigure41.
TotalDeterministicJitterEyeDiagramAND8090/Dhttp://onsemi.
com18TestEquipmentDJTestSetupThegeneraltestsetupshowninFigure42isusedtomeasurethetestequipmentpeaktopeakdeterministicjitter.
TheNBSG14testequipmentdeterministicjittereyediagraminFigure43wascreatedbytheidenticalpatterngeneratorandoscilloscopesetupthatwasusedtogeneratethetotaldeterministicjittereyediagram.
Thetestequipmentdeterministicjitterrepresentedbythehistogramattheupperrightoftheeyediagramis10.
88pspp.
TestEquipmentJitter(DJ)+PatternGenerator(DJ))Oscilloscope(DJ)Figure42.
TestEquipmentDeterministicJitterTestPRBSTriggerPatternGeneratorOscilloscopeDJ(PP)Figure43.
TestEquipmentDeterministicJitterEyeDiagramDUTDJCalculationTheDUTpeaktopeakdeterministicjitterisdeterminedwiththefollowingequation.
DUT(DJ)+TotalJitter(DJ)*TestEquipmentJitter(DJ)TheDUTpeaktopeakdeterministicjitterfortheaboveNBSG14exampleiscalculatedbelow.
DUT(DJ)+18.
00ps*10.
88ps+7.
12psppAND8090/Dhttp://onsemi.
com19Table3.
SymbolsandAcronymsAAmperesBERBitErrorRateDUTDeviceUnderTestECLEmitterCoupledLogicECLinPSEmitterCoupledLogicinPicoSecondsfMAXMaximumToggleFrequencyfSHIFTMaximumShiftFrequencyGbpsGigabits(109bits)persecondGHzGigahertz(109Hz)JitterPPPeaktoPeakJitterJitterRMSRMSJitterlfpmLinearFeetPerMinuteLVECLinPSLowVoltageEmitterCoupledLogicinPicoSecondsMHzMegahertz(106Hz)NBSGGigaCommProductPrefixnsNanoseconds(109sec)ppPeaktoPeakPRBSPseudoRandomBinarySequencepsPicoseconds(1012sec)RFRadioFrequencySOICSmallOutlineIntegratedCircuittfFallTimethHoldTimetJITTERJittertPHLFallingEdgePropagationDelaytPLHRisingEdgePropagationDelaytPWminMinimumInputPulseWidthtrRiseTimetRRSetandResetRecoverytSSetupTimetSK++InputRisingEdgetoOutputRisingEdgeSkewtSKInputFallingEdgetoOutputFallingEdgeSkewtSKEWSkewVBBSwitchingReferenceVoltageVCCTheMostPositiveSupplyVoltageVCMRCommonModeRangeVEETheMostNegativeSupplyVoltageVIHInputHighVoltageLevelVILInputLowVoltageLevelVINInputVoltageVOHOutputHighVoltageLevelVOLOutputLowVoltageLevelVOUTOutputVoltageVOUTppOutputPeaktoPeakVoltageSwingVPPmin(OrVINPPmin)MinimumInputPeaktoPeakVoltageSwingVPPmax(OrVINPPmax)MaximumInputPeaktoPeakVoltageSwingVTTTerminationVoltageTypicallyEqualtoVCC–2.
0VXptCrosspointoftheTrueandInvertedWaveformsAND8090/Dhttp://onsemi.
com20REFERENCESJohnson,HowardandGraham,Martin.
HighSpeedDigitalDesign:AHandbookofBlackMagic.
PTRPrenticeHall.
NewJersey,1993.
INCITS.
MethodologiesforJitterSpecification.
T11.
2Project1230.
http://www.
t11.
org.
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