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CY7C144AVCY7C006AV3.
3V8K/16K*8AsynchronousDual-PortStaticRAMCypressSemiconductorCorporation198ChampionCourtSanJose,CA95134-1709408-943-2600DocumentNumber:38-06051Rev.
*JRevisedSeptember14,20153.
3V8K/16K*8Dual-PortStaticRAMFeaturesTruedual-portedmemorycellswhichallowsimultaneousaccessofthesamememorylocation8K/16K*8organizations(CY7C144AV/CY7C006AV)0.
35-microncomplementarymetaloxidesemiconductor(CMOS)foroptimumspeed/powerHigh-speedaccess:25nsLowoperatingpowerActive:ICC=115mA(typical)Standby:ISB3=10A(typical)FullyasynchronousoperationAutomaticpower-downExpandabledatabusto16bitsormoreusingMaster/SlavechipselectwhenusingmorethanonedeviceOn-chiparbitrationlogicSemaphoresincludedtopermitsoftwarehandshakingbetweenportsINTflagforport-to-portcommunicationPinselectforMasterorSlaveAvailablein64-pinthinquadflatpack(TQFP)(7C006AVand7C144AV)Pb-freepackagesavailableFunctionalDescriptionForacompletelistofrelateddocumentation,clickhere.
LogicBlockDiagramI/OControlAddressDecodeA0L–A12–13LCELOELR/WLBUSYLI/OControlInterruptSemaphoreArbitrationSEMLINTLM/SA0L–A12–13LTrueDual-PortedRAMArrayA0R–A12–13RCEROERR/WRBUSYRSEMRINTRAddressDecodeA0R–A12–13R[1][1][3][3]R/WLOELI/O0L–I/O7LCELR/WROERI/O0R–I/O7RCER13–14813–14813–1413–14[2][2][2][2]Notes1.
I/O0–I/O7for*8devices.
2.
A0–A12for8Kdevices;A0–A13for16Kdevices.
3.
BUSYisanoutputinmastermodeandaninputinslavemode.
CY7C138AVCY7C139AVCY7C144AVCY7C145AVCY7C006AVCY7C016AVCY7C007AVCY7C017AV3.
3V8K/16K*8AsynchronousDual-PortStaticRAMCY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage2of21ContentsPinConfigurations3SelectionGuide4PinDefinitions4Architecture4FunctionalOverview4ReadandWriteOperations4Interrupts5Busy5Master/Slave5SemaphoreOperation5MaximumRatings6OperatingRange6ElectricalCharacteristics6Capacitance6ACTestLoadsandWaveforms7DataRetentionMode7Timing7SwitchingCharacteristics8SwitchingWaveforms10Non-ContendingRead/Write16InterruptOperationExample16SemaphoreOperationExample16OrderingInformation178K*83.
3VAsynchronousDual-PortSRAM1716K*83.
3VAsynchronousDual-PortSRAM.
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17OrderingCodeDefinitions17PackageDiagrams18Acronyms19DocumentConventions19UnitsofMeasure19DocumentHistoryPage20Sales,Solutions,andLegalInformation21WorldwideSalesandDesignSupport21Products21PSoCSolutions21CypressDeveloperCommunity21TechnicalSupport21CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage3of21PinConfigurationsFigure1.
64-pinTQFPpinout(TopView)Figure2.
64-pinTQFPpinout(TopView)12345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916GNDOERI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RI/O6RGNDVCCA4LA3LA2LA1LA0LGNDBUSYLBUSYRM/SA0RA1RA2RA3RA4RINTLINTRI/O7RA5RA12RA11RA10RA9RA8RA7RA6RNCCERSEMRR/WRVCCOELI/O1LI/O0LA5LA12LA11LA10LA9LA8LA7LA6LNCCELSEMLR/WLCY7C144AV(8K*8)12345678910111213141548474645444342414039383736353433176418631962206121602259235824572556265527542853295230513150324916GNDOERI/O2LI/O3LI/O4LI/O5LI/O6LI/O7LVCCGNDI/O0RI/O1RI/O2RI/O3RI/O4RI/O5RI/O6RGNDVCCA4LA3LA2LA1LA0LGNDBUSYLBUSYRM/SA0RA1RA2RA3RA4RINTLINTRI/O7RA5RA12RA11RA10RA9RA8RA7RA6RA13RCERSEMRR/WRVCCOELI/O1LI/O0LA5LA12LA11LA10LA9LA8LA7LA6LA13LCELSEMLR/WLCY7C006AV(16K*8)CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage4of21ArchitectureTheCY7C144AVandCY7C006AVconsistofanarrayof8Kand16Kwordsof8bitseachofdual-portRAMcells,I/Oandaddresslines,andcontrolsignals(CE,OE,R/W).
Thesecontrolpinspermitindependentaccessforreadsorwritestoanylocationinmemory.
Tohandlesimultaneouswrites/readstothesamelocation,aBUSYpinisprovidedoneachport.
Twointerrupt(INT)pinscanbeutilizedforport-to-portcommunication.
Twosemaphore(SEM)controlpinsareusedforallocatingsharedresources.
WiththeM/Spin,thedevicecanfunctionasamaster(BUSYpinsareoutputs)orasaslave(BUSYpinsareinputs).
Thedevicealsohasanautomaticpower-downfeaturecontrolledbyCE.
Eachportisprovidedwithitsownoutputenablecontrol(OE),whichallowsdatatobereadfromthedevice.
FunctionalOverviewTheCY7C144AVandCY7C006AVarelow-powerCMOS8K/16K*8dual-portstaticRAMs.
Variousarbitrationschemesareincludedonthedevicestohandlesituationswhenmultipleprocessorsaccessthesamepieceofdata.
Twoportsareprovided,permittingindependent,asynchronousaccessforreadsandwritestoanylocationinmemory.
Thedevicescanbeutilizedasstandalone8-bitdual-portstaticRAMsormultipledevicescanbecombinedinordertofunctionasa16-bitorwidermaster/slavedual-portstaticRAM.
AnM/Spinisprovidedforimplementing16-bitorwidermemoryapplicationswithouttheneedforseparatemasterandslavedevicesoradditionaldiscretelogic.
Applicationareasincludeinterprocessor/multiprocessordesigns,communicationsstatusbuffering,anddual-portvideo/graphicsmemory.
Eachporthasindependentcontrolpins:ChipEnable(CE),ReadorWriteEnable(R/W),andOutputEnable(OE).
Twoflagsareprovidedoneachport(BUSYandINT).
BUSYsignalsthattheportistryingtoaccessthesamelocationcurrentlybeingaccessedbytheotherport.
TheInterruptflag(INT)permitscommunicationbetweenportsorsystemsbymeansofamailbox.
Thesemaphoresareusedtopassaflag,ortoken,fromoneporttotheothertoindicatethatasharedresourceisinuse.
Thesemaphorelogiciscomprisedofeightsharedlatches.
Onlyonesidecancontrolthelatch(semaphore)atanytime.
Controlofasemaphoreindicatesthatasharedresourceisinuse.
Anautomaticpower-downfeatureiscontrolledindependentlyoneachportbyaChipSelect(CE)pin.
ReadandWriteOperationsWhenwritingdatamustbesetupforadurationoftSDbeforetherisingedgeofR/Winordertoguaranteeavalidwrite.
AwriteoperationiscontrolledbyeithertheR/Wpin(seeWriteCycleNo.
1waveform)ortheCEpin(seeWriteCycleNo.
2waveform).
SelectionGuideDescriptionCY7C144AV/CY7C006AV-25Maximumaccesstime(ns)25Typicaloperatingcurrent(mA)115TypicalstandbycurrentforISB1(mA)(BothportsTTLlevel)30TypicalstandbycurrentforISB3(A)(BothportsCMOSlevel)10PinDefinitionsLeftPortRightPortDescriptionCELCERChipenableR/WLR/WRRead/WriteenableOELOEROutputenableA0L–A12/13LA0R–A12/13RAddress(A0–A12for8Kdevices;A0–A13for16Kdevices)I/O0L–I/O7LI/O0R–I/O7RDatabusinput/output(I/O0–I/O7for*8devices)SEMLSEMRSemaphoreEnableINTLINTRInterruptflagBUSYLBUSYRBusyflagM/SMasterorSlaveselectVCCPowerGNDGroundNCNoconnectCY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage5of21Requiredinputsfornon-contentionoperationsaresummarizedinTable1onpage16.
Ifalocationisbeingwrittentobyoneportandtheoppositeportattemptstoreadthatlocation,aport-to-portflowthroughdelaymustoccurbeforethedataisreadontheoutput;otherwisethedatareadisnotdeterministic.
DatawillbevalidontheporttDDDafterthedataispresentedontheotherport.
Whenreadingthedevice,theusermustassertboththeOEandCEpins.
DatawillbeavailabletACEafterCEortDOEafterOEisasserted.
Iftheuserwishestoaccessasemaphoreflag,thentheSEMpinmustbeassertedinsteadoftheCEpinandOEmustalsobeasserted.
InterruptsTheuppertwomemorylocationsmaybeusedformessagepassing.
Thehighestmemorylocation(1FFFfortheCY7C144AVand3FFFfortheCY7C006AV)isthemailboxfortherightportandthesecond-highestmemorylocation(1FFEfortheCY7C144AVand3FFEfortheCY7C006AV)isthemailboxfortheleftport.
Whenoneportwritestotheotherport'smailbox,aninterruptisgeneratedtotheowner.
Theinterruptisresetwhentheownerreadsthecontentsofthemailbox.
Themessageisuserdefined.
Eachportcanreadtheotherport'smailboxwithoutresettingtheinterrupt.
Theactivestateofthebusysignal(toaport)preventstheportfromsettingtheinterrupttothewinningport.
Also,anactivebusytoaportpreventsthatportfromreadingitsownmailboxand,thus,resettingtheinterrupttoit.
Ifanapplicationdoesnotrequiremessagepassing,donotconnecttheinterruptpintotheprocessor'sinterruptrequestinputpin.
TheoperationoftheinterruptsandtheirinteractionwithBusyaresummarizedinTable2onpage16.
BusyTheCY7C144AVandCY7C006AVprovideon-chiparbitrationtoresolvesimultaneousmemorylocationaccess(contention).
Ifbothports'CEsareassertedandanaddressmatchoccurswithintPSofeachother,thebusylogicwilldeterminewhichporthasaccess.
IftPSisviolated,oneportwilldefinitelygainpermissiontothelocation,butitisnotpredictablewhichportwillgetthatpermission.
BUSYwillbeassertedtBLAafteranaddressmatchortBLCafterCEistakenLOW.
Master/SlaveAnM/Spinisprovidedinordertoexpandthewordwidthbyconfiguringthedeviceaseitheramasteroraslave.
TheBUSYoutputofthemasterisconnectedtotheBUSYinputoftheslave.
Thiswillallowthedevicetointerfacetoamasterdevicewithnoexternalcomponents.
WritingtoslavedevicesmustbedelayeduntilaftertheBUSYinputhassettled(tBLCortBLA),otherwise,theslavechipmaybeginawritecycleduringacontentionsituation.
WhentiedHIGH,theM/Spinallowsthedevicetobeusedasamasterand,therefore,theBUSYlineisanoutput.
BUSYcanthenbeusedtosendthearbitrationoutcometoaslave.
SemaphoreOperationTheCY7C144AVandCY7C006AVprovideeightsemaphorelatches,whichareseparatefromthedual-portmemorylocations.
Semaphoresareusedtoreserveresourcesthataresharedbetweenthetwoports.
Thestateofthesemaphoreindicatesthataresourceisinuse.
Forexample,iftheleftportwantstorequestagivenresource,itsetsalatchbywritingazerotoasemaphorelocation.
Theleftportthenverifiesitssuccessinsettingthelatchbyreadingit.
Afterwritingtothesemaphore,SEMorOEmustbedeassertedfortSOPbeforeattemptingtoreadthesemaphore.
ThesemaphorevaluewillbeavailabletSWRD+tDOEaftertherisingedgeofthesemaphorewrite.
Iftheleftportwassuccessful(readsazero),itassumescontrolofthesharedresource,otherwise(readsaone)itassumestherightporthascontrolandcontinuestopollthesemaphore.
Whentherightsidehasrelinquishedcontrolofthesemaphore(bywritingaone),theleftsidewillsucceedingainingcontrolofthesemaphore.
Iftheleftsidenolongerrequiresthesemaphore,aoneiswrittentocancelitsrequest.
SemaphoresareaccessedbyassertingSEMLOW.
TheSEMpinfunctionsasachipselectforthesemaphorelatches(CEmustremainHIGHduringSEMLOW).
A0–2representsthesemaphoreaddress.
OEandR/Wareusedinthesamemannerasanormalmemoryaccess.
Whenwritingorreadingasemaphore,theotheraddresspinshavenoeffect.
Whenwritingtothesemaphore,onlyI/O0isused.
Ifazeroiswrittentotheleftportofanavailablesemaphore,aonewillappearatthesamesemaphoreaddressontherightport.
Thatsemaphorecannowonlybemodifiedbythesideshowingzero(theleftportinthiscase).
Iftheleftportnowrelinquishescontrolbywritingaonetothesemaphore,thesemaphorewillbesettooneforbothsides.
However,iftherightporthadrequestedthesemaphore(writtenazero)whiletheleftporthadcontrol,therightportwouldimmediatelyownthesemaphoreassoonastheleftportreleasedit.
Table3onpage16showssamplesemaphoreoperations.
Whenreadingasemaphore,alldatalinesoutputthesemaphorevalue.
Thereadvalueislatchedinanoutputregistertopreventthesemaphorefromchangingstateduringawritefromtheotherport.
IfbothportsattempttoaccessthesemaphorewithintSPSofeachother,thesemaphorewilldefinitelybeobtainedbyonesideortheother,butthereisnoguaranteewhichsidewillcontrolthesemaphore.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage6of21MaximumRatingsExceedingmaximumratings[4]mayimpairtheusefullifeofthedevice.
Theseuserguidelinesarenottested.
Storagetemperature65°Cto+150°CAmbienttemperaturewithPowerapplied55°Cto+125°CSupplyvoltagetogroundpotential0.
5Vto+4.
6VDCvoltageappliedtoOutputsinHighZstate0.
5VtoVCC+0.
5VDCinputvoltage[5]0.
5VtoVCC+0.
5VOutputcurrentintooutputs(LOW)20mAStaticdischargevoltage2001VLatch-upcurrent200mAOperatingRangeRangeAmbientTemperatureVCCCommercial0°Cto+70°C3.
3V300mVElectricalCharacteristicsOvertheOperatingRangeParameterDescriptionCY7C144AV/CY7C006AV-25UnitMinTypMaxVOHOutputHIGHvoltage(VCC=3.
3V)2.
4––VVOLOutputLOWvoltage–0.
4VVIHInputHIGHvoltage2.
0–VVILInputLOWvoltage–0.
8VIOZOutputleakagecurrent–1010AICCOperatingcurrent(VCC=Max.
,IOUT=0mA)OutputsDisabledCommercial–115165mAISB1Standbycurrent(BothportsTTLlevel)CEL&CERVIH,f=fMAX[6]Commercial–3040mAISB2Standbycurrent(OneportTTLlevel)CEL|CERVIH,f=fMAX[6]Commercial–6595mAISB3Standbycurrent(BothportsCMOSlevel)CEL&CERVCC–0.
2V,f=0[6]Commercial–10500AISB4Standbycurrent(OneportCMOSlevel)CEL|CERVIH,f=fMAX[6]Commercial–6080mACapacitanceParameter[7]DescriptionTestConditionsMaxUnitCINInputcapacitanceTA=25°C,f=1MHz,VCC=3.
3V10pFCOUTOutputcapacitance10pFNotes4.
TheVoltageonanyinputorI/Opincannotexceedthepowerpinduringpower-up.
5.
PulsewidthtRCafterVCCreachestheminimumoperatingvoltage(3.
0Volts).
ACTestLoadsandWaveformsFigure3.
ACTestLoadsandWaveforms3.
0VGND90%90%10%3ns3ns10%ALLINPUTPULSES(a)NormalLoad(Load1)R1=5903.
3VOUTPUTR2=435C=30pFVTH=1.
4VOUTPUTC=30pF(b)ThéveninEquivalent(Load1)(c)Three-StateDelay(Load2)R1=590R2=4353.
3VOUTPUTC=5pFRTH=250includingscopeandjig)(UsedfortLZ,tHZ,tHZWE&tLZWETimingFigure4.
TimingParameterTestConditions[8]MaxUnitICCDR1@VCCDR=2V50ADataRetentionMode3.
0V3.
0VVCC2.
0VVCCtoVCC–0.
2VVCCCEtRCVIHNote8.
CE=VCC,VIN=GNDtoVCC,TA=25°C.
Thisparameterisguaranteedbutnottested.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage8of21SwitchingCharacteristicsOvertheOperatingRangeParameter[9]DescriptionCY7C144AV/CY7C006AVUnit-25MinMaxREADCYCLEtRCReadcycletime25–nstAAAddresstodatavalid–25nstOHAOutputholdfromaddresschange3–nstACE[10]CELOWtodatavalid–25nstDOEOELOWtodatavalid–13nstLZOE[11,12]OELowtoLowZ3–nstHZOE[11,12]OEHIGHtoHighZ–15nstLZCE[11,12]CELOWtoLowZ3–nstHZCE[11,12]CEHIGHtoHighZ–15nstPUCELOWtopower-up0–nstPDCEHIGHtopower-down–25nsWRITECYCLEtWCWritecycletime25–nstSCE[10]CELOWtowriteend20–nstAWAddressvalidtowriteend20–nstHAAddressholdfromwriteend0–nstSA[10]Addressset-uptowritestart0–nstPWEWritepulsewidth20–nstSDDataset-uptowriteend15–nstHDDataholdfromwriteend0–nstHZWER/WLOWtoHighZ–15nstLZWER/WHIGHtoLowZ3–nstWDD[13]Writepulsetodatadelay–50nstDDD[13]Writedatavalidtoreaddatavalid–35nsNotes9.
Testconditionsassumesignaltransitiontimeof3nsorless,timingreferencelevelsof1.
5V,inputpulselevelsof0to3.
0V,andoutputloadingofthespecifiedIOI/IOHand30-pFloadcapacitance.
10.
ToaccessRAM,CE=L,SEM=H.
Toaccesssemaphore,CE=HandSEM=L.
EitherconditionmustbevalidfortheentiretSCEtime.
11.
Atanygiventemperatureandvoltageconditionforanygivendevice,tHZCEislessthantLZCEandtHZOEislessthantLZOE.
12.
TestconditionsusedareLoad3.
13.
Forinformationonport-to-portdelaythroughRAMcellsfromwritingporttoreadingport,refertoReadTimingwithBusywaveform.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage9of21BUSYTIMINGtBLABUSYLOWfromaddressmatch–20nstBHABUSYHIGHfromaddressmismatch–20nstBLCBUSYLOWfromCELOW–20nstBHCBUSYHIGHfromCEHIGH–17nstPSPortset-upforpriority5–nstWBR/WHIGHafterBUSY(Slave)0–nstWHR/WHIGHafterBUSYHIGH(Slave)17–nstBDD[14]BUSYHIGHtodatavalid–25nsINTERRUPTTIMINGtINSINTsettime–20nstINRINTresettime–20nsSEMAPHORETIMINGtSOPSEMflagupdatepulse(OEorSEM)12–nstSWRDSEMflagwritetoreadtime5–nstSPSSEMflagcontentionwindow5–nstSAASEMaddressaccesstime–25nsSwitchingCharacteristics(continued)OvertheOperatingRangeParameter[9]DescriptionCY7C144AV/CY7C006AVUnit-25MinMaxNote14.
tBDDisacalculatedparameterandisthegreateroftWDD–tPWE(actual)ortDDD–tSD(actual).
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage10of21SwitchingWaveformsFigure5.
ReadCycleNo.
1(EitherPortAddressAccess)[15,16,17]Figure6.
ReadCycleNo.
2(EitherPortCE/OEAccess)[15,18,19]Figure7.
ReadCycleNo.
3(EitherPort)[15,17,18,19]tRCtAAtOHADATAVALIDPREVIOUSDATAVALIDDATAOUTADDRESStOHAtACEtLZOEtDOEtHZOEtHZCEDATAVALIDtLZCEtPUtPDISBICCDATAOUTOECECURRENTDATAOUTtRCADDRESStAAtOHACEtLZCEtABEtHZCEtACEtLZCENotes15.
R/WisHIGHforreadcycles.
16.
DeviceiscontinuouslyselectedCE=VIL.
Thiswaveformcannotbeusedforsemaphorereads.
17.
OE=VIL.
18.
AddressvalidpriortoorcoincidentwithCEtransitionLOW.
19.
ToaccessRAM,CE=VIL,SEM=VIH.
Toaccesssemaphore,CE=VIH,SEM=VIL.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage11of21Figure8.
WriteCycleNo.
1(R/WControlledTiming)[20,21,22,23]Figure9.
WriteCycleNo.
2(CEControlledTiming)[20,21,22,27]SwitchingWaveforms(continued)tAWtWCtPWEtHDtSDtHACER/WOEDATAOUTDATAINADDRESStHZOEtSAtHZWEtLZWE[24][24][23][25]Note26Note26tAWtWCtSCEtHDtSDtHACER/WDATAINADDRESStSA[25]Notes20.
R/WmustbeHIGHduringalladdresstransitions.
21.
Awriteoccursduringtheoverlap(tSCEortPWE)ofaLOWCEorSEM.
22.
tHAismeasuredfromtheearlierofCEorR/Wor(SEMorR/W)goingHIGHattheendofwritecycle.
23.
IfOEisLOWduringaR/Wcontrolledwritecycle,thewritepulsewidthmustbethelargeroftPWEor(tHZWE+tSD)toallowtheI/OdriverstoturnoffanddatatobeplacedonthebusfortherequiredtSD.
IfOEisHIGHduringanR/Wcontrolledwritecycle,thisrequirementdoesnotapplyandthewritepulsecanbeasshortasthespecifiedtPWE.
24.
Transitionismeasured500mVfromsteadystatewitha5-pFload(includingscopeandjig).
Thisparameterissampledandnot100%tested.
25.
ToaccessRAM,CE=VIL,SEM=VIH.
26.
Duringthisperiod,theI/Opinsareintheoutputstate,andinputsignalsmustnotbeapplied.
27.
IftheCEorSEMLOWtransitionoccurssimultaneouslywithoraftertheR/WLOWtransition,theoutputsremaininthehigh-impedancestate.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage12of21Figure10.
SemaphoreReadafterWriteTiming,eitherSide[28]Figure11.
TimingDiagramofSemaphoreContention[29,30,31]SwitchingWaveforms(continued)tSOPtSAAVALIDADRESSVALIDADRESStHDDATAINVALIDDATAOUTVALIDtOHAtAWtHAtACEtSOPtSCEtSDtSAtPWEtSWRDtDOEWRITECYCLEREADCYCLEOER/WI/O0SEMA0–A2MATCHtSPSA0L–A2LMATCHR/WLSEMLA0R–A2RR/WRSEMRNotes28.
CE=HIGHforthedurationoftheabovetiming(bothwriteandreadcycle).
29.
I/O0R=I/O0L=LOW(requestsemaphore);CER=CEL=HIGH.
30.
Semaphoresarereset(availabletobothports)atcyclestart.
31.
IftSPSisviolated,thesemaphorewilldefinitelybeobtainedbyonesideortheother,butwhichsidewillgetthesemaphoreisunpredictable.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage13of21Figure12.
TimingDiagramofReadwithBUSY(M/S=HIGH)[32]Figure13.
WriteTimingwithBusyInput(M/S=LOW)SwitchingWaveforms(continued)VALIDtDDDtWDDMATCHMATCHR/WRDATAINRDATAOUTLtWCADDRESSRtPWEVALIDtSDtHDADDRESSLtPStBLAtBHAtBDDBUSYLtPWER/WBUSYtWBtWHNote32.
CEL=CER=LOW.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage14of21Figure14.
BusyTimingDiagramNo.
1(CEArbitration)[33]Figure15.
BusyTimingDiagramNo.
2(AddressArbitration)[33]SwitchingWaveforms(continued)ADDRESSMATCHtPStBLCtBHCADDRESSMATCHtPStBLCtBHCCERValidFirst:ADDRESSL,RBUSYRCELCERBUSYLCERCELADDRESSL,RCELValidFirst:ADDRESSMATCHtPSADDRESSLBUSYRADDRESSMISMATCHtRCortWCtBLAtBHAADDRESSRADDRESSMATCHADDRESSMISMATCHtPSADDRESSLBUSYLtRCortWCtBLAtBHAADDRESSRRightAddressValidFirst:LeftAddressValidFirstNote33.
IftPSisviolated,thebusysignalwillbeassertedononesideortheother,butthereisnoguaranteetowhichsideBUSYwillbeasserted.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage15of21Figure16.
InterruptTimingDiagramsSwitchingWaveforms(continued)WRITE1FFF/3FFF(SeeFunctionalDescription)tWCRightSideClearsINTR:tHAREAD1FFF/3FFFtRCtINRWRITE1FFE/3FFE(SeeFunctionalDescription)tWCRightSideSetsINTL:LeftSideSetsINTR:LeftSideClearsINTL:READ1FFE/3FFEtINRtRCADDRESSRCELR/WLINTLOELADDRESSRR/WRCERINTLADDRESSRCERR/WRINTROERADDRESSLR/WLCELINTRtINStHAtINS(SeeFunctionalDescription)(SeeFunctionalDescription)[34][35][35][35][34][35]Notes34.
tHAdependsonwhichenablepin(CELorR/WL)isdeassertedfirst.
35.
tINSortINRdependsonwhichenablepin(CELorR/WL)isassertedlast.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage16of21Non-ContendingRead/WriteInterruptOperationExampleSemaphoreOperationExampleTable1.
Non-ContendingRead/WriteInputsOutputsOperationCER/WOESEMI/O0–I/O7HXXHHighZDeselected:Power-downHHLLDataoutReaddatainsemaphoreflagXXHXHighZI/OlinesdisabledHXLDatainWriteintosemaphoreflagLHLHDataoutReadLLXHDatainWriteLXXLNotallowedTable2.
InterruptOperationExample(assumesBUSYL=BUSYR=HIGH)FunctionLeftPortRightPortR/WLCELOELA0L–13LINTLR/WRCEROERA0R–13RINTRSetRightINTRflagLLX1FFF/3FFF[36]XXXXXL[37]ResetRightINTRflagXXXXXXLL1FFF/3FFF[36]H[38]SetLeftINTLflagXXXXL[38]LLX1FFE/3FFE[36]XResetLeftINTLflagXLL1FFE/3FFE[36]H[37]XXXXXTable3.
SemaphoreOperationExampleFunctionI/O0–I/O7LeftI/O0–I/O7RightStatusNoaction11SemaphorefreeLeftportwrites0tosemaphore01LeftPorthassemaphoretokenRightportwrites0tosemaphore01Nochange.
RightsidehasnowriteaccesstosemaphoreLeftportwrites1tosemaphore10RightportobtainssemaphoretokenLeftportwrites0tosemaphore10Nochange.
LeftporthasnowriteaccesstosemaphoreRightportwrites1tosemaphore01LeftportobtainssemaphoretokenLeftportwrites1tosemaphore11SemaphorefreeRightportwrites0tosemaphore10RightporthassemaphoretokenRightportwrites1tosemaphore11SemaphorefreeLeftportwrites0tosemaphore01LeftporthassemaphoretokenLeftportwrites1tosemaphore11SemaphorefreeNotes36.
SeeFunctionalDescriptionforspecificaddressesbydevicepartnumber.
37.
IfBUSYL=L,thennochange.
38.
IfBUSYR=L,thennochange.
CY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage17of21OrderingInformationOrderingCodeDefinitions8K*83.
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*JPage19of21AcronymsDocumentConventionsUnitsofMeasureAcronymDescriptionCEChipEnableCMOSComplementaryMetalOxideSemiconductorI/OInput/OutputOEOutputEnableSRAMStaticRandomAccessMemoryTQFPThinQuadFlatPackTTLTransistor-TransistorLogicSymbolUnitofMeasure°CdegreeCelsiusMHzmegahertzAmicroamperemAmilliamperemmmillimetermVmillivoltnsnanosecondohm%percentpFpicofaradVvoltWwattCY7C144AVCY7C006AVDocumentNumber:38-06051Rev.
*JPage20of21DocumentHistoryPageDocumentTitle:CY7C144AV/CY7C006AV,3.
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ECNNo.
IssueDateOrig.
ofChangeDescriptionofChange**11020312/02/01SZVChangefromSpecnumber:38-00837to38-06051*A12230112/27/02RBIUpdatedMaximumRatings(AddedPoweruprequirementstoMaximumRatingsInformation).
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*F335206708/23/2011ADMUUpdatedFeatures.
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Updatedtonewtemplate.
*G340209110/12/2011ADMUUpdatedOrderingInformation(RemovedprunedpartCY7C144AV-25AC).
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*H369918508/01/2012SMCHUpdatedtitletoreadas"CY7C144AV/CY7C006AV,3.
3V8K/16K*8AsynchronousDual-PortStaticRAM".
UpdatedSwitchingCharacteristics(RemovedtheNote"TestconditionsusedareLoad3.
"anditsreference,removedtheNote"TestconditionsusedareLoad2.
"anditsreference,removedtheNote"Thisparameterisguaranteedbutnottested.
Forinformationonport-to-portdelaythroughRAMcellsfromwritingporttoreadingport,refertoReadTimingwithBusywaveform.
"anditsreference).
UpdatedSwitchingWaveforms(UpdatedFigure14).
*I458166711/27/2014SMCHUpdatedFunctionalDescription:Added"Foracompletelistofrelateddocumentation,clickhere.
"attheend.
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*J491879109/14/2015VINIUpdatedPackageDiagrams:spec51-85046–Changedrevisionfrom*Fto*G.
Updatedtonewtemplate.
CompletingSunsetReview.
DocumentNumber:38-06051Rev.
*JRevisedSeptember14,2015Page21of21Allproductsandcompanynamesmentionedinthisdocumentmaybethetrademarksoftheirrespectiveholders.
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