systemwww.168dy.cc

TL16C752Cwww.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014TL16C752C–DualUARTWith64-ByteFIFOCheckforSamples:TL16C752C1FEATURESST16C654/654DPinCompatibleWithCompleteStatusReportingCapabilitiesinAdditionalEnhancements(PFBPackageOnly)BothNormalandSleepModeSupportsupto:LineBreakGenerationandDetection–24-MHzCrystalInputClock(1.
5Mbps)InternalTestandLoopbackCapabilities–48-MHzOscillatorInputClock(3Mbps)forFullyPrioritizedInterruptSystemControls5-VOperationModemControlFunctions(CTS,RTS,DSR,–32-MHzOscillatorInputClock(2Mbps)forDTR,RI,andCD)3.
3-VOperationInfraredDataAssociation(IrDA)Capability–24-MHzInputClock(1.
5Mbps)for2.
5-VOperationDESCRIPTIONTheTL16C752Cisadualuniversalasynchronous–16-MHzInputClock(1Mbps)for1.
8-Vreceivertransmitter(UART)with64-byteFIFOs,Operationautomatichardwareandsoftwareflowcontrol,and64-ByteTransmitFIFOdataratesupto3Mbps.
Itincorporatesthe64-ByteReceiveFIFOWithErrorFlagsfunctionalityoffourUARTs,eachUARThavingitsownregistersetandFIFOs.
ThefourUARTsshareProgrammableandSelectableTransmitandonlythedatabusinterfaceandclocksource,ReceiveFIFOTriggerLevelsforDMAandotherwisetheyoperateindependently.
AnothernameInterruptGenerationfortheUARTfunctionisasynchronousProgrammableReceiveFIFOTriggerLevelsforcommunicationselement(ACE),andthesetermsareSoftware/HardwareFlowControlusedinterchangeably.
ThebulkofthisdocumentSoftware/HardwareFlowControldescribesthebehaviorofeachACE,withtheunderstandingthatfoursuchdevicesare–ProgrammableXon/XoffCharactersincorporatedintotheTL16C752C.
TheTL16C752C–ProgrammableAuto-RTSandAuto-CTSoffersenhancedfeatures.
IthasatransmissionOptionalDataFlowResumebyXonAnycontrolregister(TCR)thatstoresreceivedFIFOthresholdleveltostartorstoptransmissionduringCharacterhardwareandsoftwareflowcontrol.
WiththeFIFODMASignalingCapabilityforBothReceivedRDYregister,thesoftwaregetsthestatusofandTransmittedDataonPNPackageTXRDY/RXRDYforallfourportsinoneaccess.
On-RS-485ModeSupportchipstatusregistersprovidetheuserwitherrorindications,operationalstatus,andmodeminterfaceSupport1.
8-V,2.
5-V,3.
3-V,or5-VSupplycontrol.
SysteminterruptsmaybetailoredtomeetCharacterizedforOperationFrom–40°Ctouserrequirements.
Aninternalloopbackcapability85°C,AvailableinCommercialandIndustrialallowsonboarddiagnostics.
TemperatureGradesEachUARTtransmitsdatasenttoitfromtheSoftware-SelectableBaud-RateGeneratorperipheral8-bitbusontheTXsignalandreceivesPrescalableProvidesAdditionalDivide-by-4charactersontheRXsignal.
CharacterscanbeFunctionprogrammedtobe5,6,7,or8bits.
TheUARThasaProgrammableSleepMode64-bytereceiveFIFOandtransmitFIFOandcanbeprogrammedtointerruptatdifferenttriggerlevels.
ProgrammableSerialInterfaceCharacteristicsTheUARTgeneratesitsowndesiredbaudrate–5-,6-,7-,or8-BitCharactersbaseduponaprogrammabledivisoranditsinput–Even,Odd,orNoParityBitGenerationandclock.
Itcantransmiteven,odd,ornoparityand1-,1.
5-,or2-stopbits.
Thereceivercandetectbreak,Detectionidleorframingerrors,FIFOoverflow,andparity–1-,1.
5-,or2-StopBitGenerationerrors.
ThetransmittercandetectFIFOunderflow.
FalseStartBitDetection1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2008–2014,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
TL16C752CSLLS646B–MARCH2008–REVISEDJANUARY2014www.
ti.
comDESCRIPTION(CONTINUED)TheUARTalsocontainsasoftwareinterfaceformodemcontroloperations,andsoftwareflowcontrolandhardwareflowcontrolcapabilities.
TheTL16C752Cisavailableina32-pinQFN(RHB)packageand48-pinQFP(PFB)package.
PFBPACKAGE(TOPVIEW)N.
C.
–Nointernalconnection2SubmitDocumentationFeedbackCopyright2008–2014,TexasInstrumentsIncorporatedProductFolderLinks:TL16C752CTL16C752Cwww.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014RHBPACKAGE(TOPVIEW)NOTE:The32-pinRHBpackagedoesnotprovideaccesstoDSRA,DSRB,RIA,RIB,CDA,andCDBinputsorOPA,OPB,RXRDYA,RXRDYB,andTXRDYAoutputs.
Table1.
TerminalFunctionsTERMINALNO.
I/ODESCRIPTIONNAMEPFBRHBAddressbit0select.
Internalregistersaddressselection.
RefertoFigure24forRegisterA02818IAddressMap.
Addressbit1select.
Internalregistersaddressselection.
RefertoFigure24forRegisterA12717IAddressMap.
Addressbit2select.
Internalregistersaddressselection.
RefertoFigure24forRegisterA22616IAddressMap.
Carrierdetect(activelow).
TheseinputsareassociatedwithindividualUARTchannelsACDA,CDB40,16IthroughB.
Alowonthesepinsindicatesthatacarrierhasbeendetectedbythemodemforthatchannel.
ChipselectAandB(activelow).
ThesepinsenabledatatransfersbetweentheuserCPUandtheTL16C752Cforthechannelorchannelsaddressed.
IndividualUARTCSA,CSB10,117,8Isections(A,B,C,D)areaddressedbyprovidingalowontherespectiveCSAthroughCSDpin.
Cleartosend(activelow).
TheseinputsareassociatedwithindividualUARTchannelsAandB.
AlowontheCTSpinsindicatesthemodemordatasetisreadytoacceptCTSA,CTSB38,2325,15ItransmitdatafromtheTL16C752C.
StatuscanbecheckedbyreadingMSR[4].
ThesepinsonlyaffectthetransmitandreceiveoperationswhenautoCTSfunctionisenabledthroughtheenhancedfeatureregister(EFR[7]),forhardwareflowcontroloperation.
Databus(bidirectional).
Thesepinsarethe8-bit,3-statedatabusfortransferringD0–D4,44–48,27–31I/OinformationtoorfromthecontrollingCPU.
D0istheleastsignificantbitandthefirstdataD5–D71–332,1,2bitinatransmitorreceiveserialdatastream.
Datasetready(activelow).
TheseinputsareassociatedwithindividualUARTchannelsDSRA,DSRB39,20IAthroughB.
AlowonthesepinsindicatesthemodemordatasetispoweredonandisreadyfordataexchangewiththeUART.
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comTable1.
TerminalFunctions(continued)TERMINALNO.
I/ODESCRIPTIONNAMEPFBRHBDataterminalready(activelow).
TheseoutputsareassociatedwithindividualUARTchannelsAthroughB.
AlowonthesepinsindicatesthattheTL16C752Cispoweredonandready.
Thesepinscanbecontrolledthroughthemodemcontrolregister.
Writinga1DTRA,DTRB34,3522,23OtoMCR[0]setstheDTRoutputtolow,enablingthemodem.
Theoutputofthesepinsishighafterwritinga0toMCR[0],orafterareset.
ThesepinscanalsobeusedintheRS-485modetocontrolanexternalRS-485driverortransceiver.
GND1712PwrPowersignalandpowergroundInterruptAandB(activehigh).
Thesepinsprovideindividualchannelinterrupts,INTA-D.
INTADareenabledwhenMCR[3]issettoa1,interruptsareenabledintheinterruptINTA,INTB30,2920,19Oenableregister(IER)andwhenaninterruptconditionexists.
Interruptconditionsinclude:receivererrors,availablereceiverbufferdata,transmitbufferempty,orwhenamodemstatusflagisdetected.
INTADareinthehigh-impedancestateafterreset.
Readinput(activelowstrobe).
AvalidlowlevelonIORloadsthecontentsofaninternalIOR1913IregisterdefinedbyaddressbitsA0throughA2ontotheTL16C752Cdatabus(D0throughD7)foraccessbyanexternalCPU.
Writeinput(activelowstrobe).
AvalidlowlevelonIOWtransfersthecontentsoftheIOW1511Idatabus(D0throughD7)fromtheexternalCPUtoaninternalregisterthatisdefinedbyaddressbitsA0throughA2.
12,24NCNointernalconnection35,37Userdefinedoutputs.
ThisfunctionisassociatedwithindividualchannelsAandB.
ThestateofthesepinsisdefinedbytheuserthroughthesoftwaresettingsoftheMCRregister,bit3.
INTA-BaresettoactivemodeandOPtoalogic0whentheMCR-3issetOPA,OPB32,9Otoalogic1.
INTA-Baresettothe3-statemodeandOPtoalogic1whenMCR-3issettoalogic0.
Seebit3,modemcontrolregister(MCRbit3).
Theoutputofthesetwopinsishighafterreset.
Reset.
RESETresetstheinternalregistersandalltheoutputs.
TheUARTtransmitterRESET3624Ioutputandthereceiverinputaredisabledduringresettime.
Forinitializationdetails,seeTL16C752Cexternalresetconditions.
RESETisanactivehighinput.
Ringindicator(activelow).
TheseinputsareassociatedwithindividualUARTchannelsAandB.
AlogiclowonthesepinsindicatesthemodemhasreceivedaringingsignalfromRIA,RIB,41,21Ithetelephoneline.
Alow-to-hightransitionontheseinputpinsgeneratesamodemstatusinterrupt,ifenabled.
Thestateoftheseinputsisreflectedinthemodemstatusregister(MSR).
Requesttosend(activelow).
TheseoutputsareassociatedwithindividualUARTchannelsAthroughD.
AlowontheRTSpinsindicatesthetransmitterhasdatareadyandwaitingtosend.
Writinga1inthemodemcontrolregister(MCR[1])setsthesepinsRTSA,RTSB33,2221,14Otolow,indicatingdataisavailable.
Afterareset,thesepinsaresetto1.
Thesepinsonlyaffectthetransmitandreceiveoperationwhenauto-RTSfunctionisenabledthroughtheenhancedfeatureregister(EFR[6]),forhardwareflowcontroloperation.
Receivedatainput.
TheseinputsareassociatedwithindividualserialchanneldatatotheTL16C752C.
Duringthelocalloopbackmode,theseRXinputpinsaredisabledandRXA,RXB5,44,3ITXdataisinternallyconnectedtotheUARTRXinputinternally.
Duringnormalmode,RXnshouldbeheldhighwhennodataisbeingreceived.
TheseoutputsalsocanbeusedinIrDAmode.
Formoreinformation,seeIrDAOverview.
Receiveready(activelow).
RXRDYAandRXRDYBgolowwhenthetriggerlevelhasRXRDYA,31,18Obeenreachedoratimeoutinterruptoccurs.
TheygohighwhentheRXFIFOisemptyorRXRDYBthereisanerrorinRXFIFO.
Transmitdata.
TheseoutputsareassociatedwithindividualserialtransmitchanneldataTXA,TXB,7,85,6OfromtheTL16C752C.
Duringthelocalloopbackmode,theTXinputpinisdisabledandTXdataisinternallyconnectedtotheUARTRXinput.
TXRDYA,Transmitready(activelow).
TXRDYAandTXRDYBgolowwhenthereareatrigger43,6OTXRDYBlevelnumberofsparesavailable.
TheygohighwhentheTXbufferisfull.
VCC4226PwrPowersupplyinputsCrystalorexternalclockinput.
XTAL1functionsasacrystalinputorasanexternalclockinput.
AcrystalcanbeconnectedbetweenXTAL1andXTAL2toformaninternalXTAL1139Ioscillatorcircuit(seeFigure10).
Alternatively,anexternalclockcanbeconnectedtoXTAL1toprovidecustomdatarates.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014Table1.
TerminalFunctions(continued)TERMINALNO.
I/ODESCRIPTIONNAMEPFBRHBOutputofthecrystaloscillatororbufferedclock.
SeealsoXTAL1.
XTAL2isusedasaXTAL21410Ocrystaloscillatoroutputorbufferedclockoutput.
FunctionalBlockDiagramCopyright2008–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:TL16C752CTL16C752CSLLS646B–MARCH2008–REVISEDJANUARY2014www.
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comA.
ThevotelogicdetermineswhethertheRXdataisalogic1or0.
IttakesthreesamplesoftheRXlineandusesamajorityvotetodeterminethelogiclevelreceived.
Thevotelogicoperatesonallbitsreceived.
FunctionalDescriptionTheTL16C752CUARTispincompatiblewiththeTL16C2550UARTinthePFBpackage.
Itprovidesmoreenhancedfeatures.
Alladditionalfeaturesareprovidedthroughaspecialenhancedfeatureregister.
TheUARTperformsserial-to-parallelconversionondatacharactersreceivedfromperipheraldevicesormodemsandparallel-to-parallelconversionondatacharacterstransmittedbytheprocessor.
ThecompletestatusofeachchanneloftheTL16C752CUARTcanbereadatanytimeduringfunctionaloperationbytheprocessor.
TheTL16C752CUARTcanbeplacedinanalternatemode(FIFOmode)relievingtheprocessorofexcessivesoftwareoverheadbybufferingreceivedandtransmittedcharacters.
BoththereceiverandtransmitterFIFOscanstoreupto64bytes(includingthreeadditionalbitsoferrorstatusperbyteforthereceiverFIFO)andhaveselectableorprogrammabletriggerlevels.
PrimaryoutputsRXRDYandTXRDYallowSignalingofDMAtransfers.
TheTL16C752CUARThasselectablehardwareflowcontrolandsoftwareflowcontrol.
Bothschemessignificantlyreducesoftwareoverheadandincreasesystemefficiencybyautomaticallycontrollingserialdataflow.
HardwareflowcontrolusestheRTSoutputandCTSinputsignals.
SoftwareflowcontrolusesprogrammableXonandXoffcharacters.
TheTL16C752Cincludesaprogrammablebaudrategeneratorthatcandividethetimingreferenceclockbyadivisorbetween1and65535.
Abit(MCR7)canbeusedtoinvokeaprescaler(divideby4)offthereferenceclock,priortothebaudrategeneratorinput.
Thedivideby4prescalerisselectedwhenMCR7issetto1.
TriggerLevelsTheTL16C752CUARTprovidesindependentselectableandprogrammabletriggerlevelsforbothreceiverandtransmitterDMAandinterruptgeneration.
Afterreset,bothtransmitterandreceiverFIFOsaredisabledandso,ineffect,thetriggerlevelisthedefaultvalueofonebyte.
TheselectabletriggerlevelsareavailablethroughtheFCR.
TheprogrammabletriggerlevelsareavailablethroughtheTLR.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014HardwareFlowControlHardwareflowcontroliscomposedofauto-CTSandauto-RTS.
Auto-CTSandauto-RTScanbeenabledordisabledindependentlybyprogrammingEFR[7:6].
Withauto-CTS,CTSmustbeactivebeforetheUARTcantransmitdata.
Auto-RTSonlyactivatestheRTSoutputwhenthereisenoughroomintheFIFOtoreceivedataanddeactivatestheRTSoutputwhentheRXFIFOissufficientlyfull.
TheHALTandRESTOREtriggerlevelsintheTCRdeterminethelevelsatwhichRTSisactivatedordeactivated.
Ifbothauto-CTSandauto-RTSareenabled,whenRTSisconnectedtoCTS,datatransmissiondoesnotoccurunlessthereceiverFIFOhasemptyspace.
Thus,overrunerrorsareeliminatedduringhardwareflowcontrol.
Ifnotenabled,overrunerrorsoccurifthetransmitdatarateexceedsthereceiveFIFOservicinglatency.
Auto-RTSAuto-RTSdataflowcontroloriginatesinthereceiverblock(see).
Figure1showsRTSfunctionaltiming.
ThereceiverFIFOtriggerlevelsusedinAuto-RTSarestoredintheTCR.
RTSisactiveiftheRXFIFOlevelisbelowtheHALTtriggerlevelinTCR[3:0].
WhenthereceiverFIFOHALTtriggerlevelisreached,RTSisdeasserted.
Thesendingdevice(forexample,anotherUART)maysendanadditionalbyteafterthetriggerlevelisreached(assumingthesendingUARThasanotherbytetosend)becauseitmaynotrecognizethedeassertionofRTSuntilithasbegunsendingtheadditionalbyte.
RTSisautomaticallyreassertedoncethereceiverFIFOreachestheRESUMEtriggerlevelprogrammedviaTCR[7:4].
Thisreassertionallowsthesendingdevicetoresumetransmission.
A.
N=receiverFIFOtriggerlevelB.
B.
ThetwoblocksindashedlinescoverthecasewhereanadditionalbyteissentasdescribedinAuto-RTS.
Figure1.
RTSFunctionalTimingAuto-CTSThetransmittercircuitrychecksCTSbeforesendingthenextdatabyte.
WhenCTSisactive,thetransmittersendsthenextbyte.
Tostopthetransmitterfromsendingthefollowingbyte,CTSmustbedeassertedbeforethemiddleofthelaststopbitthatiscurrentlybeingsent.
Theauto-CTSfunctionreducesinterruptstothehostsystem.
Whenflowcontrolisenabled,theCTSstatechangesandneednottriggerhostinterruptsbecausethedeviceautomaticallycontrolsitsowntransmitter.
Withoutauto-CTS,thetransmittersendsanydatapresentinthetransmitFIFOandareceiveroverrunerrorcanresult.
Figure2showsCTSfunctionaltiming,andFigure3showsanexampleofautoflowcontrol.
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WhenCTSislow,thetransmitterkeepssendingserialdataout.
B.
WhenCTSgoeshighbeforethemiddleofthelaststopbitofthecurrentbyte,thetransmitterfinishessendingthecurrentbyte,butitdoesnotsendthenextbyte.
C.
WhenCTSgoesfromhightolow,thetransmitterbeginssendingdataagain.
Figure2.
CTSFunctionalTimingFigure3.
AutoflowControl(Auto-RTSandAuto-CTS)ExampleSoftwareFlowControlSoftwareflowcontrolisenabledthroughtheenhancedfeatureregisterandthemodemcontrolregister.
DifferentcombinationsofsoftwareflowcontrolcanbeenabledbysettingdifferentcombinationsofEFR[30].
Table2showssoftwareflowcontroloptions.
Twootherenhancedfeaturesrelatetosoftwareflowcontrol:XonAnyFunction[MCR(5):OperationresumesafterreceivinganycharacterafterrecognizingtheXoffcharacter.
NOTEItispossiblethatanXon1characterisrecognizedasanXonAnycharacter,whichcouldcauseanXon2charactertobewrittentotheRXFIFO.
SpecialCharacter[EFR(5)]:IncomingdataiscomparedtoXoff2.
DetectionofthespecialcharactersetstheXoffinterrupt{IIR(4)]butdoesnothalttransmission.
TheXoffinterruptisclearedbyareadoftheIIR.
ThespecialcharacteristransferredtotheRXFIFO.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014Table2.
SoftwareFlowControlOptionsEFR[3:0]BIT3BIT2BIT1BIT0Tx,RxSOFTWAREFLOWCONTROLS00XXNotransmitflowcontrol10XXTransmitXon1,Xoff101XXTransmitXon2,Xoff211XXTransmitXon1,Xon2:Xoff1,Xoff2XX00NoreceiveflowcontrolXX10ReceivercomparesXon1,Xoff1XX01XX01ReceivercomparesXon2,Xoff2TransmitXon1,Xoff11011ReceivercomparesXon1orXon2,Xoff1orXoff2TransmitXon2,Xoff20111ReceivercomparesXon1orXon2,Xoff1orXoff2TransmitXon1,Xon2:Xoff1,Xoff21111ReceivercomparesXon1andXon2:Xoff1andXoff2Notransmitflowcontrol0011ReceivercomparesXon1andXon2:Xoff1andXoff2Whensoftwareflowcontroloperationisenabled,theTL16C752CcomparesincomingdatawithXoff1/2programmedcharacters(incertaincasesXoff1andXoff2mustbereceivedsequentially(1)).
WhenanXoffcharacterisreceived,transmissionishaltedaftercompletingtransmissionofthecurrentcharacter.
XoffcharacterdetectionalsosetsIIR[4]andcausesINTtogohigh(ifenabledviaIER[5]).
ToresumetransmissionanXon1/2charactermustbereceived(incertaincasesXon1andXon2mustbereceivedsequentially).
WhenthecorrectXoncharactersarereceivedIIR[4]isclearedandtheXoffinterruptdisappears.
NOTEIfaparity,framing,orbreakerroroccurswhilereceivingasoftwareflowcontrolcharacter,thischaracteristreatedasnormaldataandiswrittentotheRCVFIFO.
Xoff1andXoff2charactersaretransmittedwhentheRXFIFOhaspassedtheprogrammedtriggerlevelTCR[3:0].
Xon1andXon2charactersaretransmittedwhentheRXFIFOreachesthetriggerlevelprogrammedviaTCR[7:4].
NOTEIf,afteranXoffcharacterhasbeensent,softwareflowcontrolisdisabled,theUARTtransmitsXoncharactersautomaticallytoenablenormaltransmissiontoproceed.
AfeatureoftheTL16C752CUARTdesignisthatifthesoftwareflowcombination(EFR[3:0])changesafteranXoffhasbeensent,theoriginallyprogrammedXonisautomaticallysent.
IftheRXFIFOisstillabovethetriggerlevel,thenewlyprogrammedXoff1orXoff2istransmitted.
ThetransmissionofXoffandXonfollowstheexactsameprotocolastransmissionofanordinarybytefromtheFIFO.
Thismeansthatevenifthewordlengthissettobe5,6,or7characters,thenthe5,6,or7leastsignificantbitsofXoff1,Xoff2andXon1,Xon2aretransmitted.
Thetransmissionof5,6,or7bitsofacharacterisseldomdone,butthisfunctionalityisincludedtomaintaincompatibilitywithearlierdesigns.
Itisassumedthatsoftwareflowcontrolandhardwareflowcontrolareneverenabledsimultaneously.
Figure4showsasoftwareflowcontrolexample.
(1)WhenpairsofXon/Xoffcharactersareprogrammedtooccursequentially,receivedXon1/Xoff1characterswillbewrittentotheRxFIFOifthesubsequentcharacterisnotXon2/Xoff2.
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SoftwareFlowControlExampleSoftwareFlowControlExampleAssumptions:UART1istransmittingalargetextfiletoUART2.
BothUARTsareusingsoftwareflowcontrolwithsinglecharacterXoff(0F)andXon(0D)tokens.
BothhaveXoffthreshold(TCR[3:0]=F)setto60andXonthreshold(TCR[7:4]=8)setto32.
Bothhavetheinterruptreceivethreshold(TLR[7:4]=D)setto52.
UART1beginstransmissionandsends52characters,atwhichpointUART2generatesaninterrupttoitsprocessortoservicetheRCVFIFO,butassumestheinterruptlatencyisfairlylong.
UART1continuessendingcharactersuntilatotalof60charactershavebeensent.
AtthistimeUART2transmitsa0FtoUART1,informingUART1tohalttransmission.
UART1likelysendsthe61stcharacterwhileUART2issendingtheXoffcharacter.
NowUART2isservicedandtheprocessorreadsenoughdataoutoftheRCVFIFOthattheleveldropsto32.
UART2nowsendsa0DtoUART1,informingUART1toresumetransmission.
ResetTable3summarizesthestateofoutputsafterreset.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014Table3.
RegisterResetFunctions(1)RESETREGISTERRESETSTATECONTROLInterruptenableregisterRESETAllbitsclearedInterruptidentificationregisterRESETBit0isset.
Allotherbitscleared.
FIFOcontrolregisterRESETAllbitsclearedLinecontrolregisterRESETResetto00011101(1Dhex)ModemcontrolregisterRESETAllbitsclearedLinestatusregisterRESETBits5and6set.
Allotherbitscleared.
ModemstatusregisterRESETBits0–3cleared.
Bits4–7inputsignals.
EnhancedfeatureregisterRESETAllbitsclearedReceiverholdingregisterRESETPointerlogicclearedTransmitterholdingregisterRESETPointerlogicclearedTransmissioncontrolregisterRESETAllbitsclearedTriggerlevelregisterRESETAllbitsclearedAlternatefunctionregisterRESETAllbits(exceptAFR4)cleared;AFR4set(1)RegistersDLL,DLH,SPR,Xon1,Xon2,Xoff1,andXoff2arenotresetbythetop-levelresetsignalRESET,thatis,theyholdtheirinitializationvaluesduringreset.
Table4summarizesthestateofoutputsafterreset.
Table4.
SignalResetFunctionsSIGNALRESETCONTROLRESETSTATETXRESETHighRTSRESETHighDTRRESETHighRXRDYA–BRESETHighTXRDYA–BRESETLowInterruptsTheTL16C752CUARThasinterruptgenerationandprioritization(sixprioritizedlevelsofinterrupts)capability.
Theinterruptenableregister(IER)enableseachofthesixtypesofinterruptsandtheINTsignalinresponsetoaninterruptgeneration.
TheIERalsocandisabletheinterruptsystembyclearingbits0to3,5to7.
Whenaninterruptisgenerated,theinterruptidentificationregister(IIR)indicatesthataninterruptispendingandprovidesthetypeofinterruptthroughIIR[50].
Table5summarizestheinterruptcontrolfunctions.
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InterruptControlFunctionsPRIORITYINTERRUPTIIR[5–0]INTERRUPTSOURCEINTERRUPTRESETMETHODLEVELTYPE000001NoneNoneNoneNone0001101ReceiverlineOE,FE,PE,orBIerrorsoccurinFETCR[7:4].
Thereisnobuilt-inhardwarechecktomakesurethisconditionismet.
Also,theTCRmustbeprogrammedwiththisconditionbeforeAuto-RTSorsoftwareflowcontrolisenabledtoavoidspuriousoperationofthedevice.
TriggerLevelRegister(TLR)This8-bitregisterisusedtostorethetransmitandreceivedFIFOtriggerlevelsusedforDMAandinterruptgeneration.
Triggerlevelsfrom4to60canbeprogrammedwithagranularityof4.
Table21showstriggerlevelregisterbitsettings.
Table21.
TriggerLevelRegister(TLR)BitSettingsBITNO.
BITSETTINGSTransmitFIFOtriggerlevels(4to60),numberofspaces3:0availableRCVFIFOtriggerlevels(4to60),numberofcharacters7:4availableTLRcanbewrittentoonlywhenEFR[4]=1andMCR[6]=1.
IfTLR[3:0]orTLR[7:4]are0,thentheselectabletriggerlevelsviatheFIFOcontrolregister(FCR)areusedforthetransmitandreceiveFIFOtriggerlevels.
Triggerlevelsfrom4to60bytesareavailablewithagranularityof4.
TheTLRshouldbeprogrammedforN/4,whereNisthedesiredtriggerlevel.
FIFOReadyRegisterTheFIFOreadyregisterprovidesrealtimestatusofthetransmitandreceiveFIFOsofbothchannels.
Table22showstheFIFOreadyregisterbitsettings.
ThetriggerlevelmentionedinTable22referstothesettingineitherFCR(whenTLRvalueis0),orTLR(whenithasanonzerovalue).
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FIFOReadyRegisterBITNO.
BITSETTINGS0=TherearefewerthanaTXtriggerlevelnumberofspacesavailableintheTXFIFOofchannelA.
01=ThereareatleastaTXtriggerlevelnumberofspacesavailableintheTXFIFOofchannelA.
0=TherearefewerthanaTXtriggerlevelnumberofspacesavailableintheTXFIFOofchannelB.
11=ThereareatleastaTXtriggerlevelnumberofspacesavailableintheTXFIFOofchannelB.
3:2Unused,always00=TherearefewerthanaRXtriggerlevelnumberofcharactersintheRXFIFOofchannelA.
41=TheRXFIFOofchannelAhasmorethanaRXtriggerlevelnumberofcharactersavailableforreadingoratimeoutconditionhasoccurred.
0=TherearefewerthanaRXtriggerlevelnumberofcharactersintheRXFIFOofchannelB.
51=TheRXFIFOofchannelBhasmorethanaRXtriggerlevelnumberofcharactersavailableforreadingoratimeoutconditionhasoccurred.
7:6Unused,always0TheFIFORdyregisterisareadonlyregisterandcanbeaccessedwhenanyofthetwoUARTsareselected.
CSAorCSB=0,MCR[2](FIFORdyEnable)isalogic1,andloopbackisdisabled.
Itsaddressis111.
AlternateFunctionRegister(AFR)Thealternatefunctionregister(AFR)isusedtoenablesomeextrafunctionalitybeyondthecapabilitiesoftheoriginalTL16C752B.
Thefirstoftheseisaconcurrentwritemode,whichcanbeusefulinmoreexpedientlysettingupallfourUARTchannels.
ThesecondadditionistheIrDAmode,whichsupportsStandardIrDA(SIR)modewithbaudratesfrom2400to115.
2bps.
ThethirdadditionissupportforRS-485busdriversortransceiversbyprovidinganoutputpin(DTRx)perchannel,whichistimedtokeeptheRS-485driverenabledaslongastransmitdataispending.
TheAFRislocatedatA[2:0]=010whenLCR[7:5]=100.
Table23.
AlternateFunctionRegister(AFR)BitSettingsBITNO.
BITSETTINGSCONCenablestheconcurrentwriteofallfour(754)ortwo(752)channelssimultaneously,whichhelpsspeedup0initialization.
Ensurethatanyindirectaddressingmodeshavebeenenabledbeforeusing.
IRENenablestheIrDASIRmode.
Thismodeisonlyspecifiedto115.
2bpsanduseofthismodeathigherspeedsisnot1recommended.
485ENenablesthehalfduplexRS-485modeandcausestheDTRxoutputtobesethighwheneverthereisanydataintheTHRorTSRandtobeheldhighuntilthedelaysetbyDLY3:0hasexpired,atwhichtimeitissetlow.
TheDTRx2outputisintendedtodrivetheenabledinputofanRS-485driver.
Whenthisbitisset,thetransmitterinterruptsareheldoffuntiltheTSRisempty,unless485LGisset.
485LGissetwhenthe485ENisset.
Thisbitindicatesthatarelativelylargedatablockisbeingset,requiringmorethan3asingleloadofthexmtfifo.
Inthiscase,thetransmitterinterruptsoccurasinthestandardRS-232mode,eitherwhenthexmtfifocontentsdropbelowthexmtthresholdorwhenthexmtfifoisempty.
RCVENisvalidonlywhen485ENorIRENisset,andallowstheserialreceivertolisteninorsnoopontheRS485trafficorIrDAtraffic.
RS485modeisgenerallyconsideredhalfduplex,andusuallyanodeiseitherdrivingorreceiving,buttherecanbecaseswhenitisadvantageoustoverifywhatyouaresending.
Thiscanbeusedtodetectcollisionsoraspartofanarbitrationmechanismonthebus.
WhenbothRCVENand485ENareset,thereceiverstoresanydatapresentedonRX,ifany.
NotethatimpliesthattheexternalRS485receiverisenabled.
Whenever485ENiscleared,theserialreceiverisenabledfornormalfullduplexRS232traffic.
IfRCVENisclearedwhile485ENisset,thereceiverisdisabledwhilethatchannelistransmitting.
StandardIrDA(SIR)isalsoconsideredhalfduplex.
Oftenthelightenergy4fromthetransmittingLEDiscoupledbackintothereceivingPINdiode,whichcreatesaninputdatastreamthatisnotofinteresttothehost.
Disablingthereceiver(clearingRCVEN)preventsthisreception,andeliminatesthetaskofunloadingthedata.
Ontheotherhand,fordiagnosticorotherpurposes,itmaybeusefultoobservethisdatastream.
Forexample,amirrorcouldbeusedtointentionallycoupletheoutputLEDtotheinputPIN.
Forthesecases,RCVENcouldbesettoenablethereceiver.
NOTE:WhenRCVENiscleared(setto0),thecharactertimeoutinterruptisnotavailable,eveninRSA-232mode.
Thiscanbeusefulwhencheckingcodeforvalidthresholdinterrupts,asthetimeoutinterruptwillnotoverridethethresholdinterrupt.
DLY3–DLY0setsadelayafterthelaststopbitofthelastdatabytebeingsetbeforetheDTRxissetlow,toallowforlongcableruns.
Thedelayisinnumberofbittimesandisenabledby485EN.
Thedelaystartsonlywhenboththexmtserial7:5shiftregister(TSR)isemptyandthexmtfifo(THR)isempty,andifstarted,willbeclearedbyanydatabeingwrittentotheTHR.
Copyright2008–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback39ProductFolderLinks:TL16C752CTL16C752CSLLS646B–MARCH2008–REVISEDJANUARY2014www.
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comTable24.
LOOPandRCVENFunctionalityLOOPMODERCVENAFRMODEDESCRIPTIONReceivethreshold,timeout,anderrordetectioninterruptsavailableAFR=10RS-232DatastoredinreceiveFIFOReceivethreshold,timeout,anderrordetectioninterruptsavailableRCVEN=1AFR=14RS-485DatastoredinreceiveFIFOLOOPmodeoff,Receivethreshold,timeout,anderrordetectioninterruptsavailableAFR=12IrDAMCR4=0,DatastoredinreceiveFIFORX,TXactiveReceivethresholdanderrordetectioninterruptsavailableAFR=00RS-232DatastoredinreceiveFIFORCVEN=0AFR=04RS-485NodatastoredinreceiveFIFO,hencenointerruptsavailableAFR=02IrDANodatastoredinreceiveFIFO,hencenointerruptsavailableReceivethreshold,timeout,anderrordetectioninterruptsavailableAFR=10RS-232DatastoredinreceiveFIFOReceivethreshold,timeout,anderrordetectioninterruptsavailableRCVEN=1AFR=14RS-485DatastoredinreceiveFIFOReceivethreshold,timeout,anderrordetectioninterruptsavailableAFR=12IrDALOOPmodeon,DatastoredinreceiveFIFOMCR4=1,ReceivethresholdanderrordetectioninterruptsavailableRX,TXinactiveAFR=00RS-232DatastoredinreceiveFIFOReceivethresholdanderrordetectioninterruptsavailableRCVEN=0AFR=04RS-485DatastoredinreceiveFIFOReceivethresholdanderrordetectioninterruptsavailableAFR=02IrDADatastoredinreceiveFIFORS-485ModeTheRS-485modeisintendedtosimplifytheinterfacebetweentheUARTchannelandanRS-485driverortransceiver.
Whenenabledbysetting485EN,theDTRxoutputgoeshighonebittimebeforethefirststopbitofthefirstdatabytebeingsent,andremainshighaslongasthereispendingdatainthetransmittershiftregister(TSR)ortransmitterholdingregister(THR,xmtfifo).
Afterbothareempty(afterthelaststopbitofthelastdatabyte),theDTRxoutputstayshighforaprogrammabledelayof0to15bittimes,assetbyDLY[3:0].
Thishelpspreservedataintegrityoverlongsignallines.
Thisisillustratedinthefollowing.
OftenRS-485packetsarerelativelyshortandtheentirepacketcanfitwithinthe64bytexmtfifo.
Inthiscase,itgoesemptywhentheTSRgoesempty.
Butincaseswherealargerblockneedstobesent,itisadvantageoustoreloadthexmtfifoassoonasitisdepleted.
Otherwise,thetransmissionstallswhilewaitingforthexmtfifotobereloaded,whichvarieswithprocessorload.
Inthiscase,itisbesttoalsoset485LG(largeblock),whichcausesthetransmitinterrupttooccurwitherwhentheTHRbecomesempty(ifthexmtfifolevelwasnotabovethethreshold),orwhenthexmtfifothresholdiscrossed.
Thereloadingofthexmtfifooccurswhilesomedataisbeingshiftedout,eliminatingfifounderrun.
Ifdesired,whenthelastbytesofacurrenttransmissionarebeingloadedinthexmtfifo,485LGcanbeclearedbeforetheloadandthetransmitinterruptoccursontheTSRgoingempty.
A.
Waveformsarenotshowntoscale,astheWRTHRpulsestypicallyarelessthan100ns,wheretheTXwaveformvarieswithbaudratebutistypicallyinthemicrosecondrange.
Figure25.
DTRxandTransmitDataRelationship40SubmitDocumentationFeedbackCopyright2008–2014,TexasInstrumentsIncorporatedProductFolderLinks:TL16C752CTL16C752Cwww.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014Figure26.
RS-485ApplicationExample1Figure27.
RS-485ApplicationExample2IrDAOverviewFigure28.
IrDAModeTheIrDAdefinesseveralprotocolsforsendingandreceivingserialinfrareddata,includingratesof115.
2kbps,0.
576Mbps,1.
152Mbps,and4Mbps.
Thelowrateof115.
2kbpswasspecifiedfirstandtheothersmustmaintaindownwardcompatibilitywithit.
Atthe115.
2kbpsrate,theprotocolimplementedinthehardwareisfairlysimple.
Itprimarilydefinesaserialinfrareddatawordtobesurroundedbyastartbitequalto0andastopbitequalto1.
Individualbitsareencodedordecodedthesamewhethertheyarestart,data,orstopbits.
TheIrDAengineintheTL16C752Cevaluateonlysinglebitsandonlyfollowthe115.
2-kbpsprotocol.
The115.
2-kbpsrateCopyright2008–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback41ProductFolderLinks:TL16C752CTL16C752CSLLS646B–MARCH2008–REVISEDJANUARY2014www.
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comisamaximumrate.
Whenbothendsofthetransferaresetuptoalowerbutmatchingspeed,theprotocolstillworks.
Theclockusedtocodeorsamplethedatais16timesthebaudrate,or1.
843MHzmaximum.
Tocodea1,nopulseissentorreceivedfor1-bittimeperiod,or16clockcycles.
Tocodea0,onepulseissentorreceivedwithina1-bittimeperiod,or16clockcycles.
Thepulsemustbeatleast1.
6-μswideand3clockcycleslongat1.
843MHz.
Atlowerbaudratesthepulsecanbe1.
6μswideoraslongas3clockcycles.
Thetransmitteroutput,Tx,isintendedtodriveaLEDcircuittogenerateaninfraredpulse.
TheLEDcircuitsworkonpositivepulses.
Aterminalcircuitisexpectedtocreatethereceiverinput,Rx.
Most,butnotall,PINcircuitshaveinversionandgeneratenegativepulsesfromthedetectedinfraredlight.
Theiroutputisnormallyhigh.
TheTL16C752CcandecodeeithernegativeorpositivepulsesonRx.
IrDAEncoderFunctionSerialdatafromaUARTisencodedtotransmitdatatotheoptoelectronics.
Whiletheserialdatainputtothisblock(Int_Tx)ishigh,theoutput(Tx)isalwayslow,andthecounterusedtoformapulseonTxiscontinuouslycleared.
AfterInt_Txresetsto0,Txrisesonthefallingedgeoftheseventh16XCLK.
Onthefallingedgeofthetenth16XCLKpulse,Txfalls,creatinga3-clock-widepulse.
WhileInt_Txstayslow,apulseistransmittedduringtheseventhtotenthclocksofeach16-clockbitcycle.
Figure29.
IrDA-SIREncodingScheme–DetailedFigure30.
EncodingScheme–MacroViewTimingDiagramAfterreset,Int_Rxishighandthe4-bitcounteriscleared.
WhenafallingedgeisdetectedonRx,Int_Rxfallsonthenextrisingedgeof16XCLKwithsufficientsetuptime.
Int_Rxstayslowfor16cycles(16XCLK)andthenreturnstohighasrequiredbytheIrDAspecification.
Aslongasnopulses(fallingedges)aredetectedonRx,Int_Rxremainshigh.
Figure31.
IrDA-SIRDecodingScheme–DetailedFigure32.
IrDA-SIRDecodingScheme–MacroTimingDiagramViewItispossibleforjitterorslightfrequencydifferencestocausethenextfallingedgeonRxtobemissedforone16XCLKcycle.
Inthatcase,a1-clock-widepulseappearsonInt_Rxbetweenconsecutivezeroes.
ItisimportantfortheUARTtostrobeInt_Rxinthemiddleofthebittimetoavoidlatchingthis1-clock-widepulse.
TheTL16C550CUARTalreadystrobesincomingserialdataatthepropertime.
Otherwise,notethatdataisrequiredtobeframedbyaleading0andatrailing1.
Thefallingedgeofthatfirst0onInt_Rxsynchronizesthereadstrobe.
Thestrobeoccursontheeighth16XCLKpulseaftertheInt_Rxfallingedgeandonceevery16cyclesthereafteruntilthestopbitoccurs.
42SubmitDocumentationFeedbackCopyright2008–2014,TexasInstrumentsIncorporatedProductFolderLinks:TL16C752CTL16C752Cwww.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014Figure33.
TimingCausing1-Clock-WidePulseBetweenConsecutiveOnesFigure34.
RecommendedStrobingforDecodedDataTheTL16C752CcandecodepositivepulsesonRx.
Thetimingisdifferent,butthevariationisinvisibletotheUART.
Thedecoder,whichworksfromthefallingedge,nowrecognizesa0onthetrailingedgeofthepulseratherthanontheleadingedge.
Aslongasthepulsewidthisfairlyconstant,asdefinedbythespecification,thetrailingedgesshouldalsobe16clockcyclesapartanddatacanreadilybedecoded.
The0appearsonInt_Rxafterthepulseratherthanatthestartofit.
Figure35.
PositiveRxPulseDecode–DetailedViewCopyright2008–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback43ProductFolderLinks:TL16C752CTL16C752CSLLS646B–MARCH2008–REVISEDJANUARY2014www.
ti.
comFigure36.
PositiveRxPulseDecode–MacroView44SubmitDocumentationFeedbackCopyright2008–2014,TexasInstrumentsIncorporatedProductFolderLinks:TL16C752CTL16C752Cwww.
ti.
comSLLS646B–MARCH2008–REVISEDJANUARY2014TL16C752CProgrammer'sGuideThebasesetofregistersthatareusedduringhigh-speeddatatransferhaveastraightforwardaccessmethod.
Theextendedfunctionregistersrequirespecialaccessbitstobedecodedalongwiththeaddresslines.
Thefollowingguidehelpswithprogrammingtheseregisters.
Notethatthedescriptionsareforindividualregisteraccess.
Somestreamliningthroughinterleavingcanbeobtainedwhenprogrammingalltheregisters.
SetbaudratetoVALUE1,VALUE2ReadLCR(03),saveintempSetLCR(03)to80SetDLL(00)toVALUE1SetDLM(01)toVALUE2SetLCR(03)totempSetXoff1,Xon1toVALUE1,VALUE2ReadLCR(03),saveintempSetLCR(03)toBFSetXoff1(06)toVALUE1SetXon1(04)toVALUE2SetLCR(03)totempSetXoff2,Xon2toVALUE1,VALUE2ReadLCR(03),saveintempSetLCR(03)toBFSetXoff2(07)toVALUE1SetXon2(05)toVALUE2SetLCR(03)totempSetsoftwareflowcontrolmodetoVALUEReadLCR(03),saveintempSetLCR(03)toBFSetEFR(02)toVALUESetLCR(03)totempSetflowcontrolthresholdtoVALUEReadLCR(03),saveintemp1SetLCR(03)toBFReadEFR(02),saveintemp2SetEFR(02)to10+temp2SetLCR(03)to00ReadMCR(04),saveintemp3SetMCR(04)to40+temp3SetTCR(06)toVALUESetLCR(03)toBFSetEFR(02)totemp2SetLCR(03)totemp1SetMCR(04)totemp3SetxmtandrcvFIFOthresholdstoVALUEReadLCR(03),saveintemp1SetLCR(03)toBFReadEFR(02),saveintemp2SetEFR(02)to10+temp2SetLCR(03)to00ReadMCR(04),saveintemp3SetMCR(04)to40+temp3SetTLR(07)toVALUESetLCR(03)toBFSetEFR(02)totemp2SetLCR(03)totemp1SetMCR(04)totemp3ReadFIFORdyregisterReadMCR(04),saveintemp1Settemp2=temp1*EFSetMCR(04),saveintemp2ReadFRR(07),saveintemp2Passtemp2backtohostSetMCR(04)totemp1Copyright2008–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback45ProductFolderLinks:TL16C752CTL16C752CSLLS646B–MARCH2008–REVISEDJANUARY2014www.
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comFigure37.
DiagramoftheGenericConfigurationProcess46SubmitDocumentationFeedbackCopyright2008–2014,TexasInstrumentsIncorporatedProductFolderLinks:TL16C752CTL16C752Cwww.
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comSLLS646B–MARCH2008–REVISEDJANUARY2014REVISIONHISTORYChangesfromRevisionA(August2009)toRevisionBPageAddedthetypicalpackagethermalresistancedata18ReplacedtheregistermaptablewithFigure2429UpdatedTable1030AddedFigure37,adiagramofthegenericconfigurationprocess46Copyright2008–2014,TexasInstrumentsIncorporatedSubmitDocumentationFeedback47ProductFolderLinks:TL16C752CPACKAGEOPTIONADDENDUMwww.
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com15-Dec-2014Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinish(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesTL16C752CIPFBACTIVETQFPPFB48250Green(RoHS&noSb/Br)CUNIPDAULevel-2-260C-1YEAR-40to85752CIPFBTL16C752CIPFBRACTIVETQFPPFB481000Green(RoHS&noSb/Br)CUNIPDAULevel-2-260C-1YEAR-40to85752CIPFBTL16C752CIRHBRACTIVEVQFNRHB323000Green(RoHS&noSb/Br)CUNIPDAULevel-3-260C-168HR-40to85752CITL16C752CIRHBRG4ACTIVEVQFNRHB323000Green(RoHS&noSb/Br)CUNIPDAULevel-3-260C-168HR-40to85752CITL16C752CPFBACTIVETQFPPFB48250Green(RoHS&noSb/Br)CUNIPDAULevel-2-260C-1YEAR0to70752CPFBTL16C752CPFBRACTIVETQFPPFB481000Green(RoHS&noSb/Br)CUNIPDAULevel-2-260C-1YEAR0to70752CPFBTL16C752CRHBRACTIVEVQFNRHB323000Green(RoHS&noSb/Br)CUNIPDAULevel-3-260C-168HR0to70752C(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
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TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
PACKAGEOPTIONADDENDUMwww.
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OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantTL16C752CIPFBRTQFPPFB481000330.
016.
49.
69.
61.
512.
016.
0Q2TL16C752CIRHBRVQFNRHB323000330.
012.
45.
35.
31.
58.
012.
0Q2TL16C752CPFBRTQFPPFB481000330.
016.
49.
69.
61.
512.
016.
0Q2TL16C752CRHBRVQFNRHB323000330.
012.
45.
35.
31.
58.
012.
0Q2PACKAGEMATERIALSINFORMATIONwww.
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com3-Nov-2016PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)TL16C752CIPFBRTQFPPFB481000367.
0367.
038.
0TL16C752CIRHBRVQFNRHB323000336.
6336.
628.
6TL16C752CPFBRTQFPPFB481000367.
0367.
038.
0TL16C752CRHBRVQFNRHB323000336.
6336.
628.
6PACKAGEMATERIALSINFORMATIONwww.
ti.
com3-Nov-2016PackMaterials-Page2MECHANICALDATAMTQF019A–JANUARY1995–REVISEDJANUARY1998POSTOFFICEBOX655303DALLAS,TEXAS75265PFB(S-PQFP-G48)PLASTICQUADFLATPACK4073176/B10/96GagePlane0,13NOM0,250,450,75SeatingPlane0,05MIN0,170,2724251312SQ36377,206,804815,50TYPSQ8,809,201,050,951,20MAX0,080,50M0,080°–7°NOTES:A.
Alllineardimensionsareinmillimeters.
B.
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C.
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