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2014SiliconStorageTechnology,Inc.
DS20005086B11/14DataSheetwww.
microchip.
comFeaturesLPCInterfaceFlash–SST49LF080A:1024Kx8(8Mbit)ConformstoIntelLPCInterfaceSpecification1.
0FlexibleEraseCapability–Uniform4KByteSectors–Uniform64KByteoverlayblocks–64KByteTopBootBlockprotection–Chip-EraseforPPModeOnlySingle3.
0-3.
6VReadandWriteOperationsSuperiorReliability–Endurance:100,000Cycles(typical)–Greaterthan100yearsDataRetentionLowPowerConsumption–ActiveReadCurrent:6mA(typical)–StandbyCurrent:10A(typical)FastSector-Erase/Byte-ProgramOperation–Sector-EraseTime:18ms(typical)–Block-EraseTime:18ms(typical)–Chip-EraseTime:70ms(typical)–Byte-ProgramTime:14s(typical)–ChipRewriteTime:16seconds(typical)–Single-pulseProgramorErase–InternaltiminggenerationTwoOperationalModes–LowPinCount(LPC)Interfacemodeforin-systemoperation–ParallelProgramming(PP)Modeforfastproductionpro-grammingLPCInterfaceMode–5-signalcommunicationinterfacesupportingbyteReadandWrite–33MHzclockfrequencyoperation–WP#andTBL#pinsprovidehardwarewriteprotectforentirechipand/ortopbootblock–StandardSDPCommandSet–Data#PollingandToggleBitforEnd-of-Writedetection–5GPIpinsforsystemdesignflexibility–4IDpinsformulti-chipselectionParallelProgramming(PP)Mode–11-pinmultiplexedaddressand8-pindataI/Ointerface–SupportsfastprogrammingIn-SystemonprogrammerequipmentCMOSandPCII/OCompatibilityPackagesAvailable–32-leadPLCC–32-leadTSOP(8mmx14mm)Allnon-Pb(lead-free)devicesareRoHScompliant8MbitLPCFlashSST49LF080ATheSST49LF080AflashmemorydeviceisdesignedtointerfacewiththeLPCbusforPCandInternetApplianceapplicationincompliancewithIntelLowPinCount(LPC)InterfaceSpecification1.
0.
Twointerfacemodesaresupported:LPCmodeforin-systemoperationsandParallelProgramming(PP)modetointerfacewithprogrammingequipment.
TheSST49LF080Aflashmemorydeviceismanu-facturedwithproprietary,high-performanceSuperFlashTechnology.
Thesplit-gatecelldesignandthick-oxidetunnelinginjectorattainbetterreliabilityandman-ufacturabilitycomparedwithalternateapproaches2014SiliconStorageTechnology,Inc.
DS20005086B11/1428MbitLPCFlashSST49LF080ADataSheetProductDescriptionSST49LF080AflashmemorydeviceisdesignedtointerfacewiththeLPCbusforPCandInternetApplianceapplicationincompliancewithIntelLowPinCount(LPC)InterfaceSpecification1.
0.
Twointerfacemodesaresupported:LPCmodeforin-systemoperationsandParallelProgramming(PP)modetointerfacewithprogrammingequipment.
SST49LF080Aflashmemorydeviceismanufacturedwithproprietary,high-performanceSuperFlashTechnology.
Thesplit-gatecelldesignandthick-oxidetunnelinginjectorattainbetterreliabilityandmanufacturabilitycomparedwithalternateapproaches.
TheSST49LF080Adevicesignificantlyimprovesperformanceandreliability,whileloweringpowerconsumption.
TheSST49LF080Adevicewrites(ProgramorErase)withasingle3.
0-3.
6Vpowersupply.
ItuseslessenergyduringEraseandProgramthanalternativeflashmemorytechnologies.
Thetotalenergyconsumedisafunctionoftheappliedvoltage,currentandtimeofapplication.
Foranygivevoltagerange,theSuperFlashtechnologyuseslesscurrenttoprogramandhasashortererasetime;thetotalenergyconsumedduringanyEraseorProgramoperationislessthanalternativeflashmemorytechnologies.
TheSST49LF080AproductprovidesamaximumByte-Programtimeof20sec.
Theentirememorycanbeerasedandprogrammedbyte-by-bytetypicallyin16secondswhenusingstatusdetectionfeaturessuchasToggleBitorData#PollingtoindicatethecompletionofProgramoperation.
TheSuperFlashtechnologypro-videsfixedEraseandProgramtime,independentofthenumberofErase/Programcyclesthathaveperformed.
ThereforethesystemsoftwareorhardwaredoesnothavetobecalibratedorcorrelatedtothecumulativenumberofErasecyclesasisnecessarywithalternativeflashmemorytechnologies,whoseEraseandProgramtimeincreasewithaccumulatedErase/Programcycles.
Tomeethighdensity,surfacemountrequirements,theSST49LF080Adeviceisofferedin32-leadTSOPand32-leadPLCCpackages.
SeeFigures2and3forpinassignmentsandTable1forpindescriptions.
2014SiliconStorageTechnology,Inc.
DS20005086B11/1438MbitLPCFlashSST49LF080ADataSheetFunctionalBlockDiagramFigure1:FunctionalBlockDiagram1235B1.
0Y-DecoderI/OBuffersandDataLatchesAddressBuffersLatchesX-DecoderSuperFlashMemoryControlLogicLCLKRST#CE#MODEGPI[4:0]ProgrammerInterfaceWP#TBL#INIT#ID[3:0]LFRAME#R/C#OE#WE#A[10:0]DQ[7:0]LAD[3:0]LPCInterface2014SiliconStorageTechnology,Inc.
DS20005086B11/1448MbitLPCFlashSST49LF080ADataSheetPinAssignmentsFigure2:PinAssignmentsfor32-leadPLCCFigure3:PinAssignmentsfor32-leadTSOP(8mmx14mm)5678910111213292827262524232221A7(GPI1)A6(GPI0)A5(WP#)A4(TBL#)A3(ID3)A2(ID2)A1(ID1)A0(ID0)DQ0(LAD0)MODE(MODE)NC(CE#)NCNCVDD(VDD)OE#(INIT#)WE#(LFRAME#)NCDQ7(RES)4321323130A8(GPI2)A9(GPI3)RST#(RST#)NCVDD(VDD)R/C#(LCLK)A10(GPI4)32-leadPLCCTopView123532-plccP1.
014151617181920DQ1(LAD1)DQ2(LAD2)VSS(VSS)DQ3(LAD3)DQ4(RES)DQ5(RES)DQ6(RES)()DesignatesLPCModeNCNCNCNC(CE#)MODE(MODE)A10(GPI4)R/C#(LCLK)VDD(VDD)NCRST#(RST#)A9(GPI3)A8(GPI2)A7(GPI1)A6(GPI0)A5(WP#)A4(TBL#)12345678910111213141516OE#(INIT#)WE#(LFRAME#)VDD(VDD)DQ7(RES)DQ6(RES)DQ5(RES)DQ4(RES)DQ3(LAD3)VSS(VSS)DQ2(LAD2)DQ1(LAD1)DQ0(LAD0)A0(ID0)A1(ID1)A2(ID2)A3(ID3)32313029282726252423222120191817123532-tsopP2.
0StandardPinoutTopViewDieUp()DesignatesLPCMode2014SiliconStorageTechnology,Inc.
DS20005086B11/1458MbitLPCFlashSST49LF080ADataSheetTable1:PinDescriptionSymbolPinNameType1InterfaceFunctionsPPLPCA10-A0AddressIXInputsforlow-orderaddressesduringReadandWriteoperations.
AddressesareinternallylatchedduringaWritecycle.
Forthepro-gramminginterface,theseaddressesarelatchedbyR/C#andsharethesamepinsasthehigh-orderaddressinputs.
DQ7-DQ0DataI/OXTooutputdataduringReadcyclesandreceiveinputdataduringWritecycles.
DataisinternallylatchedduringaWritecycle.
Theout-putsareintri-statewhenOE#ishigh.
OE#OutputEnableIXTogatethedataoutputbuffers.
WE#WriteEnableIXTocontroltheWriteoperations.
MODEInterfaceModeSelectIXXThispindetermineswhichinterfaceisoperational.
Whenheldhigh,programmermodeisenabledandwhenheldlow,LPCmodeisenabled.
Thispinmustbesetupatpower-uporbeforereturnfromresetandnotchangeduringdeviceoperation.
Thispinmustbeheldhigh(VIH)forPPmodeandlow(VIL)forLPCmode.
INIT#InitializeIXThisisthesecondresetpinforin-systemuse.
Thispinisinter-nallycombinedwiththeRST#pin;IfthispinorRST#pinisdrivenlow,identicaloperationisexhibited.
ID[3:0]IdentificationInputsIXThesefourpinsarepartofthemechanismthatallowsmultiplepartstobeattachedtothesamebus.
Thestrappingofthesepinsisusedtoidentifythecomponent.
ThebootdevicemusthaveID[3:0]=0000forallsubsequentdevicesshouldusesequentialup-countstrapping.
Thesepinsareinternallypulled-downwitharesistorbetween20-100KGPI[4:0]GeneralPurposeInputsIXTheseindividualinputscanbeusedforadditionalboardflexibility.
ThestateofthesepinscanbereadthroughLPCregisters.
TheseinputsshouldbeattheirdesiredstatebeforethestartofthePCIclockcycledur-ingwhichthereadisattempted,andshouldremaininplaceuntiltheendoftheReadcycle.
UnusedGPIpinsmustnotbefloated.
TBL#TopBlockLockIXWhenlow,preventsprogrammingtothebootblocksectorsattopofmemory.
WhenTBL#ishighitdisableshardwarewriteprotectionforthetopblocksectors.
Thispincannotbeleftunconnected.
LAD[3:0]AddressandDataI/OXToprovideLPCcontrolsignals,aswellasaddressesandCommandInputs/Outputsdata.
LCLKClockIXToprovideaclockinputtothecontrolunitLFRAME#FrameIXToindicatestartofadatatransferoperation;alsousedtoabortanLPCcycleinprogress.
RST#ResetIXXToresettheoperationofthedeviceWP#WriteProtectIXWhenlow,preventsprogrammingtoallbutthehighestaddressableblocks.
WhenWP#ishighitdisableshardwarewriteprotectionfortheseblocks.
Thispincannotbeleftunconnected.
R/C#Row/ColumnSelectIXSelectfortheProgramminginterface,thispindetermineswhethertheaddresspinsarepointingtotherowaddresses,ortothecolumnaddresses.
RESReservedXThesepinsmustbeleftunconnected.
VDDPowerSupplyPWRXXToprovidepowersupply(3.
0-3.
6V)VSSGroundPWRXXCircuitground(0Vreference)CE#ChipEnableIXThissignalmustbeassertedtoselectthedevice.
WhenCE#islow,thedeviceisenabled.
WhenCE#ishigh,thedeviceisplacedinlowpowerstandbymode.
NCNoConnectionIXXUnconnectedpins.
T1.
0250261.
I=Input,O=Output2014SiliconStorageTechnology,Inc.
DS20005086B11/1468MbitLPCFlashSST49LF080ADataSheetDeviceMemoryMapsFigure4:DeviceMemoryMap0FFFFFH0F0000H0EFFFFH0E0000H0DFFFFH0D0000H0CFFFFH0C0000H0BFFFFH0B0000H0AFFFFH0A0000H09FFFFH090000H08FFFFH080000H07FFFFH070000H06FFFFH060000H05FFFFH050000H04FFFFH040000H03FFFFH030000H02FFFFH020000H01FFFFH010000H00FFFFHBlock7Block8Block6Block5Block4Block3Block2Block1Block15Block14Block13Block12Block11Block10Block9Block0(64KByte)1235F03.
0WP#forBlock014TBL#4KByteSector14KByteSector24KByteSector154KByteSector0BootBlock002000H001000H000000H2014SiliconStorageTechnology,Inc.
DS20005086B11/1478MbitLPCFlashSST49LF080ADataSheetDesignConsiderationsSSTrecommendsahighfrequency0.
1FceramiccapacitortobeplacedascloseaspossiblebetweenVDDandVSSlessthan1cmawayfromtheVDDpinofthedevice.
Additionally,alowfre-quency4.
7FelectrolyticcapacitorfromVDDtoVSSshouldbeplacedwithin5cmoftheVDDpin.
Ifyouuseasocketforprogrammingpurposesaddanadditional1-10Fnexttoeachsocket.
ProductIdentificationTheProductIdentificationmodeidentifiesthedeviceastheSST49LF080AandmanufacturerasSST.
ModeSelectionTheSST49LF080Aflashmemorydevicescanoperateintwodistinctinterfacemodes:theLPCmodeandtheParallelProgramming(PP)mode.
Themodepinisusedtosettheinterfacemodeselection.
IfthemodepinissettologicHigh,thedeviceisinPPmode.
IfthemodepinissetLow,thedeviceisintheLPCmode.
Themodeselectionpinmustbeconfiguredpriortodeviceoperation.
Themodepinisinternallypulleddownifthepinisleftunconnected.
InLPCmode,thedeviceisconfiguredtoitshostusingstandardLPCinterfaceprotocol.
CommunicationbetweenHostandtheSST49LF080Aoccursviathe4-bitI/Ocommunicationsignals,LAD[3:0]andLFRAME#.
InPPmode,thedeviceispro-grammedviaan11-bitaddressandan8-bitdataI/Oparallelsignals.
Theaddressinputsaremulti-plexedinrowandcolumnselectedbycontrolsignalR/C#pin.
Therowaddressesaremappedtothelowerinternaladdresses(A10-0),andthecolumnaddressesaremappedtothehigherinternaladdresses(AMS-11).
SeeFigure4,theDeviceMemoryMap,foraddressassignments.
Table2:ProductIdentificationAddressDataManufacturer'sID0000HBFHDeviceIDSST49LF080A0001H5BHT2.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/1488MbitLPCFlashSST49LF080ADataSheetLPCModeDeviceOperationTheLPCmodeusesa5-signalcommunicationinterface,a4-bitaddress/databus,LAD[3:0],andacontrolline,LFRAME#,tocontroloperationsoftheSST49LF080A.
CycletypeoperationssuchasMemoryReadandMemoryWritearedefinedinIntelLowPinCountInterfaceSpecification,Revision1.
0.
JEDECStandardSDP(SoftwareDataProtection)ProgramandErasecommandssequencesareincorporatedintothestandardLPCmemorycycles.
SeeFigures7through12forcommandsequences.
LPCsignalsaretransmittedviathe4-bitAddress/Databus(LAD[3:0]),andfollowaparticularsequence,dependingonwhethertheyareReadorWriteoperations.
LPCmemoryReadandWritecycleisdefinedinTables5and6.
BothLPCReadandWriteoperationsstartinasimilarwayasshowninFigures5and6.
Thehost(whichisthetermusedheretodescribethedevicedrivingthememory)assertsLFRAME#fortwoormoreclocksanddrivesastartvalueontheLAD[3:0]bus.
Atthebeginningofanoperation,thehostmayholdtheLFRAME#activeforseveralclockcycles,andevenchangetheStartvalue.
TheLAD[3:0]busislatchedeveryrisingedgeoftheclock.
OnthecycleinwhichLFRAME#goesinactive,thelastlatchedvalueistakenastheStartvalue.
CE#mustbeassertedonecyclebeforethestartcycletoselecttheSST49LF080AforReadandWriteoperations.
OncetheSST49LF080Aidentifiestheoperationasvalid(astartvalueofallzeros),itnextexpectsanibblethatindicateswhetherthisisamemoryReadorWritecycle.
Oncethisisreceived,thedeviceisnowreadyfortheAddresscycles.
TheLPCprotocolsupportsa32-bitaddressphase.
TheSST49LF080AencodesIDandregisterspaceaccessintheaddressfield.
SeeTable3foraddressbitsdefinition.
ForWriteoperationtheDatacyclewillfollowtheAddresscycle,andforReadoperationTARandSYNCcyclesoccurbetweentheAddressandDatacycles.
Attheendofeveryoperation,thecontrolofthebusmustbereturnedtothehostbya2-clockTARcycle.
Table3:AddressbitsdefinitionA31:A2511.
Thetop32MByteaddressrangeFFFFFFFFHtoFE000000Handthebottom128KBytememoryaccessaddress000FFFFFHto000E0000Haredecoded.
A24:A23A22A21:A20A19:A01111111bor0000000bID[3:2]22.
SeeTable7formultipledeviceselectionconfiguration1=MemoryAccess0=RegisteraccessID[1:0]2DeviceMemoryaddressT3.
1250262014SiliconStorageTechnology,Inc.
DS20005086B11/1498MbitLPCFlashSST49LF080ADataSheetCE#TheCE#pin,enablesanddisablestheSST49LF080A,controllingreadandwriteaccessofthedevice.
ToenabletheSST49LF080A,theCE#pinmustbedrivenlowoneclockcyclepriortoLFRAME#beingdrivenlow.
ThedevicewillenterstandbymodewheninternalWriteoperationsarecompletedandCE#ishigh.
LFRAME#TheLFRAME#signifiesthestartofa(frame)buscycleortheterminationofanundesiredcycle.
AssertingLFRAME#foroneormoreclockcycleanddrivingavalidSTARTvalueonLAD[3:0]williniti-atedeviceoperation.
ThedevicewillenterstandbymodewheninternaloperationsarecompletedandLFRAME#ishigh.
TBL#,WP#TheTopBootLock(TBL#)andWriteProtect(WP#)pinsareprovidedforhardwarewriteprotectionofdevicememory.
TheTBL#pinisusedtoWrite-Protect16bootsectors(64KByte)atthehighestmem-oryaddressrangefortheSST49LF080A.
TheWP#pinwriteprotectstheremainingsectorsintheflashmemory.
AnactivelowsignalattheTBL#pinpreventsProgramandEraseoperationsofthetopbootsectors.
WhenTBL#pinisheldhigh,thewriteprotectionofthetopbootsectorsisdisabled.
TheWP#pinservesthesamefunctionfortheremainingsectorsofthedevicememory.
TheTBL#andWP#pinswriteprotectionfunctionsoperateindependentlyofoneanother.
BothTBL#andWP#pinsmustbesettotheirrequiredprotectionstatespriortostartingaProgramorEraseoperation.
AlogiclevelchangeoccurringattheTBL#orWP#pinduringaProgramorEraseoperationcouldcauseunpredictableresults.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14108MbitLPCFlashSST49LF080ADataSheetINIT#,RST#AVILonINIT#orRST#pininitiatesadevicereset.
INIT#andRST#pinshavethesamefunctioninternally.
ItisrequiredtodriveINIT#orRST#pinslowduringasystemresettoensureproperCPUinitialization.
DuringaReadoperation,drivingINIT#orRST#pinslowdeselectsthedeviceandplacestheoutputdrivers,LAD[3:0],inahigh-impedancestate.
TheresetsignalmustbeheldlowforaminimaldurationoftimeTRSTP.
AresetlatencywilloccurifaresetprocedureisperformedduringaProgramorEraseoperation.
SeeTable19,ResetTimingParametersformoreinforma-tion.
AdeviceresetduringanactiveProgramorErasewillaborttheoperationandmemorycon-tentsmaybecomeinvalidduetodatabeingalteredorcorruptedfromanincompleteEraseorProgramoperation.
SystemMemoryMappingTheLPCinterfaceprotocolhasaddresslengthof32-bitor4GByte.
TheSST49LF080AwillrespondtoaddressesintherangeasspecifiedinTable4.
Referto"MultipleDeviceSelection"sectionformoredetailonstrappingmultipleSST49LF080Adevicestoincreasememorydensitiesinasystemand"Registers"sectiononvalidregisteraddresses.
Table4:AddressDecodingRangeIDStrappingDeviceAccessAddressRangeMemorySizeDevice#0-3MemoryAccessFFFFFFFFH:FFC00000H4MByteRegisterAccessFFBFFFFFH:FF800000H4MByteDevice#4-7MemoryAccessFF7FFFFFH:FF400000H4MByteRegisterAccessFF3FFFFFH:FF000000H4MByteDevice#8-11MemoryAccessFEFFFFFFH:FEC00000H4MByteRegisterAccessFEBFFFFFH:FE800000H4MByteDevice#12-15MemoryAccessFE7FFFFFH:FE400000H4MByteRegisterAccessFE3FFFFFH:FE000000H4MByteDevice#011.
Fordevice#0(BootDevice),SST49LF080Adecodesthephysicaladdressesofthetop2blocks(includingBootBlock)bothatsystemmemoryrangesFFFFFFFFHtoFFFE0000Hand000FFFFFHto000E0000H.
MemoryAccess000FFFFFH:000E0000H128KByteT4.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14118MbitLPCFlashSST49LF080ADataSheetFigure5:LPCReadCycleWaveformTable5:LPCReadCycleClockCycleFieldNameFieldContentsLAD[3:0]1LAD[3:0]DirectionComments1START0000INLFRAME#mustbeactive(low)fortheparttorespond.
Onlythelaststartfield(beforeLFRAME#transitionshigh)shouldberecognized.
2CYCTYPE+DIR010XINIndicatesthetypeofcycle.
Bits3:2mustbe"01b"formemorycycle.
Bit1indicatesthetypeoftransfer"0"forRead.
Bit0isreserved.
3-10ADDRESSYYYYINAddressPhaseforMemoryCycle.
LPCprotocolsup-portsa32-bitaddressphase.
YYYYisonenibbleoftheentireaddress.
Addressesaretransferredmost-signifi-cantnibblefist.
SeeTable3foraddressbitsdefinitionandTable4forvalidmemoryaddressrange.
11TAR01111INthenFloatInthisclockcycle,thehosthasdriventhebustoall1sandthenfloatsthebus.
Thisisthefirstpartofthebus"turnaroundcycle.
"12TAR11111(float)FloatthenOUTTheSST49LF080Atakescontrolofthebusduringthiscycle13SYNC0000OUTTheSST49LF080Aoutputsthevalue0000bindicatingthatdatawillbeavailableduringthenextclockcycle.
14DATAZZZZOUTThisfieldistheleast-significantnibbleofthedatabyte.
15DATAZZZZOUTThisfieldisthemost-significantnibbleofthedatabyte.
16TAR01111OUTthenFloatInthisclockcycle,theSST49LF080Ahasdriventhebustoall1sandthenfloatsthebus.
Thisisthefirstpartofthebus"turnaroundcycle.
"17TAR11111(float)FloatthenINThehosttakescontrolofthebusduringthiscycleT5.
0250261.
Fieldcontentsarevalidontherisingedgeofthepresentclockcycle.
1235F04.
0LCLKCE#LFRAME#LAD[3:0]0000b010XbA[23:20]A[19:16]A[3:0]A[7:4]A[11:8]A[15:12]1111bTri-State2ClocksTAR0LoadAddressin8ClocksAddress1Clock1ClockStartCYCTYPE+DIRTAR1ClockSyncDataDataOut2Clocks0000bD[7:4]D[3:0]A[31:28]A[27:24]TAR12014SiliconStorageTechnology,Inc.
DS20005086B11/14128MbitLPCFlashSST49LF080ADataSheetFigure6:LPCWriteCycleWaveformTable6:LPCWriteCycleClockCycleFieldNameFieldContentsLAD[3:0]1LAD[3:0]DirectionComments1START0000INLFRAME#mustbeactive(low)fortheparttorespond.
Onlythelaststartfield(beforeLFRAME#transitionshigh)shouldberecog-nized.
2CYCTYPE+DIR011XINIndicatesthetypeofcycle.
Bits3:2mustbe"01b"formemorycycle.
Bit1indicatesthetypeoftransfer"1"forWrite.
Bit0isreserved.
3-10ADDRESSYYYYINAddressPhaseforMemoryCycle.
LPCprotocolsupportsa32-bitaddressphase.
YYYYisonenibbleoftheentireaddress.
Addressesaretransferredmost-significantnibblefirst.
SeeTable3foraddressbitsdefinitionandTable4forvalidmemoryaddressrange.
11DATAZZZZINThisfieldistheleast-significantnibbleofthedatabyte.
12DATAZZZZINThisfieldisthemost-significantnibbleofthedatabyte.
13TAR01111INthenFloatInthisclockcycle,thehosthasdriventhebustoall'1'sandthenfloatsthebus.
Thisisthefirstpartofthebus"turnaroundcycle.
"14TAR11111(float)FloatthenOUTTheSST49LF080Atakescontrolofthebusdur-ingthiscycle.
15SYNC0000OUTTheSST49LF080Aoutputsthevalues0000,indicat-ingthatithasreceiveddataoraflashcommand.
16TAR01111OUTthenFloatInthisclockcycle,theSST49LF080Ahasdriventhebustoall'1'sandthenfloatsthebus.
Thisisthefirstpartofthebus"turnaroundcycle.
"17TAR11111(float)FloatthenINHostresumescontrolofthebusduringthiscycle.
T6.
0250261.
Fieldcontentsarevalidontherisingedgeofthepresentclockcycle.
1235F05.
0LFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]A[3:0]A[7:4]A[11:8]A[15:12]1111bTri-State2ClocksTAR0LoadAddressin8ClocksAddress1Clock1ClockStartCYCTYPE+DIRTAR1ClockSyncDataLoadDatain2Clocks0000bD[7:4]D[3:0]LCLKCE#A[31:28]A[27:24]DataTAR12014SiliconStorageTechnology,Inc.
DS20005086B11/14138MbitLPCFlashSST49LF080ADataSheetResponseToInvalidFieldsDuringLPCRead/Writeoperations,theSST49LF080Awillnotexplicitlyindicatethatithasreceivedinvalidfieldsequences.
Theresponsetospecificinvalidfieldsorsequencesisasfollows:Addressoutofrange:TheSST49LF080AwillonlyrespondtoaddressrangesasspecifiedinTable4.
IDmismatch:IDinformationisincludedineveryaddresscycle.
TheSST49LF080AwillcompareIDbitsintheaddressfieldwiththehardwareIDstrapping.
Ifthereisamis-match,thedevicewillignorethecycle.
SeeMultipleDeviceSelectionsectionfordetails.
OncevalidSTART,CYCTYPE+DIR,validaddressrangeandIDbitsarereceived,theSST49LF080Awillalwayscompletethebuscycle.
However,ifthedeviceisbusyperformingaflashEraseorProgramoperation,nonewinternalWritecommand(memorywriteorregisterwrite)willbeexecuted.
AslongasthestatesofLAD[3:0]andLAD[4]areknown,theresponseoftheSST49LF080AtosignalsreceivedduringtheLPCcycleshouldbepredictable.
AbortMechanismIfLFRAME#isdrivenlowforoneormoreclockcyclesafterthestartofanLPCcycle,thecyclewillbeterminated.
ThehostmaydrivetheLAD[3:0]with'1111b'(ABORTnibble)toreturntheinterfacetoreadymode.
TheABORTonlyaffectsthecurrentbuscycle.
Foramulti-cyclecommandsequence,suchastheEraseorProgramSDPcommands,ABORTdoesn'tinterrupttheentirecommandsequence,butonlythecurrentbuscycleofthecommandsequence.
Thehostcanre-sendthebuscycleandcontinuetheSDPcommandsequenceafterthedeviceisreadyagain.
WriteOperationStatusDetectionTheSST49LF080AdeviceprovidestwosoftwaremeanstodetectthecompletionofaWrite(ProgramorErase)cycle,inordertooptimizethesystemWritecycletime.
Thesoftwaredetectionincludestwostatusbits:Data#Polling,D[7],andToggleBit,D[6].
TheEnd-of-WritedetectionmodeisincorporatedintotheLPCReadCycle.
Theactualcompletionofthenonvolatilewriteisasynchronouswiththesys-tem;therefore,eitheraData#PollingorToggleBitreadmaybesimultaneouswiththecompletionoftheWritecycle.
Ifthisoccurs,thesystemmaypossiblygetanerroneousresult,i.
e.
,validdatamayappeartoconflictwitheitherD[7]orD[6].
Inordertopreventspuriousrejection,ifanerroneousresultoccurs,thesoftwareroutineshouldincludealooptoreadtheaccessedlocationanadditionaltwo(2)times.
Ifbothreadsarevalid,thenthedevicehascompletedtheWritecycle,otherwisetherejectionisvalid.
Data#PollingWhentheSST49LF080AdeviceisintheinternalProgramoperation,anyattempttoreadD[7]willpro-ducethecomplementofthetruedata.
OncetheProgramoperationiscompleted,D[7]willproducetruedata.
NotethateventhoughD[7]mayhavevaliddataimmediatelyfollowingthecompletionofaninternalWriteoperation,theremainingdataoutputsmaystillbeinvalid:validdataontheentiredatabuswillappearinsubsequentsuccessiveReadcyclesafteranintervalof1s.
DuringinternalEraseoperation,anyattempttoreadD[7]willproducea'0'.
OncetheinternalEraseoperationiscompleted,D[7]willproducea'1'.
ProperstatuswillnotbegivenusingData#Pollingiftheaddressisintheinvalidrange.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14148MbitLPCFlashSST49LF080ADataSheetToggleBitDuringtheinternalProgramorEraseoperation,anyconsecutiveattemptstoreadD[6]willproducealternating0sand1s,i.
e.
,togglingbetween0and1.
WhentheinternalProgramorEraseoperationiscompleted,thetogglingwillstop.
MultipleDeviceSelectionMultipleLPCflashdevicesmaybestrappedtoincreasememorydensitiesinasystem.
ThefourIDpins,ID[3:0],allowupto16devicestobeattachedtothesamebusbyusingdifferentIDstrappinginasystem.
BIOSsupport,busloading,ortheattachingbridgemaylimitthisnumber.
ThebootdevicemusthaveanIDof0(determinedbyID[3:0]);subsequentdevicesuseincrementalnumbering.
Equaldensitymustbeusedwithmultipledevices.
Whenusedasabootdevice,ID[3:0]mustbestrappedas0000;allsubsequentdevicesshoulduseasequentialup-countstrapping(i.
e.
0001,0010,0011,etc.
).
Withthehardwarestrapping,IDinforma-tionisincludedineveryLPCaddressmemorycycle.
TheIDbitsintheaddressfieldareinverseofthehardwarestrapping.
Theaddressbits[A24:A23,A21:A20]areusedtoselectthedevicewithproperIDs.
SeeTable7forIDs.
TheSST49LF080AwillcomparethesebitswithID[3:0]'sstrappingvalues.
Ifthereisamismatch,thedevicewillignoretheremainderofthecycle.
Table7:MultipleDeviceSelectionConfigurationDevice#HardwareStrappingAddressBitsDecodingID[3:0]A24A23A21A200(Bootdevice)00001111100011110200101101300111100401001011501011010601101001701111000810000111910010110101010010111101101001211000011131101001014111000011511110000T7.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14158MbitLPCFlashSST49LF080ADataSheetRegistersTherearetworegistersavailableontheSST49LF080A,theGeneralPurposeInputsRegisters(GPI_REG)andtheJEDECIDRegisters.
SincemultipleLPCmemorydevicesmaybeusedtoincreasememorydensities,theseregistersappearatitsrespectiveaddresslocationinthe4GBytesystemmemorymap.
Unusedregisterlocationswillreadas00H.
AnyattempttoreadregistersduringinternalWriteoperationwillrespondas"Writeoperationstatusdetection"(Data#PollingorToggleBit).
AnyattempttowriteanyregistersduringinternalWriteoperationwillbeignored.
Table9listsGPI_REGandJEDECIDaddresslocationsforSST49LF080Awithitsrespectivedevicestrapping.
Table8:GeneralPurposeInputsRegisterBitFunctionPin#32-PLCC32-TSOP7:5Reserved--4GPI[4]Readsstatusofgeneralpurposeinputpin3063GPI[3]Readsstatusofgeneralpurposeinputpin3112GPI[2]Readsstatusofgeneralpurposeinputpin4121GPI[1]Readsstatusofgeneralpurposeinputpin5130GPI[0]Readsstatusofgeneralpurposeinputpin614T8.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14168MbitLPCFlashSST49LF080ADataSheetGeneralPurposeInputsRegisterTheGPI_REG(GeneralPurposeInputsRegister)passesthestateofGPI[4:0]pinsatpower-upontheSST49LF080A.
ItisrecommendedthattheGPI[4:0]pinsbeinthedesiredstatebeforeLFRAME#isbroughtlowforthebeginningofthenextbuscycle,andremaininthatstateuntiltheendofthecycle.
Thereisnodefaultvaluesincethisisapass-throughregister.
SeetheGeneralPurposeInputsRegis-tertablefortheGPI_REGbitsandfunction,andTable9formemoryaddresslocationsforitsrespec-tivedevicestrapping.
JEDECIDRegistersTheJEDECIDregistersidentifythedeviceasSST49LF080AandmanufacturerasSSTinLPCmode.
SeeTable9formemoryaddresslocationsforitsrespectiveJEDECIDlocation.
Table9:MemoryMapRegisterAddressesforSST49LF080ADevice#HardwareStrappingID[3:0]GPI_REGJEDECIDManufacturerDevice0(Bootdevice)0000FFBC0100HFFBC0000HFFBC0001H10001FFAC0100HFFAC0000HFFAC0001H20010FF9C0100HFF9C0000HFF9C0001H30011FF8C0100HFF8C0000HFF8C0001H40100FF3C0100HFF3C0000HFF3C0001H50101FF2C0100HFF2C0000HFF2C0001H60110FF1C0100HFF1C0000HFF1C0001H70111FF0C0100HFF0C0000HFF0C0001H81000FEBC0100HFEBC0000HFEBC0001H91001FEAC0100HFEAC0000HFEAC0001H101010FE9C0100HFE9C0000HFE9C0001H111011FE8C0100HFE8C0000HFE8C0001H121100FE3C0100HFE3C0000HFE3C0001H131101FE2C0100HFE2C0000HFE2C0001H141110FE1C0100HFE1C0000HFE1C0001H151111FE0C0100HFE0C0000HFE0C0001HT9.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14178MbitLPCFlashSST49LF080ADataSheetParallelProgrammingModeDeviceOperationCommandsareusedtoinitiatethememoryoperationfunctionsofthedevice.
ThedataportionofthesoftwarecommandsequenceislatchedontherisingedgeofWE#.
DuringthesoftwarecommandsequencetherowaddressislatchedonthefallingedgeofR/C#andthecolumnaddressislatchedontherisingedgeofR/C#.
ResetDrivingtheRST#lowwillinitiateahardwareresetoftheSST49LF080A.
SeeTable25forResettimingparametersandFigure17forResettimingdiagram.
ReadTheReadoperationoftheSST49LF080AdeviceiscontrolledbyOE#.
OE#istheoutputcontrolandisusedtogatedatafromtheoutputpins.
RefertotheReadcycletimingdiagram,Figure18,forfurtherdetails.
Byte-ProgramOperationTheSST49LF080Adeviceisprogrammedonabyte-by-bytebasis.
Beforeprogramming,onemustensurethatthesectorinwhichthebyteisprogrammedisfullyerased.
TheByte-Programoperationisinitiatedbyexecutingafour-bytecommandloadsequenceforSoftwareDataProtectionwithaddress(BA)anddatainthelastbytesequence.
DuringtheByte-Programoperation,therowaddress(A10-A0)islatchedonthefallingedgeofR/C#andthecolumnaddress(A21-A11)islatchedontherisingedgeofR/C#.
ThedatabusislatchedontherisingedgeofWE#.
TheProgramoperation,onceinitiated,willbecompleted,within20s.
SeeFigure22forProgramoperationtimingdiagramandFigure34foritsflowchart.
DuringtheProgramoperation,theonlyvalidreadsareData#PollingandToggleBit.
DuringtheinternalProgramoperation,thehostisfreetoperformadditionaltasks.
Anycommandswrittendur-ingtheinternalProgramoperationwillbeignored.
Sector-EraseOperationTheSector-Eraseoperationallowsthesystemtoerasethedeviceonasector-by-sectorbasis.
Thesectorarchitectureisbasedonuniformsectorsizeof4KByte.
TheSector-Eraseoperationisinitiatedbyexecutingasix-bytecommandloadsequenceforSoftwareDataProtectionwithSector-Erasecom-mand(30H)andsectoraddress(SA)inthelastbuscycle.
TheinternalEraseoperationbeginsafterthesixthWE#pulse.
TheEnd-of-ErasecanbedeterminedusingeitherData#PollingorToggleBitmethods.
SeeFigure23forSector-Erasetimingwaveforms.
AnycommandswrittenduringtheSector-Eraseoperationwillbeignored.
Block-EraseOperationTheBlock-EraseOperationallowsthesystemtoerasethedevicein64KByteuniformblocksizefortheSST49LF080A.
TheBlock-Eraseoperationisinitiatedbyexecutingasix-bytecommandloadsequenceforSoftwareDataProtectionwithBlock-Erasecommand(50H)andblockaddress.
TheinternalBlock-EraseoperationbeginsafterthesixthWE#pulse.
TheEnd-of-ErasecanbedeterminedusingeitherData#PollingorToggleBitmethods.
SeeFigure24forBlock-Erasetimingwaveforms.
AnycommandswrittenduringtheBlock-Eraseoperationwillbeignored.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14188MbitLPCFlashSST49LF080ADataSheetChip-EraseOperationTheSST49LF080AdevicesprovideaChip-Eraseoperation,whichallowstheusertoerasetheentirememoryarraytothe"1s"state.
Thisisusefulwhentheentiredevicemustbequicklyerased.
TheChip-Eraseoperationisinitiatedbyexecutingasix-byteSoftwareDataProtectioncommandsequencewithChip-Erasecommand(10H)withaddress5555Hinthelastbytesequence.
TheinternalEraseoperationbeginswiththerisingedgeofthesixthWE#.
DuringtheinternalEraseoperation,theonlyvalidreadisToggleBitorData#Polling.
SeeTable11forthecommandsequence,Figure25forChip-Erasetimingdiagram,andFigure37fortheflowchart.
AnycommandswrittenduringtheChip-Eraseoperationwillbeignored.
WriteOperationStatusDetectionTheSST49LF080AdevicesprovidetwosoftwaremeanstodetectthecompletionofaWrite(ProgramorErase)cycle,inordertooptimizethesystemWritecycletime.
Thesoftwaredetectionincludestwostatusbits:Data#PollingD[7]andToggleBitD[6].
TheEnd-of-WritedetectionmodeisenabledaftertherisingedgeofWE#whichinitiatestheinternalProgramorEraseoperation.
Theactualcompletionofthenonvolatilewriteisasynchronouswiththesystem;therefore,eitheraData#PollingorToggleBitreadmaybesimultaneouswiththecompletionoftheWritecycle.
Ifthisoccurs,thesystemmaypossiblygetanerroneousresult,i.
e.
,validdatamayappeartoconflictwitheitherD[7]orD[6].
Inordertopreventspuriousrejection,ifanerroneousresultoccurs,thesoftwareroutineshouldincludealooptoreadtheaccessedlocationanadditionaltwo(2)times.
Ifbothreadsarevalid,thenthedevicehascompletedtheWritecycle,otherwisetherejectionisvalid.
Data#Polling(DQ7)WhentheSST49LF080AdeviceisintheinternalProgramoperation,anyattempttoreadDQ7willpro-ducethecomplementofthetruedata.
OncetheProgramoperationiscompleted,DQ7willproducetruedata.
NotethateventhoughDQ7mayhavevaliddataimmediatelyfollowingthecompletionofaninternalWriteoperation,theremainingdataoutputsmaystillbeinvalid:validdataontheentiredatabuswillappearinsubsequentsuccessiveReadcyclesafteranintervalof1s.
DuringinternalEraseoperation,anyattempttoreadDQ7willproducea'0'.
OncetheinternalEraseoperationiscompleted,DQ7willproducea'1'.
TheData#PollingisvalidaftertherisingedgeoffourthWE#pulseforProgramoperation.
ForSector-,Block-,orChip-Erase,theData#PollingisvalidaftertherisingedgeofsixthWE#pulse.
SeeFigure20forData#PollingtimingdiagramandFigure35foraflowchart.
Propersta-tuswillnotbegivenusingData#Pollingiftheaddressisintheinvalidrange.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14198MbitLPCFlashSST49LF080ADataSheetToggleBit(DQ6)DuringtheinternalProgramorEraseoperation,anyconsecutiveattemptstoreadDQ6willproducealternating'0'sand'1's,i.
e.
,togglingbetween0and1.
WhentheinternalProgramorEraseoperationiscompleted,thetogglingwillstop.
Thedeviceisthenreadyforthenextoperation.
TheToggleBitisvalidaftertherisingedgeoffourthWE#pulseforProgramoperation.
ForSector-,Block-,orChip-Erase,theToggleBitisvalidaftertherisingedgeofsixthWE#pulse.
SeeFigure21forToggleBittim-ingdiagramandFigure35foraflowchart.
DataProtection(PPMode)TheSST49LF080Adevicesprovidebothhardwareandsoftwarefeaturestoprotectnonvolatiledatafrominadvertentwrites.
HardwareDataProtectionNoise/GlitchProtection:AWE#pulseoflessthan5nswillnotinitiateaWritecycle.
VDDPowerUp/DownDetection:TheWriteoperationisinhibitedwhenVDDislessthan1.
5V.
WriteInhibitMode:ForcingOE#low,WE#highwillinhibittheWriteoperation.
Thispreventsinadver-tentwritesduringpower-uporpower-down.
SoftwareDataProtection(SDP)TheSST49LF080AprovidestheJEDECapprovedSoftwareDataProtectionschemeforalldataalter-ationoperation,i.
e.
,ProgramandErase.
AnyProgramoperationrequirestheinclusionofaseriesofthree-bytesequence.
Thethree-byteloadsequenceisusedtoinitiatetheProgramoperation,provid-ingoptimalprotectionfrominadvertentWriteoperations,e.
g.
,duringthesystempower-uporpower-down.
AnyEraseoperationrequirestheinclusionofasix-byteloadsequence.
Table10:OperationModesSelection(PPMode)ModeRST#OE#WE#DQAddressReadVIHVILVIHDOUTAINProgramVIHVIHVILDINAINEraseVIHVIHVILX11.
XcanbeVILorVIH,butnoothervalue.
SectororBlockaddress,XXHforChip-EraseResetVILXXHighZXWriteInhibitVIHXVILXXVIHHighZ/DOUTHighZ/DOUTXXProductIdentificationVIHVILVIHManufacturer'sID(BFH)DeviceID22.
DeviceID=5BHforSST49LF080ASeeTable11T10.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14208MbitLPCFlashSST49LF080ADataSheetSoftwareCommandSequenceTable11:SoftwareCommandSequenceCommandSequence1st1Cycle1.
LPCmodeuseconsecutiveWritecyclestocompleteacommandsequence;PPmodeuseconsecutivebuscyclestocompleteacommandsequence.
2nd1Cycle3rd1Cycle4th1Cycle5th1Cycle6th1CycleAddr22.
YYYY=A[31:16].
InLPCmode,duringSDPcommandsequence,YYYYmustbewithinmemoryaddressrangespeci-fiedinTable4.
InPPmode,YYYYcanbeVILorVIH,butnoothervalue.
DataAddr2DataAddr2DataAddr2DataAddr2DataAddr2DataByte-ProgramYYYY5555HAAHYYYY2AAAH55HYYYY5555HA0HPA33.
PA=ProgramByteaddressDataSector-EraseYYYY5555HAAHYYYY2AAAH55HYYYY5555H80HYYYY5555HAAHYYYY2AAAH55HSAX44.
SAXforSector-EraseAddress30HBlock-EraseYYYY5555HAAHYYYY2AAAH55HYYYY5555H80HYYYY5555HAAHYYYY2AAAH55HBAX55.
BAXforBlock-EraseAddress50HChip-Erase66.
Chip-EraseissupportedinPPmodeonlyYYYY5555HAAHYYYY2AAAH55HYYYY5555H80HYYYY5555HAAHYYYY2AAAH55HYYYY5555H10HSoftwareIDEntryYYYY5555HAAHYYYY2AAAH55HYYYY5555H90HReadID77.
SSTManufacturer'sID=BFH,isreadwithA0=0.
WithA19-A1=0;SST49LF080ADeviceID=5BH,isreadwithA0=1.
SoftwareIDExit88.
BothSoftwareIDExitoperationsareequivalentXXXXXXXXHF0HSoftwareIDExit8YYYY5555HAAHYYYY2AAAH55HYYYY5555HF0HT11.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14218MbitLPCFlashSST49LF080ADataSheetFigure7:ProgramCommandSequence(LPCMode)1235F06.
0LCLKLFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]0101b0101b0101b1010b0101b1010bTri-StateTARLoadAddressYYYY5555Hin8ClocksWritethe1stcommandtothedeviceinLPCmode.
Address11Clock1Clock1stStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadDataAAHin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]1010b1010b1010b0101b0010b0101bTri-StateTARLoadAddressYYYY2AAAHin8ClocksWritethe2ndcommandtothedeviceinLPCmode.
Address11Clock1Clock2ndStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadData55Hin2Clocks1111b0000bLCLKLFRAME#LoadAddressYYYY5555Hin8ClocksWritethe3rdcommandtothedeviceinLPCmode.
1Clock1Clock3rdStart1Clock1Clock2ClocksLoadDataA0Hin2ClocksLCLKLFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]A[11:8]A[7:4]A[3:0]D[7:4]A[15:12]D[3:0]Tri-StateTARLoadAinin8ClocksWritethe4thcommand(targetlocationstobeprogrammed)tothedeviceinLPCmode.
Address11Clock1Clock4thStartMemoryWriteCycleTARSyncDataInternalprogramstartInternalprogramstart1Clock2ClocksLoadDatain2Clocks1111b0000bCE#CE#CE#CE#LAD[3:0]0000b011XbA[23:20]A[19:16]0101b0101b0101b1010b0101b0000bTri-StateTARAddress1TARSyncDataStartnextCommand1111b0000bA[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]Note:1.
AddressmustbewithinmemoryaddressrangespecifiedinTable4.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14228MbitLPCFlashSST49LF080ADataSheetFigure8:Data#PollingCommandSequence(LPCMode)1235F07.
00000b011XbA[11:8]A[7:4]A[3:0]Dn[7:4]A[15:12]D[3:0]Tri-StateTARLoadAddressin8ClocksWritethelastcommand(ProgramorErase)tothedeviceinLPCmode.
Address11Clock1Clock1stStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadDatain2Clocks1111b0000b0000bLAD[3:0]ReadtheDQ7toseeifinternalwritecompleteornot.
LCLKLFRAME#LAD[3:0]0000b010XbA[11:8]A[7:4]A[3:0]D7,xxxA[15:12]XXXXbTri-StateTARLoadAddressin8ClocksWheninternalwritecomplete,theDQ7willequaltoD7.
Address11Clock1ClockStartMemoryReadCycleTARSyncDataNextstart1ClockDataout2Clocks1Clock2Clocks1111b0000b0000bLFRAME#LCLK0000b010XbA[11:8]A[7:4]A[3:0]D7#,xxxA[15:12]XXXXbTri-StateTARLoadAddressin8ClocksAddress11Clock1ClockStartMemoryReadCycleTARSyncDataNextstart1ClockDataout2Clocks1Clock2Clocks1111b0000b0000bCE#CE#A[23:20]A[19:16]A[23:20]A[19:16]A[23:20]A[19:16]LFRAME#LAD[3:0]LCLKCE#A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]Note:1.
AddressmustbewithinmemoryaddressrangespecifiedinTable4.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14238MbitLPCFlashSST49LF080ADataSheetFigure9:ToggleBitCommandSequence(LPCMode)1235F08.
0LFRAME#LAD[3:0]0000b011XbA[11:8]A[7:4]A[3:0]D[7:4]A[15:12]D[3:0]Tri-StateTARLoadAddressin8ClocksWritethelastcommand(ProgramorErase)tothedeviceinLPCmode.
Address11Clock1Clock1stStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadDatain2Clocks1111b0000b0000bLCLKLFRAME#LAD[3:0]0000b010XbX,D6#,XXbXXXXbTri-StateTARLoadAddressin8ClocksReadtheDQ6toseeifinternalwritecompleteornot.
Address11Clock1ClockStartMemoryReadCycleTARSyncDataNextstart1ClockDataout2Clocks1Clock2Clocks1111b0000b0000bLCLKLFRAME#LAD[3:0]0000b010XbX,D6,XXbXXXXbTri-StateTARLoadAddressin8ClocksWheninternalwritecomplete,theDQ6willstoptoggle.
Address11Clock1ClockStartMemoryReadCycleTARSyncDataNextstart1ClockDataout2Clocks1Clock2Clocks1111b0000b0000bCE#CE#LCLKCE#A[11:8]A[7:4]A[3:0]A[15:12]A[11:8]A[7:4]A[3:0]A[15:12]A[23:20]A[19:16]A[23:20]A[19:16]A[23:20]A[19:16]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]Note:1.
AddressmustbewithinmemoryaddressrangespecifiedinTable4.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14248MbitLPCFlashSST49LF080ADataSheetFigure10:Sector-EraseCommandSequence(LPCMode)1235F12.
0LFRAME#LAD[3:0]0000b011Xb0101b0101b0101b1010b0101b1010bTri-StateTARLoadAddressYYYY5555Hin8ClocksWritethe1stcommandtothedeviceinLPCmode.
Address11Clock1Clock1stStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadDataAAHin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011Xb1010b1010b1010b0101b0010b0101bTri-StateTARLoadAddressYYYY2AAAHin8ClocksWritethe2ndcommandtothedeviceinLPCmode.
Address11Clock1Clock2ndStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadData55Hin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011Xb0101b0101b0101b1000b0101b0000bTri-StateTARLoadAddressYYYY5555Hin8ClocksWritethe3rdcommandtothedeviceinLPCmode.
Address11Clock1Clock3rdStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadData80Hin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011Xb0101b0101b0101b1010b0101b1010bTri-StateTARLoadAddressYYYY5555Hin8ClocksWritethe4thcommandtothedeviceinLPCmode.
Address11Clock1Clock4thStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadDataAAHin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011Xb1010b1010b1010b0101b0010b0101bXXXXbXXXXbXXXXb0011bSAX0000bTri-StateTARLoadAddressYYYY2AAAin8ClocksHLoadSectorAddressin8ClocksWritethe5thcommandtothedeviceinLPCmode.
Address11Clock1Clock5thMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadData55Hin2ClocksLoadData"30"in2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011XbTri-StateTARWritethe6thcommand(targetsectortobeerased)tothedeviceinLPCmode.
SAX=SectorAddressAddress11Clock1Clock6thStartMemoryWriteCycleTARSyncDataInternalerasestartInternalerasestart1Clock2Clocks1111b0000bCE#CE#CE#CE#CE#LCLKCE#A[23:20]A[19:16]A[23:20]A[19:16]A[23:20]A[19:16]A[23:20]A[19:16]A[23:20]A[19:16]A[23:20]A[19:16]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]2014SiliconStorageTechnology,Inc.
DS20005086B11/14258MbitLPCFlashSST49LF080ADataSheetFigure11:Block-EraseCommandSequence(LPCMode)1235F10.
0LFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]0101b0101b0101b1010b0101b1010bTri-StateTARLoadAddressYYYY5555Hin8ClocksWritethe1stcommandtothedeviceinLPCmode.
Address11Clock1Clock1stStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadDataAAHin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]1010b1010b1010b0101b0010b0101bTri-StateTARLoadAddressYYYY2AAAHin8ClocksWritethe2ndcommandtothedeviceinLPCmode.
Address11Clock1Clock2ndStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadData55Hin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]0101b0101b0101b1000b0101b0000bTri-StateTARLoadAddressYYYY5555Hin8ClocksWritethe3rdcommandtothedeviceinLPCmode.
Address11Clock1Clock3rdStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadData80Hin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]0101b0101b0101b1010b0101b1010bTri-StateTARLoadAddressYYYY5555Hin8ClocksWritethe4thcommandtothedeviceinLPCmode.
Address11Clock1Clock4thStartMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadDataAAHin2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011XbA[23:20]A[19:16]1010b1010b1010b0101b0010b0101bA[19:16]XXXXbXXXXbXXXXb0101bBAX0000bTri-StateTARLoadAddressYYYY2AAAHin8ClocksLoadBlockAddressin8ClocksWritethe5thcommandtothedeviceinLPCmode.
Address11Clock1Clock5thMemoryWriteCycleTARSyncDataStartnextCommand1Clock1Clock2ClocksLoadData55Hin2ClocksLoadData"50"in2Clocks1111b0000bLCLKLFRAME#LAD[3:0]0000b011XbA[23:20]Tri-StateTARWritethe6thcommand(targetsectortobeerased)tothedeviceinLPCmode.
BAX=BlockAddressAddress11Clock1Clock6thStartMemoryWriteCycleTARSyncDataInternalerasestartInternalerasestart1Clock2Clocks1111b0000bCE#CE#CE#CE#CE#LCLKCE#A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]A[31:28]A[27:24]Note:1.
AddressmustbewithinmemoryaddressrangespecifiedinTable4.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14268MbitLPCFlashSST49LF080ADataSheetFigure12:RegisterReadoutCommandSequence(LPCMode)DS200050860000b010Xb1111bTri-StateTARLoadAddressin8ClocksAddress11Clock1ClockStartMemoryReadCycleTARSyncDataStartnext1ClockDataout2Clocks1Clock2Clocks0000bD[3:0]D[7:4]0000b1235F11.
0LFRAME#LAD[3:0]LCLKCE#A[23:20]A[19:16]A[11:8]A[7:4]A[3:0]A[15:12]A[31:28]A[27:24]Note:1.
SeeTable9forregisteraddresses.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14278MbitLPCFlashSST49LF080ADataSheetElectricalSpecificationsTheACandDCspecificationsfortheLPCinterfacesignals(LA0[3:0],LFRAME,LCLCKandRST#)asdefinedinSection4.
2.
2.
4ofthePCIlocalBusspecification,Rev.
2.
1.
RefertoTable14fortheDCvolt-ageandcurrentspecifications.
RefertoTables18through21andTables23through25fortheACtim-ingspecificationsforClock,Read,Write,andResetoperations.
AbsoluteMaximumStressRatings(Appliedconditionsgreaterthanthoselistedunder"AbsoluteMaximumStressRatings"maycausepermanentdamagetothedevice.
Thisisastressratingonlyandfunctionaloperationofthedeviceattheseconditionsorconditionsgreaterthanthosedefinedintheoperationalsectionsofthisdatasheetisnotimplied.
Exposuretoabsolutemaximumstressratingcon-ditionsmayaffectdevicereliability.
)TemperatureUnderBias55°Cto+125°CStorageTemperature65°Cto+150°CD.
C.
VoltageonAnyPintoGroundPotential0.
5VtoVDD+0.
5VTransientVoltage(Commercial0°Cto+85°C3.
0-3.
6VT12.
125026Table13:ACConditionsofTest11.
SeeFigures28and29InputRise/FallTimeOutputLoad3nsCL=30pFT13.
1250262014SiliconStorageTechnology,Inc.
DS20005086B11/14288MbitLPCFlashSST49LF080ADataSheetDCCharacteristicsTable14:DCOperatingCharacteristics(AllInterfaces)SymbolParameterLimitsTestConditionsMinMaxUnitsIDD11.
IDDactivewhileaReadorWrite(ProgramorErase)operationisinprogress.
ActiveVDDCurrentLCLK(LPCmode)andAddressInput(PPmode)=VILT/VIHTatf=33MHz(LPCmode)or1/TRCmin(PPMode)Allotherinputs=VILorVIHRead12mAAlloutputs=open,VDD=VDDMaxWrite24mASeeNote22.
ForPPMode:OE#=WE#=VIH;ForLPCMode:f=1/TRCmin,LFRAME#=VIH,CE#=VIL.
ISBStandbyVDDCurrent(LPCInterface)100ALCLK(LPCmode)andAddressInput(PPmode)=VILT/VIHTatf=33MHz(LPCmode)or1/TRCmin(PPMode)LFRAME#=0.
9VDD,f=33MHz,CE#=0.
9VDD,VDD=VDDMax,Allotherinputs0.
9VDDor0.
1VDDIRY33.
ThedeviceisinReadymodewhennoactivityisontheLPCbus.
ReadyModeVDDCur-rent(LPCInterface)10mALCLK(LPCmode)andAddressInput(PPmode)=VILT/VIHTatf=33MHz(LPCmode)or1/TRCmin(PPMode)LFRAME#=VIL,f=33MHz,VDD=VDDMaxAllotherinputs0.
9VDDor0.
1VDDIIInputCurrentforModeandID[3:0]pins200AVIN=GNDtoVDD,VDD=VDDMaxILIInputLeakageCurrent1AVIN=GNDtoVDD,VDD=VDDMaxILOOutputLeakageCur-rent1AVOUT=GNDtoVDD,VDD=VDDMaxVIHIINIT#InputHighVolt-age1.
1VDD+0.
5VVDD=VDDMaxVILIINIT#InputLowVolt-age-0.
50.
4VVDD=VDDMinVILInputLowVoltage-0.
50.
3VDDVVDD=VDDMinVIHInputHighVoltage0.
5VDDVDD+0.
5VVDD=VDDMaxVOLOutputLowVoltage0.
1VDDVIOL=1500A,VDD=VDDMinVOHOutputHighVoltage0.
9VDDVIOH=-500A,VDD=VDDMinT14.
025026Table15:RecommendedSystemPower-upTimingsSymbolParameterMinimumUnitsTPU-READ11.
ThisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthisparameterPower-uptoReadOperation100sTPU-WRITE1Power-uptoWriteOperation100sT15.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14298MbitLPCFlashSST49LF080ADataSheetFigure13:LCLKWaveform(LPCMode)Table16:PinCapacitance(VDD=3.
3V,Ta=25°C,f=1Mhz,otherpinsopen)ParameterDescriptionTestConditionMaximumCI/O1I/OPinCapacitanceVI/O=0V12pFCIN1InputCapacitanceVIN=0V12pFT16.
0250261.
Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthisparameter.
Table17:ReliabilityCharacteristicsSymbolParameterMinimumSpecificationUnitsTestMethodNEND11.
Thisparameterismeasuredonlyforinitialqualificationandafteradesignorprocesschangethatcouldaffectthisparameter.
Endurance10,000CyclesJEDECStandardA117TDR1DataRetention100YearsJEDECStandardA103ILTH1LatchUp100+IDDmAJEDECStandard78T17.
025026Table18:ClockTimingParameters(LPCMode)SymbolParameterMinMaxUnitsTCYCLCLKCycleTime30nsTHIGHLCLKHighTime11nsTLOWLCLKLowTime11ns-LCLKSlewRate(peak-to-peak)14V/ns-RST#orINIT#SlewRate50mV/nsT18.
0250261235F12.
00.
4VDDp-to-p(minimum)TcycThighTlow0.
4VDD0.
3VDD0.
6VDD0.
2VDD0.
5VDD2014SiliconStorageTechnology,Inc.
DS20005086B11/14308MbitLPCFlashSST49LF080ADataSheetFigure14:ResetTimingDiagram(LPCMode)Table19:ResetTimingParameters,VDD=3.
0-3.
6V(LPCMode)SymbolParameterMinMaxUnitsTPRSTVDDstabletoResetLow1msTKRSTClockStabletoResetLow100sTRSTPRST#PulseWidth100nsTRSTFRST#LowtoOutputFloat48nsTRST1RST#HightoLFRAME#Low1sTRSTERST#LowtoresetduringSector-/Block-EraseorPro-gram10sT19.
0250261.
TheremaybeadditionallatencyduetoTRSTEifaresetprocedureisperformedduringaProgramorEraseoperation.
CLKVDDRST#/INIT#LFRAME#LAD[3:0]1235F13.
0TPRSTTKRSTTRSTPTRSTFTRSTESector-/Block-EraseorProgramoperationabortedTRST2014SiliconStorageTechnology,Inc.
DS20005086B11/14318MbitLPCFlashSST49LF080ADataSheetACCharacteristicsTable20:Read/WriteCycleTimingParameters,VDD=3.
0-3.
6V(LPCMode)SymbolParameterMinMaxUnitsTCYCClockCycleTime30nsTSUDataSetUpTimetoClockRising7nsTDHClockRisingtoDataHoldTime0nsTVAL11.
Minimumandmaximumtimeshavedifferentloads.
SeePCIspec.
ClockRisingtoDataValid211nsTBPByteProgrammingTime20sTSESector-EraseTime25msTBEBlock-EraseTime25msTONClockRisingtoActive(FloattoActiveDelay)2nsTOFFClockRisingtoInactive(ActivetoFloatDelay)28nsT20.
025026Table21:ACInput/OutputSpecifications(LPCMode)SymbolParameterMinMaxUnitsConditionsIOH(AC)SwitchingCurrentHigh-12VDD-17.
1(VDD-VOUT)EquationC11.
SeePCIspec.
mAmA0VOUT0.
6VDD0.
6VDD>VOUT>0.
1VDD0.
18VDD>VOUT>0(TestPoint)38VDDmAVOUT=0.
18VDDICLLowClampCurrent-25+(VIN+1)/0.
015mA-3VINVDD+1slewr22.
PCIspecificationoutputloadisused.
OutputRiseSlewRate14V/ns0.
2VDD-0.
6VDDloadslewf2OutputFallSlewRate14V/ns0.
6VDD-0.
2VDDloadT21.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14328MbitLPCFlashSST49LF080ADataSheetFigure15:OutputTimingParameters(LPCMode)Figure16:InputTimingParameters(LPCMode)Table22:InterfaceMeasurementConditionParameters(LPCMode)SymbolValueUnitsVTH11.
Theinputtestenvironmentisdonewith0.
1VDDofoverdriveoverVIHandVIL.
Timingparametersmustbemetwithnomoreoverdrivethanthis.
VMAXspecifiedthemaximumpeak-to-peakwaveformallowedformeasuringinputtiming.
Pro-ductiontestingmayusedifferentvoltagevalues,butmustcorrelateresultsbacktotheseparameters0.
6VDDVVTL10.
2VDDVVTEST0.
4VDDVVMAX10.
4VDDVInputSignalEdgeRate1V/nsT22.
025026TVALTOFFTON1235F14.
0LCLKLAD[3:0](ValidOutputData)LAD[3:0](FloatOutputData)VTESTVTLVTHTSUTDHInputsValid1235F15.
0LCLKLAD[3:0](ValidInputData)VTESTVTLVMAXVTH2014SiliconStorageTechnology,Inc.
DS20005086B11/14338MbitLPCFlashSST49LF080ADataSheetTable23:ReadCycleTimingParameters,VDD=3.
0-3.
6V(PPMode)SymbolParameterMinMaxUnitsTRCReadCycleTime270nsTRSTRST#HightoRowAddressSetup1sTASR/C#AddressSet-upTime45nsTAHR/C#AddressHoldTime45nsTAAAddressAccessTime120nsTOEOutputEnableAccessTime60nsTOLZOE#LowtoActiveOutput0nsTOHZOE#HightoHigh-ZOutput35nsTOHOutputHoldfromAddressChange0nsT23.
025026Table24:Program/EraseCycleTimingParameters,VDD=3.
0-3.
6V(PPMode)SymbolParameterMinMaxUnitsTRSTRST#HightoRowAddressSetup1sTASR/C#AddressSetupTime50nsTAHR/C#AddressHoldTime50nsTCWHR/C#toWriteEnableHighTime50nsTOESOE#HighSetupTime20nsTOEHOE#HighHoldTime20nsTOEPOE#toData#PollingDelay40nsTOETOE#toToggleBitDelay40nsTWPWE#PulseWidth100nsTWPHWE#PulseWidthHigh100nsTDSDataSetupTime50nsTDHDataHoldTime5nsTIDASoftwareIDAccessandExitTime150nsTBPByteProgrammingTime20sTSESector-EraseTime25msTBEBlock-EraseTime25msTSCEChip-EraseTime100msT24.
0250262014SiliconStorageTechnology,Inc.
DS20005086B11/14348MbitLPCFlashSST49LF080ADataSheetFigure17:ResetTimingDiagram(PPMode)Table25:ResetTimingParameters,VDD=3.
0-3.
6V(PPMode)SymbolParameterMinMaxUnitsTPRSTVDDstabletoResetLow1msTRSTPRST#PulseWidth100nsTRSTFRST#LowtoOutputFloat48nsTRST1RST#HightoRowAddressSetup1sTRSTERST#LowtoresetduringSector-/Block-EraseorPro-gram10sTRSTCRST#LowtoresetduringChip-Erase50sT25.
0250261.
TheremaybeadditionalresetlatencyduetoTRSTEorTRSTCifaresetprocedureisperformedduringaProgramorEraseoperation.
VDDRST#AddressesR/C#DQ7-01235F16.
0TPRSTTRSTPTRSTFTRSTERowAddressSector-/Block-EraseorProgramoperationabortedTRSTTRSTCChip-Eraseaborted2014SiliconStorageTechnology,Inc.
DS20005086B11/14358MbitLPCFlashSST49LF080ADataSheetFigure18:ReadCycleTimingDiagram(PPMode)Figure19:WriteCycleTimingDiagram(PPMode)RST#TRST1235F17.
0ColumnAddressDataValidHigh-ZRowAddressColumnAddressRowAddressAddressesR/C#VIHHigh-ZTRCTASTAHTAHTAATOETOLZTOHZTOHTASWE#OE#DQ7-01235F18.
0ColumnAddressRowAddressDataValidRST#AddressesR/C#TRSTTASTAHTCWHTWPTOESTWPHTOEHTDHTDSTAHTASWE#OE#DQ7-02014SiliconStorageTechnology,Inc.
DS20005086B11/14368MbitLPCFlashSST49LF080ADataSheetFigure20:Data#PollingTimingDiagram(PPMode)Figure21:ToggleBitTimingDiagram(PPMode)Figure22:Byte-ProgramTimingDiagram(PPMode)1235F19.
0AddressesR/C#TOEPRowColumnWE#OE#DQ7D#DD#D1235F20.
0AddressesR/C#TOETRowColumnWE#OE#DQ6DD555555552AAAA14-0(InternalAMS-0)R/C#OE#WE#DQ7-0BAInternalProgramStartsAA55A0DATABA=Byte-ProgramAddressAMS=MostSignificantAddress1235F21.
02014SiliconStorageTechnology,Inc.
DS20005086B11/14378MbitLPCFlashSST49LF080ADataSheetFigure23:Sector-EraseTimingDiagram(PPMode)Figure24:Block-EraseTimingDiagram(PPMode)Figure25:Chip-EraseTimingDiagram(PPMode)5555555555552AAASAX2AAAA14-0(InternalAMS-0)R/C#OE#WE#DQ7-0InternalEraseStartsAA5580AA5530SAX=SectorAddress1235F22.
05555555555552AAABAX2AAAA14-0(InternalAMS-0)R/C#OE#WE#DQ7-0InternalEraseStartsAA5580AA5550BAX=BlockAddress1235F23.
05555555555552AAA55552AAAA14-0(InternalAMS-0)R/C#OE#WE#DQ7-0InternalEraseStartsAA5580AA55101235F24.
02014SiliconStorageTechnology,Inc.
DS20005086B11/14388MbitLPCFlashSST49LF080ADataSheetFigure26:SoftwareIDEntryandRead(PPMode)Figure27:SoftwareIDExit(PPMode)55555555000000012AAAA14-0(InternalAMS-0)R/C#OE#WE#DQ7-0AA1235F25.
0DeviceIDBF5590TWPTWPHTIDATAANote:DeviceID=5BHforSST49LF080A555555552AAAA14-0(InternalAMS-0)R/C#OE#WE#DQ7-0AA1235F26.
055F0TIDA2014SiliconStorageTechnology,Inc.
DS20005086B11/14398MbitLPCFlashSST49LF080ADataSheetFigure28:ACInput/OutputReferenceWaveformsFigure29:ATestLoadExampleFigure30:ReadFlowchart(LPCMode)1235F27.
0REFERENCEPOINTSOUTPUTINPUTVITVIHTVILTVOTACtestinputsaredrivenatVIHT(0.
9VDD)foralogic"1"andVILT(0.
1VDD)foralogic"0".
Measure-mentreferencepointsforinputsandoutputsareVIT(0.
5VDD)andVOT(0.
5VDD).
Inputriseandfalltimes(10%90%)areCommandSequenceAvailableforNextCommand2014SiliconStorageTechnology,Inc.
DS20005086B11/14408MbitLPCFlashSST49LF080ADataSheetFigure31:Byte-ProgramFlowchart(LPCMode)1235F30.
0Address:5555HWriteData:AAHCycle:1Address:2AAAHWriteData:55HCycle:2Address:5555HWriteData:A0HCycle:3Address:AINWriteData:DINCycle:4AvailableforNextByteWaitTBP2014SiliconStorageTechnology,Inc.
DS20005086B11/14418MbitLPCFlashSST49LF080ADataSheetFigure32:EraseCommandSequencesFlowchart(LPCMode)1235F31.
0Sector-EraseCommandSequenceAddress:5555HWriteData:AAHCycle:1Address:2AAAHWriteData:55HCycle:2Address:5555HWriteData:80HCycle:3Address:5555HWriteData:AAHCycle:4Address:2AAAHWriteData:55HCycle:5SectorerasedtoFFHAddress:SAXWriteData:30HCycle:6WaitTSEAvailableforNextCommandBlock-EraseCommandSequenceAddress:5555HWriteData:AAHCycle:1Address:2AAAHWriteData:55HCycle:2Address:5555HWriteData:80HCycle:3Address:5555HWriteData:AAHCycle:4Address:2AAAHWriteData:55HCycle:5BlockerasedtoFFHAddress:BAXWriteData:50HCycle:6WaitTBEAvailableforNextCommand2014SiliconStorageTechnology,Inc.
DS20005086B11/14428MbitLPCFlashSST49LF080ADataSheetFigure33:SoftwareProductIDCommandSequencesFlowchart(LPCMode)1235F32.
0SoftwareProductIDEntryCommandSequenceWaitTIDASoftwareProductIDExitCommandSequenceWaitTIDAWaitTIDAAddress:5555HWriteData:AAHCycle:1Address:2AAAHWriteData:55HCycle:2Address:5555HWriteData:90HCycle:3Address:5555HWriteData:AAHCycle:1Address:XXXXHWriteData:F0HCycle:1Address:2AAAHWriteData:55HCycle:2Address:5555HWriteData:F0HCycle:3Address:0001HReadData:BFHCycle:4Address:0002HReadData:Cycle:5AvailableforNextCommandAvailableforNextCommandAvailableforNextCommandNote:XcanbeVILorVIH,butnoothervalue.
2014SiliconStorageTechnology,Inc.
DS20005086B11/14438MbitLPCFlashSST49LF080ADataSheetFigure34:Byte-ProgramCommandSequencesFlowchart(PPMode)1235F33.
0StartWritedata:AAHAddress:5555HWritedata:55HAddress:2AAAHWritedata:A0HAddress:5555HLoadByteAddress/ByteDataWaitforendofProgram(TBP,Data#Pollingbit,orTogglebitoperation)ProgramCompleted2014SiliconStorageTechnology,Inc.
DS20005086B11/14448MbitLPCFlashSST49LF080ADataSheetFigure35:WaitOptionsFlowchart(PPMode)1235F34.
0WaitTBP,TSCE,TBE,orTSEByte-Program/EraseInitiatedInternalTimerToggleBitYesYesNoNoProgram/EraseCompletedDoesDQ6matchReadsamebyteData#PollingProgram/EraseCompletedProgram/EraseCompletedReadbyteIsDQ7=truedataReadDQ7Byte-Program/EraseInitiatedByte-Program/EraseInitiated2014SiliconStorageTechnology,Inc.
DS20005086B11/14458MbitLPCFlashSST49LF080ADataSheetFigure36:SoftwareProductIDCommandSequencesFlowchart(PPMode)1235F35.
0Writedata:AAHAddress:5555HSoftwareProductIDEntryCommandSequenceWritedata:55HAddress:2AAAHWritedata:90HAddress:5555HWaitTIDAReadSoftwareIDWritedata:AAHAddress:5555HSoftwareProductIDExitCommandSequenceWritedata:55HAddress:2AAAHWritedata:F0HAddress:5555HWritedata:F0HAddress:XXHReturntonormaloperationWaitTIDAWaitTIDAReturntonormaloperation2014SiliconStorageTechnology,Inc.
DS20005086B11/14468MbitLPCFlashSST49LF080ADataSheetFigure37:EraseCommandSequenceFlowchart(PPMode)1235F36.
0Writedata:AAHAddress:5555HChip-EraseCommandSequenceWritedata:55HAddress:2AAAHWritedata:80HAddress:5555HWritedata:55HAddress:2AAAHWritedata:10HAddress:5555HWritedata:AAHAddress:5555HWaitTSCEChiperasedtoFFHWritedata:AAHAddress:5555HSector-EraseCommandSequenceWritedata:55HAddress:2AAAHWritedata:80HAddress:5555HWritedata:55HAddress:2AAAHWritedata:30HAddress:SAXWritedata:AAHAddress:5555HWaitTSESectorerasedtoFFHWritedata:AAHAddress:5555HBlock-EraseCommandSequenceWritedata:55HAddress:2AAAHWritedata:80HAddress:5555HWritedata:55HAddress:2AAAHWritedata:50HAddress:BAXWritedata:AAHAddress:5555HWaitTBEBlockerasedtoFFH2014SiliconStorageTechnology,Inc.
DS20005086B11/14478MbitLPCFlashSST49LF080ADataSheetProductOrderingInformationValidcombinationsforSST49LF080ASST49LF080A-33-4C-WHESST49LF080A-33-4C-NHENote:Validcombinationsarethoseproductsinmassproductionorwillbeinmassproduction.
ConsultyourSSTsalesrepresentativetoconfirmavailabilityofvalidcombinationsandtodetermineavailabilityofnewcombi-nations.
SST49LF080A-33-4C-NHEXXXXXXXX-XX-XX-XXXEnvironmentalAttributeE1=non-PbPackageModifierH=32leadsPackageTypeN=PLCCW=TSOP(type1,dieup,8mmx14mm)OperatingTemperatureC=Commercial=0°Cto+85°CMinimumEndurance4=10,000cyclesSerialAccessClockFrequency33=33MHzVersionDeviceDensity080=8MbitVoltageRangeL=3.
0-3.
6V1.
Environmentalsuffix"E"denotesnon-Pbsol-der.
SSTnon-Pbsolderdevicesare"RoHSCompliant".
2014SiliconStorageTechnology,Inc.
DS20005086B11/14488MbitLPCFlashSST49LF080ADataSheetPackagingDiagramsFigure38:32-leadPlasticLeadChipCarrier(PLCC)SSTPackageCode:NH.
040.
030.
021.
013.
530.
490.
095.
075.
140.
125.
032.
026.
032.
026.
029.
023.
453.
447.
553.
547.
595.
585.
495.
485.
112.
106.
042.
048.
048.
042.
015Min.
TOPVIEWSIDEVIEWBOTTOMVIEW1232.
400BSC32-plcc-NH-3Note:1.
ComplieswithJEDECpublication95MS-016AEdimensions,althoughsomedimensionsmaybemorestringent.
2.
Alllineardimensionsareininches(max/min).
3.
Dimensionsdonotincludemoldflash.
Maximumallowablemoldflashis.
008inches.
4.
Coplanarity:4mils.
.
050BSC.
050BSCOptionalPin#1Identifier.
020R.
MAX.
R.
x30°2014SiliconStorageTechnology,Inc.
DS20005086B11/14498MbitLPCFlashSST49LF080ADataSheetFigure39:32-leadThinSmallOutlinePackage(TSOP)8mmx14mmSSTPackageCode:WH32-tsop-WH-7Note:1.
ComplieswithJEDECpublication95MO-142BAdimensions,althoughsomedimensionsmaybemorestringent.
2.
Alllineardimensionsareinmillimeters(max/min).
3.
Coplanarity:0.
1mm4.
Maximumallowablemoldflashis0.
15mmatthepackageends,and0.
25mmbetweenleads.
1.
20max.
1mmPin#1Identifier12.
5012.
3014.
2013.
800.
700.
508.
107.
900.
270.
170.
50BSC1.
050.
950.
150.
050.
700.
500°-5°DETAIL2014SiliconStorageTechnology,Inc.
DS20005086B11/14508MbitLPCFlashSST49LF080ADataSheetTable26:RevisionHistoryRevisionDescriptionDate00Initialrelease(SST49LF080ApreviouslyreleasedindatasheetS71206)Apr200301Addedstatementthatnon-PbdevicesareRoHScomplianttoFeaturessectionUpdatedSurfaceMountSolderReflowTemperatureinformationAddedfootnotetoProductOrderingInformationsectionRemovedleadedpartnumbersJan200602UpdatedTable5onpage11May2006AAppliednewdocumentformatReleaseddocumentunderletterrevisionsystemUpdatedSpecnumberfromS71235toDS25086Nov2011BUpdated"LFRAME#"onpage9Nov20142014MicrochipTechnologyInc.
SST,SiliconStorageTechnology,theSSTlogo,SuperFlash,andMTPareregisteredtrademarksofMicrochipTechnology,Inc.
MPF,SQI,SerialQuadI/O,andZ-ScalearetrademarksofMicrochipTechnology,Inc.
Allothertrademarksandregisteredtrade-marksmentionedhereinarethepropertyoftheirrespectiveowners.
Specificationsaresubjecttochangewithoutnotice.
Refertowww.
microchip.
comforthemostrecentdocumentation.
Forthemostcurrentpackagedrawings,pleaseseethePackagingSpecificationlocatedathttp://www.
microchip.
com/packaging.
Memorysizesdenoterawstoragecapacity;actualusablecapacitymaybeless.
MicrochipmakesnowarrantyfortheuseofitsproductsotherthanthoseexpresslycontainedintheStandardTermsandConditionsofSale.
Forsalesofficelocationsandinformation,pleaseseewww.
microchip.
com.
www.
microchip.
comISBN:978-1-63276-793-6