PGMD55555tk

FeaturesIncorporatestheARM7TDMIARMThumbProcessor–High-performance32-bitRISCArchitecture–High-density16-bitInstructionSet–LeaderinMIPS/Watt–EmbeddedICEIn-circuitEmulation,DebugCommunicationChannelSupportInternalHigh-speedFlash–512Kbytes,OrganizedinTwoContiguousBanksof1024Pagesof256BytesDualPlane(AT91SAM7SE512)–256Kbytes(AT91SAM7SE256)OrganizedinOneBankof1024Pagesof256BytesSinglePlane(AT91SAM7SE256)–32Kbytes(AT91SAM7SE32)OrganizedinOneBankof256Pagesof128BytesSinglePlane(AT91SAM7SE32)–SingleCycleAccessatUpto30MHzinWorstCaseConditions–PrefetchBufferOptimizingThumbInstructionExecutionatMaximumSpeed–PageProgrammingTime:6ms,IncludingPageAuto-erase,FullEraseTime:15ms–10,000EraseCycles,10-yearDataRetentionCapability,SectorLockCapabilities,FlashSecurityBit–FastFlashProgrammingInterfaceforHighVolumeProduction32Kbytes(AT91SAM7SE512/256)or8Kbytes(AT91SAM7SE32)ofInternalHigh-speedSRAM,Single-cycleAccessatMaximumSpeedOneExternalBusInterface(EBI)–SupportsSDRAM,StaticMemory,GluelessConnectiontoCompactFlashandECC-enabledNANDFlashMemoryController(MC)–EmbeddedFlashController–MemoryProtectionUnit–AbortStatusandMisalignmentDetectionResetController(RSTC)–BasedonPower-onResetCellsandLow-powerFactory-calibratedBrownoutDetector–ProvidesExternalResetSignalShapingandResetSourceStatusClockGenerator(CKGR)–Low-powerRCOscillator,3to20MHzOn-chipOscillatorandOnePLLPowerManagementController(PMC)–PowerOptimizationCapabilities,IncludingSlowClockMode(Downto500Hz)andIdleMode–ThreeProgrammableExternalClockSignalsAdvancedInterruptController(AIC)–IndividuallyMaskable,Eight-levelPriority,VectoredInterruptSources–TwoExternalInterruptSourcesandOneFastInterruptSource,SpuriousInterruptProtectedDebugUnit(DBGU)–Two-wireUARTandSupportforDebugCommunicationChannelinterrupt,ProgrammableICEAccessPreventionPeriodicIntervalTimer(PIT)–20-bitProgrammableCounterplus12-bitIntervalCounterWindowedWatchdog(WDT)–12-bitkey-protectedProgrammableCounter–ProvidesResetorInterruptSignalstotheSystem–CounterMayBeStoppedWhiletheProcessorisinDebugStateorinIdleModeAT91ARMThumb-basedMicrocontrollersAT91SAM7SE512AT91SAM7SE256AT91SAM7SE32AdvanceInformationSummary6222AS–ATARM–21-Aug-0626222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Real-timeTimer(RTT)–32-bitFree-runningCounterwithAlarm–RunsOfftheInternalRCOscillatorThreeParallelInput/OutputControllers(PIO)–Eighty-eightProgrammableI/OLinesMultiplexedwithuptoTwoPeripheralI/Os–InputChangeInterruptCapabilityonEachI/OLine–IndividuallyProgrammableOpen-drain,Pull-upResistorandSynchronousOutput–SchmittTriggeronAllinputsElevenPeripheralDMAController(PDC)ChannelsOneUSB2.
0FullSpeed(12Mbitspersecond)DevicePort–On-chipTransceiver,EightEndpoints,2688-byteConfigurableIntegratedFIFOsOneSynchronousSerialController(SSC)–IndependentClockandFrameSyncSignalsforEachReceiverandTransmitter–ISAnalogInterfaceSupport,TimeDivisionMultiplexSupport–High-speedContinuousDataStreamCapabilitieswith32-bitDataTransferTwoUniversalSynchronous/AsynchronousReceiverTransmitters(USART)–IndividualBaudRateGenerator,IrDAInfraredModulation/Demodulation–SupportforISO7816T0/T1SmartCard,HardwareHandshaking,RS485Support–FullModemLineSupportonUSART1OneMaster/SlaveSerialPeripheralInterfaces(SPI)–8-to16-bitProgrammableDataLength,FourExternalPeripheralChipSelectsOneThree-channel16-bitTimer/Counter(TC)–ThreeExternalClockInputs,TwoMulti-purposeI/OPinsperChannel–DoublePWMGeneration,Capture/WaveformMode,Up/DownCapabilityOneFour-channel16-bitPWMController(PWMC)OneTwo-wireInterface(TWI)–Master,Multi-MasterandSlaveModeSupport,AllTwo-wireAtmelEEPROMsSupported–GeneralCallSupportedinSlaveModeOne8-channel10-bitAnalog-to-DigitalConverter,FourChannelsMultiplexedwithDigitalI/OsSAM-BA–DefaultBootprogram–InterfacewithSAM-BAGraphicUserInterfaceIEEE1149.
1JTAGBoundaryScanonAllDigitalPinsFourHigh-currentDriveI/Olines,Upto16mAEachPowerSupplies–Embedded1.
8VRegulator,Drawingupto100mAfortheCoreandExternalComponents–1.
8Vor3,3VVDDIOI/OLinesPowerSupply,Independent3.
3VVDDFLASHFlashPowerSupply–1.
8VVDDCORECorePowerSupplywithBrownoutDetectorFullyStaticOperation:Upto48MHzat1.
65Vand85°CWorstCaseConditionsAvailableina128-leadLQFPGreenPackage,ora144-ballLFBGARoHS-compliantPackage36222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]1.
DescriptionAtmel'sAT91SAM7SESeriesisamemberofitsSmartARMMicrocontrollerfamilybasedonthe32-bitARM7RISCprocessorandhigh-speedFlashmemory.
AT91SAM7SE512featuresa512Kbytehigh-speedFlashanda32KbyteSRAM.
AT91SAM7SE256featuresa256Kbytehigh-speedFlashanda32KbyteSRAM.
AT91SAM7SE32featuresa32Kbytehigh-speedFlashandan8KbyteSRAM.
Italsoembedsalargesetofperipherals,includingaUSB2.
0device,anExternalBusInterface(EBI),andacompletesetofsystemfunctionsminimizingthenumberofexternalcomponents.
TheEBIincorporatescontrollersforsynchronousDRAM(SDRAM)andStaticmemoriesandfeaturesspecificcircuitryfacilitatingtheinterfaceforNANDFlash,SmartMediaandCompactFlash.
Thedeviceisanidealmigrationpathfor8/16-bitmicrocontrolleruserslookingforadditionalper-formance,extendedmemoryandhigherlevelsofsystemintegration.
TheembeddedFlashmemorycanbeprogrammedin-systemviatheJTAG-ICEinterfaceorviaaparallelinterfaceonaproductionprogrammerpriortomounting.
Built-inlockbitsandasecu-ritybitprotectthefirmwarefromaccidentaloverwriteandpreserveitsconfidentiality.
TheAT91SAM7SESeriessystemcontrollerincludesaresetcontrollercapableofmanagingthepower-onsequenceofthemicrocontrollerandthecompletesystem.
Correctdeviceoperationcanbemonitoredbyabuilt-inbrownoutdetectorandawatchdogrunningoffanintegratedRCoscillator.
BycombiningtheARM7TDMIprocessorwithon-chipFlashandSRAM,andawiderangeofperipheralfunctions,includingUSART,SPI,ExternalBusInterface,TimerCounter,RTTandAnalog-to-DigitalConvertersonamonolithicchip,theAT91SAM7SE512/256/32isapowerfuldevicethatprovidesaflexible,cost-effectivesolutiontomanyembeddedcontrolapplications.
1.
1ConfigurationSummaryoftheAT91SAM7SE512,AT91SAM7SE256andAT91SAM7SE32TheAT91SAM7SE512,AT91SAM7SE256andAT91SAM7SE32differinmemorysizesandorganization.
Table1-1belowsummarizestheconfigurationsforthethreedevices.
Table1-1.
ConfigurationSummaryDeviceFlashSizeFlashOrganizationRAMSizeAT91SAM7SE512512Kbytesdualplane32KbytesAT91SAM7SE256256Kbytessingleplane32KbytesAT91SAM7SE3232Kbytessingleplane8Kbytes46222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]2.
BlockDiagramFigure2-1.
AT91SAM7SE512/256/32BlockDiagramSignalDescriptionResetControllerPMCAPBICEJTAGSCANARM7TDMIProcessorSystemControllerAICDBGUPDCPDCPLLOSCRCOSCBODPORPIOPITWDTRTTPIOAPIOBPIOCPIOPIOPIOUSART0USART1SPITimerCounterPDCPDCPDCPDCPDCPDCPDCPDCTC0TC1TC2ADCADVREFTWISSCPWMCUSBDeviceFIFOStaticMemoryControllerECCControllerSDRAMControllerEBICompactFlashNANDFlashSRAM32Kbytes(SE512/256)or8Kbytes(SE32)Flash512Kbytes(SE512)256Kbytes(SE256)32Kbytes(SE32)1.
8VVoltageRegulatorMemoryControllerEmbeddedFlashControllerAddressDecoderAbortStatusMisalignmentDetectionMemoryProtectionUnitPeripheralDMAController11ChannelsPeripheralBridgeFastFlashProgrammingInterfaceSAM-BATranscieverPDCROMNPCS0NPCS1NPCS2NPCS3MISOMOSISPCKTIOA0TIOB0TIOA1TIOB1TIOA2TIOB2ADTRGAD0AD1AD2AD3AD4AD5AD6AD7TCLK0TCLK1TCLK2RXD0TXD0SCK0RTS0CTS0RXD1TXD1SCK1RTS1CTS1DCD1DSR1DTR1RI1NRSTVDDCOREVDDCOREVDDFLASHXINXOUTPLLRCPCK0-PCK2DRXDDTXDIRQ0-IRQ1FIQTSTTDITDOTMSTCKJTAGSELVDDINGNDVDDOUTVDDCOREVDDIOVDDFLASHERASEPGMRDYPGMNVALIDPGMNOEPGMCKPGMM0-PGMM3PGMD0-PGMD15PGMNCMDPGMEN0-PGMEN1D[31:0]A0/NBS0A1/NBS2A[15:2],A[20:18]A21/NANDALEA22/REG/NANDCLEA16/BA0A17/BA1NCS0NCS1/SDCSNCS2/CFCS1NCS3/NANDCSNRD/CFOENWR0/NWE/CFWENWR1/NBS1/CFIORNBS3/CFIOWSDCKERASCASSDWESDA10CFRNWNCS4/CFCS0NCS5/CFCE1NCS6/CFCE2NCS7NANDOENANDWENWAITSDCKDDMDDPPWM0PWM1PWM2PWM3TFTKTDRDRKRFTWDTWCK56222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]3.
SignalDescriptionTable3-1.
SignalDescriptionListSignalNameFunctionTypeActiveLevelCommentsPowerVDDINVoltageRegulatorandADCPowerSupplyInputPower3Vto3.
6VVDDOUTVoltageRegulatorOutputPower1.
85VVDDFLASHFlashandUSBPowerSupplyPower3Vto3.
6VVDDIOI/OLinesPowerSupplyPower3Vto3.
6Vor1.
65Vto1.
95VVDDCORECorePowerSupplyPower1.
65Vto1.
95VVDDPLLPLLPower1.
65Vto1.
95VGNDGroundGroundClocks,OscillatorsandPLLsXINMainOscillatorInputInputXOUTMainOscillatorOutputOutputPLLRCPLLFilterInputPCK0-PCK2ProgrammableClockOutputOutputICEandJTAGTCKTestClockInputNopull-upresistorTDITestDataInInputNopull-upresistor.
TDOTestDataOutOutputTMSTestModeSelectInputNopull-upresistor.
JTAGSELJTAGSelectionInputPull-downresistor.
FlashMemoryERASEFlashandNVMConfigurationBitsEraseCommandInputHighPull-downresistorReset/TestNRSTMicrocontrollerResetI/OLowPull-UpresistorTSTTestModeSelectInputHighPull-downresistorDebugUnitDRXDDebugReceiveDataInputDTXDDebugTransmitDataOutputAICIRQ0-IRQ1ExternalInterruptInputsInputFIQFastInterruptInputInput66222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]PIOPA0-PA31ParallelIOControllerAI/OPulled-upinputatresetPB0-PB31ParallelIOControllerBI/OPulled-upinputatresetPC0-PC23ParallelIOControllerCI/OPulled-upinputatresetUSBDevicePortDDMUSBDevicePortData-AnalogDDPUSBDevicePortData+AnalogUSARTSCK0-SCK1SerialClockI/OTXD0-TXD1TransmitDataI/ORXD0-RXD1ReceiveDataInputRTS0-RTS1RequestToSendOutputCTS0-CTS1ClearToSendInputDCD1DataCarrierDetectInputDTR1DataTerminalReadyOutputDSR1DataSetReadyInputRI1RingIndicatorInputSynchronousSerialControllerTDTransmitDataOutputRDReceiveDataInputTKTransmitClockI/ORKReceiveClockI/OTFTransmitFrameSyncI/ORFReceiveFrameSyncI/OTimer/CounterTCLK0-TCLK2ExternalClockInputsInputTIOA0-TIOA2TimerCounterI/OLineAI/OTIOB0-TIOB2TimerCounterI/OLineBI/OPWMControllerPWM0-PWM3PWMChannelsOutputSerialPeripheralInterfaceMISOMasterInSlaveOutI/OMOSIMasterOutSlaveInI/OSPCKSPISerialClockI/ONPCS0SPIPeripheralChipSelect0I/OLowNPCS1-NPCS3SPIPeripheralChipSelect1to3OutputLowTable3-1.
SignalDescriptionList(Continued)SignalNameFunctionTypeActiveLevelComments76222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Two-WireInterfaceTWDTwo-wireSerialDataI/OTWCKTwo-wireSerialClockI/OAnalog-to-DigitalConverterAD0-AD3AnalogInputsAnalogAnalogInputsAD4-AD7AnalogInputsAnalogDigitalpulled-upinputsatresetADTRGADCTriggerInputADVREFADCReferenceAnalogFastFlashProgrammingInterfacePGMEN0-PGMEN2ProgrammingEnablingInputPGMM0-PGMM3ProgrammingModeInputPGMD0-PGMD15ProgrammingDataI/OPGMRDYProgrammingReadyOutputHighPGMNVALIDDataDirectionOutputLowPGMNOEProgrammingReadInputLowPGMCKProgrammingClockInputPGMNCMDProgrammingCommandInputLowExternalBusInterfaceD[31:0]DataBusI/OA[22:0]AddressBusOutputNWAITExternalWaitSignalInputLowStaticMemoryControllerNCS[7:0]ChipSelectLinesOutputLowNWR[1:0]WriteSignalsOutputLowNRDReadSignalOutputLowNWEWriteEnableOutputLowNUBNUB:UpperByteSelectOutputLowNLBNLB:LowerByteSelectOutputLowEBIforCompactFlashSupportCFCE[2:1]CompactFlashChipEnableOutputLowCFOECompactFlashOutputEnableOutputLowCFWECompactFlashWriteEnableOutputLowCFIORCompactFlashI/OReadSignalOutputLowCFIOWCompactFlashI/OWriteSignalOutputLowCFRNWCompactFlashReadNotWriteSignalOutputCFCS[1:0]CompactFlashChipSelectLinesOutputLowTable3-1.
SignalDescriptionList(Continued)SignalNameFunctionTypeActiveLevelComments86222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]EBIforNANDFlashSupportNANDCSNANDFlashChipSelectLineOutputLowNANDOENANDFlashOutputEnableOutputLowNANDWENANDFlashWriteEnableOutputLowNANDCLENANDFlashCommandLineEnableOutputLowNANDALENANDFlashAddressLineEnableOutputLowSDRAMControllerSDCKSDRAMClockOutputTiedlowafterresetSDCKESDRAMClockEnableOutputHighSDCSSDRAMControllerChipSelectLineOutputLowBA[1:0]BankSelectOutputSDWESDRAMWriteEnableOutputLowRAS-CASRowandColumnSignalOutputLowNBS[3:0]ByteMaskSignalsOutputLowSDA10SDRAMAddress10LineOutputTable3-1.
SignalDescriptionList(Continued)SignalNameFunctionTypeActiveLevelComments96222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]4.
PackageTheAT91SAM7SE512/256/32isavailablein:20x14mm128-leadLQFPpackagewitha0.
5mmleadpitch.
10x10x1.
4mm144-ballLFBGApackagewitha0.
8mmleadpitch4.
1128-leadLQFPPackageOutlineFigure4-1showstheorientationofthe128-leadLQFPpackageandadetailedmechanicaldescriptionisgivenintheMechanicalCharacteristicssectionofthefulldatasheet.
Figure4-1.
128-leadLQFPPackageOutline(TopView)651031026439381128106222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]4.
2128-leadLQFPPinoutTable4-1.
Pinoutin128-leadLQFPPackage1ADVREF33PB3165TDI97SDCK2GND34PB3066TDO98PC83AD735PB2967PB299PC74AD636PB2868PB1100PC65AD537PB2769PB0101PC56AD438PB2670GND102PC47VDDOUT39PB2571VDDIO103PC38VDDIN40PB2472VDDCORE104PC29PA20/PGMD8/AD341PB2373NRST105PC110PA19/PGMD7/AD242PB2274TST106PC011PA18/PGMD6/AD143PB2175ERASE107PA3112PA17/PGMD5/AD044PB2076TCK108PA3013PA16/PGMD445GND77TMS109PA2914PA15/PGMD346VDDIO78JTAGSEL110PA2815PA14/PGMD247VDDCORE79PC23111PA27/PGMD1516PA13/PGMD148PB1980PC22112PA26/PGMD1417PA12/PGMD049PB1881PC21113PA25/PGMD1318PA11/PGMM350PB1782PC20114PA24/PGMD1219PA10/PGMM251PB1683PC19115PA23/PGMD1120PA9/PGMM152PB1584PC18116PA22/PGMD1021VDDIO53PB1485PC17117PA21/PGMD922GND54PB1386PC16118VDDCORE23VDDCORE55PB1287PC15119GND24PA8/PGMM056PB1188PC14120VDDIO25PA7/PGMNVALID57PB1089PC13121DM26PA6/PGMNOE58PB990PC12122DP27PA5/PGMRDY59PB891PC11123VDDFLASH28PA4/PGMNCMD60PB792PC10124GND29PA361PB693PC9125XIN/PGMCK30PA2/PGMEN262PB594GND126XOUT31PA1/PGMEN163PB495VDDIO127PLLRC32PA0/PGMEN064PB396VDDCORE128VDDPLL116222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]4.
3144-ballLFBGAPackageOutlineFigure4-2showstheorientationofthe144-ballLFBGApackageandadetailedmechanicaldescriptionisgivenintheMechanicalCharacteristicssection.
Figure4-2.
144-ballLFBGAPackageOutline(TopView)ABCDEFGHJKLM121110987654321BallA1126222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]4.
4144-ballLFBGAPinoutTable4-2.
SAM7SE512/256/32Pinoutfor144-ballLFBGAPackagePinSignalNamePinSignalNamePinSignalNamePinSignalNameA1PB7D1VDDCOREG1PC18K1PC11A2PB8D2VDDCOREG2PC16K2PC6A3PB9D3PB2G3PC17K3PC2A4PB12D4TDOG4PC9K4PC0A5PB13D5TDIG5VDDIOK5PA27/PGMD15A6PB16D6PB17G6GNDK6PA26/PGMD14A7PB22D7PB26G7GNDK7GNDA8PB23D8PA14/PGMD2G8GNDK8VDDCOREA9PB25D9PA12/PGMD0G9GNDK9VDDFLASHA10PB29D10PA11/PGMM3G10AD4K10VDDIOA11PB30D11PA8/PGMM0G11VDDINK11VDDIOA12PB31D12PA7/PGMNVALIDG12VDDOUTK12PA18/PGMD6/AD1B1PB6E1PC22H1PC15L1SDCKB2PB3E2PC23H2PC14L2PC7B3PB4E3NRSTH3PC13L3PC4B4PB10E4TCKH4VDDCOREL4PC1B5PB14E5ERASEH5VDDCOREL5PA29B6PB18E6TESTH6GNDL6PA24/PGMD12B7PB20E7VDDCOREH7GNDL7PA21/PGMD9B8PB24E8VDDCOREH8GNDL8ADVREFB9PB28E9GNDH9GNDL9VDDFLASHB10PA4/PGMNCMDE10PA9/PGMM1H10PA19/PGMD7/AD2L10VDDFLASHB11PA0/PGMEN0E11PA10/PGMM2H11PA20/PGMD8/AD3L11PA17/PGMD5/AD0B12PA1/PGMEN1E12PA13/PGMD1H12VDDIOL12GNDC1PB0F1PC21J1PC12M1PC8C2PB1F2PC20J2PC10M2PC5C3PB5F3PC19J3PA30M3PC3C4PB11F4JTAGSELJ4PA28M4PA31C5PB15F5TMSJ5PA23/PGMD11M5PA25/PGMD13C6PB19F6VDDIOJ6PA22/PGMD10M6DMC7PB21F7GNDJ7AD6M7DPC8PB27F8GNDJ8AD7M8GNDC9PA6/PGMNOEF9GNDJ9VDDCOREM9XIN/PGMCKC10PA5/PGMRDYF10AD5J10VDDCOREM10XOUTC11PA2/PGMEN2F11PA15/PGMD3J11VDDCOREM11PLLRCC12PA3F12PA16/PGMD4J12VDDIOM12VDDPLL136222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]5.
PowerConsiderations5.
1PowerSuppliesTheAT91SAM7SE512/256/32hassixtypesofpowersupplypinsandintegratesavoltageregu-lator,allowingthedevicetobesuppliedwithonlyonevoltage.
Thesixpowersupplypintypesare:VDDINpin.
ItpowersthevoltageregulatorandtheADC;voltagerangesfrom3.
0Vto3.
6V,3.
3Vnominal.
VDDOUTpin.
Itistheoutputofthe1.
8Vvoltageregulator.
VDDIOpin.
ItpowerstheI/Olines;twovoltagerangesaresupported:–from3.
0Vto3.
6V,3.
3Vnominal–orfrom1.
65Vto1.
95V,1.
8Vnominal.
VDDFLASHpin.
ItpowerstheUSBtransceiversandapartoftheFlash.
ItisrequiredfortheFlashtooperatecorrectly;voltagerangesfrom3.
0Vto3.
6V,3.
3Vnominal.
VDDCOREpins.
Theypowerthelogicofthedevice;voltagerangesfrom1.
65Vto1.
95V,1.
8Vtypical.
ItcanbeconnectedtotheVDDOUTpinwithdecouplingcapacitor.
VDDCOREisrequiredforthedevice,includingitsembeddedFlash,tooperatecorrectly.
VDDPLLpin.
ItpowerstheoscillatorandthePLL.
ItcanbeconnecteddirectlytotheVDDOUTpin.
Inordertodecreasecurrentconsumption,ifthevoltageregulatorandtheADCarenotused,VDDIN,ADVREF,AD4,AD5,AD6andAD7shouldbeconnectedtoGND.
InthiscaseVDDOUTshouldbeleftunconnected.
Noseparategroundpinsareprovidedforthedifferentpowersupplies.
OnlyGNDpinsarepro-videdandshouldbeconnectedasshortlyaspossibletothesystemgroundplane.
5.
2PowerConsumptionTheAT91SAM7SE512/256/32hasastaticcurrentoflessthan60AonVDDCOREat25°C,includingtheRCoscillator,thevoltageregulatorandthepower-onresetwhenthebrownoutdetectorisdeactivated.
Activatingthebrownoutdetectoradds20Astaticcurrent.
ThedynamicpowerconsumptiononVDDCOREislessthan80mAatfullspeedwhenrunningoutoftheFlash.
Underthesameconditions,thepowerconsumptiononVDDFLASHdoesnotexceed10mA.
5.
3VoltageRegulatorTheAT91SAM7SE512/256/32embedsavoltageregulatorthatismanagedbytheSystemController.
InNormalMode,thevoltageregulatorconsumeslessthan100Astaticcurrentanddraws100mAofoutputcurrent.
ThevoltageregulatoralsohasaLow-powerMode.
Inthismode,itconsumeslessthan20Astaticcurrentanddraws1mAofoutputcurrent.
AdequateoutputsupplydecouplingismandatoryforVDDOUTtoreducerippleandavoidoscil-lations.
Thebestwaytoachievethisistousetwocapacitorsinparallel:146222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Oneexternal470pF(or1nF)NPOcapacitorshouldbeconnectedbetweenVDDOUTandGNDasclosetothechipaspossible.
Oneexternal2.
2F(or3.
3F)X7RcapacitorshouldbeconnectedbetweenVDDOUTandGND.
AdequateinputsupplydecouplingismandatoryforVDDINinordertoimprovestartupstabilityandreducesourcevoltagedrop.
Theinputdecouplingcapacitorshouldbeplacedclosetothechip.
Forexample,twocapacitorscanbeusedinparallel:100nFNPOand4.
7FX7R.
5.
4TypicalPoweringSchematicsTheAT91SAM7SE512/256/32supportsa3.
3Vsinglesupplymode.
Theinternalregulatorinputconnectedtothe3.
3VsourceanditsoutputfeedsVDDCOREandtheVDDPLL.
Figure5-1showsthepowerschematicstobeusedforUSBbus-poweredsystems.
Figure5-1.
3.
3VSystemSinglePowerSupplySchematicPowerSourcerangesfrom4.
5V(USB)to18V3.
3VVDDINVoltageRegulatorVDDOUTVDDIODC/DCConverterVDDCOREVDDFLASHVDDPLL156222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]6.
I/OLinesConsiderations6.
1JTAGPortPinsTMS,TDIandTCKareschmitttriggerinputsandarenot5V-tolerant.
TMS,TDIandTCKdonotintegrateapull-upresistor.
TDOisanoutput,drivenatuptoVDDIO,andhasnopull-upresistor.
ThepinJTAGSELisusedtoselecttheJTAGboundaryscanwhenassertedatahighlevel.
ThepinJTAGSELintegratesapermanentpull-downresistorofabout15ktoGND,sothatitcanbeleftunconnectedfornormaloperations.
6.
2TestPinTheTSTpinisusedformanufacturingtestorfastprogrammingmodeoftheAT91SAM7SE512/256/32whenassertedhigh.
TheTSTpinintegratesapermanentpull-downresistorofabout15ktoGND,sothatitcanbeleftunconnectedfornormaloperations.
Toenterfastprogrammingmode,theTSTpinandthePA0andPA1pinsshouldbetiedhighandPA2tiedlow.
DrivingtheTSTpinatahighlevelwhilePA0orPA1isdrivenat0leadstounpredictableresults.
6.
3ResetPinTheNRSTpinisbidirectional.
Itishandledbytheon-chipresetcontrollerandcanbedrivenlowtoprovidearesetsignaltotheexternalcomponentsorassertedlowexternallytoresetthemicrocontroller.
Thereisnoconstraintonthelengthoftheresetpulse,andtheresetcontrollercanguaranteeaminimumpulselength.
Thisallowsconnectionofasimplepush-buttonontheNRSTpinassystemuserreset,andtheuseoftheNRSTsignaltoresetallthecomponentsofthesystem.
Anexternalpower-onresetcandrivethispinduringthestart-upinsteadofusingtheinternalpower-onresetcircuit.
TheNRSTpinintegratesapermanentpull-upofabout100kresistortoVDDIO.
Thispinisnot5V-tolerantandhasschmitttriggerinput.
6.
4ERASEPinTheERASEpinisusedtore-initializetheFlashcontentandsomeofitsNVMbits.
Itintegratesapermanentpull-downresistorofabout15ktoGND,sothatitcanbeleftunconnectedfornor-maloperations.
ThispinisdebouncedbytheRCoscillatortoimprovetheglitchtolerance.
Whenthepinistiedtohighduringlessthan100ms,ERASEpinisnottakenintoaccount.
Thepinmustbetiedhighduringmorethan220mstoperformthere-initializationoftheFlash.
6.
5SDCKPinTheSDCKpinisdedicatedtotheSDRAMClockandisanoutput-onlywithoutpull-upandisnot5V-tolerant.
MaximumOutputFrequencyofthispadis48MHzat3.
0Vand25MHzat1.
65Vwithamaximumloadof30pF.
166222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]6.
6PIOControllerlinesAlltheI/OlinesPA0toPA31,PB0toPB31,PC0toPC23integrateaprogrammablepull-upresistor.
Programmingofthispull-upresistorisperformedindependentlyforeachI/OlinethroughthePIOcontrollers.
Typicalpull-upvalueis100k.
AlltheI/Olineshaveschmitttriggerinputs.
6.
7I/OLinesCurrentDrawingThePIOlinesPA0toPA3arehigh-drivecurrentcapable.
EachoftheseI/Olinescandriveupto16mApermanently.
TheremainingI/Olinescandrawonly8mA.
However,thetotalcurrentdrawnbyalltheI/Olinescannotexceed300mA.
176222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]7.
ProcessorandArchitecture7.
1ARM7TDMIProcessorRISCprocessorbasedonARMv4TVonNeumannarchitecture–Runsatupto48MHz,providing0.
9MIPS/MHzTwoinstructionsets–ARMhigh-performance32-bitinstructionset–Thumbhighcodedensity16-bitinstructionsetThree-stagepipelinearchitecture–InstructionFetch(F)–InstructionDecode(D)–Execute(E)7.
2DebugandTestFeaturesEmbeddedICE(Integratedembeddedin-circuitemulator)–Twowatchpointunits–TestaccessportaccessiblethroughaJTAGprotocol–DebugcommunicationchannelDebugUnit–Two-pinUART–Debugcommunicationchannelinterrupthandling–ChipIDRegisterIEEE1149.
1JTAGBoundary-scanonalldigitalpins7.
3MemoryControllerProgrammableBusArbiter–HandlesrequestsfromtheARM7TDMIandthePeripheralDMAControllerAddressdecoderprovidesselectionsignalsfor–Fourinternal1Mbytememoryareas–One256-Mbyteembeddedperipheralarea–Eightexternal256-MbytememoryareasAbortStatusRegisters–Source,Typeandallparametersoftheaccessleadingtoanabortaresaved–FacilitatesdebugbydetectionofbadpointersMisalignmentDetector–Alignmentcheckingofalldataaccesses–AbortgenerationincaseofmisalignmentRemapCommand–RemapstheSRAMinplaceoftheembeddednon-volatilememory–Allowshandlingofdynamicexceptionvectors16-areaMemoryProtectionUnit(InternalMemoryandperipheralprotectiononly)186222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]–Individuallyprogrammablesizebetween1KByteand1MByte–Individuallyprogrammableprotectionagainstwriteand/oruseraccess–Peripheralprotectionagainstwriteand/oruseraccessEmbeddedFlashController–EmbeddedFlashinterface,uptothreeprogrammablewaitstates–Prefetchbuffer,bufferingandanticipatingthe16-bitrequests,reducingtherequiredwaitstates–Key-protectedprogram,eraseandlock/unlocksequencer–Singlecommandforerasing,programmingandlockingoperations–Interruptgenerationincaseofforbiddenoperation7.
4ExternalBusInterfaceIntegratesThreeExternalMemoryControllers:–StaticMemoryController–SDRAMController–ECCControllerAdditionalLogicforNANDFlashandCompactFlashSupport–NANDFlashsupport:8-bitaswellas16-bitdevicesaresupported–CompactFlashsupport:allmodes(AttributeMemory,CommonMemory,I/O,TrueIDE)aresupportedbutthesignals_IOIS16(I/OandTrueIDEmodes)and-ATASEL(TrueIDEmode)arenothandled.
OptimizedExternalBus:–16-or32-bitDataBus(32-bitDataBusforSDRAMonly)–Upto23-bitAddressBus,Upto8-MbytesAddressable–Upto8ChipSelects,eachreservedtooneoftheeightMemoryAreas–OptimizedpinmultiplexingtoreducelatenciesonExternalMemoriesConfigurableChipSelectAssignment:–StaticMemoryControlleronNCS0–SDRAMControllerorStaticMemoryControlleronNCS1–StaticMemoryControlleronNCS2,OptionalCompactFlashSupport–StaticMemoryControlleronNCS3,NCS5-NCS6,OptionalNANDFlashSupport–StaticMemoryControlleronNCS4,OptionalCompactFlashSupport–StaticMemoryControlleronNCS77.
5StaticMemoryControllerExternalmemorymapping,512-Mbyteaddressspace8-,or16-bitDataBusUpto8ChipSelectLinesMultipleAccessModessupported–ByteWriteorByteSelectLines–TwodifferentReadProtocolsforeachMemoryBank196222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Multipledeviceadaptability–CompliantwithLCDModule–ProgrammableSetupTimeRead/Write–ProgrammableHoldTimeRead/WriteMultipleWaitStateManagement–ProgrammableWaitStateGeneration–ExternalWaitRequest–ProgrammableDataFloatTime7.
6SDRAMControllerNumerousconfigurationssupported–2K,4K,8KRowAddressMemoryParts–SDRAMwithtwoorfourInternalBanks–SDRAMwith16-or32-bitDataPathProgrammingfacilities–Word,half-word,byteaccess–AutomaticpagebreakwhenMemoryBoundaryhasbeenreached–MultibankPing-pongAccess–Timingparametersspecifiedbysoftware–Automaticrefreshoperation,refreshrateisprogrammableEnergy-savingcapabilities–Self-refresh,andLow-powerModessupportedErrordetection–RefreshErrorInterruptSDRAMPower-upInitializationbysoftwareLatencyissettotwoclocks(CASLatencyof1,3NotSupported)AutoPrechargeCommandnotused7.
7ErrorCorrectedCodeControllerTrackingtheaccessestoaNANDFlashdevicebytriggeringonthecorrespondingchipselectSinglebiterrorcorrectionand2-bitRandomdetection.
AutomaticHammingCodeCalculationwhilewriting–ECCvalueavailableinaregisterAutomaticHammingCodeCalculationwhilereading–ErrorReport,includingerrorflag,correctableerrorflagandwordaddressbeingdetectederroneous–Supports8-or16-bitNANDFlashdeviceswith512-,1024-,2048-or4096-bytepages7.
8PeripheralDMAControllerHandlesdatatransferbetweenperipheralsandmemoriesElevenchannels206222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]–TwoforeachUSART–TwofortheDebugUnit–TwofortheSerialSynchronousController–TwofortheSerialPeripheralInterface–OnefortheAnalog-to-digitalConverterLowbusarbitrationoverhead–OneMasterClockcycleneededforatransferfrommemorytoperipheral–TwoMasterClockcyclesneededforatransferfromperipheraltomemoryNextPointermanagementforreducinginterruptlatencyrequirements216222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]8.
Memories512KbytesofFlashMemory(AT91SAM7SE512)–dualplane–twocontiguousbanksof1024pagesof256bytes–Fastaccesstime,30MHzsingle-cycleaccessinWorstCaseconditions–Pageprogrammingtime:6ms,includingpageauto-erase–Pageprogrammingwithoutauto-erase:3ms–Fullchiperasetime:15ms–10,000writecycles,10-yeardataretentioncapability–32lockbits,eachprotecting32lockregionsof64pages–ProtectionModetosecurecontentsoftheFlash256KbytesofFlashMemory(AT91SAM7SE256)–singleplane–onebankof1024pagesof256bytes–Fastaccesstime,30MHzsingle-cycleaccessinWorstCaseconditions–Pageprogrammingtime:6ms,includingpageauto-erase–Pageprogrammingwithoutauto-erase:3ms–Fullchiperasetime:15ms–10,000cycles,10-yeardataretentioncapability–16lockbits,eachprotecting16lockregionsof64pages–ProtectionModetosecurecontentsoftheFlash32KbytesofFlashMemory(AT91SAM7SE32)–singleplane–onebankof256pagesof128bytes–Fastaccesstime,30MHzsingle-cycleaccessinWorstCaseconditions–Pageprogrammingtime:6ms,includingpageauto-erase–Pageprogrammingwithoutauto-erase:3ms–Fullchiperasetime:15ms–10,000cycles,10-yeardataretentioncapability–8lockbits,eachprotecting8lockregionsof32pages–ProtectionModetosecurecontentsoftheFlash32KbytesofFastSRAM(AT91SAM7SE512/256)–Single-cycleaccessatfullspeed8KbytesofFastSRAM(AT91SAM7SE32)–Single-cycleaccessatfullspeed226222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Figure8-1.
AT91SAM7SEMemoryMappingInternalPeripherals0x100000000x000000000x0FFFFFFF0x200000000x1FFFFFFF0x300000000x2FFFFFFF0x400000000x3FFFFFFF0x6FFFFFFF0x600000000x5FFFFFFF0x500000000x4FFFFFFF0x700000000x7FFFFFFF0x800000000x8FFFFFFF0x900000000xF00000000xEFFFFFFF0xFFFFFFFF256MBytes256MBytes256MBytes256MBytes256MBytes256MBytes256MBytes256MBytes256MBytes256MBytes6x256MBytes1,536MBytes0x000FFFFF0x001000000x001FFFFF0x002000000x002FFFFF0x003000000x003FFFFF0x004000000x000000001MBytes1MBytes1MBytes1MBytes252MBytes0xFFFA00000xFFFA3FFF0xFFFA40000xF00000000xFFFB80000xFFFC00000xFFFC3FFF0xFFFC40000xFFFC7FFF0xFFFD40000xFFFD7FFF0xFFFD3FFF0xFFFDFFFF0xFFFE00000xFFFE3FFF0xFFFFEFFF0xFFFFF0000xFFFFFFFF0xFFFE40000xFFFB40000xFFFB7FFF0xFFF9FFFF0xFFFCFFFF0xFFFD80000xFFFDBFFF0xFFFCBFFF0xFFFCC0000xFFFBFFFF0xFFFBC0000xFFFBBFFF0xFFFAFFFF0xFFFB00000xFFFB3FFF0xFFFD00000xFFFDC0000xFFFC800016Kbytes16Kbytes16Kbytes16Kbytes16Kbytes16Kbytes16Kbytes16Kbytes16Kbytes0x0FFFFFFF512Bytes/128registers512Bytes/128registers512Bytes/128registers256Bytes/64registers16Bytes/4registers16Bytes/4registers16Bytes/4registers16Bytes/4registers256Bytes/64registers4Bytes/1register512Bytes/128registers512Bytes/128registers0xFFFFF0000xFFFFF2000xFFFFF1FF0xFFFFF3FF0xFFFFF9FF0xFFFFFBFF0xFFFFFCFF0xFFFFFEFF0xFFFFFFFF0xFFFFF4000xFFFFFA000xFFFFFC000xFFFFFD0F0xFFFFFC2F0xFFFFFC3F0xFFFFFD4F0xFFFFFC6F0xFFFFF5FF0xFFFFF6000xFFFFF7FF0xFFFFF8000xFFFFFD000xFFFFFF000xFFFFFD200xFFFFFD300xFFFFFD400xFFFFFD600xFFFFFD70InternalMemoriesEBIChipSelect0SMCEBIChipSelect1/SMCorSDRAMCEBIChipSelect2SMCEBIChipSelect3SMC/NANDFlash/SmartMediaEBIChipSelect4SMCCompactFlashEBIChipSelect5SMCCompactFlashEBIChipSelect6EBIChipSelect7Undefined(Abort)(1)CanbeROM,FlashorSRAMdependingonGPNVM2andREMAPFlashbeforeRemapSRAMafterRemapInternalFlashInternalSRAMInternalROMReservedBootMemory(1)AddressMemorySpaceInternalMemoryMappingNote:TC0,TC1,TC2USART0USART1PWMCReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedTWISSCSPISYSCUDPADCAICDBGUPIOAReservedPMCMCWDTPITRTTRSTCVREGPIOBPIOCPeripheralMappingSystemControllerMapping236222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]AfirstlevelofaddressdecodingisperformedbytheMemoryController,i.
e.
,bytheimplementa-tionoftheAdvancedSystemBus(ASB)withadditionalfeatures.
Decodingsplitsthe4Gbytesofaddressspaceinto16areasof256Mbytes.
Theareas1to8aredirectedtotheEBIthatassociatestheseareastotheexternalchipselectsNC0toNCS7.
Thearea0isreservedfortheaddressingoftheinternalmemories,andasecondlevelofdecodingprovides1Mbyteofinternalmemoryarea.
Thearea15isreservedfortheperipheralsandpro-videsaccesstotheAdvancedPeripheralBus(APB).
Otherareasareunusedandperforminganaccesswithinthemprovidesanaborttothemasterrequestingsuchanaccess.
8.
1EmbeddedMemories8.
1.
1InternalMemories8.
1.
1.
1InternalSRAMTheAT91SAM7SE512/256embedsahigh-speed32-KbyteSRAMbank.
TheAT91SAM7SE32embedsahigh-speed8-KbyteSRAMbank.
AfterresetanduntiltheRemapCommandisper-formed,theSRAMisonlyaccessibleataddress0x00200000.
AfterRemap,theSRAMalsobecomesavailableataddress0x0.
8.
1.
1.
2InternalROMTheAT91SAM7SE512/256/32embedsanInternalROM.
Atanytime,theROMismappedataddress0x300000.
TheROMcontainstheFFPIandtheSAM-BAbootprogram.
8.
1.
1.
3InternalFlashTheAT91SAM7SE512featurestwobanksof256KbytesofFlash.
TheAT91SAM7SE256featuresonebankof256KbytesofFlash.
TheAT91SAM7SE32featuresonebankof32KbytesofFlash.
Atanytime,theFlashismappedtoaddress0x00100000.
AgeneralpurposeNVM(GPNVM)bitisusedtobooteitherontheROM(default)orfromtheFlash.
ThisGPNVMbitcanbeclearedorsetrespectivelythroughthecommands"ClearGeneral-pur-poseNVMBit"and"SetGeneral-purposeNVMBit"oftheEFCUserInterface.
SettingtheGPNVMbit2selectsthebootfromtheFlash,clearingitselectsthebootfromtheROM.
AssertingERASEclearstheGPNVMbit2andthusselectsthebootfromtheROMbydefault.
246222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Figure8-2.
InternalMemoryMappingwithGPNVMBit2=0(default)Figure8-3.
InternalMemoryMappingwithGPNVMBit2=18.
1.
2EmbeddedFlash8.
1.
2.
1FlashOverviewTheFlashoftheAT91SAM7SE512isorganizedintwobanks(dualplane)of1024pagesof256bytes.
Itreadsas131,07232-bitwords.
TheFlashoftheAT91SAM7SE256isorganizedin1024pages(singleplane)of256bytes.
Itreadsas65,53632-bitwords.
TheFlashoftheAT91SAM7SE32isorganizedin256pages(singleplane)of128bytes.
Itreadsas32,76832-bitwords.
TheFlashoftheAT91SAM7SE32containsa128-bytewritebuffer,accessiblethrougha32-bitinterface.
TheFlashoftheAT91SAM7SE512/256containsa256-bytewritebuffer,accessiblethrougha32-bitinterface.
256MBytesROMBeforeRemapSRAMAfterRemapUndefinedAreas(Abort)0x000FFFFF0x001FFFFF0x002FFFFF0x0FFFFFFF1MBytes1MBytes1MBytes252MBytesInternalFLASHInternalSRAM0x000000000x001000000x002000000x00300000InternalROM0x003FFFFF0x004000001MBytes256MBytesFlashBeforeRemapSRAMAfterRemapUndefinedAreas(Abort)0x000FFFFF0x001FFFFF0x002FFFFF0x0FFFFFFF1MBytes1MBytes1MBytes252MBytesInternalFLASHInternalSRAM0x000000000x001000000x002000000x00300000InternalROM0x003FFFFF0x004000001MBytes256222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]TheFlashbenefitsfromtheintegrationofapowerresetcellandfromthebrownoutdetector.
Thispreventscodecorruptionduringpowersupplychanges,evenintheworstconditions.
8.
1.
2.
2EmbeddedFlashControllerTheEmbeddedFlashController(EFC)managesaccessesperformedbythemastersofthesys-tem.
ItenablesreadingtheFlashandwritingthewritebuffer.
ItalsocontainsaUserInterface,mappedwithintheMemoryControllerontheAPB.
TheUserInterfaceallows:programmingoftheaccessparametersoftheFlash(numberofwaitstates,timings,etc.
)startingcommandssuchasfullerase,pageerase,pageprogram,NVMbitset,NVMbitclear,etc.
gettingtheendstatusofthelastcommandgettingerrorstatusprogramminginterruptsontheendofthelastcommandsoronerrorsTheEmbeddedFlashControlleralsoprovidesadual32-bitPrefetchBufferthatoptimizes16-bitaccesstotheFlash.
ThisisparticularlyefficientwhentheprocessorisrunninginThumbmode.
TwoEFCs(EFC0andEFC1)areembeddedintheSAM7SE512tocontroleachplaneof256KBytes.
DualplaneorganizationallowsconcurrentReadandProgram.
OneEFC(EFC0)isembeddedintheSAM7SE256tocontrolthesingleplane256KBytes.
OneEFC(EFC0)isembeddedintheSAM7SE32tocontrolthesingleplane32KBytes.
8.
1.
2.
3LockRegionsTheAT91SAM7SE512EmbeddedFlashControllermanages32lockbitstoprotect32regionsoftheflashagainstinadvertentflasherasingorprogrammingcommands.
TheAT91SAM7SE512contains32lockregionsandeachlockregioncontains64pagesof256bytes.
Eachlockregionhasasizeof16Kbytes.
TheAT91SAM7SE256EmbeddedFlashControllermanages16lockbitstoprotect16regionsoftheflashagainstinadvertentflasherasingorprogrammingcommands.
TheAT91SAM7SE256contains16lockregionsandeachlockregioncontains64pagesof256bytes.
Eachlockregionhasasizeof16Kbytes.
TheAT91SAM7SE32EmbeddedFlashControllermanages8lockbitstoprotect8regionsoftheflashagainstinadvertentflasherasingorprogrammingcommands.
TheAT91SAM7SE32contains8lockregionsandeachlockregioncontains32pagesof128bytes.
Eachlockregionhasasizeof4Kbytes.
Ifalocked-region'seraseorprogramcommandoccurs,thecommandisabortedandtheEFCtrigsaninterrupt.
The32(AT91SAM7SE512),16(AT91SAM7SE256)or8(AT91SAM7SE32)NVMbitsaresoft-wareprogrammablethroughtheEFCUserInterface.
Thecommand"SetLockBit"enablestheprotection.
Thecommand"ClearLockBit"unlocksthelockregion.
AssertingtheERASEpinclearsthelockbits,thusunlockingtheentireFlash.
8.
1.
2.
4SecurityBitFeatureTheAT91SAM7SE512/256/32featuresasecuritybit,basedonaspecificNVM-bit.
Whenthesecurityisenabled,anyaccesstotheFlash,eitherthroughtheICEinterfaceorthroughtheFastFlashProgrammingInterface,isforbidden.
266222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]ThesecuritybitcanonlybeenabledthroughtheCommand"SetSecurityBit"oftheEFCUserInterface.
DisablingthesecuritybitcanonlybeachievedbyassertingtheERASEpinat1andafterafullflasheraseisperformed.
Whenthesecuritybitisdeactivated,allaccessestotheflasharepermitted.
ItisimportanttonotethattheassertionoftheERASEpinshouldalwaysbelongerthan200ms.
AstheERASEpinintegratesapermanentpull-down,itcanbeleftunconnectedduringnormaloperation.
However,itissafertoconnectitdirectlytoGNDforthefinalapplication.
8.
1.
2.
5Non-volatileBrownoutDetectorControlTwogeneralpurposeNVM(GPNVM)bitsareusedforcontrollingthebrownoutdetector(BOD),sothatevenafterapowerloss,thebrownoutdetectoroperationsremainintheirstate.
ThesetwoGPNVMbitscanbeclearedorsetrespectivelythroughthecommands"ClearGen-eral-purposeNVMBit"and"SetGeneral-purposeNVMBit"oftheEFCUserInterface.
GPNVMbit0isusedasabrownoutdetectorenablebit.
SettingtheGPNVMbit0enablestheBOD,clearingitdisablestheBOD.
AssertingERASEclearstheGPNVMbit0andthusdisablesthebrownoutdetectorbydefault.
GPNVMbit1isusedasabrownoutresetenablesignalfortheresetcontroller.
SettingtheGPNVMbit1enablesthebrownoutresetwhenabrownoutisdetected,ClearingtheGPNVMbit1disablesthebrownoutreset.
AssertingERASEdisablesthebrownoutresetbydefault.
8.
1.
2.
6CalibrationBitsSixteenNVMbitsareusedtocalibratethebrownoutdetectorandthevoltageregulator.
Thesebitsarefactoryconfiguredandcannotbechangedbytheuser.
TheERASEpinhasnoeffectonthecalibrationbits.
8.
1.
3FastFlashProgrammingInterfaceTheFastFlashProgrammingInterfaceallowsprogrammingthedevicethrougheitheraserialJTAGinterfaceorthroughamultiplexedfully-handshakedparallelport.
Itallowsgang-program-mingwithmarket-standardindustrialprogrammers.
TheFFPIsupportsread,pageprogram,pageerase,fullerase,lock,unlockandprotectcommands.
TheFastFlashProgrammingInterfaceisenabledandtheFastProgrammingModeisenteredwhentheTSTpinandthePA0andPA1pinsarealltiedhighandPA2tiedtolow.
TheFlashoftheAT91SAM7SE512isorganizedin2048pagesof256bytes(dualplane).
Itreadsas131,07232-bitwords.
TheFlashoftheAT91SAM7SE256isorganizedin1024pagesof256bytes(singleplane).
Itreadsas65,53632-bitwords.
TheFlashoftheAT91SAM7SE32isorganizedin256pagesof128bytes(singleplane).
Itreadsas32,76832-bitwords.
TheFlashoftheAT91SAM7SE512/256containsa256-bytewritebuffer,accessiblethrougha32-bitinterface.
TheFlashoftheAT91SAM7SE32containsa128-bytewritebuffer,accessiblethrougha32-bitinterface.
276222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]8.
1.
4SAM-BABootTheSAM-BABootisadefaultBootProgramwhichprovidesaneasywaytoprogramin-situtheon-chipFlashmemory.
TheSAM-BABootAssistantsupportsserialcommunicationviatheDBGUortheUSBDevicePort.
CommunicationviatheDBGUsupportsawiderangeofcrystalsfrom3to20MHzviasoftwareauto-detection.
CommunicationviatheUSBDevicePortislimitedtoan18.
432MHzcrystal.
TheSAM-BABootprovidesaninterfacewithSAM-BAGraphicUserInterface(GUI).
TheSAM-BABootisinROMandismappedinFlashataddress0x0whenGPNVMbit2issetto0.
8.
2ExternalMemoriesTheexternalmemoriesareaccessedthroughtheExternalBusInterface.
RefertothememorymapinFigure8-1onpage22.
286222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]9.
SystemControllerTheSystemControllermanagesallvitalblocksofthemicrocontroller:interrupts,clocks,power,time,debugandreset.
TheSystemControllerperipheralsareallmappedtothehighest4Kbytesofaddressspace,betweenaddresses0xFFFFF000and0xFFFFFFFF.
Figure9-1onpage29showstheSystemControllerBlockDiagram.
Figure8-1onpage22showsthemappingoftheUserInterfaceoftheSystemControllerperiph-erals.
NotethattheMemoryControllerconfigurationuserinterfaceisalsomappedwithinthisaddressspace.
296222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Figure9-1.
SystemControllerBlockDiagramNRSTSLCKAdvancedInterruptControllerReal-TimeTimerPeriodicIntervalTimerResetControllerPA0-PA31periph_nresetSystemControllerWatchdogTimerwdt_faultWDRPROCPIOControllerPORBODRCOSCgpnvm[0]calenPowerManagementControllerOSCPLLXINXOUTPLLRCMAINCKPLLCKpit_irqMCKproc_nresetwdt_irqperiph_irq{2-3]periph_nresetperiph_clk[2.
.
18]PCKMCKpmc_irqUDPCKnirqnfiqrtt_irqEmbeddedPeripheralsperiph_clk[2-3]pck[0-3]inoutenableARM7TDMISLCKSLCKirq0-irq1fiqirq0-irq1fiqperiph_irq[4.
.
18]periph_irq[2.
.
18]intintperiph_nresetperiph_clk[4.
.
18]EmbeddedFlashflash_poejtag_nresetflash_poegpnvm[0.
.
2]flash_wrdisflash_wrdisproc_nresetperiph_nresetdbgu_txddbgu_rxdpit_irqrtt_irqdbgu_irqpmc_irqrstc_irqwdt_irqrstc_irqSLCKgpnvm[1]BoundaryScanTAPControllerjtag_nresetdebugPCKdebugidledebugMemoryControllerMCKproc_nresetbod_rst_enproc_nresetperiph_nresetperiph_nresetidleDebugUnitdbgu_irqMCKdbgu_rxdperiph_nresetforce_ntrstdbgu_txdUSBDevicePortUDPCKperiph_nresetperiph_clk[11]periph_irq[11]usb_suspendusb_suspendVoltageRegulatorstandbyVoltageRegulatorModeControllersecurity_bitcalpower_on_resetpower_on_resetforce_ntrstcalPB0-PB31PC0-PC29306222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]9.
1ResetControllerBasedononepower-onresetcellandadoublebrownoutdetectorStatusofthelastreset,eitherPower-upReset,SoftwareReset,UserReset,WatchdogReset,BrownoutResetControlstheinternalresetsandtheNRSTpinoutputAllowstoshapeasignalontheNRSTline,guaranteeingthatthelengthofthepulsemeetsanyrequirement.
9.
1.
1BrownoutDetectorandPowerOnResetTheAT91SAM7SE512/256/32embedsonebrownoutdetectioncircuitandapower-onresetcell.
Thepower-onresetissuppliedwithandmonitorsVDDCORE.
BothsignalsareprovidedtotheFlashtopreventanycodecorruptionduringpower-uporpower-downsequencesorifbrownoutsoccurontheVDDCOREpowersupply.
Thepower-onresetcellhasalimited-accuracythresholdataround1.
5V.
Itsoutputremainslowduringpower-upuntilVDDCOREgoesoverthisvoltagelevel.
Thissignalgoestotheresetcon-trollerandallowsafullre-initializationofthedevice.
ThebrownoutdetectormonitorstheVDDCOREandVDDFLASHlevelsduringoperationbycomparingittoafixedtriggerlevel.
Itsecuressystemoperationsinthemostdifficultenviron-mentsandpreventscodecorruptionincaseofbrownoutontheVDDCOREorVDDFLASH.
WhenthebrownoutdetectorisenabledandVDDCOREdecreasestoavaluebelowthetriggerlevel(Vbot18-,definedasVbot18-hyst/2),thebrownoutoutputisimmediatelyactivated.
WhenVDDCOREincreasesabovethetriggerlevel(Vbot18+,definedasVbot18+hyst/2),theresetisreleased.
ThebrownoutdetectoronlydetectsadropifthevoltageonVDDCOREstaysbelowthethresholdvoltageforlongerthanabout1s.
TheVDDCOREthresholdvoltagehasahysteresisofabout50mV,toensurespikefreebrown-outdetection.
Thetypicalvalueofthebrownoutdetectorthresholdis1.
68Vwithanaccuracyof±2%andisfactorycalibrated.
WhenthebrownoutdetectorisenabledandVDDFLASHdecreasestoavaluebelowthetriggerlevel(Vbot33-,definedasVbot33-hyst/2),thebrownoutoutputisimmediatelyactivated.
WhenVDDFLASHincreasesabovethetriggerlevel(Vbot33+,definedasVbot33+hyst/2),theresetisreleased.
ThebrownoutdetectoronlydetectsadropifthevoltageonVDDCOREstaysbelowthethresholdvoltageforlongerthanabout1s.
TheVDDFLASHthresholdvoltagehasahysteresisofabout50mV,toensurespikefreebrown-outdetection.
Thetypicalvalueofthebrownoutdetectorthresholdis2.
80Vwithanaccuracyof±3.
5%andisfactorycalibrated.
Thebrownoutdetectorislow-power,asitconsumeslessthan20Astaticcurrent.
However,itcanbedeactivatedtosaveitsstaticcurrent.
Inthiscase,itconsumeslessthan1A.
Thedeac-tivationisconfiguredthroughtheGPNVMbit0oftheFlash.
9.
2ClockGeneratorTheClockGeneratorembedsonelow-powerRCOscillator,oneMainOscillatorandonePLLwiththefollowingcharacteristics:RCOscillatorrangesbetween22KHzand42KHz316222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]MainOscillatorfrequencyrangesbetween3and20MHzMainOscillatorcanbebypassedPLLoutputrangesbetween80and220MHzItprovidesSLCK,MAINCKandPLLCK.
Figure9-2.
ClockGeneratorBlockDiagram9.
3PowerManagementControllerThePowerManagementControllerusestheClockGeneratoroutputstoprovide:theProcessorClockPCKtheMasterClockMCKtheUSBClockUDPCKalltheperipheralclocks,independentlycontrollablethreeprogrammableclockoutputsTheMasterClock(MCK)isprogrammablefromafewhundredHztothemaximumoperatingfre-quencyofthedevice.
TheProcessorClock(PCK)switchesoffwhenenteringprocessoridlemode,thusallowingreducedpowerconsumptionwhilewaitingforaninterrupt.
PowerManagementControllerXINXOUTPLLRCSlowClockSLCKMainClockMAINCKPLLClockPLLCKControlStatusEmbeddedRCOscillatorMainOscillatorPLLandDividerClockGenerator326222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Figure9-3.
PowerManagementControllerBlockDiagram9.
4AdvancedInterruptControllerControlstheinterruptlines(nIRQandnFIQ)ofanARMProcessorIndividuallymaskableandvectoredinterruptsources–Source0isreservedfortheFastInterruptInput(FIQ)–Source1isreservedforsystemperipherals(RTT,PIT,EFC,PMC,DBGU,etc.
)–Othersourcescontroltheperipheralinterruptsorexternalinterrupts–Programmableedge-triggeredorlevel-sensitiveinternalsources–Programmablepositive/negativeedge-triggeredorhigh/lowlevel-sensitiveexternalsources8-levelPriorityController–DrivesthenormalinterruptnIRQoftheprocessor–Handlespriorityoftheinterruptsources–HigherpriorityinterruptscanbeservedduringserviceoflowerpriorityinterruptVectoring–Optimizesinterruptserviceroutinebranchandexecution–One32-bitvectorregisterperinterruptsource–InterruptvectorregisterreadsthecorrespondingcurrentinterruptvectorProtectMode–EasydebuggingbypreventingautomaticoperationsFastForcing–PermitsredirectinganyinterruptsourceonthefastinterruptGeneralInterruptMask–ProvidesprocessorsynchronizationoneventswithouttriggeringaninterruptMCKperiph_clk[2.
.
14]intUDPCKSLCKMAINCKPLLCKPrescaler/1,/2,/4,.
.
.
,/64PCKProcessorClockControllerIdleModeMasterClockControllerPeripheralsClockControllerON/OFFUSBClockControllerON/OFFSLCKMAINCKPLLCKPrescaler/1,/2,/4,.
.
.
,/64ProgrammableClockControllerPLLCKDivider/1,/2,/4pck[0.
.
2]usb_suspend336222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]9.
5DebugUnitComprises:–Onetwo-pinUART–OneInterfacefortheDebugCommunicationChannel(DCC)support–OnesetofChipIDRegisters–OneInterfaceprovidingICEAccessPreventionTwo-pinUART–USART-compatibleUserInterface–ProgrammableBaudRateGenerator–Parity,FramingandOverrunError–AutomaticEcho,LocalLoopbackandRemoteLoopbackChannelModesDebugCommunicationChannelSupport–OffersvisibilityofCOMMRXandCOMMTXsignalsfromtheARMProcessorChipIDRegisters–Identificationofthedevicerevision,sizesoftheembeddedmemories,setofperipherals–ChipIDis0x272A0A40(VERSION0)forAT91SAM7SE512–ChipIDis0x272A0940(VERSION0)forAT91SAM7SE256–ChipIDis0x27280340(VERSION0)forAT91SAM7SE329.
6PeriodicIntervalTimer20-bitprogrammablecounterplus12-bitintervalcounter9.
7WatchdogTimer12-bitkey-protectedProgrammableCounterrunningonprescaledSLCKProvidesresetorinterruptsignalstothesystemCountermaybestoppedwhiletheprocessorisindebugstateorinidlemode9.
8Real-timeTimer32-bitfree-runningcounterwithalarmrunningonprescaledSLCKProgrammable16-bitprescalerforSLCKaccuracycompensation9.
9PIOControllersThreePIOControllers.
PIOAandBeachcontrol32I/OlinesandPIOCcontrols24I/Olines.
Fullyprogrammablethroughset/clearregistersMultiplexingoftwoperipheralfunctionsperI/OlineForeachI/Oline(whetherassignedtoaperipheralorusedasgeneral-purposeI/O)–Inputchangeinterrupt–Halfaclockperiodglitchfilter–Multi-driveoptionenablesdrivinginopendrain–Programmablepull-uponeachI/Oline–Pindatastatusregister,suppliesvisibilityofthelevelonthepinatanytime346222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Synchronousoutput,providesSetandClearofseveralI/Olinesinasinglewrite9.
10VoltageRegulatorControllerThepurposeofthiscontrolleristoselectthePowerModeoftheVoltageRegulatorbetweenNormalMode(bit0iscleared)orStandbyMode(bit0isset).
356222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]10.
Peripherals10.
1UserInterfaceTheUserPeripheralsaremappedinthe256MBytesoftheaddressspacebetween0xF0000000and0xFFFFEFFF.
Eachperipheralisallocated16Kbytesofaddressspace.
AcompletememorymapispresentedinFigure8-1onpage22.
10.
2PeripheralIdentifiersTheAT91SAM7SE512/256/32embedsawiderangeofperipherals.
Table10-1definesthePeripheralIdentifiersoftheAT91SAM7SE512/256/32.
UniqueperipheralidentifiersaredefinedforboththeAdvancedInterruptControllerandthePowerManagementController.
Note:1.
SettingSYSIRQandADCbitsintheclockset/clearregistersofthePMChasnoeffect.
TheSystemControllerandADCarecontinuouslyclocked.
TheADCclockisautomaticallystartedforthefirstconversion.
InSleepModetheADCclockisautomaticallystoppedaftereachconversion.
Table10-1.
PeripheralIdentifiersPeripheralIDPeripheralMnemonicPeripheralNameExternalInterrupt0AICAdvancedInterruptControllerFIQ1SYSIRQ(1)2PIOAParallelI/OControllerA3PIOBParallelI/OControllerB4PIOCParallelI/OControllerC5SPISerialPeripheralInterface06US0USART07US1USART18SSCSynchronousSerialController9TWITwo-wireInterface10PWMCPWMController11UDPUSBDevicePort12TC0Timer/Counter013TC1Timer/Counter114TC2Timer/Counter215ADC(1)Analog-toDigitalConverter16-28reserved29AICAdvancedInterruptControllerIRQ030AICAdvancedInterruptControllerIRQ1366222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]10.
3PeripheralMultiplexingonPIOLinesTheAT91SAM7SE512/256/32featuresthreePIOcontrollers,PIOA,PIOBandPIOC,thatmulti-plextheI/Olinesoftheperipheralset.
PIOControllerAandBcontrol32lines;PIOControllerCcontrols24lines.
Eachlinecanbeassignedtooneoftwoperipheralfunctions,AorB.
SomeofthemcanalsobemultiplexedwiththeanaloginputsoftheADCController.
Table10-2onpage37defineshowtheI/OlinesoftheperipheralsAandBortheanaloginputsaremultiplexedonthePIOControllerA,BandC.
Thetwocolumns"Function"and"Comments"havebeeninsertedfortheuser'sowncomments;theymaybeusedtotrackhowpinsaredefinedinanapplication.
Notethatsomeperipheralfunctionsthatareoutputonlymaybeduplicatedinthetable.
Atreset,allI/Olinesareautomaticallyconfiguredasinputwiththeprogrammablepull-upenabled,sothatthedeviceismaintainedinastaticstateassoonasaresetisdetected.
376222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]10.
4PIOControllerAMultiplexingTable10-2.
MultiplexingonPIOControllerAPIOControllerAApplicationUsageI/OLinePeripheralAPeripheralBCommentsFunctionCommentsPA0PWM0A0/NBS0High-DrivePA1PWM1A1/NBS2High-DrivePA2PWM2A2High-DrivePA3TWDA3High-DrivePA4TWCKA4PA5RXD0A5PA6TXD0A6PA7RTS0A7PA8CTS0A8PA9DRXDA9PA10DTXDA10PA11NPCS0A11PA12MISOA12PA13MOSIA13PA14SPCKA14PA15TFA15PA16TKA16/BA0PA17TDA17/BA1AD0PA18RDNBS3/CFIOWAD1PA19RKNCS4/CFCS0AD2PA20RFNCS2/CFCS1AD3PA21RXD1NCS6/CFCE2PA22TXD1NCS5/CFCE1PA23SCK1NWR1/NBS1/CFIORPA24RTS1SDA10PA25CTS1SDCKEPA26DCD1NCS1/SDCSPA27DTR1SDWEPA28DSR1CASPA29RI1RASPA30IRQ1D30PA31NPCS1D31386222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]10.
5PIOControllerBMultiplexingTable10-3.
MultiplexingonPIOControllerBPIOControllerBApplicationUsageI/OLinePeripheralAPeripheralBCommentsFunctionCommentsPB0TIOA0A0/NBS0PB1TIOB0A1/NBS2PB2SCK0A2PB3NPCS3A3PB4TCLK0A4PB5NPCS3A5PB6PCK0A6PB7PWM3A7PB8ADTRGA8PB9NPCS1A9PB10NPCS2A10PB11PWM0A11PB12PWM1A12PB13PWM2A13PB14PWM3A14PB15TIOA1A15PB16TIOB1A16/BA0PB17PCK1A17/BA1PB18PCK2D16PB19FIQD17PB20IRQ0D18PB21PCK1D19PB22NPCS3D20PB23PWM0D21PB24PWM1D22PB25PWM2D23PB26TIOA2D24PB27TIOB2D25PB28TCLK1D26PB29TCLK2D27PB30NPCS2D28PB31PCK2D29396222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]10.
6PIOControllerCMultiplexing10.
7SerialPeripheralInterfaceSupportscommunicationwithexternalserialdevices–Fourchipselectswithexternaldecoderallowcommunicationwithupto15peripherals–Serialmemories,suchasDataFlashand3-wireEEPROMs–Serialperipherals,suchasADCs,DACs,LCDControllers,CANControllersandSensors–Externalco-processorsMasterorslaveserialperipheralbusinterfaceMultiplexingonPIOControllerCPIOControllerCApplicationUsageI/OLinePeripheralAPeripheralBCommentsFunctionCommentsPC0D0PC1D1PC2D2PC3D3PC4D4PC5D5PC6D6PC7D7PC8D8RTS1PC9D9DTR1PC10D10PCK0PC11D11PCK1PC12D12PCK2PC13D13PC14D14NPCS1PC15D15NCS3/NANDCSPC16A18NWAITPC17A19NANDOEPC18A20NANDWEPC19A21/NANDALEPC20A22/REG/NANDCLENCS7PC21NWR0/NWE/CFWEPC22NRD/CFOEPC23CFRNWNCS0406222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]–8-to16-bitprogrammabledatalengthperchipselect–Programmablephaseandpolarityperchipselect–Programmabletransferdelaysperchipselect,betweenconsecutivetransfersandbetweenclockanddata–Programmabledelaybetweenconsecutivetransfers–Selectablemodefaultdetection–MaximumfrequencyatuptoMasterClock10.
8TwoWireInterfaceMaster,Multi-MasterandSlaveModeOperationCompatibilitywithstandardtwo-wireserialmemoriesOne,twoorthreebytesforslaveaddressSequentialread/writeoperationsBitRate:Upto400Kbit/sGeneralCallSupportedinSlaveMode10.
9USARTProgrammableBaudRateGenerator5-to9-bitfull-duplexsynchronousorasynchronousserialcommunications–1,1.
5or2stopbitsinAsynchronousMode–1or2stopbitsinSynchronousMode–Paritygenerationanderrordetection–Framingerrordetection,overrunerrordetection–MSBorLSBfirst–Optionalbreakgenerationanddetection–By8orby16over-samplingreceiverfrequency–HardwarehandshakingRTS-CTS–ModemSignalsManagementDTR-DSR-DCD-RIonUSART1–Receivertime-outandtransmittertimeguard–Multi-dropModewithaddressgenerationanddetectionRS485withdrivercontrolsignalISO7816,T=0orT=1Protocolsforinterfacingwithsmartcards–NACKhandling,errorcounterwithrepetitionanditerationlimitIrDAmodulationanddemodulation–Communicationatupto115.
2KbpsTestModes–RemoteLoopback,LocalLoopback,AutomaticEcho10.
10SerialSynchronousControllerProvidesserialsynchronouscommunicationlinksusedinaudioandtelecomapplicationsContainsanindependentreceiverandtransmitterandacommonclockdivider416222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]OffersaconfigurableframesyncanddatalengthReceiverandtransmittercanbeprogrammedtostartautomaticallyorondetectionofdifferenteventontheframesyncsignalReceiverandtransmitterincludeadatasignal,aclocksignalandaframesynchronizationsignal10.
11TimerCounterThree16-bitTimerCounterChannels–ThreeoutputcompareortwoinputcaptureWiderangeoffunctionsincluding:–Frequencymeasurement–Eventcounting–Intervalmeasurement–Pulsegeneration–Delaytiming–PulseWidthModulation–Up/downcapabilitiesEachchannelisuser-configurableandcontains:–Threeexternalclockinputs–Fiveinternalclockinputs,asdefinedinTable10-4–Twomulti-purposeinput/outputsignals–TwoglobalregistersthatactonallthreeTCchannels10.
12PWMControllerFourchannels,one16-bitcounterperchannelCommonclockgenerator,providingthirteendifferentclocks–OneModuloncounterprovidingelevenclocks–TwoindependentlineardividersworkingonmoduloncounteroutputsIndependentchannelprogramming–Independentenable/disablecommands–Independentclockselection–Independentperiodanddutycycle,withdoublebuffering–Programmableselectionoftheoutputwaveformpolarity–ProgrammablecenterorleftalignedoutputwaveformTable10-4.
TimerCounterClocksAssignmentTCClockinputClockTIMER_CLOCK1MCK/2TIMER_CLOCK2MCK/8TIMER_CLOCK3MCK/32TIMER_CLOCK4MCK/128TIMER_CLOCK5MCK/1024426222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]10.
13USBDevicePortUSBV2.
0full-speedcompliant,12Mbitspersecond.
EmbeddedUSBV2.
0full-speedtransceiverEmbedded2688-bytedual-portRAMforendpointsEightendpoints–Endpoint0:64bytes–Endpoint1and2:64bytesping-pong–Endpoint3:64bytes–Endpoint4and5:512bytesping-pong–Endpoint6and7:64bytesping-pong–Ping-pongMode(twomemorybanks)forIsochronousandbulkendpointsSuspend/resumelogicIntegratedPull-uponDDP10.
14Analog-to-DigitalConverter8-channelADC10-bit384Ksamples/sec.
or8-bit583Ksamples/sec.
SuccessiveApproximationRegisterADC-3/+3LSBIntegralNonLinearity,-2/+2LSBDifferentialNonLinearityIntegrated8-to-1multiplexer,offeringeightindependent3.
3VanaloginputsExternalvoltagereferenceforbetteraccuracyonlowvoltageinputsIndividualenableanddisableofeachchannelMultipletriggersources–Hardwareorsoftwaretrigger–Externaltriggerpin–TimerCounter0to2outputsTIOA0toTIOA2triggerSleepModeandconversionsequencer–AutomaticwakeupontriggerandbacktosleepmodeafterconversionsofallenabledchannelsEachanaloginputsharedwithdigitalsignals436222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]11.
PackageDrawingsFigure11-1.
128-leadLQFPPackageDrawingThispackagerespectstherecommendationsoftheNEMIUserGroup.
Table11-1.
DeviceandLQFPPackageMaximumWeightAT91SAM7SE512/256/32800mgTable11-2.
PackageReferenceJEDECDrawingReferenceMS-026JESD97Classificatione2Table11-3.
LQFPPackageCharacteristicsMoistureSensitivityLevel3446222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]Figure11-2.
144-ballLFBGAPackageDrawingThispackagerespectstherecommendationsoftheNEMIUserGroup.
AlldimensionsareinmmTable11-4.
DeviceandLFBAPackageMaximumWeightAT91SAM7SE512/256/32mgTable11-5.
PackageReferenceJEDECDrawingReferenceMS-026JESD97Classificatione1Table11-6.
LFBGAPackageCharacteristicsMoistureSensitivityLevel3456222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]12.
OrderingInformationTable12-1.
OrderingInformationOrderingCodePackagePackageTypeTemperatureOperatingRangeAT91SAM7SE512-AULQFP128GreenIndustrial(-40°Cto85°C)AT91SAM7SE256-AULQFP128GreenIndustrial(-40°Cto85°C)AT91SAM7SE32-AULQFP128GreenIndustrial(-40°Cto85°C)AT91SAM7SE512-CJLFBGA144GreenIndustrial(-40°Cto85°C)AT91SAM7SE256-CJLFBGA144GreenIndustrial(-40°Cto85°C)AT91SAM7SE32-CJLFBGA144GreenIndustrial(-40°Cto85°C)466222AS–ATARM–21-Aug-06AT91SAM7SE512/256/32[AdvanceInformationSummary]RevisionHistoryDoc.
RevCommentsChangeRequestRef.
622ASFirstissueRevisedMemorieswithcondensedmapping.
AddedPackageOutlinesand144-ballLFBGApinandorderinginformation.
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