ZEROS小米3大概要多少钱

3MSPS,10-/12-BitADCsin8-LeadTSOTAD7273/AD7274Rev.
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FEATURESThroughputrate:3MSPSSpecifiedforVDDof2.
35Vto3.
6VPowerconsumption11.
4mWat3MSPSwith3VsuppliesWideinputbandwidth70dBSNRat1MHzinputfrequencyFlexiblepower/serialclockspeedmanagementNopipelinedelaysHighspeedserialinterfaceSPI-/QSPI-/MICROWIRE-/DSP-compatibleTemperaturerange:40°Cto+125°CPower-downmode:0.
1μAtyp8-leadTSOTpackage8-leadMSOPpackageGENERALDESCRIPTIONTheAD7273/AD7274are10-/12-bit,highspeed,lowpower,successiveapproximationADCs,respectively.
Thepartsoperatefromasingle2.
35Vto3.
6Vpowersupplyandfeaturethroughputratesofupto3MSPS.
Eachpartcontainsalownoise,widebandwidthtrack-and-holdamplifierthatcanhandleinputfrequenciesinexcessof55MHz.
TheconversionprocessanddataacquisitionarecontrolledusingCSandtheserialclock,allowingthedevicestointerfacewithmicroprocessorsorDSPs.
TheinputsignalissampledonthefallingedgeofCS,andtheconversionisalsoinitiatedatthispoint.
TheconversionrateisdeterminedbytheSCLK.
Therearenopipelinedelaysassociatedwiththeseparts.
TheAD7273/AD7274useadvanceddesigntechniquestoachieveverylowpowerdissipationathighthroughputrates.
Thereferenceforthepartsisappliedexternallyandcanbeintherangeof1.
4VtoVDD.
ThisallowsthewidestdynamicinputrangetotheADC.
FUNCTIONALBLOCKDIAGRAMT/HCONTROLLOGIC10-/12-BITSUCCESSIVEAPPROXIMATIONADCDGNDVDDAD7273/AD7274VINAGNDSCLKSDATACSVREF04973-001Figure1.
Table1.
PartNumberResolutionPackageAD72731108-leadMSOP8-LeadTSOTAD72741128-leadMSOP8-LeadTSOTAD7276128-leadMSOP6-LeadTSOTAD7277108-leadMSOP6-LeadTSOTAD727888-leadMSOP6-LeadTSOT1Partscontainexternalreferencepin.
PRODUCTHIGHLIGHTS1.
3MSPSADCsinan8-leadTSOTpackage.
2.
Highthroughputwithlowpowerconsumption.
3.
Flexiblepower/serialclockspeedmanagement.
Allowsmaximumpowerefficiencyatlowthroughputrates.
4.
Referencecanbedrivenuptothepowersupply.
5.
Nopipelinedelay.
6.
ThepartsfeatureastandardsuccessiveapproximationADCwithaccuratecontrolofthesamplinginstantviaaCSinputandonce-offconversioncontrol.
AD7273/AD7274Rev.
0|Page2of28TABLEOFCONTENTSFeatures1GeneralDescription.
1FunctionalBlockDiagram1ProductHighlights1RevisionHistory2Specifications.
3AD7274Specifications.
3AD7273Specifications.
5TimingSpecifications7TimingExamples.
8AbsoluteMaximumRatings.
9ESDCaution.
9PinConfigurationsandFunctionDescriptions10TypicalPerformanceCharacteristics11Terminology.
14CircuitInformation.
15ConverterOperation.
15ADCTransferFunction.
15TypicalConnectionDiagram16AnalogInput.
16DigitalInputs16ModesofOperation17NormalMode.
17PartialPower-DownMode17FullPower-DownMode.
17Power-UpTimes.
18Powervs.
ThroughputRate.
20SerialInterface21MicroprocessorInterfacing.
23ApplicationHints24GroundingandLayout24EvaluatingtheAD7273/AD7274Performance.
24OutlineDimensions.
25OrderingGuide25REVISIONHISTORY9/05—Revision0:InitialVersionAD7273/AD7274Rev.
0|Page3of28SPECIFICATIONSAD7274SPECIFICATIONSVDD=2.
35Vto3.
6V,VREF=2.
35VtoVDD,fSCLK=48MHz,fSAMPLE=3MSPS,TA=TMINtoTMAX,unlessotherwisenoted.
Table2.
ParameterBGrade1Unit2TestConditions/CommentsDYNAMICPERFORMANCEfIN=1MHzsinewaveSignal-to-Noise+Distortion(SINAD)368dBminSignal-to-NoiseRatio(SNR)69.
5dBminTotalHarmonicDistortion(THD)373dBmax78dBtypPeakHarmonicorSpuriousNoise(SFDR)380dBtypIntermodulationDistortion(IMD)Second-OrderTerms82dBtypfa=1MHz,fb=0.
97MHzThird-OrderTerms82dBtypfa=1MHz,fb=0.
97MHzApertureDelay5nstypApertureJitter18pstypFullPowerBandwidth55MHztyp@3dB8MHztyp@0.
1dBPowerSupplyRejectionRatio(PSRR)82dBtypDCACCURACYResolution12BitsIntegralNonlinearity3±1LSBmaxDifferentialNonlinearity3±1LSBmaxGuaranteednomissedcodesto12bitsOffsetError3±3LSBmaxGainError3±3.
5LSBmaxTotalUnadjustedError(TUE)3±3.
5LSBmaxANALOGINPUTInputVoltageRange0toVREFVDCLeakageCurrent±1μAmax40°Cto+85°C±5.
5μAmax85°Cto125°CInputCapacitance42pFtypWhenintrack10pFtypWheninholdREFERENCEINPUTVREFInputVoltageRange1.
4toVDDVmin/VmaxDCleakageCurrent±1μAmaxInputCapacitance20pFtypInputImpedance32ΩtypLOGICINPUTSInputHighVoltage,VINH1.
7Vmin2.
35V≤VDD≤2.
7V2Vmin2.
7V6VInputLowVoltage,VINL0.
7Vmax2.
35V≤VDD<2.
7V0.
8Vmax2.
7V≤VDD≤3.
6VInputCurrent,IIN±1μAmaxTypically10nA,VIN=0VorVDDInputCapacitance,CIN42pFmaxLOGICOUTPUTSOutputHighVoltage,VOHVDD0.
2VminISOURCE=200μA,VDD=2.
35Vto3.
6VOutputLowVoltage,VOL0.
2VmaxISINK=200μAFloating-StateLeakageCurrent±2.
5μAmaxFloating-StateOutputCapacitance44.
5pFmaxOutputCodingStraight(natural)binaryAD7273/AD7274Rev.
0|Page4of28ParameterBGrade1Unit2TestConditions/CommentsCONVERSIONRATEConversionTime291nsmax14SCLKcycleswithSCLKat48MHzTrack-and-HoldAcquisitionTime360nsmaxThroughputRate3MSPSmaxSeetheSerialInterfacesectionPOWERRQUIREMENTSVDD2.
35/3.
6Vmin/VmaxIDDDigitalI/Ps=0VorVDDNormalMode(Static)1mAtypVDD=3V,SCLKonoroffNormalMode(Operational)5mAmaxVDD=2.
35Vto3.
6V,fSAMPLE=3MSPS3.
8mAtypVDD=3VPartialPower-DownMode(Static)34μAtypFullPower-DownMode(Static)2μAmax40°Cto+85°C,typically0.
1μA10μAmax85°Cto125°CPowerDissipation5NormalMode(Operational)18mWmaxVDD=3.
6V,fSAMPLE=3MSPS11.
4mWtypVDD=3VPartialPower-Down102μWmaxVDD=3VFullPower-Down7.
2μWmaxVDD=3.
6V,40°Cto+85°C1Temperaturerangefrom40°Cto+125°C.
2TypicalspecificationsaretestedwithVDD=3VandVREF=3Vat25°C.
3SeetheTerminologysection.
4Guaranteedbycharacterization.
5SeethePowervs.
ThroughputRatesection.
AD7273/AD7274Rev.
0|Page5of28AD7273SPECIFICATIONSVDD=2.
35Vto3.
6V,VREF=2.
35VtoVDD,fSCLK=48MHz,fSAMPLE=3MSPS,TA=TMINtoTMAX,unlessotherwisenoted.
Table3.
ParameterBGrade1Unit2TestConditions/CommentsDYNAMICPERFORMANCEfIN=1MHzsinewaveSignal-to-Noise+Distortion(SINAD)361dBminTotalHarmonicDistortion(THD)372dBmax77dBtypPeakHarmonicorSpuriousNoise(SFDR)380dBtypIntermodulationDistortion(IMD)Second-OrderTerms81dBtypfa=1MHz,fb=0.
97MHzThird-OrderTerms81dBtypfa=1MHz,fb=0.
97MHzApertureDelay5nstypApertureJitter18pstypFullPowerBandwidth74MHztyp@3dB10MHztyp@0.
1dBPowerSupplyRejectionRatio(PSRR)82dBtypDCACCURACYResolution10BitsIntegralNonlinearity3±0.
5LSBmaxDifferentialNonlinearity3±0.
5LSBmaxGuaranteednomissedcodesto10bitsOffsetError3±1LSBmaxGainError3±1.
5LSBmaxTotalUnadjustedError(TUE)3±2.
5LSBmaxANALOGINPUTInputVoltageRange0toVREFVDCLeakageCurrent±1μAmax40°Cto+85°C±5.
5μAmax85°Cto125°CInputCapacitance42pFtypWhenintrack10pFtypWheninholdREFERENCEINPUTVREFInputVoltageRange1.
4toVDDVmin/VmaxDCleakageCurrent±1μAmaxInputCapacitance20pFtypInputImpedance32ΩtypLOGICINPUTSInputHighVoltage,VINH1.
7Vmin2.
35V≤VDD≤2.
7V2Vmin2.
7V6VInputLowVoltage,VIN0.
7Vmax2.
35V≤VDD<2.
7V0.
8Vmax2.
7V≤VDD≤3.
6VInputCurrent,IIN±1μAmaxTypically10nA,VIN=0VorVDDInputCapacitance,CIN42pFmaxLOGICOUTPUTSOutputHighVoltage,VOHVDD0.
2VminISOURCE=200μA;VDD=2.
35Vto3.
6VOutputLowVoltage,VOL0.
2VmaxISINK=200μAFloating-StateLeakageCurrent±2.
5μAmaxFloating-StateOutputCapacitance44.
5pFmaxOutputCodingStraight(natural)binaryCONVERSIONRATEConversionTime250nsmax12SCLKcycleswithSCLKat48MHzTrack-and-HoldAcquisitionTime360nsmaxThroughputRate3.
45MSPSmaxSeetheSerialInterfacesectionAD7273/AD7274Rev.
0|Page6of28ParameterBGrade1Unit2TestConditions/CommentsPOWERRQUIREMENTSVDD2.
35/3.
6Vmin/VmaxIDDDigitalI/Ps=0VorVDDNormalMode(Static)0.
6mAtypVDD=3V,SCLKonoroffNormalMode(Operational)5mAmaxVDD=2.
35Vto3.
6V,fSAMPLE=3MSPS3.
2mAtypVDD=3VPartialPower-DownMode(Static)34μAtypFullPower-DownMode(Static)2μAmax40°Cto+85°C,typically0.
1μA10μAmax85°Cto125°CPowerDissipation5NormalMode(Operational)18mWmaxVDD=3.
6V,fSAMPLE=3MSPS9.
6mWtypVDD=3VPartialPower-Down102μWmaxVDD=3VFullPower-Down7.
2μWmaxVDD=3.
6V,40°Cto+85°C1Temperaturerangefrom40°Cto+125°C.
2TypicalspecificationsaretestedwithVDD=3VandVREF=3Vat25°C.
3SeetheTerminologysection.
4Guaranteedbycharacterization.
5SeethePowervs.
ThroughputRatesection.
AD7273/AD7274Rev.
0|Page7of28TIMINGSPECIFICATIONSVDD=2.
35Vto3.
6V;VREF=2.
35toVDD;TA=TMINtoTMAX,unlessotherwisenoted.
1Guaranteedbycharacterization.
Allinputsignalsarespecifiedwithtr=tf=2ns(10%to90%ofVDD)andtimedfromavoltagelevelof1.
6V.
Table4.
ParameterLimitatTMIN,TMAXAD7273/AD7274UnitDescriptionfSCLK2500kHzmin348MHzmaxtCONVERT14*tSCLKAD727412*tSCLKAD7273tQUIET4nsminMinimumquiettimerequiredbetweenbusrelinquishandstartofnextconversiont13nsminMinimumCSpulsewidtht26nsminCStoSCLKsetuptimet344nsmaxDelayfromCSuntilSDATAthree-statedisabledt4415nsmaxDataaccesstimeafterSCLKfallingedget50.
4tSCLKnsminSCLKlowpulsewidtht60.
4tSCLKnsminSCLKhighpulsewidtht745nsminSCLKtodatavalidholdtimet814nsmaxSCLKfallingedgetoSDATAthree-state5nsminSCLKfallingedgetoSDATAthree-statet94.
2nsmaxCSrisingedgetoSDATAthree-statetPOWER-UP51μsmaxPower-uptimefromfullpower-down1Sampletestedduringinitialreleasetoensurecompliance.
Alltimingspecificationsgivenarewitha10pFloadcapacitance.
Withaloadcapacitancegreaterthanthisvalue,adigitalbufferorlatchmustbeused.
2Mark/spaceratiofortheSCLKinputis40/60to60/40.
3MinimumfSCLKatwhichspecificationsareguaranteed.
4ThetimerequiredfortheoutputtocrosstheVIHorVILvoltage.
5SeethePower-UpTimessectionSCLKVIHVILSDATAt404973-002Figure2.
AccessTimeAfterSCLKFallingEdgeSCLKVIHVILSDATAt704973-003Figure3.
HoldTimeAfterSCLKFallingEdgeSCLK1.
4VSDATAt804973-004Figure4.
SCLKFallingEdgeSDATAThree-StateAD7273/AD7274Rev.
0|Page8of28TIMINGEXAMPLESFortheAD7274,ifCSisbroughthighduringthe14thSCLKrisingedgeafterthetwoleadingzerosand12bitsoftheconversionareprovided,thepartcanachievethefastestthroughputrate,3MSPS.
IfCSisbroughthighduringthe16thSCLKrisingedgeafterthetwoleadingzeros,12bitsoftheconversion,andtwotrailingzerosareprovided,athroughputrateof2.
97MSPSisachievable.
Thisisillustratedinthefollowingtwotimingexamples.
TimingExample1InFigure6,usinga14SCLKcycle,fSCLK=48MHz,andthethroughputis3MSPS.
Thisproducesacycletimeoft2+12.
5(1/fSCLK)+tACQ=333ns,wheret2=6nsminandtACQ=67ns.
Thissatisfiestherequirementof60nsfortACQ.
Figure6alsoshowsthattACQcomprises0.
5(1/fSCLK)+t9+tQUIET,wheret9=4.
2nsmax.
Thisallowsavalueof52.
8nsfortQUIET,satisfyingtheminimumrequirementof4ns.
TimingExample2TheexampleinFigure7usesa16SCLKcycle,fSCLK=48MHz,andthethroughputis2.
97MSPS.
Thisproducesacycletimeoft2+12.
5(1/fSCLK)+tACQ=336ns,wheret2=6nsminandtACQ=70ns.
Figure7showsthattACQcomprises2.
5(1/fSCLK)+t8+tQUIET,wheret8=14nsmax.
Thissatisfiestheminimumrequirementof4nsfortQUIET.
1234513141516SCLKSDATATHREE-STATETHREE-STATETWOLEADINGZEROSTWOTRAILINGZEROSBCSt3tCONVERTt2ZEROZDB11DB10DB9DB1DB0ZEROZEROt6t5t8t1tQUIET1/THROUGHPUTt4t704973-005Figure5.
AD7274SerialInterfaceTiming16SCLKCycle123451314SCLKSDATATHREE-STATETHREE-STATETWOLEADINGZEROSBCSt3tCONVERTt2ZEROZDB11DB10DB9DB1DB0t6t9t1tQUIET1/THROUGHPUTt4t704973-006t5Figure6.
AD7274SerialInterfaceTiming14SCLKCycle123451312141516SCLKBCStCONVERTt2t8t1tQUIET1/THROUGHPUT12.
5(1/fSCLK)tACQUISITION04973-007Figure7.
SerialInterfaceTiming16SCLKCycleAD7273/AD7274Rev.
0|Page9of28ABSOLUTEMAXIMUMRATINGSTA=25°C,unlessotherwisenoted.
Table5.
ParametersRatingsVDDtoAGND/DGND0.
3Vto+6VAnalogInputVoltagetoAGND0.
3VtoVDD+0.
3VDigitalInputVoltagetoDGND0.
3Vto+6VDigitalOutputVoltagetoDGND0.
3VtoVDD+0.
3VInputCurrenttoAnyPinExceptSupplies1±10mAOperatingTemperatureRangeCommercial(BGrade)40°Cto+125°CStorageTemperatureRange65°Cto+150°CJunctionTemperature150°C6-LeadTSOTPackageθJAThermalImpedance230°C/WθJCThermalImpedance92°C/W8-LeadMSOPPackageθJAThermalImpedance205.
9°C/WθJCThermalImpedance43.
74°C/WLeadTemperatureSolderingReflow(10to30sec)255°CLeadTemperatureSolderingReflow(10to30sec)260°CESD1.
5kV1Transientcurrentsofupto100mAcauseSCRlatch-up.
StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thisisastressratingonly;functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthisspecificationisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
ESDCAUTIONESD(electrostaticdischarge)sensitivedevice.
Electrostaticchargesashighas4000Vreadilyaccumulateonthehumanbodyandtestequipmentandcandischargewithoutdetection.
AlthoughthisproductfeaturesproprietaryESDprotectioncircuitry,permanentdamagemayoccurondevicessubjectedtohighenergyelectrostaticdischarges.
Therefore,properESDprecautionsarerecommendedtoavoidperformancedegradationorlossoffunctionality.
AD7273/AD7274Rev.
0|Page10of28PINCONFIGURATIONSANDFUNCTIONDESCRIPTIONSVDD1SDATA2CS3AGND4VIN8DGND7SCLK6VREF5AD7273/AD7274TOPVIEW(NottoScale)04973-008Figure8.
8-LeadMSOPPinConfigurationVDDVIN1SDATA2348765DGNDAGNDCSSCLKVREFAD7273/AD7274TOPVIEW(NottoScale)04973-009Figure9.
8-LeadTSOTPinConfigurationTable6.
PinFunctionDescriptionsPinNo.
MSOPTSOTMnemonicDescription11VDDPowerSupplyInput.
TheVDDrangefortheAD7273/AD7274isfrom2.
35Vto3.
6V.
22SDATADataOut.
Logicoutput.
TheconversionresultfromtheAD7273/AD7274isprovidedonthisoutputasaserialdatastream.
ThebitsareclockedoutonthefallingedgeoftheSCLKinput.
ThedatastreamfromtheAD7274consistsoftwoleadingzerosfollowedbythe12bitsofconversiondataandtwotrailingzeros,providedMSBfirst.
ThedatastreamfromtheAD7273consistsoftwoleadingzerosfollowedbythe10bitsofconversiondataandfourtrailingzeros,providedMSBfirst.
37CSChipSelect.
Activelowlogicinput.
ThisinputprovidesthedualfunctionofinitiatingconversionontheAD7273/AD7274andframingtheserialdatatransfer.
48AGNDAnalogGround.
GroundreferencepointforallcircuitryontheAD7273/AD7274.
AllanalogsignalsandanyexternalreferencesignalshouldbereferredtothisAGNDvoltage.
55VREFVoltageReferenceInput.
Thispinbecomesthereferencevoltageinput.
Anexternalreferenceshouldbeappliedatthispin.
Theexternalreferenceinputrangeis1.
4VtoVDD.
A10μFcapacitorshouldbetiedbetweenthispinandAGND.
66SCLKSerialClock.
Logicinput.
SCLKprovidestheserialclockforaccessingdatafromthepart.
ThisclockinputisalsousedastheclocksourcefortheconversionprocessofAD7273/AD7274.
73DGNDDigitalGround.
GroundreferencepointforalldigitalcircuitryontheAD7273/AD7274.
TheDGNDandAGNDvoltagesideallyshouldbeatthesamepotentialandmustnotbemorethan0.
3Vapart,evenonatransientbasis.
84VINAnalogInput.
Single-endedanaloginputchannel.
Theinputrangeis0toVREF.
AD7273/AD7274Rev.
0|Page11of28TYPICALPERFORMANCECHARACTERISTICS–20–40–60–80–100–1200150014001300120011001000900800700600500400300200FREQUENCY(kHz)SNR(dB)10016384POINTFFTFSAMPLE=3MSPSFIN=1MHzSINAD=71.
05THD=–80.
9SFDR=–82.
204973-010Figure10.
AD7274DynamicPerformanceat3MSPS,InputTone=1MHz–20–40–60–80–100–1200150014001300120011001000900800700600500400300200FREQUENCY(kHz)SNR(dB)10016384POINTFFTFSAMPLE=3MSPSFIN=1MHzSINAD=66.
56THD=–77.
4SFDR=–78.
204973-011Figure11.
AD7273DynamicPerformanceat3MSP,InputTone=1MHz72.
272.
071.
070.
870.
670.
471.
270.
270.
069.
869.
669.
469.
271.
471.
671.
869.
010015001000INPUTFREQUENCY(kHz)SINAD(dB)VDD=3VVDD=3.
6VFSAMPLE=3MSPS04973-012VDD=2.
5VFigure12.
AD7274SINADvs.
AnalogInputFrequencyat3MSPSforVariousSupplyVoltages,SCLKFrequency=48MHz72.
272.
071.
871.
671.
471.
271.
070.
870.
670.
470.
210015001000INPUTFREQUENCY(kHz)SNR(dB)VDD=3VVDD=2.
5VVDD=3.
6VFSAMPLE=3MSPS04973-013Figure13.
AD7274SNRvs.
AnalogInputFrequencyat3MSPSforVariousSupplyVoltages,SCLKFrequency=48MHz–72–74–76–78–80–82–84–86–88–9010015001000INPUTFREQUENCY(kHz)THD(dB)VDD=2.
5VVDD=3VVDD=3.
6V04973-014Figure14.
THDvs.
AnalogInputFrequencyat3MSPSforVariousSupplyVoltages,SCLKFrequency=48MHz–40–50–60–70–80–9010015001000INPUTFREQUENCY(kHz)THD(dB)RIN=100ΩRIN=0ΩRIN=10Ω04973-015Figure15.
THDvs.
AnalogInputFrequencyat3MSPSforVariousSourceImpedance,SCLKFrequency=48MHz,SupplyVoltage=3VAD7273/AD7274Rev.
0|Page12of28–70–11003000SUPPLYRIPPLEFREQUENCY(MHz)PSRR(dB)–80–90–1005001000150020002500100mVp-pSINEWAVEONAVDDNODECOUPLING04973-016Figure16.
PowerSupplyRejectionRatio(PSRR)vs.
SupplyRippleFrequencyWithoutDecoupling1.
00.
80.
60.
40.
20–0.
2–0.
4–0.
6–0.
8–1.
004000350030002500200015001000500CODESINLERROR(LSB)VDD=3V04973-017Figure17.
AD7274INLPerformance1.
00.
80.
60.
40.
20–0.
2–0.
4–0.
6–0.
8–1.
004000350030002500200015001000500CODESDNLERROR(LSB)VDD=3V04973-018Figure18.
AD7274DNLPerformance1.
0–1.
01.
43.
6REFERENCEVOLTAGE(V)INLERROR(LSB)04973-0190.
80.
60.
40.
20–0.
2–0.
4–0.
6–0.
81.
61.
82.
02.
22.
42.
62.
83.
03.
23.
4POSITIVEINLNEGATIVEINLFigure19.
ChangeinINLvs.
ReferenceVoltage,3VSupply1.
0–1.
01.
43.
6REFERENCEVOLTAGE(V)DNLERROR(LSB)04973-0200.
80.
60.
40.
20–0.
2–0.
4–0.
6–0.
81.
61.
82.
02.
22.
42.
62.
83.
03.
23.
4POSITIVEDNLNEGATIVEDNLFigure20.
ChangeinDNLvs.
ReferenceVoltage,3VSupply3.
603.
403.
203.
002.
802.
602.
402.
202.
001.
801.
601.
401.
201.
000.
800.
6005040302010SCLKFREQUENCY(MHz)MAXCURRENT(mA)VDD=2.
5VVDD=3.
6VVDD=3V04973-021Figure21.
MaximumCurrentvs.
SupplyVoltageforDifferentSCLKFrequenciesAD7273/AD7274Rev.
0|Page13of281800002045CODENUMBEROFCODES1600014000120001000080006000400020002046204720482049205030,000CODES04973-022Figure22.
HistogramofCodesfor30,000Samples12.
010.
01.
43.
6VREF(V)EFFECTIVENUMBERSOFBITS04973-02311.
511.
010.
51.
61.
82.
02.
22.
42.
62.
83.
03.
23.
4Figure23.
ENOB/SINADvs.
ReferenceVoltageAD7273/AD7274Rev.
0|Page14of28TERMINOLOGYIntegralNonlinearity(INL)ThemaximumdeviationfromastraightlinepassingthroughtheendpointsoftheADCtransferfunction.
FortheAD7273/AD7274,theendpointsofthetransferfunctionarezeroscaleat0.
5LSBbelowthefirstcodetransitionandfullscaleat0.
5LSBabovethelastcodetransition.
DifferentialNonlinearity(DNL)Thedifferencebetweenthemeasuredandtheideal1LSBchangebetweenanytwoadjacentcodesintheADC.
OffsetErrorThedeviationofthefirstcodetransition(00.
.
.
000)to(00.
.
.
001)fromtheideal,thatis,AGND+0.
5LSB.
GainErrorThedeviationofthelastcodetransition(111.
.
.
110)to(111.
.
.
111)fromtheideal,thatis,VREF–1.
5LSB,afteradjustingfortheoffseterror.
TotalUnadjustedError(TUE)Acomprehensivespecificationthatincludesgain,linearity,andoffseterrors.
Track-and-HoldAcquisitionTimeThetimerequiredfortheoutputofthetrack-and-holdamplifiertoreachitsfinalvalue,within±0.
5LSB,aftertheendoftheconversion.
SeetheSerialInterfacesectionformoredetails.
Signal-to-Noise+DistortionRatio(SINAD)ThemeasuredratioofsignaltonoiseplusdistortionattheoutputoftheADC.
Thesignalisthermsamplitudeofthefundamental,andnoiseisthermssumofallnonfundamentalsignalsuptohalfthesamplingfrequency(fS/2),includingharmonicsbutexcludingdc.
Theratioisdependentonthenumberofquantizationlevelsinthedigitizationprocess:themorelevels,thesmallerthequantizationnoise.
ForanidealN-bitconverter,theSINADisdB76.
102.
6+=NSINADAccordingtothisequation,theSINADis74dBfora12-bitconverterand62dBfora10-bitconverter.
However,variouserrorsourcesintheADC,includingintegralanddifferentialnonlinearitiesandinternalacnoisesources,causethemeasuredSINADtobelessthanitstheoreticalvalue.
TotalHarmonicDistortion(THD)Theratioofthermssumofharmonicstothefundamental.
Itisdefinedas:()12625242322log20dBVVVVVVTHD++++=whereV1isthermsamplitudeofthefundamental,andV2,V3,V4,V5,andV6arethermsamplitudesofthesecondthroughthesixthharmonics.
PeakHarmonicorSpuriousNoise(SFDR)TheratioofthermsvalueofthenextlargestcomponentintheADCoutputspectrum(uptof/2,excludingdc)tothermsvalueofthefundamental.
Normally,thevalueofthisspecificationisdeterminedbythelargestharmonicinthespectrum;however,forADCswithharmonicsburiedinthenoisefloor,itisdeter-minedbyanoisepeak.
SIntermodulationDistortion(IMD)Withinputsconsistingofsinewavesattwofrequencies,faandfb,anyactivedevicewithnonlinearitiescreatesdistortionproductsatsumanddifferencefrequenciesofmfa±nfb,wheremandn=0,1,2,3,….
Intermodulationdistortiontermsarethoseforwhichneithermnornareequaltozero.
Forexample,thesecond-ordertermsinclude(fa+fb)and(fafb),andthethird-ordertermsinclude(2fa+fb),(2fafb),(fa+2fb),and(fa2fb).
TheAD7273/AD7274aretestedusingtheCCIFstandardinwhichtwoinputfrequenciesareused(seefaandfbintheSpecificationssection).
Inthiscase,thesecond-ordertermsareusuallydistancedinfrequencyfromtheoriginalsinewaves,andthethird-ordertermsareusuallyatafrequencyclosetotheinputfrequencies.
Asaresult,thesecond-andthird-ordertermsarespecifiedseparately.
ThecalculationoftheintermodulationdistortionisaspertheTHDspecification,whereitistheratioofthermssumoftheindividualdistortionproductstothermsamplitudeofthesumofthefundamentalsexpressedindecibels.
PowerSupplyRejectionRatio(PSRR)TheratioofthepowerintheADCoutputatfull-scalefrequency,f,tothepowerofa100mVp-psinewaveappliedtotheADCVsupplyoffrequencyf.
DDS()()SPfPfPSRRlog10dB=wherePfisthepoweratfrequencyfintheADCoutput;PfSisthepoweratfrequencyfScoupledontotheADCVDDsupply.
ApertureDelayThemeasuredintervalbetweentheleadingedgeofthesamplingclockandthepointatwhichtheADCactuallytakesthesample.
ApertureJitterThesample-to-samplevariationintheeffectivepointintimeatwhichthesampleistaken.
AD7273/AD7274Rev.
0|Page15of28CIRCUITINFORMATIONTheAD7273/AD7274arehighspeed,lowpower,10-/12-bit,singlesupplyADCs,respectively.
Thepartscanbeoperatedfroma2.
35Vto3.
6Vsupply.
Whenoperatedfromanysupplyvoltagewithinthisrange,theAD7273/AD7274arecapableofthroughputratesof3MSPSwhenprovidedwitha48MHzclock.
TheAD7273/AD7274providetheuserwithanon-chiptrack-and-holdADCandaserialinterfacehousedinan8-leadTSOToran8-leadMSOPpackage,whichofferstheuserconsiderablespace-savingadvantagesoveralternativesolutions.
TheserialclockinputaccessesdatafromthepartandprovidestheclocksourceforthesuccessiveapproximationADC.
Theanaloginputrangeis0toVREF.
Anexternalreferenceintherangeof1.
4VtoVDDisrequiredbytheADC.
TheAD7273/AD7274alsofeatureapower-downoptiontosavepowerbetweenconversions.
Thepower-downfeatureisimplementedacrossthestandardserialinterfaceasdescribedintheModesofOperationsection.
CONVERTEROPERATIONTheAD7273/AD7274aresuccessiveapproximationADCsbasedonachargeredistributionDAC.
Figure24andFigure25showsimplifiedschematicsoftheADC.
Figure24showstheADCduringitsacquisitionphase,whereSW2isclosed,SW1isinPositionA,thecomparatorisheldinabalancedcondition,andthesamplingcapacitoracquiresthesignalonVIN.
COMPARATORACQUISITIONPHASEVDD/2SW2VINSAMPLINGCAPACITORAGNDASW1BCHARGEREDISTRIBUTIONDACCONTROLLOGIC04973-024Figure24.
ADCAcquisitionPhaseWhentheADCstartsaconversion,SW2opensandSW1movestoPositionB,causingthecomparatortobecomeunbalanced(seeFigure25).
ThecontrollogicandthechargeredistributionDACareusedtoaddandsubtractfixedamountsofchargefromthesamplingcapacitortobringthecomparatorbackintoabalancedcondition.
Whenthecomparatorisrebalanced,theconversioniscomplete.
ThecontrollogicgeneratestheADCoutputcode.
Figure26showstheADCtransferfunction.
COMPARATORACQUISITIONPHASEVDD/2SW2VINSAMPLINGCAPACITORAGNDASW1BCHARGEREDISTRIBUTIONDACCONTROLLOGIC04973-025Figure25.
ADCConversionPhaseADCTRANSFERFUNCTIONTheoutputcodingoftheAD7273/AD7274isstraightbinary.
ThedesignedcodetransitionsoccurmidwaybetweensuccessiveintegerLSBvalues,suchas0.
5LSBand1.
5LSB.
TheLSBsizeisVREF/4,096fortheAD7274andVREF/1,024fortheAD7273.
TheidealtransfercharacteristicfortheAD7273/AD7274isshowninFigure26.
000.
.
.
0000VADCCODEANALOGINPUT111.
.
.
111000.
.
.
001111.
.
.
000011.
.
.
111111.
.
.
110000.
.
.
0101LSB=VREF/4096(AD7274)1LSB=VREF/1024(AD7273)+VREF–1.
5LSB0.
5LSB04973-026Figure26.
AD7273/AD7274TransferCharacteristicAD7273/AD7274Rev.
0|Page16of28TYPICALCONNECTIONDIAGRAMFigure27showsatypicalconnectiondiagramfortheAD7273/AD7274.
AnexternalreferencemustbeappliedtotheADC.
Thisreferencecanbeintherangeof1.
4VtoVDD.
Aprecisionreference,suchastheREF19xfamilyortheADR421,canbeusedtosupplythereferencevoltagetotheAD7273/AD7274.
Theconversionresultisoutputina16-bitwordwithtwoleadingzerosfollowedbythe12-bitor10-bitresult.
The12-bitresultfromtheAD7274isfollowedbytwotrailingzeros,andthe10-bitresultfromtheAD7273isfollowedbyfourtrailingzeros.
Table7providessometypicalperformancedatawithvariousreferencesunderthesamesetupconditionsfortheAD7274.
Table7.
AD7274Performance(VariousVoltageReferenceIC)VoltageReferenceAD7274SNRPerformance1MHzInputAD780@2.
5V71.
3dBAD780@3V70.
1dBREF19570.
9dBAD7273/AD7274VDDVINSERIALINTERFACE0VTOVREFINPUTDSP/μC/μPVREFAGND/DGNDSCLKCSSDATA0.
1μF10μF10pF0.
1μF2.
5V3.
6VSUPPLY4.
6mAREF19504973-027Figure27.
AD7273/AD7274TypicalConnectionDiagramANALOGINPUTFigure28showsanequivalentcircuitoftheanaloginputstructureoftheAD7273/AD7274.
Thetwodiodes,D1andD2,provideESDprotectionfortheanaloginputs.
Caremustbetakentoensurethattheanaloginputsignalneverexceedsthesupplyrailsbymorethan300mV.
Signalsexceedingthisvaluecausethesediodestobecomeforwardbiasedandtostartconductingcurrentintothesubstrate.
Thesediodescanconductamaximumcurrentof10mAwithoutcausingirreversibledamagetothepart.
CapacitorC1inFigure28istypicallyabout4pFandcanprimarilybeattributedtopincapacitance.
ResistorR1isalumpedcomponentmadeupoftheonresistanceofaswitch.
Thisresistoristypicallyabout75Ω.
CapacitorC2istheADCsamplingcapacitorandhasacapacitanceof32pFtypically.
Foracapplications,removinghighfrequencycomponentsfromtheanaloginputsignalisrecommendedbyusingaband-passfilterontherelevantanaloginputpin.
Inapplicationswhereharmonicdistortionandsignal-to-noiseratioarecritical,theanaloginputshouldbedrivenfromalowimpedancesource.
LargesourceimpedancessignificantlyaffecttheacperformanceoftheADCs.
Thismaynecessitatetheuseofaninputbufferamplifier.
TheAD8021opampiscompatiblewiththisdevice;however,thechoiceoftheopampisafunctionoftheparticularapplication.
C14pFC2R1CONVERSIONPHASE–SWITCHOPENTRACKPHASE–SWITCHCLOSEDD1D2VDDVIN04973-028Figure28.
EquivalentAnalogInputCircuitWhennoamplifierisusedtodrivetheanaloginput,thesourceimpedanceshouldbelimitedtoalowvalue.
ThemaximumsourceimpedancedependsontheamountofTHDthatcanbetolerated.
TheTHDincreasesasthesourceimpedanceincreasesandperfor-mancedegrades.
Figure14showsagraphoftheTHDvs.
theanaloginputfrequencyfordifferentsourceimpedanceswhenusingasupplyvoltageof3Vandsamplingatarateof3MSPS.
DIGITALINPUTSThedigitalinputsappliedtotheAD7273/AD7274arenotlimitedbythemaximumratingsthatlimittheanaloginputs.
Instead,thedigitalinputscanbeappliedatupto6VandarenotrestrictedbytheVDD+0.
3Vlimitoftheanaloginputs.
Forexample,iftheAD7273/AD7274wereoperatedwithaVDDof3V,then5Vlogiclevelscouldbeusedonthedigitalinputs.
However,itisimportanttonotethatthedataoutputonSDATAstillhas3VlogiclevelswhenVDD=3V.
AnotheradvantageofSCLKandCSnotbeingrestrictedbytheVDD+0.
3Vlimitisthatpowersupplysequencingissuesareavoided.
Forexample,unlikewiththeanaloginputs,withthedigitalinputs,ifCSorSCLKareappliedbeforeVDD,thereisnoriskoflatch-up.
AD7273/AD7274Rev.
0|Page17of28MODESOFOPERATIONThemodeofoperationoftheAD7273/AD7274isselectedbycontrollingthelogicstateoftheCSsignalduringaconversion.
Therearethreepossiblemodesofoperation:normalmode,partialpower-downmode,andfullpower-downmode.
ThepointatwhichCSispulledhighaftertheconversionisinitiateddetermineswhichpower-downmode,ifany,thedeviceenters.
Similarly,ifthedeviceisalreadyinpower-downmode,CScancontrolwhetherthedevicereturnstonormaloperationorremainsinpower-downmode.
Thesemodesofoperationaredesignedtoprovideflexiblepowermanagementoptions,whichcanbechosentooptimizethepowerdissipation/throughputrateratiofordifferentapplicationrequirements.
NORMALMODEThismodeisintendedforfastestthroughputrateperformancebecausetheAD7273/AD7274remainfullypoweredatalltimes,eliminatingworryaboutpower-uptimes.
Figure29showsthegeneraldiagramoftheoperationoftheAD7273/AD7274inthismode.
TheconversionisinitiatedonthefallingedgeofCSasdescribedintheSerialInterfacesection.
Toensurethatthepartremainsfullypoweredupatalltimes,CSmustremainlowuntilatleast10SCLKfallingedgeselapseafterthefallingedgeofCS.
IfCSisbroughthighanytimeafterthe10thSCLKfalling,butbeforethe16thSCLKfallingedge,thepartremainspoweredup,buttheconversionisterminated,andSDATAgoesbackintothree-state.
FortheAD7274,aminimumof14serialclockcyclesarerequiredtocompletetheconversionandaccessthecompleteconversionresult.
FortheAD7273,aminimumof12serialclockcyclesarerequiredtocompletetheconversionandaccessthecompleteconversionresult.
CScanidlehighuntilthenextconversionorlowuntilCSreturnshighbeforethenextconversion(effectivelyidlingCSlow).
Onceadatatransferiscomplete(SDATAhasreturnedtothree-state),anotherconversioncanbeinitiatedafterthequiettime,tQUIET,haselapsedbybringingCSlowagain.
PARTIALPOWER-DOWNMODEThismodeisintendedforuseinapplicationswhereslowerthroughputratesarerequired.
AnexampleofthisiswheneithertheADCispowereddownbetweeneachconversionoraseriesofconversionsisperformedatahighthroughputrateandthentheADCispowereddownforarelativelylongdurationbetweentheseburstsofseveralconversions.
WhentheAD7273/AD7274areinpartialpower-downmode,allanalogcircuitryispowereddownexceptthebiasgenerationcircuit.
Toenterpartialpower-downmode,interrupttheconversionprocessbybringingCShighbetweenthesecondand10thfallingedgesofSCLK,asshowninFigure30.
OnceCSisbroughthighinthiswindowofSCLKs,thepartenterspartialpower-downmode,theconversionthatwasinitiatedbythefallingedgeofCSisterminated,andSDATAgoesbackintothree-state.
IfCSisbroughthighbeforethesecondSCLKfallingedge,thepartremainsinnormalmodeanddoesnotpowerdown.
Thispreventsaccidentalpower-downduetoglitchesontheCSline.
ToexitthismodeofoperationandpoweruptheAD7274/AD7273,performadummyconversion.
OnthefallingedgeofCS,thedevicebeginstopowerupandcontinuestopowerupaslongasCSisheldlowuntilafterthefallingedgeofthe10thSCLK.
Thedeviceisfullypowereduponce16SCLKselapse;validdataresultsfromthenextconversion,asshowninFigure31.
IfCSisbroughthighbeforethe10thfallingedgeofSCLK,theAD7274/AD7273goesintofullpower-downmode.
Therefore,althoughthedevicemaybegintopoweruponthefallingedgeofCS,itpowersdownontherisingedgeofCSaslongasthisoccursbeforethe10thSCLKfallingedge.
IftheAD7273/AD7274isalreadyinpartialpower-downmodeandCSisbroughthighbeforethe10thfallingedgesofSCLK,thedeviceentersfullpower-downmode.
Formoreinformationonthepower-uptimesassociatedwithpartialpower-downmodeinvariousconfigurations,seethePower-UpTimessection.
FULLPOWER-DOWNMODEThismodeisintendedforuseinapplicationswherethroughputratesslowerthanthoseinthepartialpower-downmodearerequired,becausepower-upfromafullpower-downtakessubstantiallylongerthanthatfromapartialpower-down.
Thismodeissuitedtoapplicationswhereaseriesofconversionsperformedatarelativelyhighthroughputratearefollowedbyalongperiodofinactivityandthuspower-down.
WhentheAD7273/AD7274areinfullpower-downmode,allanalogcircuitryispowereddown.
Toenterfullpower-downmodeputthedeviceintopartialpower-downmodebybringingCShighbetweenthesecondand10thfallingedgesofSCLK.
Inthenextconversioncycle,interrupttheconversionprocessinthewayshowninFigure32bybringingCShighbeforethe10thSCLKfallingedge.
OnceCSisbroughthighinthiswindowofSCLKs,thepartpowersdowncompletely.
Notethatitisnotnecessarytocomplete16SCLKsonceCSisbroughthightoentereitherofthepower-downmodes.
Glitchprotectionisnotavailablewhenenteringfullpower-downmode.
Toexitfullpower-downmodeandpoweruptheAD7273/AD7274again,performadummyconversion,similartowhenpoweringupfrompartialpower-downmode.
OnthefallingAD7273/AD7274Rev.
0|Page18of28edgeofCS,thedevicebeginstopowerupandcontinuestopowerupuntilafterthefallingedgeofthe10thSCLKaslongasCSisheldlow.
Thepower-uptimerequiredmustelapsebeforeaconversioncanbeinitiated,asshowninFigure33.
SeethePower-UpTimessectionforthepower-uptimesassociatedwiththeAD7273/AD7274.
POWER-UPTIMESTheAD7273/AD7274hastwopower-downmodes,partialpower-downandfullpower-down,whicharedescribedindetailintheModesofOperationsection.
Thissectiondealswiththepower-uptimerequiredwhencomingoutofeitherofthesemodes.
Topowerupfrompartialpower-downmode,onecycleisrequired.
Therefore,withaSCLKfrequencyofupto48MHz,onedummycycleissufficienttoallowthedevicetopowerupfrompartialpower-downmode.
Oncethedummycycleiscomplete,theADCisfullypoweredupandtheinputsignalisacquiredproperly.
Thequiettime,tQUIET,mustbeallowedfromthepointwherethebusgoesbackintothree-stateafterthedummyconversiontothenextfallingedgeofCS.
Topowerupfromfullpower-down,approximately1μsshouldbeallowedfromthefallingedgeofCS,showninFigure33astPOWER-UP.
Notethatduringpower-upfrompartialpower-downmode,thetrack-and-hold,whichisinholdmodewhilethepartispowereddown,returnstotrackmodeafterthefirstSCLKedgeisreceivedafterthefallingedgeofCS.
ThisisshownasPointAinFigure31.
WhenpowersuppliesarefirstappliedtotheAD7273/AD7274,theADCcanpowerupineitherofthepower-downmodesorinnormalmode.
Becauseofthis,itisbesttoallowadummycycletoelapsetoensurethatthepartisfullypoweredupbeforeattemptingavalidconversion.
Likewise,ifthepartistobekeptinpartialpower-downmodeimmediatelyafterthesuppliesareapplied,twodummycyclesmustbeinitiated.
ThefirstdummycyclemustholdCSlowuntilafterthe10thSCLKfallingedge(seeFigure29).
Inthesecondcycle,CSmustbebroughthighbetweenthesecondand10thSCLKfallingedges(seeFigure30).
Alternatively,ifthepartistobeplacedintofullpower-downmodeafterthesuppliesareapplied,threedummycyclesmustbeinitiated.
ThefirstdummycyclemustholdCSlowuntilafterthe10thSCLKfallingedge(seeFigure29);thesecondandthirddummycyclesplacethepartintofullpower-downmode(seeFigure32).
SeealsotheModesofOperationsection.
CSSCLK110121416AD7273/AD7674SDATAVALIDDATA04973-029Figure29.
NormalModeOperationAD7273/AD7274Rev.
0|Page19of28SCLK121016SDATATHREE-STATECS04973-030Figure30.
EnteringPartialPower-DownModeTHEPARTBEGINSTOPOWERUPTHEPARTISFULLYPOWEREDUP,SEEPOWER-UPTIMESSECTIONCSSDATAINVALIDDATAVALIDDATA1A1016116SCLK04973-031Figure31.
ExitingPartialPower-DownModeTHEPARTENTERSPARTIALPOWERDOWNTHEPARTENTERSFULLPOWERDOWNCSSDATAINVALIDDATAVALIDDATATHEPARTBEGINSTOPOWERUP12101611610SCLKTHREE-STATETHREE-STATE04973-032Figure32.
EnteringFullPower-DownModeTHEPARTBEGINSTOPOWERUPtPOWER-UPCSSDATAINVALIDDATAVALIDDATATHEPARTISFULLYPOWEREDUP1101611SCLK604973-033Figure33.
ExitingFullPower-DownModeAD7273/AD7274Rev.
0|Page20of28POWERVS.
THROUGHPUTRATEFigure34showsthepowerconsumptionofthedeviceinnormalmode,inwhichthepartisneverpowereddown.
Byusingthepower-downmodeoftheAD7273/AD7274whennotperformingaconversion,theaveragepowerconsumptionoftheADCdecreasesasthethroughputratedecreases.
Figure35showsthatasthethroughputrateisreduced,thedeviceremainsinitspower-downstatelongerandtheaveragepowerconsumptionovertimedropsaccordingly.
Forexample,iftheAD7273/AD7274areoperatedincontinuoussamplingmodewithathroughputrateof200kSPSandaSCLKof48MHz(VDD=3V)andthedevicesareplacedintopower-downmodebetweenconversions,thepowerconsumptioniscalculatedasfollows.
Thepowerdissipationduringnormaloperationis11.
6mW(VDD=3V).
Ifthepower-uptimeisonedummycycle,thatis,333ns,andtheremainingconversiontimeis290ns,theAD7273/AD7274canbesaidtodissipate11.
6mWfor623nsduringeachconversioncycle.
Ifthethroughputrateis200kSPS,thecycletimeis5μsandtheaveragepowerdissipatedduringeachcycleis623/5,000*9.
6mW=1.
42mW.
Figure35showsthepowervs.
throughputratewhenusingthepartialpower-downmodebetweenconversionsat3V.
Thepower-downmodeisintendedforusewiththroughputratesoflessthan600kSPS,becauseathighersamplingratesthereisnopowersavingachievedbyusingthepower-downmode.
04973-034THROUGHPUT(kSPS)POWER(mW)3.
403.
804.
204.
605.
005.
405.
806.
206.
607.
00200400600800100012001400160018002000VDD=3V48MHzSCLKVARIABLESCLKFigure34.
Powervs.
Throughput,NormalMode04973-035THROUGHPUT(kSPS)POWER(mW)00.
40.
81.
21.
62.
02.
42.
83.
23.
64.
04.
44.
85.
25.
66.
06.
46.
87.
202004006008001000VDD=3VFigure35.
Powervs.
Throughput,PartialPower-DownModeAD7273/AD7274Rev.
0|Page21of28SERIALINTERFACEFigure36throughFigure38showthedetailedtimingdiagramsforserialinterfacingtotheAD7274andAD7273,respectively.
TheserialclockprovidestheconversionclockandcontrolsthetransferofinformationfromtheAD7273/AD7274duringconversion.
TheCSsignalinitiatesthedatatransferandconversionprocess.
ThefallingedgeofCSputsthetrack-and-holdintoholdmodeandtakesthebusoutofthree-state.
Theanaloginputissampledandtheconversionisinitiatedatthispoint.
FortheAD7274,theconversionrequirescompleting14SCLKcycles.
Once13SCLKfallingedgeshaveelapsed,thetrack-and-holdgoesbackintotrackmodeonthenextSCLKrisingedge,asshowninFigure36atPointB.
IftherisingedgeofCSoccursbefore14SCLKshaveelapsed,theconversionisterminatedandtheSDATAlinegoesbackintothree-state.
If16SCLKsareconsideredinthecycle,thelasttwobitsarezerosandSDATAreturnstothree-stateonthe16thSCLKfallingedge,asshowninFigure37.
FortheAD7273,theconversionrequirescompleting12SCLKcycles.
Once11SCLKfallingedgeselapse,thetrack-and-holdgoesbackintotrackmodeonthenextSCLKrisingedge,asshowninFigure38atPointB.
IftherisingedgeofCSoccursbefore12SCLKselapse,theconversionisterminatedandtheSDATAlinegoesbackintothree-state.
If16SCLKsareconsideredinthecycle,theAD7273clocksoutfourtrailingzerosforthelastfourbitsandSDATAreturnstothree-stateonthe16thSCLKfallingedge,asshowninFigure38.
Iftheuserconsidersa14-SCLKcycleserialinterfacefortheAD7273/AD7274,CSmustbebroughthighafterthe14thSCLKfallingedge.
Thenthelasttwotrailingzerosareignored,andSDATAgoesbackintothree-state.
Inthiscase,the3MSPSthroughputcanbeachievedbyusinga48MHzclockfrequency.
CSgoinglowclocksoutthefirstleadingzerotobereadbythemicrocontrollerorDSP.
TheremainingdataisthenclockedoutbysubsequentSCLKfallingedges,beginningwiththesecondleadingzero.
Therefore,thefirstfallingclockedgeontheserialclockprovidesthefirstleadingzeroandclocksoutthesecondleadingzero.
Thefinalbitinthedatatransferisvalidonthe16thfallingedge,becauseitisclockedoutontheprevious(15th)fallingedge.
InapplicationswithaslowerSCLK,itispossibletoreaddataoneachSCLKrisingedge.
Insuchcases,thefirstfallingedgeofSCLKclocksoutthesecondleadingzeroandcanbereadonthefirstrisingedge.
However,thefirstleadingzeroclockedoutwhenCSgoeslowismissedifreadwithinthefirstfallingedge.
The15thfallingedgeofSCLKclocksoutthelastbitandcanbereadonthe15thrisingSCLKedge.
IfCSgoeslowjustafteroneSCLKfallingedgeelapses,CSclocksoutthefirstleadingzeroandcanbereadontheSCLKrisingedge.
ThenextSCLKfallingedgeclocksoutthesecondleadingzeroandcanbereadonthefollowingrisingedge.
tCONVERTTWOLEADINGZEROSt2CSSCLKSDATATHREE-STATETHREE-STATEB1/THROUGHPUT123451314ZERODB11DB10DB9DB1DB0Zt6t1tQUIETt9t5t7t4t304973-036Figure36.
AD7274SerialInterfaceTimingDiagram14SCLKCycleAD7273/AD7274Rev.
0|Page22of28tCONVERTCSSCLKSDATATWOLEADINGZEROSTHREE-STATETHREE-STATETWOTRAILINGZEROSB1/THROUGHPUT1234513151614DB11DB10DB9DB1DB0ZEROZEROZEROZt2t3t4t7t5t8tQUIETt1t604973-037Figure37.
AD7274SerialInterfaceTimingDiagram16SCLKCycletCONVERTSCLKB123410111214161513t2t3t4t7t8CSt1SDATATWOLEADINGZEROSTHREE-STATETHREE-STATEFOURTRAILINGZEROS1/THROUGHPUTDB9DB8DB0DB1ZEROZEROZEROZEROZEROZtQUIETt5t604973-038Figure38.
AD7273SerialInterfaceTimingDiagramAD7273/AD7274Rev.
0|Page23of28MICROPROCESSORINTERFACINGAD7273/AD7274toADSP-BF53xTheADSP-BF53xfamilyofDSPsinterfacesdirectlytotheAD7273/AD7274withoutrequiringgluelogic.
TheSPORT0ReceiveConfiguration1registershouldbesetupasoutlinedinTable8.
AD7273/AD72741ADSP-BF53x1SCLKRCLK0SPORT0DR0PRIRFS0DT0DOUTCSDIN1ADDITIONALPINSOMITTEDFORCLARITY04973-039Figure39.
InterfacingtotheADSP-BF53xTable8.
TheSPORT0ReceiveConfiguration1Register(SPORT0_RCR1)SettingDescriptionRCKFE=1SampledatawithfallingedgeofRSCLKLRFS=1ActivelowframesignalRFSR=1FrameeverywordIRFS=1InternalRFSusedRLSBIT=0ReceiveMSBfirstRDTYPE=00ZerofillIRCLK=1InternalreceiveclockRSPEN=1ReceiveenabledSLEN=111116-bitdata-word(orcanbesetto1101fora14-bitdata-word)TFSR=RFSR=1Toimplementthepower-downmodes,setSLENto1001toissuean8-bitSCLKburst.
AD7273/AD7274Rev.
0|Page24of28APPLICATIONHINTSGROUNDINGANDLAYOUTTheprintedcircuitboardthathousestheAD7273/AD7274shouldbedesignedsothattheanaloganddigitalsectionsareseparatedandconfinedtocertainareasoftheboard.
Thisdesignfacilitatesusinggroundplanesthatcanbeeasilyseparated.
Toprovideoptimumshieldingforgroundplanes,aminimumetchtechniqueisgenerallybest.
AllAGNDpinsoftheAD7273/AD7274shouldbesunkintotheAGNDplane.
Digitalandanaloggroundplanesshouldbejoinedinonlyoneplace.
IftheAD7273/AD7274areinasystemwheremultipledevicesrequireanAGND-to-DGNDconnection,theconnectionshouldbemadeatonlyonepoint,astargroundpoint,establishedascloseaspossibletothegroundpinontheAD7273/AD7274.
Avoidrunningdigitallinesunderthedevice,becausethiscouplesnoiseontothedie.
However,theanaloggroundplaneshouldbeallowedtorunundertheAD7273/AD7274toavoidnoisecoupling.
ThepowersupplylinestotheAD7273/AD7274shoulduseaslargeatraceaspossibletoprovidelowimpedancepathsandreducetheeffectsofglitchesonthepowersupplyline.
Toavoidradiatingnoisetoothersectionsoftheboard,componentswithfast-switchingsignals,suchasclocks,shouldbeshieldedwithdigitalground,andtheyshouldneverberunneartheanaloginputs.
Avoidcrossoverofdigitalandanalogsignals.
Toreducetheeffectsoffeedthroughwithintheboard,tracesonoppositesidesoftheboardshouldrunatrightanglestoeachother.
Amicrostriptechniqueisbyfarthebestmethod,butitisnotalwayspossibletousethisapproachwithadouble-sidedboard.
Inthistechnique,thecomponentsideoftheboardisdedicatedtogroundplanes,andsignalsareplacedonthesolderside.
Gooddecouplingisalsoimportant.
Allanalogsuppliesshouldbedecoupledwith10μFceramiccapacitorsinparallelwith0.
1μFcapacitorstoAGND/DGND.
Toachievethebestresultsfromthesedecouplingcomponents,theymustbeplacedascloseaspossibletothedevice,ideallyrightupagainstthedevice.
The0.
1μFcapacitorsshouldhaveloweffectiveseriesresistance(ESR)andloweffectiveseriesinductance(ESI),suchasistypicalofcommonceramicorsurface-mounttypesofcapacitors.
CapacitorswithlowESRandlowESIprovidealowimpedancepathtogroundathighfrequencies,whichallowsthemtohandletransientcurrentsduetointernallogicswitching.
EVALUATINGTHEAD7273/AD7274PERFORMANCETherecommendedlayoutfortheAD7273/AD7274isoutlinedintheevaluationboarddocumentation.
Theevaluationboardpackageincludesafullyassembledandtestedevaluationboard,documentation,andsoftwareforcontrollingtheboardfromaPCviatheevaluationboardcontroller.
TheevaluationboardcontrollercanbeusedinconjunctionwiththeAD7273/AD7274evaluationboard,aswellasmanyotherAnalogDevicesevaluationboardsendingintheCBdesignator,todemonstrate/evaluatetheacanddcperformanceoftheAD7273/AD7274.
Thesoftwareallowstheusertoperformac(fastFouriertrans-form)anddc(histogramofcodes)testsontheAD7273/AD7274.
ThesoftwareanddocumentationareonaCDshippedwiththeevaluationboard.
AD7273/AD7274Rev.
0|Page25of28OUTLINEDIMENSIONS135628472.
90BSCPIN1INDICATOR1.
60BSC1.
95BSC0.
65BSC0.
380.
220.
10MAX*0.
900.
870.
84SEATINGPLANE*1.
00MAX0.
200.
080.
600.
450.
308°4°0°2.
80BSC*COMPLIANTTOJEDECSTANDARDSMO-193-BAWITHTHEEXCEPTIONOFPACKAGEHEIGHTANDTHICKNESS.
Figure40.
8-LeadThinSmallOutlineTransistorPackage[TSOT](UJ-8)Dimensionsshowninmillimeters0.
800.
600.
408°0°48154.
90BSCPIN10.
65BSC3.
00BSCSEATINGPLANE0.
150.
000.
380.
221.
10MAX3.
00BSCCOPLANARITY0.
100.
230.
08COMPLIANTTOJEDECSTANDARDSMO-187-AAFigure41.
8-LeadMiniSmallOutlinePackage[MSOP](RM-8)DimensionsshowninmillimetersORDERINGGUIDEModelTemperatureRangeLinearityError(LSB)1PackageDescriptionPackageOptionBrandingAD7274BRM40°Cto+125°C±1max8-LeadMiniSmallOutlinePackage(MSOP)RM-8C1VAD7274BRMZ240°Cto+125°C±1max8-LeadMiniSmallOutlinePackage(MSOP)RM-8C34AD7274BRMZ-REEL240°Cto+125°C±1max8-LeadMiniSmallOutlinePackage(MSOP)RM-8C34AD7274BUJ-500RL740°Cto+125°C±1max8-LeadMiniSmallOutlinePackage(MSOP)UJ-8C1VAD7274BUJZ-500RL7240°Cto+125°C±1max8-LeadThinSmallOutlineTransistorPackage(TSOT)UJ-8C34AD7274BUJZ-REEL7240°Cto+125°C±1max8-LeadThinSmallOutlineTransistorPackage(TSOT)UJ-8C34AD7273BRMZ240°Cto+125°C±0.
5max8-LeadMiniSmallOutlinePackage(MSOP)RM-8C33AD7273BRMZ-REEL240°Cto+125°C±0.
5max8-LeadMiniSmallOutlinePackage(MSOP)RM-8C33AD7273BUJ-REEL740°Cto+125°C±0.
5max8-LeadThinSmallOutlineTransistorPackage(TSOT)UJ-8C1UAD7273BUJZ-500RL7240°Cto+125°C±0.
5max8-LeadThinSmallOutlineTransistorPackage(TSOT)UJ-8C33EVAL-AD7274CB3EvaluationBoardEVAL-AD7273CB3EvaluationBoardEVAL-CONTROLBRD24ControlBoard1Linearityerrorreferstointegralnonlinearity.
2Z=Pb-freepart.
3ThiscanbeusedasastandaloneevaluationboardorinconjunctionwiththeEVAL-CONTROLboardforevaluation/demonstrationpurposes.
4ThisboardisacompleteunitthatallowsaPCtocontrolandcommunicatewithallAnalogDevicesevaluationboardsthatendinaCBdesignator.
Toorderacompleteevaluationkit,theparticularADCevaluationboard(suchasEVAL-AD7273CB/AD7274CB),theEVAL-CONTROLBRD2,anda12Vtransformermustbeordered.
Seetherelevantevaluationboardtechnicalnoteformoreinformation.
AD7273/AD7274Rev.
0|Page26of28NOTESAD7273/AD7274Rev.
0|Page27of28NOTESAD7273/AD7274Rev.
0|Page28of28TNOTES2005AnalogDevices,Inc.
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