commandios5

IntegratedSiliconSolution,Inc.
1Rev.
A04/7/2015Copyright2015IntegratedSiliconSolution,Inc.
Allrightsreserved.
ISSIreservestherighttomakechangestothisspecificationanditsproductsatanytimewithoutnotice.
ISSIassumesnoliabilityarisingoutoftheapplicationoruseofanyinformation,productsorservicesdescribedherein.
Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonanypublishedinformationandbeforeplacingordersforproducts.
IntegratedSiliconSolution,Inc.
doesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailureormalfunctionoftheproductcanreason-ablybeexpectedtocausefailureofthelifesupportsystemortosignificantlyaffectitssafetyoreffectiveness.
ProductsarenotauthorizedforuseinsuchapplicationsunlessIntegratedSiliconSolution,Inc.
receiveswrittenassurancetoitssatisfaction,that:a.
)theriskofinjuryordamagehasbeenminimized;b.
)theuserassumeallsuchrisks;andc.
)potentialliabilityofIntegratedSiliconSolution,IncisadequatelyprotectedunderthecircumstancesIS43R83200FIS43/46R16160F,IS43/46R32800FFEATURESVDDandVDDQ:2.
5V±0.
2VSSTL_2compatibleI/ODouble-dataratearchitecture;twodatatransfersperclockcycleBidirectional,datastrobe(DQS)istransmitted/receivedwithdata,tobeusedincapturingdataatthereceiverDQSisedge-alignedwithdataforREADsandcentre-alignedwithdataforWRITEsDifferentialclockinputs(CKandCK)DLLalignsDQandDQStransitionswithCKtransitionsCommandsenteredoneachpositiveCKedge;dataanddatamaskreferencedtobothedgesofDQSFourinternalbanksforconcurrentoperationDataMaskforwritedata.
DMmaskswritedataatbothrisingandfallingedgesofdatastrobeBurstLength:2,4and8BurstType:SequentialandInterleavemodeProgrammableCASlatency:2,2.
5and3AutoRefreshandSelfRefreshModesAutoPrechargeTRASLockoutsupported(tRAP=tRCD)OPTIONSConfiguration(s):8Mx32,16Mx16,32Mx8Package(s):144BallBGA(x32)66-pinTSOP-II(x8,x16)and60BallBGA(x8,x16)Lead-freepackageavailableTemperatureRange:Commercial(0°Cto+70°C)Industrial(-40°Cto+85°C)Automotive,A1(-40°Cto+85°C)Automotive,A2(-40°Cto+105°C)8Mx32,16Mx16,32Mx8256MbDDRSDRAMMARCH2015DEVICEOVERVIEWISSI's256-MbitDDRSDRAMachieveshighspeeddatatransferusingpipelinearchitectureandtwodatawordaccessesperclockcycle.
The268,435,456-bitmemoryarrayisinternallyorganizedasfourbanksof64Mbtoallowconcurrentoperations.
ThepipelineallowsReadandWriteburstaccessestobevirtuallycontinuous,withtheoptiontoconcatenateortruncatethebursts.
Theprogrammablefeaturesofburstlength,burstsequenceandCASlatencyenablefurtheradvantages.
Thedeviceisavailablein8-bit,16-bitand32-bitdatawordsizeInputdataisregisteredontheI/OpinsonbothedgesofDataStrobesignal(s),whileoutputdataisreferencedtobothedgesofDataStrobeandbothedgesofCLK.
CommandsareregisteredonthepositiveedgesofCLK.
AnAutoRefreshmodeisprovided,alongwithaSelfRefreshmode.
AllI/OsareSSTL_2compatible.
KEYTIMINGPARAMETERSSpeedGrade-5-6UnitsFckMaxCL=3200167MHzFckMaxCL=2.
5167167MHzFckMaxCL=2133133MHzADDRESSTABLEParameter8Mx3216Mx1632Mx8Configuration2Mx32x4banks4Mx16x4banks8Mx8x4banksBankAddressPinsBA0,BA1BA0,BA1BA0,BA1AutoprechargePinsA8/APA10/APA10/APRowAddress4K(A0–A11)8K(A0–A12)8K(A0–A12)ColumnAddress512(A0–A7,A9)512(A0–A8)1K(A0–A9)RefreshCountCom.
/Ind.
/A1A24K/64ms4K/16ms8K/64ms8K/16ms8K/64ms2IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FCKCKCKECSRASCASWEA11COMMANDDECODER&CLOCKGENERATORModeRegistersandExt.
ModeRegistersREFRESHCONTROLLERREFRESHCOUNTERSELFREFRESHCONTROLLERROWADDRESSLATCHMULTIPLEXERCOLUMNADDRESSLATCHBURSTCOUNTERCOLUMNADDRESSBUFFERCOLUMNDECODERDATAINBUFFERDATAOUTBUFFERI/O0-31VDD/VDDQVss/VssQ12141291212212932323232512(x32)409640964096ROWDECODER4096MEMORYCELLARRAYBANK0SENSEAMPI/OGATEBANKCONTROLLOGICROWADDRESSBUFFERA9A8A7A6A5A4A3A2A1A0BA0BA1A104DM0-DM3DQS0-DQS342FUNCTIONALBLOCKDIAGRAM(x32)IntegratedSiliconSolution,Inc.
3Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FFUNCTIONALBLOCKDIAGRAM(x16)CKCKCKECSRASCASWEA12A11COMMANDDECODER&CLOCKGENERATORModeRegistersandExt.
ModeRegistersREFRESHCONTROLLERREFRESHCOUNTERSELFREFRESHCONTROLLERROWADDRESSLATCHMULTIPLEXERCOLUMNADDRESSLATCHBURSTCOUNTERCOLUMNADDRESSBUFFERCOLUMNDECODERDATAINBUFFERDATAOUTBUFFERI/O0-15VDD/VDDQVss/VssQ13151391313213916161616512(x16)819281928192ROWDECODER8192MEMORYCELLARRAYBANK0SENSEAMPI/OGATEBANKCONTROLLOGICROWADDRESSBUFFERA9A8A7A6A5A4A3A2A1A0BA0BA1A102LDM,UDMLDQS,UDQS224IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FPINCONFIGURATIONS66pinTSOP-TypeIIforx8VDDDQ0VDDQNCDQ1VSSQNCDQ2VDDQNCDQ3VSSQNCNCVDDQNCNCVDDNCNCWECASRASCSNCBA0BA1A10/APA0A1A2A3VDD123456789101112131415161718192021222324252627282930313233666564636261605958575655545352515049484746454443424140393837363534VSSDQ7VSSQNCDQ6VDDQNCDQ5VSSQNCDQ4VDDQNCNCVSSQDQSNCVREFVSSDMCKCKCKENCA12A11A9A8A7A6A5A4VSSPINDESCRIPTION:x8A0-A12RowAddressInputA0-A9ColumnAddressInputBA0,BA1BankSelectAddressDQ0–DQ7DataI/OCK,CKSystemClockInputCKEClockEnableCSChipSelectCASColumnAddressStrobeCommandRASRowAddressStrobeCommandWEWriteEnableDMDataWriteMaskDQSDataStrobeVDDPowerVDDQPowerSupplyforI/OPinsVSSGroundVSSQGroundforI/OPinsVREFSSTL_2referencevoltageNCNoConnectionIntegratedSiliconSolution,Inc.
5Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FPINCONFIGURATIONPackageCodeB:60-ballFBGA(topview)forx8(8mmx13mmBody,0.
8mmBallPitch)TopView(BallsseenthroughthePackage)PINDESCRIPTION:x8A0-A12RowAddressInputA0-A9ColumnAddressInputBA0,BA1BankSelectAddressDQ0–DQ7DataI/OCK,CKSystemClockInputCKEClockEnableCSChipSelectCASColumnAddressStrobeCommandRASRowAddressStrobeCommandWEWriteEnableDMDataWriteMaskDQSDataStrobeVDDPowerVDDQPowerSupplyforI/OPinsVSSGroundVSSQGroundforI/OPinsVREFSSTL_2referencevoltageNCNoConnectionABCDEFGHJKLMVSSQDQ7NCNCNCNCVDDQDQ6VDDQNCNCNCVSSQVDDDQ0DQ1NCVDDQDQ2DQ3VSSQNCNCVDDQVDDWECASRASBA1BA0A0A10/APA2A1A5A6A7A8A9CSVREFA12NCA4A3DQ5VDDQVSSQDQ4CKEA11CKVSSQDQSVSSDMCKVSSVDDVSS123789x8DeviceBallPatternABCDEFGHJKLM:BallExisting:DepopulatedBallTopView(SeetheballsthroughthePackage)123456789BGAPackageBallPatternTopView6IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FPINCONFIGURATIONS66pinTSOP-TypeIIforx16VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7NCVDDQLDQSNCVDDNCLDMWECASRASCSNCBA0BA1A10/APA0A1A2A3VDD123456789101112131415161718192021222324252627282930313233666564636261605958575655545352515049484746454443424140393837363534VSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8NCVSSQUDQSNCVREFVSSUDMCKCKCKENCA12A11A9A8A7A6A5A4VSSPINDESCRIPTION:x16A0-A12RowAddressInputA0-A8ColumnAddressInputBA0,BA1BankSelectAddressDQ0–DQ15DataI/OCK,CKSystemClockInputCKEClockEnableCSChipSelectCASColumnAddressStrobeCommandRASRowAddressStrobeCommandWEWriteEnableLDM,UDMDataWriteMaskLDQS,UDQSDataStrobeVDDPowerVDDQPowerSupplyforI/OPinsVSSGroundVSSQGroundforI/OPinsVREFSSTL_2referencevoltageNCNoConnectionIntegratedSiliconSolution,Inc.
7Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FPINCONFIGURATIONPackageCodeB:60-ballFBGA(topview)forx16(8mmx13mmBody,0.
8mmBallPitch)TopView(BallsseenthroughthePackage)PINDESCRIPTION:x16A0-A12RowAddressInputA0-A8ColumnAddressInputBA0,BA1BankSelectAddressDQ0–DQ15DataI/OCK,CKSystemClockInputCKEClockEnableCSChipSelectCASColumnAddressStrobeCommandRASRowAddressStrobeCommandWEWriteEnableLDM,UDMDataWriteMaskLDQS,UDQSDataStrobeVDDPowerVDDQPowerSupplyforI/OPinsVSSGroundVSSQGroundforI/OPinsVREFSSTL_2referencevoltageNCNoConnectionABCDEFGHJKLMVSSQDQ15DQ14VDDQDQ13DQ12VDDQDQ3VSSQVDDDQ0DQ2DQ1VDDQDQ4DQ6VSSQDQ5LDQSDQ7VDDQLDMVDDWECASRASBA1BA0A0A10/APA2A1A5A6A7A8A9CSVREFA12NCA4A3DQ11VDDQVSSQDQ9DQ10DQ8CKEA11CKVSSQUDQSVSSUDMCKVSSVDDVSS123789x16DeviceBallPatternABCDEFGHJKLM:BallExisting:DepopulatedBallTopView(SeetheballsthroughthePackage)123456789BGAPackageBallPatternTopView8IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FABCDEFGHJKLMDQS0DQ4DQ6DQ7DQ17DQ19DQS2DQ21DQ22CASRASCSDM0VDDQDQ5VDDQDQ16DQ18DM2DQ20DQ23WENCNCVSSQNCVSSQVDDVDDQVDDQNCVDDQVDDQVDDNCBA0DQ3VDDQVSSQVSSVSSQVSSQVSSQVSSQVSSQVSSBA1A0DQ2DQ1VSSQVSSQVSSVSSVSSVSSVSSA10A2A1DQ0VDDQVDDVSSVSSVSSVSSVSSVSSVDDA11A3DQ31VDDQVDDVSSVSSVSSVSSVSSVSSVDDA9A4DQ29DQ30VSSQVSSQVSSVSSVSSVSSVSSNCA5A6DQ28VDDQVSSQVSSVSSQVSSQVSSQVSSQVSSQVSSNCA7VSSQNCVSSQVDDVDDQVDDQNCVDDQVDDQVDDCKA8DM3VDDQDQ26VDDQDQ15DQ13DM1DQ11DQ9NCCKCKEDQS3DQ27DQ25DQ24DQ14DQ12DQS1DQ10DQ8NCNCVREF123456789101112Note:Vssballsinsidethedottedboxareoptionalforpurposesofthermaldissipation.
A0-A11RowAddressInputA0-A7,A9ColumnAddressInputBA0,BA1BankSelectAddressDQ0–DQ31DataI/OCK,CKSystemClockInputCKEClockEnableCSChipSelectCASColumnAddressStrobeCommandRASRowAddressStrobeCommandWEWriteEnableDM0-DM3DataWriteMaskDQS0-DQS3DataStrobeVDDPowerVDDQPowerSupplyforI/OPinsVREFSSTL_2referencevoltageVSSGroundVSSQGroundforI/OPinsNCNoConnectionPINDESCRIPTION:forx32PINCONFIGURATIONPackageCodeB:144-ballFBGA(topview)(12mmx12mmBody,0.
8mmBallPitch)TopView(Ballsseenthroughthepackage)IntegratedSiliconSolution,Inc.
9Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FPINFUNCTIONALDESCRIPTIONSSymbolTypeDescriptionCK,CKInputClock:CKandCKaredifferentialclockinputs.
AlladdressandcontrolinputsignalsaresampledonthecrossingofthepositiveedgeofCKandnegativeedgeofCK.
InputandoutputdataisreferencedtothecrossingofCKandCK(bothdirectionsofcrossing).
InternalclocksignalsarederivedfromCK/CK.
CKEInputClockEnable:CKEHIGHactivates,andCKELOWdeactivatesinternalclocksignals,anddeviceinputbuffersandoutputdrivers.
TakingCKELOWprovidesPRECHARGEPOWER-DOWNandSELFREFRESHoperation(allbanksidle),orACTIVEPOWERDOWN(rowACTIVEinanybank).
CKEissynchronousforallfunctionsexceptforSELFREFRESHEXIT,whichisachievedasynchronously.
Inputbuffers,excludingCK,CKandCKE,aredisabledduringpower-downandselfrefreshmodewhicharecontrivedforlowstandbypowerconsumption.
CSInputChipSelect:CSenables(registeredLOW)anddisables(registeredHIGH)thecommanddecoder.
AllcommandsaremaskedwhenCSisregisteredHIGH.
CSprovidesforexternalbankselectiononsystemswithmultiplebanks.
CSisconsideredpartofthecommandcode.
RAS,CAS,WEInputCommandInputs:RAS,CASandWE(alongwithCS)definethecommandbeingentered.
DM:x8;LDM,UDM:x16;DM0-DM3:x32InputInputDataMask:DMisaninputmasksignalforwritedata.
InputdataismaskedwhenDMissampledHIGHalongwiththatinputdataduringaWRITEaccess.
DMissampledonbothedgesofDQS.
AlthoughDMpinsareinput-only,theDMloadingmatchestheDQandDQSloading.
Forx16devices,LDMcorrespondstothedataonDQ0-DQ7,UDMcorrespondstothedataonDQ8-DQ15.
Forx32devices,DM0correspondstothedataonDQ0-DQ7,DM1correspondstothedataonDQ8-DQ15,DM2correspondstothedataonDQ16-DQ23,andDM3correspondstothedataonDQ24-DQ31.
BA0,BA1InputInputBankAddressInputs:BA0andBA1definetowhichbankanACTIVE,READ,WRITEorPRECHARGEcommandisbeingapplied.
A[12:0]InputAddressInputs:providetherowaddressforACTIVEcommands,andthecolumnaddressandAUTOPRECHARGEbitforREAD/WRITEcommands,toselectonelocationoutofthememoryarrayintherespectivebank.
TheaddressinputsalsoprovidetheopcodeduringaMODEREGISTERSETcommand.
A12isnotusedforx32.
DQ:DQ0-DQ7:x8;DQ0-DQ15:x16DQ0-DQ31:x32I/ODataBus:Input/OutputDQS:x8:LDQS,UDQSx16:DQS0-DQS3:x32I/ODataStrobe:Outputwithreaddata,inputwithwritedata.
Edge-alignedwithreaddata,centeredwithwritedata.
Usedtocapturewritedata.
Forx16device,LDQScorrespondstothedataonDQ0-DQ7,UDQScorrespondstothedataonDQ8-DQ15.
Forx32device,DQS0correspondstothedataonDQ0-DQ7,DQS1correspondstothedataonDQ8-DQ15,DQS2correspondstothedataonDQ16-DQ23,andDQS3correspondstothedataonDQ24-DQ31.
NC--NoConnect:Shouldbeleftunconnected.
VREFSupplySSTL_2referencevoltage.
VDDQSupplyI/OPowerSupply.
VSSQSupplyI/OGround.
VDDSupplyPowerSupply.
VSSSupplyGround.
10IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FCOMMANDSTRUTHTABLESAllcommands(addressandcontrolsignals)areregisteredonthepositiveedgeofclock(crossingofCKgoinghighandCKgoinglow).
TruthTableshowsbasictimingparametersforallcommands.
NAME(FUNCTION)CSRASCASWEBAAPAddressNotesDESELECT(NOP)HXXXXXX2NOOPERATION(NOP)LHHHXXX2ACTIVE(selectbankandactivaterow)LLHHValidXRowREAD(selectbankandcolumnandstartreadburst)LHLHValidLColumnREADwithAP(readburstwithAutoPrecharge)LHLHValidHColumn3WRITE(selectbankandcolumnandstartwriteburst)LHLLValidLColumnWRITEwithAP(writeburstwithAutoPrecharge)LHLLValidHColumn3BURSTTERMINATELHHLXXX4PRECHARGE(deactivaterowinselectedbank)LLHLValidLX5PRECHARGEALL(deactivaterowsinallbanks)LLHLXHX5AUTOREFRESHorenterSELFREFRESHLLLHXXX6,7,8MODEREGISTERSETLLLLValidOp-code9Notes:1.
Allstatesandsequencesnotshownareillegalorreserved.
2.
DESELECTandNOParefunctionallyinterchangeable.
3.
Autoprechargeisnon-persistent.
APHighenablesAutoPrecharge,whileAPLowdisablesAutoprecharge.
4.
BurstTerminateappliestoonlyReadburstswithAutoPrechargedisabled.
ThiscommandisundefinedandshouldnotbeusedforReadwithAutoPrechargeenabled,andforWritebursts.
5.
IfAPisLow,bankaddressdetermineswhichbankistobeprecharged.
IfAPisHigh,allbanksareprechargedandBA0-BA1aredon'tcare.
6.
ThiscommandisAUTOREFRESHifCKEisHigh,andSELFREFRESHifCKEislow.
7.
AlladdressinputsandI/Oare'don'tcare'exceptforCKE.
Internalrefreshcounterscontrolbankandrowaddressing.
8.
AllbanksmustbeprechargedbeforeissuinganAUTO-REFRESHorSELFREFRESHcommand.
9.
BA0andBA1valueselectbetweenMRSandEMRS.
10.
CKEisHIGHforallcommandsshownexceptSELFREFRESH.
TRUTHTABLE-DMOperationsFUNCTIONDMDQWriteEnableLValidWriteInhibitHXNote:Usedtomaskwritedata,providedcoincidentwiththecorrespondingdata.
TRUTHTABLE-COMMANDSx32x16x8AutoPrecharge(AP)A8A10A10RowAddress(RA)A0-A11A0-A12A0-A12ColumnAddress(CA)A0-A7,A9A0-A8A0-A9ADDRESSINGIntegratedSiliconSolution,Inc.
11Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FTRUTHTABLE-CKECKEn-1CKEnCurrentStateCOMMANDnACTIONnNOTESLLPowerDownXMaintainPowerDownLLSelfRefreshXMaintainSelfRefreshLHPowerDownNOPorDESELECTExitPowerDown6LHSelfRefreshNOPorDESELECTExitSelfRefresh6,7HLAllBanksIdleNOPorDESELECTPrechargePowerDownEntry6HLBank(s)ActiveNOPorDESELECTActivePowerDownEntry6HLAllBanksIdleAUTOREFRESHSelfRefreshentryHHSeeTruthTables-CommandsNotes:1.
CKEnisthelogicstateofCKEatclockedgen;CKEn-1wasthestateofCKEatthepreviousclockedge.
2.
CurrentstateisthestateofDDRimmediatelypriortoclockedgen.
3.
COMMANDnisthecommandregisteredatclockedgen,andACTIONnistheresultofCOMMANDn.
4.
Allstatesandsequencesnotshownareillegalorreserved.
5.
CKEmustnotgoLOWduringaReadorWrite,andmuststayHIGHuntilaftertrpstortwr,respectively.
6.
DESELECTandNOParefunctionallyinterchangeable.
7.
NOPsorDeselectsmustbeissuedforatleasttsnrafterSelf-Refreshexitbeforeanyothercommand.
AfterDLLReset,atleasttxsrdmustelapsebeforeanyReadcommandsoccur.
BasicTimingParametersforCommandsNOTE:Input=A0-An,BA0,BA1,CKE,CS,RAS,CAS,WE;An=AddressbusMSB=Don'tCaretCLtCHtIStIHtCKCKCKInputValidValidValid12IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FSIMPLIFIEDSTATEDIAGRAMPREALL=PrechargeAllBanksCKEL=EnterPowerDownMRS=ModeRegisterSetCKEH=ExitPowerDownEMRS=ExtendedModeRegisterSetACT=ActiveSelfAutoIdleMRSEMRSRowPrechargeWriteWriteWriteReadReadPowerACTReadAReadREFSREFSXREFACKELMRSCKEHCKEHCKELWritePowerAppliedAutomaticSequenceCommandSequenceReadAWriteAReadPREPREPREPRERefreshRefreshActiveActivePowerDownPrechargePowerDownOnAReadAReadAWriteABurstStopPREALLPrechargePREALLREFS=EnterSelfRefreshWriteA=WritewithAutoprechargeREFSX=ExitSelfRefreshReadA=ReadwithAutoprechargeREFA=AutoRefreshPRE=PrechargeIntegratedSiliconSolution,Inc.
13Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FFUNCTIONALDESCRIPTIONTheDDRSDRAMisahighspeedCMOS,dynamicrandom-accessmemoryinternallyconfiguredasaquad-bankDRAM.
The256Mbdevicescontains:268,435,456bits.
TheDDRSDRAMusesdoubledataratearchitecturetoachievehighspeedoperation.
Thedoubledataratearchitectureisessentiallya2nprefetcharchitecturewithaninterfacedesignedtotransfertwodatawordsperclockcycleattheI/Opins.
AsinglereadorwriteaccessfortheDDRSDRAMeffectivelyconsistsofasingle2n-bitwide,oneclockcycledatatransferattheinternalDRAMcoreandtwocorrespondingn-bitwide,one-half-clock-cycledatatransfersattheI/Opins.
ReadandwriteaccessestotheDDRSDRAMareburstoriented;accessesstartataselectedlocationandcontinueforaprogrammednumberoflocationsinaprogrammedsequence.
AccessesbeginwiththeregistrationofanACTIVEcommand,whichisthenfollowedbyaREADorWRITEcommand.
TheaddressbitsregisteredcoincidentwiththeACTIVEcommandareusedtoselectthebankandtherowtobeaccessed.
TheaddressbitsregisteredcoincidentwiththeREADorWRITEcommandareusedtoselectthebankandthestartingcolumnlocationfortheburstaccess.
Priortonormaloperation,theDDRSDRAMmustbeinitialized.
Thefollowingsectionprovidesdetailedinformationcoveringdeviceinitialization,registerdefinition,commanddescriptionanddeviceoperationINITIALIZATIONDDRSDRAMsmustbepoweredupandinitializedinapredefinedmanner.
Operationsproceduresotherthanthosespecifiedmayresultinundefinedoperation.
Ifthereisanyinterruptiontothedevicepower,theinitializationroutineshouldbefollowed.
Thestepstobefollowedfordeviceinitializationarelistedbelow.
TheInitializationFlowdiagramandtheInitializationFlowsequenceareshowninthefollowingfigures.
TheModeRegisterandExtendedModeRegisterdonothavedefaultvalues.
Iftheyarenotprogrammedduringtheinitializationsequence,itmayleadtounspecifiedoperation.
TheclockstopfeatureisnotavailableuntilthedevicehasbeenproperlyinitializedfromStep1through13.
Step1:ApplyVDDbeforeoratthesametimeasVDDQ.
Step2:CKEmustmaintainLVCMOSLowuntilVREFisstable.
ApplyVDDQbeforeapplyingVTTandVREF.
Step3:Theremustbeatleast200μsofvalidclocksbeforeanycommandmaybegiventotheDRAM.
DuringthistimeNOPorDESELECTcommandsmustbeissuedonthecommandbusandCKEshouldbebroughtHIGH.
Step4:IssueaPRECHARGEALLcommand.
Step5:ProvideNOPsorDESELECTcommandsforatleasttRPtime.
Step6:IssueEMRScommandStep7:IssueMRScommand,loadthebasemoderegisterandtoresettheDLL.
Setthedesiredoperatingmodes.
Step8:ProvideNOPsorDESELECTcommandsforatleasttMRDtime.
Step9:IssueaPRECHARGEALLcommandStep10:Issue2ormoreAUTOREFRESHcyclesStep11:IssueMRScommandwiththeresetDLLbitdeactivatedtoprogramoperatingparameterswithoutresettingtheDLLStep12:ProvideNOPorDESELECTcommandsforatleasttMRDtime.
Step13:TheDRAMhasbeenproperlyinitializedandisreadyforanyvalidcommand.
14IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FInitializationWaveformSequenceNotes:1.
VTTisnotapplieddirectlytothedevice,howevertVTDmustbegreaterthanorequaltozerotoavoiddevicelatch--up.
2.
tMRDisrequiredbeforeanycommandcanbeapplied,and200cyclesofCKarerequiredbeforeanyexecutablecommandcanbeapplied3.
ThetwoAutoRefreshcommandsmaybemovedtofollowthefirstMRSbutprecedethesecondPRECHARGEALLcom-mand.
4.
APisA8forx32,andA10forx8/x16.
AddressisA0toA12exceptAP.
CKELVCMOSLOWLEVELDQBA0,BA1200cyclesofCK**ExtendedModeRegisterSetLoadModeRegister,ResetDLL(withAP=H)LoadModeRegister(withAP=L)tMRDtMRDtMRDtRPtRFCtRFCtISPower--up:VDDandCLKstableT=200sHigh--ZtIH()()()()DM()()()()()()()()()()()()()()()()()()DQSHigh--Z()()()()AddressAP4ALLBANKSDON'TCARECKCKtCKtCHtCLVTT(system1)VREFVDDVDDQCOMMANDMRSNOPPREEMRSAR)ARtIStIHBA0=H,BA1=LtIStIHtIStIHBA0=L,BA1=LtIStIH()()()()()()()()()()()()()()()()()()()()())()(()CODECODEtIStIHCODECODEMRSBA0=L,BA1=LCODECODE()()()()()()()()PREALLBANKStIStIHRARAACTBA()()()()()()()()()()()()()(()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()()tVDT≥0222IntegratedSiliconSolution,Inc.
15Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FMODEREGISTER(MR)DEFINITIONTheModeRegisterisusedtodefinethespecificmodeofoperationoftheDDRSDRAM.
Thisdefinitionincludesthedefinitionofaburstlength,abursttype,andaCASlatency.
TheModeRegisterisprogrammedviatheMODEREGISTERSETcommand(withBA0=0andBA1=0)andwillretainthestoredinformationuntilitisreprogrammed,orthedevicelosespower.
ModeRegisterbitsA0-A2specifytheburstlength,A3thetypeofburst(sequentialorinterleave),A4-A6theCASlatency,andA8DLLreset.
Alogic0shouldbeprogrammedtoalltheundefinedaddressesbitstoensurefuturecompatibility.
TheModeRegistermustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimetMRDbeforeinitiatinganysubsequentoperation.
Violatingeitheroftheserequirementswillresultinunspecifiedoperation.
Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfutureversionsmayresultModeRegisterBA1BA0A121A11A10A9A8A7A6A5A4A3A2A1A0A2A1A0BurstLength000Reserved001201040118100Reserved101Reserved110Reserved111ReservedAddressBus(Ax)ModeReg.
(Ex)A3BurstType0Sequential1InterleaveA6A5A4CASLatency000Reserved001Reserved01020113100Reserved101Reserved1102.
5111ReservedNotes:1.
A12isnotusedinx32andshouldbeignoredforthisoption.
2.
Alogic0shouldbeprogrammedtoallunused/undefinedaddressbitstoensurefuturecompatibility.
BA1BA0ModeRegisterDefinition00ProgramModeRegister01ProgramExtendedModeRegister10Reserved11ReservedA12A11A10A9A8A7DLL000000Normaloperation000010ResetDLL16IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FBURSTLENGTHReadandwriteaccessestotheDDRSDRAMareburstoriented,withtheburstlengthbeingsetandtheburstorderasinBurstDefinition.
TheburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcanbeaccessedforagivenREADorWRITEcommand.
Burstlengthsof2,4,or8locationsareavailableforboththesequentialandtheinterleavedbursttypes.
Notes:1.
Foraburstlengthoftwo,A1-Anselectsthetwodataelementblock;A0selectsthefirstaccesswithintheblock.
2.
Foraburstlengthoffour,A2-Anselectsthefourdataelementblock;A0-A1selectsthefirstaccesswithintheblock.
3.
Foraburstlengthofeight,A3-Anselectstheeightdataelementblock;A0-A2selectsthefirstaccesswithintheblock.
4.
Wheneveraboundaryoftheblockisreachedwithinagivensequence,thefollowingaccesswrapswithintheblock.
BurstDefinitionBurstLengthStartingColumnAddressOrderofAccessesWithinaBurstType=SequentialType=Interleaved2A000-10-111-01-04A1A0000-1-2-30-1-2-3011-2-3-01-0-3-2102-3-0-12-3-0-1113-0-1-23-2-1-08A2A1A00000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-2-3-4-5-6-7-01-0-3-2-5-4-7-60102-3-4-5-6-7-0-12-3-0-1-6-7-4-50113-4-5-6-7-0-1-23-2-1-0-7-6-5-41004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-6-7-0-1-2-3-45-4-7-6-1-0-3-21106-7-0-1-2-3-4-56-7-4-5-2-3-0-11117-0-1-2-3-4-5-67-6-5-4-3-2-1-0IntegratedSiliconSolution,Inc.
17Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FWhenaREADorWRITEcommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.
Allaccessesforthatbursttakeplacewithintheblock,meaningthattheburstwillwrapwithintheblockifaboundaryisreached.
TheblockisuniquelyselectedbyA1-Anwhentheburstlengthissettotwo,byA2-Anwhentheburstlengthissetto4,byA3-Anwhentheburstlengthissetto8.
Anisthemostsignificantcolumnaddressbit,whichdependsifthedeviceisx8,x16orx32.
An=A9forx8,An=A8forx16andAn=A9forx32.
Theprogrammedburstlengthappliestobothreadandwritebursts.
BURSTTYPEAccesseswithinagivenburstmaybeprogrammedtobeeithersequentialorinterleaved;thisisreferredtoasthebursttypeandisselectedviabitA3.
Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,thebursttypeandthestartingcolumnaddress.
READLATENCYTheREADlatency,orCASlatency,isthedelaybetweentheregistrationofaREADcommandandtheavailabilityofthefirstpieceofoutputdata.
IfaREADcommandisregisteredataclockedgenandthelatencyis3clocks,thefirstdataelementwillbevalidatn+2tCK+tAC.
IfaREADcommandisregisteredataclockedgenandthelatencyis2clocks,thefirstdataelementwillbevalidatn+tCK+tAC.
OPERATINGMODEThenormaloperatingmodeisselectedbyissuingaModeRegisterSetcommandwithbitsA7toAneachsettozero,andbitsA0toA6settothedesiredvalues.
ADLLresetisinitiatedbyissuingaModeRegisterSetcommandwithbitsA7andA9toAneachsettozero,bitA8settoone,andbitsA0toA6settothedesiredvalues.
AModeRegisterSetcommandissuedtoresettheDLLmustalwaysbefollowedbyaModeRegisterSetcommandtoselectnormaloperatingmode(A8=0).
AllothercombinationsofvaluesforA7toAnarereservedforfutureuseand/ortestmodes.
Testmodesandreservedstatesshouldnotbeusedbecauseunknownoperationorincompatibilitywithfutureversionsmayresult.
18IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FCASLATENCIESIntegratedSiliconSolution,Inc.
19Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FEXTENDEDMODEREGISTER(EMR)DEFINITIONTheExtendedModeRegistercontrolsfunctionsbeyondthosecontrolledbytheModeRegister;theseadditionalfunctionsincludeDLLenable/disable,andoutputdrivestrengthselection.
TheExtendedModeRegisterisprogrammedviatheMODEREGISTERSETcommand(withBA1=0andBA0=1)andwillretainthestoredinformationuntilitisreprogrammed,orthedevicelosespower.
TheExtendedModeRegistermustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwaitthespecifiedtimetMRDbeforeinitiatinganysubsequentoperation.
Violatingeitheroftheserequirementswillresultinunspecifiedoperation.
Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfutureversionsmayresult.
DLLEnable/DisableTheDLLmustbeenabledfornormaloperation.
DLLenableisrequiredduringpower-upinitialization,anduponreturningtonormaloperationafterhavingdisabledtheDLLforthepurposeofdebugorevaluation(uponexitingSelfRefreshMode,theDLLisenabledautomatically).
AnytimetheDLLisenabledaDLLResetmustfollowand200clockcyclesmustoccurbeforeanyexecutablecommandcanbeissued.
OUTPUTDRIVESTRENGTH(DS)ThenormaldrivestrengthforalloutputsisspecifiedtobeSSTL_2,ClassII.
ThisDRAMalsosupportsareduceddriverstrengthoption,intendedforlighterloadand/orpoint-to-pointenvironments.
EXTENDEDMODEREGISTERBA1BA0A122A11A10A9A8A7A6A5A4A3A2A1A0A0DLL0Enable1DisableAddressBus(Ax)Ext.
ModeReg.
(Ex)A6A1DriveStrength00Full(100%)01Weak(60%)10Reserved11Matched(30%)NOTES:1.
Alogic0shouldbeprogrammedtoallunused/undefinedad-dressbitstoensurefuturecompatibility2.
A12isnotusedforx32andshouldbeignoredforthisoption.
BA1BA0ModeRegisterDefinition00ProgramModeRegister01ProgramExtendedModeRegister10Reserved11ReservedReserved(1)Reserved(1)20IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FAbsoluteMaximumRatingParameterSymbolValueUnitVoltageonanypinrelativetoVSSVin,Vout-1.
0~3.
6VVoltageonVDD&VDDQsupplyrelativetoVSSVdd,Vddq-1.
0~3.
6VStoragetemperatureTstg-55~+150oCPowerdissipationPd1.
5WShortcircuitcurrentIos50mANote:PermanentdevicedamagemayoccurifABSOLUTEMAXIMUMRATINGSareexceeded.
Functionaloperationshouldberestrictedtorecommendoperationcondition.
ExposuretohigherthanrecommendedvoltageforextendedperiodsoftimecouldaffectdevicereliabilityAC/DCElectricalCharacteristicsandOperatingConditionsRecommendedoperatingconditions(VoltagereferencedtoVSS=0V;TA=0to70oCforCommercial,TA=-40oCto+85oCforIndustrialandA1,TA=-40oCto+105oCforA2)ParameterSymbolMinMaxUnitNoteSupplyvoltage(withanominalVDDof2.
5V)Vdd2.
32.
7VI/OSupplyvoltage(withanominalVDDof2.
5V)Vddq2.
32.
7VI/OReferencevoltageVref0.
49*VDDQ0.
51*VDDQV1I/OTerminationvoltage(system)VttVREF-0.
04VREF+0.
04V2InputlogichighvoltageVih(dc)VREF+0.
15VDDQ+0.
3VInputlogiclowvoltageVil(dc)-0.
3VREF-0.
15VInputVoltageLevel,CLKandCLKinputsVin(dc)-0.
3VDDQ+0.
3VInputDifferentialVoltage,CLKandCLKinputsVid(dc)0.
36VDDQ+0.
6V3V-IMatching:PulluptoPulldownCurrentRatioVi(Ratio)0.
711.
4–4InputleakagecurrentIl-22uAOutputleakagecurrentIoz-55uAOutputHighCurrent(Normalstrengthdriver);VOUT=VTT+0.
84VIoh-16.
8–mAOutputLowCurrent(Normalstrengthdriver);VOUT=VTT-0.
84VIol16.
8–mAOutputHighCurrent(Halfstrengthdriver);VOUT=VTT+0.
45VIohr-9–mAOutputLowCurrent(Halfstrengthdriver);VOUT=VTT-0.
45VIolr9–mAAmbientOperatingTemperatureCommercialIndustrialA1A2TaTaTaTa0-40-40-40+70+85+85+105oCoCoCoCNote:1.
VREFisexpectedtobeequalto0.
5*VDDQofthetransmittingdevice,andtotrackvariationsinthedclevelofsame.
Peak-topeaknoiseonVREFmaynotexceed+/-2%ofthedcvalue.
2.
VTTisnotapplieddirectlytothedevice.
VTTisasystemsupplyforsignalterminationresistors,isexpectedtobesetequaltoVREF,andmusttrackvariationsintheDClevelofVREF3.
VIDisthemagnitudeofthedifferencebetweentheinputlevelonCLKandtheinputlevelonCLK.
4.
Theratioofthepullupcurrenttothepulldowncurrentisspecifiedforthesametemperatureandvoltage,overtheentiretem-peratureandvoltagerange,fordevicedraintosourcevoltagesfrom0.
25Vto1.
0V.
Foragivenoutput,itrepresentsthemaxi-mumdifferencebetweenpullupandpulldowndriversduetoprocessvariation.
Thefullvariationintheratioofthemaximumtominimumpullupandpulldowncurrentwillnotexceed1.
7fordevicedraintosourcevoltagesfrom0.
1to1.
0.
IntegratedSiliconSolution,Inc.
21Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FCAPACITANCECHARACTERISTICS(1,2)(Vdd=Vddq=2.
5V+0.
2V,unlessotherwisenoted)SymbolParameterTestConditionLimitsUnitsMinMaxCI(A)InputCapacitance,addresspinVI=1.
25vf=100MHzVI=25mVrms1.
33pFCI(C)InputCapacitance,controlpin1.
33pFCI(K)InputCapacitance,CLKpin24pFCI/OI/OCapacitance,I/O,DQS,DMpin35pFNotes:1.
Thisparameterischaracterized.
2.
Conditions:Frequency=100MHz;Vout(DC)=Vdd/2;Vout(peak-to-peak)=0.
2V;Vref=Vss.
PackageSubstrateTheta-ja(Airflow=0m/s)Theta-ja(Airflow=1m/s)Theta-ja(Airflow=2m/s)Theta-jcUnitsTSOP2(66)4-layer55.
849.
446.
08.
1C/WBGA(60)4-layer43.
539.
937.
712.
2C/WBGA(144)4-layerTBDTBDTBDTBDC/WTHERMALRESISTANCE22IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FIDDSpecificationParametersandTestConditions:x8,x16(Vdd=Vddq=2.
5V±0.
2V,Vss=VssQ=0V,OutputOpen,unlessotherwisenoted)SymbolParameter/TestCondition-5-6UnitsIDD0Operatingcurrentforonebankactive-precharge;tRC=tRC(min);tCK=tCK(min);DQ,DMandDQSinputschangingonceperclockcycle;addressandcontrolinputschangingonceeverytwoclockcycles;CS=highbetweenvalidcommands.
9075mAIDD1Operatingcurrentforonebankoperation;onebankopen,BL=4,tRC=tRC(min),tCK=tCK(min),Iout=0mA,Addressandcontrolinputschangingonceperclockcycle.
11095mAIDD2PPrechargepower-downstandbycurrent;allbanksidle;power-downmode;CKEVIL(max);tCK=tCK(min);VIN=VREFforDQ,DQSandDM3030mAIDD2FPrechargefloatingstandbycurrent;CSVIH(min);allbanksidle;CKEVIH(min);tCK=tCK(min);addressandothercontrolinputschangingonceperclockcycle;VIN=VREFforDQ,DQSandDM8070mAIDD3PActivepower-downstandbycurrent;onebankactive;power-downmode;CKEVIL(max);tCK=tCK(min);VIN=VREFforDQ,DQSandDM3030mAIDD3NActivestandbycurrent;CSVIH(min);CKEVIH(min);onebankactive;tRC=tRAS(max);tCK=tCK(min);DQ,DQSandDMinputschangingtwiceperclockcycle;addressandothercontrolinputschangingonceperclockcycle8070mAIDD4ROperatingcurrentforburstread;burstlength=2;reads;continuousburst;onebankactive;addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);50%ofdatachangingoneverytransfer;lOUT=0mA190160mAIDD4WOperatingcurrentforburstwrite;burstlength=2;writes;continuousburst;onebankactiveaddressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle,50%ofinputdatachangingateverytransfer200170mAIDD5Autorefreshcurrent;tRC=tRFC(min);110110mAIDD6Selfrefreshcurrent;CKE0.
2V;66mAIDD7Operatingcurrentforfourbankoperation;fourbankinterleavingREADs(BL=4)withautoprecharge;tRC=tRC(min),tCK=tCK(min);AddressandcontrolinputschangeonlyduringACTIVE,READ,orWRITEcommands220190mAIntegratedSiliconSolution,Inc.
23Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FIDDSpecificationParametersandTestConditions:x32(Vdd=Vddq=2.
5V±0.
2V,Vss=VssQ=0V,OutputOpen,unlessotherwisenoted)SymbolParameter/TestCondition-5-6UnitsIDD0Operatingcurrentforonebankactive-precharge;tRC=tRC(min);tCK=tCK(min);DQ,DMandDQSinputschangingonceperclockcycle;addressandcontrolinputschangingonceeverytwoclockcycles;CS=highbetweenvalidcommands.
130105mAIDD1Operatingcurrentforonebankoperation;onebankopen,BL=4,tRC=tRC(min),tCK=tCK(min),Iout=0mA,Addressandcontrolinputschangingonceperclockcycle.
160140mAIDD2PPrechargepower-downstandbycurrent;allbanksidle;power-downmode;CKEVIL(max);tCK=tCK(min);VIN=VREFforDQ,DQSandDM3535mAIDD2FPrechargefloatingstandbycurrent;CSVIH(min);allbanksidle;CKEVIH(min);tCK=tCK(min);addressandothercontrolinputschangingonceperclockcycle;VIN=VREFforDQ,DQSandDM9080mAIDD3PActivepower-downstandbycurrent;onebankactive;power-downmode;CKEVIL(max);tCK=tCK(min);VIN=VREFforDQ,DQSandDM3535mAIDD3NActivestandbycurrent;CSVIH(min);CKEVIH(min);onebankactive;tRC=tRAS(max);tCK=tCK(min);DQ,DQSandDMinputschangingtwiceperclockcycle;addressandothercontrolinputschangingonceperclockcycle9080mAIDD4ROperatingcurrentforburstread;burstlength=2;reads;continuousburst;onebankactive;addressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);50%ofdatachangingoneverytransfer;lOUT=0mA260210mAIDD4WOperatingcurrentforburstwrite;burstlength=2;writes;continuousburst;onebankactiveaddressandcontrolinputschangingonceperclockcycle;tCK=tCK(min);DQ,DMandDQSinputschangingtwiceperclockcycle,50%ofinputdatachangingateverytransfer280240mAIDD5Autorefreshcurrent;tRC=tRFC(min);180180mAIDD6Selfrefreshcurrent;CKE0.
2V;66mAIDD7Operatingcurrentforfourbankoperation;fourbankinterleavingREADs(BL=4)withautoprecharge;tRC=tRC(min),tCK=tCK(min);AddressandcontrolinputschangeonlyduringACTIVE,READ,orWRITEcommands340300mA24IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FPARAMETERSYMBOL-5-6UNITSMINMAXMINMAXDQoutputaccesstimeforCLK,/CLKtAC-0.
70.
7-0.
70.
7nsDQSoutputaccesstimeforCLK,/CLKtDQSCK-0.
60.
6-0.
60.
6nsCLKhigh-levelwidthtCH0.
450.
550.
450.
55tCKCLKlow-levelwidthtCL0.
450.
550.
450.
55tCKCLKhalfperiodtHPmin(tCL,tCH)–min(tCL,tCH)–nsCLKcycletimeCL=3tCK(3)510610nsCL=2.
5tCK(2.
5)610610nsCL=2tCK(2)7.
5107.
510nsDQandDMinputholdtimetDH0.
4–0.
45–nsDQandDMinputsetuptimetDS0.
4–0.
45–nsControl&Addressinputpulsewidth(foreachinput)tIPW2.
2–2.
2–nsDQandDMinputpulsewidth(foreachinput)tDIPW1.
75–1.
75–nsDQ&DQShigh-impedancetimefromCLK,/CLKtHZ–0.
7–0.
7nsDQ&DQSlow--impedancetimefromCLK,/CLKtLZ-0.
7–-0.
7–nsDQS--DQSkew,DQStolastDQvalid,pergroup,peraccesstDQSQ–0.
4–0.
45nsDQ/DQSoutputholdtimefromDQStQHtHP-tQHS–tHP-tQHS–nsDataHoldSkewFactortQHS–0.
5–0.
55nsWritecommandtofirstDQSlatchingtransitiontDQSS0.
721.
280.
751.
28tCKDQSinputhighpulsewidthtDQSH0.
35–0.
35–tCKDQSinputlowpulsewidthtDQSL0.
35–0.
35–tCKDQSfallingedgetoCLKsetuptimetDSS0.
2–0.
2–tCKDQSfallingedgeholdtimefromCLKtDSH0.
2–0.
2–tCKMODEREGISTERSETcommandcycletimetMRD2–2–tCKWritepreamblesetuptimetWPRES0–0–nsWritepostambletWPST0.
40.
60.
40.
6tCKWritepreambletWPRE0.
25–0.
25–tCKAddressandControlinputholdtime(fastslewrate)tIHF0.
6–0.
75–nsAddressandControlinputsetuptime(fastslewrate)tISF0.
6–0.
75–nsAddressandControlinputholdtime(slowslewrate)tIH0.
7–0.
8-–nsAddressandControlinputsetuptime(slowslewrate)tIS0.
7–0.
8–nsReadpreambletRPRE0.
91.
10.
91.
1tCKReadpostambletRPST0.
40.
60.
40.
6tCKACTIVEtoPRECHARGEcommandtRAS4070,00042120,000nsACTIMINGREQUIREMENTSAbsoluteSpecifications(VDD,VDDQ=+2.
5V±0.
2V)IntegratedSiliconSolution,Inc.
25Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FPARAMETERSYMBOL-5-6UNITSMINMAXMINMAXACTIVEtoACTIVE/AutoRefreshcommandperiodtRC55–60–nsAutoRefreshtoActive/AutotRFC70–72–nsACTIVEtoREADorWRITEdelaytRCD15–15–nsPRECHARGEcommandperiodtRP15–15–nsActivetoAutoprechargeDelaytRAP15–15–nsACTIVEbankAtoACTIVEbankBcommandtRRD10–12–nsWriterecoverytimetWR15–15–nsAutoPrechargewriterecovery+prechargetimetDALtWR+tRP–tWR+tRP–tCKInternalWritetoReadCommandDelaytWTR2–1–tCKExitselfrefreshtonon-READtXSNR70–75–nsExitselfrefreshtoREADcommandtXSRD200–200–tCKAveragePeriodicRefreshInterval(x8/x16)Ta≤85CtREFI–7.
8–7.
8msTa>85C,A2onlytREFI–1.
9–1.
9msAveragePeriodicRefreshInterval(x32)Ta≤85CtREFI–15.
6–15.
6msTa>85C,A2onlytREFI–3.
9–3.
9msACTIMINGREQUIREMENTSAbsoluteSpecifications(VDD,VDDQ=+2.
5V±0.
2V)OutputLoadConditionDQOutputTimingMeasurementReferencePointVREFVREFDQSVOUTVREF30pF50VTT=VREFZo=5026IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FNotes:1.
AllvoltagesreferencedtoVss.
2.
TestsforACtiming,IDD,andelectrical,ACandDCcharacteristics,maybeconductedatnominalreference/supplyvoltagelevels,buttherelatedspecificationsanddeviceoperationareguaranteedforthefullvoltagerangespecified.
3.
ACtimingandIDDtestsmayuseaVILtoVIHswingofupto1.
5Vinthetestenvironment,butinputtimingisstillreferencedtoVREF(ortothecrossingpointforCK//CK),andparameterspecificationsareguaranteedforthespecifiedACinputlevelsun-dernormaluseconditions.
Theminimumslewratefortheinputsignalsis1V/nsintherangebetweenVIL(AC)andVIH(AC).
4.
TheACandDCinputlevelspecificationsareasdefinedintheSSTL_2Standard(i.
e.
thereceiverwilleffectivelyswitchasaresultofthesignalcrossingtheACinputlevel,andwillremaininthatstateaslongasthesignaldoesnotringbackabove(below)theDCinputLOW(HIGH)level.
5.
VREFisexpectedtobeequalto0.
5*VddQofthetransmittingdevice,andtotrackvariationsintheDClevelofthesame.
Peak-to-peaknoiseonVREFmaynotexceed+2%oftheDCvalue.
6.
VTTisnotapplieddirectlytothedevice.
VTTisasystemsupplyforsignalterminationresistors,isexpectedtobesetequaltoVREF,andmusttrackvariationsintheDClevelofVREF.
7.
VIDisthemagnitudeofthedifferencebetweentheinputlevelonCLKandtheinputlevelon/CLK.
8.
ThevalueofVIXisexpectedtoequal0.
5*VddQofthetransmittingdeviceandmusttrackvariationsintheDClevelofthesame.
9.
IDDspecificationsaretestedafterthedeviceisproperlyinitialized.
10.
TheCLK//CLKinputreferencelevel(fortimingreferencedtoCLK//CLK)isthepointatwhichCLKand/CLKcross;theinputreferencelevelforsignalsotherthanCLK//CLK,isVREF.
11.
InputsarenotrecognizedasvaliduntilVREFstabilizes.
Exception:duringtheperiodbeforeVREFstabilizes,CKE0.
3VddQisrecognizedasLOW.
12.
tHZandtLZtransitionsoccurinthesameaccesstimewindowsasvaliddatatransitions.
Theseparametersarenotrefer-encedtoaspecificvoltagelevel,butspecifywhenthedeviceoutputisnolongerdriving(HZ),orbeginsdriving(LZ).
13.
ThemaximumlimitfortWPRESisnotadevicelimit.
Thedevicewilloperatewithagreatervalueforthisparameter,butsys-temperformance(busturnaround)willdegradeaccordingly.
14.
ThespecificrequirementisthatDQSbevalid(HIGH,LOW,oratsomepointonavalidtransition)onorbeforethisCLKedge.
Avalidtransitionisdefinedasmonotonic,andmeetingtheinputslewratespecificationsofthedevice.
Whennowriteswerepreviouslyinprogressonthebus,DQSwillbetransitioningfromHigh-ZtologicLOW.
Ifapreviouswritewasinprog-ress,DQScouldbeHIGH,LOW,ortransitioningfromHIGHtoLOWatthistime,dependingontDQSS.
15.
AmaximumofeightAUTOREFRESHcommandscanbepostedtoanygivenDDRSDRAMdevice.
16.
tXPRDshouldbe200tCLKintheconditionoftheunstableCLKoperationduringthepowerdownmode.
17.
Forcommand/addressandCK&/CKslewrate>1.
0V/ns.
18.
Forslewrateslessthan1V/nsandgreaterthanorequalto0.
5V/ns.
Iftheslewrateislessthan0.
5V/ns,timingmustbederated:tishasanadditional50pspereach100mV/nsreductioninslewratefromthe500mV/ns.
tihhasnothingadded.
Iftheslewrateexceeds4.
5V/ns,functionalityisuncertain.
Foroperationat166mHzorfaster,slewratesmustbegreaterthanorequalto0.
5V/ns.
19.
Tomaintainavalidlevel,thetransitioningedgeoftheinputmust:a.
SustainaconstantslewratefromthecurrentAClevelthroughtothetargetAClevel,VIL(AC)orVIH(AC).
b.
ReachatleastthetargetAClevel.
c.
AftertheACtargetlevelisreached,continuetomaintainatleastthetargetDClevel,VIL(DC)orVIH(DC).
20.
VIHovershoot:VIH,max=VDDO+1.
5Vforapulsewidth≤3ns,andthepulsewidthcannotbegreaterthan1/3ofthecyclerate.
VIIundershoot:VIL,min=-1.
5Vforapulsewidth≤3ns,andthepulsewifthcannotbegreaterthan1/3ofthecyclerate.
21.
Min(tCL,tCH)referstothesmalleroftheactualclocklowtimeandtheactualclockhightimeasprovidedtothedevice.
22.
ForA2temperaturegradewithTA>85°C:IDD2F,IDD3N,andIDD7arederatedto10%abovethesevalues;IDD2PandIDD6arederatedto20%abovethesevalues.
Parameter/ConditionSymbolMinMaxUnitsInputhigh(logic1)voltageVIH(AC)VREF+0.
3101.
5VInputlow(logic0)voltageVIL(AC)-1.
5VI/OreferencevoltageVREF(AC)0.
51xVDDQ4.
5V-nsACInputOperatingConditions(VDD=VDDQ=2.
5±0.
2V,VSS=VSSQ=0V,outputopen,unlessotherwisenoted.
)IntegratedSiliconSolution,Inc.
27Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FOUTPUTSLEWRATECHARACTERISTICSSlewRateCharacteristicTypicalRange(V/ns)Min(V/ns)Max(V/ns)PullupSlewRate1.
2-2.
50.
75.
0PulldownSlewRate1.
2-2.
50.
75.
0ACOVERSHOOT/UNDERSHOOTSPECIFICATIONFORADDRESSANDCONTROLPINSParameterMaxUnitsPeakamplitudeallowedforovershoot1.
5VPeakamplitudeallowedforundershoot1.
5VAreabetweentheovershootsignalandVDDmustbelessthanorequalto(seefigurebelow)4.
5V-nsAreabetweentheundershootsignalandGNDmustbelessthanorequalto(seefigurebelow)4.
5V-nsOvershoot/UndershootSpecificationforData,Strobe,andMaskPinsParameterMaxUnitsPeakamplitudeallowedforovershoot1.
2VPeakamplitudeallowedforundershoot1.
2VAreabetweentheovershootsignalandVDDmustbelessthanorequalto(seefigurebelow)2.
4V-nsAreabetweentheundershootsignalandGNDmustbelessthanorequalto(seefigurebelow)2.
4V-nsAddressandControlACOvershootandUndershootDefinitionDQ/DM/DQSACOvershootandUndershootDefinitionGroundVDD-3-2-1+1+2+3+4+500123456Time(ns)Volts(V)UndershootOvershootMax.
amplitude=1.
5VMax.
area=4.
5V-nsVDD-3-2-1+1+2+3+4+500123456Volts(V)UndershootOvershootMax.
amplitude=1.
2VTime(ns)GroundMax.
area=2.
4V--ns28IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800F32Mx8ORDERINGINFORMATION-VDD=2.
5VCommercialRange:0°Cto+70°CFrequencySpeed(ns)OrderPartNo.
Package200MHz5IS43R83200F-5TL66-pinTSOP-II,Lead-free166MHz6IS43R83200F-6TL66-pinTSOP-II,Lead-freeIndustrialRange:-40°Cto+85°CFrequencySpeed(ns)OrderPartNo.
Package200MHz5IS43R83200F-5TLI66-pinTSOP-II,Lead-free166MHz6IS43R83200F-6TLI66-pinTSOP-II,Lead-freeIntegratedSiliconSolution,Inc.
29Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800F16Mx16ORDERINGINFORMATION-VDD=2.
5VCommercialRange:0°Cto+70°CFrequencySpeed(ns)OrderPartNo.
Package200MHz5IS43R16160F-5BL60-ballBGA,Lead-freeIS43R16160F-5TL66-pinTSOP-II,Lead-free166MHz6IS43R16160F-6BL60-ballBGA,Lead-freeIS43R16160F-6TL66-pinTSOP-II,Lead-freeIndustrialRange:-40°Cto+85°CFrequencySpeed(ns)OrderPartNo.
Package200MHz5IS43R16160F-5BLI60-ballBGA,Lead-freeIS43R16160F-5BI60-ballBGAIS43R16160F-5TLI66-pinTSOP-II,Lead-free166MHz6IS43R16160F-6BLI60-ballBGA,Lead-freeIS43R16160F-6BI60-ballBGAIS43R16160F-6TLI66-pinTSOP-II,Lead-freeAutomotive(A1)Range:-40°Cto+85°CFrequencySpeed(ns)OrderPartNo.
Package200MHz5IS46R16160F-5BLA160-ballBGA,Lead-freeIS46R16160F-5TLA166-pinTSOP-II,Lead-free166MHz6IS46R16160F-6BLA160-ballBGA,Lead-freeIS46R16160F-6TLA166-pinTSOP-II,Lead-free8Mx32ORDERINGINFORMATION-VDD=2.
5VCommercialRange:0°Cto+70°CFrequencySpeed(ns)OrderPartNo.
Package200MHz5IS43R32800F-5BL144-ballBGA,Lead-free166MHz6IS43R32800F-6BL144-ballBGA,Lead-freeIndustrialRange:-40°Cto+85°CFrequencySpeed(ns)OrderPartNo.
Package200MHz5IS43R32800F-5BLI144-ballBGA,Lead-freeIS43R32800F-5BI144-ballBGA166MHz6IS43R32800F-6BLI144-ballBGA,Lead-freeAutomotive(A1)Range:-40°Cto+85°CFrequencySpeed(ns)OrderPartNo.
Package166MHz6IS46R32800F-6BLA1144-ballBGA,Lead-freeAutomotive(A2)Range:-40°Cto+105°CFrequencySpeed(ns)OrderPartNo.
Package166MHz6IS46R16160F-6BLA260-ballBGA,Lead-freeIS46R16160F-6TLA266-pinTSOP-II,Lead-free30IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FΘNOTE:4.
Formedleadsshallbeplanarwithrespecttooneanotherwithin0.
1mm3.
Dimensionbdoesnotincludedambarprotrusion/intrusion.
2.
DimensionDandE1donotincludemoldprotrusion.
attheseatingplaneafterfinaltest.
1.
Controllingdimension:mmPackageOutline10/04/2006IntegratedSiliconSolution,Inc.
31Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800FMiniBallGridArrayPackageCode:B(60-Ball)8mmx13mm32IntegratedSiliconSolution,Inc.
Rev.
A04/7/2015IS43R83200FIS43/46R16160F,IS43/46R32800F