tRASios

DocumentNo.
E0349E20(Ver.
2.
0)DatePublishedMarch2003(K)JapanURL:http://www.
elpida.
comElpidaMemory,Inc.
2003PRELIMINARYDATASHEET20;BACKGROUND-COLOR:#4ae2f7">56MbitsDDRSDRAMEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTA(32Mwords****8bits)DescriptionTheEDD20;BACKGROUND-COLOR:#4ae2f7">508AKisa20;BACKGROUND-COLOR:#4ae2f7">56MbitsDDRSDRAMorganizedas8,388,608words*8bits*4banks.
ReadandwriteoperationsareperformedatthecrosspointsoftheCKandthe/CK.
Thishigh-speeddatatransferisrealizedbythe2bitsprefetch-pipelinedarchitecture.
Datastrobe(DQS)bothforreadandwriteareavailableforhighspeedandreliabledatabusdesign.
Bysettingextendedmoderesistor,theon-chipDelayLockedLoop(DLL)canbesetenableordisable.
Theyarepackagedinstandard66-pinplasticTSOP(II).
Features2.
0;BACKGROUND-COLOR:#4ae2f7">5Vpowersupply:VDDQ=2.
6V±0.
1V:VDD=2.
6V±0.
1VDatarate:400Mbps(max.
)DoubleDataRatearchitecture;twodatatransfersperclockcycleBi-directional,datastrobe(DQS)istransmitted/receivedwithdata,tobeusedincapturingdataatthereceiverDatainputs,outputs,andDMaresynchronizedwithDQS4internalbanksforconcurrentoperationDQSisedgealignedwithdataforREADs;centeralignedwithdataforWRITEsDifferentialclockinputs(CKand/CK)DLLalignsDQandDQStransitionswithCKtransitionsCommandsenteredoneachpositiveCKedge;dataanddatamaskreferencedtobothedgesofDQSDatamask(DM)forwritedataAutoprechargeoptionforeachburstaccess2.
0;BACKGROUND-COLOR:#4ae2f7">5V(SSTL_2compatible)I/OProgrammableburstlength(BL):2,4,8Programmable/CASlatency(CL):3Programmableoutputdriverstrength:normal/weakRefreshcycles:8192refreshcycles/64ms7.
8smaximumaverageperiodicrefreshinterval2variationsofrefreshAutorefreshSelfrefreshPinConfigurations/xxxindicatesactivelowsignal.
12340;BACKGROUND-COLOR:#4ae2f7">56789101112131410;BACKGROUND-COLOR:#4ae2f7">516171819202122232420;BACKGROUND-COLOR:#4ae2f7">526272829303132336660;BACKGROUND-COLOR:#4ae2f7">564636261600;BACKGROUND-COLOR:#4ae2f7">590;BACKGROUND-COLOR:#4ae2f7">580;BACKGROUND-COLOR:#4ae2f7">570;BACKGROUND-COLOR:#4ae2f7">560;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">540;BACKGROUND-COLOR:#4ae2f7">530;BACKGROUND-COLOR:#4ae2f7">520;BACKGROUND-COLOR:#4ae2f7">510;BACKGROUND-COLOR:#4ae2f7">504948474640;BACKGROUND-COLOR:#4ae2f7">544434241403938373630;BACKGROUND-COLOR:#4ae2f7">534(Topview)VDDDQ0VDDQNCDQ1VSSQNCDQ2VDDQNCDQ3VSSQNCNCVDDQNCNCVDDNCNC/WE/CAS/RAS/CSNCBA0BA1A10(AP)A0A1A2A3VDDVSSDQ7VSSQNCDQ6VDDQNCDQ0;BACKGROUND-COLOR:#4ae2f7">5VSSQNCDQ4VDDQNCNCVSSQDQSNCVREFVSSDM/CKCKCKENCA12A11A9A8A7A6A0;BACKGROUND-COLOR:#4ae2f7">5A4VSSAddressinputBankselectaddressData-input/outputInputandoutputdatastrobeChipselectRowaddressstrobecommandColumnaddressstrobecommandWriteenableInputmaskClockinputDifferentialclockinputClockenableInputreferencevoltagePowerforinternalcircuitGroundforinternalcircuitPowerforDQcircuitGroundforDQcircuitNoconnectionA0toA12BA0,BA1DQ0toDQ7DQS/CS/RAS/CAS/WEDMCK/CKCKEVREFVDDVSSVDDQVSSQNC66-pinPlasticTSOP(II)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)2OrderingInformationPartnumberMaskversionOrganization(words*bits)InternalbanksDatarateMbps(max.
)JEDECspeedbin(CL-tRCD-tRP)PackageEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTA-0;BACKGROUND-COLOR:#4ae2f7">5CK32M*84400DDR400C(3-4-4)66-pinPlasticTSOP(II)PartNumberElpidaMemoryDensity/Bank20;BACKGROUND-COLOR:#4ae2f7">5:20;BACKGROUND-COLOR:#4ae2f7">56M/4-bankBitOrganization8:x8Voltage,InterfaceA:2.
0;BACKGROUND-COLOR:#4ae2f7">5V,SSTL_2DieRev.
PackageTA:TSOP(II)Speed0;BACKGROUND-COLOR:#4ae2f7">5C:DDR400C(3-4-4)ProductCodeD:DDRSDRAMTypeD:MonolithicDeviceEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTA-0;BACKGROUND-COLOR:#4ae2f7">5CEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)3CONTENTSDescription.
1Features.
1PinConfigurations1OrderingInformation.
2PartNumber2ElectricalSpecifications.
4BlockDiagram10PinFunction.
11CommandOperation13SimplifiedStateDiagram.
21OperationoftheDDRSDRAM.
22TimingWaveforms.
40PackageDrawing46RecommendedSolderingConditions.
47EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)4ElectricalSpecificationsAllvoltagesarereferencedtoVSS(GND).
Afterpowerup,waitmorethan200sandthen,executepoweronsequenceandCBR(Auto)refreshbeforeproperdeviceoperationisachieved.
AbsoluteMaximumRatingsParameterSymbolRatingUnitNoteVoltageonanypinrelativetoVSSVT–1.
0to+3.
6VSupplyvoltagerelativetoVSSVDD–1.
0to+3.
6VShortcircuitoutputcurrent000000;BACKGROUND-COLOR:#ffff00">IOS0;BACKGROUND-COLOR:#4ae2f7">50mAPowerdissipationPD1.
0WOperatingtemperatureTA0to+70°CStoragetemperatureTstg–0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5to+120;BACKGROUND-COLOR:#4ae2f7">5°CCautionExposingthedevicetostressabovethoselistedinAbsoluteMaximumRatingscouldcausepermanentdamage.
Thedeviceisnotmeanttobeoperatedunderconditionsoutsidethelimitsdescribedintheoperationalsectionofthisspecification.
ExposuretoAbsoluteMaximumRatingconditionsforextendedperiodsmayaffectdevicereliability.
RecommendedOperatingConditions(TA=0to70°°°°C)ParameterSymbolMinTypMaxUnitNotesSupplyvoltageVDD,VDDQ2.
0;BACKGROUND-COLOR:#4ae2f7">52.
62.
7V1VSS,VSSQ000VInputreferencevoltageVREF0.
49*VDDQ0.
0;BACKGROUND-COLOR:#4ae2f7">50*VDDQ0.
0;BACKGROUND-COLOR:#4ae2f7">51*VDDQVTerminationvoltageVTTVREF–0.
04VREFVREF+0.
04VInputhighvoltageVIH(DC)VREF+0.
10;BACKGROUND-COLOR:#4ae2f7">5—VDDQ+0.
3V2InputlowvoltageVIL(DC)–0.
3—VREF–0.
10;BACKGROUND-COLOR:#4ae2f7">5V3Inputvoltagelevel,CKand/CKinputsVIN(DC)–0.
3—VDDQ+0.
3V4Inputdifferentialcrosspointvoltage,CKand/CKinputsVIX(DC)0.
0;BACKGROUND-COLOR:#4ae2f7">5*VDDQ0.
2V0.
0;BACKGROUND-COLOR:#4ae2f7">5*VDDQ0.
0;BACKGROUND-COLOR:#4ae2f7">5*VDDQ+0.
2VVInputdifferentialvoltage,CKand/CKinputsVID(DC)0.
36—VDDQ+0.
6V0;BACKGROUND-COLOR:#4ae2f7">5,6Notes:1.
VDDQmustbelowerthanorequaltoVDD.
2.
VIHisallowedtoexceedVDDupto3.
6Vfortheperiodshorterthanorequalto0;BACKGROUND-COLOR:#4ae2f7">5ns.
3.
VILisallowedtooutreachbelowVSSdownto–1.
0Vfortheperiodshorterthanorequalto0;BACKGROUND-COLOR:#4ae2f7">5ns.
4.
VIN(DC)specifiestheallowableDCexecutionofeachdifferentialinput.
0;BACKGROUND-COLOR:#4ae2f7">5.
VID(DC)specifiestheinputdifferentialvoltagerequiredforswitching.
6.
VIH(CK)minassumedoverVREF+0.
18V,VIL(CK)maxassumedunderVREF–0.
18Vifmeasurement.
EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)0;BACKGROUND-COLOR:#4ae2f7">5DCCharacteristics1(TA=0to+70°°°°C,VDD,VDDQ=2.
6V±0.
1V,VSS,VSSQ=0V)max.
ParameterSymbolGrade*8UnitTestconditionNotesOperatingcurrent(ACT-PRE)IDD0-0;BACKGROUND-COLOR:#4ae2f7">5C100mACKE≥VIH,tRC=tRC(min.
)1,2,9Operatingcurrent(ACT-READ-PRE)IDD1-0;BACKGROUND-COLOR:#4ae2f7">5C130mACKE≥VIH,BL=4,CL=3,tRC=tRC(min.
)1,2,0;BACKGROUND-COLOR:#4ae2f7">5IdlepowerdownstandbycurrentIDD2P-0;BACKGROUND-COLOR:#4ae2f7">5C3mACKE≤VIL4FloatingidlestandbycurrentIDD2F-0;BACKGROUND-COLOR:#4ae2f7">5C30mACKE≥VIH,/CS≥VIHDQ,DQS,DM=VREF4,0;BACKGROUND-COLOR:#4ae2f7">5QuietidlestandbycurrentIDD2Q-0;BACKGROUND-COLOR:#4ae2f7">5C20;BACKGROUND-COLOR:#4ae2f7">5mACKE≥VIH,/CS≥VIHDQ,DQS,DM=VREF4,10ActivepowerdownstandbycurrentIDD3P-0;BACKGROUND-COLOR:#4ae2f7">5C20mACKE≤VIL3ActivestandbycurrentIDD3N-0;BACKGROUND-COLOR:#4ae2f7">5C60mACKE≥VIH,/CS≥VIHtRAS=tRAS(max.
)3,0;BACKGROUND-COLOR:#4ae2f7">5,6Operatingcurrent(Burstreadoperation)IDD4R-0;BACKGROUND-COLOR:#4ae2f7">5C200mACKE≥VIH,BL=2,CL=31,2,0;BACKGROUND-COLOR:#4ae2f7">5,6Operatingcurrent(Burstwriteoperation)IDD4W-0;BACKGROUND-COLOR:#4ae2f7">5C210mACKE≥VIH,BL=2,CL=31,2,0;BACKGROUND-COLOR:#4ae2f7">5,6AutoRefreshcurrentIDD0;BACKGROUND-COLOR:#4ae2f7">5-0;BACKGROUND-COLOR:#4ae2f7">5C170mAtRFC=tRFC(min.
),Input≤VILor≥VIHSelfrefreshcurrentIDD6-0;BACKGROUND-COLOR:#4ae2f7">5C3mAInput≥VDD–0.
2VInput≤0.
2VOperatingcurrent(4banksinterleaving)IDD7A-0;BACKGROUND-COLOR:#4ae2f7">5C320mABL=40;BACKGROUND-COLOR:#4ae2f7">5,6,7Notes:1.
TheseIDDdataaremeasuredunderconditionthatDQpinsarenotconnected.
2.
Onebankoperation.
3.
Onebankactive.
4.
Allbanksidle.
0;BACKGROUND-COLOR:#4ae2f7">5.
Command/Addresstransitiononceperoneclockcycle.
6.
DQ,DMandDQStransitiontwiceperoneclockcycle.
7.
4banksactive.
OnlyonebankisrunningattRC=tRC(min.
)8.
TheIDDdataonthistablearemeasuredwithregardtotCK=tCK(min.
)ingeneral.
9.
Command/Addresstransitiononceeverytwoclockcycle.
10.
Command/Addressstableat≥VIHor≤VIL.
DCCharacteristics2(TA=0to+70°°°°C,VDD,VDDQ=2.
6V±0.
1V,VSS,VSSQ=0V)ParameterSymbolmin.
max.
UnitTestconditionNotesInputleakagecurrentILI–22AVDD≥VIN≥VSSOutputleakagecurrentILO–0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5AVDDQ≥VOUT≥VSSOutputhighcurrentIOH–10;BACKGROUND-COLOR:#4ae2f7">5.
2—mAVOUT=1.
90;BACKGROUND-COLOR:#4ae2f7">5VOutputlowcurrentIOL10;BACKGROUND-COLOR:#4ae2f7">5.
2—mAVOUT=0.
30;BACKGROUND-COLOR:#4ae2f7">5VEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)6PinCapacitance(TA=+20;BACKGROUND-COLOR:#4ae2f7">5°C,VDD,VDDQ=2.
6V±0.
1V)ParameterSymbolPinsmin.
Typmax.
UnitNotesInputcapacitanceCI1CK,/CK2.
0—3.
0pF1CI2Allotherinputpins2.
0—3.
0pF1DeltainputcapacitanceCdi1CK,/CK——0.
20;BACKGROUND-COLOR:#4ae2f7">5pF1Cdi2Allotherinput-onlypins——0.
0;BACKGROUND-COLOR:#4ae2f7">5pF1Datainput/outputcapacitanceCI/ODQ,DM,DQS4.
0—0;BACKGROUND-COLOR:#4ae2f7">5pF1,2,Deltainput/outputcapacitanceCdioDQ,DM,DQS——0.
0;BACKGROUND-COLOR:#4ae2f7">5pF1Notes:1.
Theseparametersaremeasuredonconditions:f=100MHz,VOUT=VDDQ/2,VOUT=0.
2V,TA=+20;BACKGROUND-COLOR:#4ae2f7">5°C.
2.
DOUTcircuitsaredisabled.
ACCharacteristics(TA=0to+70°°°°C,VDD,VDDQ=2.
6V±0.
1V,VSS,VSSQ=0V)-0;BACKGROUND-COLOR:#4ae2f7">5CParameterSymbolmin.
max.
UnitNotesClockcycletimetCK0;BACKGROUND-COLOR:#4ae2f7">58ns10CKhigh-levelwidthtCH0.
40;BACKGROUND-COLOR:#4ae2f7">50.
0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5tCKCKlow-levelwidthtCL0.
40;BACKGROUND-COLOR:#4ae2f7">50.
0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5tCKCKhalfperiodtHPmin(tCH,tCL)—tCKDQoutputaccesstimefromCK,/CKtAC–0.
70.
7ns2,11DQSoutputaccesstimefromCK,/CKtDQSCK–0.
0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">50.
0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5ns2,11DQStoDQskewtDQSQ—0.
4ns3DQ/DQSoutputholdtimefromDQStQHtHP–tQHS—nsDataholdskewfactortQHS—0.
0;BACKGROUND-COLOR:#4ae2f7">5nsData-outhigh-impedancetimefromCK,/CKtHZ—0.
7ns0;BACKGROUND-COLOR:#4ae2f7">5,11Data-outlow-impedancetimefromCK,/CKtLZ–0.
70.
7ns6,11ReadpreambletRPRE0.
91.
1tCKReadpostambletRPST0.
40.
6tCKDQandDMinputsetuptimetDS0.
4—ns8DQandDMinputholdtimetDH0.
4—ns8DQandDMinputpulsewidthtDIPW1.
70;BACKGROUND-COLOR:#4ae2f7">5—ns7WritepreamblesetuptimetWPRES0—nsWritepreambletWPRE0.
20;BACKGROUND-COLOR:#4ae2f7">5—tCKWritepostambletWPST0.
40.
6tCK9WritecommandtofirstDQSlatchingtransitiontDQSS0.
721.
28tCKDQSfallingedgetoCKsetuptimetDSS0.
2—tCKDQSfallingedgeholdtimefromCKtDSH0.
2—tCKDQSinputhighpulsewidthtDQSH0.
30;BACKGROUND-COLOR:#4ae2f7">5—tCKDQSinputlowpulsewidthtDQSL0.
30;BACKGROUND-COLOR:#4ae2f7">5—tCKAddressandcontrolinputsetuptimetIS0.
6—ns8AddressandcontrolinputholdtimetIH0.
6—ns8AddressandcontrolinputpulsewidthtIPW2.
2—ns7ModeregistersetcommandcycletimetMRD2—tCKActivetoPrechargecommandperiodtRAS40120000nsEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)7-0;BACKGROUND-COLOR:#4ae2f7">5CParameterSymbolmin.
max.
UnitNotesActivetoActive/AutorefreshcommandperiodtRC60—nsAutorefreshtoActive/AutorefreshcommandperiodtRFC70—nsActivetoRead/WritedelaytRCD18—nsPrechargetoactivecommandperiodtRP18—nsActivetoAutoprechargedelaytRAPtRCDmin.
—nsActivetoactivecommandperiodtRRD10—nsWriterecoverytimetWR10;BACKGROUND-COLOR:#4ae2f7">5—nsAutoprechargewriterecoveryandprechargetimetDAL(tWR/tCK)+(tRP/tCK)—tCK13InternalwritetoReadcommanddelaytWTR2—tCKAverageperiodicrefreshintervaltREF—7.
8sNotes:1.
OnallACmeasurements,weassumethetestconditionsshowninthenextpage.
Fortimingparameterdefinitions,see'TimingWaveforms'section.
2.
ThisparameterdefinesthesignaltransitiondelayfromthecrosspointofCKand/CK.
ThesignaltransitionisdefinedtooccurwhenthesignallevelcrossingVTT.
3.
ThetimingreferencelevelisVTT.
4.
OutputvalidwindowisdefinedtobetheperiodbetweentwosuccessivetransitionofdataoutorDQS(read)signals.
ThesignaltransitionisdefinedtooccurwhenthesignallevelcrossingVTT.
0;BACKGROUND-COLOR:#4ae2f7">5.
tHZisdefinedasDOUTtransitiondelayfromLow-ZtoHigh-Zattheendofreadburstoperation.
ThetimingreferenceiscrosspointofCKand/CK.
ThisparameterisnotreferredtoaspecificDOUTvoltagelevel,butspecifywhenthedeviceoutputstopsdriving.
6.
tLZisdefinedasDOUTtransitiondelayfromHigh-ZtoLow-Zatthebeginningofreadoperation.
ThisparameterisnotreferredtoaspecificDOUTvoltagelevel,butspecifywhenthedeviceoutputbeginsdriving.
7.
InputvalidwindowsisdefinedtobetheperiodbetweentwosuccessivetransitionofdatainputorDQS(write)signals.
ThesignaltransitionisdefinedtooccurwhenthesignallevelcrossingVREF.
8.
ThetimingreferencelevelisVREF.
9.
ThetransitionfromLow-ZtoHigh-Zisdefinedtooccurwhenthedeviceoutputstopsdriving.
Aspecificreferencevoltagetojudgethistransitionisnotgiven.
10.
tCK(max.
)isdeterminedbythelockrangeoftheDLL.
Beyondthislockrange,theDLLoperationisnotassured.
11.
tCK=tCK(min)whentheseparametersaremeasured.
Otherwise,absoluteminimumvaluesofthesevaluesare10%oftCK.
12.
VDDisassumedtobe2.
6V±0.
1V.
VDDpowersupplyvariationpercycleexpectedtobelessthan0.
4V/400cycle.
13.
tDAL=(tWR/tCK)+(tRP/tCK)Foreachofthetermsabove,ifnotalreadyaninteger,roundtothenexthighestinteger.
Example:For–0;BACKGROUND-COLOR:#4ae2f7">5CSpeedatCL=3,tCK=0;BACKGROUND-COLOR:#4ae2f7">5ns,tWR=10;BACKGROUND-COLOR:#4ae2f7">5nsandtRP=18ns,tDAL=(10;BACKGROUND-COLOR:#4ae2f7">5ns/0;BACKGROUND-COLOR:#4ae2f7">5ns)+(18ns/0;BACKGROUND-COLOR:#4ae2f7">5ns)=(3)+(4)tDAL=7clocksEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)8TestConditionsParameterSymbolValueUnitInputreferencevoltageVREFVDDQ/2VTerminationvoltageVTTVREFVInputhighvoltageVIH(AC)VREF+0.
31VInputlowvoltageVIL(AC)VREF0.
31VInputdifferentialvoltage,CKand/CKinputsVID(AC)0.
62VInputdifferentialcrosspointvoltage,CKand/CKinputsVIX(AC)VREFVInputsignalslewrateSLEW1V/nsVTTVREF/CKCKVREFVSSSLEW=(VIH(AC)–VIL(AC))/tMeasurementpointVIHVILVDDVDDVSSDQRT=0;BACKGROUND-COLOR:#4ae2f7">50CL=30pFVIXttCLtCKtCHVIDInputWaveformsandOutputLoadEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)9TimingParameterMeasuredinClockCycleNumberofclockcycletCK0;BACKGROUND-COLOR:#4ae2f7">5nsParameterSymbolmin.
max.
UnitWritetopre-chargecommanddelay(samebank)tWPD4+BL/2tCKReadtopre-chargecommanddelay(samebank)tRPDBL/2tCKWritetoreadcommanddelay(toinputalldata)tWRD2+BL/2tCKBurststopcommandtowritecommanddelaytBSTW3tCKBurststopcommandtoDQHigh-ZtBSTZ33tCKReadcommandtowritecommanddelay(tooutputalldata)tRWD3+BL/2tCKPre-chargecommandtoHigh-ZtHZP33tCKWritecommandtodatainlatencytWCD11tCKWriterecoverytWR3tCKDMtodatainlatencytDMD00tCKModeregistersetcommandcycletimetMRD2tCKSelfrefreshexittonon-readcommandtSNR10;BACKGROUND-COLOR:#4ae2f7">5tCKSelfrefreshexittoreadcommandtSRD200tCKPowerdownentrytPDEN11tCKPowerdownexittocommandinputtPDEX1tCKEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)10BlockDiagramA0toA12,BA0,BA1/CS/RAS/CAS/WECommanddecoderInput&OutputbufferLatchcircuitDatacontrolcircuitColumndecoderRowdecoderMemorycellarrayBank0Senseamp.
Bank1Bank2Bank3ControllogicColumnaddressbufferandburstcounterRowaddressbufferandrefreshcounterModeregisterClockgeneratorDQCK/CKCKEDQSDMDLLCK,/CKEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)11PinFunctionCK,/CK(inputpins)TheCKandthe/CKarethemasterclockinputs.
AllinputsexceptDM,DQSandDQsarereferredtothecrosspointoftheCKrisingedgeandthe/CKfallingedge.
Whenareadoperation,DQSandDQsarereferredtothecrosspointoftheCKandthe/CK.
Whenawriteoperation,DQSandDQsarereferredtothecrosspointoftheDQSandtheVREFlevel.
DQSforwriteoperationisreferredtothecrosspointoftheCKandthe/CK.
CKisthemasterclockinputtothispin.
TheotherinputsignalsarereferredatCKrisingedge.
/CS(inputpin)When/CSisLow,commandsanddatacanbeinput.
When/CSisHigh,allinputsareignored.
However,internaloperations(bankactive,burstoperations,etc.
)areheld.
/RAS,/CAS,and/WE(inputpins)Thesepinsdefineoperatingcommands(read,write,etc.
)dependingonthecombinationsoftheirvoltagelevels.
See"Commandoperation".
A0toA12(inputpins)Rowaddress(AX0toAX12)isdeterminedbytheA0totheA12levelatthecrosspointoftheCKrisingedgeandthe/CKfallingedgeinabankactivecommandcycle.
Columnaddress(See"AddressPinsTable")isloadedviatheA0totheA9,andA11atthecrosspointoftheCKrisingedgeandthe/CKfallingedgeinareadorawritecommandcycle.
Thiscolumnaddressbecomesthestartingaddressofaburstoperation.
[AddressPinsTable]Address(A0toA12)PartnumberRowaddressColumnaddressEDD20;BACKGROUND-COLOR:#4ae2f7">508AKAX0toAX12AY0toAY9A10(AP)(inputpin)A10definestheprechargemodewhenaprechargecommand,areadcommandorawritecommandisissued.
IfA10=Highwhenaprechargecommandisissued,allbanksareprecharged.
IfA10=Lowwhenaprechargecommandisissued,onlythebankthatisselectedbyBA1/BA0isprecharged.
IfA10=Highwhenreadorwritecommand,auto-prechargefunctionisenabled.
WhileA10=Low,auto-prechargefunctionisdisabled.
BA0andBA1(inputpins)BA0,BA1arebankselectsignals(BA).
Thememoryarrayisdividedintobank0,bank1,bank2andbank3.
(SeeBankSelectSignalTable)[BankSelectSignalTable]BA0BA1Bank0LLBank1HLBank2LHBank3HHRemark:H:VIH.
L:VIL.
EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)12CKE(inputpin)ThispindetermineswhetherornotthenextCKisvalid.
IfCKEisHigh,thenextCKrisingedgeisvalid.
IfCKEisLow.
CKEcontrolspowerdownandself-refresh.
Thepowerdownandtheself-refreshcommandsareenteredwhentheCKEisdrivenLowandexitedwhenitresumestoHigh.
CKEmustbemaintainedhighthroughoutreadorwriteaccess.
TheCKElevelmustbekeptfor1CKcycleatleast,thatis,ifCKEchangesatthecrosspointoftheCKrisingedgeandthe/CKfallingedgewithpropersetuptimetIS,bythenextCKrisingedgeCKElevelmustbekeptwithproperholdtimetIH.
DM(inputpin)DMisthereferencesignalofthedatainputmaskfunction.
DMissampledatthecrosspointofDQSandVREF.
DQ0toDQ7(input/outputpins)Dataisinputtoandoutputfromthesepins.
DQS(inputandoutputpin):DQSprovidesthereaddatastrobe(asoutput)andthewritedatastrobe(asinput).
VDD,VSS,VDDQ,VSSQ(Powersupply)VDDandVSSarepowersupplypinsforinternalcircuits.
VDDQandVSSQarepowersupplypinsfortheoutputbuffers.
EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)13CommandOperationCommandTruthTableDDRSDRAMrecognizethefollowingcommandsspecifiedbythe/CS,/RAS,/CAS,/WEandaddresspins.
Allothercombinationsthanthoseinthetablebelowareillegal.
CKECommandSymboln–1n/CS/RAS/CAS/WEBA1BA0APAddressIgnorecommandDESLHHHNooperationNOPHHLHHH****BurststopinreadcommandBSTHHLHHL****ColumnaddressandreadcommandREADHHLHLHVVLVReadwithauto-prechargeREADAHHLHLHVVHVColumnaddressandwritecommandWRITHHLHLLVVLVWritewithauto-prechargeWRITAHHLHLLVVHVRowaddressstrobeandbankactiveACTHHLLHHVVVVPrechargeselectbankPREHHLLHLVVL*PrechargeallbankPALLHHLLHL**H*RefreshREFHHLLLH****SELFHLLLLH****ModeregistersetMRSHHLLLLLLLVEMRSHHLLLLLHLVRemark:H:VIH.
L:VIL.
*:VIHorVILV:ValidaddressinputNote:TheCKElevelmustbekeptfor1CKcycleatleast.
Ignorecommand[DESL]When/CSisHighatthecrosspointoftheCKrisingedgeandtheVREFlevel,everyinputareneglectedandinternalstatusisheld.
Nooperation[NOP]AslongasthiscommandisinputatthecrosspointoftheCKrisingedgeandtheVREFlevel,addressanddatainputareneglectedandinternalstatusisheld.
Burststopinreadoperation[BST]Thiscommandstopsaburstreadoperation,whichisnotapplicableforaburstwriteoperation.
Columnaddressstrobeandreadcommand[READ]Thiscommandstartsareadoperation.
Thestartaddressoftheburstreadisdeterminedbythecolumnaddress(See"AddressPinsTable"inPinFunction)andthebankselectaddress.
Afterthecompletionofthereadoperation,theoutputbufferbecomesHigh-Z.
Readwithauto-precharge[READA]Thiscommandstartsareadoperation.
Aftercompletionofthereadoperation,prechargeisautomaticallyexecuted.
Columnaddressstrobeandwritecommand[WRIT]Thiscommandstartsawriteoperation.
Thestartaddressoftheburstwriteisdeterminedbythecolumnaddress(See"AddressPinsTable"inPinFunction)andthebankselectaddress.
Writewithauto-precharge[WRITA]Thiscommandstartsawriteoperation.
Aftercompletionofthewriteoperation,prechargeisautomaticallyexecuted.
EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)14Rowaddressstrobeandbankactivate[ACT]ThiscommandactivatesthebankthatisselectedbyBA0,BA1anddeterminestherowaddress(AX0toAX12).
(SeeBankSelectSignalTable)Prechargeselectedbank[PRE]ThiscommandstartsprechargeoperationforthebankselectedbyBA0,BA1.
(SeeBankSelectSignalTable)[BankSelectSignalTable]BA0BA1Bank0LLBank1HLBank2LHBank3HHRemark:H:VIH.
L:VIL.
Prechargeallbanks[PALL]Thiscommandstartsaprechargeoperationforallbanks.
Refresh[REF/SELF]Thiscommandstartsarefreshoperation.
Therearetwotypesofrefreshoperation,oneisauto-refresh,andanotherisself-refresh.
Fordetails,refertotheCKEtruthtablesection.
Moderegisterset/Extendedmoderegisterset[MRS/EMRS]TheDDRSDRAMhasthetwomoderegisters,themoderegisterandtheextendedmoderegister,todefineshowitworks.
Thebothmoderegistersaresetthroughtheaddresspins(theA0totheA12,BA0toBA1)inthemoderegistersetcycle.
Fordetails,referto"Moderegisterandextendedmoderegisterset".
CKETruthTableCKECurrentstateCommandn–1n/CS/RAS/CAS/WEAddressNotesIdleAuto-refreshcommand(REF)HHLLLH*2IdleSelf-refreshentry(SELF)HLLLLH*2IdlePowerdownentry(PDEN)HLLHHH*HLH****SelfrefreshSelfrefreshexit(SELFX)LHLHHH*LHH****PowerdownPowerdownexit(PDEX)LHLHHH*LHH****Remark:H:VIH.
L:VIL.
*:VIHorVIL.
Notes:1.
AllthebanksmustbeinIDLEbeforeexecutingthiscommand.
2.
TheCKElevelmustbekeptfor1CKcycleatleast.
EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)10;BACKGROUND-COLOR:#4ae2f7">5FunctionTruthTableThefollowingtablesshowtheoperationsthatareperformedwheneachcommandisissuedineachstateoftheDDRSDRAM.
FunctionTruthTable(1)Currentstate/CS/RAS/CAS/WEAddressCommandOperationNextstatePrecharging*1H****DESLNOPldleLHHH*NOPNOPldleLHHL*BSTILLEGAL*11—LHLHBA,CA,A10READ/READAILLEGAL*11—LHLLBA,CA,A10WRIT/WRITAILLEGAL*11—LLHHBA,RAACTILLEGAL*11—LLHLBA,A10PRE,PALLNOPldleLLL**ILLEGAL—Idle*2H****DESLNOPldleLHHH*NOPNOPldleLHHL*BSTILLEGAL*11—LHLHBA,CA,A10READ/READAILLEGAL*11—LHLLBA,CA,A10WRIT/WRITAILLEGAL*11—LLHHBA,RAACTActivatingActiveLLHLBA,A10PRE,PALLNOPldleLLLH*REF,SELFRefresh/Selfrefresh*12ldle/SelfrefreshLLLLMODEMRSModeregisterset*12ldleRefresh(auto-refresh)*3H****DESLNOPldleLHHH*NOPNOPldleLHHL*BSTILLEGAL—LHL**ILLEGAL—LL***ILLEGAL—EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)16FunctionTruthTable(2)Currentstate/CS/RAS/CAS/WEAddressCommandOperationNextstateActivating*4H****DESLNOPActiveLHHH*NOPNOPActiveLHHL*BSTILLEGAL*11—LHLHBA,CA,A10READ/READAILLEGAL*11—LHLLBA,CA,A10WRIT/WRITAILLEGAL*11—LLHHBA,RAACTILLEGAL*11—LLHLBA,A10PRE,PALLILLEGAL*11—LLL**ILLEGAL—Active*0;BACKGROUND-COLOR:#4ae2f7">5H****DESLNOPActiveLHHH*NOPNOPActiveLHHL*BSTILLEGALActiveLHLHBA,CA,A10READ/READAStartingreadoperationRead/READALHLLBA,CA,A10WRIT/WRITAStartingwriteoperationWriterecovering/prechargingLLHHBA,RAACTILLEGAL*11—LLHLBA,A10PRE,PALLPre-chargeIdleLLL**ILLEGAL—Read*6H****DESLNOPActiveLHHH*NOPNOPActiveLHHL*BSTBSTActiveLHLHBA,CA,A10READ/READAInterruptingburstreadoperationtostartnewreadActiveLHLLBA,CA,A10WRIT/WRITAILLEGAL*13—LLHHBA,RAACTILLEGAL*11—LLHLBA,A10PRE,PALLInterruptingburstreadoperationtostartpre-chargePrechargingLLL**ILLEGAL—EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)17FunctionTruthTable(3)Currentstate/CS/RAS/CAS/WEAddressCommandOperationNextstateReadwithauto-pre-charge*7H****DESLNOPPrechargingLHHH*NOPNOPPrechargingLHHL*BSTILLEGAL—LHLHBA,CA,A10READ/READAILLEGAL*14—LHLLBA,CA,A10WRIT/WRITAILLEGAL*14—LLHHBA,RAACTILLEGAL*11,14—LLHLBA,A10PRE,PALLILLEGAL*11,14—LLL**ILLEGAL—Write*8H****DESLNOPWriterecoveringLHHH*NOPNOPWriterecoveringLHHL*BSTILLEGAL—LHLHBA,CA,A10READ/READAInterruptingburstwriteoperationtostartreadoperation.
Read/ReadALHLLBA,CA,A10WRIT/WRITAInterruptingburstwriteoperationtostartnewwriteoperation.
Write/WriteALLHHBA,RAACTILLEGAL*11—LLHLBA,A10PRE,PALLInterruptingwriteoperationtostartpre-charge.
IdleLLL**ILLEGAL—Writerecovering*9H****DESLNOPActiveLHHH*NOPNOPActiveLHHL*BSTILLEGAL—LHLHBA,CA,A10READ/READAStartingreadoperation.
Read/ReadALHLLBA,CA,A10WRIT/WRITAStartingnewwriteoperation.
Write/WriteALLHHBA,RAACTILLEGAL*11—LLHLBA,A10PRE/PALLILLEGAL*11—LLL**ILLEGAL—FunctionTruthTable(4)Currentstate/CS/RAS/CAS/WEAddressCommandOperationNextstateWritewithauto-pre-charge*10H****DESLNOPPrechargingLHHH*NOPNOPPrechargingLHHL*BSTILLEGAL—LHLHBA,CA,A10READ/READAILLEGAL*14—LHLLBA,CA,A10WRIT/WRITAILLEGAL*14—LLHHBA,RAACTILLEGAL*11,14—LLHLBA,A10PRE,PALLILLEGAL*11,14—LLL**ILLEGAL—Remark:H:VIH.
L:VIL.
*:VIHorVILEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)18Notes:1.
TheDDRSDRAMisin"Precharging"statefortRPafterprechargecommandisissued.
2.
TheDDRSDRAMreaches"IDLE"statetRPafterprechargecommandisissued.
3.
TheDDRSDRAMisin"Refresh"statefortRFCafterauto-refreshcommandisissued.
4.
TheDDRSDRAMisin"Activating"statefortRCDafterACTcommandisissued.
0;BACKGROUND-COLOR:#4ae2f7">5.
TheDDRSDRAMisin"Active"stateafter"Activating"iscompleted.
6.
TheDDRSDRAMisin"READ"stateuntilburstdatahavebeenoutputandDQoutputcircuitsareturnedoff.
7.
TheDDRSDRAMisin"READwithauto-precharge"fromREADAcommanduntilburstdatahasbeenoutputandDQoutputcircuitsareturnedoff.
8.
TheDDRSDRAMisin"WRITE"statefromWRITcommandtothelastburstdataareinput.
9.
TheDDRSDRAMisin"Writerecovering"fortWRafterthelastdataareinput.
10.
TheDDRSDRAMisin"Writewithauto-precharge"untiltWRafterthelastdatahasbeeninput.
11.
Thiscommandmaybeissuedforotherbanks,dependingonthestateofthebanks.
12.
Allbanksmustbein"IDLE".
13.
Beforeexecutingawritecommandtostoptheprecedingburstreadoperation,BSTcommandmustbeissued.
14.
TheDDRSDRAMsupportstheconcurrentauto-prechargefeature,areadwithauto-prechargeenabled,orawritewithauto-prechargeenabled,maybefollowedbyanycolumncommandtootherbanks,aslongasthatcommanddoesnotinterruptthereadorwritedatatransfer,andallotherrelatedlimitationsapply.
(E.
g.
ConflictbetweenREADdataandWRITEdatamustbeavoided.
)Theminimumdelayfromareadorwritecommandwithautoprechargeenabled,toacommandtoadifferentbank,issummarizedbelow.
FromcommandTocommand(differentbank,non-interruptingcommand)Minimumdelay(ConcurrentAPsupported)UnitsReadw/APReadorReadw/APBL/2tCKWriteorWritew/APCL(roundedup)+(BL/2)tCKPrechargeorActivate1tCKWritew/APReadorReadw/AP1+(BL/2)+tWTRtCKWriteorWritew/APBL/2tCKPrechargeorActivate1tCKEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)19CommandTruthTableforCKECurrentStateCKEn–1n/CS/RAS/CAS/WEAddressOperationNotesSelfrefreshHINVALID,CK(n-1)wouldexitselfrefreshLHH****SelfrefreshrecoveryLHLHH**SelfrefreshrecoveryLHLHL**ILLEGALLHLL***ILLEGALLLMaintainselfrefreshSelfrefreshrecoveryHHH****IdleaftertRCHHLHH**IdleaftertRCHHLHL**ILLEGALHHLL***ILLEGALHLH****ILLEGALHLLHH**ILLEGALHLLHL**ILLEGALHLLL***ILLEGALPowerdownHINVALID,CK(n–1)wouldexitpowerdownLHH****EXITpowerdown→IdleLHLHHH*LLMaintainpowerdownmodeAllbanksidleHHH***RefertooperationsinFunctionTruthTableHHLH**RefertooperationsinFunctionTruthTableHHLLH*RefertooperationsinFunctionTruthTableHHLLLH*CBR(auto)refreshHHLLLLOPCODERefertooperationsinFunctionTruthTableHLH***RefertooperationsinFunctionTruthTableHLLH**RefertooperationsinFunctionTruthTableHLLLH*RefertooperationsinFunctionTruthTableHLLLLH*Selfrefresh1HLLLLLOPCODERefertooperationsinFunctionTruthTableLPowerdown1RowactiveHRefertooperationsinFunctionTruthTableLPowerdown1Remark:H:VIH.
L:VIL.
*:VIHorVILNote:Selfrefreshcanbeenteredonlyfromtheallbanksidlestate.
Powerdowncanbeenteredonlyfromallbanksidleorrowactivestate.
EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)20Auto-refreshcommand[REF]Thiscommandexecutesauto-refresh.
ThebanksandtheROWaddressestoberefreshedareinternallydeterminedbytheinternalrefreshcontroller.
Theaveragerefreshcycleis7.
8s.
TheoutputbufferbecomesHigh-Zafterauto-refreshstart.
Prechargehasbeencompletedautomaticallyaftertheauto-refresh.
TheACTorMRScommandcanbeissuedtRFCafterthelastauto-refreshcommand.
Self-refreshentry[SELF]Thiscommandstartsself-refresh.
Theself-refreshoperationcontinuesaslongasCKEisheldLow.
Duringtheself-refreshoperation,allROWaddressesarerepeatedrefreshingbytheinternalrefreshcontroller.
Aself-refreshisterminatedbyaself-refreshexitcommand.
Powerdownmodeentry[PDEN]tPDEN(=1cycle)afterthecyclewhen[PDEN]isissued.
TheDDRSDRAMentersintopower-downmode.
Inpowerdownmode,powerconsumptionissuppressedbydeactivatingtheinputinitialcircuit.
PowerdownmodecontinueswhileCKEisheldLow.
Nointernalrefreshoperationoccursduringthepowerdownmode.
[PDEN]donotdisableDLL.
Self-refreshexit[SELFX]Thiscommandisexecutedtoexitfromself-refreshmode.
Toissuenon-readcommands,tSNRhastobesatisfied.
((tSNR=)10;BACKGROUND-COLOR:#4ae2f7">5cyclesfortCK=0;BACKGROUND-COLOR:#4ae2f7">5.
0nsafter[SELFX])Toissuereadcommand,tSRDhastobesatisfiedtoadjustDOUTtimingbyDLL.
(200cyclesafter[SELFX])Aftertheexit,inputauto-refreshcommandwithin7.
8s.
Powerdownexit[PDEX]TheDDRSDRAMcanexitfrompowerdownmodetPDEX(1cyclemin.
)afterthecyclewhen[PDEX]isissued.
EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)21SimplifiedStateDiagramPRECHARGEROWACTIVEIDLEIDLEPOWERDOWNAUTOREFRESHSELFREFRESHMODEREGISTERSETACTIVEPOWERDOWNPOWERONWRITEAREADASRENTRYSREXITMRSREFRESHCKECKE_CKECKE_ACTIVEWRITEREADBSTWRITEWITHAPREADWITHAPPOWERAPPLIEDPRECHARGEAPREADWRITEWITHAPREADWITHREADWITHAPPRECHARGEPRECHARGEPRECHARGE*1READReadWRITEWriteAutomatictransitionaftercompletionofcommand.
Transitionresultingfromcommandinput.
Note:1.
Aftertheauto-refreshoperation,prechargeoperationisperformedautomaticallyandentertheIDLEstate.
EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)22OperationoftheDDRSDRAMPower-upSequenceThefollowingsequenceisrecommendedforPower-up.
(1)ApplypowerandattempttomaintainCKEatanLVCMOSlowstate(allotherinputsmaybeundefined).
ApplyVDDbeforeoratthesametimeasVDDQ.
ApplyVDDQbeforeoratthesametimeasVTTandVREF.
(2)Startclockandmaintainstableconditionforaminimumof200s.
(3)Aftertheminimum200sofstablepowerandclock(CK,/CK),applyNOPandtakeCKEhigh.
(4)Issueprechargeallcommandforthedevice.
(0;BACKGROUND-COLOR:#4ae2f7">5)IssueEMRStoenableDLL.
(6)Issueamoderegistersetcommand(MRS)for"DLLreset"withbitA8settohigh(Anadditional200cyclesofclockinputisrequiredtolocktheDLLaftereveryDLLreset).
(7)Issueprechargeallcommandforthedevice.
(8)Issue2ormoreauto-refreshcommands.
(9)Issueamoderegistersetcommandtoinitializedeviceoperation.
CommandEMRSPALLMRSREF2cycles(min.
)2cycles(min.
)200cycles(min)2cycles(min.
)2cycles(min.
)tRPtRFCtRFCPALLMRSREFREFAnycommandDLLenableDLLreset/CKCKPower-upSequenceafterCKEGoesHighModeRegisterandExtendedModeRegisterSetTherearetwomoderegisters,themoderegisterandtheextendedmoderegistersoastodefinetheoperatingmode.
ParametersaresettoboththroughtheA0totheA12andBA0,BA1pinsbythemoderegistersetcommand[MRS]ortheextendedmoderegistersetcommand[EMRS].
ThemoderegisterandtheextendedmoderegisteraresetbyinputtingsignalviatheA0totheA12andBA0,BA1duringmoderegistersetcycles.
BA0andBA1determinewhichoneofthemoderegisterortheextendedmoderegisterareset.
Priortoareadorawriteoperation,themoderegistermustbeset.
Remindthatnootherparametersareshowninthetablebellowareallowedtoinputtotheregisters.
A2A1A0BurstLength001201040118BT=0BT=1248A30Sequential1InterleaveBurstTypeA6A0;BACKGROUND-COLOR:#4ae2f7">5A4CASLatency0113A9A8A7A6A0;BACKGROUND-COLOR:#4ae2f7">5A4A3A2A1A000000DRLMODEBTBLA80No1YesDLLResetA11A10A12BA10BA00MRSModeRegisterSet[MRS](BA0=0,BA1=0)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)23A00DLLEnable1DLLDisableDLLControlA9A8A7A6A0;BACKGROUND-COLOR:#4ae2f7">5A4A3A2A1A000000000000DLL0A11A10A12BA10BA01EMRSA10Normal1WeakDriveStrengthExtendedModeRegisterSet[EMRS](BA0=1,BA1=0)BurstOperationThebursttype(BT)andthefirstthreebitsofthecolumnaddressdeterminetheorderofadataout.
A2A1A0Addressing(decimal)000001010011111InterleaveSequence100110101StartingAd.
0,1,2,3,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,7,1,2,3,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,7,2,3,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,7,3,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,7,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,7,0;BACKGROUND-COLOR:#4ae2f7">5,6,7,6,7,7,0,0,1,0,1,2,0,1,2,3,0,1,2,3,4,0,1,2,3,4,0;BACKGROUND-COLOR:#4ae2f7">5,0,1,2,3,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,0,1,2,3,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,7,1,0,3,2,0;BACKGROUND-COLOR:#4ae2f7">5,4,7,2,3,0,1,6,7,3,2,1,0,7,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,7,0;BACKGROUND-COLOR:#4ae2f7">5,4,7,6,7,7,6,4,0;BACKGROUND-COLOR:#4ae2f7">5,6,0;BACKGROUND-COLOR:#4ae2f7">5,4,0,1,2,3,6,1,0,3,2,4,0;BACKGROUND-COLOR:#4ae2f7">5,2,3,0,1,6,0;BACKGROUND-COLOR:#4ae2f7">5,4,3,2,1,0,Burstlength=8A1A0Addressing(decimal)00011011InterleaveSequenceStartingAd.
0,1,2,3,1,2,3,0,2,3,0,1,3,0,1,2,0,1,2,3,1,0,3,2,2,3,0,1,3,2,1,0,Burstlength=4A0Addressing(decimal)01InterleaveSequenceStartingAd.
0,1,1,0,0,1,1,0,Burstlength=2EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)24Read/WriteOperationsBankactiveAreadorawriteoperationbeginswiththebankactivecommand[ACT].
Thebankactivecommanddeterminesabankaddressandarowaddress.
Forthebankandtherow,areadorawritecommandcanbeissuedtRCDaftertheACTisissued.
ReadoperationTheburstlength(BL),the/CASlatency(CL)andthebursttype(BT)ofthemoderegisterarereferredwhenareadcommandisissued.
Theburstlength(BL)determinesthelengthofasequentialoutputdatabythereadcommandthatcanbesetto2,4,or8.
Thestartingaddressoftheburstreadisdefinedbythecolumnaddress,thebankselectaddresswhichareloadedviatheA0toA12andBA0,BA1pinsinthecyclewhenthereadcommandisissued.
ThedataoutputtimingarecharacterizedbyCL3andtAC.
ThereadburststartCLtCK+tAC(ns)aftertheclockrisingedgewherethereadcommandarelatched.
TheDDRSDRAMoutputthedatastrobethroughDQSsimultaneouslywithdata.
tRPREpriortothefirstrisingedgeofthedatastrobe,theDQSaredrivenLowfromVTTlevel.
ThislowperiodofDQSisreferredasreadpreamble.
Theburstdataareoutputcoincidentallyatboththerisingandfallingedgeofthedatastrobe.
TheDQpinsbecomeHigh-Zinthenextcycleaftertheburstreadoperationcompleted.
tRPSTfromthelastfallingedgeofthedatastrobe,theDQSpinsbecomeHigh-Z.
ThislowperiodofDQSisreferredasreadpostamble.
out0out1out0out1out2out3out0out1out2out3out4out0;BACKGROUND-COLOR:#4ae2f7">5out6out7CK/CKAddressDQSDQBL=2BL=4BL=8CommandCL=3BL:Burstlengtht1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8tRCDtRPREtRPSTACTNOPNOPNOPREAD;;;;;RowColumnt9ReadOperation(BurstLength)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)20;BACKGROUND-COLOR:#4ae2f7">5CK/CKVTTVTTDQSDQCL=3Commandt0t0.
0;BACKGROUND-COLOR:#4ae2f7">5t1t1.
0;BACKGROUND-COLOR:#4ae2f7">5t2t2.
0;BACKGROUND-COLOR:#4ae2f7">5t3t3.
0;BACKGROUND-COLOR:#4ae2f7">5t4t4.
0;BACKGROUND-COLOR:#4ae2f7">5t0;BACKGROUND-COLOR:#4ae2f7">5t0;BACKGROUND-COLOR:#4ae2f7">5.
0;BACKGROUND-COLOR:#4ae2f7">5out0out1out2out3tRPSTtAC,tDQSCKREADNOPtRPREReadOperation(/CASLatency)WriteoperationTheburstlength(BL)andthebursttype(BT)ofthemoderegisterarereferredwhenawritecommandisissued.
Theburstlength(BL)determinesthelengthofasequentialdatainputbythewritecommandthatcanbesetto2,4,or8.
Thelatencyfromwritecommandtodatainputisfixedto1.
Thestartingaddressoftheburstreadisdefinedbythecolumnaddress,thebankselectaddresswhichareloadedviatheA0toA12,BA0toBA1pinsinthecyclewhenthewritecommandisissued.
DQSshouldbeinputasthestrobefortheinput-dataandDMaswellduringburstoperation.
tWPREpriortothefirstrisingedgeoftheDQSshouldbesettoLowandtWPSTafterthelastfallingedgeofthedatastrobecanbesettoHigh-Z.
TheleadinglowperiodofDQSisreferredaswritepreamble.
ThelastlowperiodofDQSisreferredaswritepostamble.
in1in0in1in2in3in0in1in2in3in4in0;BACKGROUND-COLOR:#4ae2f7">5in6in7CK/CKAddressDQSDQBL=2BL=4BL=8CommandBL:Burstlengtht1t0t2t3t3.
0;BACKGROUND-COLOR:#4ae2f7">5t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8in0ACTNOPNOPNOPWRITEtWPREtWPRESRowColumntRCDtWPSTWriteOperationEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)26BurstStopBurststopcommandduringburstreadTheburststop(BST)commandisusedtostopdataoutputduringaburstread.
TheBSTcommandstopstheburstreadandsetstheoutputbuffertoHigh-Z.
tBSTZ(=CL)cyclesafteraBSTcommandissued,theDQpinsbecomeHigh-Z.
TheBSTcommandisnotsupportedfortheburstwriteoperation.
Notethatbankaddressisnotreferredwhenthiscommandisexecuted.
CK/CKDQSDQCL=3Commandt0t0.
0;BACKGROUND-COLOR:#4ae2f7">5t1t1.
0;BACKGROUND-COLOR:#4ae2f7">5t2t2.
0;BACKGROUND-COLOR:#4ae2f7">5t3t3.
0;BACKGROUND-COLOR:#4ae2f7">5t4t4.
0;BACKGROUND-COLOR:#4ae2f7">5t0;BACKGROUND-COLOR:#4ae2f7">5t0;BACKGROUND-COLOR:#4ae2f7">5.
0;BACKGROUND-COLOR:#4ae2f7">5out0out1CL:/CASlatencyREADBSTNOPtBSTZ3cyclesBurstStopduringaReadOperationEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)27AutoPrechargeReadwithauto-prechargeTheprechargeisautomaticallyperformedaftercompletingareadoperation.
TheprechargestartstRPD(BL/2)cycleafterREADAcommandinput.
tRAPspecificationforREADAallowsareadcommandwithautoprechargetobeissuedtoabankthathasbeenactivated(opened)buthasnotyetsatisfiedthetRAS(min)specification.
Acolumncommandtotheotheractivebankcanbeissuedthenextcycleafterthelastdataoutput.
Readwithauto-prechargecommanddoesnotlimitrowcommandsexecutionforotherbank.
Referto'Functiontruthtable(3),(4)andrelatednote(Notes.
*14)'.
out0out1out2out3CK/CKDQCommandtRP(min)tRAP(min)=tRCD(min)ACTNote:Internalauto-prechargestartsatthetimingindicatedby"".
NOP2cycles(=BL/2)READAACTDQStAC,tDQSCKtRPDReadwithauto-prechargeWritewithauto-prechargeTheprechargeisautomaticallyperformedaftercompletingaburstwriteoperation.
Theprechargeoperationisstarted(BL/2+3)cyclesafterWRITAcommandissued.
Acolumncommandtotheotherbankscanbeissuedthenextcycleaftertheinternalprechargecommandissued.
Writewithauto-prechargecommanddoesnotlimitrowcommandsexecutionforotherbank.
Refertothe'ReadwithAuto-PrechargeEnabled,WritewithAuto-PrechargeEnabled'section.
Referto'Functiontruthtable(3),(4)andrelatednote(Notes.
*14)'.
;;in1in2in3in4CK/CKDQCommandDMtRAS(min)tRCD(min);;;tRPDQSACTWRITAACTBL/2+3cyclesNote:Internalauto-prechargestartsatthetimingindicatedby"".
BL=4NOPNOPBurstWrite(BL=4)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)28CommandIntervalsAReadcommandtotheconsecutiveReadcommandIntervalDestinationrowoftheconsecutivereadcommandBankaddressRowaddressStateOperation1.
SameSameACTIVETheconsecutivereadcanbeperformedafteranintervalofnolessthan1cycletointerrupttheprecedingreadoperation.
2.
SameDifferent—Prechargethebanktointerrupttheprecedingreadoperation.
tRPaftertheprechargecommand,issuetheACTcommand.
tRCDaftertheACTcommand,theconsecutivereadcommandcanbeissued.
See'Areadcommandtotheconsecutiveprechargeinterval'section.
3.
DifferentAnyACTIVETheconsecutivereadcanbeperformedafteranintervalofnolessthan1cycletointerrupttheprecedingreadoperation.
IDLEPrechargethebankwithoutinterruptingtheprecedingreadoperation.
tRPaftertheprechargecommand,issuetheACTcommand.
tRCDaftertheACTcommand,theconsecutivereadcommandcanbeissued.
;;;;;outA0outA1outB0outB1outB2outB3CK/CKAddressBADQDQSCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8Bank0Active;;;;;;CL=3BL=4Bank0NOPACTNOPREADRowColumnAREADColumnBColumn=AReadColumn=BReadColumn=ADoutColumn=BDoutt9READtoREADCommandInterval(sameROWaddressinthesamebank)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)29;;;;;;;outA0outA1outB0outB1outB2outB3CK/CKAddressBADQDQSCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8t9Bank0ActiveBank3ActiveBank0ReadBank3ReadBank0Dout;;;;;CL=3BL=4NOPACTNOPNOPRow0ACTREADRow1ColumnAREADColumnBColumn=AReadColumn=BReadBank3Doutt10READtoREADCommandInterval(differentbank)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)30AWritecommandtotheconsecutiveWritecommandIntervalDestinationrowoftheconsecutivewritecommandBankaddressRowaddressStateOperation1.
SameSameACTIVETheconsecutivewritecanbeperformedafteranintervalofnolessthan1cycletointerrupttheprecedingwriteoperation.
2.
SameDifferent—Prechargethebanktointerrupttheprecedingwriteoperation.
tRPaftertheprechargecommand,issuetheACTcommand.
tRCDaftertheACTcommand,theconsecutivewritecommandcanbeissued.
See'Awritecommandtotheconsecutiveprechargeinterval'section.
3.
DifferentAnyACTIVETheconsecutivewritecanbeperformedafteranintervalofnolessthan1cycletointerrupttheprecedingwriteoperation.
IDLEPrechargethebankwithoutinterruptingtheprecedingwriteoperation.
tRPaftertheprechargecommand,issuetheACTcommand.
tRCDaftertheACTcommand,theconsecutivewritecommandcanbeissued.
;;;;;inA0inA1inB0inB1inB2inB3CK/CKAddressBADQCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8Bank0Active;;;;;BL=4Bank0NOPDQSACTNOPWRITRowColumnAWRITColumnBColumn=AWriteColumn=BWriteWRITEtoWRITECommandInterval(sameROWaddressinthesamebank)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)31inA0inA1inB0inB1inB2inB3CK/CKAddressBADQCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8t9Bank0ActiveBank3ActiveBank0WriteBank3WriteBL=4Bank0,3NOPDQSACTNOPACTWRITRow0Row1ColumnAWRITColumnBWRITEtoWRITECommandInterval(differentbank)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)32AReadcommandtotheconsecutiveWritecommandintervalwiththeBSTcommandDestinationrowoftheconsecutivewritecommandBankaddressRowaddressStateOperation1.
SameSameACTIVEIssuetheBSTcommand.
tBSTW(≥tBSTZ)aftertheBSTcommand,theconsecutivewritecommandcanbeissued.
2.
SameDifferent—Prechargethebanktointerrupttheprecedingreadoperation.
tRPaftertheprechargecommand,issuetheACTcommand.
tRCDaftertheACTcommand,theconsecutivewritecommandcanbeissued.
See'Areadcommandtotheconsecutiveprechargeinterval'section.
3.
DifferentAnyACTIVEIssuetheBSTcommand.
tBSTW(≥tBSTZ)aftertheBSTcommand,theconsecutivewritecommandcanbeissued.
IDLEPrechargethebankindependentlyoftheprecedingreadoperation.
tRPaftertheprechargecommand,issuetheACTcommand.
tRCDaftertheACTcommand,theconsecutivewritecommandcanbeissued.
out0out1in0in1in2in3CK/CKDMDQCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8;;;;;;BL=4CL=3DQSOUTPUTINPUTtBSTW(≥tBSTZ)High-ZREADWRITBSTNOPNOPtBSTZ(=CL)READtoWRITECommandIntervalEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)33AWritecommandtotheconsecutiveReadcommandinterval:TocompletetheburstoperationDestinationrowoftheconsecutivereadcommandBankaddressRowaddressStateOperation1.
SameSameACTIVETocompletetheburstoperation,theconsecutivereadcommandshouldbeperformedtWRD(=BL/2+2)afterthewritecommand.
2.
SameDifferent—PrechargethebanktWPDaftertheprecedingwritecommand.
tRPaftertheprechargecommand,issuetheACTcommand.
tRCDaftertheACTcommand,theconsecutivereadcommandcanbeissued.
See'Areadcommandtotheconsecutiveprechargeinterval'section.
3.
DifferentAnyACTIVETocompleteaburstoperation,theconsecutivereadcommandshouldbeperformedtWRD(=BL/2+2)afterthewritecommand.
IDLEPrechargethebankindependentlyoftheprecedingwriteoperation.
tRPaftertheprechargecommand,issuetheACTcommand.
tRCDaftertheACTcommand,theconsecutivereadcommandcanbeissued.
in0in1in2in3out2out0out1CK/CKDMDQCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8;;;;;;BL=4CL=3tWRD(min)tWTR*DQSINPUTOUTPUTBL/2+2cycleWRITNOPNOPREADNote:tWTRisreferencedfromthefirstpositiveCKedgeafterthelastdesireddatainpairtWTR.
WRITEtoREADCommandIntervalEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)34AWritecommandtotheconsecutiveReadcommandinterval:TointerruptthewriteoperationDestinationrowoftheconsecutivereadcommandBankaddressRowaddressStateOperation1.
SameSameACTIVEDMmustbeinput1cyclepriortothereadcommandinputtopreventfrombeingwritteninvaliddata.
Incase,thereadcommandisinputinthenextcycleofthewritecommand,DMisnotnecessary.
2.
SameDifferent——*13.
DifferentAnyACTIVEDMmustbeinput1cyclepriortothereadcommandinputtopreventfrombeingwritteninvaliddata.
Incase,thereadcommandisinputinthenextcycleofthewritecommand,DMisnotnecessary.
IDLE—*1Note:1.
Prechargemustbeprecededtoreadcommand.
Thereforereadcommandcannotinterruptthewriteoperationinthiscase.
WRITEtoREADCommandInterval(Samebank,sameROWaddress)in0in1in2out0out1out2out3CK/CKDMDQCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8BL=4CL=3DQSDatamasked1cycleREADNOPWRITHigh-ZHigh-ZCL=3[WRITEtoREADdelay=1clockcycle]EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)30;BACKGROUND-COLOR:#4ae2f7">5in0in1in2in3out0out1out2out3CK/CKDMDQCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8BL=4CL=3DQSCL=3Datamasked2cycleREADNOPNOPWRITHigh-ZHigh-Z[WRITEtoREADdelay=2clockcycle]in0in1in2in3out0out1out2out3CK/CKDMDQCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8;BL=4CL=3DQSDatamasked;;;;;3cycleREADWRITNOPNOPNote:tWTRisreferencedfromthefirstpositiveCKedgeafterthelastdesireddatainpairtWTR.
tWTR*CL=3[WRITEtoREADdelay=3clockcycle]EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)36AReadcommandtotheconsecutivePrechargecommandinterval(samebank):TooutputalldataTocompleteaburstreadoperationandgetaburstlengthofdata,theconsecutiveprechargecommandmustbeissuedtRPD(=BL/2cycles)afterthereadcommandisissued.
out0out1out2out3CLK/CLKDQDQSCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8tRPD=BL/2READNOPNOPNOPPRE/PALLREADtoPRECHARGECommandInterval(samebank):Tooutputalldata(CL=3,BL=4)READtoPRECHARGECommandInterval(samebank):TostopoutputdataAburstdataoutputcanbeinterruptedwithaprechargecommand.
AllDQpinsandDQSpinsbecomeHigh-ZtHZP(=CL)aftertheprechargecommand.
out0out1CK/CKDQDQSCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7t8High-ZHigh-ZtHZPCL=3READNOPNOPPRE/PALLREADtoPRECHARGECommandInterval(samebank):Tostopoutputdata(CL=3,BL=2,4,8)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)37AWritecommandtotheconsecutivePrechargecommandinterval(samebank)TheminimumintervaltWPD((BL/2+4fortCK=0;BACKGROUND-COLOR:#4ae2f7">5ns)cycles)isnecessarybetweenthewritecommandandtheprechargecommand.
in0in1in2in3CK/CKDQDMDQSCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7LastdatainputtWPD;;;;;WRITNOPtWRPRE/PALLNOPWRITEtoPRECHARGECommandInterval(samebank)(BL=4)PrechargeTerminationinWriteCyclesDuringaburstwritecyclewithoutautoprecharge,theburstwriteoperationisterminatedbyaprechargecommandofthesamebank.
Inordertowritethelastinputdata,tWR(min)mustbesatisfied.
Whentheprechargecommandisissued,theinvaliddatamustbemaskedbyDM.
in2in3;;in0in1CK/CKDQDMDQSCommandt1t0t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6t7Datamasked;;;;;WRITNOPNOPtWRPRE/PALLPrechargeTerminationinWriteCycles(samebank)(BL=4)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)38BankactivecommandintervalDestinationrowoftheconsecutiveACTcommandBankaddressRowaddressStateOperation1.
SameAnyACTIVETwosuccessiveACTcommandscanbeissuedattRCinterval.
InbetweentwosuccessiveACToperations,prechargecommandshouldbeexecuted.
2.
DifferentAnyACTIVEPrechargethebank.
tRPaftertheprechargecommand,theconsecutiveACTcommandcanbeissued.
IDLEtRRDafteranACTcommand,thenextACTcommandcanbeissued.
CK/CKCommandBAtRCAddressACTVtRRDBank0ActiveBank3ActiveBank0PrechargeBank0ActivePREACTROW:0NOPNOPNOPACTACTROW:1ROW:0BankActivetoBankActiveModeregistersettoBank-activecommandintervalTheintervalbetweensettingthemoderegisterandexecutingabank-activecommandmustbenolessthantMRD.
CK/CKCommandAddressNOPNOPMRSACTtMRDModeRegisterSetBank3ActiveCODEBSandROWEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)39DMControlDMcanmaskinputdata.
BysettingDMtoLow,datacanbewritten.
WhenDMissettoHigh,thecorrespondingdataisnotwritten,andthepreviousdataisheld.
ThelatencybetweenDMinputandenabling/disablingmaskfunctionis0.
MaskMaskDQSDQDMt1t2t3t4t0;BACKGROUND-COLOR:#4ae2f7">5t6Writemasklatency=0DMControlEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)40TimingWaveformsCommandandAddressesInputTimingDefinitionCK/CKVREFCommand(/RAS,/CAS,/WE,/CS)AddresstIStIStIHtIH;;;;;;;;;VREFReadTimingDefinition/CKCKDQSDQ(Dout)tLZtACtQHtACtRPREtDQSCKtDQSCKtDQSCKtQHtQHtDQSQtDQSQtHZtQHtCKtCHtCLtDQSCKtDQSQtDQSQtDQSCKtDQSCKtRPSTtACtACtQHWriteTimingDefinition/CKCKDQSDMVREFVREFVREFDQ(Din)tDStDHtDQSStWPREtWPREStDStDHtDIPWtDIPWtDIPWtCKtDSHtDSStDSStDQSLtDQSHtWPSTEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)41ReadCycleBank0ActiveBank0ReadBank0PrechargeCL=2BL=4Bank0Access=VIHorVILBank0ActiveBank0ReadBank0PrechargetIStIHtCHtCKtCLtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStRPREtIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIH/RASA10AddressHigh-ZHigh-Z/CSCKECK/CK/CAS/WEBADQSDQ(output)DMVIHtRCDtRAStRPtRCtRPSTEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)42WriteCycleBank0ActiveCL=2BL=4Bank0Access=VIHorVILBank0ActiveBank0WriteBank0PrechargetIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHtIStIHVIHtRCDtRAStRCtRPtWR/CSCK/CKCKE/RAS/CAS/WEBAA10AddressDQ(input)DMDQS(input)tCKtCHtCLtDStDStDStDHtDHtDHtDQSHtDQSLtWPSTtDQSSEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)43ModeRegisterSetCycle012340;BACKGROUND-COLOR:#4ae2f7">56789101112131410;BACKGROUND-COLOR:#4ae2f7">5/CKCKCKE/CS/RAS/CAS/WEBAAddressDMDQ(output)bvalidcodecodetRPPrechargeIfneededModeregistersetBank3ActiveBank3ReadR:bC:bVIHBank3PrechargetMRDHigh-ZHigh-ZCL=2BL=4=VIHorVILDQSRead/WriteCycle;;;;;;;;;;;;;;R:aC:aC:bR:bC:b'';;;;;;;;;;;;;;;;;;;;;b''Bank0ActiveBank3ActiveBank0ReadBank3Read012340;BACKGROUND-COLOR:#4ae2f7">56789101112131410;BACKGROUND-COLOR:#4ae2f7">5CKE/RAS/CSDQS/CAS/WEAddressCKBADQ(output)DQ(input)/CKBank3WritetWRDHigh-ZVIHtRWD;;;bReadcycleCL=2BL=4=VIHorVIL;DM;;;aEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)44AutoRefreshCycle;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;PrechargeIfneededAutoRefreshBank0ActiveBank0Read;;;/CKCKCKE/CS/CAS/WEBAAddressDMDQ(output)DQ(input)/RAS;;;;;;;;;;;;;;;;;;;;;;;;;;;CL=2BL=4=VIHorVIL;;VIHtRPA10=1R:bC:bbHigh-ZtRFCDQSEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)40;BACKGROUND-COLOR:#4ae2f7">5SelfRefreshCycleSelfrefreshentrySelfrefreshexitHigh-Z/CKCKE/CS/RAS/CAS/WEBAAddressDMDQ(output)DQ(input)CKPrechargeIfneededBank0ActiveBank0ReadtRPtSNRA10=1R:bC:bDQSCL=2.
0;BACKGROUND-COLOR:#4ae2f7">5BL=4=VIHorVILtIStIHCKE=lowtSRDEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)46PackageDrawing66-pinPlasticTSOP(II)0.
100.
60;BACKGROUND-COLOR:#4ae2f7">5663413322.
22±0.
101.
0±0.
00;BACKGROUND-COLOR:#4ae2f7">51.
20max10.
160to8°0.
91max.
0.
09to0.
200.
17to0.
320.
100.
60±0.
10;BACKGROUND-COLOR:#4ae2f7">50.
80Nom0.
20;BACKGROUND-COLOR:#4ae2f7">5+0.
080.
00;BACKGROUND-COLOR:#4ae2f7">511.
76±0.
20ECA-TS2-0029-01Note:Thisdimensiondoesnotincludemoldflash,protrusionsorgateburrs.
Moldflash,protrusionsorgateburrsshallnotexceed0.
20mmperside.
APIN#1IDS0.
13MSABUnit:mmB*1SEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)47RecommendedSolderingConditionsPleaseconsultwithoursalesofficesforsolderingconditionsoftheEDD20;BACKGROUND-COLOR:#4ae2f7">508AK.
TypeofSurfaceMountDeviceEDD20;BACKGROUND-COLOR:#4ae2f7">508AKTA:66-pinPlasticTSOP(II)EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)48NOTESFORCMOSDEVICES1PRECAUTIONAGAINSTESDFORMOSDEVICESExposingtheMOSdevicestoastrongelectricfieldcancausedestructionofthegateoxideandultimatelydegradetheMOSdevicesoperation.
Stepsmustbetakentostopgenerationofstaticelectricityasmuchaspossible,andquicklydissipateit,whenonceithasoccurred.
Environmentalcontrolmustbeadequate.
Whenitisdry,humidifiershouldbeused.
Itisrecommendedtoavoidusinginsulatorsthateasilybuildstaticelectricity.
MOSdevicesmustbestoredandtransportedinananti-staticcontainer,staticshieldingbagorconductivematerial.
Alltestandmeasurementtoolsincludingworkbenchandfloorshouldbegrounded.
Theoperatorshouldbegroundedusingwriststrap.
MOSdevicesmustnotbetouchedwithbarehands.
SimilarprecautionsneedtobetakenforPWboardswithsemiconductorMOSdevicesonit.
2HANDLINGOFUNUSEDINPUTPINSFORCMOSDEVICESNoconnectionforCMOSdevicesinputpinscanbeacauseofmalfunction.
Ifnoconnectionisprovidedtotheinputpins,itispossiblethataninternalinputlevelmaybegeneratedduetonoise,etc.
,hencecausingmalfunction.
CMOSdevicesbehavedifferentlythanBipolarorNMOSdevices.
InputlevelsofCMOSdevicesmustbefixedhighorlowbyusingapull-uporpull-downcircuitry.
EachunusedpinshouldbeconnectedtoVDDorGNDwitharesistor,ifitisconsideredtohaveapossibilityofbeinganoutputpin.
Theunusedpinsmustbehandledinaccordancewiththerelatedspecifications.
3STATUSBEFOREINITIALIZATIONOFMOSDEVICESPower-ondoesnotnecessarilydefineinitialstatusofMOSdevices.
ProductionprocessofMOSdoesnotdefinetheinitialoperationstatusofthedevice.
ImmediatelyafterthepowersourceisturnedON,theMOSdeviceswithresetfunctionhavenotyetbeeninitialized.
Hence,power-ondoesnotguaranteeoutputpinlevels,I/Osettingsorcontentsofregisters.
MOSdevicesarenotinitializeduntiltheresetsignalisreceived.
Resetoperationmustbeexecutedimmediatelyafterpower-onforMOSdeviceshavingresetfunction.
CME0107EDD20;BACKGROUND-COLOR:#4ae2f7">508AKTAPreliminaryDataSheetE0349E20(Ver.
2.
0)49M01E0107NopartofthisdocumentmaybecopiedorreproducedinanyformorbyanymeanswithoutthepriorwrittenconsentofElpidaMemory,Inc.
ElpidaMemory,Inc.
doesnotassumeanyliabilityforinfringementofanyintellectualpropertyrights(includingbutnotlimitedtopatents,copyrights,andcircuitlayoutlicenses)ofElpidaMemory,Inc.
orthirdpartiesbyorarisingfromtheuseoftheproductsorinformationlistedinthisdocument.
Nolicense,express,impliedorotherwise,isgrantedunderanypatents,copyrightsorotherintellectualpropertyrightsofElpidaMemory,Inc.
orothers.
Descriptionsofcircuits,softwareandotherrelatedinformationinthisdocumentareprovidedforillustrativepurposesinsemiconductorproductoperationandapplicationexamples.
Theincorporationofthesecircuits,softwareandinformationinthedesignofthecustomer'sequipmentshallbedoneunderthefullresponsibilityofthecustomer.
ElpidaMemory,Inc.
assumesnoresponsibilityforanylossesincurredbycustomersorthirdpartiesarisingfromtheuseofthesecircuits,softwareandinformation.
[Productapplications]ElpidaMemory,Inc.
makeseveryattempttoensurethatitsproductsareofhighqualityandreliability.
However,usersareinstructedtocontactElpidaMemory'ssalesofficebeforeusingtheproductinaerospace,aeronautics,nuclearpower,combustioncontrol,transportation,traffic,safetyequipment,medicalequipmentforlifesupport,orothersuchapplicationinwhichespeciallyhighqualityandreliabilityisdemandedorwhereitsfailureormalfunctionmaydirectlythreatenhumanlifeorcauseriskofbodilyinjury.
[Productusage]DesignyourapplicationsothattheproductisusedwithintherangesandconditionsguaranteedbyElpidaMemory,Inc.
,includingthemaximumratings,operatingsupplyvoltagerange,heatradiationcharacteristics,installationconditionsandotherrelatedcharacteristics.
ElpidaMemory,Inc.
bearsnoresponsibilityforfailureordamagewhentheproductisusedbeyondtheguaranteedrangesandconditions.
Evenwithintheguaranteedrangesandconditions,considernormallyforeseeablefailureratesorfailuremodesinsemiconductordevicesandemploysystemicmeasuressuchasfail-safes,sothattheequipmentincorporatingElpidaMemory,Inc.
productsdoesnotcausebodilyinjury,fireorotherconsequentialdamageduetotheoperationoftheElpidaMemory,Inc.
product.
[Usageenvironment]Thisproductisnotdesignedtoberesistanttoelectromagneticwavesorradiation.
Thisproductmustbeusedinanon-condensingenvironment.
IfyouexporttheproductsortechnologydescribedinthisdocumentthatarecontrolledbytheForeignExchangeandForeignTradeLawofJapan,youmustfollowthenecessaryproceduresinaccordancewiththerelevantlawsandregulationsofJapan.
Also,ifyouexportproducts/technologycontrolledbyU.
S.
exportcontrolregulations,oranothercountry'sexportcontrollawsorregulations,youmustfollowthenecessaryproceduresinaccordancewithsuchlawsorregulations.
Iftheseproducts/technologyaresold,leased,ortransferredtoathirdparty,orathirdpartyisgrantedlicensetousetheseproducts,thatthirdpartymustbemadeawarethattheyareresponsibleforcompliancewiththerelevantlawsandregulations.
Theinformationinthisdocumentissubjecttochangewithoutnotice.
Beforeusingthisdocument,confirmthatthisisthelatestversion.