sensingnanosim剪卡

F.
Bouesse,M.
Renaudin,G.
Sicard26av.
FélixViallet,38031GrenobleCedexfraidy.
bouesse@imag.
frAbstract.
ThepurposeofthispaperistoproposeadesigntechniqueforimprovingtheresistanceoftheQuasiDelayInsensitive(QDI)AsynchronouslogicagainstDifferentialPowerAnalysisAttacks.
ThiscountermeasureexploitsthepropertiesoftheQDIcircuitacknowledgementsignalstointroducetemporalvariationssoastorandomlydesynchronizethedataresistance,isformallypresentedandanalyzed.
ElectricalsimulationsperformedonaDEScrypto-processorconfirmtherelevancyoftheapproach,showingadrasticreductionoftheDPApeaks,thusincreasingthecomplexityofaDPAattackonQDIasynchronouscircuits.
1IntroductionandmotivationsNowadays,thepossibilitiesofferedbyallrecentpowerfulside-channelattackstoaccesstoconfidentialinformation,constrainsecuresystemsproviderstodevelopnewresistantsystemsagainsttheseattacks.
Amongthesenewhardwarecryptanalysisattacks,thereistheDifferentialPowerAnalysis(DPA)whichisoneofexistsacorrelationbetweendataprocessedbythedesignandtheobservablepowerItisinthiscontextthatthepropertiesofSelf-timedlogichavebeenexploitedinordertoproposeefficientcounter-measuresagainstDPAattacks[2][3].
Insensitiveasynchronouslogicdemonstratedthepotentialityofthistypeoflogictoincreasethechip'sresistance[4][5].
themostpowerfulandlowcostattack.
ThemainideabehindDPAisthatthereexploitedusingstatisticalmeanstoretracesecretkeyinformation.
AllresultsfromtheanalysisofSelf-timedlogicparticularlytheQuasiDelaySpringer),pp.
11–24.
ImprovingDPAResistanceofQuasiDelayprocessingtimes.
Theefficiencyofthecountermeasure,intermsofDPAshiftedAcknowledgmentSignalsTIMALaboratory,ConcurentIntegratedSystemsGroupBouesse,F.
,Renaudin,M.
,Sicard,G.
,2007,inIFIPInternationalFederationforInformationProcessing,Volume240,VLSI-SoC:FromSystemstoSilicon,eds.
Reis,R.
,Osseiran,A.
,Pfleiderer,H-J.
,(Boston:consumption.
In1998PaulKocher[1]demonstratedhowthiscorrelationcanbeInsensitiveCircuitsUsingRandomlyTime-However,paper[6]reportedthat,eveniftheQDIasynchronouslogicincreasestheresistanceofthechip,therestillexistssomeresidualsourcesofleakagethatcanbeusedtosucceedtheattack.
TheobjectiveofthispaperistomakeaDPAattackimpossibleorimpracticablewithstandardequipmentbyincreasingthecomplexityoftheattack.
Fordoingso,weintroducerandomlytimeshifted(RTS)acknowledgmentsignalsintheQDIasynchronouslogicinordertoaddnoiseinchip'spowerconsumption.
Indeed,theuseofaRTSacknowledgementsignalinanasynchronousQuasiDelayInsensitiveblockenablesustodesynchronizethedataprocessingtime,soastocomputetheblocks'outputchannelsatrandomtimes.
AstheDPAattackrequiresthesignalstobesynchronizedwithrespecttoafixedtimeinstantfordataanalysis[1][7],thisdesynchronizationmakestheDPAattackmoredifficultasitisprovedinthispaper.
Wepresentinthefirstpartofthepaper(section2),thepropertiesofQuasiDelayInsensitiveasynchronouslogic,especiallythepropertiesoftheacknowledgmentsignal.
Section3firstintroducestheformalanalysisoftheDPAattack.
ItthenpresentsthedesynchronizationtechniquebasedonRTSacknowledgementsignalsandformalizesitsefficiencyintermsofDPAresistance.
Finally,sections4and5illustratethetechniqueusingelectricalsimulationsperformedonthewellknownDataEncryptionStandard(DES)architecture.
Section6concludesthepaperandgivessomeprospects.
2QuasiDelayInsensitiveAsynchronouslogic:theacknowledgmentsignalThissectionrecallsthebasiccharacteristicsofanasynchronouscircuit,particularlytheruleoftheacknowledgementsignalintheQDIasynchronouslogic.
Becausethistypeofcircuitdoesnothaveaglobalsignalwhichsamplesthedataatthesametime,asynchronouscircuitsrequireaspecialprotocoltoperformacommunicationbetweenitsmodules.
Thebehaviorofanasynchronouscircuitissimilartoadata-flowmodel.
Theasynchronousmodule,asdescribedinfigure1andwhichcanactuallybeofanycomplexity,receivesdatafromitsinputchannels(requestsignal),processesthem,andthensendstheresultsthroughitsoutputchannels.
Therefore,amoduleisactivatedwhenitsensesthepresenceofincomingdata.
Thispoint-to-pointcommunicationisrealizedwithaprotocolimplementedinthemoduleitself.
Suchprotocolsnecessitateabi-directionalsignalingbetweenbothmodules(requestandacknowledgement):itiscalledhandshakingprotocols.
12F.
Bouesse,M.
Renaudin,G.
SicardFig.
1.
Handshakebasedcommunicationbetweenmodules.
Thebasisofthesequencingrulesofasynchronouscircuitsliesinthehandshakingprotocols.
Amongthetwomainsclassesofprotocols,onlythefour-phaseprotocolisconsideredanddescribedinthiswork.
ItisthemostwidelyusedandefficientlyimplementedinCMOS[8].
Fig.
2.
Four-phasehandshakingprotocol.
Inthefirstphase(Phase1)dataaredetectedbythereceiverwhentheirvalueschangefrominvalidtovalidstates.
Thenfollowsthesecondphasewherethereceiversetstoonetheacknowledgementsignal.
Thesenderinvalidatesalldatainthethirdphase.
Finallythereceiverresetstheacknowledgmentsignalwhichcompletesthereturntozerophase.
Dedicatedlogicandspecialencodingarenecessaryforsensingdatavalidity/invalidityandforgeneratingtheacknowledgementsignal.
Requestforcomputationcorrespondstodatadetectionandtheresetoftheacknowledgmentsignalmeansthatthecomputationiscompletedandthecommunicationisfinished.
InQDIasynchronouslogic,ifonebithastobetransferredthroughachannelwithafour-phaseprotocol,twowiresareneededtoencodeitsdifferentvalues.
Thisiscalleddual-railencoding(table1).
13ImprovingDPAresistanceofQuasiDelayInsensitiveCircuitsTable1.
Dualrailencodingofthethreestatesrequiredtocommunicate1bit.
ChanneldataA0A1010101Invalid00Unused11ThisencodingcanbeextendedtoN-rail(1-to-N).
Theacknowledgementsignalisgeneratedusingthedata-encoding.
Thedual-railencodedoutputsaresensedwithNorgatesforgeneratingtheacknowledgmentsignal,asillustratedinfigure3.
Fig.
3.
1-bitHalf-bufferimplementingafour-phaseprotocol(CrisaMullergatewitharesetsignal)TheMullerC-element'struthtableandsymbolaregiveninFigure4.
Fig.
4.
TruthtableandsymboloftheC-element.
Figure3illustratestheimplementationoftwoasynchronousmodules(AandB)withtheirmemoryelementscalledhalf-buffer.
Thehalf-bufferimplementsafour-phaseprotocol.
WhentheacknowledgementsignalofmoduleB(B_ack)isset,itmeansthatthemoduleisreadytoreceivedata.
IfadataistransferredfrommoduleAtomoduleB,moduleBcomputesitsoutputsandresetsitsacknowledgementsignal(B_ack).
ModuleBisthenreadytoreceiveinvaliddatafrommoduleA.
14F.
Bouesse,M.
Renaudin,G.
SicardInthisoperatingmode,theacknowledgmentsignalcanbeconsideredasalocalenablesignalwhichcontrolsdatastoragelocally.
Notethatthismechanismdoesnotneedanytimingassumptiontoensurefunctionalcorrectness;itissimplysensitivetoevents.
Hence,theacknowledgmentsignalenablestocontroltheactivationofthecomputationinagivenmodule,aswellasitstimeinstant.
Thetechniqueproposedinthispaper,exploitsthispropertybyinsertingrandomdelaysintheacknowledgementsignals.
ItiscalledRandomlyTime-Shiftedacknowledgmentsignals.
Itbasicallydesynchronizesthepowerconsumptioncurvesmakingthedifferentialpoweranalysismoredifficultasprovedinthenextsection.
3DPAandRTSacknowledgmentsignalonQDIasynchronouscircuits:FormalApproachInthissection,weformallyintroducethebasisoftheDPAattack[7]andformallyanalysetheeffectsoftheRTSacknowledgementsignalonQDIasynchronouscircuitsintermsofDPAresistance.
3.
1DifferentialPowerAnalysisAttackThefunctionalhypothesisofDPAattackistheexistingcorrelationbetweenthedataprocessedbythecircuitryanditspowerconsumption.
TherearethreemainphasesforprocessingtheDPAattack:thechoiceoftheselectionfunctionD,thedatacollectionphaseandthedataanalysisphase.
Phase1:Inthefirststep,theselectionfunctionisdefinedbyfindingblocksinthearchitecturewhichdependonsomepartsofthekey.
SuchafunctionintheDESalgorithmforexamplecanbedefinedasfollows:D(C1,P6,K0)=SBOX1(P6K0)C1=firstbitofSBOX1function.
P6=6-bitplain-text-inputoftheSBOX1function.
K0=6-bitofthefirstround'ssubkey:keytoguess.
SBOX1=asubstitutionfunctionofDESwitha4-bitoutput.
Phase2:ThesecondstepconsistsincollectingthediscretetimepowersignalSi(tj)andthecorrespondingciphertextoutputs(CTOi)foreachoftheNplaintextinputs(PTIi).
ThepowersignalSi(tj)representsthepowerconsumptionoftheselectionfunction:indexicorrespondstothePTIiplaintextstimulusandtimetjcorrespondstothetimewheretheanalysistakesplace.
Phase3:Therightkeyisguessedinthethirdphase.
AllcurrentsignalsSi(tj)aresplitintotwosetsaccordingtoaselectionfunctionD.
15ImprovingDPAresistanceofQuasiDelayInsensitiveCircuitsTheaveragepowersignalofeachsetisgivenby:Where|no|and|n1|representthenumberofpowersignalsSi(tj)respectivelyinsetS0andS1.
TheDPAbiassignalisobtainedby:IftheDPAbiassignalshowsimportantpeaks,itmeansthatthereisastrongcorrelationbetweentheDfunctionandthepowersignal,andsotheguessedkeyiscorrect.
Ifnot,theguessedkeyisincorrect.
SelectinganappropriateDfunctionisthenessentialinordertoguessagoodsecretkey.
Asillustratedabove,theselectionfunctionDcomputesattimetjduringtheciphering(ordeciphering)process,thevalueoftheattackedbit.
Whenthisvalueismanipulatedattimetj,therewillbeatthistime,adifferenceontheamountofdissipatedpoweraccordingtothebit'svalue(eitheroneorzero).
Let'sdefined0i(tj)theamountofdissipatedpowerwhentheattackedbitswitchesto0attimetjbyprocessingtheplaintextinputianddefined1i(tj)theamountofdissipatedpowerwhenthisbitswitchesto1.
Inreality,thevaluesofd0i(tj)andd1i(tj)correspondtothedissipatedpowerofalldata-pathswhichcontributetotheswitchingactivityoftheattackedbit.
EachoneofthesevalueshasitsweightineachaveragepowersignalA0(tj)andA1(tj).
AsthegoaloftheDPAattackistocomputethedifferencebetweenthesetwovalues,wecanexpresstheaveragepowersignalofthesebothsetsA0(tj)andA1(tj)by:(1)(3)(4)(2)(4)16F.
Bouesse,M.
Renaudin,G.
SicardInordertomakeanefficientanalysis,theamplitudeoftheDPAsignatureε(tj)mustbeashighaspossible.
Asimplewaytoguaranteethisistouseasignificantnumberofplaintextinputs(N).
Indeed,thenumberofPTIi(thenumberofpowersignalSi(tj))usedtoimplementtheattackenablestoreducetheeffectsofthenoisysignalsandtoincreasetheprobabilityofexcitingalldata-paths.
Itiswellknownthatthesignal-to-noiseratiofortheaveragedsignalincreasesasthesquarerootofthenumberofcurves.
σnoiseisthestandarddeviationofthenoiseIncreasingthenumberofplaintextinputs(PTIi)allowsustoensurethatalldata-pathswhichmakeswitchingto0orto1theattackedbitareexcited.
Thedealhere,istotakeintoconsiderationallpossiblequantitiesdxi(tj)whichrepresenttheswitchingcurrentoftheattackedbit.
Astheprobabilityofexcitingalldata-pathsisproportionaltoN,biggerthevalueofN,bettertheprobabilitytoexcitealldata-pathsoftheattackedbitis:misgenerallyunknownbythehackerandrepresentsthenumberofdata-paths.
Therefore,theknowledgeoftheimplementationwhichenablestochoosetheplaintextinputsandtheuseofhighqualityinstrumentationareassetsthatimprovetheDPAattack.
Infact,theyconsiderablyreducethenumberofdata(N)requiredforsucceedingtheattack.
3.
2TheRTSacknowledgementsignalThemethodweproposeinthispaperenablesthedesignertointroduceatemporalnoiseinthedesigninordertodesynchronizethetimerequiredforprocessingtheattackedbit.
Theideaoftheapproachistorandomlyshiftintimethecurrentprofileofthedesign.
Toachievethisgoal,werandomizetheacknowledgmentsignallatencyoftheblocksofthearchitecture.
Asillustratedinfigure5,weuseadelayelementcontrolledbyarandomnumbergenerator.
Thedesignoftherandomnumbergeneratorisoutofthescopeofthispaper.
True(5)17ImprovingDPAresistanceofQuasiDelayInsensitiveCircuitsTherefore,theDPAsignatureisexpressedby:randomnumbergenerator(TRNG)designisanimportanttopicandmanydifferenttypesofTRNGimplementationexist[9][10].
Fig.
5.
ImplementationofarandomacknowledgmentsignalLet'sdenotenthenumberofpossiblerandomdelaysimplementedinagivenarchitecture.
ndependsonthenumberofavailableacknowledgmentsignals(m)inthearchitectureandonthenumberofdelays(ki)implementedperacknowledgmentsignal.
The"n"valueiscomputedbythefollowingexpression:assumingcascadedmodules.
Iftheacknowledgmentsignalisrandomizedntimes,itmeansthatthevalueoftheattackedbitiscomputedatndifferenttimes(tj).
N/nrepresentsthenumberoftimestheattackedbitisprocessedatagiventimetjandN/2nrepresentsthenumberoftimesthequantitiesd0i(tj)andd1i(tj)ofthisbitcontributetosetS0andS1respectively.
IfweconsiderthattheNcurvesareequallysplitinbothsets(n0=n1=N/2),theaveragepowersignalofeachsetisnowexpressedby:TheDPAbiassignalisthengivenbythefollowingexpression:with;6)(6)18F.
Bouesse,M.
Renaudin,G.
SicardTheseexpressionsshowthat,insteadofhavingasinglequantityεx(tj),wehavendifferentsignificantquantitiesεx(tn)whichcorrespondtontimeswheretheattackedbitisprocessed.
Moreover,italsodemonstratesthateachquantityεx(tj)isdividedbyafactornasillustratedbythefollowingsimplification:withItmeansthat,althoughthenumberofsignificantpointsisincreasedbyn,thisapproachdividesbyntheaveragecurrentpeaksvariations.
ItoffersthepossibilitytobringdownthelevelofDPAbiassignalclosertocircuitry'snoise.
3.
2DiscussionLet'sforexampleimplementtheDPAattackusing1000plaintextinputs(N=1000).
Inthestandardapproachwheretheattackedbitisprocessedatauniquegiventime,weobtainanaverageof500currentcurvesforeachofthesetsS0andS1.
UsingourapproachwithRTSacknowledgmentsignalsandassumingn=16(forexample),weobtain16differentpoints(intermsoftime)wheretheattackedbitisprocessed.
Thereare62valuesdxi(tj)(N/ncurves)wherethisbitisprocessedattime(tj).
Eachsetthencontains31curves.
Whentheaveragepowersignalofeachsetiscalculated,valuesdxi(tj)are16timeslowerthanwithoutRTSacknowledgmentsignals.
Hence,thecontributionofdxi(tj)incurrentpeaksvariationsarereducedbyafactor16.
Therefore,tosucceedtheattackthehackerisobligedtosignificantlyincreasethenumberofacquisitions(N)ortoapplyacross-correlationfunctionwhichisexactlythegoaltoachieveintermsofattack'scomplexity.
Infact,cross-correlationremainsausefulmethodforsynchronizingdata.
Buttobefunctional,thehackermustidentifytheamountofcurrentprofileoftheattackedbit(dxi(tj))tobeusedasareference,andthencomputecross-correlationsinordertosynchronizeeachoftheNcurveswiththereference.
Knowingthat,thecross-correlationisappliedoninstantaneouscurrentcurveswhichcontainsignificantquantityofnoise.
Toincreasethedifficultyofthisanalysis,thevalueofncanbesignificantlyincreasedbydealingwiththevaluesofmandk.
Thevalueofmdependsonthearchitecture.
Itsvaluecanbeincreasedbyexpandingtheacknowledgmentsignalsofthearchitecture.
Eachbitorintermediatevalueofthedesigncanbeseparatelyacknowledged.
Thistechniqueenablesalsotoreducethedata-pathlatency.
(7)(8)19ImprovingDPAresistanceofQuasiDelayInsensitiveCircuitsThevaluesofthedelaydependonthetimespecificationtocipher/decipherdata.
Theyareboundedbythemaximumciphering/decipheringtime.
Consequently,theacknowledgementsignalsofanyasynchronousquasidelayinsensitivecircuitcanbeexploitedtointroducerandomdelaysandthereforeincreasetheDPAresistanceofthechips.
4CaseStudy:DESCrypto-processorThissectiondealswiththedifferentpossibilitiesofimplementingRTSacknowledgmentsignalsonQDIasynchronouscircuits.
TheDESwaschosenasanevaluationvectorbecausetheattackonthisalgorithmiswellknown.
Figure6representstheDEScorearchitecture,implementingafour-phasehandshakeprotocol,using1-to-Nencodeddataandbalanceddata-paths[2].
Thearchitectureiscomposedofthreeiterativeasynchronousloopssynchronizedthroughcommunicatingchannels.
Oneloopforthecipheringdata-path,thesecondforthekeydata-pathandthelastoneforthecontroldata-pathwhichenablesthecontrolofthesixteeniterationsofthealgorithm.
Forexamplelet'sapplythetechniquetothefivegreyblocksoffigure6.
Eachblockhasitsownacknowledgementsignalandthedelayinsertedineachacknowledgmentsignalcantakefourvalues.
Therefore,thereare1024possibledelayvalues(n=1024).
Itmeansthat(intermsofDPAresistance)thecurrentpeakvariationscorrespondingtodxi(tj)willbedividedby1024.
Fig.
6.
AsynchronousDEScorearchitecture20F.
Bouesse,M.
Renaudin,G.
Sicard5ResultsandAnalysis:ElectricalsimulationsElectricalsimulationsenableustoanalyzetheelectricalbehaviourofthedesignwithhighaccuracy,i.
e.
withoutdisturbingsignal(noise).
AllelectricalsimulationsareperformedwithNanosimusingtheHCMOS9designkit(0.
13!
m)fromSTMicroelectronics.
Thearchitectureusedfortheseelectricalanalysisimplementsoneacknowledgementsignalperblock.
However,fortheneedsofillustrationonlytheacknowledgmentsignaloftheinputsoftheSBOX1israndomlydelayedwith8differentdelays.
Thedefinedselectionfunction,usedtoimplementtheattack,isasfollows:D(Cn,P6,K0)=SBOX1(P6K0)withn∈{1,2,3,4}TheDPAattackhasbeenimplementedonthefouroutputbitsoftheSBOX1andonthefirstiterationoftheDESalgorithmusing64plaintextinputs(N=64).
Figure7showsthecurrentprofileofthefirstiterationwhentheRTSacknowledgmentsignalisactivatedanddeactivated.
Whenthedelayof13nsisused,thetimerequiredforprocessinganiteration(figure7-b)correspondstothetimerequiredtoprocess3iterationswithoutdelays(figure7-a).
Hencethecipheringtimeismultipliedbyafactor3.
Thisdelayischosenforthesakeofillustrationonly.
GivenalevelofDPAresistance,thedelaycanbestronglydecreasedinpractice(downtoafewnanosecondswiththistechnology)toreduceasmuchaspossiblethetimingoverheadaswellasthehardwareoverheadcausedbytheapplicationofthetechniqueFig.
7.
CurrentprofileoftheDESQDIasynchronousarchitecture.
21ImprovingDPAresistanceofQuasiDelayInsensitiveCircuitsOnlythefirstiterationsareconsideredb-withacorrectguessedkeyFig.
8.
ElectricalsignatureswhenperformedDPAattackonbit4oftheSBOX1.
Onlythefirstroundisconsideredandcomputedusingmorethan2.
100.
000point.
AstheSBOX1hasfouroutputbitsencodedindual-rail,wehave8data-paths(fromoutputstoinputs)whichenabletocompute8valuesofdxi(tj).
Let'srecallthat,dxi(tj)(d0i(tj);d1i(tj))correspondstotheamountofdissipatedpowerwhentheattackedbitisprocessedattimetj.
Forexample,let'sconsidertheoutputbit4oftheSBOX1.
Contrarytoastandardapproachandduetothe8delayshifts,thevaluesd04(tj)andd14(tj)areprocessed4timesinsteadofbeingprocessed32times,sothattheirweightsarereducedbyafactor8intosetsS1andS0.
EachofthissetenablesustocalculatetheaveragecurrentsΑ0(tj)andΑ1(tj).
22F.
Bouesse,M.
Renaudin,G.
SicardFigure8showstheseaveragecurrentprofiles(A0(tj)andA1(tj))whichareusedtocomputetheDPAbiassignal(S(tj)),alsoshowninfigure8.
PartIofthesecurvesrepresentthefirstencryptionoperationsinthefirstiteration(seefigure8).
ThispartisnotaffectedbytheRTSacknowledgmentsignalwhichisonlyappliedonSBOX1.
Infact,beforecomputingtheSBOXfunction,thechipfirstcomputesIP,ExpansionandXor48functions(figure6),sothat,inthefirstiteration,thesefunctions,arenotaffectedbytheRTSacknowledgementsignalofSBOX1.
ThisexplainswhytheamplitudeoftheaveragepowercurvestartsdecreasingafterpartIanditclearlyillustratestheeffectoftheRTSsignalonthepowercurves.
ThiscanofcoursebechangedbyactivatingtheRTSacknowledgementsignalsofblocksIP,Expansionand/orXor48.
Intheconsideredexample,64PTIicurvesareusedtoimplementtheattack.
Inthiscase,obtainingthekeybitfromtheDPAbiassignalisimpossibleasshowninfigure8.
Indeed,thereisnorelevantpeakintheDPAcurrentcurves(figure8-aand8-b).
6ConclusionThispaperpresentedacountermeasureagainstDPAbasedonrandomlytime-shiftedacknowledgmentsignalsofasynchronousQDIcircuits.
Theefficiencyofthecountermeasurewasfirsttheoreticallyformalizedandthendemonstratedusingelectricalsimulations.
ThetechniqueprinciplewasillustratedonaDESarchitecture.
generator.
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