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DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013DS92LV3241/DS92LV324220-85MHz32-BitChannelLinkIISerializer/DeserializerCheckforSamples:DS92LV3241,DS92LV32421FEATURESAPPLICATIONS2WideOperatingRangeEmbeddedClockIndustrialImaging(Machine-Vision)andSER/DESControl–Upto32-bitParallelLVCMOSDataSecurity&SurveillanceCamerasandInfrastructure–20to85MHzParallelClockMedicalimaging–Upto2.
72GbpsApplicationDataPaylodUpto30bitsperPixel,VGAtoHDVideoSelectableSerialLVDSBusWidthTransportandDisplay–DualLaneMode(20to50MHz)–QuadLaneMode(40to85MHz)DESCRIPTIONSimplifiedClockingArchitectureTheDS92LV3241(SER)serializesa32-bitdatabus–NoSeparateSerialClockLineinto2or4(selectable)embeddedclockLVDSserialchannelsforadatapayloadrateupto2.
72Gbps–NoreferenceClockRequiredovercablessuchasCATx,orbackplanesFR-4–ReceiverLockstoRandomDatatraces.
ThecompanionDS92LV3242(DES)On-ChipSignalConditioningforRobustSerialdeserializesthe2or4LVDSserialdatachannels,Connectivityde-skewschannel-to-channeldelayvariationsandconvertstheLVDSdatastreambackintoa32-bit–TransmitPre-EmphasisLVCMOSparalleldatabus.
–DataRandomizationOn-chipdataRandomization/ScramblingandDC–DC-BalanceEncodingbalanceencodingandselectableserializerPre-–ReceiveChannelDeskewemphasisensurearobust,low-EMItransmissionover–Supportsupto10mCAT-5at2.
7Gbpslonger,lossycablesandbackplanes.
TheDeserializerautomaticallylockstoincomingdataIntegratedLVDSTerminationswithoutanexternalreferenceclockorspecialsyncBuilt-inAT-SPEEDBISTforEnd-to-Endpatterns,providinganeasy"plug-and-lock"operation.
SystemTestingByembeddingtheclockinthedatapayloadandAC-CoupledInterconnectforIsolationandincludingsignalconditioningfunctions,theChannel-FaultProtectionLinkIISerDesdevicesreducetracecount,eliminate>4KVHBMESDProtectionskewissues,simplifydesigneffortandlowercable/connectorcostforawidevarietyofvideo,Space-Saving64-pinTQFPPackagecontrolandimagingapplications.
Abuilt-inAT-FullIndustrialTemperatureRange:-40°toSPEEDBISTfeaturevalidateslinkintegrityandmay+85°Cbeusedforsystemdiagnostics.
1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2Alltrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2009–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
ti.
comBlockDiagramModeDiagramsFigure1.
'DualMode2SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013Figure2.
QuadModeDS92LV3241PinDiagramFigure3.
DS92LV3241PinDiagram-TopView64-PinTQFP(PAGPackage)Copyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
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comDS92LV3241SerializerPINDESCRIPTIONSPin#PinNameI/O,TypeDescriptionLVCMOSPARALLELINTERFACEPINS10–8,TxIN[31:29],I,LVCMOSSerializerParallelInterfaceDataInputPins.
5–1,TxIN[28:24],64–57,TxIN[23:16],52–51,TxIN[15:14],48–44.
TxIN[13:9],41–33TxIN[8:0]11TxCLKINI,LVCMOSSerializerParallelInterfaceClockInputPin.
StrobeedgesetbyR_FBconfigurationpin.
CONTROLANDCONFIGURATIONPINS12PDBI,LVCMOSSerializerPowerDownBar(ACTIVELOW)PDB=L;DeviceDisabled,DifferentialserialoutputsareputintoTRI-STATEstand-bymode,PLLisshutdownPDB=H;DeviceEnabled15MODEI,LVCMOSDualorQuadmodeselect(ACTIVEH)MODE=L(default);DualMode,MODE=H;QuadMode19PREI,LVCMOSPRE-emphasislevelselectpinPRE=(RPRE>12kΩ);Imax=[(1.
2/R)x20x2],Rmin=12kΩ.
PRE=Horfloating;pre-emphasisisdisabled.
14R_FBI,LVCMOSRising/FallingBarClockEdgeSelectR_FB=H;RisingEdge,R_FB=L;FallingEdge20VSELI,LVCMOSVOD(DifferentialOutputVoltage)LlevelSelectVSEL=L;LowSwing,VSEL=H;HighSwing13BISTENI,LVCMOSBISTEnableBISTEN=L;BISTOFF,(default),normaloperatingmode.
BISTEN=H;BISTEnabled(ACTIVEHIGH)16RSVDI,LVCMOSReserved—MUSTBETIEDLOWLVDSSERIALINTERFACEPINS22,24,TxOUT[3:0]+O,LVDSSerializerLVDSNon-InvertedOutputs(+)28,3021,23,TxOUT[3:0]-O,LVDSSerializerLVDSInvertedOutputs(-)27,29POWER/GROUNDPINS7,18,32,VDDVDDDigitalVoltagesupply,3.
3V426,17,31,VSSGNDDigitalground4353,56VDDPLLVDDAnalogVoltagesupply,PLLPOWER,3.
3V54,55VSSPLLGNDAnalogground,PLLGROUND26VDDAVDDAnalogVoltagesupply25VSSAGNDAnalogground49IOVDDVDDDigitalIOVoltagesupplyConnectto1.
8Vtypfor1.
8VLVCMOSinterfaceConnectto3.
3Vtypfor3.
3VLVCMOSinterface50IOVSSGNDDigitalIOground4SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013DS92LV3242PinDiagramTopViewFigure4.
DS92LV3242PinDiagram64-PinTQFP(PAGPackage)Copyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
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comDS92LV3242DeserializerPINDESCRIPTIONSPin#PinNameI/O,TypeDescriptionLVCMOSPARALLELINTERFACEPINS5–7,RxOUT[31:29],O,LVCMOSDeserializerParallelInterfaceDataOutputPins.
10–14,RxOUT[28:24],19–25,RxOUT[23:17],28–32,RxOUT[16:12],33–39,RxOUT[11:5],42–46RxOUT[4:0]4RxCLKOUTO,LVCMOSDeserializerRecoveredClockOutput.
Paralleldatarateclockrecoveredfromtheembeddedclock.
3LOCKO,LVCMOSLOCKindicatesthestatusofthereceiverPLLLOCK=L;deserializerCDR/PLLisnotlocked,RxOUT[31:0]andRCLKareTRI-STATEDLOCK=H;deserializerCDR/PLLislockedCONTROLANDCONFIGURATIONPINS48R_FBI,LVCMOSRising/FallingBarClockEdgeSelectR_FB=H;RxOUTclockedonrisingedgeR_FB=L;RxOUTclockedonfallingedge50RENI,LVCMOSDeserializerEnable,DESOutputEnableControlInput(ACTIVEHIGH)REN=L;disabled,RxOUT[31:0]andRxCLKOUTTRI-STATED,PLLstilloperationalREN=H;Enabled(ACTIVEHIGH)49PDBI,LVCMOSPowerDownBar,ControlInputSignal(ACTIVELOW)PDB=L;disabled,RxOUT[31:0],RCLK,andLOCKareTRI-STATEDinstand-bymode,PLLisshutdownPDB=H;Enabled47RSVDI,LVCMOSReserved—MUSTBETIEDLOWLVDSSERIALINTERFACEPINS51,53,RxIN[0:3]+I,LVDSDeserializerLVDSNon-InvertedInputs(+)57,5952,54,RxIN[0:3]-I,LVDSDeserializerLVDSInvertedInputs(-)58,60POWER/GROUNDPINS9,16,VDDVDDDigitalVoltagesupply,3.
3V17,26,618,15,VSSGNDDigitalGround18,27,6255VDDAVDDAnalogLVDSVoltagesupply,POWER,3.
3V56VSSAGNDAnalogLVDSGROUND1,40,VDDPLLVDDAnalogVoltagesupplyPLLVCOPOWER,3.
3V642,41,VSSPLLGNDAnalogground,PLLVCOGROUND63Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
6SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013AbsoluteMaximumRatings(1)(2)SupplyVoltage(VDD)0.
3Vto+4VLVCMOSInputVoltage0.
3Vto(VDD+0.
3V)LVCMOSOutputVoltage0.
3Vto(VDD+0.
3V)LVDSDeserializerInputVoltage0.
3Vto+3.
9VLVDSDriverOutputVoltage0.
3Vto+3.
9VJunctionTemperature+125°CStorageTemperature65°Cto+150°CLeadTemperature(Soldering,4seconds)+260°CMaximumPackagePowerDissipationCapacityPackageDerating1/θJA°C/Wabove+25°CθJA35.
7°C/W(3)θJC12.
6°C/WESDRating(HBM)>4kV(1)"AbsoluteMaximumRatings"indicatelimitsbeyondwhichdamagetothedevicemayoccur,includinginoperabilityanddegradationofdevicereliabilityand/orperformance.
Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximumRatingsorotherconditionsbeyondthoseindicatedintheRecommendedOperatingConditionsisnotimplied.
TheRecommendedOperatingConditionsindicateconditionsatwhichthedeviceisfunctionalandthedeviceshouldnotbeoperatedbeyondsuchconditions.
(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
(3)4LayerJEDECRecommendedOperatingConditionsMinNomMaxUnitsSupplyVoltage(VDD)3.
1353.
33.
465VSupplyVoltage(IOVDD)3.
3VI/OInterface3.
1353.
33.
465V(SERONLY)1.
8VI/OInterface1.
711.
81.
89VOperatingFreeAirTemperature(TA)40+25+85°CInputClockRateDualMode2050MHzQuadMode4085MHzTolerableSupplyNoise100mVP-PCopyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
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comElectricalCharacteristics(1)(2)Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitsLVCMOSDCSPECIFICATIONSVIHHighLevelInputVoltageTx:IOVDD=1.
71Vto1.
89V0.
65xIOVDD+IOVDD0.
3VTx:IOVDD=3.
135Vto3.
465V2.
0VDDRxVILLowLevelInputVoltageTx:IOVDD=1.
71Vto1.
89V0.
35xGNDIOVDDVTx:IOVDD=3.
135Vto3.
465VGND0.
8RxVCLInputClampVoltageICL=18mA0.
81.
5VIINInputCurrentTx:VIN=0Vor3.
465V(1.
89V)10+10IOVDD=3.
465V(1.
89V)ARx:VIN=0Vor3.
465V10+10VOHHighLevelOutputVoltageIOH=2mA(Dual)2.
43.
0VDDVIOH=2mA(Quad)VOLLowLevelOutputVoltageIOH=2mA(Dual)GND0.
330.
5VIOH=2mA(Quad)IOSOutputShortCircuitCurrentVOUT=0V(Dual)2240mAVOUT=0V(Quad)3370mAIOZTRI-STATEOutputCurrentPDB=0V,10+10μAVOUT=0VorVDDSERIALIZERLVDSDCSPECIFICATIONSVODOutputDifferentialVoltageNopre-emphasis,VSEL=L350440525mVP-P(VSEL=H)(629)(850)(1000)ΔVODOutputDifferentialVoltageUnbalanceVSEL=L,Nopre-emphasis150mVP-PVOSOffsetVoltageVSEL=L,Nopre-emphasis1.
001.
251.
50VΔVOSOffsetVoltageUnbalanceVSEL=L,Nopre-emphasis450mVIOSOutputShortCircuitCurrentTxOUT[3:0]=0V,PDB=VDD,25VSEL=L,Nopre-emphasismATxOUT[3:0]=0V,PDB=VDD,610VSEL=H,Nopre-emphasisIOZTRI-STATEOutputCurrentPDB=0V,15±1+15ATxOUT[3:0]=0VORVDDPDB=VDD,15±1+15ATxOUT[3:0]=0VORVDDRTOutputTerminationInternaldifferentialoutputtermination90100130betweendifferentialpairsSERIALIZERSUPPLYCURRENT(DVDD,PVDDANDAVDDPINS)(3)IDDTQSerializer(Tx)TotalSupplyCurrentf=85MHz,CHECKERBOARDpattern150200QuadModeMODE=H,VSEL=H,PRE=OFF(includesloadcurrent)f=85MHz,CHECKERBOARDpattern150200MODE=H,VSEL=H,RPRE=12kmAf=85MHz,RANDOMpattern140195MODE=H,VSEL=H,PRE=OFFf=85MHz,RANDOMpattern140195MODE=H,VSEL=H,RPRE=12k(1)TypicalvaluesrepresentmostlikelyparametricnormsatVDD=3.
3V,TA=+25°C,andattheRecommendedOperatingConditionsatthetimeofproductcharacterizationandarenotverified.
(2)Currentintoathedeviceisdefinedaspositive.
Currentoutofadevicepinisdefinedasnegative.
VoltagesarereferencedtogroundexceptVOD,ΔVOD,VTH,VTLwhicharedifferentialvoltages.
(3)DIGITAL,PLL,ANDANALOGVDDS8SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013ElectricalCharacteristics(1)(2)(continued)Overrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitsIDDTDSerializer(Tx)TotalSupplyCurrentf=50MHz,CHECKERBOARDpattern120145DualModeMODE=L,VSEL=H,PRE=OFF(includesloadcurrent)f=50MHz,CHECKERBOARDpattern120145MODE=H,VSEL=H,RPRE=12kmAf=50MHz,RANDOMpattern115135MODE=L,VSEL=H,PRE=OFFf=50MHz,RANDOMpattern115135MODE=L,VSEL=H,RPRE=12kIDDTZSerializerSupplyCurrentTPWDNB=0V250APower-down(AllotherLVCMOSInputs=0V)DESERIALIZERLVDSDCSPECIFICATIONSVTHDifferentialThresholdHighVoltageVCM=+1.
8V+50mVVTLDifferentialThresholdLowVoltage50mVRTInputTerminationInternaldifferentialoutputtermination90100130ΩbetweendifferentialpairsIINInputCurrentVIN=+2.
4V,VDD=3.
6V±100±250AVIN=0V,VDD=3.
6V±100±250ADESERIALIZERSUPPLYCURRENT(DVDD,PVDDANDAVDDPINS)(4)IDDRDeserializerTotalSupplyCurrentf=85MHz,CL=8pF,240265(includesloadcurrent)CHECKERBOARDpattern,QuadModemAf=85MHz,CL=8pF,190210RANDOMpattern,QuadModef=50MHz,CL=8pF,145185CHECKERBOARDpattern,DualModemAf=50MHz,CL=8pF,122140RANDOMpattern,DualModeIDDRZDeserializerSupplyCurrentPower-downPDB=0V(AllotherLVCMOSInputs=0V,100ARxIN[3:0](P/N)=0V)(4)DIGITAL,PLL,ANDANALOGVDDSSerializerInputTimingRequirementsforTCLKOverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitstCIPTxCLKINPeriodMODE=L(DualMode)20tCIP50nsMODE=H(QuadMode)11.
76tCIP25tCIHTxCLKINHighTime20MHz–50MHz0.
45x0.
55x0.
5xtCIPtCIPtCIPns40MHz–85MHz0.
45x0.
55x0.
5xtCIPtCIPtCIPtTCILTxCLKINLowTime20MHz–50MHz0.
45x0.
55x0.
5xtCIPFigure7tCIPtCIPns40MHz–85MHz0.
45x0.
55x0.
5xtCIPtCIPtCIPtCITTxCLKINTransitionTime20MHz–50MHz0.
51.
2Figure6ns40MHz–85MHz0.
51.
2tJITTxCLKINJitter±100psP-PCopyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
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comSerializerSwitchingCharacteristicsOverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitstLLHTLVDSLow-to-HighTransitionTimeNopre-emphasis350psFigure5tLHLTLVDSHigh-to-LowTransitionTime350pstSTCTxIN[31:0]SetuptoTxCLKINIOVDD=1.
71Vto1.
89V0Figure7nsIOVDD=3.
135Vto3.
465V0tHTCTxIN[31:0]HoldfromTxCLKINIOVDD=1.
71Vto1.
89V2.
5nsIOVDD=3.
135Vto3.
465V2.
25tPLDSerializerPLLLockTimeFigure94400x5000xnstCIPtCIPtLZDDataOutputLOWtoTRI-STATESee(1)510nsDelaytHZDDataOutputTRI-STATEtoHIGHSee(1)510nsDelaytSDSerializerPropagationDelay-Latencyf=50MHz,R_FB=H,4.
5tCIP+PRE=OFF,6.
77MODE=LFigure8f=50MHz,R_FB=L,4.
5tCIP+4.
5tCIP+4.
5tCIP+PRE=OFF,5.
637.
099.
29MODE=Lf=20MHz,R_FB=H,4.
5tCIP+4.
5tCIP+4.
5tCIP+PRE=OFF,6.
578.
7410.
74MODE=Lnsf=85MHz,R_FB=H,9.
0tCIP+PRE=OFF,6.
99MODE=Hf=85MHz,R_FB=L,9.
0tCIP+9.
0tCIP+9.
0tCIP+PRE=OFF,5.
977.
389.
64MODE=Hf=40MHz,R_FB=HL,9.
0tCIP+9.
0tCIP+9.
0tCIP+PRE=OFF,6.
308.
2610.
49MODE=HtLVSKDLVDSOutputSkewLVDSdifferentialoutputchannel-to-30500pschannelskewΛSTXBWJitterTransferFunction-3dBDualModeBandwidthf=50MHz2.
8Figure15MHzQuadMode2f=85MHzδSTXSerializerJitterTransferFunctionDualMode0.
3Peakingf=50MHzdBQuadMode0.
9f=85MHz(1)WhentheSerializeroutputisatTRI-STATEtheDeserializerwilllosePLLlock.
ResynchronizationMUSToccurbeforedatatransfer.
10SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013DeserializerSwitchingCharacteristicsOverrecommendedoperatingsupplyandtemperaturerangesunlessotherwisespecified.
SymbolParameterConditionsMinTypMaxUnitstROCPReceiverOutputClockPeriodtROCP=tCIP(DualMode)20tROCP50Figure11nstROCP=tCIP11.
76tROCP25(QuadMode)tRODCRxCLKOUTDutyCycle455055%tROTRLVCMOSLow-to-HighTransitionCL=8pF(lumpedload)3.
2nsTime(DualMode)Figure10tROTFLVCMOSHigh-to-LowTransition3.
5nsTimetROTRLVCMOSLow-to-HighTransitionCL=8pF(lumpedload)ns2.
4Time(QuadMode)tROTFLVCMOSHigh-to-LowTransitionns1.
9TimetROSCRxOUT[31:0]SetuptoRxCLKOUTf=50MHz0.
5x5.
6ns(DualMode)tROCPtROHCRxOUT[31:0]HoldtoRxCLKOUT0.
5x7.
4nstROCPtROSCRxOUT[31:0]SetuptoRxCLKOUTf=85MHz0.
5x3.
4ns(QuadMode)tROCPtROHCRxOUT[31:0]HoldtoRxCLKOUT0.
5x3.
4nstROCPtHZRDataOutputHightoTRI-STATEFigure13510nsDelaytLZRDataOutputLowtoTRI-STATE510nsDelaytZHRDataOutputTRI-STATEtoHigh510nsDelaytZLRDataOutputTRI-STATEtoLow510nsDelaytRDDeserializerPropagationDelay–f=20MHz5.
5xnsLatency(DualMode)tROCP+Figure123.
355.
5xnsf=50MHztROCP+(DualMode)6.
0012.
0xnsf=40MHztROCP+(QuadMode)7.
412.
0xnsf=85MHztROCP+(QuadMode)5.
7tRPLLS(1)DeserializerPLLLockTime20MHz–50MHz128kx(DualMode)nstROCPFigure1340MHz–85MHz256kx(QuadMode)nstROCPFigure13TOLJITDeserializerInputJitterTolerance0.
25UItLVSKRLVDSDifferentialInputSkew20MHz–85MHz0.
4xnsToleranceFigure17tROCP(1)tRPLLSisthetimerequiredbytheDeserializertoobtainlockwhenexitingpower-downmode.
Copyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11ProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
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comACTimingDiagramsandTestCircuitsFigure5.
SerializerLVDSTransitionTimesFigure6.
SerializerInputClockTransitionTimeFigure7.
SerializerSetup/HoldandHigh/LowTimesFigure8.
SerializerPropagationDelay12SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013Figure9.
SerializerPLLLockTimeFigure10.
DeserializerLVCMOSOutputTransitionTimeFigure11.
DeserializerSetupandHoldtimesFigure12.
DeserializerPropagationDelayCopyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
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comFigure13.
DeserializerPLLLockTimeandPDBTRI-STATEDelayFigure14.
DeserializerTRI_STATETestCircuitandTimingFigure15.
SerializerJitterTransfer14SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013Figure16.
SerializerVODTestCircuitDiagramFigure17.
LVDSDeserializerInputSkewCopyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
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comFUNCTIONALDESCRIPTIONTheDS92LV3241Serializer(SER)andDS92LV3242Deserializer(DES)chipsetisaflexibleSER/DESchipsetthattranslatesa32-bitparallelLVCMOSdatabusintoaquad(4pairs)ordual(2pairs)LVDSseriallinkswithembeddedclock.
TheDS92LV3241serializesthe32-bitwideparallelLVCMOSwordintofourortwohigh-speedLVDSserialdatastreamswithembeddedclock,scramblesandDCBalancesthedatatosupportACcouplingandenhancesignalquality.
TheDS92LV3242receivesthedual/quadLVDSserialdatastreamsandconvertsitbackintoa32-bitwideparalleldatawitharecoveredclock.
Thedual/quadLVDSserialdatastreamreducescablesize,thenumberofconnectors,andeasesskewconcerns.
Parallelclocksbetween20MHzto85MHzaresupportedbythedualorquadoperatingmodes.
ThemodesareuserselectablethroughacontrolpinonSerializer.
Indualmode,thetransmitclockfrequencysupports20MHzto50MHzandinquadmodethetransmitclockfrequencysupports40MHzto85MHz.
Inthedualmodeconfiguration,theembeddedclockLVDSserialstreamshaveaneffectivedatapayloadof640Mbps(20MHzx32-bit)to1.
6Gbps(50MHzx32-bit).
Inthequadmodeconfiguration,theembeddedclockLVDSserialstreamshaveaneffectivedatapayloadof1.
28Gbps(40MHzx32-bit)to2.
72Gbps(85MHzx32-bit).
TheSER/DESchipsetisdesignedtotransmitdataoverlongdistancesthroughstandardtwistedpair(TWP)cables.
Thedifferentialinputsandoutputsareinternallyterminatedwith100ohmresistorstoprovidesourceandloadtermination,minimizestublength,toreducecomponentcountandfurtherminimizeboardspace.
TheDEScanattainlocktoadatastreamwithouttheuseofaseparatereferenceclocksource;greatlysimplifyingsystemcomplexityandreducingoverallcost.
TheDESsynchronizestotheSERregardlessofdatapattern,deliveringtrueautomatic"plug-and-lock"performance.
Itwilllocktotheincomingserialstreamwithouttheneedofspecialtrainingpatternsorspecialsynccharacters.
TheDESrecoverstheclockanddatabyextractingtheembeddedclockinformation,deskewstheserialdatachannelsandthendeserializesthedata.
TheDESalsomonitorstheincomingclockinformation,determineslockstatus,andassertstheLOCKoutputhighwhenlockoccurs.
InadditiontheDESalsosupportsanoptionalAT-SPEEDBIST(BuiltInSelfTest)mode,BISTerrorflag,andLOCKstatusreportingpin.
TheSERandtheDEShaveapowerdowncontrolsignaltoenableefficientoperationinvariousapplications.
DESKEWANDCHANNELALIGNMENTTheDESautomaticallydetectsdualorquadserialchannelmodeandprovidesaclockalignmentanddeskewfunctionwithouttheneedforanyspecialtrainingpatterns.
Duringthelockingphase,theembeddedclockinformationisrecoveredonallchannelsandtheseriallinksareinternallysynchronized,de-skewed,andautoaligned.
TheinternalCDRcircuitrywilldynamicallycompensateforupto0.
4timestheparallelclockperiodofperchannelphaseskew(channel-to-channel)betweentherecoveredclocksoftheseriallinks.
ThisprovidesskewphasetolerancefrommismatchesininterconnectwiressuchasPCBtracerouting,cablepair-to-pairlengthdifferences,andconnectorimbalances.
DATATRANSFERAfterSERlockisestablished(SERPLLtoTxCLKIN),theinputsTxIN0–TxIN31arelatchedintotheencoderblock.
DataisclockedintotheSERbytheTxCLKINinput.
TheedgeofTxCLKINusedtostrobethedataisselectableviatheR_FB(SER)pin.
R_FB(SER)highselectstherisingedgeforclockingdataandlowselectsthefallingedge.
TheSERoutputs(TxOUT[3:0]+/-)areintendedtodriveaACCoupledpoint-to-pointconnections.
TheSERlatches32-bitparalleldatabusandperformsseveraloperationstoit.
The32-bitparalleldataisinternallyencodedandsequentiallytransmittedoverthetwohigh-speedserialLVDSchannels.
Foreachserialchannel,theSERtransmits20bitsofinformationperpayloadtotheDES.
Inthedualmode,the32-bitparalleldataisscaledandbit-mappedacrosstwo20-bitdatapayloadsperchannel,resultinginaperchannelthroughputof400Mbpsto1.
0Gbps(20bitsxclockrate).
Underquadmode,theinternalPLLoperatesattheinputclockfrequencyrate.
The32bitsarebit-mappedandsequencedperevery2cyclesattheTxCLKINfrequencyacrossfourchannels,resutlinginaperchannelthroughputof400Mbpsto850Mbps(20bitsxclockrate/2).
Thechipsetsupportsfrequencyrangesof20MHzto85MHz.
16SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013WhenalloftheDESchannelsobtainlock,theLOCKpinisdrivenhighandsynchronouslydeliversvaliddataandrecoveredclockontheoutput.
TheDESlockstotheclock,usesittogeneratemultipleinternaldatastrobes,andthendrivestherecoveredclocktotheRxCLKOUTpin.
Therecoveredclock(RxCLKOUT)issynchronoustothedataontheRxOUT[31:0]pins.
WhileLOCKishigh,dataonRxOUT[31:0]isvalid.
Otherwise,RxOUT[31:0]isinvalid.
ThepolarityoftheRxCLKOUTedgeiscontrolledbyitsR_FB(DES)input.
RxOUT[31:0],LOCKandRxCLKOUToutputswilleachdriveamaximumof8pFload.
RENcontrolsTRI-STATEforRxOUT0–RxOUT31andtheRxCLKOUTpinontheDES.
RESYNCHRONIZATIONIntheabsenceofdatatransitionsononeofthechannelsintotheDES(e.
g.
alossofthelink),itwillautomaticallytrytoresynchronizeandre-establishlockusingthestandardlocksequenceonthemasterchannel(Channel0).
Forexample,iftheembeddedclockisnotdetectedonetimeinsuccessiononanyoftheseriallinks,theLOCKpinisdrivenlow.
TheDESthenmonitorsthemasterchannelforlock,oncethatisobtained,thesecondchannelislockedandaligned.
ThelogicstateoftheLOCKsignalindicateswhetherthedataonRxOUTisvalid;whenitishigh,thedataisvalid.
ThesystemmaymonitortheLOCKpintodeterminewhetherdataontheRxOUTisvalid.
POWERDOWNThePowerdownstateisalowpowersleepmodethattheSERandDESmayusetoreducepowerwhennodataisbeingtransferred.
TherespectivePDBpinsareusedtoseteachdeviceintopowerdownmode,whichreducessupplycurrentintotheArange.
TheSERentersPowerdownwhentheSERPDBpinisdrivenlow.
InPowerdown,thePLLstopsandtheoutputsgointoTRI-STATE,disablingloadcurrentandreducingcurrentsupply.
ToexitPowerdown,SERPDBmustbedrivenhigh.
WhentheSERexitsPowerdown,itsPLLmustlocktoTxCLKINbeforeitisreadyforsendingdatatotheDES.
ThesystemmustthenallowtimefortheDEStolockbeforedatacanberecovered.
TheDESentersPowerdownmodewhenDESPDBisdrivenlow.
InPowerdownmode,thePLL'sstopandtheoutputsenterTRI-STATE.
TobringtheDESblockoutofthePowerdownstate,thesystemdrivesDESPDBhigh.
BoththeSERandDESmustrelockbeforedatacanbetransferredfromHostandreceivedbytheTarget.
TheDESwillstartupandassertLOCKhighwhenitislockedtotheembeddedclocks.
SeealsoFigure13.
TRI-STATEFortheSER,TRI-STATEisenteredwhentheSERPDBpinisdrivenlow.
ThiswillTRI-STATEthedriveroutputpinsonTxOUT[3:0]+/-.
Inaddition,whenMODE=0(dualmode),theTxOUT[3:2]+/-outputspinsareinTRI-STATE.
WhenyoudrivetheRENorDESPDBpinlow,theDESoutputpins(RxOUT[31:0])andRxCLKOUTwillenterTRI-STATE.
TheLOCKoutputremainsactive,reflectingthestateofthePLL.
TheDESinputpinsarehighimpedanceduringreceiverPowerdown(DESPDBlow)andpower-off(VDD=0V).
SeealsoFigure13.
TRANSMITPARALLELDATAANDCONTROLINPUTSTheDS92LV3241operatesonacoresupplyvoltageof3.
3Vwithanoptionaldigitalsupplyvoltagefor1.
8V,low-swing,inputsupport.
TheSERsingle-ended(32-bitparalleldataandcontrolinputs)pinsare1.
8Vand3.
3VLVCMOSlogiclevelcompatibleandisconfiguredthroughtheIOVDDinputsupplyrail.
If1.
8Visrequired,theIOVDDpinmustbeconnectedtoa1.
8Vsupplyrail.
Alsowhenpowerisappliedtothetransmitter,IOVDDpinmustbeappliedbeforeorsimultaneouslywithotherpowersupplypins(3.
3V).
If1.
8Vinputswingisnotrequired,thispinshouldbetiedtothecommon3.
3Vrail.
Duringnormaloperation,thevoltagelevelontheIOVDDpinsmustnotchange.
PRE-EMPHASISTheSERLVDSLineDriverfeaturesaPre-Emphasisfunctionusedtocompensateforextralongorlossytransmissionmedia.
ThesameamountofPre-Emphasisisappliedonalloftheenableddifferentialoutputchannels.
CabledriveisenhancedwithauserselectablePre-Emphasisfeaturethatprovidesadditionaloutputcurrentduringtransitionstocounteractcableloadingeffects.
Thetransmissiondistancewillbelimitedbythelosscharacteristicsandqualityofthemedia.
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comToenablethePre-Emphasisfunction,the"PRE"pinrequiresoneexternalresistor(Rpre)toVSS(GND)inordertosetthepre-emphasizedcurrentlevel.
Optionsinclude:1.
NormalOutput(noPre-emphasis)–LeavethePREpinopen,includeanRpad,donotpopulate.
2.
EnhancedOutput(Pre-emphasisenabled)–connectaresistoronthePREpintoVss.
ValuesoftheRpreResistorshouldbebetween12KOhmand100KOhm.
Valueslessthan6KOhmshouldnotbeused.
TheamountofPre-EmphasisforagivenmediawilldependonthetransmissiondistanceandFmaxoftheapplication.
Ingeneral,toomuchPre-Emphasiscancauseoverorundershootatthereceiverinputpins.
Thiscanresultinexcessivenoise,crosstalk,reducedFmax,andincreasedpowerdissipation.
Forshortercablesordistances,Pre-Emphasisistypicallynotberequired.
SignalqualitymeasurementsshouldbemadeattheendoftheapplicationcabletoconfirmtheproperamountofPre-Emphasisforthespecificapplication.
ThePre-EmphasiscircuitincreasesthedrivecurrenttoI=48/(RPRE).
ForexampleifRPRE=15kOhms,thenthecurrentisincreasedbyanadditional3.
2mA.
TocalculatetheexpectedincreaseinVOD,multiplytheincreaseincurrentby50ohms.
SoforthecaseofRPRE=15kOhms,theboosttoVODwouldbe3.
2mAx50Ohms=160mV.
Thedurationofthecurrentiscontrolledtoonebitbytime.
Ifmorethanonebitvalueisrepeatedinthenextcycle(s),thePre-Emphasiscurrentisturnedoff(backtothenormaloutputcurrentlevel)forthenextbit(s).
Toboosthighfrequencydataandpre-equalizetehdatapatternreduceISI(Inter-SymbolInterference)improvingtheresultingeyepattern.
VODSELECTTheSERLineDriverDifferentialOutputVoltage(VOD)magnitudeisselectable.
TwolevelsareprovidedandareselectedbytheVSELpin.
WhenthispinisLOW,normaloutputlevelsareobtained.
FormostapplicationsettheVSELpinLOW.
WhenthispinisHIGH,theoutputcurrentisincreasedtodoubletheVODlevel.
Usethissettingonlyforextralongcablesorhigh-lossinterconnects.
Table1.
VODControlVSELPinSettingEffectLOWSmallVOD,typ440mVP-PHIGHLargeVOD,typ850mVP-PSERIALINTERFACETheseriallinksbetweentheDS92LV3241andtheDS92LV3242areintendedforabalanced100Ohminterconnects.
ThelinksmustbeconfiguredasanACcoupledinterface.
TheSERandDESsupportAC-coupledinterconnectsthroughanintegratedDCbalancedencoding/decodingscheme.
AnexternalACcouplingcapacitorsmustbeplaced,inseries,intheLVDSsignalpath.
TheDESinputstageisdesignedforAC-couplingbyprovidingabuilt-inACbiasnetworkwhichsetstheinternalcommonmodevoltage(VCM)to+1.
8V.
Forthehigh-speedLVDStransmission,smallfootprintpackagesshouldbeusedfortheACcouplingcapacitors.
Thiswillhelpminimizedegradationofsignalqualityduetopackageparasitics.
NPOclass1orX7Rclass2typecapacitorsarerecommended.
50WVDCshouldbetheminimumusedforbestsystem-levelESDperformance.
Themostcommonusedcapacitorvaluefortheinterfaceis100nF(0.
1uF)capacitor.
Onesetofcapacitorsmaybeusedforisolation.
Twosets(bothends)mayalsobeusedformaximumisolationofboththeSERandDESfromcablefaults.
TheDS92LV3241andtheDS92LV3242differentialI/O'sareinternallyterminatedwith100Ohmresistancebetweentheinvertingandnon-invertingpinsanddonotrequireexternaltermination.
Theinternalresistancevaluewillbebetween90ohmand130ohm.
Theintegratedterminationsimprovesignalintegrity,reducestublengths,anddecreasetheexternalcomponentcountresultinginspacesavings.
18SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013AT-SPEEDBISTFEATURETheDS92LV3241/DS92LV3242seriallinkisequippedwithbuilt-inself-test(BIST)capabilitytosupportbothsystemmanufacturingandfielddiagnostics.
BISTmodeisintendedtochecktheentirehigh-speedserialinterfaceatfulllink-speedwithouttheuseofspecializedandexpensivetestequipment.
ThisfeatureprovidesasimplemethodforasystemhosttoperformdiagnostictestingofbothSERandDES.
TheBISTfunctioniseasilyconfiguredthroughtheSERBISTENpin.
WhentheBISTmodeisactivated,theSERgeneratesaPRBS(pseudo-randombitsequence)pattern(2^7-1).
ThispatterntraverseseachlanetotheDESinput.
TheDS92LV3242includesanon-chipPRBSpatternverificationcircuitthatchecksthedatapatternforbiterrorsandreportsanyerrorsonthedataoutputpinsoftheDES.
TheAT-SpeedBISTfeatureisenabledbysettingtheBISTENtoHighonSER.
TheBISTENinputmustbeHighorLowfor4ormoreTxCLKINclockcyclesinordertoactivateordeactivatetheBISTmode.
AninputclocksignalfortheSerializerTxCLKINmustalsobeappliedduringtheentireBISToperation.
OnceBISTisenabled,alltheSerializerdatainputs(TxIN[31:0])areignoredandtheDESoutputs(RxOUT[31:0])arenotavailable.
Next,theinternaltestpatterngeneratorforeachchannelstartstransmissionoftheBISTpatternfromSERtoDES.
TheDESBISTmodewillbeautomaticallyactivatedbythissequence.
Amaximumof128consecutivesclocksymbolsonDS92LV3242DESisneededtodetectBISTenablefunction.
TheBISTisimplementedwithindependenttransmitandreceivepathsforthefourseriallinks.
EachchannelontheDESwillbeindividuallycomparedagainsttheexpectedbitsequenceoftheBISTpattern.
Figure18.
BISTTestEnabled/DisabledUndertheBISTmode,theDESparalleloutputsonRxOUT[31:0]aremultiplexedtorepresentBISTstatusindicators.
Thepass/failstatusoftheBISTisrepresentedbyaPassflagalongwithanErrorcounter.
ThePassflagoutputisdesignatedonDESRxOUT0forChannel0,andRxOUT8forChannel1.
TheDES'sPLLmustfirstbelockedtoensurethePassstatusisvalid.
TheoutputPassstatuspinwillstayLOWandthentransitiontoHighonce44*10^6symbolsareachievedacrosseachoftherespectivetransmissionlinks.
Thetotaltimedurationofthetestisdefinedbythefollowing:44*10^6xtCIP.
AfterthePassoutputflagsreachaHIGHstate,itwillnotdroptoLOWevenifsubsequentbiterrorsoccurredaftertheBISTdurationperiod.
Errorswillbereportediftheinputtestpatterncomparisondoesnotmatch.
Ifanerror(miss-compare)occurs,thestatusbitislatchedonRxOUT[7:1]forChannel0,andRxOUT[15:9]forChannel1;reflectingthenumberoferrorsdetected.
Wheneveradatabitcontainsanerror,theErrorcounterbitoutputforthatcorrespondingchannelgoesHIGH.
Eachcounterfortheseriallinkutilizesa7-bitcountertostorethenumberoferrorsdetected(0to127max).
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ti.
comFigure19.
BISTDiagramforDifferentBitErrorCasesTYPICALAPPLICATIONCONNECTIONFigure20showsatypicalapplicationoftheDS92LV3241Serializer(SER).
Thedifferentialoutputsutilize100nFcouplingcapacitorstotheseriallines.
Bypasscapacitorsareplacednearthepowersupplypins.
AsystemGPO(GeneralPurposeOutput)controlsthePDBandBISTENpins.
InthisapplicationtheR_FB(SER)pinistiedLowtolatchdataonthefallingedgeoftheTxCLKIN.
Inthisapplicationthelinkisshort,thereforetheVSELpinistiedLOWforthestandardoutputswinglevel.
ThePre-emphasisinpututilizesaresistortogroundtosettheamountofpre-emphasisdesiredbytheapplication.
ConfigurationpinsforthetypicalapplicationareshownforSER:PDB–PowerDownControlInput–ConnecttohostortieHIGH(alwaysON)BISTEN–ModeInput-tieLOWifBISTmodeisnotused,orconnecttohostVSEL–tieLOWfornormalVODmagnitude(applicationdependant)MODE–Forclockratesbetween20MHzand50MHztieLOW,for40MHzto85MHztieHIGHPRE–Leaveopenifnotrequired(haveaRpadoptiononPCB)RSVD1&RSVD2–tieLOW20SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013Thereareeightpowerpinsforthedevice.
Thesemaybebussedtogetheronacommon3.
3Vplane(3.
3VLVCMOSI/Ointerface).
If1.
8Vinputswinglevelforparalleldataandcontrolpinsarerequired,connecttheIOVDDpinto1.
8V.
Ataminimum,eight0.
1uFcapacitorsshouldbeusedforlocalbypassing.
Figure20.
DS92LV3241TypicalConnectionDiagramFigure21showsatypicalapplicationoftheDS92LV3242Deserializer(DES).
Thedifferentialinputsutilize100nFcouplingcapacitorsintheseriallines.
Bypasscapacitorsareplacednearthepowersupplypins.
AsystemGPO(GeneralPurposeOutput)controlsthePDBpin.
InthisapplicationtheR_FB(DES)pinistiedLowtostrobethedataonthefallingedgeoftheRxCLKOUT.
TheRENsignalisnotusedandistiedHighalso.
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comConfigurationpinsforthetypicalapplicationareshownforDES:PDB–PowerDownControlInput–ConnecttohostortieHIGHREN–tieHIGHifnotused(usedtoMUXtwoDEStoonetargetdevice)RSVD–tieLOWFigure21.
DS92LV3242TypicalConnectionDiagram22SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013ApplicationsInformationTRANSMISSIONMEDIATheSERandDESareusedinAC-coupledpoint-to-pointconfigurations,throughaPCBtrace,orthroughtwistedpaircables.
InterconnectforLVDStypicallyhasadifferentialimpedanceof100Ohms.
Usecablesandconnectorsthathavematcheddifferentialimpedancetominimizeimpedancediscontinuities.
Inmostapplicationsthatinvolvecables,thetransmissiondistancewillbedeterminedondataratesinvolved,acceptablebiterrorrateandtransmissionmedium.
PCBLAYOUTANDPOWERSYSTEMCONSIDERATIONSCircuitboardlayoutandstack-upfortheLVDSSER/DESdevicesshouldbedesignedtoprovidelow-noisepowerfeedtothedevice.
Goodlayoutpracticewillalsoseparatehighfrequencyorhigh-levelinputsandoutputstominimizeunwantedstraynoisepickup,feedbackandinterference.
Powersystemperformancemaybegreatlyimprovedbyusingthindielectrics(2to4mils)forpower/groundsandwiches.
ThisarrangementprovidesplanecapacitanceforthePCBpowersystemwithlow-inductanceparasitics,whichhasprovenespeciallyeffectiveathighfrequencies,andmakesthevalueandplacementofexternalbypasscapacitorslesscritical.
ExternalbypasscapacitorsshouldincludebothRFceramicandtantalumelectrolytictypes.
RFcapacitorsmayusevaluesintherangeof0.
01uFto0.
1uF.
Tantalumcapacitorsmaybeinthe2.
2uFto10uFrange.
Voltageratingofthetantalumcapacitorsshouldbeatleast5Xthepowersupplyvoltagebeingused.
Surfacemountcapacitorsarerecommendedduetotheirsmallerparasitics.
Whenusingmultiplecapacitorspersupplypin,locatethesmallervalueclosertothepin.
Alargebulkcapacitorisrecommendedatthepointofpowerentry.
Thisistypicallyinthe50uFto100uFrangeandwillsmoothlowfrequencyswitchingnoise.
Itisrecommendedtoconnectpowerandgroundpinsdirectlytothepowerandgroundplaneswithbypasscapacitorsconnectedtotheplanewithviasonbothendsofthecapacitor.
Connectingpowerorgroundpinstoanexternalbypasscapacitorwillincreasetheinductanceofthepath.
AsmallbodysizeX7Rchipcapacitor,suchas0603,isrecommendedforexternalbypass.
Itssmallbodysizereducestheparasiticinductanceofthecapacitor.
Theusermustpayattentiontotheresonancefrequencyoftheseexternalbypasscapacitors,usuallyintherangeof20-30MHzrange.
Toprovideeffectivebypassing,multiplecapacitorsareoftenusedtoachievelowimpedancebetweenthesupplyrailsoverthefrequencyofinterest.
Athighfrequency,itisalsoacommonpracticetousetwoviasfrompowerandgroundpinstotheplanes,reducingtheimpedanceathighfrequency.
Somedevicesprovideseparatepowerandgroundpinsfordifferentportionsofthecircuit.
Thisisdonetoisolateswitchingnoiseeffectsbetweendifferentsectionsofthecircuit.
SeparateplanesonthePCBaretypicallynotrequired.
PinDescriptiontablestypicallyprovideguidanceonwhichcircuitblocksareconnectedtowhichpowerpinpairs.
Insomecases,anexternalfiltermanybeusedtoprovidecleanpowertosensitivecircuitssuchasPLLs.
Useatleastafourlayerboardwithapowerandgroundplane.
LocateLVCMOSsignalsawayfromtheLVDSlinestopreventcouplingfromtheLVCMOSlinestotheLVDSlines.
Closely-coupleddifferentiallinesof100OhmsaretypicallyrecommendedforLVDSinterconnect.
Thecloselycoupledlineshelptoensurethatcouplednoisewillappearascommonmodeandthusisrejectedbythereceivers.
Thetightlycoupledlineswillalsoradiateless.
PLUGANDGOTheSerializerandDeserializerdevicessupporthotpluggingoftheserialinterconnect.
Theautomaticreceiverlocktorandomdata"plug&go"capabilityallowstheDS92LV3242toobtainlocktotheactivedatastreamduringaliveinsertionevent.
LVDSINTERCONNECTGUIDELINESForfulldetails,seetheChannel-LinkPCBandInterconnectDesign-InGuidelines(literaturenumberSNLA008)andtheTransmissionLineRAPIDESIGNEROperationandApplicationsGuide(literaturenumberSNLA035).
Use100OhmcoupleddifferentialpairsUsetheS/2S/3Sruleinspacings–S=spacebetweenthepair–2S=spacebetweenpairsCopyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242SNLS314D–SEPTEMBER2009–REVISEDAPRIL2013www.
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com–3S=spacetoLVCMOSsignalMinimizethenumberofviasUsedifferentialconnectorswhenoperatingabove500MbpslinespeedMaintainbalanceofthetracesMinimizeskewwithinthepairTerminateasclosetotheTXoutputsandRXinputsaspossibleAdditionalgeneralguidancecanbefoundintheLVDSOwner'sManual(literaturenumberSNLA187),whichisavailableinPDFformatfromtheTILVDS&CMLSolutionswebsite.
TypicalPerformanceCharacteristicsThewaveformsbelowillustratethetypicalperformanceoftheDS92LV3241.
TheSERwasgivenaPCLKandconfiguredasdescribedbeloweachpicture.
InallofthepicturestheSERwasconfiguredwithBISTENpinsettologicHIGH.
Eachwaveformwastakenbyusingahighimpedancelowcapacitancedifferentialprobetoprobeacrossa100ohmdifferentialterminationresistorwithinoneinchofTxOUT0+/-.
Figure22.
SerialOutputQuadMode,85MHz,VSEL=H,NoFigure23.
SerialOutputQuadMode,85MHz,VSEL=L,NoPre-EmphasisPre-EmphasisFigure24.
SerialOutputDualMode,50MHz,VSEL=H,NoFigure25.
SerialOutputDualMode,50MHz,VSEL=L,NoPre-EmphasisPre-Emphasis24SubmitDocumentationFeedbackCopyright2009–2013,TexasInstrumentsIncorporatedProductFolderLinks:DS92LV3241DS92LV3242DS92LV3241,DS92LV3242www.
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comSNLS314D–SEPTEMBER2009–REVISEDAPRIL2013REVISIONHISTORYChangesfromRevisionC(April2013)toRevisionDPageChangedlayoutofNationalDataSheettoTIformat24Copyright2009–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25ProductFolderLinks:DS92LV3241DS92LV3242PACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesDS92LV3241TVS/NOPBACTIVETQFPPAG64160RoHS&GreenSNLevel-3-260C-168HR-40to85DS92LV3241TVSDS92LV3241TVSX/NOPBACTIVETQFPPAG641000RoHS&GreenSNLevel-3-260C-168HR-40to85DS92LV3241TVSDS92LV3242TVS/NOPBACTIVETQFPPAG64160RoHS&GreenSNLevel-3-260C-168HR-40to85DS92LV3242TVSDS92LV3242TVSX/NOPBACTIVETQFPPAG641000RoHS&GreenSNLevel-3-260C-168HR-40to85DS92LV3242TVS(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantDS92LV3241TVSX/NOPBTQFPPAG641000330.
024.
413.
013.
01.
4516.
024.
0Q2DS92LV3242TVSX/NOPBTQFPPAG641000330.
024.
413.
013.
01.
4516.
024.
0Q2PACKAGEMATERIALSINFORMATIONwww.
ti.
com24-Apr-2013PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)DS92LV3241TVSX/NOPBTQFPPAG641000367.
0367.
045.
0DS92LV3242TVSX/NOPBTQFPPAG641000367.
0367.
045.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com24-Apr-2013PackMaterials-Page2MECHANICALDATAMTQF006A–JANUARY1995–REVISEDDECEMBER1996POSTOFFICEBOX655303DALLAS,TEXAS75265PAG(S-PQFP-G64)PLASTICQUADFLATPACK0,13NOM0,250,450,75SeatingPlane0,05MIN4040282/C11/96GagePlane330,170,27164817,50TYP4964SQ9,801,050,9511,8012,201,20MAX10,20SQ17320,080,50M0,080°–7°NOTES:A.
Alllineardimensionsareinmillimeters.
B.
Thisdrawingissubjecttochangewithoutnotice.
C.
FallswithinJEDECMS-026IMPORTANTNOTICEANDDISCLAIMERTIPROVIDESTECHNICALANDRELIABILITYDATA(INCLUDINGDATASHEETS),DESIGNRESOURCES(INCLUDINGREFERENCEDESIGNS),APPLICATIONOROTHERDESIGNADVICE,WEBTOOLS,SAFETYINFORMATION,ANDOTHERRESOURCES"ASIS"ANDWITHALLFAULTS,ANDDISCLAIMSALLWARRANTIES,EXPRESSANDIMPLIED,INCLUDINGWITHOUTLIMITATIONANYIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEORNON-INFRINGEMENTOFTHIRDPARTYINTELLECTUALPROPERTYRIGHTS.
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