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DatasheetDS000622AS7026GGBiosensorv2-002019-Sep-17DocumentFeedbackAS7026GGContentGuideDatasheetPUBLICDS000622v2-002019-Sep-171082ContentGuide1GeneralDescription.
31.
1KeyBenefits&Features31.
2Applications41.
3BlockDiagram.
42OrderingInformation.
53PinAssignment63.
1PinDiagram.
63.
2PinDescription64AbsoluteMaximumRatings.
85ElectricalCharacteristics.
96FunctionalDescription.
156.
1OpticalAnalogFrontEnd.
157RegisterDescription.
177.
1RegisterOverview.
177.
2IC.
948ApplicationInformation1058.
1ApplicationExamples.
1059PackageDrawings&Markings.
10610RevisionInformation.
10711LegalInformation108DocumentFeedbackAS7026GGGeneralDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710831GeneralDescriptionTheoperationoftheAS7026GGisbasedonphotoplethysmography(PPG)andelectrocardiogram(ECG).
PPGisthemostusedHRMmethod,whichmeasuresthepulseratebysamplinglightmodulatedbythebloodvessels,whichexpandandcontractasbloodpulsesthroughthem.
ECGisthereferenceforanymeasurementofthebiopotentialgeneratedbytheheart.
TheAS7026GGissupportedbyalgorithmsconvertingthePPGandECGreadingsintodigitalHRM,HRVandcontinuousbloodpressurevalues.
Thecuff-lessbloodpressuremeasurementhasbeenoptimizedtofulltheIEEEStd1708-2014.
ThemoduleincludestheLEDs,photo-sensor,analogfront-end(AFE)andsequenceraswellasapplicationsoftware.
InadditiontoHRM/HRVandbloodpressure,themodulealsoenablesskintemperatureandskinresistivitymeasurementsbyprovidinginterfacestoexternalsensors.
TheAS7026GG'slow-powerdesignandsmallformfactorisparticularlywellsuitedtoapplicationinfitnessbands,smartwatches,sportswatchesandsmartpatches,inwhichboardspaceislimitedandinwhichuserslookforextended,multi-dayintervalsbetweenbatteryrecharges.
1.
1KeyBenefits&FeaturesThebenefitsandfeaturesofAS7026GG,Biosensor,arelistedbelow:Figure1:AddedValueofUsingAS7026GGBenefitsFeaturesAddressallskintypesImprovedopticalpathAllowssmallestapplicationsizee.
g.
narrowHRMmeasurementbandSingledeviceintegratedopticalsolutionElectrocardiogramECGwithdryelectrodesEmbeddedlownoiseanalogfrontendforECGsignalsacquisitionEnablingbloodpressuremeasurementsSynchronizedPPGandECGacquisitionGoodHRMmeasurementqualityLownoiseanalogopticalfrontendAdditionalinformationforenduserAnalogelectricalfrontend(e.
g.
fortemperaturesensingusingaNTCorgalvanicskinresistivity(GSR))IntegratedinterferencefilterReducenegativeeffectofstrongsunlightLongoperatingtimeHardwaresequencertooffloadprocessorAdjustableLEDdriverwithcurrentcontrolDocumentFeedbackAS7026GGGeneralDescriptionDatasheetPUBLICDS000622v2-002019-Sep-171084BenefitsFeaturesWorksreliablywithambientlightEmbeddedambientlightrejectionsystem1.
2ApplicationsOpticalsensorplatformFitnessbandSmartwatchHeartratemonitorCuff-lessbloodpressuremeasurements1.
3BlockDiagramThefunctionalblocksofthisdeviceareshownbelow:Figure2:FunctionalBlocksofAS7026GGDocumentFeedbackAS7026GGOrderingInformationDatasheetPUBLICDS000622v2-002019-Sep-1710852OrderingInformationOrderingCodePackageMarkingDeliveryFormDeliveryQuantityAS7026GG-COLTOLGA-20n.
a.
Tape&Reel5000pcs/reelAS7026GG-COLMOLGA-20n.
a.
Tape&Reel1000pcs/reelDocumentFeedbackAS7026GGPinAssignmentDatasheetPUBLICDS000622v2-002019-Sep-1710863PinAssignment3.
1PinDiagramFigure3:AS7026GGOpticalModulePin-Out–TopView(nottoscale)3.
2PinDescriptionFigure4:PinDescriptionofAS7026GGPinNumberPinNamePinType(1)Description1VD1AISupplyvoltageforLEDD12VD3AIConnectiontocurrentsink33GNDGPowersupplyground.
AllvoltagesarereferencedtoGND.
4ECG_INPAIECGamplifierpositiveinput5ECG_INNAIECGamplifiernegativeinput6ECG_REFAOECGamplifierreferenceoutputDocumentFeedbackAS7026GGPinAssignmentDatasheetPUBLICDS000622v2-002019-Sep-171087PinNumberPinNamePinType(1)Description7ENABLEDIEnableinputforAS7026GG.
Activehigh.
SettingthisinputtolowresetsallinternalregistersandtheAS7026GGenterspowerdownmode.
SettingithighallowsoperationoftheAS7026GG.
IfENABLEisnotused(AS7026GGalwaysenabled),connecttoVDD.
8INTDOOpendraininterruptoutputpin.
Activelow.
9SCLDIICserialclockinputterminal–thedevicedoesnotuseclockstretchingthereforeSCLisonlyaninputterminal.
10SDADIICserialdataI/Oterminal–opendrain.
11VDDPSupplyvoltage.
Connecta2.
2FcapacitortoGND.
12GPIO0GPIOGeneralpurposeinput/output13GPIO1GPIOGeneralpurposeinput/output14GPIO2GPIOGeneralpurposeinput/output15GPIO3GPIOGeneralpurposeinput/output16V_LDOAO1.
9Voutputvoltage.
Connect2.
2FcapacitortoGND(e.
g.
0402sizedcapacitorGRM153R60J225ME95or0201sizedGRM033R60J225ME47fromMurata–needstohave>1Fwith1.
0Vvoltagebias);donotloadexternally17AGNDGNDAnalogground.
ConnecttolownoiseGND18SIGREFAOAnalogreferenceoutput.
Connect2.
2FcapacitortoGND(e.
g.
0402sizedcapacitorGRM153R60J225ME95or0201sizedGRM033R60J225ME47fromMurata–needstohave>1Fspecifiedfor1.
0Vvoltagebias);donotloadexternallyThetypicaloperatingvoltageonthispinis0.
6V(sigref_en=1)19VD2AISupplyvoltageforLEDD220VD4AISupplyvoltageforLEDD4(1)DIDigitalInputDODigitalOutputAIAnalogInputAOAnalogOutputGPIOGeneralPurposeIOPPowerSupplyDocumentFeedbackAS7026GGAbsoluteMaximumRatingsDatasheetPUBLICDS000622v2-002019-Sep-1710884AbsoluteMaximumRatingsStressesbeyondthoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.
Thesearestressratingsonly.
Functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"OperatingConditions"isnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.
Figure5AbsoluteMaximumRatingsofAS7026GGSymbolParameterMinMaxUnitCommentsElectricalParametersVSUP/VGNDSupplyVoltagetoGround6VVINInputPinVoltagetoGroundpinsGPIO0/1/2/3-0.
3VDD+0.
3Vmax.
6VVDiodetoVDDVIN-OTHERInputPinVoltagetoGroundpinsSCL/SDA/INT/ENABLEandVD1/VD2/VD3/VD4-0.
35.
5VNointernaldiodetoVDDorV_LDOVVD1/2/3/4_INTERNALVoltagebetweeninternalpinofVD1-VD4toVDDVDD+0.
3VVInternaldiodebetweencurrentsource(internalnodeatanodeoftheLEDifthepinhasaLEDotherwiseVD1/2/3/4pin)andVDDVIN-LDOInputPinVoltagetoGroundforpinV_LDO-0.
32.
0VVDiodetoVDDVIN-LDO_DIODEInputPinVoltagetoGroundpinsforECG_INP/ECG_INN/ECG_REF/SIGREF-0.
32.
0VDiodetoV_LDOVGND-AGNDAnalogtopowergroundvoltagedifference-0.
3+0.
3VISCRInputCurrent(latch-upimmunity)±100mAJEDECJESD78DNov2011ElectrostaticDischargeESDHBMElectrostaticDischargeHBM±2kVJS-001-2014TemperatureRangesandStorageConditionsTSTRGStorageTemperatureRange-4085°CTBODYPackageBodyTemperature260°CIPC/JEDECJ-STD-020(1)RHNCRelativeHumidity(non-condensing)585%MSLMoistureSensitivityLevel3Maximumfloorlifetimeof168h(1)Thereflowpeaksolderingtemperature(bodytemperature)isspecifiedaccordingtoIPC/JEDECJ-STD-020"Moisture/ReflowSensitivityClassificationforNonhermeticSolidStateSurfaceMountDevices.
"TheleadfinishforPb-freeleadedpackagesis"MatteTin"(100%Sn)DocumentFeedbackAS7026GGElectricalCharacteristicsDatasheetPUBLICDS000622v2-002019-Sep-1710895ElectricalCharacteristicsAlllimitsareguaranteed.
TheparameterswithMinandMaxvaluesareguaranteedwithproductiontestsorSQC(StatisticalQualityControl)methods.
VDD=2.
7Vto5.
5V,typ.
valuesareatTAMB=25°C(unlessotherwisespecified).
Figure6:ElectricalCharacteristicsofAS7026GGSymbolParameterConditionsMinTypMaxUnitVDDSupplyvoltage2.
73.
85.
5VTAMBOperatingfree-airtemperature3070°CIDDSupplycurrentENABLE=VDD,ldo_en=0;osc_en=0;internalLDOoperatinginlowpowermode–onlyICcommunicationpossible,noblocksshallbeenabled(1)22μAENABLE=VDD,ldo_en=1;osc_en=0;internalLDOoperatingandbandgaprunning–ICcommunicationpossible,analogblockscanbeenabled(1)32μAENABLE=VDD,ldo_en=1,osc_en=1;internalLDOoperatingandbandgapandoscillatorrunning–ICcommunicationpossible,analogblockscanbeenabled86μASIGREFbuffer(sigref_en=1)52μAtransimpedanceamplifier(pd_amp_en=1)110μAOpticalfrontendoperating(onechannel)200μADocumentFeedbackAS7026GGElectricalCharacteristicsDatasheetPUBLICDS000622v2-002019-Sep-1710810SymbolParameterConditionsMinTypMaxUnitGainstage(ofe1_gain_en=1orofe2_gain_en=1)75μAADCsamplingat20Hzwith64μssettlingtime4.
5μAECGamplifierandfrontend(needSIGREFenabled)190μAECGleakagecompensation(ecg_low_leakage_en=1),lowpassfilter,highpassfilterandgainstage151μAPowerdown,noICcommunicationpossibleENABLE=GND(2)0.
5μAVOLGPIO0-3,INT,SDAoutputlowvoltageWith3mAloadWith6mAload000.
40.
8VVOHGPIO0-3outputhighvoltageWith3mAload2.
3VDDVVIHGPIO0-3,SCL,SDA,ENABLEinputhighvoltage1.
25VVILGPIO0-3,SCL,SDA,ENABLEinputlowvoltage0.
54VILEAK1GPIO0-3,SCL,SDA,ENABLE,INT-11μAILEAK2VD1,VD2VD3,VD4-33μAE_f2MToleranceofinternal2MHzoscillator0Cto70C,VDDRegistertype10x10LED_CFGNotusedsigref_ensigref_voltage[1]sigref_voltage[0]led4_enled3_enled2_enled1_en0X12LED1_CURRLCurr1[1:0]NotusedNotusedNotusedNotusedNotusedNotused0X13LED1_CURRHCurr1[9:2]0X14LED2_CURRLCurr2[1:0]NotusedNotusedNotusedNotusedNotusedNotused0X15LED2_CURRHCurr2[9:0]0X16LED3_CURRLCurr3[1:0]NotusedNotusedNotusedNotusedNotusedNotused0X17LED3_CURRHCurr3[9:2]0X18LED4_CURRLCurr4[1:0]NotusedNotusedNotusedNotusedNotusedNotused0X19LED4_CURRHCurr4[9:2]0X2CLED12_MODEMan-sw_led2Led2_mode[2:0]Man_sw_led1Led1_mode[2:0]0X2DLED34_MODEMan-sw_led4Led4_mode[2:0]Man-sw_led3Led3_mode[2:0]0X2EMAN_SEQ_CFGman_modeman_sw_sdmultman_sw_sdpolman_sw_itgdiode_ctrl[2:0]seq_en0XA2LEDSTATUSNotusedNotusedNotusedNotusedled4_supply_lowled3_supply_lowled2_supply_lowled1_supply_low0X1APD_CFGNotusedNotusedpd4pd3pd2pd1pd_i1pd_i00X1BPDOFFX_LEDOFFpdoffx_ledoff[7:0]0X1CPDOFFX_LEDONpdoffx_ledon[7:0]0X1DPD_AMPRCCFGpd_ampres[2:0]pd_ampcap[4:0]0X1EPD_AMPCFGpd_amp_enpd_amp_autopd_ampvo[3:0]pd_ampcomp[1:0]0X1FPD_THRESHCFGpd_clipdetect_h_thresh[3:0]pd_clipdetect_l_thresh[3:0]0X30SEQ_CNTseq_count[7:0]DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710818AddrName0X31SEQ_DIVseq_div[7:0]0X32SEQ_STARTNotusedNotusedNotusedNotusedNotusedNotusedseq_start_syncseq_start0X33SEQ_PERseq_period[7:0]0X34SEQ_LED_STAseq_led_seq_led_stopstart[7:0]0X35SEQ_LED_STOseq_led_stop[7:0]0X36SEQ_SECLED_STAseq_secled_start[7:0]0X37SEQ_SECLED_STOseq_secled_stop[7:0]0X38SEQ_ITG_STAseq_itg_start[7:0]0X39SEQ_ITG_STOseq_itg_stop[7:0]0X3ASEQ_SDP1_STAseq_sdp1_start[7:0]0X3BSEQ_SDP1_STOseq_sdp1_stop[7:0]0X3CSEQ_SDP2_STAseq_sdp2_start[7:0]0X3DSEQ_SDP2_STOseq_sdp2_stop[7:0]0X3ESEQ_SDM1_STAseq_sdm1_start[7:0]0X3FSEQ_SDM1_STOseq_sdm1_stop[7:0]0X40SEQ_SDM2_STAseq_sdm2_start[7:0]0X41SEQ_SDM2_STOseq_sdm2_stop[7:0]0X42SEQ_ADCseq_adc[7:0]0X43SEQ_ADC2TIAseq_adc2tia[7:0]0X44SEQ_ADC3TIAseq_adc3tia[7:0]0X45SD_SUBSsd_subs[7:0]0X46SEQ_CFGNotusedNotusedNotusedNotusedNotusedNotusedNotusedsd_subs_always0X47SEQ_ERRirq_adc_timing_errorNotusedNotusedNotusedNotusedNotusedNotusedNotused0X60CYC_COUNTERcycle_counter[7:0]0X60SEQ_COUNTERsequence_counter[7:0]0X62SUBS_COUNTERsubs_counter[7:0]DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710819AddrName0X50OFE_CFGAofe2_enofe1_enen_bias_ofeaa_freq[1:0]gain_sd[2:0]0X51OFE_CFGBsd_clipdetect_h_thresh[3:0]sd_clipdetect_l_thresh[3:0]0X52OFE_CFGCNotusedprefilter_aa_bypprefilter_hp_bypprefilter_gain_bypprefilter_bypass_enprefilter_aa_enprefilter_hp_enprefilter_gain_en0X53OFE_CFGDNotusedNotusedNotusedNotusedNotusedNotusedofe_gs_aa[1:0]0X54OFE1_CFGAofe1_sd_pol_initofe1_sd_enofe1_hp_enofe1_gain_enofe1_sd_bypofe1_hp_bypofe1_gain_bypofe1_sd_hld0X55OFE1_CFGBNotusedofe1_gain_g[2:0]ofe1_sd_bw[1:0]ofe1_hp_freq[1:0]0X58OFE2_CFGAofe2_sd_pol_initofe2_sd_enofe2_hp_enofe2_gain_enofe2_sd_bypofe2_hp_bypofe2_gain_bypofe2_sd_hld0X59OFE2_CFGBNotusedofe2_gain_g[2:0]ofe2_sd_bw[1:0]2fe2_hp_freq[1:0]0X20LTFDATA0_Lltfdata0[7:0]0X21LTFDATA0_Hltfdata0[15:8]0X22LTFDATA1_Lltfdata0[7:0]0X23LTFDATA1_Hltfdata1[15:8]0X24ITIMEItime[7:0]0X25LTF_CONFIGinfinite_itimeaz_disable_autoreservedreservedNotusedNotusedltf_fifo_modeltf_enable0X26LTF_SELNotusedltf1_sel[2:0]Notusedltf0_sel[2:0]0X27LTF_GAINDonotuseDonotuseitime_unit[1:0]ltf_gain[3:0]0X28LTF_CONTROLDonotuseDonotuseDonotuseDonotuseDonotuseDonotuseDonotuseltf_start0X29AZ_CONTROLDonotuseDonotuseDonotuseDonotuseDonotuseDonotuseaz_enable_1az_enable_00X2AOFFSET0offset0[7:0]0X2BOFFSET1offset0[7:0]0X70AFE_CFGDonotuseDonotuseDonotuseDonotuseafe_enabafe_enab_dacafe_enab_dac_bufafe_enab_gainstage0X80EAF_GSTgpio_gst_in[2:0]gst_ref[1:0]gst_gain[2:0]0X81EAF_BIASgpio_r_bias[2:0]NotusedNotusedNotusedNotusedNotused0X82EAF_DACDonotuseDonotuseDonotusesigref_on_dac_bufmeasure_dacgpio_dac[2:0]0X83EAF_DAC1_Ldac1_value[]NotusedNotusedNotusedNotusedNotusedNotused0X84EAF_DAC1_Hdac1_value[9:2]0X85EAF_DAC2_Ldac2_value[1:0]NotusedNotusedNotusedNotusedNotusedNotused0X86EAF_DAC2_Hdac2_value[9:2]DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710820AddrName0X87EAF_DAC_CFGNotusedNotusedNotusedNotusedNotusedNotuseddac_mode[1:0]0X5CECG_CFGAecg_enNotusedecg_lp_enecg_hp_enecg_gain_enecg_lp_bypecg_hp_bypecg_gain_byp0X5DECG_CFGBNotusedecg_lp_freq[1:0]ecg_hp_freq[1:0]ecg_gain_g[2:0]0X5EECG_CFGCNotusedNotusedNotusedNotusedNotusedNotusedecg_low_leakage_enecg_ref_en0X5FECG_CFGDNotusedNotusedNotusedecg_leadsdet_sync_adcecg_leadsdet_polecg_leadsdet_curr[1:0]ecg_leadsdet_en0X68ADC_THRESHOLDadc_threshold[7:0]0X69ADC_THRESHOLD_CFGNotusedNotusedNotusedNotusedNotusedNotusedadc_thresh_differentialadc_thresh_tiaonly0X88ADC_CFGANotusedNotusedNotusedNotusedadc_multi_n[2:0]adc_multimode0X89ADC_CFGBNotusedNotusedadc_clock[2:0]adc_calibrationulpadc_en0X8AADC_CFGCNotusedNotusedNotusedadc_selfpdadc_dischargeadc_settling_time[2:0]0X8BADC_CHANNEL_MASK_Ladc_channel_mask_pregainadc_channel_mask_afeadc_channel_mask_tempadc_channel_mask_sd2adc_channel_mask_ofe2adc_channel_mask_sd1adc_channel_mask_ofe1adc_channel_mask_tia0X8CADC_CHANNEL_MASK_HNotusedNotusedNotusedNotusedadc_channel_mask_gpio2adc_channel_mask_gpio3adc_channel_mask_ecgiadc_channel_mask_ecgo0X8EADC_DATA_Ladc_data[7:0]0X8FADC_DATA_HNotusedNotusedadc_data[13:8]0X78FIFO_CFGNotusedNotusedfifo_threshold[5:0]0X79FIFO_CNTRLNotusedNotusedNotusedNotusedNotusedNotusedNotusedfifo_clear0XA3FIFOSTATUSfifooverflowFifolevel[6:0]0XFEFIFOLFifol[7:0]0XFFFIFOHFifoh[7:0]0x00CONTROLNotusedNotusedNotusedNotusedNotusedNotusedosc_enldo_en0X08GPIO_ANotusedNotusedNotusedNotusedgpio3_agpio2_agpio1_agpio0_a0X09GPIO_ENotusedNotusedNotusedNotusedgpio3_egpio2_egpio1_egpio0_e0X0AGPIO_ONotusedNotusedNotusedNotusedgpio3_ogpio2_0gpio1_0gpio0_00X0BGPIO_INotusedNotusedNotusedNotusedgpio3_igpio2_igpio1_igpio0_i0X0CGPIO_Pgpio3_pdgpio3_pugpio2_pdgpio2_pugpio1_pdgpio1_pugpio0_pdgpio0_pu0X0DGPIO_SRNotusedNotusedNotusedNotusedgpio3_srgpio2_srgpio1_srgpio0_sr0X91SUBIDsubid[4:0]Revision[2:0]0X92IDid[5:0]id_reserved[1:0]DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710821AddrName0XA0STATUSirq_led_supply_lowirq_clipdetectirq_fifooverflowirq_fifothresholdirq_adc_thresholdirq_ltfirq_sequencerirq_adc0XA1CLIPSTATUSNotusedNotusedNotusedNotusedpd_clipdetect_lpd_clipdetect_hsd_clipdetect_lsd_clipdetect_h0XA2LEDSTATUSNotusedNotusedNotusedNotusedled4_supply_lowled3_supply_lowled2_supply_lowled1_supply_low0XA8INTENABirq_led_supply_low_enabirq_clipdetect_enabirq_fifooverflow_enairq_fifothreshold_enabirq_adc_threshold_enabirq_ltf_enabirq_sequencer_enabirq_adc_enab0XA9INTRirq_led_supply_low_intrirq_clipdetect_intrirq_fifooverflow_intrirq_fifothreshold_intrirq_adc_threshold_intrirq_ltf_intrirq_sequencer_intrirq_adc_intrDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108227.
1.
1LEDConfigurationLED_CFGRegister(Address0x10)Figure11:LED_CFGRegisterAddr:0x10LED_CFGBitBitNameDefaultAccessBitDescription6sigref_en0RWSignalreference:Isrequiredforallanalogblocks(exceptPD_Amporlight-to-frequencyoperation)0…Disablesignalreference1…Enablesignalreference5:4sigref_voltage0RWVoltagesettingofSIGREF–datasheetparametersareguaranteedonlyfordefaultvalueof0.
6V.
SettingIMAX000.
6V(default)010.
7V100.
8V110.
9V3led4_en0RW0…DisablesLED4outputsource.
1…EnablesLED4outputsource.
2led3_en0RW0…DisablesLED3outputsource.
1…EnablesLED3outputsource.
1led2_en0RW0…DisablesLED2outputsource.
1…EnablesLED2outputsource.
0led1_en0RW0…DisablesLED1outputsource.
1…EnablesLED1outputsource.
TheLED_CURRdefinestheLEDoutputcurrent.
AttentionItisrecommendedtoconfigurethecurrentonlywhentheoutputisnotactive,asthereisnolatchimplementedtokeepthe10bitsconsistent.
Newvaluesareapplieddirectlyandimmediately.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710823LED1_CURRLRegister(Address0x12)Figure12:LED1_CURRLRegisterAddr:0x12LED1_CURRLBitBitNameDefaultAccessBitDescription7:6Curr1[1:0]0RWLED1outputcurrentlower2bits5:0Notused0RWNotusedLED1_CURRHRegister(Address0x13)Figure13:LED1_CURRHRegisterAddr:0x13LED1_CURRHBitBitNameDefaultAccessBitDescription7:0Curr1[9:2]0RWLED1outputcurrentupper8bitsCodingforcurr1[9:0]:000h…786A001h…883A(1LSB=97A)002h…980A166h…35mA3FFh…100mALED2_CURRLRegister(Address0x14)Figure14:LED2_CURRLRegisterAddr:0x14LED2_CURRLBitBitNameDefaultAccessBitDescription7:6Curr2[1:0]0RWLED2outputcurrentlower2bits5:0Notused0RWNotusedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710824LED2_CURRHRegister(Address0x15)Figure12:LED2_CURRHRegisterAddr:0x15LED2_CURRHBitBitNameDefaultAccessBitDescription7:0Curr2[9:2]0RWLED2outputcurrentupper8bitsCodingforcurr1[9:0]:000h…786A001h…883A(1LSB=97A)002h…980A166h…35mA3FFh…100mALED3_CURRLRegister(Address0x16)Figure13:LED3_CURRLRegisterAddr:0x16LED3_CURRLBitBitNameDefaultAccessBitDescription7:6Curr3[1:0]0RWLED3outputcurrentlower2bits5:0Notused0RWNotusedLED3_CURRHRegister(Address0x17)Figure14:LED3_CURRHRegisterAddr:0x17LED3_CURRHBitBitNameDefaultAccessBitDescription7:0Curr3[9:2]0RWLED3outputcurrentupper8bitsCodingforcurr1[9:0]:000h…786A001h…883A(1LSB=97A)002h…980A166h…35mA3FFh…100mADocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710825LED4_CURRLRegister(Address0x18)Figure15:LED4_CURRLRegisterAddr:0x18LED4_CURRLBitBitNameDefaultAccessBitDescription7:6Curr4[1:0]0RWLED4outputcurrentlower2bits5:0Notused0RWNotusedLED4_CURRHRegister(Address0x19)Figure16:LED4_CURRHRegisterAddr:0x19LED4_CURRHBitBitNameDefaultAccessBitDescription7:0Curr4[9:2]0RWLED4outputcurrentupper8bitsCodingforcurr1[9:0]:000h…786A001h…883A(1LSB=97A)002h…980A166h…35mA3FFh…100mALED12_MODERegister(Address0x2c)Figure17:LED12_MODERegisterAddr:0x2cLED12_MODEBitBitNameDefaultAccessBitDescription7Man-sw_led20RW0…LEDoutputD2disabled.
(Highimpedance)1…LEDoutputD2enabled6.
4Led2_mode0RWLED2modeSettingsBehavior000AlwaysOFF001AlwaysONwhensequencerisactiveDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710826Addr:0x2cLED12_MODEBitBitNameDefaultAccessBitDescription010Controlledbysequencer011Controlledbysequencer,onlyONineveniterations:0,2,4etc.
100Controlledbysequencer,onlyONinodditerations:1,3,5etc.
101Controlledbysequencer,onlyONineveryfourthiteration,startingat1:1,5,9etc.
110Controlledbysequencer:secondaryLEDtiming111Donotuse3Man_sw_led10RW0…LEDoutputD1disabled.
(Highimpedance)1…LEDoutputD1enable2.
0Led1_mode0RWLED1modeSettingsBehavior000AlwaysOFF001AlwaysONwhensequencerisactive010Controlledbysequencer011Controlledbysequencer,onlyONineveniterations:0,2,4etc.
100Controlledbysequencer,onlyONinodditerations:1,3,5etc.
101Controlledbysequencer,onlyONineveryfourthiteration,startingat1:1,5,9etc.
110Controlledbysequencer:secondaryLEDtiming111DonotuseDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710827LED34_MODERegister(Address0x2d)Figure18:LED34_MODERegisterAddr:0x2dLED34_MODEBitBitNameDefaultAccessBitDescription7Man-sw_led40RW0…LEDoutputD4disabled.
(Highimpedance)1…LEDoutputD4enabled6.
4Led4_mode0RWLED4modeSettingsBehavior000AlwaysOFF001AlwaysONwhensequencerisactive010Controlledbysequencer011Controlledbysequencer,onlyONineveniterations:0,2,4etc.
100Controlledbysequencer,onlyONinodditerations:1,3,5etc.
101Controlledbysequencer,onlyONineveryfourthiteration,startingat1:1,5,9etc.
110Controlledbysequencer:secondaryLEDtiming111Donotuse3Man_sw_led30RW0…LEDoutputD3disabled.
(Highimpedance)1…LEDoutputD3enable2.
0Led3_mode0RWLED3modeSettingsBehavior000AlwaysOFF001AlwaysONwhensequencerisactive010Controlledbysequencer011Controlledbysequencer,onlyONineveniterations:0,2,4etc.
100Controlledbysequencer,onlyONinodditerations:1,3,5etc.
101Controlledbysequencer,onlyONineveryfourthiteration,startingat1:1,5,9etc.
110Controlledbysequencer:secondaryLEDtiming111DonotuseDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710828TheMAN_SEQ_CFGregisterisusedtoconfiguretheoperationoftheopticalfrontendMAN_SEQ_CFGRegister(Address0x2e)Figure19:MAN_SEQ_CFGRegisterAddr:0x2eMAN_SEQ_CFGBitBitNameDefaultAccessBitDescription7man_mode0RW0…EnablesSequencer1…EnablesManualcontrolofopticalfrontend6man_sw_sdmult0RWIfman_mode=10…Disablessynchronousdemodulatormultiplication1…Enablessynchronousdemodulatormultiplication5man_sw_sdpol0RWIfman_mode=10…Negativepolarityinsynchronousdemodulatormultiplication1…Positivepolarityinsynchronousdemodulatormultiplication4man_sw_itg0RWIfman_mode=10…Allintegratorcapacitorsareshorted.
Integratorisreset1…Integratorcapacitorsarechargingup.
Integratorisrunning3:1diode_ctrl0RWConnectionofPhotodiodesPD1,PD2,PD3,PD4tothephotodiodeamplifier.
0…PD1-PD4areconnected1…PD1synchronoustoLED1,PD2sync/toLED2PD3sync/toLED3,PD4sync/toLED42…PD1synchronoustoLED1,PD2sync/toLED1PD3sync/toLED2,PD4sync/toLED23…PD1synchronoustoLED1,PD2sync/toLED1PD3sync/toLED4,PD4sync/toLED44…SPO2mode*(obsolete):(negedge(sdm1)ornegedge(sdp1))-PD1=0PD2=0PD3=1PD4=1;(negedge(sdm2)ornegedge(sdp2))-PD1=1PD2=1PD3=0PD4=0NotethatPD_CFG.
pdXtakesprecedence-toturnOFFonephotodiode,therespectivebithastobede-assertedinthePD_CFGregister.
PD_CFG.
pdXdiode_ctrlPhotoDiode1PhotoDiode2PhotoDiode3PhotoDiode40xxOFFOFFOFFOFF10ONONONONDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710829Addr:0x2eMAN_SEQ_CFGBitBitNameDefaultAccessBitDescription11LED1LED2LED3LED412LED1LED1LED2LED213LED1LED1LED4LED414SPO2mode(obsolete)15.
.
7Donotuse0seq_en0RW0…Disablessequencer1…EnablessequencerLEDSTATUSRegister(Address0xa2)Figure20:LEDSTATUSRegisterAddr:0xa2LED4_CURRLBitBitNameDefaultAccessBitDescription7:4NA0RONotUsed3led4_supply_low0ROIfthisbitisasserted,LED4voltagehasbeentoolow.
2led3_supply_low0ROIfthisbitisasserted,LED3voltagehasbeentoolow.
1led2_supply_low0ROIfthisbitisasserted,LED2voltagehasbeentoolow.
0led1_supply_low0ROIfthisbitisasserted,LED1voltagehasbeentoolow.
Anassertedbitcanbeclearedbywritinga'1'totheirq_led_supply_lowbit.
7.
1.
2PhotodiodeSelectionInordertohaveflexiblearrangementoftheusephotodiodes,PD1-PD4canbeindividuallyconnectedtothephotodiodeamplifierinput.
Theoptionaloffsetcurrentallowscancellationofconstantlightsourceslikesunlight.
Incaseofanexternalphotodiodeoranyothersensorwith(low)currentoutput,thepinsGPIO0andGPIO1canbeusedasinput.
Additionallythesequencercancontrolthediodes–seediode_ctrldescribedinregisterMAN_SEQ_CFG.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710830Figure21:PhotodiodeSelectionPD_CFGRegister(Address0x1a)Figure22:PD_CFGRegisterAddr:0x1aPD_CFGBitBitNameDefaultAccessBitDescription7:6NA0RWNotUsed5pd40RW0…PhotodiodePD4isdisconnectedfromphotoamplifier1…PhotodiodePD4isconnectedtophotoamplifier(asdefinedindiode_ctrl)4pd30RW0…PhotodiodePD3isdisconnectedfromphotoamplifier1…PhotodiodePD3isconnectedtophotoamplifier(asdefinedindiode_ctrl)3pd20RW0…PhotodiodePD2isdisconnectedfromphotoamplifier1…PhotodiodePD2isconnectedtophotoamplifier(asdefinedindiode_ctrl)2pd10RW0…PhotodiodePD1isdisconnectedfromphotoamplifier1…PhotodiodePD1isconnectedtophotoamplifier(asdefinedindiode_ctrl)DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710831Addr:0x1aPD_CFGBitBitNameDefaultAccessBitDescription1pd_i10RW0…PhotodiodeB(seePhotodiodeCharacteristics)disconnectedfromTIAinput1…PhotodiodeB(seePhotodiodeCharacteristics)connectedtoTIAinput;setltf1_sel=0andltf2_sel=0.
0pd_i00RW0…GPIO0-inputisdisconnectedfromphotoamplifier1…GPIO0-inputisconnectedtophotoamplifier;setgpio_a[0]=1.
PDOFFX_LEDOFFRegister(Address0x1b)Figure23:PDOFFX_LEDOFFRegisterAddr:0x1bPDOFFX_LEDOFFBitBitNameDefaultAccessBitDescription7:0pdoffx_ledoff0RWInputoffsetcurrentifallLEDsareOFF(allsw_led*sequenceroutputsarezero)Ioffset=pdoffx_ledoff*10nA0…OffsetsourceisturnedOFFPDOFFX_LEDONRegister(Address0x1c)Figure24:PDOFFX_LEDONRegisterAddr:0x1cPDOFFX_LEDONBitBitNameDefaultAccessBitDescription7:0pdoffx_ledon0RWInputoffsetcurrentifatleastoneLEDisON(oneormoresw_led*sequenceroutputsarenon-zero)Ioffset=pdoffx_ledon*10nA0…OffsetsourceisturnedOFFDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108327.
1.
3PhotodiodeCharacteristicsFigure25:PhotodiodeArrangement–OrientationasinFigure2Foroperationandcharacteristicsofphotodiode'A'andphotodiode'B'seesection7.
1.
12Light-to-FrequencyMode.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710833Figure26:PhotodiodeSensitivity(solidgreenandblack)andLEDEmissionSpectrum(dottedgreenanddottedblack)InformationAll4photodiodesusedpd1/2/3/4=1;perpendicularlightsourceandnodiffusorusedonAS7026GG;duetothedifferenceinphotodiodesizetheabsoluteresponseforPhotodiodeB(0.
01mm2)ismuchlowercomparedtoPD1-PD4(0.
8mm2)7.
1.
4PhotodiodeTransimpedanceAmplifier(TIA)Thephotodiodeamplifiercanbeconfiguredinthreedifferentmodes:Photocurrenttofrequencyconverter–seesection7.
1.
12Light-to-FrequencyModePhotocurrenttovoltageconverterPhotocurrentintegrator0%20%40%60%80%100%120%30040050060070080090010001100ResponseNormalized(%)Wavelength(nm)AS7026GGPD1-PD4AS7026GGPhotodiodeBGreenLEDIRLED940nmDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710834Figure27:TransimpedanceAmplifier(TIA)TheintegrationtimetINTisdefinedeitherbythesequencer(man_mode=0)ormanuallythroughthebitsw_itgifman_mode=1.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710835UsefollowingsettingsfortheprogrammingoftheTIA:Figure28:TIAProgrammingpd_amprespd12341pd_ampcappd_ampcomppd_ampvogain11…4131151V/A21…471152V/A31…451153V/A41…220155V/A3…4351…220157V/A3…4361101510V/A2…4271…2101515V/A3…42LowBandwidthMode51…4313157V/AIntegratingMode(pd_ampres=0)01…4103151V/pQ01…4203151/2V/pQ01…4303151/3V/pQDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108367.
1.
5PhotodiodeTIARegistersPD_AMPRCCFGRegister(Address0x1d)Figure29:PD_AMPRCCFGRegisterAddr:0x1dPD_AMPRCCFGBitBitNameDefaultAccessBitDescription7:5pd_ampres0RWFeedbackresistorSettingResistance0Noresistorinfeedbackofamplifier–photocurrentintegrator11MΩ22MΩ33MΩ45MΩ57MΩ610MΩ715MΩ4:0pd_ampcapFeedbackcapacitorThePD_AMPCFGregisterisusedtoconfiguretheoperatingmodeofthephotoamplifier.
PD_AMPCFGRegister(Address0x1e)Figure30:PD_AMPCFGRegisterAddr:0x1ePD_AMPCFGBitBitNameDefaultAccessBitDescription7pd_amp_en0RW0…Activatespowerdownmodeofphoto-amplifier1…Enablesphoto-amplifier(directorautomaticpd_amp_automode)alsoseten_bias_ofe=16pd_amp_auto0RW0…NormalTIAmode1…EnableTIAonlywhenseq_itgisset(i.
e.
controlledbysequenceritgsetting)alsoseten_bias_ofe=1DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710837Addr:0x1ePD_AMPCFGBitBitNameDefaultAccessBitDescription5:2pd_ampvo1RWOpAmpoffset.
Canbeusedtolimitsignalindarknessandtoshortenrisetimes1:0pd_ampcomp3RWOpAmpcompensation,dependingongainandnumberofusedphotodiodesCapacitor=pd_ampcap*0.
1pFPD_THRESHCFGRegister(Address0x1f)Figure31:PD_THRESHCFGRegisterAddr:0x1fPD_THRESHCFGBitBitNameDefaultAccessBitDescription7:4pd_clipdetect_h_thresh0RWIfthevoltageontheoutputoftheTIAexceedthisthresholdtheirq_clipdetectinterruptisasserted.
Thethresholdisdefinedas0…1824mV1…1748mV2…1672mV3…1596mV4…1520mV5…1444mV6…1368mV7…1292mV8…1216mV9…1140mV10…1064mV11…988mV12…912mV13…836mV14…760mV15…684mV3:0pd_clipdetect_l_thresh0RWIfthevoltageontheoutputoftheTIAfallsbelowthisthresholdtheirq_clipdetectinterruptisasserted.
Thethresholdisdefinedas0…67mV1…143mV2…219mVDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710838Addr:0x1fPD_THRESHCFGBitBitNameDefaultAccessBitDescription3…295mV4…371mV5…447mV6…523mV7…599mV8…675mV9…751mV10…827mV11…903mV12…979mV13…1055mV14…1131mV15…1207mV7.
1.
6VoltageModeofthePhotodiodeAmplifierTheoutputvoltageofthephotodiodeamplifierisdependingonthefeedbackcomponent.
Equation1:=FeedbackresistorEquation2:=FeedbackcapacitorInformationTheintegrationtimetINTisdefinedeitherbythesequencer(man_mode=0)ofmanuallythroughthebitsw_itgifman_mode=1.
Forthesynchronousdemodulatoronlyusetheresistivefeedback.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710839Figure32:DifferenceBetweenResistiveandCapacitiveFeedback(1)Green:CapacitiveIntegrationGreenDotted:EffectiveValuefromCapacitiveModeBlue:ResistiveFeedbackRed:LightIntensity7.
1.
7OpticalFrontEndOperatingModesOncethephotodiodeamplifierisconfiguredthemeasurementcanbedoneintwodifferentways.
EithertheLED-outputs,thephotodiodeamplifierandtheADCarecontrolledmanuallybymeansofregisterbits,ortheyarecontrolledbyabuiltinsequencer.
ManualOperationoftheOpticalFrontend:Theopticalfrontendcanbemanuallycontrolledviatheregisterman_mode=1DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710840Figure33:OpticalFrontend(1)Appliesonlyifman_mode=1.
FormanualoperationoftheLEDsanditscurrentsinkssee6.
1.
2LED-Driver7.
1.
8SequencerInordertosynchronizetheLED-currents,theintegrationtimeandtheADC-samplingtime,abuiltinsamplingsequencerscanbeused.
Thesequencergeneratesthe8-bit-timingsbasedona1sclockwhichcanbepre-scaledwithseq_div.
Theresultsoftheanalogtodigitalconversionareautomaticallystoredinapipelinebufferorinregisteradc_dataandtheADCFIFO.
Thetimingscanbeprogrammedwithfollowingregisters(applyforman_mode=0):Figure34:TimingRegistersRegisterDescriptionseq_divDividerofthe1sinputclockforallsequencertimingsseq_countNumberofmeasurementsinonesequenceseq_startWriting1startsthesequencer,0stopsthesequencerseq_periodTimeofonemeasurementcycleseq_led_startStarttimeoftheLEDdriverswithinonecycleseq_led_stopStoptimeoftheLEDdriverswithinonecycleseq_secled_startStarttimeofthesecondaryLEDdriverswithinonecycle(usedforSpO2)seq_secled_stopStoptimeofthesecondaryLEDdriverswithinonecycle(usedforSpO2)DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710841RegisterDescriptionseq_itg_startStarttimeoftheintegratorseq_itg_stopStoptimeoftheintegratorseq_sdp1_startStarttimeofthesynchronousdemodulator's1positivemultiplicationseq_sdp1_stopStoptimeofthesynchronousdemodulator's1positivemultiplicationseq_sdm1_startStarttimeofthesynchronousdemodulator's1negativemultiplicationseq_sdm1_stopStoptimeofthesynchronousdemodulator's1negativemultiplicationseq_sdp2_startStarttimeofthesynchronousdemodulator's2positivemultiplicationseq_sdp2_stopStoptimeofthesynchronousdemodulator's2positivemultiplicationseq_sdm2_startStarttimeofthesynchronousdemodulator's2negativemultiplicationseq_sdm2_stopStoptimeofthesynchronousdemodulator's2negativemultiplicationseq_adcSamplingpositionoftheADCseq_adc2tia,seq_adc3tiaIftheTIAchannelisselectedallowasecond(andthird)conversionwithinthiscycle.
sd_subs,sd_subs_alwaysSynchronousdemodulatorsubsamplingratiobetweensequencerfrequencyandADCsamplingfrequency.
ulpUltralowpowerbitforthesequencer.
Ifthisbitissetandsd_subs>0,itdisablestheLEDpulsesandpowersofftheTIAinallsequencesbuttheonewheretheTIAissampled.
ThisbitcanbeusedtooptimizethepowerconsumptionoftheLEDsandtheAS7026GG(ThisbitislocatedinADC_CFGBRegisterbit1)irq_adc_timing_errorThesequencersetupcausedatimingerroronADCconversion.
AppliesonlyIfman_mode=1Thelowestdatavalueofallregistersexceptseq_countandseq_divis1.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710842Figure35:BlockDiagramofSequencerDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108437.
1.
9SequencerRegistersSEQ_CNTRegister(Address0x30)Figure36:SEQ_CNTRegisterAddr:0x30SEQ_CNTBitBitNameDefaultAccessBitDescription7:0seq_count0RWNumberofmeasurementsinonesequence.
Ifseq_count=0x0thesequencerisrunningcontinuouslyifstartedbyseq_start=1orseq_start_sync=1.
Thisregisterisresetbydisabling/enablingofseq_start=0(butnotbyosc_off=1)SEQ_DIVRegister(Address0x31)Figure37:SEQ_DIVRegisterAddr:0x31SEQ_DIVBitBitNameDefaultAccessBitDescription7:0seq_div0RWDividervalueSequencertimeincrementtclk=(seq_div+1)*1sTheSEQ_DIVregistersetstheinputdividerforthemainclock.
SEQ_START(Address0x32)Figure38:SEQ_STARTRegisterAddr:0x32SEQ_STARTBitBitNameDefaultAccessBitDescription7:2Notused0R_PUSHNotusedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710844Addr:0x32SEQ_STARTBitBitNameDefaultAccessBitDescription1seq_start_sync0R_PUSHSimilartoseq_start,butthesequencerwillwaitforoverflowofthefrequencydividerthatfeedsalltheswitched-capfilters.
Thismeans1)Thatitcouldtakeanythingbetween0and8msbeforethesequenceractuallystarts.
2)Thatthegeneratedfrequenciesareinphasewiththesequencer.
Forthistohaveanyeffect,thesequencerperiodshouldbeselectedwiththeselectedfrequencies(sd_bw,hp_freq)inmind.
0seq_start0R_PUSHWriting1startsthesequencer(s)intheaccordingtotheconfigurationanduponrisingedgeofseq_startADCselectsfirstchannel.
Writing0stopsthesequencer(s).
Inmanualmode,writing1startsoneADCconversionbutdoesnotinitializetheADCchannelselection.
Readingreturns1ifthesequencerisrunning(sequencermode),respectivelyiftheADCisconverting(manualmode)WiththeSEQ_STARTregistersetstheconfiguredsequencercanbestartedSEQ_PER(Address0x33)Figure39:SEQ_PERRegisterAddr:0x33SEQ_PERBitBitNameDefaultAccessBitDescription7:0seq_period0RWt_periodSequencerperiodT=t_period*(seq_div+1)*1sTheSEQ_PERregistersetsonemeasurementcycleofthesequencer.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710845SEQ_LED_STA(Address0x34)Figure40:SEQ_LED_STARegisterAddr:0x34SEQ_LED_STABitBitNameDefaultAccessBitDescription7:0seq_led_start0RWLEDstarttimeTheSEQ_LEDregistersetstheLEDdrivetiming.
Dataisstoredas16-bitvalue.
SEQ_LED_STO(Address0x35)Figure41:SEQ_LED_STORegisterAddr:0x35SEQ_LED_STOBitBitNameDefaultAccessBitDescription7:0seq_led_stop0RWLEDstoptimeTheSEQ_LEDregistersetstheLEDdrivetiming.
Dataisstoredas16-bitvalue.
SEQ_SECLED_STA(Address0x36)Figure42:SEQ_SECLED_STARegisterAddr:0x36SEQ_SECLED_STABitBitNameDefaultAccessBitDescription7:0seq_secled_start0RWSecondaryLEDstarttimeTheSEQ_LEDregistersetsthesecondaryLEDdrivetimingwhichisusedinledX_mode6only.
Dataisstoredas16-bitvalue.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710846SEQ_SECLED_STO(Address0x37)Figure43:SEQ_SECLED_STORegisterAddr:0x37SEQ_SECLED_STOBitBitNameDefaultAccessBitDescription7:0seq_secled_stop0RWSecondaryLEDstoptimeSEQ_ITG_STA(Address0x38)Figure44:SEQ_ITG_STARegisterAddr:0x38SEQ_ITG_STABitBitNameDefaultAccessBitDescription7:0seq_itg_start0RWIntegratorstarttime(starttime=1andstoptime=0meansthatit's-bydefault-alwaysON)TurningOFFtheintegratoractuallymeansdischargethecapacitor.
Thisisonlyusefulincapacitiveintegrationmode,withoutthesynchronousdemodulator.
TheSEQ_ITGregistersetsthephotoamplifierintegrationtime.
Dataisstoredas16-bitvalue.
SEQ_ITG_STO(Address0x39)Figure45:SEQ_ITG_STORegisterAddr:0x39SEQ_ITG_STOBitBitNameDefaultAccessBitDescription7:0seq_itg_stop0RWIntegratorstoptimeDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710847SEQ_SDP1_STA(Address0x3a)Figure46:SEQ_SDP1_STARegisterAddr:0x3aSEQ_SDP1_STABitBitNameDefaultAccessBitDescription7:0seq_sdp1_start0RWPositivemultiplicationstarttime1TheSEQ_SDPregistersetsthesynchronousdemodulatorpositivemultiplicationtime.
Dataisstoredas16-bitvalue.
SEQ_SDP1_STO(Address0x3b)Figure47:SEQ_SDP1_STORegisterAddr:0x3bSEQ_SDP1_STOBitBitNameDefaultAccessBitDescription7:0seq_sdp1_stop0RWPositivemultiplicationstoptime1SEQ_SDP2_STA(Address0x3c)Figure48:SEQ_SDP2_STARegisterAddr:0x3cSEQ_SDP2_STABitBitNameDefaultAccessBitDescription7:0seq_sdp2_start0RWPositivemultiplicationstarttime2TheSEQ_SDPregistersetsthesynchronousdemodulatorpositivemultiplicationtime.
Dataisstoredas16-bitvalue.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710848SEQ_SDP2_STO(Address0x3d)Figure49:SEQ_SDP2_STORegisterAddr:0x3dSEQ_SDP2_STOBitBitNameDefaultAccessBitDescription7:0seq_sdp2_stop0RWPositivemultiplicationstoptime2SEQ_SDM1_STA(Address0x3e)Figure50:SEQ_SDM1_STARegisterAddr:0x3eSEQ_SDM1_STABitBitNameDefaultAccessBitDescription7:0seq_sdm1_start0RWNegativemultiplicationstarttime1TheSEQ_SDM1registersetsthesynchronousdemodulatornegativemultiplicationtime1.
Dataisstoredas16-bitvalueSEQ_SDM1_STO(Address0x3f)Figure51:SEQ_SDM1_STORegisterAddr:0x3fSEQ_SDM1_STOBitBitNameDefaultAccessBitDescription7:0seq_sdm1_stop0RWNegativemultiplicationstoptime1DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710849SEQ_SDM2_STA(Address0x40)Figure52:SEQ_SDM2_STARegisterAddr:0x40SEQ_SDM2_STABitBitNameDefaultAccessBitDescription7:0seq_sdm2_start0RWNegativemultiplicationstarttime2TheSEQ_SDM2registersetsthesynchronousdemodulatornegativemultiplicationtime2.
Dataisstoredas16-bitvalueSEQ_SDM2_STO(Address0x41)Figure53:SEQ_SDM2_STORegisterAddr:0x41SEQ_SDM2_STABitBitNameDefaultAccessBitDescription7:0seq_sdm2_stop0RWNegativemultiplicationstoptime2SEQ_ADC(Address0x42)Figure54:SEQ_ADCRegisterAddr:0x42SEQ_ADCBitBitNameDefaultAccessBitDescription7:0seq_adc0RWADCsamplingtimeTheADCconversionneedstobefinishedbeforethesequencerperiodendsotherwiseADCsamplescanbelost.
TheSEQ_ADCregisterdefinesthetimewhentheADCstartssamplingduringeachmeasurementcycle.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710850SEQ_ADC2TIA(Address0x43)Figure55:SEQ_ADC2TIARegisterAddr:0x43SEQ_ADC2TIABitBitNameDefaultAccessBitDescription7:0seq_adc2tia0RWADCsecondsamplingtimeforTIA:Ifthistimeisnon-zero,anADCconversionisstartedatthegivencycle,butonlyifadc_seliscurrentlyselectingTIA.
Forallotherchannels,thereisonlyasingleADCconversionexecutedinthesequencerperiod.
Warning:Ifnon-zero,seq_adcmustbenon-zeroaswell,andseq_adc2tiabiggerthanseq_adc.
ThedifferencemustbehighenoughsothatthesecondADCconversionisstartedafterthefirstADCconversionhasfinished.
Also,iftheseq_adc2tiafeaturesisused,thereistheadditionalrestrictionthatthesecondADCconversionhastobefinishedbeforetheendofthesequencerperiod.
SEQ_ADC3TIA(Address0x44)Figure56:SEQ_ADC3TIARegisterAddr:0x44SEQ_ADC3TIABitBitNameDefaultAccessBitDescription7:0seq_adc3tia0RWADCthirdsamplingtimeforTIA:sameasseq_adc2tia.
AlsomustmakesuretonotoverlapADCconversions!
Also,adc3tiamustbeafteradc2tiaDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710851SEQ_ADC3TIA(Address0x45)Figure57:SD_SUBSRegisterAddr:0x45SD_SUBSBitBitNameDefaultAccessBitDescription7:0sd_subs0RWSynchronousdemodulatorsubsamplingratiobetweensequencerfrequencyandADCsamplingfrequency.
ADC-Fsample=Sequencyer_Frequency/(sd_subs+1)Whensettingto0,thenineverysequenceriterationtheADCwillrun.
Whensettingto1,thenthefirstsequenceriterationwillnottriggertheADC,butthesecondonewill.
SettingtoNwillmakeNiterationswithoutADC,followedbyoneiterationwiththeADCmeasurementexecuted.
ItisrecommendedtousetheADCinterruptinthiscaseandnotthesequencerinterrupt.
Alsoseesd_subs_alwayswhichsignificantlyaffectsthismechanism.
SEQ_CFG(Address0x46)Figure58:SEQ_CFGRegisterAddr:0x46SEQ_CFGBitBitNameDefaultAccessBitDescription7:1NotUsed0RWNotUsed0sd_subs_always0RWIfthisbitisasserted,allsequencerperiodsaresubjecttosubsamplingasdefinedinSD_SUBS.
Ifthisbitiszero,thenonlythefirstperiodofan"ADCcycle"isduplicatedsd_substimes,allotherperiodsareregular.
One"ADCcycle"isthetimefromthesequenceinwhichadc_selispointingtothe"smallest"adcchannelupandincludingthesequenceofthe"largest"adcchannel.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710852SEQ_CFG(Address0x47)Figure59:SEQ_ERRRegisterAddr:0x47SEQ_ERRBitBitNameDefaultAccessBitDescription7irq_adc_timing_error0SS_WCTheADCwasstartedbythesequencer(ormanually)whileitwasstillconverting.
Thisdoesnotflaganinterruptbutwhenplayingwiththesequencersettingswesuggesttocheckthisflagtomakesurethatthereisnoproblemwiththesequencerprogramming6:0NotUsed0RWNotUsedCYC_COUNTER(Address0x60)Figure60:CYC_COUNTERRegisterAddr:0x60CYC_COUNTERBitBitNameDefaultAccessBitDescription7:0cycle_counter0ROCurrentcyclecountervalueTheSEQ_COUNTERregistershowsthecurrentvalueofthesequencecounterandperiodcounterSEQ_COUNTER(Address0x61)Figure61:SEQ_COUNTERRegisterAddr:0x61SEQ_COUNTERBitBitNameDefaultAccessBitDescription7:0sequence_counter0ROCurrentsequencecountervalueDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710853SUBS_COUNTER(Address0x62)Figure62:SUBS_COUNTERRegisterAddr:0x62SUBS_COUNTERBitBitNameDefaultAccessBitDescription7:0subs_counter0ROCurrentsubsamplingcountervalue7.
1.
10OpticalSignalConditioningFigure63:OpticalSignalConditioningDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710854SynchronousDemodulatorTwooptionalsynchronousdemodulatorscanbeusedtodetectsmallopticalsignalsinthepresenceoflargeunwantednoise(ambientlight).
SincethedetectorsynchronizestotheLEDfrequency,thedemodulatorcanonlybeusedofthemeasurementsequencerisrunning.
Itincludesinputfiler(highpassat200Hz,adjustablelowpass)andan2ndorderadjustableoutputlowpass.
Thedemodulatoritselfmultipliesthesignalby+1/0/-1withatimingwhichiscontrolledbythesequencer.
InformationTheopticalsignalconditioningstageneedsigref_en=1foroperation.
HighPassFilterTwooptionalhighpassfiltercanbeusedtoremoveunwantedDC-componentsfromthesignalandallowsfurtheramplification.
Inordertoguaranteefastsettlingtimesofthefilter,fourcutofffrequenciescanbechosen.
GainStageTwooptionalgainstagecanbeusedtoamplifythesignalaftertheDC-componenthasbeenremoved.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108557.
1.
11OpticalSignalConditioningRegistersOFE_CFGA(Address0x50)Figure64:OFE_CFGARegisterAddr:0x50OFE_CFGABitBitNameDefaultAccessBitDescription7ofe2_en0RWEnableOFE26ofe1_en0RWEnableOFE15en_bias_ofe0RWEnablebiasforOFEandTIA4:3aa_freq0RWAnti-aliasingfiltercut-OFFfrequencySettingsSignal010kHz120kHz240kHz360kHz2:0gain_sd0RWSDgainSettingsNormalGain011224384165326647ReservedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710856OFE_CFGB(Address0x50)Figure65:OFE_CFGBRegisterAddr:0x51OFE_CFGBBitBitNameDefaultAccessBitDescription7:4sd_clipdetect_h_thresh0RWIfthevoltageontheoutputofthegain_sdstage(inputofsynchronousdemodulator)exceedthisthresholdtheirq_clipdetectinterruptisasserted.
Thethresholdisdefinedas:0…1824mV1…1748mV2…1672mV3…1596mV4…1520mV5…1444mV6…1368mV7…1292mV8…1216mV9…1140mV10…1064mV11…988mV12…912mV13…836mV14…760mV15…684mV3:0sd_clipdetect_l_thresh0RWIfthevoltageontheoutputofthegain_sdstage(inputofsynchronousdemodulator)fallsbelowthisthresholdtheirq_clipdetectinterruptisasserted.
Thethresholdisdefinedas:0…67mV1…143mV2…219mV3…295mV4…371mV5…447mV6…523mV7…599mV8…675mV9…751mV10…827mV11…903mVDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710857Addr:0x51OFE_CFGBBitBitNameDefaultAccessBitDescription12…979mV13…1055mV14…1131mV15…1207mVOFE_CFGC(Address0x52)Figure66:OFE_CFGCRegisterAddr:0x52OFE_CFGCBitBitNameDefaultAccessBitDescription7Notused0RWNotused6prefilter_aa_byp0RW0…Antialiasingfilter(aa_filter)isused1…Bypassantialiasingfilter5prefilter_hp_byp0RW0…Use200Hzhighpassfilter1…Bypass200Hzhighpassfilter4prefilter_gain_byp0RW0…Usegain_sdstage1…Bypassgain_sdstage3prefilter_bypass_en0RW0…Useprefilterunlessanyoftheaboveregisterisset1…Bypasscompleteprefilter2prefilter_aa_en0RW0…Antialiasingfilter(aa_filter)isOFF1…AntialiasingfilterisON1prefilter_hp_en0RW0…200HzhighpassfilterisOFF1…200HzhighpassfilterisON0prefilter_gain_en0RW0…gain_sdstageisOFF1…gain_sdstageisONDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710858OFE_CFGD(Address0x53)Figure67:OFE_CFGDRegisterAddr:0x53OFE_CFGDBitBitNameDefaultAccessBitDescription7:2Notused0RWNotused1:0ofe_gs_aa0RWOFEantialiasingSettingNominalGain0Bypass1fc=100kHz2fc=10kHz3fc=826HzOFE1_CFGA(Address0x54)Figure68:OFE1_CFGARegisterAddr:0x54OFE1_CFGABitBitNameDefaultAccessBitDescription7ofe1_sd_pol_init0RWThelowleveldrivershallensurethatthisregisteris0ifoneoftheseq_sdmpulsesisfirst,andis1iftheseq_sdpisfirstwithinasequence.
6ofe1_sd_en0RW0…PowerdownoftheSynchronousdemodulator1…EnableSynchronousdemodulator5ofe1_hp_en0RW0…Powerdownofthehighpassfilter1…Enablehighpassfilter4ofe1_gain_en0RW0…PowerdownoftheGainstage1…EnableGainstage3ofe1_sd_byp0RW0…Synchronousdemodulatorisused1…Synchronousdemodulatorisbypassed2ofe1_hp_byp0RW0…HPfilterisused1…HPfilterisbypassed1ofe1_gain_byp0RW0…Gainstageisused1…GainstageisbypassedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710859Addr:0x54OFE1_CFGABitBitNameDefaultAccessBitDescription0ofe1_sd_hld0RWSDhold0…OutputofsynchronousdemodulatorisforcedtoSIGREFifnotsetto+1or-11…Outputofsynchronousdemodulatoristristatedifnotsetto+1or-1OFE1_CFGB(Address0x55)Figure69:OFE1_CFGBRegisterAddr:0x55OFE1_CFGBBitBitNameDefaultAccessBitDescription7Notused0RWNotused6:4ofe1_gain_g0RWGainSettingGain011224384165326647Donotuse3:2ofe1_sd_bw0RWSynchronousdemodulatorlowpassfilterSettingFrequency010Hz120Hz240Hz380HzDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710860Addr:0x55OFE1_CFGBBitBitNameDefaultAccessBitDescription1:0ofe1_hp_freq0RWHighpassfiltercutofffrequencySettingCutoffFrequency00.
33Hz11.
32Hz25.
28Hz310.
56HzOFE2_CFGA(Address0x58)Figure70:OFE2_CFGARegisterAddr:0x58OFE2_CFGABitBitNameDefaultAccessBitDescription7ofe2_sd_pol_init0RWThelowleveldrivershallensurethatthisregisteris0ifoneoftheseq_sdmpulsesisfirst,andis1iftheseq_sdpisfirstwithinasequence.
6ofe2_sd_en0RW0…Powerdownofthesynchronousdemodulator1…EnableSynchronousdemodulator5ofe2_hp_en0RW0…Powerdownofthehighpassfilter1…Enablehighpassfilter4ofe2_gain_en0RW0…PowerdownoftheGainstage1…EnableGainstage3ofe2_sd_byp0RW0…Synchronousdemodulatorisused1…Synchronousdemodulatorisbypassed2ofe2_hp_byp0RW0…HPfilterisused1…HPfilterisbypassed1ofe2_gain_byp0RW0…Gainstageisused1…Gainstageisbypassed00fe2_sd_hld0RWSDhold0…OutputofsynchronousdemodulatorisforcedtoSIGREFifnotsetto+1or-11…Outputofsynchronousdemodulatoristristatedifnotsetto+1or-1DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710861OFE2_CFGB(Address0x59)Figure71:OFE2_CFGBRegisterAddr:0x59OFE2_CFGBBitBitNameDefaultAccessBitDescription7Notused0RWNotused6:4ofe2_gain_g0RWGainSettingGain011224384165326647Donotuse3:2ofe2_sd_bw0RWSynchronousdemodulatorlowpassfilterSettingFrequency010Hz120Hz240Hz380Hz1:0ofe2_hp_freq0RWHighpassfiltercutofffrequencySettingCutoffFrequency00.
33Hz11.
32Hz25.
28Hz310.
56HzDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108627.
1.
12Light-to-FrequencyModeTheLTF(light-to-frequency,orFM,frequencymode)mode.
Figure72:Light-to-FrequencyModeInternalCircuit(1)DonotusediodeswhichareconnectedtotheTIA(registerpd_a,pd_b,pd1.
.
.
4)atthesametimewhenItf_enisenabledonthesamediode.
LTFDATA0_L(Address0x20)Figure73:LTFDATA0_LRegisterAddr:0x20LTFDATA0_LBitBitNameDefaultAccessBitDescription7:0ltfdata0[7:0]0ROLTFresultchannel0lowbyte.
SoftwaremustmakesurethattheLTFintegrationisnotrunningwhenaccessingtheLTFDATAregisters.
Thesearethedirectcounterregisters,theyarenotlatched.
Ifbufferingisrequired,considerusingFIFOmode.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710863LTFDATA0_H(Address0x21)Figure74:LTFDATA0_HRegisterAddr:0x21LTFDATA0_HBitBitNameDefaultAccessBitDescription7:0ltfdata0[15:8]0ROLTFresultchannel0highbyteLTFDATA1_L(Address0x22)Figure75:LTFDATA1_LRegisterAddr:0x22LTFDATA1_LBitBitNameDefaultAccessBitDescription7:0ltfdata0[7:0]0ROLTFresultchannel1lowbyte.
SoftwaremustmakesurethattheLTFintegrationisnotrunningwhenaccessingtheLTFDATAregisters.
Ifbufferingisrequired,considerusingFIFOmode.
LTFDATA1_H(Address0x23)Figure76:LTFDATA1_HRegisterAddr:0x23LTFDATA1_HBitBitNameDefaultAccessBitDescription7:0ltfdata1[15:8]0ROLTFresultchannel1highbyteDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710864ITIME(Address0x24)Figure77:ITIMERegisterAddr:0x24ITIMEBitBitNameDefaultAccessBitDescription7:0itime0RWLTFintegrationtime.
MODCLKis2/3MHz(666.
67kHz).
OneLSBofitimeis3.
072ms(2048MODCLKcycles).
0=3.
072ms.
.
.
255=786.
432msUsingtheitime_unitregister(seebelow),theunitofitimecanbereducedby2,4,or8.
Thisshorterintegrationtimescanbeselected(requiredforflickerdetection),butitcanalsobeusedtoincreasetheresolutionofitime.
Forexample,if50msintegrationtimearedesired,thebestvalueforregularitimewouldbe15(=16periods=49.
152ms).
However,butsettingitime_unit=2(LSB=768s),onecanselect64(=65periods=49.
9ms)Warning:selectinganintegrationtimesmallerthan3.
072mswillreducetheresolutionoftheconversion,asthemaximumltfdatavalueisnot1024(10bits)anymore,but512(9bits)incaseof1.
536msintegrationtime,256(8bits)for768sand128(7bits)for384sDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710865LTF_CONFIG(Address0x25)Figure78:LTF_CONFIGRegisterAddr:0x25LTF_CONFIGBitBitNameDefaultAccessBitDescription7infinite_itime0RWIfthisisasserted,thenintegrationdoesnotstop.
TheITIMEsettingisignored.
Usewithwatchtheltfdatacounters.
(Warning:mustbefilteredinsoftwaretopreventinconsistentupper/lowerbyte).
It'simplementedasacountdisableontheintegrationcounter,sowhenresettingbitto0again,theitimecounterwillcontinueandresultscanbereadafterwardsthroughtheregularmechanisms(ltfdataorFIFO)Thisisintendedforverylongintegrationtimes-asthetimingiscontrolledbysoftware/IC,accuracyfullydependsonthesystemandICmaster.
6az_disable_auto0RW0:RunautozeroonbothchannelseverytimeFMmodeisactivatedforthefirsttimeafterENABisbeingasserted.
1:Donotrunautozeroautomatically.
Autozerocanonlybeactivatedmanually(AZ_CONTROL)5:4reserved0RWReserved–leaveat01ltf_fifo_mode0RWRunLTFintegrationsbacktoback,theLTFmodulatorisrunningcontinuously(themodulatorsarenotresetbetweenintegrationscycles).
Aftereachintegration,theresultgetswrittentotheFIFO.
TheFIFOisbeingfilledautomatically,FIFOthresholdinterruptisflaggedasconfigured.
ThefirstitemreadfromtheFIFOisfromchannel0,thenextonefromchannel1,etc.
Notethatthereisnoltf_doneinterrupttriggeredaftereachintegration.
AFIFOthresholdof1canbeusedtogenerateaninterruptforeachresult.
irq_ltf_enabshouldbekeptassertedtoavoidmissinganltf_satinterrupt.
DonotenableADC/sequencerFIFOmodeandltf_fifo_modeatthesametime,corrupteddatawouldbetheresult.
MakesuretoemptytheFIFOintime,iftheFIFOisfull,newdataisnotbeingstoredintheFIFO.
SourceofdatareadfromtheFIFOafteranoverflowconditionisundefined(canbefromchannel0orchannel1)Stoptheprocedurebyclearingthisbit.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710866Addr:0x25LTF_CONFIGBitBitNameDefaultAccessBitDescription0ltf_enable0RWThisbitmustbeassertedforanyLTFfunction(powersuptheLTFclocktree)LTF_SEL(Address0x26)Figure79:LTF_SELRegisterAddr:0x26LTF_SELBitBitNameDefaultAccessBitDescription7Donotuse0RWDonotuse6:4ltf1_sel2RWSelectthesensordiodeforLTF1SettingSource0A1A/162B3B/164PD15PD26PD37PD42:0ltf0_sel0RWSelectthesensordiodeforLTF0SettingSource0A1A/162B3B/164PD15PD26PD37PD4DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710867LTF_GAIN(Address0x27)Figure80:LTF_GAINRegisterAddr:0x27LTF_GAINBitBitNameDefaultAccessBitDescription7:6Donotuse0RWDonotuse5:4itime_unit0RWSelecttheitimeunit.
SeeITIMEregisterdescription(Figure77).
SettingBehavior0Normal,timeLSB=3.
072ms1/2,LSB=1.
536ms2/4,timeLSB=768s3/8,timeLSB=384s3:0ltf_gain0RWSelectthegainSettingGain00.
2510.
5213244586167248649-15Reserved–donotuseLTF_CONTROL(Address0x28)Figure81:LTF_CONTROLRegisterAddr:0x28LTF_CONTROLBitBitNameDefaultAccessBitDescription7:1Donotuse0R_PUSHDonotuseDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710868Addr:0x28LTF_CONTROLBitBitNameDefaultAccessBitDescription0ltf_start0R_PUSHWriting1startsthecounter,anditwillrunforthespecifiedtime(itime).
Afterwardsitstopsautomaticallyandinterruptisflagged.
writing0tothecounterstopsitaswell.
readingthevaluereturnswhetherthecounterisrunning.
Ifltf_fifo_modeisnon-zero,thenFMconversionsaredonecontinuouslyuntila0iswrittentothisbitagain.
AZ_CONTROL(Address0x29)Figure82:AZ_CONTROLRegisterAddr:0x29AZ_CONTROLBitBitNameDefaultAccessBitDescription7:2Donotuse0RW_SMDonotuse1az_enable_10RW_SMWritinga'1'tothisregisterstartstheAZengineforchannel1.
Thisisusuallynotnecessary,asAZisexecutedautomaticallybeforethefirstLTFintegration(unlessaz_disable_autoisset)Thebitisclearedto'0'automaticallywhentheAZhasfinished.
Youcannotwritea'0'tothisregister.
0az_enable_00RW_SMThesameasaz_enable_1,butforchannel0.
OFFSET0(Address0x2a)Figure83:OFFSET0RegisterAddr:0x2aOFFSET0BitBitNameDefaultAccessBitDescription7:0offset0[7:0]0RW_SMThisregisterholdsthevalueoftheoffsetonthechannel0OpAmp.
Itcanbeoverwritten,anditgetsoverwrittenbytheauto-zeromechanism.
Thevalueisinsign/magnitudeencoding.
Thevalueis±127,sign/magnitudeDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710869OFFSET1(Address0x2b)Figure84:OFFSET1RegisterAddr:0x2bOFFSET1BitBitNameDefaultAccessBitDescription7:0offset0[7:0]0RW_SMThisregisterholdsthevalueoftheoffsetonthechannel1OpAmp.
Itcanbeoverwritten,anditgetsoverwrittenbytheauto-zeromechanism.
Thevalueisinsign/magnitudeencoding.
Thevalueis±127,sign/magnitudeDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108707.
1.
13ElectricalAnalogFrontEndTheelectricalanalogfrontendconsistsofthreeidenticalsignalpathswithindependentsettingsofbiascondition,gainandoffset.
Figure85:ElectricalAnalogFrontEndInternalCircuitDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710871DACSwitchingFigure86:ElectricalAnalogFrontEndDACLevelSwitchingIfbitdac_modeisnotzero,theDACswitchesitscodesbetweendac1_valueanddac2_valueonthebeginningofevery/every2nd/every4thsequencercyclewheretheADCisconvertingtheelectricalfrontendchannel.
ADCconversionsofanyotherchanneldonotswitchtheDAC.
InputPinsFourgeneralpurposepinsandECG_REFcanbeusedeitherasconfigurableGPIOpinorasanaloginputpinsfortheelectricalanalogfrontend.
Theanaloginputscanbeconfiguredtosetupdifferentamplifiertopologies.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108727.
1.
14EAF(ElectricalAnalogFrontend)RegistersAFE_CFG(Address0x70)Figure87:AFE_CFGRegisterAddr:0x70AFE_CFGBitBitNameDefaultAccessBitDescription7:4Donotuse0RWDonotuse3afe_enab0RW0…EAFbiasdeactivated1…EAFbiasactivated(needtobesetforanyfunctionsoftheEAFareused).
2afe_enab_dac0RW0…DACinsidetheEAFOFF1…DACinsidetheEAFON1afe_enab_dac_buf0RW0…DACbufferOFF1…DACbufferON0afe_enab_gainstage0RW0…GainstageinEAFOFF1…GainstageinEAFONTheAFE_CFGregisterisusedtoconfiguretheanalogfrontend.
EAF_GST(Address0x80)Figure88:EAF_GSTRegisterAddr:0x80EAF_GSTBitBitNameDefaultAccessBitDescription7:5gpio_gst_in0RWGainstageinputselectionSettingMeaning0Notconnected1GPIO02GPIO13GPIO24GPIO35ECG_REFDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710873Addr:0x80EAF_GSTBitBitNameDefaultAccessBitDescription4:3gst_ref0RWGainstagereferencevoltageSettingMeaning0AGND1DACbuffer2SIGREF3Reserved2:0gst_gain0RWGainstagegainSettingMeaning011224384165326647ReservedTheEAFregisterisusedtoconfiguretheelectricalfrontendEAF_BIAS(Address0x81)Figure89:EAF_BIASRegisterAddr:0x81EAF_BIASBitBitNameDefaultAccessBitDescription7:5gpio_r_bias0RWResistivebiasingSettingMeaning0Noresistivebiasing1ResistivebiasingonGPIO02ResistivebiasingonGPIO13ResistivebiasingonGPIO24ResistivebiasingonGPIO35ResistivebiasingonECG_REFDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710874Addr:0x81EAF_BIASBitBitNameDefaultAccessBitDescription4:0Notused0RWDonotuseEAF_DAC(Address0x82)Figure90:EAF_DACRegisterAddr:0x82AFE_CFGBitBitNameDefaultAccessBitDescription7:5Donotuse0RWDonotuse4sigref_on_dac_buf0RWIfasserted,connectSIGREFtoDACbuffer.
3measure_dac0RWIfthisbitisasserted,theDACoutputisconnectedtothegainstageinput(independentofgpio_gst_inselection,thereforetheDACoutputismeasurableontheGPIOpin)2:0gpio_dac0RWDAConGPIOSettingMeaning0NoDACbiasing1DAConGPIO02DAConGPIO13DAConGPIO24DAConGPIO35DAConECG_REFEAF_DAC1_L(Address0x83)Figure91:EAF_DAC1_LRegisterAddr:0x83EAF_DAC1_LBitBitNameDefaultAccessBitDescription7:6dac1_value[1:0]0RWDACvalue1(2LSB)5:0Notused0RWNotusedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710875TheEAF_DAC1/2_L/Hregistersisusedtoconfigurethedacvalue.
Seebitdac_modeforselectionofdacregister1or2EAF_DAC1_H(Address0x84)Figure92:EAF_DAC1_HRegisterAddr:0x84EAF_DAC1_HBitBitNameDefaultAccessBitDescription7:0dac1_value[9:2]0RWDACvalue1(upper8bits)10-bitvalue:0x000…0V0x3FF…1.
9VEAF_DAC2_L(Address0x85)Figure93:EAF_DAC2_LRegisterAddr:0x85EAF_DAC2_LBitBitNameDefaultAccessBitDescription7:6dac2_value[1:0]0RWDACvalue2(2LSB)5:0Notused0RWNotusedEAF_DAC2_H(Address0x86)Figure94:EAF_DAC2_HRegisterAddr:0x86EAF_DAC2_HBitBitNameDefaultAccessBitDescription7:0dac2_value[9:2]0RWDACvalue1(upper8bits)10-bitvalue:0x000…0V0x3FF…1.
9VDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710876EAF_DAC_CFG(Address0x87)Figure95:EAF_DAC_CFGRegisterAddr:0x85EAF_DAC_CFGBitBitNameDefaultAccessBitDescription7:2Notused0RWNotused1:0dac_mode0RWDACmodeTheEAFhasaDACthatcanbeswitchedoutonGPIOs.
dac_mode0usesstaticallydac1_value,theothermodesswitchdynamicallybetweenthetwovalues.
ThesystemswitchesfromonevaluetothenextalwaysatthebeginningofasequenceinwhichtheADCwillsampletheAFEchannel.
SettingMeaning01-1-1-1-1-1-1-1-1-1-1-11-2-1-2-1-2-1-2-1-2-1-21-1-2-2-1-1-2-2-1-1-2-31-1-1-1-2-2-2-2-1-1-1-PossibleConfigurationsofEveryAmplifierStageFigure96:NonInvertingAmplifierwithOffsetandInputVoltageDivider(TemperatureSensor)DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710877Figure97:NonInvertingAmplifierwithCurrentSourceandOffset(TemperatureSensor)Figure98:NonInvertingAmplifierwithCurrentSourceandReferencePath(TemperatureSensor)Figure99:NonInvertingAmplifierHighImpedance,GNDReferencedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710878Figure100:NonInvertingAmplifierwithDC-Blocking,ReferencedtoV_ADCRef/2Figure101:NonInvertingAmplifierwithDC-BlockingandFastSettlingTime,ReferencedtoADCRef/2DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108797.
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15ECGAmplifierFigure102:ECGAmplifierTheECG(electrocardiogram)amplifierisahighimpedance,lownoiseinstrumentationamplifierwithanalogcircuitrytobandpassfilterthesignalandamplifyitbeforeconvertingitwiththeADC.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710880ECGLeadOFFDetectionFigure103:ECGLeadOFFDetectionInternalCircuitTheECGleadOFFdetectioncanbeusedfordetectioniftheuseractuallytouchestheleads.
Itisacircuitrytomeasurethecapacitorand/orresistancebetweenthetwoleadinputsECG_INPandECG_INN.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108817.
1.
16ECGRegistersECG_CFGA(Address0x5c)Figure104:ECG_CFGARegisterAddr:0x5cECG_CFGABitBitNameDefaultAccessBitDescription7ecg_en0RWEnableECGinstrumentationamplifier6notused0RWDonotrelyonthecontentofthisregister5ecg_lp_en0RW0…LPfilterdisabled1…LPfilterenabled4ecg_hp_en0RW0…Powerdownofthehighpassfilter1…Enablehighpassfilter3ecg_gain_en0RW0…PowerdownoftheGainstage1…EnableGainstage2ecg_lp_byp0RW0…LPstageisused1…LPstageisbypassed1ecg_hp_byp0RW0…HPfilterisused1…HPfilterisbypassed0ecg_gain_byp0RW0…Gainstageisused1…GainstageisbypassedECG_CFGB(Address0x5d)Figure105:ECG_CFGBRegisterAddr:0x5dECG_CFGBBitBitNameDefaultAccessBitDescription7Notused0RWDonotused6:5ecg_lp_freq0RWECGlowpassfilterSettingFrequency040Hz180Hz3160Hz4320HzDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710882Addr:0x5dECG_CFGBBitBitNameDefaultAccessBitDescription4:3ecg_hp_freq0RWHighpassfiltercutofffrequencySettingFilterFrequencyCutoffFrequency0122Hz0.
33Hz1488Hz1.
32Hz21935Hz5.
28Hz33906Hz10.
56Hz2:0ecg_gain_g0RWGainSettingGain011224384165326647128ECG_CFGC(Address0x5e)Figure106:ECG_CFGCRegisterAddr:0x5eECG_CFGCBitBitNameDefaultAccessBitDescription7:2Notused0RWDonotuse1ecg_low_leakage_en0RWEnableECGleakagecompensation0ecg_ref_en0RWECGReferenceFeedbackAmplifierEnableDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710883ECG_CFGD(Address0x5f)Figure107:ECG_CFGDRegisterAddr:0x5fECG_CFGDBitBitNameDefaultAccessBitDescription7:5Notused0RWDonotused4ecg_leadsdet_sync_adc0RWECGLeadsDetectionAutomaticUpdate.
Ifthisisasserted,thenecg_leadsdet_polisinvertedautomaticallyatthestartofasequence(atcount=2)ifinthissequencetheADCwillconverttheECGichannel.
3ecg_leadsdet_pol0RWECGLeadsDetectionPolarity.
Canbewrittentomanuallyifecg_leadsdet_sync_adcisclear,otherwiseitisautomaticallytoggled.
2:1ecg_leadsdet_curr0RWECGLeadsDetectionCurrentSettingCurrent020nA1100nA2500nA31A0ecg_leadsdet_en0RWECGLeadsDetectionEnable7.
1.
17ADCandFIFOTheADCisa14-bitsuccessive-approximationregister(SAR)type.
Itsupports14-bitwithconversiontimeupto50ksps.
TheADCisstartedbythesequenceranditstimingorinmanualmode(man_mode=1)bysettingseq_start=1(seq_startstays'1'aslongastheconversionruns).
TheAS7026GGcanbeconfiguredtotriggeraninterruptuponendofconversion.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710884Figure108:ADCInternalCircuitandMultiplexerForbestaccuracy,theADCcanbeoptionallycalibrated.
InformationIfGPIO2orGPIO3isusedasADCinput,thereisnoanti-aliasingfilterinfrontoftheADC(needstobeaddedexternally).
7.
1.
18ADCThresholdAttheoutputoftheADCconverteradigitalthresholdcanbeenabled.
IftheoutputoftheADCexceedsthethresholdadc_threshold,ittriggersaninterrupt.
Thismechanismcanbeusedtoidentifyifanobjectisinproximityofthesensorandthentointerruptthehost.
Incaseswherenoobjectisdetected,thehostcanbesleepingthereforereducingpowerconsumptionofthesystem.
FordetaileddescriptionofthethresholdcalculationseetheregisterADC_THRESHOLDandADC_THRESHOLD_CFGdescriptionDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108857.
1.
19ADCRegistersADC_THRESHOLD(Address0x68)Figure109:ADC_THRESHOLDRegisterAddr:0x68ADC_THRESHOLDBitBitNameDefaultAccessBitDescription7:0adc_threshold0xffRWIftheADCreturnsavalueaboveadc_threshold(notequal),thentheadc_thresholdinterruptcanbetriggered.
Notethatwhenonlytheupper8bitsarecompared,thelower6bitsareignored.
Avalueof0xffcanthereforenevertriggertheinterruptADC_THRESHOLD_CFG(Address0x69)Figure110:ADC_THRESHOLD_CFGRegisterAddr:0x69ADC_THRESHOLD_CFGBitBitNameDefaultAccessBitDescription7:2NotUsed0RWNotused1adc_thresh_differential0RWIfadc_thresh_tiaonlyisassertedandanyofseq_adc[23]tiaisnon-zero,meaningthattherearetwoorthreeADCTIAmeasurementsinonesequencerperiod,thenthesecondissubtractedfromthefirst,andthedifferenceisbeingcomparedtotheadc_threshold.
0adc_thresh_tiaonly0RWNormally,theadc_thresholdworksregardlessoftheadcchannel.
Ifthisbitisset,thenthethresholdisonlycheckediftheadcchannelisTIADocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710886ADC_CFGA(Address0x88)Figure111:ADC_CFGARegisterAddr:0x88ADC_CFGABitBitNameDefaultAccessBitDescription7:4NotUsed0RWNotused3:1adc_multi_n0RWDefinesnumberofsamplesthataretakeninmultimode(adc_multimode=1)SettingNumberofSamplesperADCConversionCommand0214283164325486647960adc_multimode0RW0…IfADCisstartedonesampleismeasured1…IfADCisstartedmultiplesamplesarestoredinsequenceintheFIFO.
Thenumberofsamplesisdefinedwith"adc_multi_n".
InformationIftheADCistriggeredwiththesequencer,theveryfirstADCconversionafterseq_en=1storesthenumberofsamplesaccordingtoabovetable.
Allsubsequentsamplesuseonesampleless(e.
g.
7insteadof8).
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710887ADC_CFGB(Address0x89)Figure112:ADC_CFGBRegisterAddr:0x89ADC_CFGBBitBitNameDefaultAccessBitDescription7:6NotUsed0RWNotused5:3adc_clock0RWADCclockdivider:TheADCclockisfreelyconfigurableSettingPeriodsskHz021100014250026333338425041052005126167614714371681252adc_calibration0RWToactivatetheoptionalselfcalibration,thisbitmustbeasserted,andanADC"conversion"hastobestartedinmanualmode(man_mode=1)byassertingseq_start.
1ulp0RWUltralowpowerbitforthesequencer.
Ifthisbitissetandsd_subs>0,itdisablestheLEDpulsesandpowersofftheTIAinallsequencesbuttheonewheretheTIAissampled.
0adc_en0RW0…ResetADC1…EnableADCWarning:InresetstatetheADCclearsitscalibrationdata.
Re-calibrationisnecessarynexttimeitisenabledagain.
ADC_CFGC(Address0x8a)Figure113:ADC_CFGCRegisterAddr:0x8aADC_CFGCBitBitNameDefaultAccessBitDescription7:5NotUsed0RWNotusedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710888Addr:0x8aADC_CFGCBitBitNameDefaultAccessBitDescription4adc_selfpd0RW1…PowerdowntheADCwhennotconverting;usethistoconservepower,butsetadc_settling_timetominimum64ustopermitsettlingoftheADCreferencebuffer.
0…AlwaysenableADC3adc_discharge0RW0:SuppressADCcapacitordischarging–usewithcaution1:DischargeADCcapacitorbeforetrackingIfasserted,thecapacitorisdischargedbeforethetrackingphase.
Ifzero,thedischargephaseissuppressedandthetrackingphaseisstartedonecycleearlier2:0adc_settling_time0RWADCsettlingtime:Usewithsynchronousdemodulator.
ItdefinesthenumberofADCclockcyclesthesamplingwindowiskeptopenadditionally.
Ifthegainstageintheopticalfrontendisused(gain_byp=0),setthistominimum8s.
Ifadc_selfpd=1,setthistominimum64s.
SettingPeriodss(@500kHz)s(@250kHz)000014816281632316326443264128564128256612825651272565121msADC_CHANNEL_MASK_L(Address0x8b)Figure114:ADC_CHANNEL_MASK_LRegisterAddr:0x8bADC_CHANNEL_MASK_LBitBitNameDefaultAccessBitDescription7adc_channel_mask_pregain0RWPregainchannelselection6adc_channel_mask_afe0RWElectricalfrontendDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710889Addr:0x8bADC_CHANNEL_MASK_LBitBitNameDefaultAccessBitDescription5adc_channel_mask_temp0RWTemperaturemeasurement4adc_channel_mask_sd20RWSynchronousmodulator2outputjustbeforethegainstage3adc_channel_mask_ofe20RWSynchronousmodulator2outputafterthegainstage2adc_channel_mask_sd10RWSynchronousmodulator1outputjustbeforethegainstage1adc_channel_mask_ofe10RWSynchronousmodulator1outputafterthegainstage0adc_channel_mask_tia0RWTransimpedanceamplifieroutputTheadcchannelischosenautomaticallyfromthebitswithintheadc_channel_mask_*set.
Itstartsfromrightandfinishesleft(LSB->MSB)andwrapsbackfromthemostsignificantassertedbittotheleastsignificantoftheassertedbits.
AftereveryADCconversionitswitchestothenextenabledchannel,(exceptaroundtheadc2tia/adc3tiacases).
SeeregisterdescriptionFIFOHandFIFOLforencodingofthefirstchannelinthedatastream.
Thisappliestoboth,manualmodeandsequencermode.
Insequencermode,itstartswiththesmallestchannelwhenthesequencerisbeingstarted.
Inmanualmode,theadc_selisresetwitheverywritetoeitherADC_CHANNEL_MASK_LorADC_CHANNEL_MASK_H.
ADC_CHANNEL_MASK_H(Address0x8c)Figure115:ADC_CHANNEL_MASK_HRegisterAddr:0x8cADC_CHANNEL_MASK_HBitBitNameDefaultAccessBitDescription7:4Notused0RWNotused3adc_channel_mask_gpio20RWGPIO2input–setgpio2_a=1andWrite0x47toregister0xC6Write0x0Ctoregister0xC2Write0x0Ctoregister0xC32adc_channel_mask_gpio30RWGPIO3input–setgpio3_a=1andWrite0x47toregister0xC6Write0x0Ctoregister0xC2Write0x0Ctoregister0xC31adc_channel_mask_ecgi0RWECGamplifierinput–useforleadsoffdetectionDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710890Addr:0x8cADC_CHANNEL_MASK_HBitBitNameDefaultAccessBitDescription0adc_channel_mask_ecgo0RWECGamplifieroutput–amplifiedECGsignalADC_DATA_L(Address0x8e)Figure116:ADC_DATA_LRegisterAddr:0x8eADC_DATA_LBitBitNameDefaultAccessBitDescription7:0adc_data[7:0]0ROCurrentADCoutput:lowbyteTheADC_DATAregistershowsthecurrentrawoutputoftheADC.
ADC_DATA_H(Address0x8f)Figure117:ADC_DATA_HRegisterAddr:0x8fADC_DATA_HBitBitNameDefaultAccessBitDescription7:6Notused0RONotused5:0adc_data[13:8]0ROCurrentADCoutput:highbytewarning:thereisnolatchmechanismimplementedtoguaranteeconsistencyiftheADCispossiblyrunningwhenreadingthisregister,thenthedatacanbecorrupted-usetheFIFOtoguaranteedataconsistencyDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108917.
1.
20FIFORegistersFIFO_CFG(Address0x78)Figure118:FIFO_CFGRegisterAddr:0x78FIFO_CFGBitBitNameDefaultAccessBitDescription7:6Notused0RWNotused5:0fifo_threshold0RWFIFOthreshold.
Thefifo_thresholdinterruptisflaggediftherearemorethanthismanyentriesintheFIFO.
0…Interruptwith1(16-bit)entryinFIFO63…InterruptwhenFIFOisfullbutone;notethattheFIFOis64entriesdeepFIFO_CNTRL(Address0x79)Figure119:FIFO_CNTRLRegisterAddr:0x79FIFO_CNTRLBitBitNameDefaultAccessBitDescription7:1Notused0RWNotused0fifo_clear0PUSH1Writea1heretocleartheFIFO.
CanbeusefulwhenswitchingfromonesequencermodetoanothertomakesurethattherearenooldFIFOentriesleftDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710892FIFOSTATUS(Address0xa3)Figure120:FIFOSTATUSRegisterAddr:0xa3FIFOSTATUSBitBitNameDefaultAccessBitDescription7fifooverflow0ROFIFOoverflowindicator6:0fifolevel0ROFIFOfilllevel(0…64)FIFOL(Address0xfe)Figure121:FIFOLRegisterAddr:0xfeFIFOLBitBitNameDefaultAccessBitDescription7:0fifol0PUSHPOPLowbyteofFIFOFIFOLcanbereadoutwithsinglereads(2consecutiveICaddresseshavetobereadtogetoneFIFOentry)orwithblock-read(upto2xfifo_depthvaluescanbereadinasingleblock-read)UponreadingofFIFOH,itautomaticallyadvancestheinternalreadpointeranddecreasesFIFOlevel.
IfreadingbeyondendofFIFO,datawillreturn00h.
Thereisnounderrunflag,thisisnotanerrorcondition.
UseamsSDKfunctionstoreadfromtheFIFOregistertokeepthereadinginsynchronizationwiththeADCchannelselection.
Ifsynchronizationisnoconcernuse[fifoh[7:0]:fifol[7:2]]asADCresultastheADCdataismultipliedbyx4beforeitispushedintotheFIFO.
FIFOl[0]isusedasanADCfirstchannelindication.
ThefirstchannelindicationbittogglesuponeverynewentryunlessthefirstADCchannelistransmitted.
Thentogglingcanbestoppedforupto5FIFOentriesandtheveryfirststoppingindicatesthefirstADCchannel.
ToallowencodingofanynumberofADCchannels,thefirstADCchannelencodingisdroppedfromtimetotime.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710893FIFOH(Address0xff)Figure122:FIFOHRegisterAddr:0xffFIFOHBitBitNameDefaultAccessBitDescription7:0fifoh0PUSHPOPHighbyteofFIFOSeeInterruptsfortheactualFIFOinterrupt.
7.
1.
21DigitalInterfacePowerManagementAftersettingthepinENABLE=1theAS7026GGregisterscanbeaccessedbytheICinterface.
Beforeenablinganyadditionalfunction(currentsource,TIA,ADC…)setthebitldo_en=1tosettheinternalLDOtonormalmode.
ForoperatingtheADCorthesequencerenabletheoscillatorbysettingosc_en=1GPIOPinsFigure123:GPIOInternalCircuitDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710894InterruptsAninterruptoutputpinINTcanbeusedtointerruptthehost.
Followinginterruptsourcesarepossible:irq_adc:EndofADCconversionirq_sequencer:Endofsequencersequencereached.
irq_ltf:Alight-to-frequencyconversionisfinished.
irq_adc_threshold:ADCthresholdtriggered–seeADCThreshold.
irq_fifothreshold:FIFOalmostfull(asdefinedinbitfifo_threshold)irq_fifooverflow:FIFOoverflow(errorcondition,dataislost)irq_clipdetect:TIAoutputand/orSDoutputexceededthreshold–seedetailsinCLIPSTATUSirq_led_supply_low:ledsupplylowcomparatortriggered–seedetailsinLEDSTATUSDependingonthesettinginregisterINTENABeachoftheaboveinterruptsourcecanassertINToutputpin(activelow).
7.
2ICTheAS7026GGincludesanICslaveusinganICaddressof0x30(7-bitformat;R/Wbithastobeadded)respectively60h(8-bitformatforwriting)and61h(8-bitformatforreading).
Itexpectsexternalpullupresistors.
7.
2.
1ICSerialControlInterfaceICFeatureListFastmode(400kHz)andstandardmode(100kHz)support7+1-bitaddressingmodeWriteformats:Single-Byte-Write,Page-WriteReadformats:Current-Address-Read,Random-Read,Sequential-ReadSDAinputdelayandSCLspikefilteringbyintegratedRC-componentsDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710895ICProtocolFigure124:ICSymbolDefinitionSymbolDefinitionRWNoteSStartconditionafterstopR1-bitSrRepeatedstartR1-bitDWDeviceaddressforwriteR01100000b(60h)DRDeviceaddressforreadR01100001b(61h)WAWordaddressR8-bitAAcknowledgeW1-bitNNoAcknowledgeR1-bitreg_dataRegisterdata/writeR8-bitdata(n)Registerdata/readW8-bitPStopconditionR1-bitWA++IncrementwordaddressinternallyRDuringacknowledgeICSymbolDefinition:Showsthesymbolsusedinthefollowingmodedescriptions.
ICWriteAccessByteWriteandPageWriteformatsareusedtowritedatatotheslaveFigure125:ICByteWriteICByteWrite:ShowstheformatofanICbytewriteaccessDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710896Figure126:ICPageWriteICPageWrite:ShowstheformatofanICpagewriteaccessThetransmissionbeginswiththeSTARTcondition,whichisgeneratedbythemasterwhenthebusisinIDLEstate(thebusisfree).
Thedevice-writeaddressisfollowedbythewordaddress.
Afterthewordaddressanynumberofdatabytescanbesenttotheslave.
Thewordaddressisincrementedinternally,inordertowritesubsequentdatabytesonsubsequentaddresslocations.
Forreadingdatafromtheslavedevice,themasterhastochangethetransferdirection.
ThiscanbedoneeitherwitharepeatedSTARTconditionfollowedbythedevice-readaddress,orsimplywithanewtransmissionSTARTfollowedbythedevice-readaddress,whenthebusisinIDLEstate.
Thedevice-readaddressisalwaysfollowedbythe1stregisterbytetransmittedfromtheslave.
InReadmodeanynumberofsubsequentregisterbytescanbereadfromtheslave.
Thewordaddressisincrementedinternally.
Figure127:ICRandomReadICRandomRead:ShowstheformatofanICrandomreadaccessRandomReadandSequentialReadarecombinedformats.
TherepeatedSTARTconditionisusedtochangethedirectionafterthedatatransferfromthemaster.
ThewordaddresstransferisinitiatedwithaSTARTconditionissuedbythemasterwhilethebusisidle.
TheSTARTconditionisfollowedbythedevice-writeaddressandthewordaddress.
InordertochangethedatadirectionarepeatedSTARTconditionisissuedonthe1stSCLpulseaftertheacknowledgebitofthewordaddresstransfer.
Afterthereceptionofthedevice-readaddress,theslavebecomesthetransmitter.
Inthisstatetheslavetransmitsregisterdatalocatedbythepreviousreceivedwordaddressvector.
Themasterrespondstothedatabytewithanot-acknowledge,andissuesaSTOPconditiononthebus.
DocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710897Figure128:ICSequentialReadICSequentialRead:ShowstheformatofanICsequentialreadaccessSequentialReadistheextendedformofRandomRead,asmorethanoneregister-databytesaretransferredsubsequently.
IndifferencetotheRandomRead,forasequentialreadthetransferredregister-databytesarerespondedbyanacknowledgefromthemaster.
Thenumberofdatabytestransferredinonesequenceisunlimited(considerthebehavioroftheword-addresscounter).
Toterminatethetransmissionthemasterhastosendanot-acknowledgefollowingthelastdatabyteandgeneratetheSTOPconditionsubsequently.
Figure129:ICCurrentAddressReadICCurrentAddressRead:ShowstheformatofanICcurrentaddressreadaccess.
Tokeeptheaccesstimeassmallaspossible,thisformatallowsareadaccesswithoutthewordaddresstransferinadvancetothedatatransfer.
ThebusisidleandthemasterissuesaSTARTconditionfollowedbytheDevice-Readaddress.
AnalogoustoRandomRead,asinglebytetransferisterminatedwithanot-acknowledgeafterthe1stregisterbyte.
AnalogoustoSequentialReadanunlimitednumberofdatabytescanbetransferred,wherethedatabyteshastoberespondedwithanacknowledgefromthemaster.
Forterminationofthetransmissionthemastersendsanot-acknowledgefollowingthelastdatabyteandasubsequentSTOPcondition.
CONTROL(Address0x00)Figure130:CONTROLRegisterAddr:0x00CONTROLBitBitNameDefaultAccessBitDescription7:2NotUsed0RWNotUsedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710898Addr:0x00CONTROLBitBitNameDefaultAccessBitDescription1osc_en0RWEnabletheoscillator.
Theoscillatormustbeenabledforanyanalogblock(ADC,sequencer,opticalfrontend,sequencer);notmandatoryforcurrentsinksorECGamplifier0ldo_en0RWIftheENinputisnotasserted,thechipisinresetIfasserted,ICtransactionsarepossible.
Uponassertionofldo_en,thereferenceandtheLDOareenabledTheLDOmustbeenabledforanythingbutplainICregisterread/writeGPIO_A(Address0x08)Figure131:GPIO_ARegisterAddr:0x08GPIO_ABitBitNameDefaultAccessBitDescription7:4NotUsed0RWNotUsed3gpio3_a0RW1=PutGPIO3inanalogmode;setthisbitwhenusedforananalogfunctione.
g.
theelectricalfrontend.
IfsetexecutefollowingICcommands(otherwiseaninternalpulldownwillbeenabled)inthissequence:Write0x47toregister0xC6Write0x0Ctoregister0xC2Write0x0Ctoregister0xC32gpio2_a0RW1=PutGPIO2inanalogmodeIfsetexecutefollowingICcommands(otherwiseaninternalpulldownwillbeenabled)inthissequence:Write0x47toregister0xC6Write0x0Ctoregister0xC2Write0x0Ctoregister0xC31gpio1_a0RW1=PutGPIO1inanalogmode0gpio0_a0RW1=PutGPIO0inanalogmodeDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-1710899GPIO_E(Address0x09)Figure132:GPIO_ERegisterAddr:0x09GPIO_EBitBitNameDefaultAccessBitDescription7:4NotUsed0RWNotUsed3gpio3_e0RWGPIO3outputenabledifset2gpio2_e0RWGPIO2outputenabledifset1gpio1_e0RWGPIO1outputenabledifset0gpio0_e0RWGPIO0outputenabledifsetGPIO_O(Address0x0a)Figure133:GPIO_ORegisterAddr:0x0aGPIO_OBitBitNameDefaultAccessBitDescription7:4NotUsed0RWNotUsed3gpio3_o0RWIfgpio3_e=1,gpio3_odefinestheoutputstateofGPIO32gpio2_00RWIfgpio2_e=1,gpio2_odefinestheoutputstateofGPIO21gpio1_00RWIfgpio1_e=1,gpio1_odefinestheoutputstateofGPIO10gpio0_00RWIfgpio0_e=1,gpio0_odefinestheoutputstateofGPIO0GPIO_I(Address0x0b)Figure134:GPIO_IRegisterAddr:0x0bGPIO_IBitBitNameDefaultAccessBitDescription7:4NotUsed0RONotUsedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108100Addr:0x0bGPIO_IBitBitNameDefaultAccessBitDescription3gpio3_i0ROThedigitalvaluesensedonGPIO32gpio2_i0ROThedigitalvaluesensedonGPIO21gpio1_i0ROThedigitalvaluesensedonGPIO10gpio0_i0ROThedigitalvaluesensedonGPIO0GPIO_P(Address0x0c)Figure135:GPIO_PRegisterAddr:0x0cGPIO_PBitBitNameDefaultAccessBitDescription7gpio3_pd0RWGPIO3pulldownconfiguration0:NopulldownonGPIO31:PulldowntoGNDonGPIO36gpio3_pu0RWGPIO3pullupconfiguration0:NopulluponGPIO31:PulluptoVDDonGPIO35gpio2_pd0RWGPIO2pulldownconfiguration4gpio2_pu0RWGPIO2pullupconfiguration3gpio1_pd0RWGPIO1pulldownconfiguration2gpio1_pu0RWGPIO1pullupconfiguration1gpio0_pd0RWGPIO0pulldownconfiguration0gpio0_pu0RWGPIO0pullupconfigurationGPIO_SR(Address0x0d)Figure136:GPIO_SRRegisterAddr:0x0cGPIO_SRBitBitNameDefaultAccessBitDescription7:4NotUsed0RWNotUsedDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108101Addr:0x0cGPIO_SRBitBitNameDefaultAccessBitDescription3gpio3_sr0RWGPIO3slewrateconfiguration0:Defaultslewrate1:Increasedslewrate2gpio2_sr0RWGPIO2slewrateconfiguration1gpio1_sr0RWGPIO1slewrateconfiguration0gpio0_sr0RWGPIO0slewrateconfigurationSUBID(Address0x91)Figure137:SUBIDRegisterAddr:0x91SUBIDBitBitNameDefaultAccessBitDescription7:3subidNARODefinesproductversion.
Donotrelyonbitsdefinedas'X'.
1XXXXb2:0RevisionNAROReserved.
Donouseanddonotrelythatthecontentstaysthesameforeachdevice.
ID(Address0x92)Figure138:IDRegisterAddr:0x92IDBitBitNameDefaultAccessBitDescription7:2id0ROPartNumberIdentification.
ValueMeaning110011AS7026GG1:0id_reserved0ROReserved.
DonouseanddonotrelythatthecontentstaysthesameforeachdeviceDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108102STATUS(Address0xa0)Figure139:STATUSRegisterAddr:0xa0STATUSBitBitNameDefaultAccessBitDescription7irq_led_supply_low0R_PUSH1CheckLEDSTATUS6irq_clipdetect0R_PUSH1CheckCLIPSTATUS5irq_fifooverflow0R_PUSH1FIFOoverflow(errorcondition,newdataislost)4irq_fifothreshold0R_PUSH1FIFOisalmostfull(asdefinedinfifo_threshold,usually3/4)3irq_adc_threshold0R_PUSH1TheADCvaluewasabovetheprogrammedadc_thresholdregistersetting2irq_ltf0R_PUSH1LTFmeasurementisdone.
checkLTFSTATUS(orignoreit)1irq_sequencer0R_PUSH1Allconfiguredsequenceriterationshavefinished0irq_adc0R_PUSH1ADChasfinishedTheSTATUSregistershowsthecurrentstateoftheinterface.
Somebitsinherecantriggeraninterrupt.
Anassertedbitcanbeclearedbywritinga'1'toit-incaseofirq_led_supply_lowandirq_clipdetect,thisalsoclearstheunderlyingconditionintheCLIPSTATUSandLEDSTATUSregisters.
TheFIFOthresholdinterruptcannotbecleareddirectly,butonlybyloweringtheFIFOlevel.
TheFIFOoverflowinterruptisstickyandmustbeclearedexplicitly.
CLIPSTATUS(Address0xa1)Figure140:CLIPSTATUSRegisterAddr:0xa1CLIPSTATUSBitBitNameDefaultAccessBitDescription7:4Notused0RONotUsed3pd_clipdetect_lIfthisbitisasserted,photodiodeamplifierhasbeenbelowthelowerthresholdDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108103Addr:0xa1CLIPSTATUSBitBitNameDefaultAccessBitDescription2pd_clipdetect_hIfthisbitisasserted,photodiodeamplifierhasbeenabovetheupperthreshold1sd_clipdetect_lIfthisbitisasserted,photodiodeamplifierhasbeenbelowthelowerthreshold0sd_clipdetect_hIfthisbitisasserted,photodiodeamplifierhasbeenabovetheupperthresholdLEDSTATUS(Address0xa2)Figure141:LEDSTATUSRegisterAddr:0xa2LEDSTATUSBitBitNameDefaultAccessBitDescription7:4Notused0RONotUsed3led4_supply_low0ROIfthisbitisasserted,LED4voltagehasbeentoolow2led3_supply_low0ROIfthisbitisasserted,LED3voltagehasbeentoolow1led2_supply_low0ROIfthisbitisasserted,LED3voltagehasbeentoolow0led1_supply_low0ROIfthisbitisasserted,LED1voltagehasbeentoolowINTENAB(Address0xa8)Figure142:INTENABRegisterAddr:0xa8INTENABBitBitNameDefaultAccessBitDescription7irq_led_supply_low_enab0RW1…Enableledsupplylowinterrupt6irq_clipdetect_enab0RW1…Enableclipdetectinterrupt5irq_fifooverflow_ena0RW1…EnablefifooverflowinterruptDocumentFeedbackAS7026GGRegisterDescriptionDatasheetPUBLICDS000622v2-002019-Sep-17108104Addr:0xa8INTENABBitBitNameDefaultAccessBitDescription4irq_fifothreshold_enab0RW1…Enablefifothresholdinterrupt3irq_adc_threshold_enab0RW1…Enableirq_adc_thresholdasaninterruptsource2irq_ltf_enab0RW1…EnableLTFasaninterruptsource1irq_sequencer_enab0RW1…Enableirq_sequencerasaninterruptsource0irq_adc_enab0RW1…Enableirq_adcasaninterruptsourceEachoftheSTATUSregisterbitscancauseaninterrupt(registerINTR)iftherespectivebitisassertedintheINTENABregisterINTR(Address0xa9)Figure143:INTRRegisterAddr:0xa9INTRBitBitNameDefaultAccessBitDescription7irq_led_supply_low_intr0RO6irq_clipdetect_intr0RO5irq_fifooverflow_intr0RO4irq_fifothreshold_intr0RO3irq_adc_threshold_intr0RO2irq_ltf_intr0RO1irq_sequencer_intr0RO0irq_adc_intr0ROTheINTRregistersshowsthebitorbitsthatareresponsibleforanassertedinterrupt.
Effectively,thesebitsareOR-edtogethertodrivetheinterruptpinINTlow(opendrainoutput).
DocumentFeedbackAS7026GGApplicationInformationDatasheetPUBLICDS000622v2-002019-Sep-171081058ApplicationInformation8.
1ApplicationExamplesThefollowingfigureshowsthecompleteintegrationoftheAS7026GGinamobileopticalmeasurementsystemforHRM,SpO2,GSR(galvanicskinresistivity)andskintemperatureusinganNTC.
ThedevicecanbepowereddirectlybyaLi-ionbatteryasithasitsownpowermanagement.
NeverthelesstheI2Cinterfacecanbepoweredby1.
8Vcircuitry.
InformationAS7026GGcanbeusedinthesameconfigurationfore.
g.
afitnessbandorasmartwatch.
Figure144:AS7026GGOpticalHRMMeasurementSystemforWristBasedApplicationDocumentFeedbackAS7026GGPackageDrawings&MarkingsDatasheetPUBLICDS000622v2-002019-Sep-171081069PackageDrawings&MarkingsFigure145:AS7026GGPackageOutlineDrawingRef.
MinNomMaxA0.
9111.
1A10.
2REFA20.
8REFD6.
2BSCE2.
75BSCW0.
20.
250.
3L0.
550.
60.
65e0.
633BSCn20D15.
697BSCE11.
95BSCSD0.
3165BSCSEBSCaaa0.
1ddd0.
08(1)Alldimensionsareinmillimeters.
Anglesindegrees.
(2)DimensioningandtolerancingconformtoASMEY14.
5M-1994.
(3)nisthetotalnumberofterminals.
(4)Thispackagecontainsnolead(Pb).
(5)Thisdrawingissubjecttochangewithoutnotice.
DocumentFeedbackAS7026GGRevisionInformationDatasheetPUBLICDS000622v2-002019-Sep-1710810710RevisionInformationDocumentStatusProductStatusDefinitionProductPreviewPre-DevelopmentInformationinthisdatasheetisbasedonproductideasintheplanningphaseofdevelopment.
AllspecificationsaredesigngoalswithoutanywarrantyandaresubjecttochangewithoutnoticePreliminaryDatasheetPre-ProductionInformationinthisdatasheetisbasedonproductsinthedesign,validationorqualificationphaseofdevelopment.
TheperformanceandparametersshowninthisdocumentarepreliminarywithoutanywarrantyandaresubjecttochangewithoutnoticeDatasheetProductionInformationinthisdatasheetisbasedonproductsinramp-uptofullproductionorfullproductionwhichconformtospecificationsinaccordancewiththetermsofamsAGstandardwarrantyasgivenintheGeneralTermsofTradeDatasheet(discontinued)DiscontinuedInformationinthisdatasheetisbasedonproductswhichconformtospecificationsinaccordancewiththetermsofamsAGstandardwarrantyasgivenintheGeneralTermsofTrade,buttheseproductshavebeensupersededandshouldnotbeusedfornewdesignsChangesfrompreviousversiontocurrentrevisionv2-00PageUpdateOrderingInformation5Pageandfigurenumbersforthepreviousversionmaydifferfrompageandfigurenumbersinthecurrentrevision.
Correctionoftypographicalerrorsisnotexplicitlymentioned.
DocumentFeedbackAS7026GGLegalInformationDatasheetPUBLICDS000622v2-002019-Sep-1710810811LegalInformationCopyrights&DisclaimerCopyrightamsAG,TobelbaderStrasse30,8141Premstaetten,Austria-Europe.
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