INPUTadsl原理
adsl原理 时间:2021-05-09 阅读:()
UltralowPower,AdaptiveLinearPower,Dual-PortADSL/ADSL2+LineDriverDataSheetADLD8403Rev.
DDocumentFeedbackInformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.
However,noresponsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorotherrightsofthirdpartiesthatmayresultfromitsuse.
Specificationssubjecttochangewithoutnotice.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofAnalogDevices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
OneTechnologyWay,P.
O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:781.
329.
47002014–2017AnalogDevices,Inc.
Allrightsreserved.
TechnicalSupportwww.
analog.
comFEATURES2differentialDSLchannelscomprisingcurrentfeedback,highoutputcurrentamplifierswithintegratedfeedbackresistorsplusbiasingnetworkIdealforuseasADSL/ADSL2+dual-channelcentraloffice(CO)linedriversLowpowerconsumptionusingClassHtechnologySingle12.
5Vsupplyoperation20.
4dBmlinepower,1:1transformerLessthan600mWperchanneltotalpowerdissipationwhiledriving20.
4dBm(includes110mWlinepower)Lessthan275mWperchanneltotalpowerdissipationwhiledriving14.
5dBm(includinglinepower)Highoutputvoltageandcurrentdrive43.
4VdifferentialoutputvoltageswingLowdistortion65dBctypicalmultitonepowerratio(MTPR)at20.
4dBm,26kHzto2.
2MHzLowcostprotectioncomponentsenableITU-T-K20andGR-1089complianceAPPLICATIONSADSL/ADSL2+COlinedriversINTERNALSCHEMATICVEEPVCCPVCCAV=13V/VVOPAVONAINPAVCOM_AINNAVCC4k4k08848-001Figure1.
ChannelAInternalSchematicGENERALDESCRIPTIONTheADLD8403comprisestwodifferential,highoutputcurrent,lowpowerconsumptionoperationalamplifiers.
ItisparticularlywellsuitedfortheCOdriverinterfaceindigitalsubscriberlinesystems,suchasADSLandADSL2+.
Thedrivercandeliver20.
4dBmtoalinewhilecompensatingforlossesduetohybridinsertionandbackterminationresistors.
TheADLD8403usestheAnalogDevices,Inc.
,secondgenerationAdaptiveLinearPower(ClassH)architecturetoachieveunprecedentedpowerefficiencyusingasinglepowersupply.
Additionalfunctionalityallowstheshutdownofpumpsforenhancedpowersavingsforlinepowersoflessthan14.
5dBm.
Thisfunctionalityyieldsthesmallestprintedcircuitboard(PCB)footprintandlowesttotalcostofownership.
Thelowpowerconsumption,highoutputcurrent,highoutputvoltageswing,androbustthermalpackagingenabletheADLD8403tobetheCOlinedriverinADSLandotherxDSLsystems.
TheADLD8403isavailableina4mm*4mm,20-leadLFCSP.
18–6–2261014010987654321VOLTAGE(V)TIME(s)VOPAVONAVOPBVONBVCCPVEEP08848-002Figure2.
OutputsandPumpsTimeDomainResponse,TypicalADSL/ADSL2+ApplicationCircuit,VCC=12.
5V,POUT=20.
4dBm,CrestFactor=5.
45ADLD8403DataSheetRev.
D|Page2of10TABLEOFCONTENTSFeatures1Applications.
1InternalSchematic.
1GeneralDescription.
1RevisionHistory2Specifications.
3AbsoluteMaximumRatings.
4ThermalResistance.
4MaximumPowerDissipation4ESDCaution.
4PinConfigurationandFunctionDescriptions.
5TypicalPerformanceCharacteristics6TheoryofOperation.
7ApplicationsInformation.
8Supplies,Grounding,andLayout.
8PowerManagement8DynamicSupplies.
8TypicalADSL/ADSL2+Application8MultitonePowerRatio(MTPR)9LightningandACPowerFault9OutlineDimensions.
10OrderingGuide10REVISIONHISTORY3/2017—Rev.
CtoRev.
DChangedLFCSP_WQtoLFCSP.
ThroughoutChangetoTable34UpdatedOutlineDimensions.
10ChangestoOrderingGuide109/2014—RevisionC:InitialVersionDataSheetADLD8403Rev.
D|Page3of10SPECIFICATIONSVCC=12.
5V,RL=100,GDIFF=13(fixed),PD_A=0,PD_B=0,T=25°C,typicalDSLapplicationcircuit,unlessotherwisenoted.
Table1.
ParameterMinTypMaxUnitTestConditions/CommentsDYNAMICPERFORMANCE3dBSmallSignalBandwidth8MHzVOUT=0.
1Vp-p,differential3dBLargeSignalBandwidth8MHzVOUT=2Vp-p,differentialDifferentialGain12.
81313.
2V/VNOISE/DISTORTIONPERFORMANCEMultitonePowerRatio(MTPR)65dBc26kHzto2.
2MHz,ZLINE=100,differentialloadDifferentialOutputNoise120nV/√Hzf=10kHzINPUTCHARACTERISTICSReferredtoOutput(RTO)OffsetVoltage<100mVSingle-ended15200mVDifferentialInputResistance8kDifferentialInputCapacitance1pFDifferentialOUTPUTCHARACTERISTICSDifferentialOutputVoltageSwing43.
4VΔVOUT,RL=100POWERSUPPLYOperatingRange,SingleSupply11.
7512.
5VTotalQuiescentCurrentFullchipPD_A=0,PD_B=0,PD_PMP=035.
638mAPumpsareon,bothchannelsactivePD_A=0,PD_B=0,PD_PMP=122.
025mAPumpsareoff,bothchannelsactivePD_A=0,PD_B=1,PD_PMP=021.
023.
5mAPumpsareon,onechannelactivePD_A=0,PD_B=1,PD_PMP=110.
613mAPumpsareoff,onechannelactivePD_A=1,PD_B=12.
53.
5mAPumpsareoff,bothchannelsinactiveCommon-ModeVoltage20mVWithrespecttomidsupplyThresholdPD_A=0,PD_B=00.
8VPD_A=1,PD_B=12.
4VInputCurrentPD_A=0,PD_B=03560A0≡0.
8VPD_A=1,PD_B=1510A1≡2.
4VADLD8403DataSheetRev.
D|Page4of10ABSOLUTEMAXIMUMRATINGSTable2.
ParameterRatingSupplyVoltage,VCC13.
2VPowerDissipationSeeFigure3StorageTemperatureRange65°Cto+150°COperatingTemperatureRange40°Cto+85°CLeadTemperature(Soldering,10sec)300°CJunctionTemperature150°CStressesatorabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetotheproduct.
Thisisastressratingonly;functionaloperationoftheproductattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthisspecificationisnotimplied.
Operationbeyondthemaximumoperatingconditionsforextendedperiodsmayaffectproductreliability.
THERMALRESISTANCEθJAisspecifiedinstillairwiththeexposedpadsolderedtoa4-layerJEDECtestboard.
θJCisspecifiedattheexposedpad.
Table3.
ThermalResistancePackageTypeθJAθJCUnit20-LeadLFCSP(CP-20-8)36.
15.
7°C/WMAXIMUMPOWERDISSIPATIONThemaximumsafepowerdissipationfortheADLD8403islimitedbyitsjunctiontemperatureonthedie.
Themaximumsafejunctiontemperatureofplasticencapsulateddevices,asdeterminedbytheglasstransitiontemperatureoftheplastic,is150°C.
Exceedingthislimitmaytemporarilycauseashiftintheparametricperformanceduetoachangeinthestressesexertedonthediebythepackage.
Exceedingthislimitforanextendedperiodcanresultindevicefailure.
Figure3showsthemaximumpowerdissipationinthepackagevs.
theambienttemperatureforthe20-leadLFCSPonaJEDECstandard4-layerboard.
θJAvaluesareapproximations.
6012345–2585756555453525155–5–15MAXIMUMPOWERDISSIPATION(W)AMBIENTTEMPERATURE(°C)TJ=150°C08848-003Figure3.
MaximumPowerDissipationvs.
AmbientTemperaturefora4-LayerBoardThepowerdissipatedinthepackage(PD)iseasilycomputedbytakingthetotalpowerconsumedwhiledrivingasignalandsubtractingthepowerdissipatedintheload.
Thetotalpowerconsumedissimplytheproductofthevoltagebetweenthesupplypins(VCC,VEEP,andVCCP)timesthesupplycurrent(IS).
Usermsvoltagesandcurrents.
Airflowincreasesheatdissipation,effectivelyreducingθJA.
Inaddition,morecopperindirectcontactwiththepackageleadsfromPCBtraces,throughholes,ground,andpowerplanesreducesθJA.
ESDCAUTIONDataSheetADLD8403Rev.
D|Page5of10PINCONFIGURATIONANDFUNCTIONDESCRIPTIONS141312134VCCP15CAPPGNDVEEP11CAPNINPAPD_PMP2INNAINNB5INPB7PD_B6VCOM_B8VONB9VOPB10GND19PD_A20VCOM_A18VONA17VOPA16VCCADLD8403TOPVIEW(NottoScale)NOTES1.
CONNECTTHEEXPOSEDPADTOTHEGNDPLANEFORTHETHERMALPATH.
NOINTERNALELECTRICALCONNECTIONEXISTS.
08848-004Figure4.
PinConfigurationTable4.
PinFunctionDescriptionsPinNo.
MnemonicDescription1INPAPortAInputP2INNAPortAInputN3PD_PMPControlforPortAandPortBPumps4INNBPortBInputN5INPBPortBInputP6VCOM_BPortBVCOM7PD_BPortBShutdown8VONBPortBOutputN9VOPBPortBOutputP10GNDGround11CAPNPumpCapacitorNegative12VEEPDynamicNegativeSupply13GNDGround14VCCPDynamicPositiveSupply15CAPPPumpCapacitorPositive16VCCPositivePowerSupply17VOPAPortAOutputP18VONAPortAOutputN19PD_APortAShutdown20VCOM_APortAVCOMEPADExposedPad.
ConnecttheexposedpadtotheGNDplaneforthethermalpath.
Nointernalelectricalconnectionexists.
ADLD8403DataSheetRev.
D|Page6of10TYPICALPERFORMANCECHARACTERISTICS25–20–15–10–5051015200.
11k100101CLOSED-LOOPGAIN(dB)FREQUENCY(MHz)DMVOUT=0.
1Vp-pDMVOUT=2Vp-pCM08848-005Figure5.
Closed-LoopGainvs.
Frequency,RL=100Ω18–6–2261014010987654321VOLTAGE(V)TIME(s)VOPAVONAVOPBVONBVCCPVEEP08848-006Figure6.
OutputsandPumpsTimeDomainResponse,TypicalADSL/ADSL2+ApplicationCircuit,VCC=12.
5V,POUT=20.
4dBm,CrestFactor=5.
450–80–70–60–50–40–30–20–1000.
51.
01.
52.
02.
53.
0OUTPUTPOWER(dBm/Hz)FREQUENCY(MHz)08848-007Figure7.
MultitonePowerRatio(MTPR),TypicalADSL/ADSL2+ApplicationCircuit,VCC=12.
5V,POUT=20.
4dBm,CrestFactor=5.
4570060050040030020010006810121416182022POWERDISSIPATION(mW)OUTPUTPOWER(dBm)CLASSH(PUMPSON)CLASSAB(PUMPSOFF)08848-008Figure8.
PowerDissipationperChannelvs.
OutputPower;IncludesLinePower24–12–8–404812162004.
03.
53.
02.
52.
01.
51.
00.
5VOLTAGE(V)TIME(s)VOPxVONxVCCPVEEP08848-009Figure9.
OutputsandPumpsTimeDomainResponse,TypicalADSL/ADSL2+ApplicationCircuit,VCC=12.
5V,POUT=19.
8dBm,CrestFactor=6.
91k100110k1k10010VOLTAGENOISE(nV/Hz)FREQUENCY(kHz)08848-010Figure10.
DifferentialOutputVoltageNoisevs.
FrequencyDataSheetADLD8403Rev.
D|Page7of10THEORYOFOPERATIONAClassHDSLlinedriverachievespowersavingsbyusinginternallydeveloped,signaltracking,powersupplies.
ThesetrackingpowersuppliesarederivedfromasingleVCCpowersupplyof12.
5Vnominal.
Thepowersavingsoccurduetominimumheadroomprovidedbythetracking,orpumped,suppliestoensurenonsaturationoftheoutputbufferamplifier.
ForClassHdrivers,theaveragetotalpowerthattheamplifierconsumesislowerthanthatofconventionalClassABamplifierarchitecturesusingafixedsupply.
TheADLD8403isthesecondimplementationofapatentedamplifierarchitecturedevelopedbyAnalogDevices.
Thisnewarchitecture,knownasAdaptiveLinearPower(ALP),isoptimizedtoprocesssignalswithoccasionalpeaksthataremuchgreaterthanthermslevel,suchasthediscretemultitone(DMT)signalsusedinxDSLapplications.
Figure11showstheADLD8403blockdiagram.
IncludedaretwoClassABcurrentfeedback(CFB)amplifiers,alongwiththeALPunitandstandardbiasblock.
ThearchitecturecombinesClassABamplifierswiththeALPtoprovideasystemthatgeneratesinternalsupplies(VCCPandVEEP)thatmovelinearlywiththeinputsignal.
Thismovementisachievedbysamplingtheinputsignalviatheinputpins,INPAandINNA,andapplyingtheappropriategaintocreatethevariablesuppliesattheVCCPandVEEPpins.
TheADLD8403containstwocompletechannelsofADSL2+compliantdrivers.
Eachchannelhasapowermodesignal,orPDpin(PD_AandPD_B),thatenablestheoutputbuffer.
Additionally,inapplicationswherelessthan14.
5dBmoflinepowerisrequired,athirdPD_PMPsignalisusedtodisablethesignaltracking,powersupplies.
Thisfeaturereducespowerconsumptionbyapproximately125mWforthesereducedlinepowers.
BecausebothchannelssharethepumpedsuppliesintheADLD8403,thePD_PMPpinisusedonlywhenbothchannelsrequirelessthan14.
5dBmoflinepower.
TheADLD8403isintendedforuseindigitalsubscriberlineaccessmultiplexor(DSLAM)applications.
TheADLD8403asimpleprocessandallowsforeaseofupgradingexistingDSLAMsystems.
VCC4k4k+–+–VOPAINPAVCOM_AINNAVONAAV=13V/VCFBCFBBIASALPPD_APD_PMPVCCCAPPVCCPCAPNVEEPGND08848-017Figure11.
BlockDiagramADLD8403DataSheetRev.
D|Page8of10APPLICATIONSINFORMATIONSUPPLIES,GROUNDING,ANDLAYOUTTheADLD8403ispoweredfromasingle12.
5Vpowersupply.
Foroptimumperformance,useawell-regulatedlowripplepowersupply.
Aswithallhighspeedamplifiers,paycloseattentiontosupplydecoupling,grounding,andoverallboardlayout.
Providelowfrequencysupplydecouplingbyusinga10FtantalumcapacitorbetweenVCCandground.
Inaddition,decoupleVCCtogroundusingahighquality0.
1Fceramicchipcapacitorplacedascloseaspossibletothedriver.
Useaninternallowimpedancegroundplanetoprovideacommongroundpointforalldriveranddecouplingcapacitorgroundrequirements.
Wheneverpossible,useseparategroundplanesforanaloganddigitalcircuitry.
Donotdecouplethepumpedsupplypins,VCCPandVEEP,becausedoingsoadverselyaffectstheoperationoftheinternalchargepumps.
Keepinputandoutputtracesasshortaspossibleandasfarapartfromeachotheraspracticaltominimizecrosstalk.
Keepalldifferentialsignaltracesassymmetricalaspossible.
POWERMANAGEMENTAdigitallyprogrammablelogicpinswitcheseachportoftheADLD8403betweenactivebiasandshutdownstates.
ThePD_ApincontrolsPortA,andthePD_BpincontrolsPortB.
Thesepinscanbecontrolleddirectlywitheither3.
3Vor5VCMOSlogicusingtheGNDpinsasareference.
Ifleftunconnected,thePD_AandPD_Bpinsfloathigh,placingtheamplifierinthepower-downstate.
Additionally,forloweroutputpowerapplicationsinwhichthedifferentialDMTpeaksarebelow10V(assumingasupplyvoltageof12.
5V),thePD_PMPpincanbeusedtoturnofftheinternalchargepumpsforadditionalpowersavings.
Ifleftunconnected,thePD_PMPpinfloatshigh,placingthechargepumpintheinactivestate.
IntheeventthatPD_AandPD_Barebothheldhigh,thechargepumpisdisabled,regardlessofthelogiclevelonPD_PMP.
SeetheSpecificationssectionforthequiescentcurrentforeachoftheavailablebiasstates.
DYNAMICSUPPLIESTheADLD8403usesthestoredchargeofcapacitorstoprovidethesupplyboostnecessarytopassthepeaksofthexDSLsignal.
ThecapacitorsareplacedbetweenCAPPandVCCP,aswellasbetweenCAPNandVEEP,asshowninFigure11.
Thechargepumpcapacitorsmustbe0.
47Fwithaminimumdcvoltageratingof16V.
UsingadielectricX7Rcapacitorisrecommended.
Chargingtimeiscriticalforproperchipoperationbecause,dependingontheapplication,peakcurrentscanbelarge(upto250mA).
Thesystemisoptimizedforsignalswithoccasionalpeaksthataremuchgreaterthanthermslevel,suchastheDMTwaveformusedinxDSLapplications.
Itmaynotbeapplicableforasystemprocessingaperiodicsinusoidalwaveformwithanamplitudethatexceedsthedcsupply(VCC)intoaheavyload(<500Ω).
TYPICALADSL/ADSL2+APPLICATIONInatypicalADSL/ADSL2+application,adifferentiallinedrivertakesthesignalfromtheanalogfrontend(AFE)anddrivesitontothetwistedpairtelephoneline.
ReferringtothetypicalcircuitrepresentationinFigure12,thedifferentialinputappearsatVIN+andVINfromtheAFE,andthedifferentialoutputistransformer-coupledtothetelephonelineatthetipandring.
Thecommon-modeoperatingpoint,generallymidwaybetweenthesupplies,issetinternallyandisavailableatbothVCOM_AandVCOM_B.
VCCGND4k4k+–+–VCOM0.
1FVIN+VIN–1:NTIPRINGRmRm08848-018Figure12.
TypicalADSL/ADSL2+ApplicationCircuitDataSheetADLD8403Rev.
D|Page9of10MULTITONEPOWERRATIO(MTPR)TheDMTsignalusedinADSL/ADSL2+systemscarriesdataindiscretetonesorbins,whichappearinthefrequencydomaininevenlyspaced4.
3125kHzintervals.
Inapplicationsusingthistypeofwaveform,theMTPRiscommonlyusedtomeasureaclinearity.
Ingeneral,designersareconcernedwithtwotypesofMTPR:in-bandandout-of-band.
In-bandMTPRisthemeasureddifferencefromthepeakofonetonethatisloadedwithdatatothepeakofanadjacentemptytone.
Out-of-bandMTPRisthespuriousemissionsthatoccurinbandsjustbelowandabovethetransmitband.
ForADSL2+applications,theout-of-bandMTPRisthereceivebandbetween25.
875kHzand138kHzandtheregionabove2.
208MHz.
Figure13showstheout-of-bandMTPRfortheADLD8403.
08848-0190–80–70–60–50–40–30–20–1000.
51.
01.
52.
02.
53.
0OUTPUTPOWER(dBm/Hz)FREQUENCY(MHz)Figure13.
Out-of-BandMTPRLIGHTNINGANDACPOWERFAULTAsanADSL/ADSL2+linedriver,theADLD8403istransformercoupledtothetwistedpairtelephoneline.
Inthisenvironment,theADLD8403issubjecttolargelinetransientsresultingfromeventssuchaslightningstrikesordownedpowerlines.
AdditionalcircuitryisrequiredtoprotecttheADLD8403fromdamageduetotheseevents.
ADLD8403DataSheetRev.
D|Page10of10OUTLINEDIMENSIONS0.
50BSC0.
500.
400.
300.
300.
250.
18COMPLIANTTOJEDECSTANDARDSMO-220-WGGD-11.
4.
104.
00SQ3.
900.
800.
750.
700.
05MAX0.
02NOM0.
20REF0.
25MINCOPLANARITY0.
08PIN1INDICATOR2.
752.
60SQ2.
351206101115165BOTTOMVIEWTOPVIEWSIDEVIEWFORPROPERCONNECTIONOFTHEEXPOSEDPAD,REFERTOTHEPINCONFIGURATIONANDFUNCTIONDESCRIPTIONSSECTIONOFTHISDATASHEET.
02-21-2017-BEXPOSEDPADPKG-005089SEATINGPLANEPIN1INDICATORAREAOPTIONS(SEEDETAILA)DETAILA(JEDEC95)Figure14.
20-LeadLeadFrameChipScalePackage[LFCSP]4mm*4mmBodyand0.
75mmPackageHeight(CP-20-8)DimensionsshowninmillimetersORDERINGGUIDEModel1TemperatureRangePackageDescriptionPackageOptionADLD8403ACPZ-R240°Cto+85°C20-LeadLeadFrameChipScalePackage[LFCSP]CP-20-8ADLD8403ACPZ-R740°Cto+85°C20-LeadLeadFrameChipScalePackage[LFCSP]CP-20-8ADLD8403ACPZ-RL40°Cto+85°C20-LeadLeadFrameChipScalePackage[LFCSP]CP-20-81Z=RoHSCompliantPart.
2014–2017AnalogDevices,Inc.
Allrightsreserved.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
D08848-0-3/17(D)
DDocumentFeedbackInformationfurnishedbyAnalogDevicesisbelievedtobeaccurateandreliable.
However,noresponsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorotherrightsofthirdpartiesthatmayresultfromitsuse.
Specificationssubjecttochangewithoutnotice.
NolicenseisgrantedbyimplicationorotherwiseunderanypatentorpatentrightsofAnalogDevices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
OneTechnologyWay,P.
O.
Box9106,Norwood,MA02062-9106,U.
S.
A.
Tel:781.
329.
47002014–2017AnalogDevices,Inc.
Allrightsreserved.
TechnicalSupportwww.
analog.
comFEATURES2differentialDSLchannelscomprisingcurrentfeedback,highoutputcurrentamplifierswithintegratedfeedbackresistorsplusbiasingnetworkIdealforuseasADSL/ADSL2+dual-channelcentraloffice(CO)linedriversLowpowerconsumptionusingClassHtechnologySingle12.
5Vsupplyoperation20.
4dBmlinepower,1:1transformerLessthan600mWperchanneltotalpowerdissipationwhiledriving20.
4dBm(includes110mWlinepower)Lessthan275mWperchanneltotalpowerdissipationwhiledriving14.
5dBm(includinglinepower)Highoutputvoltageandcurrentdrive43.
4VdifferentialoutputvoltageswingLowdistortion65dBctypicalmultitonepowerratio(MTPR)at20.
4dBm,26kHzto2.
2MHzLowcostprotectioncomponentsenableITU-T-K20andGR-1089complianceAPPLICATIONSADSL/ADSL2+COlinedriversINTERNALSCHEMATICVEEPVCCPVCCAV=13V/VVOPAVONAINPAVCOM_AINNAVCC4k4k08848-001Figure1.
ChannelAInternalSchematicGENERALDESCRIPTIONTheADLD8403comprisestwodifferential,highoutputcurrent,lowpowerconsumptionoperationalamplifiers.
ItisparticularlywellsuitedfortheCOdriverinterfaceindigitalsubscriberlinesystems,suchasADSLandADSL2+.
Thedrivercandeliver20.
4dBmtoalinewhilecompensatingforlossesduetohybridinsertionandbackterminationresistors.
TheADLD8403usestheAnalogDevices,Inc.
,secondgenerationAdaptiveLinearPower(ClassH)architecturetoachieveunprecedentedpowerefficiencyusingasinglepowersupply.
Additionalfunctionalityallowstheshutdownofpumpsforenhancedpowersavingsforlinepowersoflessthan14.
5dBm.
Thisfunctionalityyieldsthesmallestprintedcircuitboard(PCB)footprintandlowesttotalcostofownership.
Thelowpowerconsumption,highoutputcurrent,highoutputvoltageswing,androbustthermalpackagingenabletheADLD8403tobetheCOlinedriverinADSLandotherxDSLsystems.
TheADLD8403isavailableina4mm*4mm,20-leadLFCSP.
18–6–2261014010987654321VOLTAGE(V)TIME(s)VOPAVONAVOPBVONBVCCPVEEP08848-002Figure2.
OutputsandPumpsTimeDomainResponse,TypicalADSL/ADSL2+ApplicationCircuit,VCC=12.
5V,POUT=20.
4dBm,CrestFactor=5.
45ADLD8403DataSheetRev.
D|Page2of10TABLEOFCONTENTSFeatures1Applications.
1InternalSchematic.
1GeneralDescription.
1RevisionHistory2Specifications.
3AbsoluteMaximumRatings.
4ThermalResistance.
4MaximumPowerDissipation4ESDCaution.
4PinConfigurationandFunctionDescriptions.
5TypicalPerformanceCharacteristics6TheoryofOperation.
7ApplicationsInformation.
8Supplies,Grounding,andLayout.
8PowerManagement8DynamicSupplies.
8TypicalADSL/ADSL2+Application8MultitonePowerRatio(MTPR)9LightningandACPowerFault9OutlineDimensions.
10OrderingGuide10REVISIONHISTORY3/2017—Rev.
CtoRev.
DChangedLFCSP_WQtoLFCSP.
ThroughoutChangetoTable34UpdatedOutlineDimensions.
10ChangestoOrderingGuide109/2014—RevisionC:InitialVersionDataSheetADLD8403Rev.
D|Page3of10SPECIFICATIONSVCC=12.
5V,RL=100,GDIFF=13(fixed),PD_A=0,PD_B=0,T=25°C,typicalDSLapplicationcircuit,unlessotherwisenoted.
Table1.
ParameterMinTypMaxUnitTestConditions/CommentsDYNAMICPERFORMANCE3dBSmallSignalBandwidth8MHzVOUT=0.
1Vp-p,differential3dBLargeSignalBandwidth8MHzVOUT=2Vp-p,differentialDifferentialGain12.
81313.
2V/VNOISE/DISTORTIONPERFORMANCEMultitonePowerRatio(MTPR)65dBc26kHzto2.
2MHz,ZLINE=100,differentialloadDifferentialOutputNoise120nV/√Hzf=10kHzINPUTCHARACTERISTICSReferredtoOutput(RTO)OffsetVoltage<100mVSingle-ended15200mVDifferentialInputResistance8kDifferentialInputCapacitance1pFDifferentialOUTPUTCHARACTERISTICSDifferentialOutputVoltageSwing43.
4VΔVOUT,RL=100POWERSUPPLYOperatingRange,SingleSupply11.
7512.
5VTotalQuiescentCurrentFullchipPD_A=0,PD_B=0,PD_PMP=035.
638mAPumpsareon,bothchannelsactivePD_A=0,PD_B=0,PD_PMP=122.
025mAPumpsareoff,bothchannelsactivePD_A=0,PD_B=1,PD_PMP=021.
023.
5mAPumpsareon,onechannelactivePD_A=0,PD_B=1,PD_PMP=110.
613mAPumpsareoff,onechannelactivePD_A=1,PD_B=12.
53.
5mAPumpsareoff,bothchannelsinactiveCommon-ModeVoltage20mVWithrespecttomidsupplyThresholdPD_A=0,PD_B=00.
8VPD_A=1,PD_B=12.
4VInputCurrentPD_A=0,PD_B=03560A0≡0.
8VPD_A=1,PD_B=1510A1≡2.
4VADLD8403DataSheetRev.
D|Page4of10ABSOLUTEMAXIMUMRATINGSTable2.
ParameterRatingSupplyVoltage,VCC13.
2VPowerDissipationSeeFigure3StorageTemperatureRange65°Cto+150°COperatingTemperatureRange40°Cto+85°CLeadTemperature(Soldering,10sec)300°CJunctionTemperature150°CStressesatorabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetotheproduct.
Thisisastressratingonly;functionaloperationoftheproductattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthisspecificationisnotimplied.
Operationbeyondthemaximumoperatingconditionsforextendedperiodsmayaffectproductreliability.
THERMALRESISTANCEθJAisspecifiedinstillairwiththeexposedpadsolderedtoa4-layerJEDECtestboard.
θJCisspecifiedattheexposedpad.
Table3.
ThermalResistancePackageTypeθJAθJCUnit20-LeadLFCSP(CP-20-8)36.
15.
7°C/WMAXIMUMPOWERDISSIPATIONThemaximumsafepowerdissipationfortheADLD8403islimitedbyitsjunctiontemperatureonthedie.
Themaximumsafejunctiontemperatureofplasticencapsulateddevices,asdeterminedbytheglasstransitiontemperatureoftheplastic,is150°C.
Exceedingthislimitmaytemporarilycauseashiftintheparametricperformanceduetoachangeinthestressesexertedonthediebythepackage.
Exceedingthislimitforanextendedperiodcanresultindevicefailure.
Figure3showsthemaximumpowerdissipationinthepackagevs.
theambienttemperatureforthe20-leadLFCSPonaJEDECstandard4-layerboard.
θJAvaluesareapproximations.
6012345–2585756555453525155–5–15MAXIMUMPOWERDISSIPATION(W)AMBIENTTEMPERATURE(°C)TJ=150°C08848-003Figure3.
MaximumPowerDissipationvs.
AmbientTemperaturefora4-LayerBoardThepowerdissipatedinthepackage(PD)iseasilycomputedbytakingthetotalpowerconsumedwhiledrivingasignalandsubtractingthepowerdissipatedintheload.
Thetotalpowerconsumedissimplytheproductofthevoltagebetweenthesupplypins(VCC,VEEP,andVCCP)timesthesupplycurrent(IS).
Usermsvoltagesandcurrents.
Airflowincreasesheatdissipation,effectivelyreducingθJA.
Inaddition,morecopperindirectcontactwiththepackageleadsfromPCBtraces,throughholes,ground,andpowerplanesreducesθJA.
ESDCAUTIONDataSheetADLD8403Rev.
D|Page5of10PINCONFIGURATIONANDFUNCTIONDESCRIPTIONS141312134VCCP15CAPPGNDVEEP11CAPNINPAPD_PMP2INNAINNB5INPB7PD_B6VCOM_B8VONB9VOPB10GND19PD_A20VCOM_A18VONA17VOPA16VCCADLD8403TOPVIEW(NottoScale)NOTES1.
CONNECTTHEEXPOSEDPADTOTHEGNDPLANEFORTHETHERMALPATH.
NOINTERNALELECTRICALCONNECTIONEXISTS.
08848-004Figure4.
PinConfigurationTable4.
PinFunctionDescriptionsPinNo.
MnemonicDescription1INPAPortAInputP2INNAPortAInputN3PD_PMPControlforPortAandPortBPumps4INNBPortBInputN5INPBPortBInputP6VCOM_BPortBVCOM7PD_BPortBShutdown8VONBPortBOutputN9VOPBPortBOutputP10GNDGround11CAPNPumpCapacitorNegative12VEEPDynamicNegativeSupply13GNDGround14VCCPDynamicPositiveSupply15CAPPPumpCapacitorPositive16VCCPositivePowerSupply17VOPAPortAOutputP18VONAPortAOutputN19PD_APortAShutdown20VCOM_APortAVCOMEPADExposedPad.
ConnecttheexposedpadtotheGNDplaneforthethermalpath.
Nointernalelectricalconnectionexists.
ADLD8403DataSheetRev.
D|Page6of10TYPICALPERFORMANCECHARACTERISTICS25–20–15–10–5051015200.
11k100101CLOSED-LOOPGAIN(dB)FREQUENCY(MHz)DMVOUT=0.
1Vp-pDMVOUT=2Vp-pCM08848-005Figure5.
Closed-LoopGainvs.
Frequency,RL=100Ω18–6–2261014010987654321VOLTAGE(V)TIME(s)VOPAVONAVOPBVONBVCCPVEEP08848-006Figure6.
OutputsandPumpsTimeDomainResponse,TypicalADSL/ADSL2+ApplicationCircuit,VCC=12.
5V,POUT=20.
4dBm,CrestFactor=5.
450–80–70–60–50–40–30–20–1000.
51.
01.
52.
02.
53.
0OUTPUTPOWER(dBm/Hz)FREQUENCY(MHz)08848-007Figure7.
MultitonePowerRatio(MTPR),TypicalADSL/ADSL2+ApplicationCircuit,VCC=12.
5V,POUT=20.
4dBm,CrestFactor=5.
4570060050040030020010006810121416182022POWERDISSIPATION(mW)OUTPUTPOWER(dBm)CLASSH(PUMPSON)CLASSAB(PUMPSOFF)08848-008Figure8.
PowerDissipationperChannelvs.
OutputPower;IncludesLinePower24–12–8–404812162004.
03.
53.
02.
52.
01.
51.
00.
5VOLTAGE(V)TIME(s)VOPxVONxVCCPVEEP08848-009Figure9.
OutputsandPumpsTimeDomainResponse,TypicalADSL/ADSL2+ApplicationCircuit,VCC=12.
5V,POUT=19.
8dBm,CrestFactor=6.
91k100110k1k10010VOLTAGENOISE(nV/Hz)FREQUENCY(kHz)08848-010Figure10.
DifferentialOutputVoltageNoisevs.
FrequencyDataSheetADLD8403Rev.
D|Page7of10THEORYOFOPERATIONAClassHDSLlinedriverachievespowersavingsbyusinginternallydeveloped,signaltracking,powersupplies.
ThesetrackingpowersuppliesarederivedfromasingleVCCpowersupplyof12.
5Vnominal.
Thepowersavingsoccurduetominimumheadroomprovidedbythetracking,orpumped,suppliestoensurenonsaturationoftheoutputbufferamplifier.
ForClassHdrivers,theaveragetotalpowerthattheamplifierconsumesislowerthanthatofconventionalClassABamplifierarchitecturesusingafixedsupply.
TheADLD8403isthesecondimplementationofapatentedamplifierarchitecturedevelopedbyAnalogDevices.
Thisnewarchitecture,knownasAdaptiveLinearPower(ALP),isoptimizedtoprocesssignalswithoccasionalpeaksthataremuchgreaterthanthermslevel,suchasthediscretemultitone(DMT)signalsusedinxDSLapplications.
Figure11showstheADLD8403blockdiagram.
IncludedaretwoClassABcurrentfeedback(CFB)amplifiers,alongwiththeALPunitandstandardbiasblock.
ThearchitecturecombinesClassABamplifierswiththeALPtoprovideasystemthatgeneratesinternalsupplies(VCCPandVEEP)thatmovelinearlywiththeinputsignal.
Thismovementisachievedbysamplingtheinputsignalviatheinputpins,INPAandINNA,andapplyingtheappropriategaintocreatethevariablesuppliesattheVCCPandVEEPpins.
TheADLD8403containstwocompletechannelsofADSL2+compliantdrivers.
Eachchannelhasapowermodesignal,orPDpin(PD_AandPD_B),thatenablestheoutputbuffer.
Additionally,inapplicationswherelessthan14.
5dBmoflinepowerisrequired,athirdPD_PMPsignalisusedtodisablethesignaltracking,powersupplies.
Thisfeaturereducespowerconsumptionbyapproximately125mWforthesereducedlinepowers.
BecausebothchannelssharethepumpedsuppliesintheADLD8403,thePD_PMPpinisusedonlywhenbothchannelsrequirelessthan14.
5dBmoflinepower.
TheADLD8403isintendedforuseindigitalsubscriberlineaccessmultiplexor(DSLAM)applications.
TheADLD8403asimpleprocessandallowsforeaseofupgradingexistingDSLAMsystems.
VCC4k4k+–+–VOPAINPAVCOM_AINNAVONAAV=13V/VCFBCFBBIASALPPD_APD_PMPVCCCAPPVCCPCAPNVEEPGND08848-017Figure11.
BlockDiagramADLD8403DataSheetRev.
D|Page8of10APPLICATIONSINFORMATIONSUPPLIES,GROUNDING,ANDLAYOUTTheADLD8403ispoweredfromasingle12.
5Vpowersupply.
Foroptimumperformance,useawell-regulatedlowripplepowersupply.
Aswithallhighspeedamplifiers,paycloseattentiontosupplydecoupling,grounding,andoverallboardlayout.
Providelowfrequencysupplydecouplingbyusinga10FtantalumcapacitorbetweenVCCandground.
Inaddition,decoupleVCCtogroundusingahighquality0.
1Fceramicchipcapacitorplacedascloseaspossibletothedriver.
Useaninternallowimpedancegroundplanetoprovideacommongroundpointforalldriveranddecouplingcapacitorgroundrequirements.
Wheneverpossible,useseparategroundplanesforanaloganddigitalcircuitry.
Donotdecouplethepumpedsupplypins,VCCPandVEEP,becausedoingsoadverselyaffectstheoperationoftheinternalchargepumps.
Keepinputandoutputtracesasshortaspossibleandasfarapartfromeachotheraspracticaltominimizecrosstalk.
Keepalldifferentialsignaltracesassymmetricalaspossible.
POWERMANAGEMENTAdigitallyprogrammablelogicpinswitcheseachportoftheADLD8403betweenactivebiasandshutdownstates.
ThePD_ApincontrolsPortA,andthePD_BpincontrolsPortB.
Thesepinscanbecontrolleddirectlywitheither3.
3Vor5VCMOSlogicusingtheGNDpinsasareference.
Ifleftunconnected,thePD_AandPD_Bpinsfloathigh,placingtheamplifierinthepower-downstate.
Additionally,forloweroutputpowerapplicationsinwhichthedifferentialDMTpeaksarebelow10V(assumingasupplyvoltageof12.
5V),thePD_PMPpincanbeusedtoturnofftheinternalchargepumpsforadditionalpowersavings.
Ifleftunconnected,thePD_PMPpinfloatshigh,placingthechargepumpintheinactivestate.
IntheeventthatPD_AandPD_Barebothheldhigh,thechargepumpisdisabled,regardlessofthelogiclevelonPD_PMP.
SeetheSpecificationssectionforthequiescentcurrentforeachoftheavailablebiasstates.
DYNAMICSUPPLIESTheADLD8403usesthestoredchargeofcapacitorstoprovidethesupplyboostnecessarytopassthepeaksofthexDSLsignal.
ThecapacitorsareplacedbetweenCAPPandVCCP,aswellasbetweenCAPNandVEEP,asshowninFigure11.
Thechargepumpcapacitorsmustbe0.
47Fwithaminimumdcvoltageratingof16V.
UsingadielectricX7Rcapacitorisrecommended.
Chargingtimeiscriticalforproperchipoperationbecause,dependingontheapplication,peakcurrentscanbelarge(upto250mA).
Thesystemisoptimizedforsignalswithoccasionalpeaksthataremuchgreaterthanthermslevel,suchastheDMTwaveformusedinxDSLapplications.
Itmaynotbeapplicableforasystemprocessingaperiodicsinusoidalwaveformwithanamplitudethatexceedsthedcsupply(VCC)intoaheavyload(<500Ω).
TYPICALADSL/ADSL2+APPLICATIONInatypicalADSL/ADSL2+application,adifferentiallinedrivertakesthesignalfromtheanalogfrontend(AFE)anddrivesitontothetwistedpairtelephoneline.
ReferringtothetypicalcircuitrepresentationinFigure12,thedifferentialinputappearsatVIN+andVINfromtheAFE,andthedifferentialoutputistransformer-coupledtothetelephonelineatthetipandring.
Thecommon-modeoperatingpoint,generallymidwaybetweenthesupplies,issetinternallyandisavailableatbothVCOM_AandVCOM_B.
VCCGND4k4k+–+–VCOM0.
1FVIN+VIN–1:NTIPRINGRmRm08848-018Figure12.
TypicalADSL/ADSL2+ApplicationCircuitDataSheetADLD8403Rev.
D|Page9of10MULTITONEPOWERRATIO(MTPR)TheDMTsignalusedinADSL/ADSL2+systemscarriesdataindiscretetonesorbins,whichappearinthefrequencydomaininevenlyspaced4.
3125kHzintervals.
Inapplicationsusingthistypeofwaveform,theMTPRiscommonlyusedtomeasureaclinearity.
Ingeneral,designersareconcernedwithtwotypesofMTPR:in-bandandout-of-band.
In-bandMTPRisthemeasureddifferencefromthepeakofonetonethatisloadedwithdatatothepeakofanadjacentemptytone.
Out-of-bandMTPRisthespuriousemissionsthatoccurinbandsjustbelowandabovethetransmitband.
ForADSL2+applications,theout-of-bandMTPRisthereceivebandbetween25.
875kHzand138kHzandtheregionabove2.
208MHz.
Figure13showstheout-of-bandMTPRfortheADLD8403.
08848-0190–80–70–60–50–40–30–20–1000.
51.
01.
52.
02.
53.
0OUTPUTPOWER(dBm/Hz)FREQUENCY(MHz)Figure13.
Out-of-BandMTPRLIGHTNINGANDACPOWERFAULTAsanADSL/ADSL2+linedriver,theADLD8403istransformercoupledtothetwistedpairtelephoneline.
Inthisenvironment,theADLD8403issubjecttolargelinetransientsresultingfromeventssuchaslightningstrikesordownedpowerlines.
AdditionalcircuitryisrequiredtoprotecttheADLD8403fromdamageduetotheseevents.
ADLD8403DataSheetRev.
D|Page10of10OUTLINEDIMENSIONS0.
50BSC0.
500.
400.
300.
300.
250.
18COMPLIANTTOJEDECSTANDARDSMO-220-WGGD-11.
4.
104.
00SQ3.
900.
800.
750.
700.
05MAX0.
02NOM0.
20REF0.
25MINCOPLANARITY0.
08PIN1INDICATOR2.
752.
60SQ2.
351206101115165BOTTOMVIEWTOPVIEWSIDEVIEWFORPROPERCONNECTIONOFTHEEXPOSEDPAD,REFERTOTHEPINCONFIGURATIONANDFUNCTIONDESCRIPTIONSSECTIONOFTHISDATASHEET.
02-21-2017-BEXPOSEDPADPKG-005089SEATINGPLANEPIN1INDICATORAREAOPTIONS(SEEDETAILA)DETAILA(JEDEC95)Figure14.
20-LeadLeadFrameChipScalePackage[LFCSP]4mm*4mmBodyand0.
75mmPackageHeight(CP-20-8)DimensionsshowninmillimetersORDERINGGUIDEModel1TemperatureRangePackageDescriptionPackageOptionADLD8403ACPZ-R240°Cto+85°C20-LeadLeadFrameChipScalePackage[LFCSP]CP-20-8ADLD8403ACPZ-R740°Cto+85°C20-LeadLeadFrameChipScalePackage[LFCSP]CP-20-8ADLD8403ACPZ-RL40°Cto+85°C20-LeadLeadFrameChipScalePackage[LFCSP]CP-20-81Z=RoHSCompliantPart.
2014–2017AnalogDevices,Inc.
Allrightsreserved.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
D08848-0-3/17(D)
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