typicallywww.bu622.com

LP3972www.
ti.
comSNVS468K–SEPTEMBER2006–REVISEDMAY2013PowerManagementUnitforAdvancedApplicationProcessorsCheckforSamples:LP39721FEATURESAPPLICATIONS2CompatibleWithAdvancedApplicationsPDAPhonesProcessorsRequiringDVM(DynamicVoltageSmartPhonesManagement)PersonalMediaPlayersThreeBuckRegulatorsforPoweringHigh-DigitalCamerasCurrentProcessorFunctionsorI/OsApplicationProcessorsSixLDOsforPoweringRTC,Peripherals,and–MarvellPXAI/Os–FreescaleBackupBatteryChargerWithAutomatic–SamsungSwitchforLithium-ManganeseCoinCellBatteriesandSuperCapacitorsDESCRIPTIONI2CCompatibleHigh-SpeedSerialInterfaceTheLP3972isamulti-functionprogrammablePowerSoftwareControlofRegulatorFunctionsandManagementUnitdesignedespeciallyforadvancedSettingsapplicationprocessors.
TheLP3972isoptimizedforPrecisionInternalReferencelow-powerhandheldapplicationsandprovidessixlow-dropoutlow-noiselinearregulators,threeDC/DCThermalOverloadProtectionmagneticbuckregulators,aback-upbatterycharger,CurrentOverloadProtectionandtwoGPIOs.
Ahigh-speedserialinterfaceisTiny40-Pin5x5mmWQFNPackageincludedtoprogramindividualregulatoroutputvoltagesaswellasonandoffcontrol.
KEYSPECIFICATIONSBuckRegulators–ProgrammableVOUTfrom0.
725to3.
3V–Upto95%efficiency–Upto1.
6Aoutputcurrent–±3%outputvoltageaccuracyLDOs–ProgrammableVOUTof1.
0V–3.
3V–±3%outputvoltageaccuracy–150/300/400mAoutputcurrents–LDO_RTC30mA–LDO1300mA–LDO2150mA–LDO3150mA–LDO4150mA–LDO5400mA–100mV(typ)dropout1Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
2Alltrademarksarethepropertyoftheirrespectiveowners.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
Copyright2006–2013,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.
Productionprocessingdoesnotnecessarilyincludetestingofallparameters.
LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
ti.
comApplicationCircuitsFigure1.
SimplifiedApplicationCircuit2SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013TheI2ClinesarepulledupviaaI/OsourceVINLDOs4,5caneitherbepoweredfrommainbatterysource,orbyabuckregulatororVIN.
Figure2.
ApplicationCircuitCopyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback3ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comConnectionDiagramNote:Circlemarkspin1position.
40-PinWQFN,PackageNumberRSB0040APINDESCRIPTIONSPinNo.
NameI/OType(1)Description1PWR_ONIDThisisanactiveHIpushbuttoninputwhichcanbeusedtosignalPWR_ONandPWR_OFFeventstotheCPUbycontrollingtheext_wakeup[pin4]andselectcontentsofregister8H'882nTEST_JIGIDThisisanactiveLOWinputsignalusedfordetectinganexternalHWevent.
Theresponseisseenintheext_wakeup[pin4]andselectcontentsofregister8H'883SPAREIDThisisaninputsignalusedfordetectingaexternalHWevent.
Theresponseisseenintheext_wakeup[pin4]andselectcontentsofregister8H'88.
Thepolarityonthispinisassignable4EXT_WAKEUPODThispingeneratesasingle10mspulseoutputtoCPUinresponsetoinputfrompins1,2,and3.
FlagsCPUtointerrogateregister8H'885FB1IABuck1inputfeedbackterminal6VINIPWRBatteryInput(InternalcircuitryandLDO1-3powerinput)7VOUTLDO1OPWRLDO1output8VOUTLDO2OPWRLDO2output9nRSTIIDActivelowResetpin.
SignalusedtoresettheIC(bydefaultispulledhighinternally).
Typicallyapushbuttonreset.
10GND1GGGround11VREFOABypassCap.
forthehighinternalimpedancereference.
12VOUTLDO3OPWRLDO3output13VOUTLDO4OPWRLDO4output14VINLDO4IPWRPowerinputtoLDO4,thiscanbeconnectedtoeitherfroma1.
8VsupplytomainBatterysupply.
15VINBUBATTIPWRBackUpBatteryinputsupply.
16VOUTLDO_RTCOPWRLDO_RTCoutputsupplytotheRTCoftheapplicationprocessor.
17nBATT_FLTODMainBatteryfaultoutput,indicatesthemainbatteryislow(discharged)orthedcsourcehasbeenremovedfromthesystem.
Thisgivestheprocessoranindicatorthatthepowerwillshutdown.
Duringthistimetheprocessorwilloperatefromthebackupcoincell.
18PGND2GGBuck2NMOSPowerGround19SW2OPWRBuck2switcheroutput(1)A:AnalogPinD:DigitalPinG:GroundPinP:PowerPinI:InputPinI/O:Input/OutputPinO:OutputPinNote:Inthisdocument,active-lowlogicitemsareprefixedwithalowercase"n".
4SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013PINDESCRIPTIONS(continued)PinNo.
NameI/OType(1)Description20VINBuck2IPWRBatteryinputpowertoBuck221SDAI/ODI2CData(Bidirectional)22SCLIDI2CClock23FB2IABuck2inputfeedbackterminal24nRSTOODResetoutputfromthePMICtotheprocessor25VOUTLDO5OPWRLDO5output26VINLDO5IPWRPowerinputtoLDO5,thiscanbeconnectedtoVINortoaseparate1.
8Vsupply.
27VDDAIPWRAnalogPowerforVREF,BIAS28FB3IABuck3Feedback29GPIO1/I/ODGeneralPurposeI/O/Ext.
backupbatterychargerenablepin.
ThispinenablesnCHG_ENthemainbattery/DCsourcepowertochargethebackupbattery.
Thispintoggledviatheapplicationprocessor.
BygroundingthispintheDCsourcecontinuouslychargesthebackupbattery30GPIO2I/ODGeneralPurposeI/O31VINBuck3IPWRBatteryinputpowertoBuck332SW3OPWRBuck3switcheroutput33PGND3GGBuck3NMOSPowerGround34BGND1,2,3GGBucks1,2and3analogGround35SYNCIDFrequencySynchronization:ConnectiontoanexternalclocksignalPLLtosynchronizethePMICinternaloscillator.
InputDigitalenablepinforthehighvoltagepowerdomainsupplies.
Outputfrom36SYS_ENIDtheMonahansprocessor.
DigitalenablepinfortheLowVoltagedomainsupplies.
Outputsignalfromthe37PWR_ENIDMonahansprocessor38PGND1GGBuck1NMOSPowerGround39SW1OPWRBuck1Switcheroutput40VINBuck1IPWRBatteryinputpowertoBuck1Thesedeviceshavelimitedbuilt-inESDprotection.
TheleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
AbsoluteMaximumRatings(1)(2)AllInputs0.
3Vto+6.
5VGNDtoGNDSLUG±0.
3VJunctionTemperature(TJ-MAX)150°CStorageTemperature65°Cto+150°CPowerDissipation(TA=70°C)(3)3.
2WJunction-to-AmbientThermalResistanceθJA(3)25°C/WMaximumLeadTemp(Soldering)260°CHumanBodyModel2kVESDRating(4)MachineModel200V(1)AbsoluteMaximumRatingsarelimitsbeyondwhichdamagetothedevicemayoccur.
OperatingRatingsareconditionsunderwhichoperationofthedeviceisspecified.
OperatingRatingsdonotimplyensuredperformancelimits.
Forspecifiedperformancelimitsandassociatedtestconditions,seetheElectricalCharacteristicstables.
(2)IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityandspecifications.
(3)Inapplicationswherehighpowerdissipationand/orpoorpackagethermalresistanceispresent,themaximumambienttemperaturemayhavetobederated.
Maximumambienttemperature(TA-MAX)isdependentonthemaximumoperatingjunctiontemperature(TJ-MAX-OP=125°C),themaximumpowerdissipationofthedeviceintheapplication(PD-MAX),andthejunction-toambientthermalresistanceofthepart/packageintheapplication(θJA),asgivenbythefollowingequation:TA-MAX=TJ-MAX-OP–(θJAxPD-MAX).
(4)TheHumanbodymodelisa100pFcapacitordischargedthrougha1.
5kresistorintoeachpin.
(MIL-STD-8833015.
7)Themachinemodelisa200pFcapacitordischargeddirectlyintoeachpin.
(EAIJ).
Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback5ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comOperatingRatingsVIN2.
7Vto5.
5VVINLDO4,51.
74toVINJunctionTemperature(TJ)40°Cto+125°COperatingTemperature(TA)40°Cto+85°CMaximumPowerDissipation(TA=70°C)(1)(2)2.
2W(1)Inapplicationswherehighpowerdissipationand/orpoorpackagethermalresistanceispresent,themaximumambienttemperaturemayhavetobederated.
Maximumambienttemperature(TA-MAX)isdependentonthemaximumoperatingjunctiontemperature(TJ-MAX-OP=125°C),themaximumpowerdissipationofthedeviceintheapplication(PD-MAX),andthejunction-toambientthermalresistanceofthepart/packageintheapplication(θJA),asgivenbythefollowingequation:TA-MAX=TJ-MAX-OP–(θJAxPD-MAX).
(2)Junction-to-ambientthermalresistance(θJA)istakenfromathermalmodelingresult,performedundertheconditionsandguidelinessetforthintheJEDECstandardJESD51–7.
Thetestboardisa4-layerFR-4boardmeasuring102mmx76mmx1.
6mmwitha2x1arrayofthermalvias.
Thegroundplaneontheboardis50mmx50mm.
Thicknessofcopperlayersare36m/1.
8m/18m/36m(1.
5oz/1oz/1oz/1.
5oz).
Ambienttemperatureinsimulationis22°C,stillair.
Powerdissipationis1W.
Junction-to-ambientthermalresistanceishighlyapplicationandboard-layoutdependent.
Inapplicationswherehighmaximumpowerdissipationexists,specialcaremustbepaidtothermaldissipationissuesinboarddesign.
ThevalueofθJAofthisproductcanvarysignificantly,dependingonPCBmaterial,layout,andenvironmentalconditions.
Inapplicationswherehighmaximumpowerdissipationexists(highVIN,highIOUT),specialcaremustbepaidtothermaldissipationissues.
Formoreinformationonthesetopics,seeApplicationNoteAN-1187LeadlessLeadframePackage(LLP)(SNOA401)andthePowerEfficiencyandPowerDissipationsectionsofthisdatasheet.
GeneralElectricalCharacteristicsTypicalvaluesandlimitsappearinginnormaltypeapplyforTJ=25°C.
Limitsappearinginboldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,40°Cto+125°C(1)(2)(3)SymbolParameterTestConditionsMinTypMaxUnitVIN,VDDA,VINBuck1,2and3BatteryVoltage2.
73.
65.
5VVINLDO4,VINLDO5PowerSupplyforLDO4and51.
743.
6VINVTSDThermalShutdown(4)Temperature160°CHysteresis20(1)AllvoltagesarewithrespecttothepotentialattheGNDpin.
(2)Alllimitsspecifiedatroomtemperature(standardtypeface)andattemperatureextremes(boldtypeface).
Allroomtemperaturelimitsareproductiontested,ensuredthroughstatisticalanalysisorensuredbydesign.
AlllimitsattemperatureextremesareensuredviacorrelationusingstandardStatisticalQualityControl(SQC)methods.
AlllimitsareusedtocalculateAverageOutgoingQualityLevel(AOQL).
(3)NoinputsupplyshouldbehigherthenVDDA(4)Thiselectricalspecificationisensuredbydesign.
SupplySpecifications(1)(2)VOUT(Volts)IMAX:MaximumCurrentSupplyRangeResolutionCurrent(mA)(V)(mV)LDO_RTC2.
8VN/A30mAdcsource10mAbackupsourceLDO1(VCC_MVT)1.
7to2.
025300LDO21.
8to3.
3100150LDO31.
8to3.
3100150LDO41.
0to3.
350-600150LDO5(VCC_SRAM)0.
850to1.
525400BUCK1(VCC_APPS)0.
725to1.
5251600BUCK20.
8to3.
350-6001600BUCK30.
8to3.
350-6001600(1)AllvoltagesarewithrespecttothepotentialattheGNDpin.
(2)TheHumanbodymodelisa100pFcapacitordischargedthrougha1.
5kresistorintoeachpin.
(MIL-STD-8833015.
7)Themachinemodelisa200pFcapacitordischargeddirectlyintoeachpin.
(EAIJ).
6SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013DefaultVoltageOption(1)(2)(3)VersionLP3972SQ-A514LP3972SQ-A413EnableVersionAVersionALDO_RTC—2.
8—2.
8LDO1SYS_EN1.
8SYS_EN1.
8LDO2SYS_EN1.
8DSYS_EN1.
8DLDO3SYS_EN3DSYS_EN3DLDO4SYS_EN3DSYS_EN2.
8DLDO5PWR_EN1.
4PWR_EN1.
4BUCK1PWR_EN1.
4PWR_EN1.
4BUCK2SYS_EN3.
3SYS_EN3BUCK3SYS_EN1.
8SYS_EN1.
8VersionLP3972SQ-E514LP3972SQ-I514EnableVersionEVersionILDO_RTC—2.
8—2.
8LDO1SYS_EN1.
8SYS_EN1.
8LDO2SYS_EN1.
8ESYS_EN1.
8ELDO3SYS_EN3DSYS_EN3ELDO4SYS_EN3DSYS_EN3ELDO5PWR_EN1.
4PWR_EN1.
4BUCK1PWR_EN1.
4PWR_EN1.
4BUCK2SYS_EN3.
3SYS_EN3.
3BUCK3SYS_EN1.
8SYS_EN1.
8VersionLP3972SQ-I414LP3972SQ-0514EnableVersionIVersion0LDO_RTC—2.
8Trackingenabled3.
3w/trackingLDO1SYS_EN1.
8SYS_EN1.
8LDO2SYS_EN1.
8ESYS_EN1.
8ELDO3SYS_EN3ESYS_EN3.
3ELDO4SYS_EN3ESYS_EN3ELDO5PWR_EN1.
4PWR_EN1.
4BUCK1PWR_EN1.
4PWR_EN1.
4BUCK2SYS_EN3.
0SYS_EN3.
3BUCK3SYS_EN1.
8SYS_EN1.
8VersionLP3972SQ-5810EnableVersion5LDO_RTC2.
8LDO1SYS_EN1.
8LDO2SYS_EN1.
8ELDO3SYS_EN2.
5ELDO4PWR_EN1.
3ELDO5PWR_EN1.
1BUCK1PWR_EN1.
35BUCK2SYS_EN1.
2BUCK3SYS_EN1.
8(1)AllvoltagesarewithrespecttothepotentialattheGNDpin.
(2)TheHumanbodymodelisa100pFcapacitordischargedthrougha1.
5kresistorintoeachpin.
(MIL-STD-8833015.
7)Themachinemodelisa200pFcapacitordischargeddirectlyintoeachpin.
(EAIJ).
(3)E=RegulatorisENABLEDduringstartup.
D=RegulatorisDISABLEDduringstartup.
Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback7ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comLDORTCUnlessotherwisenoted,VIN=3.
6V,CIN=1.
0F,COUT=0.
47F,COUT(VRTC)=1.
0Fceramic.
TypicalvaluesandlimitsappearinginnormaltypeapplyforTJ=25°C.
Limitsappearinginboldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,40°Cto+125°C(1)(2)(3)(4)SymbolParameterTestConditionsMinTypMaxUnitVOUTAccuracyOutputVoltageAccuracyVINConnected,LoadCurrent=1mA2.
6322.
82.
968VΔVOUTLineRegulationVIN=(VOUTnom+1.
0V)to5.
5V(5)0.
15%/VLoadCurrent=1mALoadRegulationFromMainBattery0.
05LoadCurrent=1mAto30mA%/mAFromBackupBattery,VIN=3.
0V0.
5LoadCurrent=1mAto10mAISCShortCircuitCurrentLimitFromMainBattery100VIN=VOUT+0.
3Vto5.
5VmAFromBackupBattery30VIN-VOUTDropoutVoltageLoadCurrent=10mA375mVIQ_MaxMaximumQuiescentCurrentIOUT=0mA30ATP1RTCLDOInputSwitchedfromVINFalling2.
9VMainBatterytoBackupBatteryTP2RTCLDOInputSwitchedfromVINRising3.
0VBackupBatterytoMainBatteryCOOutputCapacitorCapacitanceforStability0.
71.
0FESR5500m(1)AllvoltagesarewithrespecttothepotentialattheGNDpin.
(2)Alllimitsspecifiedatroomtemperature(standardtypeface)andattemperatureextremes(boldtypeface).
Allroomtemperaturelimitsareproductiontested,ensuredthroughstatisticalanalysisorensuredbydesign.
AlllimitsattemperatureextremesareensuredviacorrelationusingstandardStatisticalQualityControl(SQC)methods.
AlllimitsareusedtocalculateAverageOutgoingQualityLevel(AOQL).
(3)Dropoutvoltageistheinput-to-outputvoltagedifferenceatwhichtheoutputvoltageis100mVbelowitsnominalvalue.
(4)LDO_RTCvoltagecantrackLDO3voltage.
LP3972hasatrackingfunction(nIO_TRACK).
Whenenabled,LDO_RTCvoltagewilltrackLDO3voltagewithin200mVdownto2.
8VwhenLDO3isenabled(5)VINminimumforlineregulationvaluesis2.
7VforLDOs1–3and1.
8VforLDOs4and5.
Conditiondoesnotapplytoinputvoltagesbelowtheminimuminputoperatingvoltage.
8SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013LDOs1to5Unlessotherwisenoted,VIN=3.
6V,CIN=1.
0F,COUT=0.
47F,COUT(VRTC)=1.
0Fceramic.
TypicalvaluesandlimitsappearinginnormaltypeapplyforTJ=25°C.
Limitsappearinginboldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,40°Cto+125°C(1)(2)(3)(4)(5)(6)(7)SymbolParameterTestConditionsMinTypMaxUnitVOUTAccuracyOutputVoltageAccuracyLoadCurrent=1mA33%(DefaultVOUT)ΔVOUTLineRegulationVIN=3.
1Vto5.
0V(5),0.
15%/VLoadCurrent=1mALoadRegulationVIN=3.
6V,0.
011%/mALoadCurrent=1mAtoIMAXISCShortCircuitCurrentLimitLDO1–4,VOUT=0V400mALDO5,VOUT=0V500VIN-VOUTDropoutVoltageLoadCurrent=50mA(3)150mVPSRRPowerSupplyRippleRejectionf=10kHz,LoadCurrent=IMAX45dBIQQuiescentCurrent"On"IOUT=0mA40QuiescentCurrent"On"IOUT=IMAX60AQuiescentCurrent"Off"ENisde-asserted0.
03TONTurnOnTimeStartupfromShut-down300secCOUTOutputCapacitorCapacitanceforStability0.
330.
470°C≤TJ≤125°CF40°C≤TJ≤125°C0.
681.
0ESR5500m(1)AllvoltagesarewithrespecttothepotentialattheGNDpin.
(2)Alllimitsspecifiedatroomtemperature(standardtypeface)andattemperatureextremes(boldtypeface).
Allroomtemperaturelimitsareproductiontested,ensuredthroughstatisticalanalysisorensuredbydesign.
AlllimitsattemperatureextremesareensuredviacorrelationusingstandardStatisticalQualityControl(SQC)methods.
AlllimitsareusedtocalculateAverageOutgoingQualityLevel(AOQL).
(3)Dropoutvoltageistheinput-to-outputvoltagedifferenceatwhichtheoutputvoltageis100mVbelowitsnominalvalue.
(4)LDO_RTCvoltagecantrackLDO3voltage.
LP3972hasatrackingfunction(nIO_TRACK).
Whenenabled,LDO_RTCvoltagewilltrackLDO3voltagewithin200mVdownto2.
8VwhenLDO3isenabled(5)VINminimumforlineregulationvaluesis2.
7VforLDOs1–3and1.
8VforLDOs4and5.
Conditiondoesnotapplytoinputvoltagesbelowtheminimuminputoperatingvoltage.
(6)Anincreaseintheloadcurrentresultsinaslightdecreaseintheoutputvoltageandviceversa.
(7)Dropoutvoltageistheinput-to-outputvoltagedifferenceatwhichtheoutputvoltageis100mVbelowitsnominalvalue.
Thisspecificationdoesnotapplyforinputvoltagesbelow2.
7VforLDOs1–3and1.
8VforLDOs4and5.
Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback9ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comLDODropoutVoltagevs.
LoadCurrentCollectDataForAllLDOsDropoutVoltagevs.
ChangeinOutputVoltageLoadCurrentvs.
LoadCurrentFigure3.
Figure4.
LDO1LineRegulationLDO1LoadTransientVOUT=1.
8voltsVIN3to4voltsLoad=100mAVIN=4.
1voltsVOUT=1.
8voltsno-load-100mAFigure5.
Figure6.
EnableStart-uptime(LDO1)LDO1Channel2LDO4Channel1Sys_enablefrom0voltsLoad=100mAFigure7.
10SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013BuckConvertersSW1,SW2,SW3Unlessotherwisenoted,VIN=3.
6V,CIN=10F,COUT=10F,LOUT=2.
2Hceramic.
TypicalvaluesandlimitsappearinginnormaltypeapplyforTJ=25°C.
Limitsappearinginboldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,40°Cto+125°C(1)(2)(3)(4)SymbolParameterTestConditionsMinTypMaxUnitVOUTOutputVoltageAccuracyDefaultVOUT3+3%EffEfficiencyLoadCurrent=500mA95%ISHDNShutdownSupplyCurrentENisde-asserted0.
1ASyncModeClockFrequencySynchronizedfrom13MHzSystemClock10.
41315.
6MHzfOSCInternalOscillatorFrequency2.
0MHzIPEAKPeakSwitchingCurrentLimit2.
12.
4AIQQuiescentCurrent"On"NoLoadPFMMode21ANoLoadPWMMode200RDSON(P)Pin-PinResistancePFET240mRDSON(N)Pin-PinResistanceNFET200mTONTurnOnTimeStartupfromShut-down500secCINInputCapacitorCapacitanceforStability8FCOOutputCapacitorCapacitanceforStability8F(1)AllvoltagesarewithrespecttothepotentialattheGNDpin.
(2)Alllimitsspecifiedatroomtemperature(standardtypeface)andattemperatureextremes(boldtypeface).
Allroomtemperaturelimitsareproductiontested,ensuredthroughstatisticalanalysisorensuredbydesign.
AlllimitsattemperatureextremesareensuredviacorrelationusingstandardStatisticalQualityControl(SQC)methods.
AlllimitsareusedtocalculateAverageOutgoingQualityLevel(AOQL).
(3)Theinputvoltagerangerecommendedforidealapplicationsperformanceforthespecifiedoutputvoltagesisgivenbelow:VIN=2.
7Vto5.
5Vfor0.
80V3.
1V),theswitchwillautomaticallyconnecttheLDO_RTCpowertothemainbattery.
AsthemainbatteryisdischargedaseparatecircuitcallednBATT_FLTwillwarnthesystem.
Thenifnoactionistakentorestorethechargeonthemainbattery,anddischargingiscontinuedthebatteryswitchwilldisconnecttheinputoftheLDO_RTCfromthemainbatteryandconnecttothebackupbattery.
ThemainbatteryvoltageatwhichtheLDO_RTCisswitchedoverfrommaintobackupbatteryis2.
8Vtypically.
Thereisahystericvoltageinthisswitchoperation,thustheLDO_RTCwillnotbereconnectedtomainbatteryuntilmainbatteryvoltageisgreaterthan3.
1Vtypically.
Thesystemdesignermaywishtodisablethebatteryswitchwhenonlyamainbatteryisused.
Thisisaccomplishedbysettingthe"nobackupbatterybit"inthecontrolregister8h'0Bbit7NBUB.
Withthisbitsetto"1",theabovedescribedswitchingwillnotoccur,thatistheLDO_RTCwillremainconnectedtothemainbatteryevenasitisdischargedbelowthe2.
9Vthreshold.
TheBackupbatteryinputshouldalsobeconnectedtomainbattery.
Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback13ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comLogicInputsandOutputsDCOperatingConditions(1)LogicInputs(SYS_EN,PWR_EN,SYNC,nRSTI,PWR_ON,nTEST_JIG,SPAREandGPI's)SymbolParameterTestConditionsMinMaxUnitVILLowLevelInputVoltage0.
5VVIHHighLevelInputVoltageVRTC0.
5VVILEAKInputLeakageCurrent1+1A(1)AllvoltagesarewithrespecttothepotentialattheGNDpin.
LogicOutputs(nRSTO,EXT_WAKEUPandGPO's)SymbolParameterTestConditionsMinMaxUnitVOLOutputLowLevelLoad=+0.
2mA=IOLMax0.
5VVOHOutputHighLevelLoad=0.
1mA=IOLMaxVRTC0.
5VVILEAKOutputLeakageCurrentVON=VIN+5ALogicOutput(nBATT_FLT)SymbolParameterTestConditionsMinTypMaxUnitnBATT_FLTThresholdVoltageProgrammableviaSerialInterface2.
42.
83.
4VDefault=2.
8VVOLOutputLowLevelLoad=+0.
4mA=IOLMax0.
5VVOHOutputHighLevelLoad=0.
2mA=IOHMaxVRTC0.
5VVILEAKInputLeakageCurrent+5AI2CCompatibleSerialInterfaceElectricalSpecifications(SDAandSCL)Unlessotherwisenoted,VIN=3.
6V.
TypicalvaluesandlimitsappearinginnormaltypeapplyforTJ=25°C.
Limitsappearinginboldfacetypeapplyovertheentirejunctiontemperaturerangeforoperation,40°Cto+125°C(1)(2)(3)SymbolParameterTestConditionsMinTypMaxUnitVILLowLevelInputVoltageSee(4)0.
50.
3VRTCVVIHHighLevelInputVoltageSee(4)0.
7VRTCVRTCVOLLowLevelOutputVoltageSee(4)00.
2VTRCIOLLowLevelOutputCurrentVOL=0.
4V(4)3.
0mAFCLKClockFrequencySee(4)400kHztBFBus-FreeTimeBetweenStartandStopSee(4)1.
3stHOLDHoldTimeRepeatedStartConditionSee(4)0.
6stCLKLPCLKLowPeriodSee(4)1.
3stCLKHPCLKHighPeriodSee(4)0.
6stSUSetUpTimeRepeatedStartConditionSee(4)0.
6stDATAHLDDataHoldTimeSee(4)0stCLKSUDataSetUpTimeSee(4)100nsTSUSetUpTimeforStartConditionSee(4)0.
6sTTRANSMaximumpulsewidthofspikesthatmustbeSee(4)50nssuppressedbytheinputfilterofbothDATAandCLKsignals(1)AllvoltagesarewithrespecttothepotentialattheGNDpin.
(2)Alllimitsspecifiedatroomtemperature(standardtypeface)andattemperatureextremes(boldtypeface).
Allroomtemperaturelimitsareproductiontested,ensuredthroughstatisticalanalysisorensuredbydesign.
AlllimitsattemperatureextremesareensuredviacorrelationusingstandardStatisticalQualityControl(SQC)methods.
AlllimitsareusedtocalculateAverageOutgoingQualityLevel(AOQL).
(3)TheI2Csignalsbehavelikeopen-drainoutputsandrequireanexternalpull-upresistoronthesystemmoduleinthe2kto20krange.
(4)Thiselectricalspecificationisensuredbydesign.
14SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013DetailedDescriptionBuckConverterOperationDEVICEINFORMATIONTheLP3972includesthreehighefficiencystepdownDC-DCswitchingbuckconverters.
Usingavoltagemodearchitecturewithsynchronousrectification,thebuckconvertershavetheabilitytodeliverupto1600mAdependingontheinputvoltage,outputvoltage,ambienttemperatureandtheinductorchosen.
Therearethreemodesofoperationdependingonthecurrentrequired-PWM,PFM,andshutdown.
ThedeviceoperatesinPWMmodeatloadcurrentsofapproximately100mAorhigher,havingvoltagetoleranceof±3%with95%efficiencyorbetter.
LighterloadcurrentscausethedevicetoautomaticallyswitchintoPFMforreducedcurrentconsumption.
Shutdownmodeturnsoffthedevice,offeringthelowestcurrentconsumption(IQ,SHUTDOWN=0.
01Atyp).
Additionalfeaturesincludesoft-start,undervoltageprotection,currentoverloadprotection,andthermalshutdownprotection.
Thepartusesaninternalreferencevoltageof0.
5V.
Itisrecommendedtokeepthepartinshutdownuntiltheinputvoltageis2.
7Vorhigher.
CIRCUITOPERATIONThebuckconverteroperatesasfollows.
Duringthefirstportionofeachswitchingcycle,thecontrolblockturnsontheinternalPFETswitch.
Thisallowscurrenttoflowfromtheinputthroughtheinductortotheoutputfiltercapacitorandload.
Theinductorlimitsthecurrenttoarampwithaslopeof(VIN–VOUT)/L,bystoringenergyinamagneticfield.
Duringthesecondportionofeachcycle,thecontrollerturnsthePFETswitchoff,blockingcurrentflowfromtheinput,andthenturnstheNFETsynchronousrectifieron.
TheinductordrawscurrentfromgroundthroughtheNFETtotheoutputfiltercapacitorandload,whichrampstheinductorcurrentdownwithaslopeof–VOUT/L.
Theoutputfilterstoreschargewhentheinductorcurrentishigh,andreleasesitwheninductorcurrentislow,smoothingthevoltageacrosstheload.
TheoutputvoltageisregulatedbymodulatingthePFETswitchontimetocontroltheaveragecurrentsenttotheload.
Theeffectisidenticaltosendingaduty-cyclemodulatedrectangularwaveformedbytheswitchandsynchronousrectifierattheSWpintoalow-passfilterformedbytheinductorandoutputfiltercapacitor.
TheoutputvoltageisequaltotheaveragevoltageattheSWpin.
PWMOPERATIONDuringPWMoperationtheconverteroperatesasavoltagemodecontrollerwithinputvoltagefeedforward.
Thisallowstheconvertertoachievegoodloadandlineregulation.
TheDCgainofthepowerstageisproportionaltotheinputvoltage.
Toeliminatethisdependence,feedforwardinverselyproportionaltotheinputvoltageisintroduced.
WhileinPWM(PulseWidthModulation)mode,theoutputvoltageisregulatedbyswitchingataconstantfrequencyandthenmodulatingtheenergypercycletocontrolpowertotheload.
AtthebeginningofeachclockcyclethePFETswitchisturnedonandtheinductorcurrentrampsupuntilthecomparatortripsandthecontrollogicturnsofftheswitch.
ThecurrentlimitcomparatorcanalsoturnofftheswitchincasethecurrentlimitofthePFETisexceeded.
ThentheNFETswitchisturnedonandtheinductorcurrentrampsdown.
ThenextcycleisinitiatedbytheclockturningofftheNFETandturningonthePFET.
Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback15ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comFigure15.
TypicalPWMOperationInternalSynchronousRectificationWhileinPWMmode,theconvertersusesaninternalNFETasasynchronousrectifiertoreducerectifierforwardvoltagedropandassociatedpowerloss.
Synchronousrectificationprovidesasignificantimprovementinefficiencywhenevertheoutputvoltageisrelativelylowcomparedtothevoltagedropacrossanordinaryrectifierdiode.
CurrentLimitingAcurrentlimitfeatureallowstheconverterstoprotectitselfandexternalcomponentsduringoverloadconditions.
PWMmodeimplementscurrentlimitingusinganinternalcomparatorthattripsat2.
0A(typ).
IftheoutputisshortedtogroundthedeviceentersatimedcurrentlimitmodewheretheNFETisturnedonforalongerdurationuntiltheinductorcurrentfallsbelowalowthreshold,ensuringinductorcurrenthasmoretimetodecay,therebypreventingrunaway.
PFMOPERATIONAtverylightloads,theconverterentersPFMmodeandoperateswithreducedswitchingfrequencyandsupplycurrenttomaintainhighefficiency.
ThepartwillautomaticallytransitionintoPFMmodewheneitheroftwoconditionsoccursforadurationof32ormoreclockcycles:1.
Theinductorcurrentbecomesdiscontinuous.
2.
ThepeakPMOSswitchcurrentdropsbelowtheIMODElevel,(TypicallyIMODE90%ofselectedvalue6:3——Reserved2RS_OKVCC_SRAMSupplyOutputVoltageStatus0-VCC_SRAM(LDO5)outputvoltage90%ofselectedvalue1——Reserved0RA_OKVCC_APPSSupplyoutputVoltageStatus0-VCC_APPS(Buck1)outputvoltage90%ofselectedvalueCopyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback23ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comOUTPUTVOLTAGEENABLEREGISTER2This8bitoutputregisterenablesanddisablestheoutputvoltagesontheLDOs2,3,4supplies.
OutputVoltageEnableRegister2(OVER2)8h'12Bit7654(1)3(1)2(1)10DesignationReservedLDO4_ENLDO3_ENLDO2_ENReservedResetValue00000000(1)One-timefactoryprogrammableEPROMregistersfordefaultvaluesOutputVoltageEnableRegister2(OVER2)8h'12DefinitionsBitAccessNameDescription7——Reserved6——Reserved5——Reserved4R/WLDO4_ENLDO4OutputVoltageEnable0=LDO4SupplyOutputDisabled,Default1=LDO4SupplyOutputEnabled3R/WLDO3_ENLDO3OutputVoltageEnable0=LDO3SupplyOutputDisabled,Default1=LDO3SupplyOutputEnabled2R/WLDO2_ENLDO2OutputVoltageEnable0=LDO2SupplyOutputDisabled,Default1=LDO2SupplyOutputEnabled1——Reserved0——ReservedOUTPUTVOLTAGESTATUSREGISTER2OutputVoltageStatusRegister2(OVSR2)8h'13Bit76543210DesignationLDO_OKN/AN/ALDO4_OKLDO3_OKLDO2_OKN/AN/AResetValue00000000OutputVoltageStatusRegister2(OVSR2)8h'13DefinitionsBitAccessNameDescription7RLDO_OKLDOs2-4SupplyOutputVoltageStatus0-(LDOs2-4)outputvoltage90%ofselectedvalue6——Reserved5——Reserved4RLDO4_OKLDO4OutputVoltageStatus0-(VCC_LDO4)outputvoltage90%ofselectedvalue3RLDO3_OKLDO3OutputVoltageStatus0-(VCC_LDO3)outputvoltage90%ofselectedvalue2RLDO2_OKLDO2OutputVoltageStatus0-(VCC_LDO2)outputvoltage90%ofselectedvalue1——Reserved0——Reserved24SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013DVMVOLTAGECHANGECONTROLREGISTER1DVMVoltageChangeControlRegister1(VCC1)8h'20Bit76543210DesignationMVSMGOSVSSGOReservedAVSAGOResetValue00000000DVMVoltageChangeControlRegister1(VCC1)8h'20DefinitionsBitAccessNameDescription7R/WMVSVCC_MVT(LDO1)VoltageSelect0-ChangeVCC_MVTOutputVoltagetoMDVT11-ChangeVCC_MVTOutputVoltagetoMDVT26R/WMGOStartVCC_MVT(LDO1)VoltageChange0-HoldVCC_MVTOutputVoltageatcurrentLevel1-RampVCC_MVTOutputVoltageasselectedbyMVS5R/WSVSVCC_SRAM(LDO5)VoltageSelect0-ChangeVCC_SRAMOutputVoltagetoSDTV11-ChangeVCC_SRAMOutputVoltagetoSDTV24R/WSGOStartVCC_SRAM(LDO5)VoltageChange0-HoldVCC_SRAMOutputVoltageatcurrentLevel1-ChangeVCC_SRAMOutputVoltageasselectedbySVS3:2——Reserved1R/WAVSVCC_APPS(Buck1)VoltageSelect0-RampVCC_APPSOutputVoltagetoADVT11-RampVCC_APPSOutputVoltagetoADVT20R/WAGOStartVCC_APPS(Buck1)VoltageChange0-HoldVCC_APPSOutputVoltageatcurrentLevel1-RampVCC_APPSOutputVoltageasselectedbyAVSBUCK1(VCC_APPS)VOLTAGE1Buck1(VCC_APPS)TargetVoltage1Register(ADTV1)8h'23Bit7654(1)3(1)2(1)1(1)0(1)DesignationReservedBuck1OutputVoltage(B1OV1)ResetValue00001011(1)One-timefactoryprogrammableBuck1(VCC_APPS)TargetVoltage1Register(ADTV1)8h'23DefinitionsBitAccessNameDescription7:5——Reserved4:0R/WB1OV1DataCodeOutputVoltageDataCodeOutputVoltage5h'00.
7255h'101.
1255h'10.
7505h'111.
1505h'20.
7755h'121.
1755h'30.
8005h'131.
2005h'40.
8255h'141.
2255h'50.
8505h'151.
2505h'60.
8755h'161.
2755h'70.
9005h'171.
3005h'80.
9255h'181.
3255h'90.
9505h'191.
3505h'A0.
9755h'1A1.
3755h'B1.
0005h'1B1.
4005h'C1.
0255h'1C1.
4255h'D1.
0505h'1D1.
4505h'E1.
0755h'1E1.
4755h'F1.
1005h'1F1.
500Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback25ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comBUCK1(VCC_APPS)TARGETVOLTAGE2REGISTERBuck1(VCC_APPS)TargetVoltage2Register(ADTV2)8h'24Bit76543210DesignationReservedBuck1OutputVoltage(B1OV2)ResetValue00001011Buck1(VCC_APPS)TargetVoltage2Register(ADTV2)8h'24DefinitionsBitAccessNameDescription7:5——Reserved4:0R/WB1OV2DataCodeOutputVoltageDataCodeOutputVoltage5h'00.
7255h'101.
1255h'10.
7505h'111.
1505h'20.
7755h'121.
1755h'30.
8005h'131.
2005h'40.
8255h'141.
2255h'50.
8505h'151.
2505h'60.
8755h'161.
2755h'70.
9005h'171.
3005h'80.
9255h'181.
3255h'90.
9505h'191.
3505h'A0.
9755h'1A1.
3755h'B1.
0005h'1B1.
4005h'C1.
0255h'1C1.
4255h'D1.
0505h'1D1.
4505h'E1.
0755h'1E1.
4755h'F1.
1005h'1F1.
500BUCK1(VCC_APPS)VOLTAGERAMPCONTROLREGISTERBuck1(VCC_APPS)VoltageRampControlRegister(AVRC)8h'25Bit76543210DesignationReservedRampRate(B1RR)ResetValue00001010Buck1(VCC_APPS)VoltageRampControlRegister(AVRC)8h'25DefinitionsBitAccessNameDescription7:5——ReservedDVMRampSpeedDataCodeRampRate(mV/uS)5h'0Instant5h'115h'225h'335h'444:0R/WB1RR5h'555h'665h'775h'885h'995h'A104h'B-4h'1FReserved26SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013VCC_COMMTARGETVOLTAGE1DUMMYREGISTER(CDTV1)VCC_COMMTargetVoltage1DummyRegister(CDTV1)8h'26WriteOnly(1)Bit76543210DesignationReservedOutputVoltageResetValue00000000(1)CDTV1mustbewritablebyanI2Ccontroller.
ThisisadummyregisterVCC_COMMTARGETVOLTAGE2DUMMYREGISTER(CDTV2)VCC_COMMTargetVoltage2DummyRegister(CDTV2)8h'27WriteOnly(1)Bit76543210DesignationReservedOutputVoltageResetValue00000000(1)CDTV2mustbewritablebyanI2Ccontroller.
Thisisadummyregisterandcannotberead.
ThisisavariablevoltagesupplytotheinternalSRAMoftheApplicationprocessor.
LDO5(VCC_SRAM)TARGETVOLTAGE1REGISTERLDO5(VCC_SRAM)TargetVoltage1Register(SDTV1)8H'29Bit7654(1)3(1)2(1)1*(1)0(1)DesignationReservedLDO5OutputVoltage(L5OV)ResetValue00001011(1)One-timefactoryprogrammableEPROMregistersfordefaultvaluesLDO5(VCC_SRAM)TargetVoltage1Register(SDTV1)8h'29DefinitionsBitAccessNameDescription7:5——Reserved4:0R/WB1OVDataCodeOutputVoltageDataCodeOutputVoltage5h'0—5h'101.
1255h'1—5h'111.
1505h'2—5h'121.
1755h'3—5h'131.
2005h'4—5h'141.
2255h'50.
8505h'151.
2505h'60.
8755h'161.
2755h'70.
9005h'171.
3005h'80.
9255h'181.
3255h'90.
9505h'191.
3505h'A0.
9755h'1A1.
3755h'B1.
0005h'1B1.
4005h'C1.
0255h'1C1.
4255h'D1.
0505h'1D1.
4505h'E1.
0755h'1E1.
4755h'F1.
1005h'1F1.
500Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback27ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comLDO5(VCC_SRAM)TARGETVOLTAGE2REGISTERLDO5(VCC_SRAM)TargetVoltage2Register(SDTV2)8h'2ABit76543210DesignationReservedLDO5OutputVoltage(L5OV)ResetValue00001011LDO5(VCC_SRAM)TargetVoltage2Register(SDTV2)8h'2ADefinitionsBitAccessNameDescription7:5——Reserved4:0R/WB1OVDataCodeOutputVoltageDataCodeOutputVoltage5h'0—5h'101.
1255h'1—5h'111.
1505h'2—5h'121.
1755h'3—5h'131.
2005h'4—5h'141.
2255h'50.
8505h'151.
2505h'60.
8755h'161.
2755h'70.
9005h'171.
3005h'80.
9255h'181.
3255h'90.
9505h'191.
3505h'A0.
9755h'1A1.
3755h'B1.
0005h'1B1.
4005h'C1.
0255h'1C1.
4255h'D1.
0505h'1D1.
4505h'E1.
0755h'1E1.
4755h'F1.
1005h'1F1.
500VCC_MVTislowtoleranceregulatedpowersupplyfortheapplicationprocessorringoscillatorandlogicforcommunicatingtotheLP3972.
VCC_MVTisenabledwhenSYS_ENisassertedanddisabledwhenSYS_ENisdeasserted.
LDO1(VCC_MVT)TARGETVOLTAGE1REGISTER(MDTV1)LDO1(VCC_MVT)TargetVoltage1Register(MDTV1)8h'32Bit7654(1)3(1)2(1)1(1)0(1)DesignationReservedOutputVoltage(OV)ResetValue00000100(1)One-timefactoryprogrammableEPROMregistersfordefaultvaluesLDO1(VCC_MVT)TargetVoltage1Register(MDTV1)8h'32DefinitionsBitAccessNameDescription7:5——Reserved4:0R/WL1OVDataCodeOutputVoltageNotes:5h'01.
7005h'11.
7255h'21.
7505h'31.
7755h'41.
8005h'51.
8255h'61.
8505h'71.
8755h'81.
9005h'91.
9255h'A1.
9505h'B1.
9755h'C2.
0005h'D-5h'FReserved28SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013LDO1(VCC_MVT)TARGETVOLTAGE2REGISTERLDO1(VCC_MVT)TargetVoltage2Register(MDTV2)8h'33Bit76543210DesignationReservedOutputVoltage(OV)ResetValue00001011LDO1(VCC_MVT)TargetVoltage2Register(MDTV2)8h'33DefinitionsBitAccessNameDescription7:5——Reserved4:0R/WL1OVDataCodeOutputVoltageNotes:5h'01.
7005h'11.
7255h'21.
7505h'31.
7755h'41.
8005h'51.
8255h'61.
8505h'71.
8755h'81.
9005h'91.
9255h'A1.
9505h'B1.
9755h'C2.
0005h'D-5h'FReservedLDO2VOLTAGECONTROLREGISTER(L12VCR)LDO2VoltageControlRegister(L12VCR)8h'39Bit7(1)6(1)5(1)4(1)3210DesignationLDO2OutputVoltage(L2OV)ReservedResetValue00000000(1)One-timefactoryprogrammableEPROMregistersfordefaultvaluesLDO2VoltageControlRegister(L12VCR)8h'39DefinitionsBitAccessNameDescription7:4R/WL2OVDataCodeOutputVoltage4h'01.
8(Default)4h'11.
94h'22.
04h'32.
14h'42.
24h'52.
34h'62.
44h'72.
54h'82.
64h'92.
74h'A2.
84h'B2.
94h'C3.
04h'D3.
14h'E3.
24h'F3.
33:0——ReservedCopyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback29ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comLDO4–LDO3VOLTAGECONTROLREGISTER(L34VCR)LDO4–LDO3VoltageControlRegister(L34VCR)8h'3ABit7(1)6(1)5(1)4(1)3(1)2(1)1(1)0(1)DesignationLDO4OutputVoltage(L4OV)LDO3OutputVoltage(L3OV)ResetValue00000000(1)One-timefactoryprogrammableEPROMregistersfordefaultvaluesLDO4–LDO3VoltageControlRegister(L34VCR)8h'3ADefinitionsBitAccessNameDescription7:4R/WL4OVDataCodeOutputVoltage4h'01.
004h'11.
054h'21.
104h'31.
154h'41.
204h'51.
254h'61.
304h'71.
354h'81.
404h'91.
504h'A1.
804h'B1.
904h'C2.
504h'D2.
804h'E3.
00(Default)4h'F3.
303:0R/WL3OVDataCodeOutputVoltage4h'01.
84h'11.
94h'22.
04h'32.
14h'42.
24h'52.
34h'62.
44h'72.
54h'82.
64h'92.
74h'A2.
84h'B2.
94h'C3.
0(Default)4h'D3.
14h'E3.
24h'F3.
330SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013TIDEFINEDCONTROLANDSTATUSREGISTERSSYSTEMCONTROLREGISTER1(SCR1)SystemControlRegister1(SCR1)8h'80Bit7(1)6(1)5(1)43210DesignationBPSENSENDLFPWM3FPWM2FPWM1BK_SLOMODBK_SSENResetValue01000000(1)One-timefactoryprogrammableEPROMregistersfordefaultvaluesSystemControlRegister1(SCR1)8h'80DefinitionsBitAccessNameDescription7R/WBPSENBypassSystemenablesafetyLock.
PreventsactivationofPWR_ENwhenSYS_ENislow.
0=PWR_EN"AND"withSYS_ENsignal,Default1=PWR_ENindependentofSYS_ENDelaytimeforHighVoltagePowerDomainsLDO2,LDO3,LDO4,Buck2,andBuck3afteractivationofSYS_EN.
VCC_LDO1hasnodelay.
DataCodeDelay(ms)6:5R/WSENDL2h'00.
02h'10.
52h'21.
0(Default)2h'31.
44R/WFPWM3Buck3PWM/PFMModeselect0-AutoSwitchbetweenPFMandPWMoperation1-PWMModeOnlywillnotswitchtoPFM3R/WFPWM2Buck2PWM/PFMModeselect0-AutoSwitchbetweenPFMandPWMoperation1-PWMModeOnlywillnotswitchtoPFM2R/WFPWM1Buck1PWM/PFMModeselect0-AutoSwitchbetweenPFMandPWMoperation1-PWMModeOnlywillnotswitchtoPFM1RBK_SLOMODBuckSpreadSpectrumModulationBucks1-30=10kHztriangularwavespreadspectrummodulation1=2kHztriangularwavespreadspectrummodulation0RBK_SSENSpreadspectrumfunctionBucks1-30=SSOutputDisabled1=SSOutputEnabledSYSTEMCONTROLREGISTER2(SCR2)SystemControlRegister2(SCR2)8h'81Bit765(1)43210DesignationBBCSSHBUBPTRWUP3GPIO2GPIO110110010(1)OnetimefactoryprogrammableEPROMregistersfordefaultvaluesSystemControlRegister2(SCR2)8h'81DefinitionsBitAccessNameDescription7R/WBBCSSetsGPIO1ascontrolinputforBackUpbatterycharger0-BackUpbatteryChargerGPIODisabled1-BackUpbatteryChargerGPIOPinEnabledShutdownBackupbatterytopreventbatterydrainduringshipping6R/WSHBU0=BackupBatteryEnabled1=BackupbatteryDisabledCopyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback31ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comBitAccessNameDescription5R/WBPTRBypassLDO_RTCOutputVoltagetoLDO3OutputVoltageTracking0-LDO_RTC3Trackingenabled1-LDO_RTC3Trackingdisabled,Default4R/WWUP3SpareWakeupcontrolinput0-ActiveHigh1-ActiveLow3:2R/WGPIO2ConfiguredirectionandoutputsenseofGPIO2PinDataCodeGPIO22h'00Hi-Z2h'01OutputLow2h'02Input2h'03Outputhigh1:0R/WGPIO1ConfiguredirectionandoutputsenseofGPIO1PinDataCodeGPIO12h'00Hi-Z2h'01OutputLow2h'02Input2h'03OutputhighOUTPUTENABLE3REGISTER(OEN3)8H'82Bit7654(1)32(1)10(1)DesignationReservedB3ENENFLAGB2ENReservedL1ENResetValue00010101(1)OnetimefactoryprogrammableEPROMregistersfordefaultvaluesOUTPUTENABLE3REGISTER(OEN3)8H'82DEFINITIONSBitAccessNameDescription7:5——Reserved4R/WB3ENVCC_Buck3SupplyOutputEnabled0=VCC_Buck3SupplyOutputDisabled1=VCC_Buck3SupplyOutputEnabled,Default3R/WENFLAGEnableforTemperatureFlags(BCT)0=TemperatureFlagDisabled1=TemperatureFlagEnabled2R/WB2ENVCC_Buck2SupplyOutputEnabled0=VCC_Buck2SupplyOutputDisabled1=VCC_Buck2SupplyOutputEnabled,Default1——Reserved0R/WL1ENLDO1(MVT)OutputVoltageEnable0=LDO1SupplyOutputDisabled1=LDO1SupplyOutputEnabled,DefaultSTATUSREGISTER3(OSR3)8H'83Bit76543210DesignationBT_OKB3_OKB2_OKLDO1_OKReservedBCT2BCT1BCT0ResetValue00000000STATUSREGISTER3(OSR3)DEFINITIONS8H'83BitAccessNameDescription7RBT_OKBucks2-3SupplyOutputVoltageStatus0-(Bucks1-3)outputvoltage90%Defaultvalue32SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013BitAccessNameDescription6RB3_OKBuck3SupplyOutputVoltageStatus0-(Buck3)outputvoltage90%Defaultvalue5RB2_OKBuck2SupplyOutputVoltageStatus0-(Buck2)outputvoltage90%Defaultvalue4RLDO1_OKLDO1OutputVoltageStatus0-(VCC_LDO1)outputvoltage90%ofselectedvalue3——Reserved2:0RBCTBinarycodedthermalmanagementflagstatusregisterTemperatureDataCodeAscending°C000400016001080011100100120101140110160111ReservedLOGICOUTPUTENABLEREGISTER(LOER)8H'84Bit76(1)5(1)4(1)3(1)2(1)1(1)0(1)DesignationReservedB3ENCB2ENCB1ENCL5ECL4ECL3ECL2ECResetValue01100111(1)OnetimefactoryprogrammableEPROMregistersfordefaultvaluesLOGICOUTPUTENABLEREGISTER(LOER)DEFINITIONS8H'84BitAccessNameDescription7——Reserved6R/WB3ENCConnectsBuck3enabletoSYS_ENorPWR_ENLogicControlpin0-Buck3enableconnectedtoPWR_EN1-Buck3enableconnectedtoSYS_EN,Default5R/WB2ENCConnectsBuck2enabletoSYS_ENorPWR_ENLogicControlpin0-Buck2enableconnectedtoPWR_EN1-Buck2enableconnectedtoSYS_EN,Default4R/WB1ENCConnectsBuck1enabletoSYS_ENorPWR_ENLogicControlpin0-Buck1enableconnectedtoPWR_EN,Default1-Buck1enableconnectedtoSYS_EN3R/WL5ECConnectsLDO5enabletoSYS_ENorPWR_ENLogicControlpin0-LDO5enableconnectedtoPWR_EN,Default1-LDO5enableconnectedtoSYS_EN2R/WL4ECConnectsLDO4enabletoSYS_ENorPWR_ENLogicControlpin0-LDO4enableconnectedtoPWR_EN1-LDO4enableconnectedtoSYS_EN,Default1R/WL3ECConnectsLDO3enabletoSYS_ENorPWR_ENLogicControlpin0-LDO3enableconnectedtoPWR_EN1-LDO3enableconnectedtoSYS_EN,Default0R/WL2ECConnectsLDO2enabletoSYS_ENorPWR_ENLogicControlpin0-LDO2enableconnectedtoPWR_EN1-LDO2enableconnectedtoSYS_EN,DefaultCopyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback33ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comVCC_BUCK2TARGETVOLTAGEREGISTER(B2TV)8H'85Bit7654(1)3(1)2(1)1(1)0(1)DesignationReservedBuck2OutputVoltage(B2OV)ResetValue00011001(1)OnetimefactoryprogrammableEPROMregistersfordefaultvaluesVCC_BUCK2TARGETVOLTAGEREGISTER(B2TV)8H'85DEFINITIONSBitAccessNameDescription7:5—Reserved4:0R/WB2OVOutputVoltageDataCode(V)DataCode(V)5h'010.
805h'0D1.
405h'020.
855h'0E1.
455h'030.
905h'0F1.
505h'040.
955h'101.
555h'051.
005h'111.
605h'061.
055h'121.
655h'071.
105h'131.
705h'081.
155h'141.
805h'091.
205h'151.
905h'0A1.
255h'162.
505h'0B1.
305h'172.
805h'0C1.
355h'183.
005h'193.
30BUCK3TARGETVOLTAGEREGISTER(B3TV)8H'86Bit7654(1)3(1)2(1)1(1)0(1)DesignationReservedBuck3OutputVoltage(B3OV)ResetValue00010100(1)OnetimefactoryprogrammableEPROMregistersfordefaultvaluesBUCK3TARGETVOLTAGEREGISTER(B3TV)8H'86DEFINITIONSBitAccessNameDescription7:5—Reserved4:0R/WB3OVOutputVoltageDataCode(V)DataCode(V)5h'010.
805h'0D1.
405h'020.
855h'0E1.
455h'030.
905h'0F1.
505h'040.
955h'111.
605h'051.
005h'121.
655h'061.
055h'131.
705h'071.
105h'141.
80Default5h'081.
155h'151.
905h'091.
205h'162.
505h'0A1.
255h'172.
805h'0B1.
305h'183.
005h'0C1.
355h'193.
30VCC_BUCK3:2VOLTAGERAMPCONTROLREGISTER(B32RC)VCC_Buck3:2VoltageRampControlRegister(B32RC)8h'87Bit76543210DesignationRampRate(B3RR)RampRate(B2RR)34SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013Bit76543210ResetValue10101010Buck3:2VoltageRampControlRegister(B3RC)8h'87DefinitionsBitAccessNameDescription7:4R/WB3RRDataCodeRampRatemV/S4h'0Instant4h'114h'224h'334h'444h'554h'664h'774h'884h'994h'A103:0R/WB2RRDataCodeRampRatemV/S4h'0Instant4h'114h'224h'334h'444h'554h'664h'774h'884h'994h'A10INTERRUPTSTATUSREGISTERISRAThisregisterspecifiesthestatusbitsfortheinterruptsgeneratedbythePMIC.
ThermalwarningoftheIC,GPIO1,GPIO2,PWR_ONpin,TEST_JIGfactoryprogrammableonsignal,andtheSPAREpin.
InterruptStatusRegisterISRA8h'88Bit76543210DesignationReservedT125GPI2GPI1WUP3WUP2WUPTWUPSResetValue00000000InterruptStatusRegisterISRA8h'88DefinitionsBitAccessNameDescription7——Reserved6RT125StatusbitforthermalwarningPMICT>125C0=PMICTemp.
125°C5RGPI2StatusbitfortheinputreadinfromGPIO2whensetasInput0=GPI2LogicLow1=GPI2LogicHigh4RGPI1StatusbitfortheinputreadinfromGPIO1whensetasInput0=GPI1LogicLow1=GPI1LogicHigh3RWUP3PWR_ONPinlongpulseWakeUpStatus0=Nowakeupevent1=Longpulsewakeupevent2RWUP2PWR_ONPinShortpulseWakeUpStatus0=Nowakeupevent1=ShortpulsewakeupeventCopyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback35ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comBitAccessNameDescription1RWUPTTEST_JIGPinWakeUpStatus0=Nowakeupevent1=Wakeupevent0RWUPSSPAREPinWakeUpStatus0=Nowakeupevent1=WakeupeventBACKUPBATTERYCHARGERCONTROLREGISTER(BCCR)Thisregisterspecifiesthestatusofthemainbatterysupply.
NBUBbitBackupBatteryChargerControlRegister(BCCR)8h'89Bit7(1)65(1)4(1)3(1)210DesignationNBUBCNBFLnBFLTBUCENIBUCResetValue00010001(1)OnetimefactoryprogrammableEPROMregistersfordefaultvaluesBackupBatteryChargerControlRegister(BCCR)8h'89DefinitionsBitAccessNameDescription7R/WNBUBNoback-upbatterydefaultsetting.
Logicwillnotallowswitchovertoback-upbattery.
0=BackupBatteryEnabled,Default1=BackupBatteryDisabled6R/WCNBFLControlfornBATT_FLToutputsignal0=nBATT_FLTEnabled1=nBATT_FLTDisablednBATT_FLTmonitorsthebatteryvoltageandcanbesettotheAssertvoltageslistedbelow.
DataCodeAssertedDe-Asserted3h'012.
62.
85:3R/WBFLT3h'022.
83.
0(Default)3h'033.
03.
23h'043.
23.
43h'053.
43.
62R/WBUCENEnablesbackupbatterycharger0=BackupBatteryChargerDisabled1=BackupBatteryChargerEnabledChargercurrentsettingforback-upbatteryDataCodeBUChargerI(A)2h'002601:0R/WIBUC2h'01190(Default)2h'023252h'03390MARVELLPXAINTERNAL1REVISIONREGISTER(II1RR)8H'8EBit76543210DesignationII1RRResetValue00000000MARVELLPXAINTERNAL1REVISIONREGISTER(II1RR)8H'8EDEFINITIONSBitAccessNameDescription7:0RII1RRIntelinternalusageregisterforrevisioninformation.
36SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013MARVELLPXAINTERNAL2REVISIONREGISTER(II2RR)8H'8FBit76543210DesignationII2RRResetValue00000000MARVELLPXAINTERNAL2REVISIONREGISTER(II2RR)8H'8FDEFINITIONSBitAccessNameDescription7:0RII2RRIntelinternalusageregisterforrevisioninformation.
REGISTERPROGRAMMINGEXAMPLESExample1)StartofDaySequencePMICRegisterPMICRegisterRegisterDataDescriptionAddressName8h'23ADTVI00011011SetstheSODVCC_APPSvoltage8h'29SDTV100011011SetstheSODVCC_SRAMvoltage8h'10OVER100000111EnablesVCC_SRAMandVCC_APPStotheirprogrammedvalues.
SODlMulti-byterandomregistertransferisoutlinedbelow:Figure26.
DeviceAddress,RegisterAAddress,Ach,RegisterAData,AchRegisterMAddress,Ach,RegisterMData,AchRegisterXAddress,Ach,RegisterXData,AchRegisterZAddress,Ach,RegisterZData,Ach,StopCopyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback37ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comExample2)VoltagechangeSequencePMICRegisterPMICRegisterRegisterDataDescriptionAddressName8h'24ADTV200010111SetstheVCC_APPStargetvoltage2to1.
3V8h'2ASDTV200001111SetstheVCC_SRAMtargetvoltage2to1.
1V8h'20VCC100110011EnableVCC_SRAMandVCC_APPStochangetotheirprogrammedtargetvalues.
I2CDATAEXCHANGEBETWEENMASTERANDSLAVEDEVICEFigure27.
LP3972ControlsDIGITALINTERFACECONTROLSIGNALSSignalDefinitionActiveStateSignalDirectionSYS_ENHighVoltagePowerEnableHighInputPWR_ENLowVoltagePowerEnableHighInputSCLSerialBusClockLineClockInputSDASerialBusDataLineBidirectionalnRSTIForcesanunconditionalLowInputhardwareresetnRSTOForcesanunconditionalLowOutputhardwareresetnBATT_FLTMainBatteryremovedorLowOutputdischargedindicatorPWR_ONWakeupInputtoCPUHighInputnTEST_JIGWakeupInputtoCPULowInputSPAREWakeupInputtoCPUHigh/LowInputEXT_WAKEUPWake-UpOutputforapplicationHighOutputprocessorGPIO1/nCHG_ENGeneralPurposeI/O/External—Bidirectional/InputBack-upBatteryChargerenableGPIO2GeneralPurposeI/O—Bidirectional38SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013POWERDOMAINENABLESPMUOutputHWEnableSWEnableLDO_RTC——LDO1(VCC_MVT)SYS_ENLDO1_ENLDO2SYS_ENLDO2_ENLDO3SYS_ENLDO3_ENLDO4SYS_ENLDO4_ENLDO5(VCC_SRAM)PWR_ENS_ENBuck1(VCC_APPS)PWR_ENA_ENBUCK2SYS_ENB2_ENBUCK3SYS_ENB3_ENPOWERDOMAINSSEQUENCING(DELAY)BydefaultSYS_ENmustbeontohavePWR_ENenablebutthisfeaturecanbeswitchedoffbyregisterbitBP_SYS.
BydefaultSYS_ENenablesLDO1alwaysfirstandafteratypicalof1msdelayothers.
AlsowhenSYS_ENissetofftheLDO1willgoofflast.
ThisfunctioncanbeswitchedoffordelaycanbechangedbyDELAYbitsviaserialinterfaceasseenontablebelow.
8h'80Bit5:4DELAYbits'00''01''10''11'Delay,ms00.
51.
01.
5LDO_RTCTRACKING(nIO_TRACK)LP3972hasatrackingfunction(nIO_TRACK).
Whenenabled,LDO_RTCvoltagewilltrackLDO3voltagewithin200mVdownto2.
8VwhenLDO3isenabled.
Thisfunctioncanbeswitchedon/offbynIO_TRACKregisterbitBPTR.
POWERSUPPLYENABLESYS_ENandPWR_ENcanbechangedbyprogrammableregisterbits.
WAKE-UPFUNCTIONALITY(PWR_ON,nTEST_JIG,SPAREANDEXT_WAKEUP)Threeinputpinscanbeusedtoassertwakeupoutputfor10msforapplicationprocessornotificationtowakeup.
SPAREInputcanbeprogrammedthroughI2Ccompatibleinterfacetobeactiveloworhigh(SPAREbit,Defaultisactivelow'1').
AreasonforwakeupeventcanbereadthroughI2Ccompatibleinterfacealso.
Additionallywakeupinputshave30msde-bouncefiltering.
FurthermorePWR_ONhavedistinguishingbetweenshortandlong(1s)pulses(pushbuttoninput).
LP3972alsohasaninternalThermalShutdownearlywarningthatgeneratesawakeuptothesystemalso.
Thisisgeneratedusuallyat125°C.
Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback39ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comFigure28.
WAKEUPregisterbitsReasonforWAKEUPWUP0SPAREWUP1TEST_JIGWUP2PWR_ONshortpulseWUP3PWR_ONlongpulseTSD_EWTSDEarlyWarningINTERNALTHERMALSHUTDOWNPROCEDUREThermalshutdownisbuildtogenerateearlywarning(typ.
125°C)whichtriggerstheEXT_WAKEUPfortheprocessoracknowledge.
Whenathermalshutdowntriggers(typ.
160°C)thePMUwillresetthesystemuntilthedevicecoolsdown.
BATTERYSWITCHANDBACKUPBATTERYCHARGERWhenBack-Upbatteryisconnectedbutthemainbatteryhasbeenremovedoritssupplyvoltagetoolow,LP3972usesBack-UpBatteryforgeneratingLDO_RTCvoltage.
WhenMainBatteryisavailablethebatteryFETswitchesovertothemainbatteryforLDO_RTCvoltage.
WhenMainbatteryvoltageistooloworremovednBATT_FLTisasserted.
Ifnobackupbatteryexists,thebatteryswitchtobackupcanbeswitchedoffbynBU_BAT_ENbit.
UsercansetthebatteryfaultdeterminationvoltageandbatterychargercurrentviaI2Ccompatibleinterface.
Enablingofbackupbatterychargercanbedoneviaserialinterface(nBAT_CHG_EN)orexternalchargerenablepin(nCHG_EN).
Pin29issetasexternalchargerenableinputbydefault.
GENERALPURPOSEI/OFUNCTIONALITY(GPIO1ANDGPIO2)LP3972has2generalpurposeI/Osforsystemcontrol.
I2Ccompatibleinterfacewillbeusedforsettinganyofthepinstoinput,outputorhi-Zmode.
Inputsvaluecanbereadviaserialinterface(GPIO1,2bits).
Thepin29functionalityneedstobesettoGPIObyserialinterfaceregisterbitnEXTCHGEN.
(GPIO/CHG)ControlsPortFunctionRegbatmonchgGPIOGPIONextchgen_selbucenGPIO1Gpin1FunctionXX10Input=00EnabledXX10Input=10NotEnabled101XX0XXX1XEnabled000XHiZ100XInput(dig)->Input010XOutput=0040SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013ControlsPortFunctionRegbatmonchgGPIOGPIONextchgen_selbucenGPIO1Gpin1Function110XOutput=10GPIOGPIOFactoryfmdisabledGPIO_tstiobGPIO2gpin2001HiZ0101Input(dig)->input011Output=00111Output=10TheLP3972hasprovisionfortwobatteryconnections,themainbatteryVBATandBackupBattery(SeeApplicationsSchematicDiagrams1&2oftheLP3972DataSheet).
ThefunctionofthebatteryswitchistoconnectpowertotheLDO_RTCfromtheappropriatebattery,dependingonconditionsdescribedbelow:Ifonlythebackupbatteryisapplied,theswitchwillautomaticallyconnecttheLDO_RTCpowertothisbattery.
Ifonlythemainbatteryisapplied,theswitchwillautomaticallyconnecttheLDO_RTCpowertothisbattery.
Ifbothbatteriesareapplied,andthemainbatteryissufficientlycharged(VBAT>3.
1V),theswitchwillautomaticallyconnecttheRTCLDOpowertothemainbattery.
Asthemainbatteryisdischargedbyuse,theuserwillbewarnedbyaseparatecircuitcallednBATT_FLT.
Thenifnoactionistakentorestorethechargeonthemainbattery,anddischargingiscontinuedthebatteryswitchwillprotecttheLDO_RTCbydisconnectingfromthemainbatteryandconnectingtothebackupbattery.
–ThemainbatteryvoltageatwhichtheLDO_RTCisswitchedfrommaintobackupbatteryis2.
9Vtypically.
–Thereisahysteresisvoltageinthisswitchoperationso,theLDO_RTCwillnotbereconnectedtomainbatteryuntilmainbatteryvoltageisgreaterthan3.
1Vtypically.
Additionally,theusermaywishtodisablethebatteryswitch,suchas,inthecasewhenonlyamainbatteryisused.
Thisisaccomplishedbysettingthe"nobackupbatterybit"inthecontrolregister8h'89bit7NBUB.
Withthisbitsetto"1",theabovedescribedswitchingwillnotoccur,thatistheLDO_RTCwillremainconnectedtothemainbatteryevenasitisdischargedbelowthe2.
9Voltthreshold.
REGULATEDVOLTAGESOKAllthepowerdomainshaveownregisterbit(X_OK)thatprocessorcanreadviaserialinterfacetobesurethatenabledpowersareOK(regulating).
Notethatthesereadonlybitsareonlyvalidwhenregulatorsaresettled(avoidreadingthesebitsduringvoltagechangeorpowerup).
THERMALMANAGEMENTApplication:Thereisamodewhereinall6comparators(flags)canbeturnedonviathe"enallflags"controlregisterbit.
Thismodeallowstheusertointerrogatethedeviceorsystemtemperatureunderthesetoperatingconditions.
Thus,therateoftemperaturechangecanalsobeestimated.
Thesystemmaythennegotiateforspeedandpowertradeoff,ordeploycoolingmaneuverstooptimizesystemperformance.
The"enallflags"bitneedsenabledonlywhenthe"bctbitsarereadtoconservepower.
Note:Thethermalmanagementflagshavebeenverifiedfunctional.
Presentlytheseregistersareaccessiblebyfactoryonly.
Ifthereisademandforthisfunction,therelevantregistercontrolsmaybeshiftedintotheuserprogrammablebank;thetemperaturerangeandresolutionoftheseflags,mightalsoberefined/redefined.
THERMALWARNING2of6lowpowercomparators,eachconsumeslessthan1A,arealwaysenabledtooperatethe"T=125°Cwarningflagwithhysteresis.
Thisallowscontinuousmonitoringofathermal-warningflagfeaturewithverylowpowerconsumption.
LP3972THERMALFLAGSFUNCTIONALDIAGRAM,DATAFROMINITIALSILICONThefollowingfunctionsareextrafeaturesfromthethermalshutdowncircuit:Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback41ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comFigure29.
ApplicationNote-LP3972ResetSequenceINITIALCOLDSTARTPOWERONSEQUENCE1.
TheBackupbatteryisconnectedtothePMU,powerisappliedtotheback-upbatterypin,theLDO_RTCturnsonandsuppliesastableoutputvoltagetotheVCC_BATTpinoftheApplicationsprocessor(initiatingthepower-onresetevent)withnRSTOassertedfromtheLP3972totheprocessor.
2.
nRSTOde-assertsafteraminimumof50mS.
3.
TheApplicationsprocessorwaitsforthede-assertionofnBATT_FLTtoindicatesystempower(VIN)isavailable.
4.
Aftersystempower(VIN)isapplied,theLP3972de-assertsnBATT_FLT.
NotethatBOTHnRSTOandnBATT_FLTneedtobede-assertedbeforeSYS_ENisenabled.
Thesequenceofthetwosignalsisindependentofeachother.
5.
TheApplicationsprocessorassertsSYS_EN,theLP3972enablesthesystemhigh-voltagepowersupplies.
TheApplicationsprocessorstartsitscountdowntimersetto125mS.
6.
TheLP3972enablesthehigh-voltagepowersupplies.
–LDO1powerforVCC_MVT(PowerforinternallogicandI/OBlocks),BG(Bandgapreferencevoltage),OSC13M(13MHzoscillatorvoltage)andPLLenabledfirst,followedbyothersifdelayison.
7.
Countdowntimerexpires;theApplicationsprocessorassertsPWR_ENtoenablethelow-voltagepowersupplies.
Theprocessorstartsthecountdowntimersetto125mSperiod.
8.
TheApplicationsprocessorassertsPWR_EN(ext.
pinorI2C),theLP3972enablesthelow-voltageregulators.
9.
Countdowntimerexpires;IfenabledpowerdomainsareOK(I2Cread)thepowerupsequencecontinuesbyenablingtheprocessors13MHzoscillatorandPLL's.
10.
TheApplicationsprocessorbeginstheexecutionofcode.
42SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013*NotethatBOTHnRSTOandnBATT_FLTneedtobede-assertedbeforeSYS_ENisenabled.
Thesequenceofthetwosignalsisindependentofeachotherandcanoccuriseitherorder.
Figure30.
POWER-ONTIMINGSymbolDescriptionMinTypMaxUnitt1DelayfromVCC_RTCassertiontonRSTOde-assertion50mSt2DelayfromnBATT_FLTde-assertiontonRSTIassertion100St3DelayfromnRSTde-assertiontoSYS_ENassertion10mSt4DelayfromSYS_ENassertiontoPWR_ENassertion125mSt5DelayfromPWR_ENassertiontonRSTOde-assertion125mSHARDWARERESETSEQUENCEHardwareresetinitiateswhenthenRSTIsignalisasserted(low).
UponassertionofnRSTtheprocessorentershardwareresetstate.
TheLP3972holdsthenRSTlowlongenough(50mstyp.
)toallowtheprocessortimetoinitiatetheresetstate.
RESETSEQUENCE1.
nRSTIisasserted.
2.
nRSTOisassertedandwillde-assertsafteraminimumof50mS3.
TheApplicationsprocessorwaitsforthede-assertionofnBATT_FLTtoindicatesystempower(VIN)isavailable.
4.
Aftersystempower(VIN)isturnedon,theLP3972de-assertsnBATT_FLT.
5.
TheApplicationsprocessorassertsSYS_EN,theLP3972enablesthesystemhigh-voltagepowersupplies.
TheApplicationsprocessorstartsitscountdowntimer.
6.
TheLP3972enablesthehigh-voltagepowersupplies.
7.
Countdowntimerexpires;theApplicationsprocessorassertsPWR_ENtoenablethelow-voltagepowersupplies.
Theprocessorstartsthecountdowntimer.
Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback43ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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TheApplicationsprocessorassertsPWR_EN,theLP3972enablesthelow-voltageregulators.
9.
Countdowntimerexpires;IfenabledpowerdomainsareOK(I2Cread)thepowerupsequencecontinuesbyenablingtheprocessors13MHzoscillatorandPLL's.
10.
TheApplicationsprocessorbeginstheexecutionofcode.
APPLICATIONHINTSLDOCONSIDERATIONSExternalCapacitorsTheLP3972'sregulatorsrequireexternalcapacitorsforregulatorstability.
Thesearespecificallydesignedforportableapplicationsrequiringminimumboardspaceandsmallestcomponents.
Thesecapacitorsmustbecorrectlyselectedforgoodperformance.
InputCapacitorAninputcapacitorisrequiredforstability.
Itisrecommendedthata1.
0FcapacitorbeconnectedbetweentheLDOinputpinandground(thiscapacitancevaluemaybeincreasedwithoutlimit).
Thiscapacitormustbelocatedadistanceofnotmorethan1cmfromtheinputpinandreturnedtoacleananalogueground.
Anygoodqualityceramic,tantalum,orfilmcapacitormaybeusedattheinput.
Important:Tantalumcapacitorscansuffercatastrophicfailuresduetosurgecurrentwhenconnectedtoalowimpedancesourceofpower(likeabatteryoraverylargecapacitor).
Ifatantalumcapacitorisusedattheinput,itmustbeensuredbythemanufacturertohaveasurgecurrentratingsufficientfortheapplication.
TherearenorequirementsfortheESR(EquivalentSeriesResistance)ontheinputcapacitor,buttoleranceandtemperaturecoefficientmustbeconsideredwhenselectingthecapacitortoensurethecapacitancewillremainapproximately1.
0Fovertheentireoperatingtemperaturerange.
OutputCapacitorTheLDOsaredesignedspecificallytoworkwithverysmallceramicoutputcapacitors.
A1.
0Fceramiccapacitor(temperaturetypesZ5U,Y5VorX7R)withESRbetween5mto500m,aresuitableintheapplicationcircuit.
ForthisdevicetheoutputcapacitorshouldbeconnectedbetweentheVOUTpinandground.
Itisalsopossibletousetantalumorfilmcapacitorsatthedeviceoutput,COUT(orVOUT),butthesearenotasattractiveforreasonsofsizeandcost(seethesectionCapacitorCharacteristics).
TheoutputcapacitormustmeettherequirementfortheminimumvalueofcapacitanceandalsohaveanESRvaluethatiswithintherange5mto500mforstability.
No-LoadStabilityTheLDOswillremainstableandinregulationwithnoexternalload.
Thisisanimportantconsiderationinsomecircuits,forexampleCMOSRAMkeep-aliveapplications.
CapacitorCharacteristicsTheLDOsaredesignedtoworkwithceramiccapacitorsontheoutputtotakeadvantageofthebenefitstheyoffer.
Forcapacitancevaluesintherangeof0.
47Fto4.
7F,ceramiccapacitorsarethesmallest,leastexpensiveandhavethelowestESRvalues,thusmakingthembestforeliminatinghighfrequencynoise.
TheESRofatypical1.
0Fceramiccapacitorisintherangeof20mto40m,whicheasilymeetstheESRrequirementforstabilityfortheLDOs.
Forbothinputandoutputcapacitors,carefulinterpretationofthecapacitorspecificationisrequiredtoensurecorrectdeviceoperation.
Thecapacitorvaluecanchangegreatly,dependingontheoperatingconditionsandcapacitortype.
Inparticular,theoutputcapacitorselectionshouldtakeaccountofallthecapacitorparameters,toensurethatthespecificationismetwithintheapplication.
ThecapacitancecanvarywithDCbiasconditionsaswellastemperatureandfrequencyofoperation.
Capacitorvalueswillalsoshowsomedecreaseovertimeduetoaging.
Thecapacitorparametersarealsodependantontheparticularcasesize,withsmallersizesgivingpoorer44SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013performancefiguresingeneral.
Asanexample,Figure31showsatypicalgraphcomparingdifferentcapacitorcasesizesinaCapacitancevs.
DCBiasplot.
Asshowninthegraph,increasingtheDCBiasconditioncanresultinthecapacitancevaluefallingbelowtheminimumvaluegivenintherecommendedcapacitorspecificationstable.
Notethatthegraphshowsthecapacitanceoutofspecforthe0402casesizecapacitorathigherbiasvoltages.
Itisthereforerecommendedthatthecapacitormanufacturers'specificationsforthenominalvaluecapacitorareconsultedforallconditions,assomecapacitorsizes(e.
g.
0402)maynotbesuitableintheactualapplication.
Figure31.
GraphShowingaTypicalVariationinCapacitancevs.
DCBiasTheceramiccapacitor'scapacitancecanvarywithtemperature.
ThecapacitortypeX7R,whichoperatesoveratemperaturerangeof55°Cto+125°C,willonlyvarythecapacitancetowithin±15%.
ThecapacitortypeX5Rhasasimilartoleranceoverareducedtemperaturerangeof55°Cto+85°C.
Manylargevalueceramiccapacitors,largerthan1FaremanufacturedwithZ5UorY5Vtemperaturecharacteristics.
Theircapacitancecandropbymorethan50%asthetemperaturevariesfrom25°Cto85°C.
ThereforeX7RisrecommendedoverZ5UandY5Vinapplicationswheretheambienttemperaturewillchangesignificantlyaboveorbelow25°C.
Tantalumcapacitorsarelessdesirablethanceramicforuseasoutputcapacitorsbecausetheyaremoreexpensivewhencomparingequivalentcapacitanceandvoltageratingsinthe0.
47Fto4.
7Frange.
AnotherimportantconsiderationisthattantalumcapacitorshavehigherESRvaluesthanequivalentsizeceramics.
ThismeansthatwhileitmaybepossibletofindatantalumcapacitorwithanESRvaluewithinthestablerange,itwouldhavetobelargerincapacitance(whichmeansbiggerandmorecostly)thanaceramiccapacitorwiththesameESRvalue.
ItshouldalsobenotedthattheESRofatypicaltantalumwillincreaseabout2:1asthetemperaturegoesfrom25°Cdownto–40°C,sosomeguardbandmustbeallowed.
BUCKCONSIDERATIONSInductorSelectionTherearetwomainconsiderationswhenchoosinganinductor;theinductorshouldnotsaturate,andtheinductorcurrentrippleissmallenoughtoachievethedesiredoutputvoltageripple.
Differentsaturationcurrentratingspecsarefollowedbydifferentmanufacturerssoattentionmustbegiventodetails.
Saturationcurrentratingsaretypicallyspecifiedat25°Csoratingsatmaxambienttemperatureofapplicationshouldberequestedfrommanufacturer.
Therearetwomethodstochoosetheinductorsaturationcurrentrating.
Method1Thesaturationcurrentisgreaterthanthesumofthemaximumloadcurrentandtheworstcaseaveragetopeakinductorcurrent.
ThiscanbewrittenasCopyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback45ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comwhereIRIPPLE:AveragetopeakinductorcurrentIOUTMAX:Maximumloadcurrent(1500mA)VIN:MaximuminputvoltageinapplicationL:Mininductorvalueincludingworstcasetolerances(30%dropcanbeconsideredformethod1)f:Minimumswitchingfrequency(1.
6MHz)VOUT:Outputvoltage(2)Method2Amoreconservativeandrecommendedapproachistochooseaninductorthathassaturationcurrentratinggreaterthanthemaxcurrentlimitof3A.
A2.
2Hinductorwithasaturationcurrentratingofatleast3Aisrecommendedformostapplications.
Theinductor'sresistanceshouldbelessthan0.
3foragoodefficiency.
Table1listssuggestedinductorsandsuppliers.
Forlow-costapplications,anunshieldedbobbininductorcouldbeconsidered.
Fornoisecriticalapplications,atoroidalorshieldedbobbininductorshouldbeused.
Agoodpracticeistolayouttheboardwithoverlappingfootprintsofbothtypesfordesignflexibility.
Thisallowssubstitutionofalow-noiseshieldedinductor,intheeventthatnoisefromlow-costbobbinmodelsisunacceptable.
InputCapacitorSelectionAceramicinputcapacitorof10F,6.
3Vissufficientformostapplications.
PlacetheinputcapacitorascloseaspossibletotheVINpinofthedevice.
Alargervaluemaybeusedforimprovedinputvoltagefiltering.
UseX7RorX5Rtypes,donotuseY5V.
DCbiascharacteristicsofceramiccapacitorsmustbeconsideredwhenselectingcasesizeslike0805and0603.
TheinputfiltercapacitorsuppliescurrenttothePFETswitchoftheconverterinthefirsthalfofeachcycleandreducesvoltagerippleimposedontheinputpowersource.
Aceramiccapacitor'slowESRprovidesthebestnoisefilteringoftheinputvoltagespikesduetothisrapidlychangingcurrent.
Selectacapacitorwithsufficientripplecurrentrating.
Theinputcurrentripplecanbecalculatedas:(3)TheworstcaseiswhenVIN=2*VOUTTable1.
SuggestedInductorsandTheirSuppliersModelVendorDimensionsLxWxH(mm)D.
C.
R.
(Typ)FDSE0312-2R2MToko3.
0x3.
0x1.
2160mDO1608C-222Coilcraft6.
6x4.
5x1.
880mOutputCapacitorSelectionUsea10F,6.
3Vceramiccapacitor.
UseX7RorX5Rtypes,donotuseY5V.
DCbiascharacteristicsofceramiccapacitorsmustbeconsideredwhenselectingcasesizeslike0805and0603.
DCbiascharacteristicsvaryfrommanufacturertomanufactureranddcbiascurvesshouldberequestedfromthemaspartofthecapacitorselectionprocess.
Theoutputfiltercapacitorsmoothsoutcurrentflowfromtheinductortotheload,helpsmaintainasteadyoutputvoltageduringtransientloadchangesandreducesoutputvoltageripple.
ThesecapacitorsmustbeselectedwithsufficientcapacitanceandsufficientlylowESRtoperformthesefunctions.
46SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
ti.
comSNVS468K–SEPTEMBER2006–REVISEDMAY2013TheoutputvoltagerippleiscausedbythecharginganddischargingoftheoutputcapacitorandalsoduetoitsESRandcanbecalculatedas:(4)Voltagepeak-to-peakrippleduetoESRcanbeexpressedasfollowsVPP-ESR=(2*IRIPPLE)*RESR(5)BecausethesetwocomponentsareoutofphasetheRMSvaluecanbeusedtogetanapproximatevalueofpeak-to-peakripple.
Voltagepeak-to-peakripple,rootmeansquaredcanbeexpressedasfollows(6)Notethattheoutputvoltagerippleisdependentontheinductorcurrentrippleandtheequivalentseriesresistanceoftheoutputcapacitor(RESR).
TheRESRisfrequencydependent(aswellastemperaturedependent);makesurethevalueusedforcalculationsisattheswitchingfrequencyofthepart.
Table2.
SuggestedCapacitorandTheirSuppliersModelTypeVendorVoltageCaseSizeInch(mm)GRM21BR60J106KCeramic,X5RMurata6.
3V0805(2012)JMK212BJ106KCeramic,X5RTaiyo-Yuden6.
3V0805(2012)C2012X5R0J106KCeramic,X5RTDK6.
3V0805(2012)BuckOutputRippleManagementIfVINandILOADincrease,theoutputrippleassociatedwiththeBuckRegulatorsalsoincreases.
Figure32showsthesafeoperatingarea.
ToensureoperationintheareaofconcernitisrecommendedthatthesystemdesignercircumventstheoutputrippleissuestoinstallSchottkydiodesontheBuck(s)thatareexpectedtoperformundertheseextremecornerconditions.
(Schottkydiodesarerecommendedtoreducetheoutputripple,ifsystemrequirementsincludethisshadedareaofoperation.
VIN>1.
5VandILOAD>1.
24)Figure32.
Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback47ProductFolderLinks:LP3972LP3972SNVS468K–SEPTEMBER2006–REVISEDMAY2013www.
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comBoardLayoutConsiderationsPCboardlayoutisanimportantpartofDC-DCconverterdesign.
PoorboardlayoutcandisrupttheperformanceofaDC-DCconverterandsurroundingcircuitrybycontributingtoEMI,groundbounce,andresistivevoltagelossinthetraces.
ThesecansenderroneoussignalstotheDC-DCconverterIC,resultinginpoorregulationorinstability.
Goodlayoutfortheconverterscanbeimplementedbyfollowingafewsimpledesignrules.
1.
Placetheconverters,inductorandfiltercapacitorsclosetogetherandmakethetracesshort.
Thetracesbetweenthesecomponentscarryrelativelyhighswitchingcurrentsandactasantennas.
Followingthisrulereducesradiatednoise.
SpecialcaremustbegiventoplacetheinputfiltercapacitorveryclosetotheVINandGNDpin.
2.
Arrangethecomponentssothattheswitchingcurrentloopscurlinthesamedirection.
Duringthefirsthalfofeachcycle,currentflowsfromtheinputfiltercapacitorthroughtheconverterandinductortotheoutputfiltercapacitorandbackthroughground,formingacurrentloop.
Inthesecondhalfofeachcycle,currentispulledupfromgroundthroughtheconverterbytheinductortotheoutputfiltercapacitorandthenbackthroughgroundformingasecondcurrentloop.
Routingtheseloopssothecurrentcurlsinthesamedirectionpreventsmagneticfieldreversalbetweenthetwohalf-cyclesandreducesradiatednoise.
3.
Connectthegroundpinsoftheconverterandfiltercapacitorstogetherusinggenerouscomponent-sidecopperfillasapseudo-groundplane.
Then,connectthistotheground-plane(ifoneisused)withseveralvias.
Thisreducesground-planenoisebypreventingtheswitchingcurrentsfromcirculatingthroughthegroundplane.
Italsoreducesgroundbounceattheconverterbygivingitalow-impedancegroundconnection.
4.
UsewidetracesbetweenthepowercomponentsandforpowerconnectionstotheDC-DCconvertercircuit.
Thisreducesvoltageerrorscausedbyresistivelossesacrossthetraces.
5.
Routenoisesensitivetraces,suchasthevoltagefeedbackpath,awayfromnoisytracesbetweenthepowercomponents.
Thevoltagefeedbacktracemustremainclosetotheconvertercircuitandshouldbedirectbutshouldberoutedoppositetonoisycomponents.
ThisreducesEMIradiatedontotheDC-DCconverter'sownvoltagefeedbacktrace.
Agoodapproachistoroutethefeedbacktraceonanotherlayerandtohaveagroundplanebetweenthetoplayerandlayeronwhichthefeedbacktraceisrouted.
Inthesamemannerfortheadjustablepartitisdesiredtohavethefeedbackdividersonthebottomlayer.
6.
Placenoisesensitivecircuitry,suchasradioRFblocks,awayfromtheDC-DCconverter,CMOSdigitalblocksandothernoisycircuitry.
Interferencewithnoise-sensitivecircuitryinthesystemcanbereducedthroughdistance.
48SubmitDocumentationFeedbackCopyright2006–2013,TexasInstrumentsIncorporatedProductFolderLinks:LP3972LP3972www.
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comSNVS468K–SEPTEMBER2006–REVISEDMAY2013REVISIONHISTORYChangesfromRevisionJ(May2013)toRevisionKPageChangedlayoutofNationalDataSheettoTIformat48Copyright2006–2013,TexasInstrumentsIncorporatedSubmitDocumentationFeedback49ProductFolderLinks:LP3972PACKAGEOPTIONADDENDUMwww.
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com3-May-2013Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Lead/BallFinishMSLPeakTemp(3)OpTemp(°C)Top-SideMarkings(4)SamplesLP3972SQ-0514/NOPBACTIVEWQFNRSB401000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM72-0514LP3972SQ-5810/NOPBACTIVEWQFNRSB401000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM72-5810LP3972SQ-A413ACTIVEWQFNRSB401000TBDCallTICallTI-40to12572-A413LP3972SQ-A413/NOPBACTIVEWQFNRSB401000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to12572-A413LP3972SQ-A514ACTIVEWQFNRSB401000TBDCallTICallTI-40to12572-A514LP3972SQ-A514/NOPBACTIVEWQFNRSB401000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to12572-A514LP3972SQ-E514ACTIVEWQFNRSB401000TBDCallTICallTI-40to12572-E514LP3972SQ-E514/NOPBACTIVEWQFNRSB401000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to12572-E514LP3972SQ-I414/NOPBACTIVEWQFNRSB401000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to12572-I414LP3972SQ-I514ACTIVEWQFNRSB401000TBDCallTICallTI-40to12572-I514LP3972SQ-I514/NOPBACTIVEWQFNRSB401000Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM-40to12572-I514LP3972SQE-A413/NOPBACTIVEWQFNRSB40250Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM72-A413LP3972SQE-A514OBSOLETEWQFNRSB40TBDCallTICallTILP3972SQE-A514/NOPBACTIVEWQFNRSB40250TBDCallTICallTILP3972SQE-E514/NOPBACTIVEWQFNRSB40250Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM72-E514LP3972SQE-I514/NOPBACTIVEWQFNRSB40250Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM72-I514LP3972SQX-0514/NOPBACTIVEWQFNRSB404500Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM72-0514LP3972SQX-5810/NOPBACTIVEWQFNRSB404500Green(RoHS&noSb/Br)CUSNLevel-1-260C-UNLIM72-5810PACKAGEOPTIONADDENDUMwww.
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LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.
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TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.
Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.
Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.
ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.
Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.
1%byweightinhomogeneousmaterial)(3)MSL,PeakTemp.
--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
PACKAGEOPTIONADDENDUMwww.
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OnlyoneTop-SideMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireTop-SideMarkingforthatdevice.
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TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantLP3972SQ-0514/NOPBWQFNRSB401000178.
012.
45.
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31.
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0Q1LP3972SQ-5810/NOPBWQFNRSB401000178.
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0Q1LP3972SQ-A413WQFNRSB401000178.
012.
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31.
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0Q1LP3972SQ-A413/NOPBWQFNRSB401000178.
012.
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0Q1LP3972SQ-A514WQFNRSB401000178.
012.
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31.
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0Q1LP3972SQ-A514/NOPBWQFNRSB401000178.
012.
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0Q1LP3972SQ-E514WQFNRSB401000178.
012.
45.
35.
31.
38.
012.
0Q1LP3972SQ-E514/NOPBWQFNRSB401000178.
012.
45.
35.
31.
38.
012.
0Q1LP3972SQ-I414/NOPBWQFNRSB401000178.
012.
45.
35.
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38.
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0Q1LP3972SQ-I514WQFNRSB401000178.
012.
45.
35.
31.
38.
012.
0Q1LP3972SQ-I514/NOPBWQFNRSB401000178.
012.
45.
35.
31.
38.
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0Q1LP3972SQE-A413/NOPBWQFNRSB40250178.
012.
45.
35.
31.
38.
012.
0Q1LP3972SQE-E514/NOPBWQFNRSB40250178.
012.
45.
35.
31.
38.
012.
0Q1LP3972SQE-I514/NOPBWQFNRSB40250178.
012.
45.
35.
31.
38.
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0Q1LP3972SQX-0514/NOPBWQFNRSB404500330.
012.
45.
35.
31.
38.
012.
0Q1LP3972SQX-5810/NOPBWQFNRSB404500330.
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0Q1LP3972SQX-A413WQFNRSB404500330.
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0Q1LP3972SQX-A413/NOPBWQFNRSB404500330.
012.
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35.
31.
38.
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0Q1PACKAGEMATERIALSINFORMATIONwww.
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com8-May-2013PackMaterials-Page1DevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantLP3972SQX-A514WQFNRSB404500330.
012.
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0Q1LP3972SQX-A514/NOPBWQFNRSB404500330.
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0Q1LP3972SQX-E514WQFNRSB404500330.
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0Q1LP3972SQX-E514/NOPBWQFNRSB404500330.
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0Q1LP3972SQX-I414/NOPBWQFNRSB404500330.
012.
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31.
38.
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0Q1LP3972SQX-I514WQFNRSB404500330.
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0Q1LP3972SQX-I514/NOPBWQFNRSB404500330.
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0Q1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)LP3972SQ-0514/NOPBWQFNRSB401000203.
0190.
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0190.
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0190.
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0190.
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0190.
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0190.
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0190.
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0PACKAGEMATERIALSINFORMATIONwww.
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com8-May-2013PackMaterials-Page2DevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)LP3972SQ-I514/NOPBWQFNRSB401000203.
0190.
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0190.
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0190.
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0LP3972SQX-0514/NOPBWQFNRSB404500367.
0367.
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0367.
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0367.
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0367.
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0367.
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0LP3972SQX-E514WQFNRSB404500367.
0367.
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0LP3972SQX-E514/NOPBWQFNRSB404500367.
0367.
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