UARTgspeed
gspeed 时间:2021-01-07 阅读:()
Copyright2018–2020XilinxCopyright2018–2020XilinxXAZynq-7000SoCZ-7010/7020/7030DevicesXAZynqUltraScale+MPSoCZU2/ZU3EG/ZU11EGZU4/ZU5EV/ZU7EVDevicesPage2AutomotiveSoCComparisonApplicationProcessorReal-TimeProcessorProgrammableLogicGraphicsProcessorDSPSlicesPowerManagementSpeedGradesAutomotiveStandardsExternalDynamicMemoryInterfaceDual-coreArmCortex-A9MPCoreupto667MHzN/A28K–125KLogicCellsN/A80–400Full(PS+PL),SeparateVoltageonPS&PL-1AEC-Q100,ProductionPartApprovalProcessx16/x32:DDR3L,DDR3,DDR2,LPDDR2w/ECC(supports16-bit)Quad-coreArmCortex-A53MPCoreupto1.
2GHzDual-coreArmCortex-R5MPCoreupto500MHz103K–653SystemLogicCellsMali-400MP2upto600MHz240–2,928SeparateVoltageonPS&PL,Full(PL+PS)/Fullpowerdomain/Lowpowerdomain/BatteryPowerDomains(PS)-1,-1L(1)AEC-Q100,ProductionPartApprovalProcessx32/x64:DDR4,LPDDR4,DDR3,DDR3L,LPDDR3w/ECCNotes:1.
ZU11EGandZU7EV-1Lspeedgradesarenotsupported.
Copyright2018–2020XilinxXAKintex-7Page3AutomotiveDeviceComparisonXAArtix-7XASpartan-6XASpartan-7CoreVoltage1.
0V1.
2V1.
0VLogicCell12K–101K3K–74K6K–102KDSPSlices40–2408–13210–160TotalBlockRAM(K)720–4,860216–3,096180–4,320PCIe1@Gen2uptox40–1@Gen1x10AutomotiveStandardsAEC-Q100,ProductionPartApprovalProcessAEC-Q100,ProductionPartApprovalProcessAEC-Q100,ProductionPartApprovalProcessSerialTransceivers2–40–40SpeedGrades-1,-2-2,-3-1,-2CMTs3–62–62–81.
0V162K6002,1881@Gen2uptox8AEC-Q100,ProductionPartApprovalProcess8-18Copyright2018–2020XilinxPage4XAZynqUltraScale+MPSoCs1.
Forfullpartnumberdetails,seetheOrderingInformationsectioninDS891,ZynqUltraScale+MPSoCOverview.
2.
XAZU11EGandXAZU7EV-1Lspeedgradesarenotsupported.
DeviceName(1)XAZU2EGXAZU3EGXAZU11EGXAZU4EVXAZU5EVXAZU7EVProcessingSystem(PS)ApplicationProcessorUnitProcessorCoreQuad-coreArmCortex-A53MPCoreupto1.
2GHzMemoryw/ECCL1Cache32KBI/Dpercore,L2Cache1MB,on-chipMemory256KBReal-TimeProcessorUnitProcessorCoreDual-coreArmCortex-R5MPCoreupto500MHzMemoryw/ECCL1Cache32KBI/Dpercore,TightlyCoupledMemory128KBpercoreGraphic&VideoAccelerationGraphicsProcessingUnitMali-400MP2upto600MHzMemoryL2Cache64KBExternalMemoryDynamicMemoryInterfacex32/x64:DDR4,LPDDR4,DDR3,DDR3L,LPDDR3withECCStaticMemoryInterfacesNAND,2xQuad-SPIConnectivityHigh-SpeedConnectivityPCIeGen2x4,2xUSB3.
0,SATA3.
1,DisplayPort,4xTri-modeGigabitEthernetGeneralConnectivity2xUSB2.
0,2xSD/SDIO/eMMC,2xUART,2xCAN2.
0B,2xI2C,2xSPI,4x32bGPIOIntegratedBlockFunctionalityPowerManagementFull/Low/PL/BatteryPowerDomainsSecurityRSA,AES,andSHAAMS-SystemMonitor10-bit,1MSPS-Temperature,Voltage,andCurrentMonitorPStoPLInterface12x32/64/128bAXIPortsProgrammableLogic(PL)ProgrammableFunctionalitySystemLogicCells(K)103154653192256504CLBFlip-Flops(K)94141597176234461CLBLUTs(K)477129988117230MemoryMax.
DistributedRAM(Mb)1.
21.
89.
12.
63.
56.
2BlockRAMBlocks150216600128144312TotalBlockRAM(Mb)5.
37.
621.
14.
55.
111.
0UltraRAMBlocks--80486496UltraRAM(Mb)--22.
514.
018.
027.
0ClockingClockManagementTiles(CMTs)338448IntegratedIPDSPSlices24036029287281,2481,728VCU---111PCIExpressGen3x16--4222AMS-SystemMonitor111111TransceiversGTH12.
5Gb/sTransceivers--32161616SpeedGradesI-Grade(2)-1(0.
85V),-L1(0.
72V)-1(0.
85V)-1(0.
85V),-L1(0.
72V)-1(0.
85V)Q-Grade-1(0.
85V)-1(0.
85V)-1(0.
85V)Copyright2018–2020XilinxPkgFootprint(2)Dimensions(mm)XAZU2EGXAZU3EGXAZU11EGSBVA484(3)19x19170,24,584,0170,24,584,0SFVA625(3)21x21170,24,1564,0170,24,1564,0SFVC784(3)23x23214,96,1564,0214,96,1564,0FFVF151740x40214,48,4164,32Page5Important:Verifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.
xilinx.
comXAZynqUltraScale+MPSoCsPSI/Os(1),3.
3VHigh-Density(HD)I/O,1.
8VHigh-Performance(HP)I/OsPS-GTR6Gb/s,GTH12.
5Gb/sNotes:1.
PSI/OisacombinationofPSMIOandPSDDRIO.
2.
Forfullpartnumberdetails,seetheOrderingInformationsectioninDS891,ZynqUltraScale+MPSoCOverview.
3.
Thesepackagesareonlyofferedin0.
8mmballpitch.
PkgFootprint(2)Dimensions(mm)XAZU4EVXAZU5EVXAZU7EVSBVA484(3)19x19SFVA625(3)21x21SFVC784(3)23x23214,96,1564,4214,96,1564,4FBVB90031x31214,48,1564,16Copyright2018–2020XilinxPage6XAZynq-7000SoCsNotes:1.
AllpackageslistedarePb-free.
2.
HR=HighRangeI/OwithsupportforI/Ovoltagefrom1.
2Vupto3.
3V.
3.
HP=HighPerformanceI/OwithsupportforI/Ovoltagefrom1.
2Vto1.
8V.
4.
PSI/OincludesuserI/OandDDRI/O.
DeviceName(1)XA7Z010XA7Z020XA7Z030ProcessingSystem(PS)ApplicationProcessorUnitProcessorCoreDualArmCortex-A9MPCoreupto667MHzProcessorExtensionNEONSIMDEngineandSingle/DoublePrecisionFloatingPointUnitperProcessorMemoryL1Cache32KBI/DperCoreL2Cache512KBOn-ChipMemory256KBExternalMemoryDynamicMemoryInterfacex32/x64:DDR3,DDR3L,DDR2,LPDDR2StaticMemoryInterfacesNAND,NOR,2xQuad-SPIConnectivityHigh-SpeedConnectivity2xTri-modeGigabitEthernetGeneralConnectivity2xUSB2.
0,2xSD/SDIO/eMMC,2xUART,2xCAN2.
0B,2xI2C,2xSPI,4x32bGPIOIntegratedBlockFunctionalitySecurityRSA,AES,andSHAAMS-SystemMonitor2x12-bit,1MSPS-Temperature,Voltage,andCurrentMonitorPStoPLInterface9x32/64AXIPortsProgrammableLogic(PL)ProgrammableFunctionalityXilinx7SeriesPLEquivalentArtix-7Artix-7Kintex-7LogicCells28,16085,280125,760CLBFlip-Flops35,300106,400157,200CLBLUTs17,60053,30078,600MemoryTotalBlockRAM(KB)(#36KbBlocks)240(60)560(140)1,060(265)IntegratedIPDSPSlices80220400PeakDSPPerformance100GMACs276GMACs593GMACsPCIExpress--Gen2x4AMS/XADCAESandSHA256bDecryptionandAuthenticationforSecureProgrammableConfigurationSpeedGradesI-Grade-1Q-Grade-1Package(1)Size(mm)Pitch(mm)HRI/O(2),HPI/O(3),PSI/O(4),GTXTransceiverPackageCLG22513x130.
854,0,84,0CLG40017x170.
8100,0,128,0125,0,128,0CLG48419x190.
8200,0,128,0FBV48423x231.
0100,63,128,4Copyright2018–2020XilinxPage7XAArtix-7FPGAsNotes:1.
SupportsPCIExpressBase2.
1specificationatGen1andGen2datarates.
2.
Representsthemaximumnumberoftransceiversavailable.
NotethattheCSG324devicesareavailablewithouttransceivers.
SeethePackagesectionofthistablefordetails.
3.
DevicemigrationisavailablewithintheArtix-7familyforlikepackagesbutisnotsupportedbetweenother7seriesfamilies.
TransceiverOptimizationattheLowestCostandHighestDSPBandwidth(1.
0V,0.
95V,0.
9V)PartNumberXA7A12TXA7A15TXA7A25TXA7A35TXA7A50TXA7A75TXA7A100TLogicResourcesLogicCells12,80016,64023,36033,28052,16075,520101,440Slices2,0002,6003,6505,2008,15011,80015,850CLBFlip-Flops16,00020,80029,20041,60065,20094,400126,800MemoryResourcesMaximumDistributedRAM(Kb)1712003134006008921,188BlockRAM/FIFOw/ECC(36Kbeach)2025455075105135TotalBlockRAM(Kb)7209001,6201,8002,7003,7804,860ClockResourcesCMTs(1MMCM+1PLL)3535566I/OResourcesMaximumSingle-EndedI/O150250150250250285285MaximumDifferentialI/OPairs7212072120120137137EmbeddedHardIPResourcesDSPSlices40458090120180240PCIeGen2(1)1111111AnalogMixedSignal(AMS)/XADC1111111ConfigurationAES/HMACBlocks1111111GTPTransceivers(6.
25Gb/sMaxRate)(2)2444444SpeedGradesI-Grade-1,-2-1,-2-1,-2-1,-2-1,-2-1,-2-1,-2Q-Grade-1-1-1-1-1-1-1Package(3)Dimensions(mm)BallPitch(mm)AvailableUserI/O:3.
3VSelectIOHRI/O(GTPTransceivers)CPG23610x100.
5106(2)106(2)106(2)CPG23810x100.
5112(2)112(2)CSG32415x150.
8210(0)210(0)210(0)210(0)210(0)CSG32515x150.
8150(2)150(4)150(4)150(4)150(4)FGG48423x231.
0285(4)285(4)Copyright2018–2020XilinxPage8XAKintex-7FPGAsNotes:1.
SupportsPCIExpressBase2.
1specificationatGen1andGen2datarates.
2.
Representsthemaximumnumberoftransceiversavailable.
3.
Devicemigrationisnotsupportedbetweenother7seriesfamilies.
OptimizedforBestPrice-Performance(1.
0V,0.
95V,0.
9V)PartNumberXA7K160TLogicResourcesLogicCells162,240Slices25,350CLBFlip-Flops202,800MemoryResourcesMaximumDistributedRAM(Kb)2,188BlockRAM/FIFOw/ECC(36Kbeach)325TotalBlockRAM(Kb)11,700ClockResourcesCMTs(1MMCM+1PLL)8I/OResourcesMaximumSingle-EndedI/O400MaximumDifferentialI/OPairs192EmbeddedHardIPResourcesDSPSlices600PCIeGen2(1)1AnalogMixedSignal(AMS)/XADC1ConfigurationAES/HMACBlocks1GTXTransceivers(8.
0Gb/sMaxRate)(2)8SpeedGradesI-Grade-1Package(3)Dimensions(mm)BallPitch(mm)AvailableUserI/O:3.
3VSelectIOHRI/O,1.
8VHP1/O(GTXTransceivers)FFG67627x271.
0250,150(8)Copyright2018–2020XilinxPage9XASpartan-7FPGAsI/OOptimizationattheLowestCostandHighestPerformance-per-Watt(1.
0V)PartNumberXA7S6XA7S15XA7S25XA7S50XA7S75XA7S100LogicCells6,00012,80023,36052,16076,800102,400Slices9382,0003,6508,15112,00016,000CLBFlip-Flops7,50016,00029,20065,20096,000128,000Max.
DistributedRAM(Kb)701503136008321,100BlockRAM/FIFOw/ECC(36Kbeach)510457590120TotalBlockRAM(Kb)1803601,6202,7003,2404,320ClockMgmtTiles(1MMCM+1PLL)223588Max.
Single-EndedI/OPins100100150250400400Max.
DifferentialI/OPairs484872120192192DSPSlices102080120140160AnalogMixedSignal(AMS)/XADC001111ConfigurationAES/HMACBlocks001111I-Grade-1,-2-1,-2-1,-2-1,-2-1,-2-1,-2Q-Grade-1-1-1-1-1-1PackageDimensions(mm)BallPitch(mm)AvailableUserI/O:3.
3VSelectIOHRI/OCPGA1968x80.
5100100CSGA22513x130.
8100100150CSGA32415x150.
8150210FGGA48423x231.
0250338338FGGA67627x271.
0400400Copyright2018–2020XilinxPage10XASpartan-6FPGAsTransceiverOptimizationattheLowestCost(1.
2V)PartNumberXA6SLX4XA6SLX9XA6SLX16XA6SLX25XA6SLX45XA6SLX75XA6SLX100XA6SLX25TXA6SLX45TXA6SLX75TLogicResourcesLogicCells3,8409,15214,57924,05143,66174,637101,26224,05143,66174,637Slices6001,4302,2783,7586,82211,66215,8223,7586,82211,662CLBFlip-Flops4,80011,44018,22430,06454,57693,296126,57630,06454,57693,296MemoryResourcesMaximumDistributedRAM(Kb)7590136229401692976229401692BlockRAM(18Kbea.
)1232325211617226852116172TotalBlockRAM(Kb)2165765769362,0883,0964,8249362,0883,096ClockResourcesCMTs(2DCM+1PLL)2222466246EmbeddedHardIPResourcesMemoryControllerBlocks(Max)0222222222EndpointBlocksPCIe0000000111GTPTransceivers(3.
2Gb/sMaxRate)0000000244TotalI/OBanks4444444444MaxUserI/O132200232266320328326250296268SpeedGradesI-Grade-2,-3Q-Grade-2,-3PackageDimensions(mm)BallPitch(mm)AvailableUserI/O:3.
3VSelectIOHRI/O(GTPTransceivers)CSG22513x130.
8132(0)160(0)160(0)FTG25617x171.
0186(0)186(0)186(0)CSG32415x150.
8200(0)232(0)226(0)218(0)190(2)190(4)CSG48419x190.
8320(0)328(0)FGG48423x231.
0266(0)316(0)280(0)326(0)250(2)296(4)268(4)Copyright2018–2020XilinxPage11DeviceOrderingInformationImportant:Verifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.
xilinx.
comI=Tjfrom–40°Cto+100°C;Q=Tjfrom–40°Cto+125°CSpeedGrade-2=Mid-3=HighestXilinxAutomotiveGenerationXA7ZFamily###ValueIndex-1SpeedGrade-1=StandardFBCL:Wire-bond(.
8mm)FB:Flip-Chip(1mm)484PackagePinCountQTemperatureGrade(I,Q)VV:RoHS6/6G:RoHS6/6XilinxAutomotiveGenerationXA6SFamily###LogicCellsin1KUnits-1FGCS:Wire-bond(.
8mm)FT:Wire-bond(1mm)FG:Wire-bond(1mm)484PackagePinCountQTemperatureGrade(I,Q)GG:RoHS6/6LXLXTSub-familiesLX:LogicLXT:Logic+TransceiversProcessorSystemE:DualRPUQuadAPUSingleGPUEngineTypeG:GeneralPurposeV:VideoXilinxAutomotiveGenerationXAZUEGSpeedGrade-1=Standard-1L=LowPower-1S:Flip-Chip(.
8mm)484PackagePinCountITemperatureGrade(I,Q)ValueIndex#VV:RoHS6/6APackageDesignatorSBF:LidB:LidlessXilinxAutomotiveGenerationXA7SFamily###LogicCellsin1KUnits-1SpeedGrade-1=Standard-2=MediumFGCP:Wire-bond(.
5mm)FT:Wire-bond(1mm)CS:Wire-bond(.
8mm)FG:Wire-bond(1mm)484PackagePinCountQTemperatureGrade(I,Q)GG:RoHS6/6APackageDesignatorXilinxAutomotiveGenerationXA7###LogicCellsIn1Kunits-1SpeedGrade-1=Standard-2=MediumCPCP:Wire-bond(.
5mm)CS:Wire-bond(.
8mm)FG:Wire-bond(1mm)236PackagePinCountITemperatureGrade(I,Q)FamilyAGG:RoHS6/6XilinxAutomotiveGenerationXA7160TLogicCellsIn1Kunits-1SpeedGrade-1=StandardFFFF:Wire-bond(1mm)676PackagePinCountITemperatureGrade(I,Q)FamilyKGG:RoHS6/6Copyright2018–2020XilinxPage12ExternalMemoryControllerMaximumBandwidth(Mb/s)Important:Verifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.
xilinx.
comXAZynqUltraScale+XAZynq-7000XASpartan-7XAKintex-7XAArtix-7XASpartan-6CoreVoltage-1I/Q(0.
85V)-L1(0.
72V)-1I(1.
0V)-1Q(1.
0V)-1I(1.
0V)-1Q(1.
0V)-2I(1.
0V)-1Q(1.
0V)-1I(1.
0V)-1Q(1.
0V)-2I(1.
0V)-2,-3(1.
2V)PLPSPLPSPLPSPLPSDDR42400240021332400DDR3213321331866213380010666671066667667800800800667800800DDR3L18661866160018666671066–1066667667800800667N/A800–DDR2––––667800533800667667800667667533800400DDR355–355400LPDDR4–2400–2400LPDDR31600160016001600LPDDR2––––533800400800–––533––––LPDDR400Copyright2018–2020XilinxDS894,XAZynqUltraScale+MPSoCDataSheet:OverviewDS925,ZynqUltraScale+MPSoCDataSheet:DCandACSwitchingCharacteristicsDS180,7SeriesFPGAsDataSheet:OverviewDS197,XAArtix-7FPGAsDataSheet:OverviewDS181,Artix-7FPGAsDataSheet:DCandACSwitchingCharacteristicsDS188,XAZynq-7000SoCDataSheet:OverviewDS187,Zynq-7000SoCDataSheet:DCandACSwitchingCharacteristicsDS175,XAKintex-7FPGADataSheet:OverviewDS189,Spartan-7FPGAsDataSheet:DCandACSwitchingCharacteristicsDS170,XASpartan-6AutomotiveFPGAFamilyDataSheet:OverviewDS162,Spartan-6FPGAsDataSheet:DCandACSwitchingCharacteristicsUG1085,ZynqUltraScale+MPSoCTechnicalReferenceManualUG1213,ZynqMigrationGuide–Zynq-7000APSoCtoZynqUltraScale+MPSoCDevicesFormoreinformationonAutomotiveproducts,gotohttps://www.
xilinx.
com/applications/automotive.
htmlPage13Important:Verifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.
xilinx.
comReferencesXMP106(v1.
6)
2GHzDual-coreArmCortex-R5MPCoreupto500MHz103K–653SystemLogicCellsMali-400MP2upto600MHz240–2,928SeparateVoltageonPS&PL,Full(PL+PS)/Fullpowerdomain/Lowpowerdomain/BatteryPowerDomains(PS)-1,-1L(1)AEC-Q100,ProductionPartApprovalProcessx32/x64:DDR4,LPDDR4,DDR3,DDR3L,LPDDR3w/ECCNotes:1.
ZU11EGandZU7EV-1Lspeedgradesarenotsupported.
Copyright2018–2020XilinxXAKintex-7Page3AutomotiveDeviceComparisonXAArtix-7XASpartan-6XASpartan-7CoreVoltage1.
0V1.
2V1.
0VLogicCell12K–101K3K–74K6K–102KDSPSlices40–2408–13210–160TotalBlockRAM(K)720–4,860216–3,096180–4,320PCIe1@Gen2uptox40–1@Gen1x10AutomotiveStandardsAEC-Q100,ProductionPartApprovalProcessAEC-Q100,ProductionPartApprovalProcessAEC-Q100,ProductionPartApprovalProcessSerialTransceivers2–40–40SpeedGrades-1,-2-2,-3-1,-2CMTs3–62–62–81.
0V162K6002,1881@Gen2uptox8AEC-Q100,ProductionPartApprovalProcess8-18Copyright2018–2020XilinxPage4XAZynqUltraScale+MPSoCs1.
Forfullpartnumberdetails,seetheOrderingInformationsectioninDS891,ZynqUltraScale+MPSoCOverview.
2.
XAZU11EGandXAZU7EV-1Lspeedgradesarenotsupported.
DeviceName(1)XAZU2EGXAZU3EGXAZU11EGXAZU4EVXAZU5EVXAZU7EVProcessingSystem(PS)ApplicationProcessorUnitProcessorCoreQuad-coreArmCortex-A53MPCoreupto1.
2GHzMemoryw/ECCL1Cache32KBI/Dpercore,L2Cache1MB,on-chipMemory256KBReal-TimeProcessorUnitProcessorCoreDual-coreArmCortex-R5MPCoreupto500MHzMemoryw/ECCL1Cache32KBI/Dpercore,TightlyCoupledMemory128KBpercoreGraphic&VideoAccelerationGraphicsProcessingUnitMali-400MP2upto600MHzMemoryL2Cache64KBExternalMemoryDynamicMemoryInterfacex32/x64:DDR4,LPDDR4,DDR3,DDR3L,LPDDR3withECCStaticMemoryInterfacesNAND,2xQuad-SPIConnectivityHigh-SpeedConnectivityPCIeGen2x4,2xUSB3.
0,SATA3.
1,DisplayPort,4xTri-modeGigabitEthernetGeneralConnectivity2xUSB2.
0,2xSD/SDIO/eMMC,2xUART,2xCAN2.
0B,2xI2C,2xSPI,4x32bGPIOIntegratedBlockFunctionalityPowerManagementFull/Low/PL/BatteryPowerDomainsSecurityRSA,AES,andSHAAMS-SystemMonitor10-bit,1MSPS-Temperature,Voltage,andCurrentMonitorPStoPLInterface12x32/64/128bAXIPortsProgrammableLogic(PL)ProgrammableFunctionalitySystemLogicCells(K)103154653192256504CLBFlip-Flops(K)94141597176234461CLBLUTs(K)477129988117230MemoryMax.
DistributedRAM(Mb)1.
21.
89.
12.
63.
56.
2BlockRAMBlocks150216600128144312TotalBlockRAM(Mb)5.
37.
621.
14.
55.
111.
0UltraRAMBlocks--80486496UltraRAM(Mb)--22.
514.
018.
027.
0ClockingClockManagementTiles(CMTs)338448IntegratedIPDSPSlices24036029287281,2481,728VCU---111PCIExpressGen3x16--4222AMS-SystemMonitor111111TransceiversGTH12.
5Gb/sTransceivers--32161616SpeedGradesI-Grade(2)-1(0.
85V),-L1(0.
72V)-1(0.
85V)-1(0.
85V),-L1(0.
72V)-1(0.
85V)Q-Grade-1(0.
85V)-1(0.
85V)-1(0.
85V)Copyright2018–2020XilinxPkgFootprint(2)Dimensions(mm)XAZU2EGXAZU3EGXAZU11EGSBVA484(3)19x19170,24,584,0170,24,584,0SFVA625(3)21x21170,24,1564,0170,24,1564,0SFVC784(3)23x23214,96,1564,0214,96,1564,0FFVF151740x40214,48,4164,32Page5Important:Verifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.
xilinx.
comXAZynqUltraScale+MPSoCsPSI/Os(1),3.
3VHigh-Density(HD)I/O,1.
8VHigh-Performance(HP)I/OsPS-GTR6Gb/s,GTH12.
5Gb/sNotes:1.
PSI/OisacombinationofPSMIOandPSDDRIO.
2.
Forfullpartnumberdetails,seetheOrderingInformationsectioninDS891,ZynqUltraScale+MPSoCOverview.
3.
Thesepackagesareonlyofferedin0.
8mmballpitch.
PkgFootprint(2)Dimensions(mm)XAZU4EVXAZU5EVXAZU7EVSBVA484(3)19x19SFVA625(3)21x21SFVC784(3)23x23214,96,1564,4214,96,1564,4FBVB90031x31214,48,1564,16Copyright2018–2020XilinxPage6XAZynq-7000SoCsNotes:1.
AllpackageslistedarePb-free.
2.
HR=HighRangeI/OwithsupportforI/Ovoltagefrom1.
2Vupto3.
3V.
3.
HP=HighPerformanceI/OwithsupportforI/Ovoltagefrom1.
2Vto1.
8V.
4.
PSI/OincludesuserI/OandDDRI/O.
DeviceName(1)XA7Z010XA7Z020XA7Z030ProcessingSystem(PS)ApplicationProcessorUnitProcessorCoreDualArmCortex-A9MPCoreupto667MHzProcessorExtensionNEONSIMDEngineandSingle/DoublePrecisionFloatingPointUnitperProcessorMemoryL1Cache32KBI/DperCoreL2Cache512KBOn-ChipMemory256KBExternalMemoryDynamicMemoryInterfacex32/x64:DDR3,DDR3L,DDR2,LPDDR2StaticMemoryInterfacesNAND,NOR,2xQuad-SPIConnectivityHigh-SpeedConnectivity2xTri-modeGigabitEthernetGeneralConnectivity2xUSB2.
0,2xSD/SDIO/eMMC,2xUART,2xCAN2.
0B,2xI2C,2xSPI,4x32bGPIOIntegratedBlockFunctionalitySecurityRSA,AES,andSHAAMS-SystemMonitor2x12-bit,1MSPS-Temperature,Voltage,andCurrentMonitorPStoPLInterface9x32/64AXIPortsProgrammableLogic(PL)ProgrammableFunctionalityXilinx7SeriesPLEquivalentArtix-7Artix-7Kintex-7LogicCells28,16085,280125,760CLBFlip-Flops35,300106,400157,200CLBLUTs17,60053,30078,600MemoryTotalBlockRAM(KB)(#36KbBlocks)240(60)560(140)1,060(265)IntegratedIPDSPSlices80220400PeakDSPPerformance100GMACs276GMACs593GMACsPCIExpress--Gen2x4AMS/XADCAESandSHA256bDecryptionandAuthenticationforSecureProgrammableConfigurationSpeedGradesI-Grade-1Q-Grade-1Package(1)Size(mm)Pitch(mm)HRI/O(2),HPI/O(3),PSI/O(4),GTXTransceiverPackageCLG22513x130.
854,0,84,0CLG40017x170.
8100,0,128,0125,0,128,0CLG48419x190.
8200,0,128,0FBV48423x231.
0100,63,128,4Copyright2018–2020XilinxPage7XAArtix-7FPGAsNotes:1.
SupportsPCIExpressBase2.
1specificationatGen1andGen2datarates.
2.
Representsthemaximumnumberoftransceiversavailable.
NotethattheCSG324devicesareavailablewithouttransceivers.
SeethePackagesectionofthistablefordetails.
3.
DevicemigrationisavailablewithintheArtix-7familyforlikepackagesbutisnotsupportedbetweenother7seriesfamilies.
TransceiverOptimizationattheLowestCostandHighestDSPBandwidth(1.
0V,0.
95V,0.
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25Gb/sMaxRate)(2)2444444SpeedGradesI-Grade-1,-2-1,-2-1,-2-1,-2-1,-2-1,-2-1,-2Q-Grade-1-1-1-1-1-1-1Package(3)Dimensions(mm)BallPitch(mm)AvailableUserI/O:3.
3VSelectIOHRI/O(GTPTransceivers)CPG23610x100.
5106(2)106(2)106(2)CPG23810x100.
5112(2)112(2)CSG32415x150.
8210(0)210(0)210(0)210(0)210(0)CSG32515x150.
8150(2)150(4)150(4)150(4)150(4)FGG48423x231.
0285(4)285(4)Copyright2018–2020XilinxPage8XAKintex-7FPGAsNotes:1.
SupportsPCIExpressBase2.
1specificationatGen1andGen2datarates.
2.
Representsthemaximumnumberoftransceiversavailable.
3.
Devicemigrationisnotsupportedbetweenother7seriesfamilies.
OptimizedforBestPrice-Performance(1.
0V,0.
95V,0.
9V)PartNumberXA7K160TLogicResourcesLogicCells162,240Slices25,350CLBFlip-Flops202,800MemoryResourcesMaximumDistributedRAM(Kb)2,188BlockRAM/FIFOw/ECC(36Kbeach)325TotalBlockRAM(Kb)11,700ClockResourcesCMTs(1MMCM+1PLL)8I/OResourcesMaximumSingle-EndedI/O400MaximumDifferentialI/OPairs192EmbeddedHardIPResourcesDSPSlices600PCIeGen2(1)1AnalogMixedSignal(AMS)/XADC1ConfigurationAES/HMACBlocks1GTXTransceivers(8.
0Gb/sMaxRate)(2)8SpeedGradesI-Grade-1Package(3)Dimensions(mm)BallPitch(mm)AvailableUserI/O:3.
3VSelectIOHRI/O,1.
8VHP1/O(GTXTransceivers)FFG67627x271.
0250,150(8)Copyright2018–2020XilinxPage9XASpartan-7FPGAsI/OOptimizationattheLowestCostandHighestPerformance-per-Watt(1.
0V)PartNumberXA7S6XA7S15XA7S25XA7S50XA7S75XA7S100LogicCells6,00012,80023,36052,16076,800102,400Slices9382,0003,6508,15112,00016,000CLBFlip-Flops7,50016,00029,20065,20096,000128,000Max.
DistributedRAM(Kb)701503136008321,100BlockRAM/FIFOw/ECC(36Kbeach)510457590120TotalBlockRAM(Kb)1803601,6202,7003,2404,320ClockMgmtTiles(1MMCM+1PLL)223588Max.
Single-EndedI/OPins100100150250400400Max.
DifferentialI/OPairs484872120192192DSPSlices102080120140160AnalogMixedSignal(AMS)/XADC001111ConfigurationAES/HMACBlocks001111I-Grade-1,-2-1,-2-1,-2-1,-2-1,-2-1,-2Q-Grade-1-1-1-1-1-1PackageDimensions(mm)BallPitch(mm)AvailableUserI/O:3.
3VSelectIOHRI/OCPGA1968x80.
5100100CSGA22513x130.
8100100150CSGA32415x150.
8150210FGGA48423x231.
0250338338FGGA67627x271.
0400400Copyright2018–2020XilinxPage10XASpartan-6FPGAsTransceiverOptimizationattheLowestCost(1.
2V)PartNumberXA6SLX4XA6SLX9XA6SLX16XA6SLX25XA6SLX45XA6SLX75XA6SLX100XA6SLX25TXA6SLX45TXA6SLX75TLogicResourcesLogicCells3,8409,15214,57924,05143,66174,637101,26224,05143,66174,637Slices6001,4302,2783,7586,82211,66215,8223,7586,82211,662CLBFlip-Flops4,80011,44018,22430,06454,57693,296126,57630,06454,57693,296MemoryResourcesMaximumDistributedRAM(Kb)7590136229401692976229401692BlockRAM(18Kbea.
)1232325211617226852116172TotalBlockRAM(Kb)2165765769362,0883,0964,8249362,0883,096ClockResourcesCMTs(2DCM+1PLL)2222466246EmbeddedHardIPResourcesMemoryControllerBlocks(Max)0222222222EndpointBlocksPCIe0000000111GTPTransceivers(3.
2Gb/sMaxRate)0000000244TotalI/OBanks4444444444MaxUserI/O132200232266320328326250296268SpeedGradesI-Grade-2,-3Q-Grade-2,-3PackageDimensions(mm)BallPitch(mm)AvailableUserI/O:3.
3VSelectIOHRI/O(GTPTransceivers)CSG22513x130.
8132(0)160(0)160(0)FTG25617x171.
0186(0)186(0)186(0)CSG32415x150.
8200(0)232(0)226(0)218(0)190(2)190(4)CSG48419x190.
8320(0)328(0)FGG48423x231.
0266(0)316(0)280(0)326(0)250(2)296(4)268(4)Copyright2018–2020XilinxPage11DeviceOrderingInformationImportant:Verifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.
xilinx.
comI=Tjfrom–40°Cto+100°C;Q=Tjfrom–40°Cto+125°CSpeedGrade-2=Mid-3=HighestXilinxAutomotiveGenerationXA7ZFamily###ValueIndex-1SpeedGrade-1=StandardFBCL:Wire-bond(.
8mm)FB:Flip-Chip(1mm)484PackagePinCountQTemperatureGrade(I,Q)VV:RoHS6/6G:RoHS6/6XilinxAutomotiveGenerationXA6SFamily###LogicCellsin1KUnits-1FGCS:Wire-bond(.
8mm)FT:Wire-bond(1mm)FG:Wire-bond(1mm)484PackagePinCountQTemperatureGrade(I,Q)GG:RoHS6/6LXLXTSub-familiesLX:LogicLXT:Logic+TransceiversProcessorSystemE:DualRPUQuadAPUSingleGPUEngineTypeG:GeneralPurposeV:VideoXilinxAutomotiveGenerationXAZUEGSpeedGrade-1=Standard-1L=LowPower-1S:Flip-Chip(.
8mm)484PackagePinCountITemperatureGrade(I,Q)ValueIndex#VV:RoHS6/6APackageDesignatorSBF:LidB:LidlessXilinxAutomotiveGenerationXA7SFamily###LogicCellsin1KUnits-1SpeedGrade-1=Standard-2=MediumFGCP:Wire-bond(.
5mm)FT:Wire-bond(1mm)CS:Wire-bond(.
8mm)FG:Wire-bond(1mm)484PackagePinCountQTemperatureGrade(I,Q)GG:RoHS6/6APackageDesignatorXilinxAutomotiveGenerationXA7###LogicCellsIn1Kunits-1SpeedGrade-1=Standard-2=MediumCPCP:Wire-bond(.
5mm)CS:Wire-bond(.
8mm)FG:Wire-bond(1mm)236PackagePinCountITemperatureGrade(I,Q)FamilyAGG:RoHS6/6XilinxAutomotiveGenerationXA7160TLogicCellsIn1Kunits-1SpeedGrade-1=StandardFFFF:Wire-bond(1mm)676PackagePinCountITemperatureGrade(I,Q)FamilyKGG:RoHS6/6Copyright2018–2020XilinxPage12ExternalMemoryControllerMaximumBandwidth(Mb/s)Important:Verifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.
xilinx.
comXAZynqUltraScale+XAZynq-7000XASpartan-7XAKintex-7XAArtix-7XASpartan-6CoreVoltage-1I/Q(0.
85V)-L1(0.
72V)-1I(1.
0V)-1Q(1.
0V)-1I(1.
0V)-1Q(1.
0V)-2I(1.
0V)-1Q(1.
0V)-1I(1.
0V)-1Q(1.
0V)-2I(1.
0V)-2,-3(1.
2V)PLPSPLPSPLPSPLPSDDR42400240021332400DDR3213321331866213380010666671066667667800800800667800800DDR3L18661866160018666671066–1066667667800800667N/A800–DDR2––––667800533800667667800667667533800400DDR355–355400LPDDR4–2400–2400LPDDR31600160016001600LPDDR2––––533800400800–––533––––LPDDR400Copyright2018–2020XilinxDS894,XAZynqUltraScale+MPSoCDataSheet:OverviewDS925,ZynqUltraScale+MPSoCDataSheet:DCandACSwitchingCharacteristicsDS180,7SeriesFPGAsDataSheet:OverviewDS197,XAArtix-7FPGAsDataSheet:OverviewDS181,Artix-7FPGAsDataSheet:DCandACSwitchingCharacteristicsDS188,XAZynq-7000SoCDataSheet:OverviewDS187,Zynq-7000SoCDataSheet:DCandACSwitchingCharacteristicsDS175,XAKintex-7FPGADataSheet:OverviewDS189,Spartan-7FPGAsDataSheet:DCandACSwitchingCharacteristicsDS170,XASpartan-6AutomotiveFPGAFamilyDataSheet:OverviewDS162,Spartan-6FPGAsDataSheet:DCandACSwitchingCharacteristicsUG1085,ZynqUltraScale+MPSoCTechnicalReferenceManualUG1213,ZynqMigrationGuide–Zynq-7000APSoCtoZynqUltraScale+MPSoCDevicesFormoreinformationonAutomotiveproducts,gotohttps://www.
xilinx.
com/applications/automotive.
htmlPage13Important:Verifyalldatainthisdocumentwiththedevicedatasheetsfoundatwww.
xilinx.
comReferencesXMP106(v1.
6)
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