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XSABoardV1.
1,V1.
2UserManualHowtoinstall,test,anduseyournewXSABoardRELEASEDATE:6/23/2005Copyright2001-2005byXEngineeringSoftwareSystemsCorporation.
AllXS-prefixproductdesignationsaretrademarksofXESSCorp.
AllXC-prefixproductdesignationsaretrademarksofXilinx.
Allrightsreserved.
Nopartofthispublicationmaybereproduced,storedinaretrievalsystem,ortransmitted,inanyformorbyanymeans,electronic,mechanical,photocopying,recording,orotherwise,withoutthepriorwrittenpermissionofthepublisher.
PrintedintheUnitedStatesofAmerica.
XSABOARDV1.
1,V1.
2USERMANUAL1TableofContentsTableofContents2Preliminaries4GettingHelp!
4Takenotice!
4PackingList5Installation.
6InstallingtheXSTOOLSUtilitiesandDocumentation.
6ApplyingPowertoYourXSABoard.
6Usinga9VDCwall-mountpowersupply6PoweringThroughthePS/2Connector.
6SolderlessProtoboardInstallation.
6ConnectingaPCtoYourXSABoard8ConnectingaVGAMonitortoYourXSABoard.
8ConnectingaMouseorKeyboardtoYourXSABoard.
8InsertingtheXSABoardintoanXStendBoard.
9SettingtheJumpersonYourXSABoard9TestingYourXSABoard.
10SettingtheXSABoardClockOscillatorFrequency.
11Programming12DownloadingDesignsintotheFPGAandCPLDofYourXSABoard.
.
.
.
12DownloadingUsingGXSLOAD.
12DownloadingUsingXilinxiMPACT.
14StoringNon-VolatileDesignsinYourXSABoard.
15DownloadingandUploadingDatatotheSDRAMinYourXSABoard.
.
.
17Programmer'sModels19XSABOARDV1.
1,V1.
2USERMANUAL2XSABoardOrganization.
19Programmablelogic:Spartan-IIFPGAandXC9572XLCPLD20100MHzProgrammableOscillator.
20SynchronousDRAM21FlashRAM.
22Seven-SegmentLED.
24Four-PositionDIPSwitch.
24PS/2Port.
24Pushbutton.
25VGAMonitorInterface25ParallelPortInterface.
25PrototypingHeader29XSAPinConnections.
31XSASchematics.
32XSABOARDV1.
1,V1.
2USERMANUAL31PreliminariesGettingHelp!
Herearesomeplacestogethelpifyouencounterproblems:Ifyoucan'tgettheXSABoardhardwaretowork,sendane-mailmessagedescribingyourproblemtohelp@xess.
comorsubmitaproblemreportathttp://www.
xess.
com/help.
html.
Ourwebsitealsohasanswerstofrequently-asked-questions,exampledesigns,applicationnotesandtutorialsfortheXSBoards,aplacetosign-upforouremailforumwhereyoucanpostquestionstootherXSBoardusers.
Ifyoucan'tgetyourXilinxWebPACKsoftwaretoolsinstalledproperly,sendane-mailmessagedescribingyourproblemtohotline@xilinx.
comorchecktheirwebsiteathttp://www.
xilinx.
com/support/support.
htm.
IfyouneedhelpusingtheWebPACKsoftwaretocreatedesignsforyourXSABoard,thencheckoutthistutorial.
Takenotice!
!
TheXSABoardrequiresanexternalpowersupplytooperate!
ItdoesnotdrawpowerthroughthedownloadingcablefromthePCparallelport.
Ifyouareconnectinga9VDCpowersupplytoyourXSABoard,pleasemakesurethecenterterminaloftheplugispositiveandtheoutersleeveisnegative.
DonotpoweryourXSABoardwithabattery!
ThiswillnotprovideenoughcurrenttoinsurereliableoperationoftheXSABoard.
XSABOARDV1.
1,V1.
2USERMANUAL4PackingListHereiswhatyoushouldhavereceivedinyourpackage:anXSABoard;a6'cablewitha25-pinmaleconnectoroneachend;anXSTOOLSCDROMwithsoftwareutilitiesanddocumentationforusingtheXSABoard.
XSABOARDV1.
1,V1.
2USERMANUAL52InstallationInstallingtheXSTOOLSUtilitiesandDocumentationXilinxcurrentlyprovidestheWebPACKtoolsforprogrammingtheirCPLDsandSpartan-IIFPGAs.
TheXESSCDROMcontainsaversionofWebPACKthatwillgeneratebitstreamconfigurationfilescompatiblewithyourXSABoard.
YoucanalsodownloadthemostcurrentversionoftheWebPACKtoolsfromtheXilinxwebsite.
.
Inaddition,XESSCorp.
providestheXSTOOLSutilitiesforinterfacingaPCtoyourXSABoard.
RuntheSETUP.
EXEprogramontheXSTOOLSCDROMtoinstalltheseutilities.
ApplyingPowertoYourXSABoardYoucanuseyourXSABoardinthreeways,distinguishedbythemethodyouusetoapplypowertotheboard.
OnlyuseoneofthesemethodstopoweryourXSABoard!
Supplyingpowerfrommultiplesourcescandamagetheboardand/orpowersupplies.
Usinga9VDCwall-mountpowersupplyYoucanuseyourXSABoardallbyitselftoexperimentwithlogicdesigns.
JustplacetheXSABoardonanon-conductingsurfaceasshowninFigure1.
ThenapplypowertojackJ5oftheXSABoardfroma9VDCwall-mountpowersupplywitha2.
1mmfemale,center-positiveplug.
(SeeFigure2forthelocationofjackJ5onyourXSABoard.
)Theon-boardvoltageregulationcircuitrywillcreatethevoltagesrequiredbytherestoftheXSABoardcircuitry.
Becareful!
!
ThevoltageregulatorsontheXSABoardwillbecomehot.
Attachaheatsinktothemifnecessary.
PoweringThroughthePS/2ConnectorYoucanuseyourXSABoardwithalaptopPCbyconnectingaPS/2male-to-malecablefromthePS/2portofthelaptoptotheJ4connector.
Youmustalsohaveashuntacrosspins1and2ofjumperJ7.
Theon-boardvoltageregulationcircuitrywillcreatethevoltagesrequiredbytherestoftheXSABoardcircuitry.
ManyPS/2portscannotsupplymorethan0.
5Asolarge,fastFPGAdesignsmaynotworkwhenusingthispowersource!
SolderlessProtoboardInstallationThetworowsofpinsfromyourXSABoardcanbepluggedintoasolderlessprotoboardwithholesspacedat0.
1"intervals.
(OneoftheA.
C.
E.
protoboardsfrom3Misagoodchoice.
)Oncepluggedin,manyofthepinsoftheFPGAareaccessibletoothercircuitsXSABOARDV1.
1,V1.
2USERMANUAL6ontheprotoboard.
(ThenumbersprintednexttotherowsofpinsonyourXSABoardcorrespondtothepinnumbersoftheFPGA.
)PowercanstillbesuppliedtoyourXSABoardthoughjackJ5,orpowercanbeapplieddirectlythroughseveralpinsontheundersideoftheboard.
Justconnect+5V,+3.
3V,+2.
5VandgroundtothepinsofyourXSABoardlistedinTable1.
Table1:PowersupplypinsfortheXSABoard.
VoltagePinNote+5V2+3.
3V54RemovetheshuntfromjumperJ7ifyouwishtouseyourown+3.
3Vsupply.
LeavetheshuntonjumperJ7togeneratethe+3.
3Vsupplyfromthe+5Vsupply.
+2.
5V22RemovetheshuntfromjumperJ2ifyouwishtouseyourown+2.
5Vsupply.
LeavetheshuntonjumperJ2togeneratethe+2.
5Vsupplyfromthe+3.
3Vsupply.
GND52ParallelPortPS/29VDCVGAFigure1:ExternalconnectionstotheXSABoard.
XSABOARDV1.
1,V1.
2USERMANUAL7J6J5J9J2J10J3J4SW2J8J7Spartan-IIFPGACPLDFlashRAMSDRAMPushbuttonPushbutton100MHzOsc.
ExternalClockInput+5V+3.
3V+2.
5VGNDVGAMonitorPCParallelPort9VDCPowerSupplyPS/2MouseorKeyboardU10U15SW1Figure2:ArrangementofcomponentsontheXSABoard.
ConnectingaPCtoYourXSABoardThe6'DB25male-to-malecableincludedwithyourXSABoardconnectsittoaPC.
OneendofthecableattachestotheparallelportonthePCandtheotherconnectstothefemaleDB-25connector(J8)atthetopoftheXSABoardasshowninFigure1.
ConnectingaVGAMonitortoYourXSABoardYoucandisplayimagesonaVGAmonitorbyconnectingittothe15-pinJ3connectoratthebottomofyourXSABoard(seeFigure1).
YouwillhavetocreateaVGAdrivercircuitforyourXSABoardtoactuallydisplayanimage.
SeethissectionfordetailsontheVGAportcircuitryandcreatingaVGAdisplaycircuit.
ConnectingaMouseorKeyboardtoYourXSABoardYoucanacceptinputsfromakeyboardormousebyconnectingittothePS/2portatthebottomofyourXSABoard(seeFigure1).
YouwillhavetocreateakeyboardormouseXSABOARDV1.
1,V1.
2USERMANUAL8interfacecircuittoactuallyreceiveinformationonkeystrokesormousemovements.
SeethissectionfordetailsonthePS/2portcircuitryandcreatingakeyboardinterface.
InsertingtheXSABoardintoanXStendBoardIfyoupurchasedtheoptionalXST-2.
xBoard,thentheXSABoardisinsertedasshownbelow.
RefertotheXST-2.
xBoardManualformoredetails.
SettingtheJumpersonYourXSABoardThedefaultjumpersettingsshowninTable2configureyourXSABoardforuseinalogicdesignenvironment.
Youwillneedtochangethejumpersettingsonlyifyouare:downloadingFPGAbitstreamstoyourXSABoardusingtheXilinxiMPACTsoftware;reprogrammingtheclockfrequencyonyourXSABoard(seepage11);changingthepowersourcesfortheXSAsupplyvoltages.
XSABOARDV1.
1,V1.
2USERMANUAL9Table2:JumpersettingsforXSABoards.
JumperSettingPurposeOn(default)Ashuntshouldbeinstalledifthe+2.
5Vsupplyvoltageisderivedfromthe+3.
3Vsupply.
J2OffTheshuntshouldberemovedifthe+2.
5Vsupplyvoltageisappliedfromanexternalsourcethroughpin22oftheXSABoard(labeled"+2.
5V"atthelowerright-handcorneroftheboard).
1-2(set)Theshuntshouldbeinstalledonpins1and2(set)whensettingthefrequencyoftheprogrammableoscillator.
J62-3(osc)(default)Theshuntshouldbeinstalledonpins2and3(osc)duringnormaloperationswhentheprogrammableoscillatorisgeneratingaclocksignal.
1-2(default)Theshuntshouldbeinstalledonpins1and2ifthe+3.
3Vsupplyvoltageisderivedfromthe+5Vsupply.
J72-3Theshuntshouldbeinstalledonpins2and3ifthe+3.
3Vsupplyvoltageisderivedfromthe9VDCsupplyappliedthroughjackJ5.
1-2(xi)Theshuntshouldbeinstalledonpins1and2(xi)iftheXSABoardistobedownloadedusingtheXilinxiMPACTsoftware.
J92-3(xs)(default)Theshuntshouldbeinstalledonpins2and3(xs)iftheXSABoardistobedownloadedusingtheXESSGXSLOADsoftware.
J10N/AThisisaheaderthatprovidesaccesstothe+5VandGNDreferencesontheboard.
Noshuntshouldbeplacedonthisheader.
TestingYourXSABoardOnceyourXSABoardisinstalledandthejumpersareintheirdefaultconfiguration,youcantesttheboardusingtheGUI-basedGXSTESTutilityasfollows.
YoustartGXSTESTbyclickingontheiconplacedonthedesktopduringtheXSTOOLSinstallation.
Thisbringsupthewindowshownbelow.
NextyouselecttheparallelportthatyourXSABoardisconnectedtofromthePortpulldownlist.
GXSTESTstartswithparallelportLPT1asthedefault,butyoucanalsoselectLPT2orLPT3dependingupontheconfigurationofyourPC.
Afterselectingtheparallelport,youselecteithertheXSA-50orXSA-100itemintheBoardTypepulldownlist.
ThenclickontheTESTbuttontostartthetestingprocedure.
GXSTESTwillconfiguretheFPGAtoperformatestprocedureonyourXSABoard.
WithinthirtysecondsyouwillseeaOdisplayedontheLEDdigitifthetestcompletessuccessfully.
OtherwiseanEwillbedisplayedifthetestfails.
AstatuswindowwillalsoappearonyourPCscreeninformingyouofthesuccessorfailureofthetest.
XSABOARDV1.
1,V1.
2USERMANUAL10IfyourXSABoardfailsthetest,youwillbeshownachecklistofcommoncausesforfailure.
Ifnoneofthesecausesappliestoyoursituation,thentesttheXSABoardusinganotherPC.
Inourexperience,99.
9%ofallproblemsareduetotheparallelport.
Ifyoucannotgetyourboardtopassthetestevenaftertakingthesesteps,thencontactXESSCorpforfurtherassistance.
AsaresultoftestingtheXSABoard,theCPLDisprogrammedwiththestandardparallelportinterfacefoundinthedwnldpar.
svfbitstreamfilelocatedwithintheXSTOOLS\XSAfolder.
ThisisthestandardinterfacethatshouldbeloadedintotheCPLDwhenyouwanttouseitwiththeGXSLOADutility.
SettingtheXSABoardClockOscillatorFrequencyTheXSABoardhasa100MHzprogrammableoscillator(aDallasSemiconductorDS1075Z-100).
The100MHzmasterfrequencycanbedividedbyfactorsof1,2,.
.
.
upto2052togetclockfrequenciesof100MHz,50MHz,.
.
.
downto48.
7KHz,respectively.
ThedividedfrequencyissenttotherestoftheXSABoardcircuitryasaclocksignal.
Thedivisorisstoredinnon-volatilememoryintheoscillatorchipsoitwillresumeoperationatitsprogrammedfrequencywheneverpowerisappliedtotheXSABoard.
YoucanstoreaparticulardivisorintotheoscillatorchipbyusingtheGUI-basedGXSSETCLKasfollows.
YoustartGXSSETCLKbyclickingontheiconplacedonthedesktopduringtheXSTOOLSinstallation.
Thisbringsupthewindowshownbelow.
YournextstepistoselecttheparallelportthatyourXSABoardisconnectedtofromthePortpulldownlist.
ThenselecteitherXSA-50orXSA-100intheBoardTypepulldownlist.
Nextyouenteradivisorbetween1and2052intotheDivisortextboxandthenclickontheSETbutton.
ThenfollowthesequenceofinstructionsgivenbyXSSETCLKformovingshuntsandremovingandrestoringpowerduringtheoscillatorprogrammingprocess.
Atthecompletionoftheprocess,thenewfrequencywillbeprogrammedintotheDS1075.
Anexternalclocksignalcanbesubstitutedfortheinternal100MHzoscillatoroftheDS1075.
CheckingtheExternalClockcheckboxwillenablethisfeatureintheprogrammableoscillatorchip.
Ifthisoptionisselected,youarethenresponsibleforprovidingtheexternalclocktotheXSABoardthroughpin64(labeled"CLK"attheupperleft-handcorneroftheboard).
XSABOARDV1.
1,V1.
2USERMANUAL113ProgrammingThissectionwillshowyouhowtodownloadalogicdesignsintotheFPGAandCPLDofyourXSABoardandhowtodownloadanduploaddatatoandfromtheSDRAMandFlashdevicesontheboard.
DownloadingDesignsintotheFPGAandCPLDofYourXSABoardDownloadingUsingGXSLOADDuringthedevelopmentandtestingphases,youwillusuallyconnecttheXSABoardtotheparallelportofaPCanddownloadyourcircuiteachtimeyoumakechangestoit.
YoucandownloadaSpartan-IIFPGAdesignintoyourXSABoardusingtheGXSLOADutilityasfollows.
YoustartGXSLOADbyclickingontheiconplacedonthedesktopduringtheXSTOOLSinstallation.
Thisbringsupthewindowshownbelow.
ThenselectthetypeofXSBoardyouareusingandtheparallelporttowhichitisconnectedasfollows.
XSABOARDV1.
1,V1.
2USERMANUAL12Aftersettingtheboardtypeandparallelport,youcandownload.
BITor.
SVFfilestotheSpartan-IIFPGAorXC9572XLCPLDonyourXSABoardsimplybydraggingthemtotheFPGA/CPLDareaoftheGXSLOADwindowasshownbelow.
Onceyoureleasetheleftmousebuttonanddropthefile,thehighlightedfilenameappearsintheFPGA/CPLDareaandtheLoadbuttonintheGXSLOADwindowisenabled.
ClickingontheLoadbuttonwillbeginsendingthehighlightedfiletotheXSABoardthroughtheparallelportconnection.
.
BITfilescontainconfigurationbitstreamsthatareloadedintotheFPGAwhile.
SVFfileswillgototheCPLD.
GXSLOADwillrejectanynon-downloadablefiles(oneswithasuffixotherthan.
BITor.
SVF).
Duringthedownloadingprocess,GXSLOADwilldisplaythenameofthefileandtheprogressofthecurrentdownload.
XSABOARDV1.
1,V1.
2USERMANUAL13Youcandrag&dropmultiplefilesintotheFPGA/CPLDarea.
Clickingyourmouseonafilenamewillhighlightthenameandselectitfordownloading.
Onlyonefileatatimecanbeselectedfordownloading.
Double-clickingthehighlightedfilewilldeselectitsonofilewillbedownloadedDoingthisdisablestheLoadbutton.
DownloadingUsingXilinxiMPACTYoucanusetheXilinxiMPACTsoftwaretodownloadbitstreamstotheXSABoard.
TheiMPACTprogrammingtooldownloadsbitstreamsthroughtheJTAGinterfaceoftheFPGAsoweneedtochangetheparallelportinterfacebyreprogrammingtheCPLD.
Drag&dropthep3jtag.
svffilefromtheXSTOOLS\XSA\50folderintotheFPGA/CPLDpaneoftheGXSLOADwindow.
ThenclickontheLoadbuttonandtheCPLDwillbereprogrammedinlessthanaminute.
ThenmovetheshuntonjumperJ9fromtheXStotheXIposition.
AtthispointyoucanstartiMPACTanditwillbelieveitisconnectedtotheXSABOARDV1.
1,V1.
2USERMANUAL14XSABoardthroughaXilinxParallelCableIIIinboundary-scanmode.
FollowtheinstructionsforiMPACTtodownloadbitstreamstotheFPGA.
NotethattheCPLDonlyneedstobereprogrammedoncetosupportiMPACTbecauseitretainsitsconfigurationevenwhenpowerisremovedfromtheboard.
(IfyouwanttogobacktousingtheGXSLOADprogrammingutility,justmustmovetheshuntonJ9backtotheXSpositionanddownloadtheXSTOOLS\XSA\50\dwnldpar.
svffileintotheCPLD.
)StoringNon-VolatileDesignsinYourXSABoardTheSpartan-IIFPGAontheXSABoardstoresitsconfigurationinanon-chipSRAMwhichiserasedwheneverpowerisremoved.
Onceyourdesignisfinished,youmaywanttostorethebitstreaminthe256-KByteFlashdeviceontheXSABoardwhichconfigurestheFPGAforoperationassoonaspowerisapplied.
BeforedownloadingtotheFlash,theFPGA.
BITfilemustbeconvertedintoa.
EXOor.
MCSformatusingoneofthefollowingcommands:promgen–u0file.
bit–pexo–s256promgen–u0file.
bit–pmcs–s256Inthecommandsshownabove,thebitstreaminthefile.
bitfileistransformedintoan.
EXOor.
MCSfileformatstartingataddresszeroandproceedingupwarduntilanupperlimitof256KBytesisreached.
BeforeattemptingtoprogramtheFlash,youmustplaceallfourDIPswitchesintotheOFFposition!
Afterthe.
EXOor.
MCSfileisgenerated,itisloadedintotheFlashdevicebydraggingitintotheFlash/EEPROMareaandclickingontheLoadbutton.
Thisactivatesthefollowingsequenceofsteps:1.
TheentireFlashdeviceiserased.
2.
TheCPLDontheXSABoardisreprogrammedtocreateaninterfacebetweentheFlashdeviceandthePCparallelport.
(Thisinterfaceisstoredinthefintf.
svfbitstreamfilelocatedwithintheXSTOOLS\XSAfolder.
)3.
Thecontentsofthe.
EXOor.
MCSfilearedownloadedintotheFlashthroughtheparallelport.
4.
TheCPLDisreprogrammedtocreateacircuitthatconfigurestheFPGAwiththecontentsoftheFlashwhenpowerisappliedtotheXSABoard.
(Thisconfigurationloaderisstoredinthefcnfg.
svfbitstreamfilelocatedwithintheXSTOOLS\XSAfolder.
)MultiplefilescanbestoredintheFlashdevicejustbydraggingthemintotheFlash/EEPROMarea,highlightingthefilestobedownloadedandclickingtheLoadbutton.
(NotethatanythingpreviouslystoredintheFlashwillbeerasedbyeachnewdownload.
)XSABOARDV1.
1,V1.
2USERMANUAL15ThisisusefulifyouneedtostoreinformationintheFlashinadditiontotheFPGAbitstream.
Filesareselectedandde-selectedfordownloadingjustbyclickingontheirnamesintheFlash/EEPROMarea.
TheaddressrangesofthedataineachfileshouldnotoverlaporthiswillcorruptthedatastoredintheFlashdevice!
YoucanalsoexaminethecontentsoftheFlashdevicebyuploadingittothePC.
TouploaddatafromanaddressrangeintheFlash,typetheupperandlowerboundsoftherangeintotheHighAddressandLowAddressfieldsbelowtheFlash/EEPROMarea,andselecttheformatinwhichyouwouldliketostorethedatausingtheUploadFormatpulldownlist.
Thenclickonthefileiconanddrag&dropitintoanyfolder.
Thisactivatesthefollowingsequenceofsteps:1.
TheCPLDontheXSABoardisreprogrammedtocreateaninterfacebetweentheFlashdeviceandthePCparallelport.
2.
TheFlashdatabetweenthehighandlowaddresses(inclusive)isuploadedthroughtheparallelport.
3.
TheuploadeddataisstoredinafilenamedFLSHUPLDwithanextensionthatreflectsthefileformat.
Theuploadeddatacanbestoredinthefollowingformats:MCS:Intelhexadecimalfileformat.
Thisisthesameformatgeneratedbythepromgenutilitywiththe–pmcsoption.
HEX:IdenticaltoMCSformat.
EXO-16:MotorolaS-recordformatwith16-bitaddresses(suitablefor64KByteuploadsonly).
EXO-24:MotorolaS-recordformatwith24-bitaddresses.
Thisisthesameformatgeneratedbythepromgenutilitywiththe–pexooption.
EXO-32:MotorolaS-recordformatwith32-bitaddresses.
XSABOARDV1.
1,V1.
2USERMANUAL16XESS-16:XESShexadecimalformatwith16-bitaddresses.
(Thisisasimplifiedfileformatthatdoesnotusechecksums.
)XESS-24:XESShexadecimalformatwith24-bitaddresses.
XESS-32:XESShexadecimalformatwith32-bitaddresses.
AfterthedataisuploadedfromtheFlash,theCPLDontheXSABoardisleftwiththeFlashinterfaceprogrammedintoit.
YouwillneedtoreprogramtheCPLDwitheithertheparallelportorFlashconfigurationcircuitbeforetheboardwillfunctionagain.
TheCPLDconfigurationbitstreamsarestoredinthefollowingfiles:XSTOOLS\XSA\dwnldpar.
svf:Drag&dropthisfileintotheFPGA/CPLDareaandclickontheLoadbuttontoputtheXSAinamodewhereitwillconfiguretheFPGAthroughtheparallelport.
XSTOOLS\XSA\fcnfg.
svf:Drag&dropthisfileintotheFPGA/CPLDareaandclickontheLoadbuttontoputtheXSAinamodewhereitwillconfiguretheFPGAwiththecontentsoftheFlashdeviceuponpower-up.
DownloadingandUploadingDatatotheSDRAMinYourXSABoardTheXSA-100Boardcontainsa16-MBytesynchronousDRAM(8Mx16SDRAM)whosecontentscanbedownloadedanduploadedbyGXSLOAD.
(TheXSA-50hasan8-MByteSDRAMorganizedas4Mx16.
)ThisisusefulforinitializingtheSDRAMwithdataforusebytheFPGAandthenreadingtheSDRAMcontentsaftertheFPGAhasoperateduponit.
TheSDRAMisloadedwithdatabydragging&droppingoneormore.
EXO,.
MCS,.
HEX,and/or.
XESfilesintotheRAMareaoftheGXSLOADwindowandthenclickingontheLoadbutton.
Thisactivatesthefollowingsequenceofsteps:1.
TheSpartan-IIFPGAontheXSABoardisreprogrammedtocreateaninterfacebetweentheRAMdeviceandthePCparallelport.
(Thisinterfaceisstoredintheram100.
bitorram50.
bitbitstreamfilelocatedwithintheXSTOOLS\XSAfolder.
TheCPLDmusthavepreviouslybeenloadedwiththedwnldpar.
svffilefoundinthesamefolder.
)2.
Thecontentsofthe.
EXO,.
MCS,.
HEXor.
XESfilesaredownloadedintotheSDRAMthroughtheparallelport.
Thedatainthefileswilloverwriteeachotheriftheiraddressrangesoverlap.
3.
IfanyfileishighlightedintheFPGA/CPLDarea,thenthisbitstreamisloadedintotheFPGAorCPLDontheXSABoard.
OtherwisetheFPGAremainsconfiguredasaninterfacebetweenthePCandtheSDRAM.
YoucanalsoexaminethecontentsoftheSDRAMdevicebyuploadingittothePC.
TouploaddatafromanaddressrangeintheSDRAM,typetheupperandlowerboundsoftherangeintotheHighAddressandLowAddressfieldsbelowtheRAMarea,andselecttheformatinwhichyouwouldliketostorethedatausingtheUploadFormatpulldownlist.
Thenclickonthefileiconanddrag&dropitintoanyfolder.
Thisactivatesthefollowingsequenceofsteps:XSABOARDV1.
1,V1.
2USERMANUAL171.
TheSpartan-IIFPGAontheXSABoardisreprogrammedtocreateaninterfacebetweentheRAMdeviceandthePCparallelport.
(Thisinterfaceisstoredintheram100.
bitorram50.
bitbitstreamfilelocatedwithintheXSTOOLS\XSAfolder.
)2.
TheSDRAMdatabetweenthehighandlowaddresses(inclusive)isuploadedthroughtheparallelport.
3.
TheuploadeddataisstoredinafilenamedRAMUPLDwithanextensionthatreflectsthefileformat.
The16-bitdatawordsintheSDRAMaremappedintotheeight-bitdataformatofthe.
HEX,.
MCS,.
EXOand.
XESfilesusingaBigEndianstyle.
Thatis,the16-bitwordataddressNintheSDRAMisstoredintheeight-bitfilewiththeuppereightbitsatlocation2Nandthelowereightbitsatlocation2N+1.
Thisbyte-orderingappliesforbothRAMuploadsanddownloads.
XSABOARDV1.
1,V1.
2USERMANUAL184Programmer'sModelsThissectiondescribesthevarioussectionsoftheXSABoardandshowshowtheI/OoftheFPGAandCPLDareconnectedtotherestofthecircuitry.
Theschematicswhichfollowarelessdetailedsoastosimplifythedescriptions.
Pleaserefertothecompleteschematicsattheendofthisdocumentifyouneedmoredetails.
XSABoardOrganizationTheXSABoardcontainsthefollowingcomponents:XC2S50orXC2S100Spartan-IIFPGA:ThisisthemainrepositoryofprogrammablelogicontheXSABoard.
XC9572XLCPLD:ThisCPLDmanagestheinterfacebetweenthePCparallelportandtherestoftheXSABoard.
Osc:AprogrammableoscillatorgeneratesthemasterclockfortheXSABoard.
Flash:A128or256-KByteFlashdeviceprovidesnon-volatilestoragefordataandconfigurationbitstreams.
SDRAM:An8or16-MByteSDRAMprovidesvolatiledatastorageaccessiblebytheFPGA.
LED:Aseven-segmentLEDallowsvisiblefeedbackastheXSABoardoperates.
DIPswitch:Afour-positionDIPswitchpassessettingstotheXSABoardorcontrolstheupperaddressbitsoftheFlashdevice.
Pushbutton:AsinglepushbuttonsendsmomentarycontactinformationtotheFPGA.
ParallelPort:ThisisthemaininterfaceforpassingconfigurationbitstreamsanddatatoandfromtheXSABoard.
PS/2Port:AkeyboardormousecaninterfacetotheXSABoardthroughthisport.
VGAPort:TheXSABoardcansendsignalstodisplaygraphicsonaVGAmonitorthroughthisport.
XSABOARDV1.
1,V1.
2USERMANUAL19PrototypingHeader:ManyoftheFPGAI/Opinsareconnectedtothe84pinsonthebottomoftheXSABoardthataremeanttomatewithsolderlessbreadboards.
A17-A0D7-D0/HSYNCPSCLKCKE/VSYNCPSDATACLKBLUE1-BLUE0GREEN1-GREEN0/CE/OE/WE/RESETA17-A0D7-D08TCKTMSTDITDOGCLK2-PPD03-PPD14-PPD25-PPD36-PPD47-PPD58-PPD69-PPD717-PPC316-PPC214-PPC11-PPC011-PPS710-PPS615-PPS313-PPS412-PPS5XC9572XLOSCFLASHPS/2PortParallelPortSDRAMVGAConnectorRED1-RED0D15-D0BA1-BA0,A12-A0RAS,CAS,/CS,/WEDQMLDQMHD7-D0CCLK/PROGRAMBSY/DOUT/WR/CS/INITM0M1M2DONETCKTMSTDITDOGCLKGCLKXC2S100Figure3:XSABoardprogrammer'smodel.
Programmablelogic:Spartan-IIFPGAandXC9572XLCPLDTheXSABoardcontainstwoprogrammablelogicchips:A50-KgateXC2S50or100-KgateXilinxXC2S100Spartan-IIFPGAina144-pinPQFPpackage.
TheFPGAisthemainrepositoryofprogrammablelogicontheXSABoard.
AXilinxXC9572XLCPLDisusedtomanagetheconfigurationoftheFPGAviatheparallelport.
TheCPLDalsocontrolstheprogrammingoftheFlashRAMontheXSABoard.
100MHzProgrammableOscillatorADallasDS1075programmableoscillatorprovidesaclocksignaltoboththeFPGAandtheCPLD.
TheDS1075hasamaximumfrequencyof100MHzthatisdividedtoprovidefrequenciesof100MHz,50MHz,33.
3MHz,25MHz,.
.
.
,48.
7KHz.
TheclocksignalfromtheDS1075isconnectedtoadedicatedclockinputoftheCPLD.
TheCPLDpassestheclocksignalontotheFPGA.
ThisallowstheCPLDtocontroltheclocksourcefortheFPGA.
XSABOARDV1.
1,V1.
2USERMANUAL20Tosetthedivisorvalue,theDS1075mustbeplacedinitsprogrammingmode.
Thisisdonebypullingtheclockoutputto+5Vonpower-upwithashuntacrosspins1and2ofjumperJ6.
ThenprogrammingcommandstosetthedivisoraresenttotheDS1075throughcontrolpinC0oftheparallelport.
ThedivisorisstoredinEEPROMintheDS1075soitwillberetainedevenwhenpowerisremovedfromtheXSABoard.
TheshuntonjumperJ6mustbeacrosspins2and3tomaketheoscillatoroutputaclocksignaluponpower-up.
TheclocksignalentersadedicatedclockinputoftheCPLD.
ThentheCPLDcanoutputaclocksignaltoadedicatedclockinputoftheFPGA.
TogetaprecisefrequencyvalueortosynctheXSAcircuitrywithanexternalsystem,youcaninsertanexternalclocksignalofupto50MHzthroughpin64oftheprototypingheader.
Thisexternalclocktakestheplaceoftheinternal100MHzclocksourceintheDS1075oscillator.
YoumustusetheGXSSETCLKsoftwareutilitytoenabletheexternalclockinputoftheDS1075.
ClocksignalscanalsobedirectlyappliedtotwoofthededicatedclockinputsoftheFPGAthroughthepinsoftheprototypingheader.
Spartan-IIFPGA881518231XC9572XLCPLD17J6PP-C0Pin64Pin31Pin1DS1075100MHzProg.
Osc.
+5V42SynchronousDRAMThevariousSDRAMorganizationsandmanufacturersusedontheXSABoardsaregiveninthefollowingtable.
SDRAMBoardOrganizationManufacturer&PartNo.
4Mx16HynixHY57V641620HGT-HXSA-504Mx16SamsungK4S641632F-TC750008Mx16HynixHY57V281620HCT-HXSA-1008Mx16SamsungK4S281632E-TC75000XSABOARDV1.
1,V1.
2USERMANUAL21TheSDRAMisconnectedtotheFPGAasshownbelow.
Currently,FPGApin133drivesano-connectpinoftheSDRAMbutthiscouldbeusedinthefutureasthethirteenthrow/columnaddressbitofalargerSDRAM.
Also,theSDRAMclocksignalisre-routedbacktoadedicatedclockinputoftheFPGAtoallowsynchronizationoftheFPGA'sinternaloperationswiththeSDRAMoperations.
ThisapplicationnotedescribesanSDRAMcontrollerthatmakestheSDRAMappearlikeasimplestaticRAMtotherestofthecircuitryintheFPGA.
8MX16SDRAM(XSA-100)4MX16SDRAM(XSA-50)Spartan-IIFPGA95Q03A7133NC136A11139A10138A9140A85A67A511A410A36A24A1141A096Q1599Q1100Q14102Q13112Q12114Q11116Q10118Q9121Q8120Q7117Q6115Q5113Q4103Q3101Q213412412913112213712613013212391BA0/CASCKEDQMLDQMHBA1/RAS/CS/WECLKFlashRAMTheFlashRAMorganizationsandmanufacturerusedontheXSABoardsaregiveninthefollowingtable.
FlashRAMBoardOrganizationManufacturer&PartNo.
XSA-50128Kx8AtmelAT49F001FlashRAMXSA-100256Kx8AtmelAT49F002FlashRAMXSABOARDV1.
1,V1.
2USERMANUAL22TheFlashRAMisconnectedsoboththeFPGAandCPLDhaveaccess.
Typically,theCPLDwillprogramtheFlashwithdatapassedthroughtheparallelport.
IfthedataisanFPGAconfigurationbitstream,thentheCPLDcanbeconfiguredtoprogramtheFPGAwiththebitstreamfromFlashwhenevertheXSABoardispoweredup.
(SeetheapplicationnoteXSAFlashProgrammingandSpartanIIConfigurationformoredetailsonthis.
)Afterpower-up,theFPGAcanreadand/orwritetheFlash.
(Ofcourse,theCPLDandFPGAhavetobeprogrammedsuchthattheydonotconflictifbotharetryingtoaccesstheFlash.
)TheFlashisdisabledbyraisingthe/CEpintoalogic1thusmakingtheI/OlinesconnectedtotheFlashavailableforgeneral-purposecommunicationbetweentheFPGAandtheCPLD.
256Kx8FlashRAM(XSA-100)128Kx8FlashRAM(XSA-50)XC9572XLCPLDSpartan-IIFPGAA0/CE114144S296DP86S475S664S554S323S0+5V48565163526447544651566543471243574244484550586659766075617462276328642914505949581067S1D0A2/WED2A3/RESETD3A4D4A5D5A6D6A7D7A8A9A1/OED1A10A11A12A13A14A15A16A17420796908S1DPS2S3S4S5S6S0DIPSW4DIPSW3DIPSW2DIPSW1XSABOARDV1.
1,V1.
2USERMANUAL23Seven-SegmentLEDTheXSABoardhasa7-segmentLEDdigitforusebytheFPGAortheCPLD.
ThesegmentsofthisLEDareactive-highmeaningthatasegmentwillglowwhenalogic-highisappliedtoit.
TheLEDsharesthesameeight-bitdatabusthatinterconnectstheCPLD,theFPGAconfigurationportandtheFlashRAMdatabus.
TheconnectionsbetweentheLEDsegmentsandthedatabusareshownbelow.
(WeusetwodistinctlabelingsoftheLEDsegmentsinourdocumentationanddesignexamples,soweshowtheconnectionsforboth.
)AS6ASBBSCCSDDSESESFS5FSGS3GSDPDPDPDP6S44S11S002253FPGA-DIN-D0FPGA-DIN-D0FPGA-D1FPGA-D1FPGA-D2FPGA-D2FPGA-D3FPGA-D3FPGA-D4FPGA-D4FPGA-D5FPGA-D5FPGA-D6FPGA-D6FPGA-D7FPGA-D7Four-PositionDIPSwitchTheXSABoardhasabankoffourDIPswitchesaccessiblefromtheCPLDandFPGA.
WhenclosedorON,eachswitchpullstheconnectedpinoftheFPGAandCPLDtoground.
Otherwise,thepinispulledhighthrougharesistorwhentheswitchisopenorOFF.
Whennotbeingused,theDIPswitchesshouldbeleftintheopenorOFFconfigurationsothepinsoftheFPGAandCPLDarenottiedtogroundandcanfreelymovebetweenlogiclowandhighlevels.
TheDIPswitchesalsosharethesamepinsastheuppermostfourbitsoftheFlashRAMaddressbus.
IftheFlashRAMisprogrammedwithseveralFPGAbitstreams,thentheDIPswitchescanbeusedtoselectaparticularbitstreamswhichwillbeloadedintotheFPGAbytheCPLDonpower-up.
However,thisfeatureisnotcurrentlysupportedbytheCPLDconfigurationthatloadstheFPGAfromtheFlashRAM(XSTOOLS\XSA\fcnfg.
svf).
PS/2PortAPS/2portprovidestheFPGAwithaninterfacetoeitherakeyboardoramouse.
TheFPGAreceivestwosignalsfromthePS/2interface:aclocksignalandaserialdatastreamthatissynchronizedwiththefallingedgeoftheclock.
(FormoredetailsonusingthePS/2portandasimplecircuitforreceivingkeystrokeinformationfromakeyboard,seethisapplicationnote.
)XSABOARDV1.
1,V1.
2USERMANUAL24Spartan-IIFPGAdata9493clkPS/2Connector(J4)+5VPushbutton(SW2)PushbuttonTheXSABoardhasasinglepushbuttonthatsharestheFPGApinconnectedtothedatalineofthePS/2port.
ThepushbuttonappliesalowleveltotheFPGApinwhenpressedandaresistorpullsthepintoahighlevelwhenthepushbuttonisnotpressed.
VGAMonitorInterfaceTheFPGAcangenerateavideosignalfordisplayonaVGAmonitor.
TheFPGAoutputstwobitseachofred,green,andbluecolorinformationtoasimpleresistor-ladderDAC.
Thisprovidesapaletteof22x22x22=64colors.
TheoutputsoftheDACaresenttotheRGBinputsofaVGAmonitor.
TheFPGAalsogeneratesthehorizontalandverticalsyncpulses(HSYNC#,VSYNC#).
(SeethisapplicationnoteformoredetailsonasimplecircuitforgeneratingVGAsignalsthatdisplaysanimagestoredinSDRAM.
)Spartan-IIFPGAred26232120191312RED0RED1BLUE0GREEN1GREEN0BLUE122hsyncvsyncgreenblueVGAConnector(J3)ParallelPortInterfaceTheparallelportisthemaininterfaceforcommunicatingwiththeXSABoard.
ControllineC0goesdirectlytotheDS1075oscillatorandisusedforsettingthedivisorasdescribedpreviously,andstatuslineS6connectsdirectlytotheFPGAforuseasacommunicationlinefromtheFPGAbacktothePC.
TheCPLDhandlesthefifteenremainingactivelinesoftheparallelportasfollows.
XSABOARDV1.
1,V1.
2USERMANUAL25Threeoftheparallelportcontrollines,C1–C3,connecttotheJTAGpinsthroughwhichtheCPLDisprogrammed.
TheC1controllineclocksconfigurationdatapresentedontheC3lineintotheCPLDwhiletheC2signalsteerstheactionsoftheCPLDprogrammingstatemachine.
Meanwhile,informationfromtheCPLDreturnstothePCthroughstatuslineS7.
Theeightdatalines,D0–D7,andtheremainingthreestatuslines,S3–S5,connecttogeneral-purposepinsoftheCPLD.
TheCPLDcanbeprogrammedtoactasaninterfacebetweentheFPGAandtheparallelport(thedwnldpar.
svffileisanexampleofsuchaninterface).
Schmitt-triggerinvertersareinsertedintotheD1linesoitcancarryacleanclockedgeforusebyanystatemachineprogrammedintotheCPLD.
TheCPLDconnectstotheconfigurationpinsoftheSpartan-IIFPGAsoitcanpassbitstreamsfromtheparallelporttotheFPGA.
TheactualconfigurationdataispresentedtotheFPGAonthesame8-bitbusthatalsoconnectstotheFlashRAMandseven-segmentLED.
TheCPLDalsodrivestheconfigurationpins(CCLK,/PROGRAM,/CS,and/WR)oftheFPGAthatcontroltheloadingofabitstream.
TheCPLDusestheM0inputoftheFPGAtoselecteithertheslave-serialormaster-selectconfigurationmode(M1andM2arealreadyhard-wiredtoVCCandGND,respectively.
)TheCPLDcanmonitorthestatusofthebitstreamdownloadthroughthe/INIT,DONE,andBSY/DOUTpinsoftheFPGA.
TheCPLDalsohasaccesstotheFPGA'sJTAGpins:TCK,TMS,TDI,TDO.
TheTMS,TDI,andTDOpinssharetheconnectionswiththeBSY/DOUT,/CS,and/WRpins.
Withtheseconnections,theCPLDcanbeprogrammedwithaninterfacethatallowsconfigurationoftheSpartan-IIFPGAthroughtheXilinxiMPACTsoftware.
JumperJ9allowstheconnectionofstatuspinS7tothegeneral-purposeCPLDpinthatalsodrivesstatuspinS5.
ThisisrequiredbytheiMPACTsoftwaresoitcancheckforthepresenceofthedownloadingcable.
XSABOARDV1.
1,V1.
2USERMANUAL26D7-D08TCKTMSTDITDO2-PPD03-PPD14-PPD25-PPD36-PPD47-PPD58-PPD69-PPD717-PPC316-PPC214-PPC11-PPC011-PPS710-PPS615-PPS313-PPS412-PPS5XC9572XLOSCFLASHRAMParallelPortCCLK373328203553302932222324252731341615401819393638133832142272306931109683478/PROGRAMBSY/DOUT/WR/CS/INITM0M1M2DONETCKTMSTDITDOSpartan-IIFPGAAftertheSpartanIIFPGAisconfiguredwithabitstreamandtheDONEpingoeshigh,theCPLDswitchesintoamodethatconnectstheparallelportdataandstatuspinstotheFPGA.
ThisletsyoupassdatatotheFPGAovertheparallelportdatalineswhilereceivingdatafromtheFPGAoverthestatuslines.
TheconnectionsbetweentheFPGAandtheparallelportareshownbelow.
XSABOARDV1.
1,V1.
2USERMANUAL27256KByteFlashRAMXC9572XLCPLDA0/CE1122332332313427202535244S29DP8S47S66S55S32S0+5V4851524746564312574445585960616263641504910S1D0D0A2/WED2D2A3/RESETD3D3S3A4D4D4S4A5D5D5S5A6D6D6A7D7D7A8A9A1/OED1D1A10A11A12A13A14A15A16A178S1DPS2S3S4S5S6S0DIPSW4DIPSW3DIPSW2DIPSW1Spartan-IIFPGA414462605749463956636454516547434248506676757427282940595867TheFPGAsendsdatabacktothePCbydrivinglogiclevelsontopins40,29and28whichpassthroughtheCPLDandontotheparallelportstatuslinesS3,S4andS5,respectively.
Conversely,thePCsendsdatatotheFPGAonparallelportdatalinesD0–D7andthedatapassesthroughtheCPLDandendsuponFPGApins50,48,42,47,65,51,58and43,respectively.
TheFPGAshouldneverdrivethesepinsunlessitisaccessingtheFlashRAMotherwisetheCPLDand/ortheFPGAcouldbedamaged.
TheCPLDcansensewhentheFPGAlowerstheFlashRAMchip-enableanditwillreleasethedatalinessotheFPGAcandrivetheaddress,output-enableandwrite-enablepinsoftheFlashRAMwithoutcontention.
TheCPLDalsodrivesthedecimal-pointoftheLEDdisplaytoindicatewhentheFPGAisconfiguredwithavalidbitstream.
UnlessitisaccessingtheFlashRAM,theFPGAshouldneverdrivepin44toalowlogicleveloritmaydamageitselfortheCPLD.
ButwhentheFPGAlowerstheFlashRAMchip-enable,theCPLDwillstopdrivingtheLEDdecimal-pointtoallowtheFPGAaccesstodatapinD1oftheFlashRAM.
XSABOARDV1.
1,V1.
2USERMANUAL28FormoredetailsonhowtheCPLDmanagestheinterfacebetweentheparallelportandtheSpartanIIFPGAbothbeforeandafterdeviceconfiguration,seetheXSAParallelPortInterfaceapplicationnote.
PrototypingHeaderThepinsoftheFPGAareaccessiblethroughthe84-pinprototypingheaderontheundersideoftheXSABoard.
Pin1oftheheader(denotedbyasquarepad)islocatedinthemiddleoftheleft-handedgeoftheboardandtheremaining83pinsarearrangedcounter-clockwisearoundtheperiphery.
Thephysicaldimensionsoftheprototypingheaderandthepinarrangementareshownbelow.
121226364841.
75"4.
1"0.
1"Asubsetofthe144pinsontheFPGA'sTQFPpackageconnectstotheprototypingheader.
ThenumberoftheFPGApinconnectedtoagivenheaderpinisprintednexttotheheaderpinontheboard.
ThismakesiteasiertofindagivenFPGApinwhenyouwanttoconnectittoanexternalsystem.
WhilemostoftheFPGApinsarealreadyusedtosupportfunctionsoftheXSABoard,theycanalsobeusedtointerfacetoexternalsystemsthroughtheprototypingheader.
TheFPGApinscanbegroupedintothevariouscategoriesshownbelow.
(Pinsdenotedwith*areuseableasgeneral-purposeI/O;pinsdenotedwith**canbeusedasgeneral-purposeI/OonlyiftheCPLDinterfaceisreprogrammedwiththealternateparallelportinterfacestoredinthedwnldpa2.
svffile;pinswithnomarkingcannotbeusedasgeneral-purposeI/Oatall.
)XSABOARDV1.
1,V1.
2USERMANUAL29ConfigurationPins(30*,31*,37,38*,39*,44*,46*,49*,57*,60*,62*,67*,68*,69,72,106,109,111):ThesepinsareusedtoloadtheSpartanIIFPGAwithaconfigurationbitstream.
Someofthesepinsarededicatedtotheconfigurationprocessandcannotbeusedasgeneral-purposeI/O(37,69,72,106,109,111).
Therestcanbeusedasgeneral-purposeI/OaftertheFPGAisconfigured.
Ifexternallogicisconnectedtothesepins,youmayhavetodisableitduringtheconfigurationprocess.
TheDONEpin(72)canbeusedforthispurposesinceitgoestoalogichighonlyaftertheconfigurationprocessiscompleted.
FlashRAMPins(27*,28*,29*,39*,40*,41*,42**,43**,44*,46*,47**,48**,49*,50**,51**,54*,56*,57*,58**,59*,60*,62*,63*,64*,65**,66*,67*,74*,75*,76*):ThesepinsareusedbytheFPGAtoaccesstheFlashRAM.
Theycanbeusedforgeneral-purposeI/Ounderthefollowingconditions.
WhentheFPGAisconfiguredfromtheFlash,theCPLDdrivesallthesepinssoanyexternallogicshouldbedisabledusingtheDONEpin.
Also,aftertheconfiguration,theFlashchip-enable(41)shouldbedrivenhightodisabletheFlashRAMsoitdoesn'tdrivethedatabuspins.
Inaddition,thestandardparallelportinterfaceloadedintotheCPLD(dwnldpar.
svf)willdriveeightoftheFlashRAMpins(42,43,47,48,50,51,58,65)withthelogicvaluesfoundontheeightdatalinesoftheparallelport.
Ifthisisnotdesired,thenusethealternateparallelportinterface(dwnldpa2.
svf)whichdoesnotdrivethesepins.
VGAPins(12*,13*,19*,20*,21*,22*,23*,26*):WhennotusedtodriveaVGAmonitor,thesepinscanbeusedforgeneral-purposeI/Othroughtheprototypingheader.
WhenusedasI/O,theRED0–RED1(12–13),GREEN0–GREEN1(19–20)andBLUE0–BLUE1(21–22)pairshaveanimpedanceofapproximately1Kbetweenthemduetothepresenceoftheresistor-ladderDACcircuitry.
PS/2Pins(93*,94*):WhennotusedtoaccessthePS/2keyboard/mouseport,thesepinscanbeusedasgeneral-purposeI/Othroughtheprototypingheader.
GlobalClockPins(15*,18*):Thesepinscanbeusedasglobalclockinputsorgeneral-purposeinputs.
Theycannotbeusedasoutputs.
FreePins(77*,78*,79*,80*,83*,84*,85*,86*,87*):ThesepinsarenotconnectedtoanyotherdevicesontheXSABoardsotheycanbeusedwithoutrestrictionsasgeneral-purposeI/Othroughtheprototypingheader.
JTAGPins(2,32,34,142):ThesepinsareusedtoaccesstheJTAGfeaturesoftheFPGA.
Theycannotbeusedasgeneral-purposeI/Opins.
XSABOARDV1.
1,V1.
2USERMANUAL30AXSAPinConnectionsThefollowingtableslistthepinnumbersoftheFPGAandCPLDalongwiththepinnamesoftheotherchipsthattheyconnecttoontheXSABoardandtheXStendBoard.
ThefirsttwotablescorrespondtoanXSABoard+XST-2.
xcombination,whilethelasttwotablescorrespondtoanXSABoard+XST-1.
xcombination.
Pinsmarkedwith*areuseableasgeneral-purposeI/O;pinsdenotedwith**canbeusedasgeneral-purposeI/OonlyiftheCPLDinterfaceisreprogrammedwiththealternateparallelportinterfacestoredinthedwnldpa2.
svffile;pinswithnomarkingcannotbeusedasgeneral-purposeI/Oatall.
XSABOARDV1.
1,V1.
2USERMANUAL31FPGAPinFunctionNetNameCPLDPinParallelPortLEDsSwitchButtonSDRAMFlashVGAPS/2Proto.
PinLEDsSwitchButtonSRAMIDEIntfc.
StereoCodecUSBSerialPort1VCCO+3.
3VPROTO542TCKFPGA-TCK13PROTO163*I/OSDRAM-A74*I/OSDRAM-A15*I/O-VREF0SDRAM-A66*I/O-VREF0SDRAM-A27*I/OSDRAM-A58GNDPROTO529VCCINT+2.
5VPROTO2210*I/OSDRAM-A311*I/OSDRAM-A412*I/O-VREF0VGA-RED0PROTO2713*I/OVGA-RED1PROTO2814VCCINT15*I-GCK3FPGA-GCK3PROTO3116VCCO17GND18*I-GCK2FPGA-GCK2PROTO119*I/OVGA-GREEN0PROTO2920*I/OVGA-GREEN1PROTO3221*I/O-VREF1VGA-BLUE0PROTO3322*I/OVGA-BLUE1PROTO3423*I/OVGA-HSYNC#PROTO36PUSHB424VCCINT25GND26*I/OVGA-VSYNC#PROTO37PUSHB327*I/O-VREF162FLASH-A3PROTO50LED2-BRAM-A0IDE-DMARQ28*I/O-VREF163PP-S5FLASH-A2PROTO51LED2-ERAM-A10USB-INT#29*I/O64PP-S4FLASH-A1PROTO56LED2-GRAM-A11USB-SUSPEND30*I/O-WRITE#FPGA-WR#19PROTO69DIPSW131*I/O-CS#FPGA-CS#15PROTO68IDE-RESET#32TDIFPGA-TDI15PROTO1533GND34TDOFPGA-TDO19PROTO3035VCCO36VCCO37CCLKFPGA-CCLK16PROTO7338*I/O-DOUT/BSYFPGA-DOUT-BSY18PROTO45LED2-DPRAM-A1IDE-DMACK#39*I/O-D0FPGA-DIN-D02LED-S1FLASH-D0PROTO71BARLED9RAM-A16IDE-IORDY40*I/O1PP-S3FLASH-A0PROTO57LED2-CRAM-A9IDE-INTRQ41*I/O-VREF211FLASH-CE#PROTO6542**I/O57PP-D2FLASH-A10PROTO58LED2-FRAM-A8IDE-D843**I/O-VREF212PP-D7FLASH-OE#PROTO61RAM-OE#IDE-D944*I/O-D1FPGA-D14LED-DPFLASH-D1PROTO40BARLED2RAM-D6IDE-D145GND46*I/O-D2FPGA-D25LED-S4FLASH-D2PROTO39BARLED3RAM-D5IDE-D247**I/O43PP-D3FLASH-A11PROTO59LED2-DRAM-A13IDE-D1048**I/O-VREF244PP-D1FLASH-A9PROTO60LED2-ARAM-A15IDE-D1149*I/O-D3FPGA-D36LED-S6FLASH-D3PROTO38BARLED4RAM-D4IDE-D350**I/O45PP-D0FLASH-A8PROTO78LED1-GRAM-A14IDE-D1251**I/O-IRDY46PP-D5FLASH-A13PROTO79LED1-BRAM-A12IDE-D1352GND53VCCO54*I/O-TRDY47DIPSW1AFLASH-A14PROTO82LED1-FRAM-A7IDE-CS0#55VCCINT56*I/O48DIPSW1DFLASH-A17PROTO83LED1-ARAM-A6IDE-CS1#57*I/O-D4FPGA-D47LED-S5FLASH-D4PROTO35BARLED5RAM-D3IDE-D458**I/O-VREF349PP-D6FLASH-WE#PROTO62DIPSW2RAM-WE#IDE-D1459*I/O50FLASH-RESET#PROTO66BARLED10AUDIO-LRCK60*I/O-D5FPGA-D58LED-S3FLASH-D5PROTO80BARLED7RAM-D0IDE-D6RS232-RD61GND62*I/O-D6FPGA-D69LED-S2FLASH-D6PROTO81BARLED6RAM-D1IDE-D5RS232-CTS63*I/O-VREF351DIPSW1CFLASH-A16PROTO84LED1-DPRAM-A5IDE-DA264*I/O52DIPSW1BFLASH-A15PROTO3LED1-DRAM-A4IDE-DA065**I/O-VREF356PP-D4FLASH-A12PROTO4LED1-CRAM-A3IDE-D1566*I/O58FLASH-A7PROTO5DIPSW5RAM-A2IDE-DA167*I/O-D7FPGA-D710LED-S0FLASH-D7PROTO10BARLED8RAM-D2IDE-D768*I/O-INIT#FPGA-INIT#38PROTO41BARLED1RAM-D7IDE-D069PROG#FPGA-PROG#39PROTO55PUSHB170VCCO71VCCO72DONEFPGA-DONE40PROTO5373GND74*I/O61FLASH-A4PROTO70DIPSW3AUDIO-SDTI75*I/O60FLASH-A5PROTO77DIPSW4AUDIO-SCLK76*I/O59FLASH-A6PROTO6LED1-EAUDIO-SDTO77*I/O-VREF4PROTO9DIPSW6AUDIO-MCLK78*I/OPP-S6PROTO67PUSHB279*I/O-VREF4PROTO7DIPSW8RAM-CE#80*I/OPROTO8DIPSW7RS232-RTS81GND82VCCINT83*I/OPROTO18RS232-TDConnectionsBetweentheFPGAandOtherXSABoardComponents…andtheXST-2.
xBoardFPGAPinFPGAPinFunctionNetNameCPLDPinParallelPortLEDsSwitchButtonSDRAMFlashVGAPS/2Proto.
PinLEDsSwitchButtonSRAMIDEIntfc.
StereoCodecUSBSerialPortConnectionsBetweentheFPGAandOtherXSABoardComponents…andtheXST-2.
xBoardFPGAPin84*I/OPROTO19USB-SCL85*I/O-VREF4PROTO20USB-SDA86*I/OPROTO23IDE-DIOR#87*I/OPROTO24IDE-DIOW#88I-GCK0MASTER-CLK42PROTO1389GND90VCCO91I-GCK1FPGA-GCK1SDRAM-CLKFB92VCCINT93*I/OPUSHBPS2-DATAPROTO2594*I/O-VREF5PS2-CLKPROTO2695*I/OSDRAM-Q096*I/OSDRAM-Q1597VCCINT98GND99*I/OSDRAM-Q1100*I/O-VREF5SDRAM-Q14101*I/OSDRAM-Q2102*I/O-VREF5SDRAM-Q13103*I/OSDRAM-Q3104N/C105N/C106M2FPGA-M2PROTO12107VCCO108VCCO109M0FPGA-M036PROTO14110GND111M1FPGA-M1PROTO21112*I/OSDRAM-Q12113*I/OSDRAM-Q4114*I/OSDRAM-Q11115*I/O-VREF6SDRAM-Q5116*I/OSDRAM-Q10117*I/O-VREF6SDRAM-Q6118*I/OSDRAM-Q9119GND120*!
/OSDRAM-Q7121*I/OSDRAM-Q8122*I/O-VREF6SDRAM-QML123*I/OSDRAM-WE#124*I/OSDRAM-QMH125VCCINT126*I/O-TRDYSDRAM-CAS#127VCCO128GND129*I/O-IRDYSDRAM-CLK130*I/OSDRAM-RAS#131*I/OSDRAM-CKE132*I/O-VREF7SDRAM-CS#133*I/OSDRAM-A12134*I/OSDRAM-BA0135GND136*I/OSDRAM-A11137*I/O-VREF7SDRAM-BA1138*I/OSDRAM-A9139*I/O-VREF7SDRAM-A10140*I/OSDRAM-A8141*I/OSDRAM-A0142TMSFPGA-TMS18PROTO17143GND144VCCOCPLDPinFunctionNetNameParallelPortLEDsSwitchButtonFlashProto.
PinLEDsSwitchButtonSRAMIDEIntfc.
StereoCodecUSBSerialPort140*PP-S3FLASH-A0PROTO57LED2-CRAM-A9IDE-INTRQ2FPGA-DIN-D039*LED-S1FLASH-D0PROTO71BARLED9RAM-A16IDE-IORDY3VCCINT4FPGA-D144*LED-DPFLASH-D1PROTO40BARLED2RAM-D6IDE-D15FPGA-D246*LED-S4FLASH-D2PROTO39BARLED3RAM-D5IDE-D26FPGA-D349*LED-S6FLASH-D3PROTO38BARLED4RAM-D4IDE-D37FPGA-D457*LED-S5FLASH-D4PROTO35BARLED5RAM-D3IDE-D48FPGA-D560*LED-S3FLASH-D5PROTO80BARLED7RAM-D0IDE-D6RS232-RD9FPGA-D662*LED-S2FLASH-D6PROTO81BARLED6RAM-D1IDE-D5RS232-CTS10FPGA-D767*LED-S0FLASH-D7PROTO10BARLED8RAM-D2IDE-D71141*FLASH-CE#PROTO651243**PP-D7FLASH-OE#PROTO61RAM-OE#IDE-D913FPGA-TCK2PROTO1614GND15GCK1FPGA-CS#31*PROTO68IDE-RESET#15GCK1FPGA-TDI32PROTO1516GCK2FPGA-CCLK37PROTO7317GCK3PROG-OSC18FPGA-DOUT-BSY38*PROTO45LED2-DPRAM-A1IDE-DMACK#18FPGA-TMS142PROTO1719FPGA-WR#30*PROTO69DIPSW119FPGA-TDO34PROTO3020PPORT-S421GND22PPORT-D723PPORT-D624PPORT-D525PPORT-D426VCCIO27PPORT-D328TDIPPORT-C329TMSPPORT-C230TCKPPORT-C131PPORT-D232PPORT-D133PPORT-D034PPORT-S335PPORT-S536FPGA-M0109PROTO1437VCCINT38FPGA-INIT#68*PROTO41BARLED1RAM-D7IDE-D039FPGA-PROG#69PROTO55PUSHB140FPGA-DONE72PROTO5341GND42MASTER-CLK88PROTO134347**PP-D3FLASH-A11PROTO59LED2-DRAM-A13IDE-D104448**PP-D1FLASH-A9PROTO60LED2-ARAM-A15IDE-D114550**PP-D0FLASH-A8PROTO78LED1-GRAM-A14IDE-D124651**PP-D5FLASH-A13PROTO79LED1-BRAM-A12IDE-D134754*DIPSW1AFLASH-A14PROTO82LED1-FRAM-A7IDE-CS0#4856*DIPSW1DFLASH-A17PROTO83LED1-ARAM-A6IDE-CS1#4958**PP-D6FLASH-WE#PROTO62DIPSW2RAM-WE#IDE-D145059*FLASH-RESET#PROTO66BARLED10AUDIO-LRCK5163*DIPSW1CFLASH-A16PROTO84LED1-DPRAM-A5IDE-DA25264*DIPSW1BFLASH-A15PROTO3LED1-DRAM-A4IDE-DA053TDOPPORT-S754GND55VCCIO5665**PP-D4FLASH-A12PROTO4LED1-CRAM-A3IDE-D155742**PP-D2FLASH-A10PROTO58LED2-FRAM-A8IDE-D85866*FLASH-A7PROTO5DIPSW5RAM-A2IDE-DA15976*FLASH-A6PROTO6LED1-EAUDIO-SDTO6075*FLASH-A5PROTO77DIPSW4AUDIO-SCLK6174*FLASH-A4PROTO70DIPSW3AUDIO-SDTI6227*FLASH-A3PROTO50LED2-BRAM-A0IDE-DMARQ6328*PP-S5FLASH-A2PROTO51LED2-ERAM-A10USB-INT#6429*PP-S4FLASH-A1PROTO56LED2-GRAM-A11USB-SUSPENDConnectionsBetweentheCPLDandOtherXSABoardComponents…andtheXST-2.
xBoardFPGAPinCPLDPinFPGAPinFunctionNetNameCPLDPinParallelPortLEDsSwitchButtonSDRAMFlashVGAPS/2Proto.
PinLEDsSwitchButtonSRAMVGAStereoCodecPS/2Xchecker1VCCO+3.
3VPROTO542TCKFPGA-TCK13PROTO16XCHK-TCK3*I/OSDRAM-A74*I/OSDRAM-A15*I/O-VREF0SDRAM-A66*I/O-VREF0SDRAM-A27*I/OSDRAM-A58GNDPROTO529VCCINT+2.
5VPROTO2210*I/OSDRAM-A311*I/OSDRAM-A412*I/O-VREF0VGA-RED0PROTO2713*I/OVGA-RED1PROTO28RLED-DP#RAM-A1514VCCINT15*I-GCK3FPGA-GCK3PROTO3116VCCO17GND18*I-GCK2FPGA-GCK2PROTO119*I/OVGA-GREEN0PROTO2920*I/OVGA-GREEN1PROTO32XCHK-RT21*I/O-VREF1VGA-BLUE0PROTO3322*I/OVGA-BLUE1PROTO3423*I/OVGA-HSYNC#PROTO3624VCCINT25GND26*I/OVGA-VSYNC#PROTO37PUSH-RESET#27*I/O-VREF162FLASH-A3PROTO50RLED-S4#RAM-A1228*I/O-VREF163PP-S5FLASH-A2PROTO51RLED-S2#RAM-A1029*I/O64PP-S4FLASH-A1PROTO56RLED-S3#RAM-A1130*I/O-WRITE#FPGA-WR#19PROTO69DIPSW8X-PS2-DATA31*I/O-CS#FPGA-CS#15PROTO68X-PS2-CLK32TDIFPGA-TDI15PROTO15XCHK-TDI33GND34TDOFPGA-TDO19PROTO30XCHK-RD35VCCO36VCCO37CCLKFPGA-CCLK16PROTO73XCHK-CCLK38*I/O-DOUT/BSYFPGA-DOUT-BSY18PROTO4539*I/O-D0FPGA-DIN-D02LED-S1FLASH-D0PROTO71XCHK-DIN40*I/O1PP-S3FLASH-A0PROTO57RLED-S1#RAM-A941*I/O-VREF211FLASH-CE#PROTO65RAM-CE#42**I/O57PP-D2FLASH-A10PROTO58RLED-S5#RAM-A1343**I/O-VREF212PP-D7FLASH-OE#PROTO61RAM-OE#44*I/O-D1FPGA-D14LED-DPFLASH-D1PROTO40BARLED2RAM-D145GND46*I/O-D2FPGA-D25LED-S4FLASH-D2PROTO39BARLED3RAM-D247**I/O43PP-D3FLASH-A11PROTO59RLED-S0#RAM-A848**I/O-VREF244PP-D1FLASH-A9PROTO60RLED-S6#RAM-A1449*I/O-D3FPGA-D36LED-S6FLASH-D3PROTO38BARLED4RAM-D350**I/O45PP-D0FLASH-A8PROTO78LLED-S3#RAM-A351**I/O-IRDY46PP-D5FLASH-A13PROTO79LLED-S4#RAM-A452GND53VCCO54*I/O-TRDY47DIPSW1AFLASH-A14PROTO82LLED-S5#RAM-A555VCCINT56*I/O48DIPSW1DFLASH-A17PROTO83LLED-S6#RAM-A657*I/O-D4FPGA-D47LED-S5FLASH-D4PROTO35BARLED5RAM-D458**I/O-VREF349PP-D6FLASH-WE#PROTO62RAM-WE#59*I/O50FLASH-RESET#PROTO66DIPSW7CODEC-LRCK60*I/O-D5FPGA-D58LED-S3FLASH-D5PROTO80BARLED7RAM-D661GND62*I/O-D6FPGA-D69LED-S2FLASH-D6PROTO81BARLED6RAM-D563*I/O-VREF351DIPSW1CFLASH-A16PROTO84LLED-DP#RAM-A764*I/O52DIPSW1BFLASH-A15PROTO3LLED-S0#RAM-A065**I/O-VREF356PP-D4FLASH-A12PROTO4LLED-S1#RAM-A166*I/O58FLASH-A7PROTO5LLED-S2#RAM-A267*I/O-D7FPGA-D710LED-S0FLASH-D7PROTO10BARLED8RAM-D768*I/O-INIT#FPGA-INIT#38PROTO41BARLED1RAM-D0XCHK-INIT#69PROG#FPGA-PROG#39PROTO55PUSH-PROG#XCHK-PROG#70VCCO71VCCO72DONEFPGA-DONE40PROTO53XCHK-DONE73GND74*I/O61FLASH-A4PROTO70DIPSW6CODEC-SDIN75*I/O60FLASH-A5PROTO77DIPSW5CODEC-SCLK76*I/O59FLASH-A6PROTO6DIPSW4CODEC-SDOUT77*I/O-VREF4PROTO9DIPSW3CODEC-MCLKXCHK-CLKO78*I/OPP-S6PROTO67PUSH-SPARE#X-VGA-VSYNC#79*I/O-VREF4PROTO7DIPSW1RAM-LCE#XCHK-TRIG80*I/OPROTO8DIPSW2RAM-RCE#XCHK-RST81GND82VCCINT83*I/OPROTO18X-VGA-RED184*I/OPROTO19X-VGA-HSYNC#85*I/O-VREF4PROTO20X-VGA-GREEN1ConnectionsBetweentheFPGAandOtherXSABoardComponents…andtheXST-1.
xBoardFPGAPinFPGAPinFunctionNetNameCPLDPinParallelPortLEDsSwitchButtonSDRAMFlashVGAPS/2Proto.
PinLEDsSwitchButtonSRAMVGAStereoCodecPS/2XcheckerConnectionsBetweentheFPGAandOtherXSABoardComponents…andtheXST-1.
xBoardFPGAPin86*I/OPROTO23X-VGA-RED087*I/OPROTO24X-VGA-GREEN088I-GCK0MASTER-CLK42PROTO13XCHK-CLKI89GND90VCCO91I-GCK1FPGA-GCK1SDRAM-CLKFB92VCCINT93*I/OPUSHBPS2-DATAPROTO25X-VGA-BLUE094*I/O-VREF5PS2-CLKPROTO26X-VGA-BLUE195*I/OSDRAM-Q096*I/OSDRAM-Q1597VCCINT98GND99*I/OSDRAM-Q1100*I/O-VREF5SDRAM-Q14101*I/OSDRAM-Q2102*I/O-VREF5SDRAM-Q13103*I/OSDRAM-Q3104N/C105N/C106M2FPGA-M2PROTO12107VCCO108VCCO109M0FPGA-M036PROTO14110GND111M1FPGA-M1PROTO21112*I/OSDRAM-Q12113*I/OSDRAM-Q4114*I/OSDRAM-Q11115*I/O-VREF6SDRAM-Q5116*I/OSDRAM-Q10117*I/O-VREF6SDRAM-Q6118*I/OSDRAM-Q9119GND120*!
/OSDRAM-Q7121*I/OSDRAM-Q8122*I/O-VREF6SDRAM-QML123*I/OSDRAM-WE#124*I/OSDRAM-QMH125VCCINT126*I/O-TRDYSDRAM-CAS#127VCCO128GND129*I/O-IRDYSDRAM-CLK130*I/OSDRAM-RAS#131*I/OSDRAM-CKE132*I/O-VREF7SDRAM-CS#133*I/OSDRAM-A12134*I/OSDRAM-BA0135GND136*I/OSDRAM-A11137*I/O-VREF7SDRAM-BA1138*I/OSDRAM-A9139*I/O-VREF7SDRAM-A10140*I/OSDRAM-A8141*I/OSDRAM-A0142TMSFPGA-TMS18PROTO17XCHK-TMS143GND144VCCOCPLDPinFunctionNetNameParallelPortLEDsSwitchButtonFlashProto.
PinLEDsSwitchButtonSRAMStereoCodecPS/2Xchecker140*PP-S3FLASH-A0PROTO57RLED-S1#RAM-A92FPGA-DIN-D039*LED-S1FLASH-D0PROTO71XCHK-DIN3VCCINT4FPGA-D144*LED-DPFLASH-D1PROTO40BARLED2RAM-D15FPGA-D246*LED-S4FLASH-D2PROTO39BARLED3RAM-D26FPGA-D349*LED-S6FLASH-D3PROTO38BARLED4RAM-D37FPGA-D457*LED-S5FLASH-D4PROTO35BARLED5RAM-D48FPGA-D560*LED-S3FLASH-D5PROTO80BARLED7RAM-D69FPGA-D662*LED-S2FLASH-D6PROTO81BARLED6RAM-D510FPGA-D767*LED-S0FLASH-D7PROTO10BARLED8RAM-D71141*FLASH-CE#PROTO65RAM-CE#1243**PP-D7FLASH-OE#PROTO61RAM-OE#13FPGA-TCK2PROTO16XCHK-TCK14GND15GCK1FPGA-CS#31*PROTO68X-PS2-CLK15GCK1FPGA-TDI32PROTO15XCHK-TDI16GCK2FPGA-CCLK37PROTO73XCHK-CCLK17GCK3PROG-OSC18FPGA-DOUT-BSY38*PROTO4518FPGA-TMS142PROTO17XCHK-TMS19FPGA-WR#30*PROTO69DIPSW8X-PS2-DATA19FPGA-TDO34PROTO30XCHK-RD20PPORT-S421GND22PPORT-D723PPORT-D624PPORT-D525PPORT-D426VCCIO27PPORT-D328TDIPPORT-C329TMSPPORT-C230TCKPPORT-C131PPORT-D232PPORT-D133PPORT-D034PPORT-S335PPORT-S536FPGA-M0109PROTO1437VCCINT38FPGA-INIT#68*PROTO41BARLED1RAM-D0XCHK-INIT#39FPGA-PROG#69PROTO55PUSH-PROG#XCHK-PROG#40FPGA-DONE72PROTO53XCHK-DONE41GND42MASTER-CLK88PROTO13XCHK-CLKI4347**PP-D3FLASH-A11PROTO59RLED-S0#RAM-A84448**PP-D1FLASH-A9PROTO60RLED-S6#RAM-A144550**PP-D0FLASH-A8PROTO78LLED-S3#RAM-A34651**PP-D5FLASH-A13PROTO79LLED-S4#RAM-A44754*DIPSW1AFLASH-A14PROTO82LLED-S5#RAM-A54856*DIPSW1DFLASH-A17PROTO83LLED-S6#RAM-A64958**PP-D6FLASH-WE#PROTO62RAM-WE#5059*FLASH-RESET#PROTO66DIPSW7CODEC-LRCK5163*DIPSW1CFLASH-A16PROTO84LLED-DP#RAM-A75264*DIPSW1BFLASH-A15PROTO3LLED-S0#RAM-A053TDOPPORT-S754GND55VCCIO5665**PP-D4FLASH-A12PROTO4LLED-S1#RAM-A15742**PP-D2FLASH-A10PROTO58RLED-S5#RAM-A135866*FLASH-A7PROTO5LLED-S2#RAM-A25976*FLASH-A6PROTO6DIPSW4CODEC-SDOUT6075*FLASH-A5PROTO77DIPSW5CODEC-SCLK6174*FLASH-A4PROTO70DIPSW6CODEC-SDIN6227*FLASH-A3PROTO50RLED-S4#RAM-A126328*PP-S5FLASH-A2PROTO51RLED-S2#RAM-A106429*PP-S4FLASH-A1PROTO56RLED-S3#RAM-A11ConnectionsBetweentheCPLDandOtherXSABoardComponents…andtheXST-1.
xBoardFPGAPinCPLDPinBXSASchematicsThefollowingpagesshowthedetailedschematicsfortheXSABoard.
XSABOARDV1.
1,V1.
2USERMANUAL32xsa1_2.
sch-1-MonFeb1108:37:192002xsa1_2.
sch-2-MonFeb1108:37:192002xsa1_2.
sch-3-MonFeb1108:37:192002xsa1_2.
sch-4-MonFeb1108:37:192002xsa1_2.
sch-5-MonFeb1108:37:192002xsa1_2.
sch-6-MonFeb1108:37:192002xsa1_2.
sch-7-MonFeb1108:37:202002xsa1_2.
sch-8-MonFeb1108:37:202002xsa1_2.
sch-9-MonFeb1108:37:202002