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Core1588v2.
0HandbookCore1588v2.
0Handbook3TableofContentsIntroduction.
5Core1588Overview.
5KeyFeatures6CoreVersion.
6SupportedDeviceFamilies.
6SupportedInterfaces6DesignDescription9DesignImplementation.
9Programmer'sModel15RegisterSummary.
15GeneralConfigurationRegister.
17InterruptEnableRegister.
18MaskedInterruptStatusRegister.
18RawInterruptStatusRegister19TransitTimestampLeastSignificantWordRegister19TransitTimestampMostSignificantWordRegister20TransitTimestampIdentificationRegister20ReceiveTimestampLeastSignificantWordRegister20ReceiveTimestampMostSignificantWordRegister20ReceiveTimestampIdentificationRegister220ReceiveTimestampIdentificationRegister121ReceiveTimestampIdentificationRegister021RTCLeastSignificantWordRegister.
21RTCMostSignificantWordRegister.
22AdjustmentRegister22TimeTrigger0LeastSignificantWordRegister.
23TimeTrigger0MostSignificantWordRegister.
23TimeTrigger1LeastSignificantWordRegister.
24TimeTrigger1MostSignificantWordRegister.
24TimeTrigger2LeastSignificantWordRegister.
25TimeTrigger2MostSignificantWordRegister.
25Latch0LeastSignificantWordRegister26Latch0MostSignificantWordRegister26Latch1LeastSignificantWordRegister27Latch1MostSignificantWordRegister27Latch2LeastSignificantWordRegister28Latch2MostSignificantWordRegister28Introduction4Core1588v2.
0HandbookInterfaces.
29Parameters29Ports29ToolFlows31Licensing.
31SmartDesign.
31SimulationFlow32SynthesisinLiberoIDE32PlaceandRouteinLiberoIDE32ApplicationHints33ConnectingCore1588inSmartDesign.
33OrderingInformation.
35OrderingCodes35ProductSupport.
37CustomerService37TechnicalSupport.
37Core1588v2.
0Handbook5IntroductionCore1588OverviewCore1588provideshardwaresupportfortheimplementationofanIEEE1588PrecisionTimeProtocol(PTP)capablesystem.
AfirmwarecomponentthatinteractswithCore1588willalsoformpartofsuchasystem.
Core1588maintainsaRealTimeCounter(RTC)andmonitorstheEthernetMAC-PHYinterfacetoidentifyIEEE1588typeframes.
Thecoretimestampsreceiptandtransmissionoftheseframesand,whenenabled,caninterruptthesystemprocessortocauseactiontobetaken.
Core1588supportsfullduplexoperation.
AnAPBinterfaceispresentonthecoreandthisallowsthesystemprocessortocontrolhowthecoreoperatesandtoretrievetimestampinformation.
LatchinputsandtriggeroutputsarepresentonCore1588andtheseprovidetheabilitytoaccuratelytimestampsystemeventsandtoeffectactionsatpredefinedtimes.
Theinterruptmechanismcanbeusedtoalertthesystemprocessorwhenalatchortriggereventoccursbuttheprocessordoesnotnecessarilyhavetobecriticallyinvolvedtimewiseinrespondingtolatchandtriggerevents.
Forexample,atriggeroutputcouldbeuseddirectlytocausesomeotheractiontooccurinthesystemwithoutwaitingfortheprocessortodosomething.
Core1588iscurrentlytargetedprimarilyatSmartFusiondevicesanditisintendedthatitwillbeusedinconjunctionwiththe(hard)MACincludedwithintheMSScomponentofthesedevices.
Core1588isitselfasoftcorethatwillbeimplementedintheFPGAfabricofaSmartFusiondevice.
The(RMII)MAC-PHYinterfaceofSmartFusioncanbemadeavailabletotheFPGAfabricofthedeviceandthisfeatureisemployedtoconnectCore1588tothesystemappropriately,allowingittomonitorEthernettraffic.
Figure1Core1588inaSmartFusionDeviceIntroduction6Core1588v2.
0HandbookKeyFeaturesRealTimeClock(RTC)(32bitsecondscounterand32bitnanosecondscounter)Supportsupto3latchinputsandupto3triggeroutputsAPBinterfaceforprocessoraccessRTCvaluecanbewrittendirectlyRTCcanbespeededuporsloweddownMonitorsRMIIinterfacetodetectIEEE1588framesSupportsfullduplexoperationCangenerateinterruptwhenIEEE1588framedetectedorwhenlatch/triggereventoccursSupports100MbpsoperationonlyCoreVersionThishandbooksupportsCore1588version2.
0.
SupportedDeviceFamiliesSmartFusionSupportedInterfacesRMIICore1588monitorstheRMIIinterfacebetweenaMACandPHYanddetectsthetransmissionandreceptionofIEEE1588frames.
ThecoretakesinalltheRMIIsignalsasinputsandsodoesnotpresentafunctionalRMIIinterface.
TransmitandreceiverelatedRMIIsignalsalikeareinputstoCore1588.
APBAnAPB(version3)interfaceisincludedonthecoretoallowasystemprocessortoaccessvariouscontrolandstatusregistersinthecore.
SupportedToolFlowsCore1588requiresLiberov9.
1SP2orlater.
UtilizationandPerformanceAsummaryofutilizationandperformanceinformationforCore1588islistedinTable1throughTable3.
Table1Core1588DeviceUtilizationandPerformance(MinimumConfiguration)FamilyTilesUtilizationPerformance(MHz)SequentialCombinatorialTotalDeviceTotal%PCLKRMII_CLKSmartFusion81411841998A2F200M3F4410090Note:Datainthistablewereachievedusingtypicalsynthesisandlayoutsettings.
Toplevelconfigurationparametersweresettotheirdefaultvalues.
SupportedInterfacesCore1588v2.
0Handbook7Table2Core1588DeviceUtilizationandPerformance(TypicalConfiguration)FamilyTilesUtilizationPerformance(MHz)SequentialCombinatorialTotalDeviceTotal%PCLKRMII_CLKSmartFusion94814362384A2F200M3F5210085Note:Datainthistablewereachievedusingtypicalsynthesisandlayoutsettings.
Toplevelconfigurationparametersthatdifferfromtheirdefaultvaluesweresetasfollows:TRIG_NUM=1,LATCH_NUM=1.
Table3Core1588DeviceUtilizationandPerformance(MaximumConfiguration)FamilyTilesUtilizationPerformance(MHz)SequentialCombinatorialTotalDeviceTotal%PCLKRMII_CLKSmartFusion121719743191A2F200M3F7010080Note:Datainthistablewereachievedusingtypicalsynthesisandlayoutsettings.
Toplevelconfigurationparametersthatdifferfromtheirdefaultvaluesweresetasfollows:TRIG_NUM=3,LATCH_NUM=3.
Core1588v2.
0Handbook9DesignDescriptionDesignImplementationFigure2showsanoverviewofCore1588.
Figure2OverviewofCore1588DesignDescription10Core1588v2.
0HandbookRTCCore1588containsanRTCwitha32bitnanosecondscounteranda32bitsecondscounter.
Whenthenanosecondscounterreaches1x109,itrevertstozeroandthesecondscounterincrementsby1.
Throughthecore'sAPBinterface,thesystemprocessorcansettheRTCvaluedirectlyaswellasspeeduporslowdowntheRTCrate.
WritingtotheRTCLandRTCMregisterssetstheRTCvalue.
ThevaluewrittentoRTCLisusedtoupdatethe32bitnanosecondscounterandthevaluewrittentoRTCMupdatesthe32bitsecondscounter.
TheRTCLregistershouldbewrittentofirst,followedbyawritetotheRTCMregister.
ThewritetoRTCLonlytakeseffectwhentheRTCMregisteriswrittento.
Inthisway,all64bitsoftheRTCareupdatedonthesameclockcycle.
WhenreadingtheRTC,RTCLshouldbereadfirstfollowedbytheRTCMregister.
ReadingtheRTCLregistercausesasnapshottobetakenofthe32bitsecondscounterandthissnapshotvalueisreturnedonthesubsequentreadoftheRTCM.
ThismechanismensuresthattheRTCMandRTCLvaluesarecoincident.
TheRTCisclockedbythe50MHzRMII_CLKsignal.
OneachrisingedgeofRMII_CLKthenanosecondscountincreasesby20,whennoadjustmentisapplied.
SpeedinguporslowingdownoftheRTCcanbeachievedbyaddingmoreorlessthan20tothecountonsomerisingedgesofRMII_CLK.
TheADJUSTregisterisusedtocontroladjustmentoftheRTC.
Thisregistercontainsafivebitadjustmentvaluetoaddtothenanosecondscount(whennotaddingthedefaultof20),anenablebitand24bitsforacounterrollovervalue.
(Theremainingtwobitsofthe32bitADJUSTregisterarereserved.
)Whentheenablebitisset,the24bitcounterrollovervalueisusedinconjunctionwithanindependent24bitcounter,alsoclockedbyRMII_CLK.
Thiscounterincrementsby1oneachRMII_CLKrisingedgeandwhenitsvaluematchesthe24bitvalueheldintheADJUSTregisterthecounterreturnstozeroandbeginstoincrementagain.
Atthesametime,theadjustmentvalueheldintheupperfivebitsoftheADJUSTregisterisaddedtotheRTCnanosecondscountinsteadoftheusualvalueof20.
Inthiswaythenanosecondscountcanoccasionallybeupdatedbyanamountgreaterthanorlessthan20,essentiallyallowingtheRTCtobespeededuporsloweddown.
TheamountbywhichtheRTCisspeduporsloweddownisafunctionofhowmuchtheadjustmentvaluediffersfrom20andhowoftentheadjustmentvalueisusedinsteadofthedefaultof20.
Thislattervariableisdeterminedbythe24bitcounterrollovervalueintheADJUSTregister.
Thelowerthisvalue,themoreoftentheadjustmentvaluewillbeusedinsteadof20.
Theadjustmentvaluecanrangefrom0to31.
Figure3givesaconceptualoverviewofhowtheADJUSTregisterisusedtoinfluencetherateatwhichtheRTCvalueincreases.
DesignImplementationCore1588v2.
0Handbook11Figure3RoleoftheADJUSTRegisterinControllingRTCRateParsingofRMIITrafficTwofinitestatemachinesareusedwithinCore1588forparsingtransmitandreceivetrafficontheRMIIinterface.
Thecoresupportsfullduplexoperation.
WhencertainIEEE1588framesaredetected,thecorerecordsatimestampfortherelevantframealongwithsomeidentificationfieldsfromtheframe.
AtimestampissimplyarecordoftheRTCvalueatthetimewhenaparticularpointoftheframetraversestheMAC-PHYinterface.
ThetimestampreferencepointisdefinedbyIEEE1588asthebeginningofthefirstsymbolaftertheStartofFrame(SOF)delimiter.
Figure4illustratesthepositionofthetimestampreferencepointintermsofRMIIsignals.
Figure4IEEE15888TimestampReferencePointFramesofInterestCore1588onlyrespondstocertainIEEE1588frames,partlydependingonwhetheritisoperatinginmasterorslavemode.
TheMST_ENbitoftheGCFGregisterdeterminesthemodeofoperationofthecore.
Core1588onlydetectstransmissionofSyncframeswheninmastermode.
Core1588onlydetectstransmissionofDelay_Reqframeswheninslavemode.
DesignDescription12Core1588v2.
0HandbookTransmissionofPdelay_ReqandPdelay_Respframesisdetectedregardlessofwhetherthecoreisoperatinginmasterorslavemode.
ReceptionofSync,Delay_Req,Pdelay_Req,Pdelay_RespandFollow_Upframesisalwaysdetectedinbothmasterandslavemode.
WhenreceiptofaframeofinterestisdetectedtheRIRTSbitoftheRawInterruptStatus(RIS)registerissetto'1'andwhentransmissionofaframeofinterestisdetectedtheRITTSbitoftheRISregisterissetto'1'.
Thesebitsmustbeclearedbyfirmwarebeforethereceipt/transmissionofanotherframeofinterestcanbedetectedandtimestamped.
ItisenvisagedthatfirmwarewillcleartheRIRTSorRITTSbitafterreadingtherelevanttimestampregisters.
ThetimestampregistersassociatedwithareceivedframeareRTSLandRTSM,andthetimestampregistersforatransmittedframeareTTSLandTTSM.
LatchInputsThecorecanbeconfiguredtosupportuptothreelatchinputs.
TheLATCH_NUMparameter,whichcanbesetusingthecore'sconfigurationGUI,controlsthenumberoflatchinputssupported.
Whenarisingedgeisdetectedonalatchinput,thecurrentRTCvalueisrecordedinlatchregistersand,ifenabled,aninterruptisgeneratedbyassertingtheINToutput.
Acircuitclockedbythe50MHzRMII_CLKclocksignalisusedtodetectrisingedgesonthelatchinputs.
IfthesignaldrivingalatchinputisnotintheRMII_CLKclockdomainthenyoumustensurethatthesignalishighformorethanoneRMII_CLKperiod,whichisequivalentto20ns,inorderforarisingedgetobedetectedonthelatchinput.
TheLT0LandLT0MregistersareusedtorecordtheRTCvaluewhenarisingedgeisdetectedontheLATCH0input.
Similarly,theLT1LandLT1MregistersareassociatedwiththeLATCH1inputandtheLT2LandLT2MregistersareassociatedwiththeLATCH2input.
Thereareseparateenablebits(LT0_EN,LT1_ENandLT2_EN)intheGCFGregisterforeachofthelatchregisterpairs.
Ifanyoftheseenablebitsissetto'0'thenthecorrespondinglatchregisterpairwillnotbeupdatedwhenarisingedgeisdetectedontherelevantlatchinput.
Theenablebitsprovideamechanismtoholdavalueinalatchregisterpaireventhoughsubsequentrisingedgesmayoccurontherelevantlatchinput.
Forexample,iftheLT0_ENbitis'0'thentheLT0LandLT0MregisterswillnotbeupdatedwhenarisingedgeoccursontheLATCH0input.
TheIELT0,IELT1andIELT2bitsoftheInterruptEnableRegister(IER)areusedtocontrolwhetherornotrisingedgesonthelatchinputscauseaninterrupttobegenerated.
TriggerOutputsUptothreetriggeroutputscanbeprovidedbythecorewhenitisappropriatelyconfigured.
TheTRIG_NUMparameter,whichcanbesetusingthecore'sconfigurationGUI,controlsthenumberoftriggeroutputssupported.
WhentheRTCreachesapresettriggervalue,apulseisgeneratedonthecorrespondingtriggeroutput,providedthatpulsegenerationhasbeenenabledfortherelevanttriggeroutput.
ThepulseisaoneclockcyclepulseintheRMII_CLKclockdomain.
TheTT0_EN,TT1_ENandTT2_ENbitsoftheGCFGregistercontrolwhetherornotpulsesaregeneratedonthetriggeroutputs.
Aninterruptcanalsobegeneratedonreachingatriggertime.
TheIETT0,IETT1andIETT2bitsoftheInterruptEnableRegister(IER)controlwhetherornotaninterruptisgeneratedonatimematch.
TheTT0LandTT0MregistersstorethematchtimefortheTRIG0output.
TheTT1LandTT1MregistersrelatetotheTRIG1output,andtheTT2LandTT2MregistersrelatetotheTRIG2output.
InterruptsCore1588caninterruptthesystemprocessorwhenvariouseventsoccur.
TheInterruptEnableRegister(IER)andtheMaskedInterruptStatus(MIS)registercanbeaccessedbythesystemprocessortoenableordisableinterruptsandtoidentifythesourceofanypendinginterrupt.
ThecorecangenerateaninterruptwhenaframeofinterestisdetectedontheRMIIinterfaceorwhenalatchortriggereventoccurs.
SeethedescriptionsfortheIERandMISregistersformoredetailsonthebitswithintheseregisters.
Interruptsareclearedbywritinga'1'totheappropriatebitpositionorpositionsintheRawInterruptStatus(RIS)register.
DesignImplementationCore1588v2.
0Handbook13TheRIRTS/RITTSbitoftheRISregisterwillbesetondetectionofthereceipt/transmissionofanIEEE1588frameofinterest.
TheRIRTS/RITTSbitmustbeclearedbyfirmwarebeforereceipt/transmissionofanotherframeofinterestcanbedetectedandtimestamped.
ResetSynchronizationTheactivelowAPBresetinput(PRESETN)tothecoreissynchronizedtotheRMII_CLKclockdomainwithinthecoretocreatearesetsignalforlogicclockedbyRMII_CLK.
PRESETNshouldbeasserted(low)foratimeexceedingoneperiodofRMII_CLK,whichisequivalentto20ns,toensurethatlogicintheRMII_CLKdomainisresetsuccessfully.
Core1588v2.
0Handbook15Programmer'sModelRegisterSummaryTable4RegisterSummaryAddressOffsetRegisterNameTypeWidthResetValueDescription0x00GCFGR/W320x00000000Generalconfigurationregister.
0x04IERR/W320x00000000Interruptenableregister.
0x08MISR320x00000000Maskedinterruptstatusregister.
0x0CRISR/W320x00000000Rawinterruptstatusregister.
0x10TTSLR320x00000000Transmittimestampleastsignificantword.
0x14TTSMR320x00000000Transmittimestampmostsignificantword.
0x18TTSIDR320x00000000Transmittimestampidentificationregister.
Containsthe16bitsequenceIDandthe16portnumberofthesourcePortIdentity.
0x1CRTSLR320x00000000Receivetimestampleastsignificantword.
0x20RTSMR320x00000000Receivetimestampmostsignificantword.
0x24RTSID2R320x00000000Receivetimestampidentificationregister2.
Containsthe16bitsequenceId,andthe16bitportnumberofthesourcePortIdentity.
0x28RTSID1R320x00000000Receivetimestampidentificationregister1.
Containsbits[63:32]ofthesourcePortIdentity.
0x2CRTSID0R320x00000000Receivetimestampidentificationregister0.
Containsbits[31:0]ofthesourcePortIdentity.
0x30RTCLR/W320x00000000RTCleastsignificantword.
32bitnanosecondscount.
WhenwritingtotheRTC,theRTCLregistershouldalwaysbewrittenfirst,followedbyawritetotheRTCMregister.
WhenreadingtheRTCvalue,theRTCLregistershouldalwaysbereadfirst,followedbyareadoftheRTCMregister.
0x34RTCMR/W320x00000000RTCmostsignificantword.
32bitsecondscount.
WhenwritingtotheRTC,theRTCLregistershouldalwaysbewrittenfirst,followedbyawritetotheRTCMregister.
WhenreadingtheRTCvalue,theRTCLregistershouldalwaysbereadfirst,followedbyareadoftheRTCMregister.
0x38ADJUSTR/W320xA0000000RTCadjustmentcontrolregister.
ThiscontrolregistercanbeusedtoadjustthespeedoftheRTC.
Seethedetaileddescriptionofthisregisterformoredetails.
Programmer'sModel16Core1588v2.
0Handbook0x3C----Reserved0x40TT0LR/W320x00000000Timetrigger0leastsignificantword.
WhenenabledandtheTT0LandTT0MregistersmatchtheRTCvalue,apulseisgeneratedontheTRIG0output.
0x44TT0MR/W320x00000000Timetrigger0mostsignificantword.
WhenenabledandtheTT0LandTT0MregistersmatchtheRTCvalue,apulseisgeneratedontheTRIG0output.
0x48TT1LR/W320x00000000Timetrigger1leastsignificantword.
WhenenabledandtheTT1LandTT1MregistersmatchtheRTCvalue,apulseisgeneratedontheTRIG1output.
0x4CTT1MR/W320x00000000Timetrigger1mostsignificantword.
WhenenabledandtheTT1LandTT1MregistersmatchtheRTCvalue,apulseisgeneratedontheTRIG1output.
0x50TT2LR/W320x00000000Timetrigger2leastsignificantword.
WhenenabledandtheTT2LandTT2MregistersmatchtheRTCvalue,apulseisgeneratedontheTRIG2output.
0x54TT2MR/W320x00000000Timetrigger2mostsignificantword.
WhenenabledandtheTT2LandTT2MregistersmatchtheRTCvalue,apulseisgeneratedontheTRIG2output.
0x58LT0LR320x00000000Latch0leastsignificantword.
WhenenabledandarisingedgeisdetectedontheLATCH0input,LT0LstorestheLSWoftheRTC.
0x5CLT0MR320x00000000Latch0mostsignificantword.
WhenenabledandarisingedgeisdetectedontheLATCH0input,LT0MstorestheMSWoftheRTC.
0x60LT1LR320x00000000Latch1leastsignificantword.
WhenenabledandarisingedgeisdetectedontheLATCH1input,LT1LstorestheLSWoftheRTC.
0x64LT1MR320x00000000Latch1mostsignificantword.
WhenenabledandarisingedgeisdetectedontheLATCH1input,LT1MstorestheMSWoftheRTC.
0x68LT2LR320x00000000Latch2leastsignificantword.
WhenenabledandarisingedgeisdetectedontheLATCH2input,LT2LstorestheLSWoftheRTC.
0x6CLT2MR320x00000000Latch2mostsignificantword.
WhenenabledandarisingedgeisdetectedontheLATCH2input,LT2MstorestheMSWoftheRTC.
GeneralConfigurationRegisterCore1588v2.
0Handbook17GeneralConfigurationRegisterTable5GeneralConfigurationRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x00GCFGR/W320x00000000Generalcoreconfigurationregister.
Table6GeneralConfigurationRegisterBitDefinitionsBitsNameTypeDescription31:16Reserved15LT2_ENR/W0:Disablelatch2timestampregisters1:Enablelatch2timestampregistersThisbitmustbesetto'1'inorderfortheLT2LandLT2MregisterstobeupdatedwiththeRTCvaluewhenarisingedgeisobservedontheLATCH2input.
14LT1_ENR/W0:Disablelatch1timestampregisters1:Enablelatch1timestampregistersThisbitmustbesetto'1'inorderfortheLT1LandLT1MregisterstobeupdatedwiththeRTCvaluewhenarisingedgeisobservedontheLATCH1input.
13LT0_ENR/W0:Disablelatch0timestampregisters1:Enablelatch0timestampregistersThisbitmustbesetto'1'inorderfortheLT0LandLT0MregisterstobeupdatedwiththeRTCvaluewhenarisingedgeisobservedontheLATCH0input.
12TT2_ENR/W0:DisableTRIG2output1:EnableTRIG2outputThisbitmustbesetto'1'inorderforapulsetobegeneratedontheTRIG2outputwhentheRTCvaluereachesthetimesetintheTT2LandTT2Mregisters.
11TT1_ENR/W0:DisableTRIG1output1:EnableTRIG1outputThisbitmustbesetto'1'inorderforapulsetobegeneratedontheTRIG1outputwhentheRTCvaluereachesthetimesetintheTT1LandTT1Mregisters.
10TT0_ENR/W0:DisableTRIG0output1:EnableTRIG0outputThisbitmustbesetto'1'inorderforapulsetobegeneratedontheTRIG0outputwhentheRTCvaluereachesthetimesetintheTT0LandTT0Mregisters.
9:4Reserved3MST_ENR/W0:Coreisoperatinginslavemode1:Coreisoperatinginmastermode2:1Reserved0ENCORR/W0:Disablecore1:EnablecoreProgrammer'sModel18Core1588v2.
0HandbookInterruptEnableRegisterTable7InterruptEnableRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x04IERR/W320x00000000InterruptenableregisterTable8InterruptEnableRegisterBitDefinitionsBitsNameTypeDescription31:8Reserved7IELT2R/W0:Disablelatch2interrupt(ILT2)1:Enablelatch2interrupt(ILT2)6IELT1R/W0:Disablelatch1interrupt(ILT1)1:Enablelatch1interrupt(ILT1)5IELT0R/W0:Disablelatch0interrupt(ILT0)1:Enablelatch0interrupt(ILT0)4IETT2R/W0:Disabletrigger2interrupt(ITT2)1:Enabletrigger2interrupt(ITT2)3IETT1R/W0:Disabletrigger1interrupt(ITT1)1:Enabletrigger1interrupt(ITT1)2IETT0R/W0:Disabletrigger0interrupt(ITT0)1:Enabletrigger0interrupt(ITT0)1IERTSR/W0:Disablereceivetimestampinterrupt(IRTS)1:Enablereceivetimestampinterrupt(IRTS)0IETTSR/W0:Disabletransmittimestampinterrupt(ITTS)1:Enabletransmittimestampinterrupt(ITTS)MaskedInterruptStatusRegisterTable9MaskedInterruptStatusRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x08MISR320x00000000MaskedinterruptstatusregisterTable10MaskedInterruptStatusRegisterBitDefinitonsBitsNameTypeDescription31:8Reserved7ILT2RThisbitisthelogicalANDofbit7ofIERandbit7ofRIS6ILT1RThisbitisthelogicalANDofbit6ofIERandbit6ofRIS5ILT0RThisbitisthelogicalANDofbit5ofIERandbit5ofRIS4ITT2RThisbitisthelogicalANDofbit4ofIERandbit4ofRIS3ITT1RThisbitisthelogicalANDofbit3ofIERandbit3ofRIS2ITT0RThisbitisthelogicalANDofbit2ofIERandbit2ofRIS1IRTSRThisbitisthelogicalANDofbit1ofIERandbit1ofRIS0ITTSRThisbitisthelogicalANDofbit0ofIERandbit0ofRISNote:AllthebitsoftheMaskedInterruptStatusregisterareORedtogethertogeneratetheINToutputfromthecore.
RawInterruptStatusRegisterCore1588v2.
0Handbook19RawInterruptStatusRegisterTable11RawInterruptStatusRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x0CRISR/W320x00000000RawInputStatusRegisterTable12RawInterruptStatusRegisterBitDefinitionsBitsNameTypeDescription31:8Reserved7RILT2R/WWhenthisbithasavalueof'1'itindicatesthatarisingedgehasbeenobservedontheLATCH2inputsincethisbitwaslast'0'.
Thisbitisclearedbywriting'1'toit.
Writing'0'hasnoeffect.
6RILT1R/WWhenthisbithasavalueof'1'itindicatesthatarisingedgehasbeenobservedontheLATCH1inputsincethisbitwaslast'0'.
Thisbitisclearedbywriting'1'toit.
Writing'0'hasnoeffect.
5RILT0R/WWhenthisbithasavalueof'1'itindicatesthatarisingedgehasbeenobservedontheLATCH0inputsincethisbitwaslast'0'.
Thisbitisclearedbywriting'1'toit.
Writing'0'hasnoeffect.
4RITT2R/WWhenthisbithasavalueof'1'itindicatesthatthetimesetinthetrigger2registers(TT2LandTT2M)hasbeenreachedsincethisbitwaslast'0'.
Thisbitisclearedbywriting'1'toit.
Writing'0'hasnoeffect.
3RITT1R/WWhenthisbithasavalueof'1'itindicatesthatthetimesetinthetrigger1registers(TT1LandTT1M)hasbeenreachedsincethisbitwaslast'0'.
Thisbitisclearedbywriting'1'toit.
Writing'0'hasnoeffect.
2RITT0R/WWhenthisbithasavalueof'1'itindicatesthatthetimesetinthetrigger0registers(TT0LandTT0M)hasbeenreachedsincethisbitwaslast'0'.
Thisbitisclearedbywriting'1'toit.
Writing'0'hasnoeffect.
1RIRTSR/WWhenthisbithasavalueof'1'itindicatesthat,sincethisbitwaslast'0',receiptofanIEEE1588framehasbeendetectedandthatthereceivetimestampregisters(RTSLandRTSM)havebeenupdated.
Thisbitisclearedbywriting'1'toit.
Writing'0'hasnoeffect.
Note:Afterthisbithasbeensetto'1'bytheframedetectionhardware,itmustbeclearedbyfirmwarebeforereceiptofanotherframecanbedetected.
ItisenvisagedthatfirmwarewillclearthisbitafterreadingtheRTSLandRTSMregisters.
0RITTSR/WWhenthisbithasavalueof'1'itindicatesthat,sincethisbitwaslast'0',transmissionofanIEEE1588framehasbeendetectedandthatthetransmittimestampregisters(TTSLandTTSM)havebeenupdated.
Thisbitisclearedbywriting'1'toit.
Writing'0'hasnoeffect.
Note:Afterthisbithasbeensetto'1'bytheframedetectionhardware,itmustbeclearedbyfirmwarebeforetransmissionofanotherframecanbedetected.
ItisenvisagedthatfirmwarewillclearthisbitafterreadingtheTTSLandTTSMregisters.
TransitTimestampLeastSignificantWordRegisterTable13TransitTimestampLSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x10TTSLR320x00000000TransittimestampleastsignificantwordProgrammer'sModel20Core1588v2.
0HandbookTransitTimestampMostSignificantWordRegisterTable14TransitTimestampMSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x14TTSMR320x00000000TransittimestampmostsignificantwordTransitTimestampIdentificationRegisterTable15TransitTimestampIdentificationRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x18TTSIDR320x00000000Transittimestampidentificationregister.
Containsthe16bitsequenceIDandthe16portnumberofthesourcePortIdentity.
Table16TransitTimestampIdentificationRegisterBitDefinitionsBitsNameTypeDescription31:16TTSSIDRStoresthesequenceIDfromthemessageheaderoftheframeassociatedwiththecurrenttransittimestamp(intheTTSLandTTSMregisters)15:0TTSPNRStorestheportnumberfromthemessageheaderoftheframeassociatedwiththecurrenttransmittimestamp(intheTTSLandTTSMregisters).
(TheportnumberispartofthesourcePortIdentityfieldoftheIEEE1588messageheader.
)ReceiveTimestampLeastSignificantWordRegisterTable17ReceiveTimestampLSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x1CRTSLR320x00000000ReceivetimestampleastsignificantwordReceiveTimestampMostSignificantWordRegisterTable18ReceiveTimestampMSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x20RTSMR320x00000000ReceivetimestampmostsignificantwordReceiveTimestampIdentificationRegister2Table19ReceiveTimestampIdentificationRegister2DescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x24RTSID2R320x00000000Receivetimestampidentificationregister2.
Containsthe16bitsequenceIdandthe16bitportnumberofthesourcePortIdentity.
ReceiveTimestampIdentificationRegister1Core1588v2.
0Handbook21Table20ReceiveTimestampIdentificationRegister2BitDefinitionsBitsNameTypeDescription31:16RTSSIDRStoresthesequenceIDfromthemessageheaderoftheframeassociatedwiththecurrentreceivetimestamp(intheRTSLandRTSMregisters).
15:0RTSPNRStorestheportnumberfromthemessageheaderoftheframeassociatedwiththecurrentreceivetimestamp(intheRTSLandRTSMregisters).
(TheportnumberispartofthesourcePortIdentityfieldoftheIEEE1588messageheader.
)ReceiveTimestampIdentificationRegister1Table21ReceiveTimestampIdentificationRegister1DescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x28RTSID1R320x00000000Receivetimestampidentificationregister1.
Containsbits[63:32]ofthesourcePortIdentity.
ReceiveTimestampIdentificationRegister0Table22ReceiveTimestampIdentificationRegister0DescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x2CRTSID0R320x00000000Receivetimestampidentificationregister0.
Containsbits[31:0]ofthesourcePortIdentity.
RTCLeastSignificantWordRegisterTable23RTCLSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x30RTCLR/W320x00000000RTCleastsignificantword.
32bitnanosecondscount.
WhenwritingtotheRTC,theRTCLregistershouldalwaysbewrittenfirst,followedbyawritetotheRTCMregister.
WhenreadingtheRTCvalue,theRTCLregistershouldalwaysbereadfirst,followedbyareadoftheRTCMregister.
Programmer'sModel22Core1588v2.
0HandbookRTCMostSignificantWordRegisterTable24RTCMSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x34RTCMR/W320x00000000RTCmostsignificantword.
32bitsecondscount.
WhenwritingtotheRTC,theRTCLregistershouldalwaysbewrittenfirst,followedbyawritetotheRTCMregister.
WhenreadingtheRTCvalue,theRTCLregistershouldalwaysbereadfirst,followedbyareadoftheRTCMregister.
AdjustmentRegisterTable25AdjustmentRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x38ADJUSTR/W320xA0000000ThiscontrolregistercanbeusedtoadjustthespeedoftheRTC.
Seethedetaileddescriptionofthisregisterformoredetails.
Table26AdjustmentRegisterBitDefinitionsBitsNameTypeDescription31:27ADJVALR/WThisfivebitfieldholdstheamounttobeaddedtoRTCleastsignificantword(nanosecondscount)eachtimetheadjustmentcounterreturnstozero(andtheADJENbitissetto1).
TheRTCoperatesinthe50MHzRMII_CLKclockdomainandthenanosecondscountnormallyincrementsby20oneachrisingedgeofRMII_CLK.
Whentheconditionsdescribedabovearemet,theRTCwillbeincrementedbythevaluestoredinADJVAL,insteadofbythenormalamountof20.
ThevaluestoredinADJVALcanrangefrom0to31.
UsingadjustmentwithanADJVALvaluelessthan20willresultinaslowingdownoftheRTC.
Similarly,usingadjustmentwithanADJVALgreaterthan20willcausetheRTCtospeedup.
TheamountofslowingdownorspeedingupisafunctionofboththeADJVALvalueandtheADJCMvalue.
26ADJENR/W0:Adjustmentfeatureisdisabled1:Adjustmentfeatureisenabled25:24--Reserved23:0ADJCMR/WAdjustmentcountermaximumvalue.
Thisfieldsetstherollovervaluefora24bitadjustmentcounterclockedbyRMII_CLK.
Theadjustmentcounterisessentiallyafreerunningcounterthatincrementsby1oneachrisingedgeofRMII_CLK.
WhenthecountervaluereachestheADJCMvalueitreturnstozeroand,iftheADJENbitisset,theRTCnanosecondscountisincrementedbytheADJVALinsteadofbythenormalamountof20.
TheADJCMfieldessentiallycontrolshowfrequentlytheADJVALisusedastheRTCincrement.
TimeTrigger0LeastSignificantWordRegisterCore1588v2.
0Handbook23TimeTrigger0LeastSignificantWordRegisterTable27TimeTrigger0LSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x40TT0LR/W320x00000000Timetrigger0leastsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport1ormoretriggeroutputs(TRIG_NUMparametersetto1orgreater).
WhentheRTCvalue(RTCL&RTCM)reachesthetimesetintheTT0LandTT0Mregisters,theRITT0bitoftheRISregisterwillbesetto'1'(orwillremainat'1'ifitisalready'1').
Aninterruptcanbegeneratedonthetimematch(dependingonthevalueoftheIETT0bitoftheIER)and/orapulsecanbegeneratedontheTRIG0output(dependingonthevalueoftheTT0_ENbitoftheGCFGregister).
TimeTrigger0MostSignificantWordRegisterTable28TimeTrigger0MSWRegisterDefinitionAddressOffsetRegisterNameTypeWidthResetValueDescription0x44TT0MR/W320x00000000Timetrigger0mostsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport1ormoretriggeroutputs(TRIG_NUMparametersetto1orgreater).
WhentheRTCvalue(RTCL&RTCM)reachesthetimesetintheTT0LandTT0Mregisters,theRITT0bitoftheRISregisterwillbesetto'1'(orwillremainat'1'ifitisalready'1').
Aninterruptcanbegeneratedonthetimematch(dependingonthevalueoftheIETT0bitoftheIER)and/orapulsecanbegeneratedontheTRIG0output(dependingonthevalueoftheTT0_ENbitoftheGCFGregister).
Programmer'sModel24Core1588v2.
0HandbookTimeTrigger1LeastSignificantWordRegisterTable29TimeTrigger1LSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x48TT1LR/W320x00000000Timetrigger1leastsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport2ormoretriggeroutputs(TRIG_NUMparametersetto2orgreater).
WhentheRTCvalue(RTCL&RTCM)reachesthetimesetintheTT1LandTT1Mregisters,theRITT1bitoftheRISregisterwillbesetto'1'(orwillremainat'1'ifitisalready'1').
Aninterruptcanbegeneratedonthetimematch(dependingonthevalueoftheIETT1bitoftheIER)and/orapulsecanbegeneratedontheTRIG1output(dependingonthevalueoftheTT1_ENbitoftheGCFGregister).
TimeTrigger1MostSignificantWordRegisterTable30TimeTrigger1MSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x4CTT1MR/W320x00000000Timetrigger1mostsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport2ormoretriggeroutputs(TRIG_NUMparametersetto2orgreater).
WhentheRTCvalue(RTCL&RTCM)reachesthetimesetintheTT1LandTT1Mregisters,theRITT1bitoftheRISregisterwillbesetto'1'(orwillremainat'1'ifitisalready'1').
Aninterruptcanbegeneratedonthetimematch(dependingonthevalueoftheIETT1bitoftheIER)and/orapulsecanbegeneratedontheTRIG1output(dependingonthevalueoftheTT1_ENbitoftheGCFGregister).
TimeTrigger2LeastSignificantWordRegisterCore1588v2.
0Handbook25TimeTrigger2LeastSignificantWordRegisterTable31TimeTrigger2LSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x50TT2LR/W320x00000000Timetrigger2leastsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport3triggeroutputs(TRIG_NUMparametersetto3).
WhentheRTCvalue(RTCL&RTCM)reachesthetimesetintheTT2LandTT2Mregisters,theRITT2bitoftheRISregisterwillbesetto'1'(orwillremainat'1'ifitisalready'1').
Aninterruptcanbegeneratedonthetimematch(dependingonthevalueoftheIETT2bitoftheIER)and/orapulsecanbegeneratedontheTRIG2output(dependingonthevalueoftheTT2_ENbitoftheGCFGregister).
TimeTrigger2MostSignificantWordRegisterTable32TimeTrigger2MSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x54TT2MR/W320x00000000Timetrigger2mostsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport3triggeroutputs(TRIG_NUMparametersetto3).
WhentheRTCvalue(RTCL&RTCM)reachesthetimesetintheTT2LandTT2Mregisters,theRITT2bitoftheRISregisterwillbesetto'1'(orwillremainat'1'ifitisalready'1').
Aninterruptcanbegeneratedonthetimematch(dependingonthevalueoftheIETT2bitoftheIER)and/orapulsecanbegeneratedontheTRIG2output(dependingonthevalueoftheTT2_ENbitoftheGCFGregister).
Programmer'sModel26Core1588v2.
0HandbookLatch0LeastSignificantWordRegisterTable33Latch0LSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x58LT0LR320x00000000Latch0leastsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport1ormorelatchinputs(LATCH_NUMparametersetto1orgreater).
WhenarisingedgeisdetectedontheLATCH0input,thevalueintheRTCLregisterwillbestoredinthisregisteriftheLT0_ENbitoftheGCFGregisterissetto'1'.
ThisregisterwillholditscurrentvalueiftheLT0_ENbitoftheGCFGregisteris'0'.
ThedetectionofarisingedgeontheLATCH0inputwillalsocausetheRILT0bitoftheRISregistertobesetto'1'(ifitisnotalreadysetto'1').
ThiscaninturncauseassertionoftheINTinterruptoutputiftheIELT0bitoftheIERissetto'1'.
Latch0MostSignificantWordRegisterTable34Latch0MSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x5CLT0MR320x00000000Latch0mostsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport1ormorelatchinputs(LATCH_NUMparametersetto1orgreater).
WhenarisingedgeisdetectedontheLATCH0input,thevalueintheRTCMregisterwillbestoredinthisregisteriftheLT0_ENbitoftheGCFGregisterissetto'1'.
ThisregisterwillholditscurrentvalueiftheLT0_ENbitoftheGCFGregisteris'0'.
ThedetectionofarisingedgeontheLATCH0inputwillalsocausetheRILT0bitoftheRISregistertobesetto'1'(ifitisnotalreadysetto'1').
ThiscaninturncauseassertionoftheINTinterruptoutputiftheIELT0bitoftheIERissetto'1'.
Latch1LeastSignificantWordRegisterCore1588v2.
0Handbook27Latch1LeastSignificantWordRegisterTable35Latch1LSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x60LT1LR320x00000000Latch1leastsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport2ormorelatchinputs(LATCH_NUMparametersetto2orgreater).
WhenarisingedgeisdetectedontheLATCH1input,thevalueintheRTCLregisterwillbestoredinthisregisteriftheLT1_ENbitoftheGCFGregisterissetto'1'.
ThisregisterwillholditscurrentvalueiftheLT1_ENbitoftheGCFGregisteris'0'.
ThedetectionofarisingedgeontheLATCH1inputwillalsocausetheRILT1bitoftheRISregistertobesetto'1'(ifitisnotalreadysetto'1').
ThiscaninturncauseassertionoftheINTinterruptoutputiftheIELT0bitoftheIERissetto'1'.
Latch1MostSignificantWordRegisterTable36Latch1MSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x64LT1MR320x00000000Latch1mostsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport2ormorelatchinputs(LATCH_NUMparametersetto2orgreater).
WhenarisingedgeisdetectedontheLATCH1input,thevalueintheRTCMregisterwillbestoredinthisregisteriftheLT1_ENbitoftheGCFGregisterissetto'1'.
ThisregisterwillholditscurrentvalueiftheLT1_ENbitoftheGCFGregisteris'0'.
ThedetectionofarisingedgeontheLATCH1inputwillalsocausetheRILT1bitoftheRISregistertobesetto'1'(ifitisnotalreadysetto'1').
ThiscaninturncauseassertionoftheINTinterruptoutputiftheIELT1bitoftheIERissetto'1'.
Programmer'sModel28Core1588v2.
0HandbookLatch2LeastSignificantWordRegisterTable37Latch2LSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x68LT2LR320x00000000Latch2leastsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport3latchinputs(LATCH_NUMparametersetto3).
WhenarisingedgeisdetectedontheLATCH2input,thevalueintheRTCLregisterwillbestoredinthisregisteriftheLT2_ENbitoftheGCFGregisterissetto'1'.
ThisregisterwillholditscurrentvalueiftheLT2_ENbitoftheGCFGregisteris'0'.
ThedetectionofarisingedgeontheLATCH2inputwillalsocausetheRILT2bitoftheRISregistertobesetto'1'(ifitisnotalreadysetto'1').
ThiscaninturncauseassertionoftheINTinterruptoutputiftheIELT2bitoftheIERissetto'1'.
Latch2MostSignificantWordRegisterTable38Latch2MSWRegisterDescriptionAddressOffsetRegisterNameTypeWidthResetValueDescription0x6CLT2MR320x00000000Latch2mostsignificantword.
Thisregisterisonlyrelevantifthecorehasbeenconfiguredtosupport3latchinputs(LATCH_NUMparametersetto3).
WhenarisingedgeisdetectedontheLATCH2input,thevalueintheRTCMregisterwillbestoredinthisregisteriftheLT2_ENbitoftheGCFGregisterissetto'1'.
ThisregisterwillholditscurrentvalueiftheLT2_ENbitoftheGCFGregisteris'0'.
ThedetectionofarisingedgeontheLATCH2inputwillalsocausetheRILT2bitoftheRISregistertobesetto'1'(ifitisnotalreadysetto'1').
ThiscaninturncauseassertionoftheINTinterruptoutputiftheIELT2bitoftheIERissetto'1'.
Core1588v2.
0Handbook29InterfacesParametersTable39Core1588ParameterDescriptionsParameterNameValidRangeDefaultValueDescriptionTRIG_NUM0to30NumberoftriggeroutputsLATCH_NUM0to30NumberoflatchinputsPortsTable40Core1588PortDescriptionsParameterNameValidRangeDefaultValuePCLKInAPBclockPRESETNInAPBresetPADDR[6:0]InAPBaddressPSELInAPBselectPENABLEInAPBenablePWRITEInAPBwritePWDATA[31:0]InAPBwritedataPRDATA[31:0]OutAPBreaddataPREADYOutAPBreadyPSLVERROutAPBslaveerrorINTOutInterruptsignalRMII_CLKInRMIIclockRMII_CRSDVInRMIIcarriersense/datavalidRMII_RXD[1:0]InRMIIreceivedataRMII_RXERInRMIIreceiveerrorRMII_TXD[1:0]InRMIItransmitdataRMII_TXENInRMIItransmitenableTRIG0OutTrigger0Aoneclockcyclepulse(intheRMII_CLKclockdomain)isgeneratedonthisoutputwhentheinternalRTCvaluereachesthevaluepresetintheTT0LandTT0Mregisters.
TRIG1OutTrigger1Aoneclockcyclepulse(intheRMII_CLKclockdomain)isgeneratedonthisoutputwhentheinternalRTCvaluereachesthevaluepresetintheTT1LandTT1Mregisters.
TRIG2OutTrigger2Aoneclockcyclepulse(intheRMII_CLKclockdomain)isgeneratedonthisoutputwhentheinternalRTCvaluereachesthevaluepresetintheTT2LandTT2Mregisters.
Interfaces30Core1588v2.
0HandbookLATCH0InLatch0Whenarisingedgeisdetectedonthisinput,thecurrentRTCvalueislatchedintotheLT0LandLT0Mregisters.
LATCH1InLatch1Whenarisingedgeisdetectedonthisinput,thecurrentRTCvalueislatchedintotheLT1LandLT1Mregisters.
LATCH2InLatch2Whenarisingedgeisdetectedonthisinput,thecurrentRTCvalueislatchedintotheLT2LandLT2Mregisters.
Core1588v2.
0Handbook31ToolFlowsLicensingCore1588islicensedintwoways:ObfuscatedandRTL.
ObfuscatedCompleteRTLcodeisprovidedforthecore,enablingthecoretobeinstantiated,configured,andgeneratedwithinSmartDesign.
Simulation,Synthesis,andLayoutcanbeperformedwithLiberoIntegratedDesignEnvironment(IDE).
TheRTLcodeforthecoreisobfuscated.
RTLCompleteRTLsourcecodeisprovidedforthecore.
SmartDesignCore1588isavailablefordownloadtotheSmartDesignIPCatalogviatheLiberoIDEwebrepository.
ForinformationonusingSmartDesigntoinstantiate,configure,connect,andgeneratecores,refertotheLiberoIDEonlinehelp.
Figure5showsanexampleofaninstantiatedviewofCore1588ontheSmartDesigncanvas.
ThecorecanbeconfiguredusingitsconfigurationGUI,asshowninFigure6.
Figure5ExampleInstantiationofCore1588onSmartDesignCanvasToolFlows32Core1588v2.
0HandbookFigure6Core1588ConfigurationGUISimulationFlowSmartDesignandLiberoIDEfacilitaterunningausertestbenchforCore1588.
Toruntheusertestbench,settheTestbenchconfigurationoptiontoUserintheCore1588configurationGUIbeforegeneratingthedesign.
Aftergeneration,setthedesignroottobetheCore1588instanceandclicktheSimulation(ModelSim)button.
ModelSimwilllaunchandruntheunittest.
SynthesisinLiberoIDETorunsynthesiswiththeconfigurationselectedintheconfigurationGUI,setthedesignrootappropriatelyandclicktheSynthesisiconinLiberoIDEtolaunchtheSynplicitysynthesistool.
ClicktheRunbuttoninthesynthesiswindowtorunsynthesis.
PlaceandRouteinLiberoIDEHavingsetthedesignrootappropriatelyandrunSynthesis,clickthePlace&RouteiconinLiberoIDEtoinvokeDesigner.
Core1588v2.
0Handbook33ApplicationHintsConnectingCore1588inSmartDesignThischapterprovidesvarioushintstoeasetheprocessofimplementationandintegrationofCore1588intoyourdesign.
Figure7showsaSmartDesigndesignthatillustratestheconnectionsrequiredbetweenCore1588andtheSmartFusionMSS.
TheMSScomponenthasbeenconfiguredtoprovidetheRMII_CLKclocksignal(viaitsGLCoutput)whichconnectsbothtoCore1588andtothetoplevelofthedesignsothatitcandrivetheexternalPHY.
TheMSShasalsobeenconfiguredtoprovideclockandresetsignalstodrivethePCLKandPRESETNinputsofCore1588andtoprovideaninterruptinput(FABINT)toaccepttheinterruptsignalfromCore1588.
TheMSShasbeenconfiguredtomaketheRMIIMAC-PHYinterfaceavailabletothefabricandthesesignals,namedMAC_0_CAPTURE_*ontheMSScomponent,connecttotheRMII_*inputsofCore1588.
Finally,theMSShasbeenconfiguredtoprovideanAPBmasterinterfacetothefabricandthisconnectstoCore1588'sAPBinterfacethroughtheCoreAPB3buscomponent.
Figure7Core1588SystemExampleCore1588v2.
0Handbook35OrderingInformationOrderingCodesCore1588canbeorderedthroughyourlocalSalesRepresentative.
Itshouldbeorderedusingthefollowingnumberscheme:Core1588-XX,whereXXislistedinTable41.
Table41OrderingCodesXXDescriptionOMRTLforObfuscatedRTL—multipleuselicenseRMRTLforRTLsource—multiple-uselicenseCore1588v2.
0Handbook37ProductSupportMicrosemibacksitsproductswithvarioussupportservicesincludingCustomerService,aCustomerTechnicalSupportCenter,awebsite,anFTPsite,electronicmail,andworldwidesalesoffices.
ThisappendixcontainsinformationaboutcontactingMicrosemiSoCProductsGroup(formerlyActel)andusingthesesupportservices.
CustomerServiceContactCustomerServicefornon-technicalproductsupport,suchasproductpricing,productupgrades,updateinformation,orderstatus,andauthorization.
FromNortheastandNorthCentralU.
S.
A.
,call650.
318.
4480FromSoutheastandSouthwestU.
S.
A.
,call650.
318.
4480FromSouthCentralU.
S.
A.
,call650.
318.
4434FromNorthwestU.
S.
A.
,call650.
318.
4434FromCanada,call650.
318.
4480FromEurope,call650.
318.
4252or+44(0)1276401500FromJapan,call650.
318.
4743Fromtherestoftheworld,call650.
318.
4743Fax,fromanywhereintheworld650.
318.
8044CustomerTechnicalSupportCenterMicrosemistaffsitsCustomerTechnicalSupportCenterwithhighlyskilledengineerswhocanhelpansweryourhardware,software,anddesignquestions.
TheCustomerTechnicalSupportCenterspendsagreatdealoftimecreatingapplicationnotesandanswerstoFAQs.
So,beforeyoucontactus,pleasevisitouronlineresources.
Itisverylikelywehavealreadyansweredyourquestions.
TechnicalSupportVisittheCustomerSupportwebsite(http://www.
actel.
com/support/search/default.
aspx)formoreinformationandsupport.
Manyanswersavailableonthesearchablewebresourceincludediagrams,illustrations,andlinkstootherresourcesonwebsite.
WebsiteYoucanbrowseavarietyoftechnicalandnon-technicalinformationontheSoChomepage,athttp://www.
actel.
com/.
ContactingtheCustomerTechnicalSupportCenterHighlyskilledengineersstafftheTechnicalSupportCenterfrom7:00A.
M.
to6:00P.
M.
,PacificTime,MondaythroughFriday.
SeveralwaysofcontactingtheCenterfollow:EmailYoucancommunicateyourtechnicalquestionstoouremailaddressandreceiveanswersbackbyemail,fax,orphone.
Also,ifyouhavedesignproblems,youcanemailyourdesignfilestoreceiveassistance.
Weconstantlymonitortheemailaccountthroughouttheday.
Whensendingyourrequesttous,pleasebesuretoincludeyourfullname,companyname,andyourcontactinformationforefficientprocessingofyourrequest.
Thetechnicalsupportemailaddressissoc_tech@microsemi.
com.
ProductSupport38Core1588v2.
0HandbookPhoneOurTechnicalSupportCenteranswersallcalls.
Thecenterretrievesinformation,suchasyourname,companyname,phonenumberandyourquestion,andthenissuesacasenumber.
TheCenterthenforwardstheinformationtoaqueuewherethefirstavailableapplicationengineerreceivesthedataandreturnsyourcall.
Thephonehoursarefrom7:00A.
M.
to6:00P.
M.
,PacificTime,MondaythroughFriday.
TheTechnicalSupportnumbersare:650.
318.
4460800.
262.
1060CustomersneedingassistanceoutsidetheUStimezonescaneithercontacttechnicalsupportviaemail(soc_tech@microsemi.
com)orcontactalocalsalesoffice.
Salesofficelistingscanbefoundatwww.
actel.
com/company/contact/default.
aspx.
50200291-0/06.
11MicrosemiCorporateHeadquarters2381MorseAvenue,Irvine,CA92614Phone;949.
221.
7100·Fax:949.
756.
0308www.
microsemi.
comMicrosemiCorporation(NASDAQ:MSCC)offerstheindustry'smostcomprehensiveportfolioofsemiconductortechnology.
Committedtosolvingthemostcriticalsystemchallenges,Microsemi'sproductsincludehigh-performance,high-reliabilityanalogandRFdevices,mixedsignalintegratedcircuits,FPGAsandcustomizableSoCs,andcompletesubsystems.
Microsemiservesleadingsystemmanufacturersaroundtheworldinthedefense,security,aerospace,enterprise,commercial,andindustrialmarkets.
Learnmoreatwww.
microsemi.
com.
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