VDD_LV_CORE_SOCavav234.com

S32V234S32V234DataSheetFeaturesARMCortex-A53,64-bitCPU–Upto1000MHzQuadARMCortex-A53–32KB/32KBI-/D-L1Cache–NEONMPEco-processor–DualprecisionFPU–2clusterswith2CPUsand256KBL2cacheeach–MemoryManagementUnit–GICInterruptController–ECC/parityerrorsupportforitsmemories–Generictimers–FaultencapsulationbyhardwareforredundantexecutedapplicationsoftwareonmultiplecoreclusterARMCortex-M4,32-bitCPU–Upto133MHz–16KB/16KBI-/D-L1Cache–32+32KBtightlycoupledmemory(TCM)–ECC/paritysupportforitsmemoriesClocks–PhaseLockedLoops(PLLs)–1externalcrystaloscillator(FXOSC)–1FIRCoscillatorSystemprotectionandpowermanagementfeatures–Flexiblerunmodestoconsumelowpowerbasedonapplicationneeds–Peripheralclockenableregistercandisableclockstounusedmodules,therebyreducingcurrents–PowergatingofunusedA53coresandGPU–Lowandhighvoltagewarninganddetect–HardwareCRCmoduletosupportfastcyclicredundancychecks(CRC)–120-bituniquechipidentifier–Hardwarewatchdog–eDMAcontrollerwith32channels(withDMAMUX)–ExtendedResourceDomainControllerSafetyconcept–ISO26262,ASILleveltarget–Measurestodetectfaultsinmemoryandlogic–Measurestodetectsinglepointandlatentfaults–Quantitativeoutofcontextanalysisoffunctionalsafety(FMEDA)tailoredtoapplicationspecifics–SafetymanualandFMEDAreportavailableSecurity–CSEwith16KBofon-chipSecureRAMandROM.
–ARMTrustZone(TZ)architecturesupport–BootfromNORflashwithAES-128(CTR)–On-ChipOne-TimeProgrammableelementController(OCOTP_CTRL)withonchipelectricalfusearray.
–SystemJTAGController(SJC)Debugfunctionality–StandardJTAGandCompactJTAG–16-bitTraceport,SerialWireOutputportTimers–Generalpurposetimers(FTM)–TwoPeriodicInterruptTimer(PIT)–IEEE1588Timers(partofEthernetSubsystem)Analog–1x12-bit1.
8VSARADCwithself-testCommunications–UART(w/LIN2.
1l)–Serialperipheralinterface(SPI)–I2Cblocks–PCIexpress2.
0withendpointandrootcomplexsupport–LFASTseriallink–1GBitEthernetwithPTPIEEE1588–FD-CAN–FlexRayDualChannel,Version2.
1RevANXPSemiconductorsDocumentNumberS32V234DataSheet:TechnicalDataRev.
9,03/2020NXPreservestherighttochangetheproductiondetailspecificationsasmayberequiredtopermitimprovementsinthedesignofitsproducts.
Memoryinterfaces–32-bitDRAMControllerwithsupportforLPDDR2/DDR3/DDR3L-Datarateofupto1066MT/sat533MHzclockfrequencywithECC(SEC-DED-TED)tripleerrordetectionsupportforsubregion–QuadSPIsupportingExecute-In-Place(XIP)–Bootflashfaultdetectionandcorrectionusingtwo-dimensionalparity.
–TriplefaultdetectionandsinglefaultcorrectionschemeforexternalDDR-RAMincludingaddress/pagefaultdetection.
Videoinputinterfaces,Imageprocessing,graphicsprocessing,display–DisplayControlUnit(2D-ACE)with24-bitRGB,GPUframebufferdecoding–GPUGC3000withframebuffercompression–2xVIU(Videointerfaceunit)forcamerainput–2xMIPICSI2withfourlanesforcamerainput(support1080pixel@30fps)–Imagesignalprocessor(ISP),supporting2x1or1x2megapixel@30fpsand4x2megapixelforsubsetoffunctions(exposurecontrol,gammacorrection)–2xAPEX2-CLImagecognitionprocessor.
APEX-642CLcomprisestwoArrayProcessingUnit(APU)coresconfigurableassingleSIMDenginewith6416-bitComputationalUnits(CU),orconfigurableastwocoreMIMDengineswith3216-bitCUseach.
–CUsarecomprisedoffourFunctionalUnits:16-bitMultiplier,LoadStoreUnit,ALU,andShifter–JPEGvideodecoder(8/12-bit)–H.
264videodecoder(8/10/12-bit),High-intraandconstrainedbaselineformats–H.
264videoencode(8/10/12-bit),High-intraonly–FastDMAfordatatransfersbetweenDRAMandSystemRAMwithCRCHuman-MachineInterface(HMI)–GPIOpinswithinterruptsupport,DMArequestcapability,digitalglitchfilter–ConfigurableslewrateanddrivestrengthonalloutputpinsSystemRAM–4MBOn-ChipSystemRAMwithECCS32V234DataSheet,Rev.
9,03/20202NXPSemiconductorsTableofContents1Blockdiagram.
52Familycomparison.
52.
1FeatureSet.
53Orderingparts.
83.
1Orderinginformation.
84General.
84.
1Operationabovemaximumoperatingconditions.
84.
2Recommendedoperatingconditions.
94.
3PowerManagementController(PMC)electricalspecifications.
104.
4Powerconsumption.
114.
5Electrostaticdischarge(ESD)specifications.
134.
6ElectromagneticCompatibility(EMC)specifications.
134.
7PCBroutingguidelines.
135I/Oparameters.
155.
1GeneralpurposeI/Oparameters.
155.
1.
1GPIOspeedatvariousvoltagelevels.
155.
1.
2DCelectricalspecifications.
175.
2DDRpads.
185.
2.
1DDR3mode.
185.
2.
1.
1DDR3modeDCelectricalspecifications.
185.
2.
2DDR3Lmode.
185.
2.
2.
1DDR3LmodeDCelectricalspecifications.
185.
2.
3LPDDR2mode.
195.
2.
3.
1LPDDR2modeDCelectricalspecifications.
195.
3BootConfigurationPinsSpecification.
206Peripheraloperatingrequirementsandbehaviors.
206.
1Analogmodules.
206.
1.
1ADCelectricalspecifications.
206.
1.
1.
1Inputequivalentcircuit.
216.
1.
2ThermalMonitoringUnit(TMU)236.
2ClocksandPLLinterfacesmodules.
236.
2.
1Mainoscillatorelectricalcharacteristics.
236.
2.
248MHzFIRCelectricalcharacteristics.
246.
2.
3PLLelectricalspecifications.
246.
2.
4DFSelectricalspecifications.
256.
2.
5LFASTPLLElectricalSpecifications.
256.
3Memoryinterfaces.
266.
3.
1QuadSPIACspecifications.
266.
4DDRSDRAMSpecificParameters(DDR3,DDR3L,andLPDDR2)316.
4.
1DDR3andDDR3Ltimingparameters316.
4.
2DDR3andDDR3Lreadcycle.
336.
4.
3DDR3andDDR3Lwritecycle.
346.
4.
4LPDDR2timingparameter.
356.
4.
5LPDDR2readcycle.
376.
4.
6LPDDR2writecycle.
386.
5Communicationmodules.
396.
5.
1DSPItiming.
396.
5.
2UltraHighSpeedSD/SDIO/MMCHostInterface(uSDHC)436.
5.
2.
1SDRmodetimingspecifications.
436.
5.
2.
2DDRmodetimingspecifications.
456.
5.
3LFASTelectricalcharacteristics.
486.
5.
3.
1LFASTinterfacetimingdiagrams.
486.
5.
3.
2LFASTInterfaceelectricalcharacteristics.
496.
5.
4FlexRay.
506.
5.
4.
1FlexRaytimingparameters.
506.
5.
4.
2TxEN.
506.
5.
4.
3TxD.
516.
5.
4.
4RxD.
526.
5.
5EthernetController(ENET)Parameters.
536.
5.
5.
1EthernetSwitchingSpecifications.
536.
5.
5.
2ReceiveandTransmitsignaltimingspecificationsforRMIIinterfaces.
536.
5.
5.
3ReceiveandTransmitsignaltimingspecificationsforMIIinterfaces.
546.
5.
5.
4ReceiveandTransmitsignaltimingspecificationsforRGMIIinterfaces.
.
.
.
.
.
566.
5.
5.
5MII/RMIISerialManagementchanneltiming(MDC/MDIO)576.
5.
6PCIExpressspecifications.
586.
5.
7IICtiming.
596.
5.
8LINFlextiming.
606.
6Displaymodules.
616.
6.
1DisplayControlUnit(2D-ACE)Parameters.
61S32V234DataSheet,Rev.
9,03/2020NXPSemiconductors36.
6.
1.
1InterfacetoTFTpanels.
616.
6.
1.
2InterfacetoTFTLCDPanels—PixelLevelTimings.
626.
6.
1.
3InterfacetoTFTLCDpanels—accesslevel.
636.
6.
2Videoinputunit(VIU)timingspecifications.
646.
6.
3MIPICSI2D-PHYelectricalandtimingparameters.
656.
6.
3.
6NOTICEOFDISCLAIMER.
686.
7Debugspecifications.
696.
7.
1JTAGinterfacetiming.
696.
7.
2Debugtracetimingspecifications.
736.
8WakeupUnit(WKPU)ACspecifications.
746.
9RESETpinglitchfilterspecifications.
746.
10Externalinterrupttiming(IRQpin)747Thermalattributes.
757.
1Thermalattributes.
758Dimensions.
768.
1Obtainingpackagedimensions769Pinouts.
769.
1Packagepinoutsandsignaldescriptions.
7610Resetsequence.
7610.
1Resetsequenceduration.
7610.
2Bootperformancematrix.
7710.
3Resetsequencedescription.
7811Powersequencingrequirements.
8012Revisionhistory.
81S32V234DataSheet,Rev.
9,03/20204NXPSemiconductors1BlockdiagramDebugCore01000MHzCortex-A5332KBI-Cache32KBD-CacheNEON/FPUCore11000MHzCortex-A5332KBI-Cache32KBD-CacheNEON/FPU256KBL2-CacheSCUCore21000MHzCortex-A5332KBI-Cache32KBD-CacheNEON/FPUCore31000MHzCortex-A5332KBI-Cache32KBD-CacheNEON/FPU256KBL2-CacheSCU128-bits128-bitsCCI-400incl.
EDC128-bits128-bitsSRAM-allothers64-bitsAHBConcentrator64-bitsAHB64-bitsAHB32-bitsAHBDMAMEMeDMA64-bitsAHB16KBI-CacheCoreP133MHzCortex-M464KBTCM16KBD-Cache64-bitsAHB64-bitsAHBBIUCSE-FLSecurityEngineSidebandOutputs1KBROMFUSEIF16KBDRAM64-bitsPeripheralBridge064-bits64-bits64-bitsOTFADROMCtrl64-bitsAHBQuadSPINORFlashCtrlPeripheralBridge164-bitsSRAM-allothers64-bits64-bitsAHBDRAM-allothers64-bitsCortex-A53AXBSBusSystemincl.
EDCXRDC32-bitsCoresPCIe/ENETallothersFastDMAAPEX-2_1APEX-2_0DCUGPUH.
264DecNVICBlkDMA32KBIMEMSeqDMA32KBDMEMMEMIFCMEM16x2Kx64APEX-2_1(2xAPU)BlkDMA32KBIMEMDMA32KBDMEMMEMIFCMEM16x2Kx64APEX-2_0(2xAPU)MC128-bitsMC128-bits16-bitVIU64-bitsCDC420EncoderGPUGC3000DEC200DecoderDisplayControlUnit(2D-ACE)MCDEC200EncoderCRCFastDMA128-bits64-bits64-bitsXRDCQoS301incl.
EDCXRDCCoresPCIe/ENETallothersFastDMAAPEX-2_1APEX-2_0VIU_H264XRDC128-bitsXRDC128-bits128-bitsHierarchicalNIC301AXIBusSystemincl.
EDCXRDC4KBPRAMSEQSCUDRAM-ECC32-bitMMDC_0LPDDR2DDR3(L)DDR-PHYSRAMControllerMultiPortedMultiBanked64KBCRAM16KBKRAMSequencer4MBSRAM24+BanksECCx64Internal32-bitMMDC_1LPDDR2DDR3(L)DDR-PHY4/2x4/8-bitsQSPIFlashExternalNORFlashOff-Chip2x4-bits64KBROM(boot)32-bitsMCCGM,RGM,PCU,MESTCUPIT_0STM_0SWT_1SWT_032-bitsSDHCFlexRaySIPI+LFAST320Mbps10Mbps1Gbps5Gbps24-bitRGBDisplayIF100MHz100MHz4Lanes4LanesPCIeEthernetAVBChanMuxChanMuxMIPI-CSI2ISP0MIPI-CSI2ISP1ISP2ISPNH.
264EncoderH.
264DecoderJPEGDecoderOCOTP_CTRLWakeUpSIULSARADC_0FlexTimer_0IIC_0Linflex_0CAN_FD_0DSPI_0DSPI_2CRC_0FCCUCRC_1DSPI_3DSPI_1CAN_FD_1Linflex_1IIC_2IIC_1FlexTimer_1SWT_4SWT_3SWT_2STM_1INTC_MONCGM-CMUsPIT_1SSETSENSPMCERM+EIMMSCMSEMA4MEMU32-bitsMCMPUDebugDebugDebugDebugDebugDebugDebugDebugDebug16-bitVIUSeqGIC-400533MHz1066MT/sDDR533MHz1066MT/sDDRDRAM-ECCFigure1.
Blockdiagram2Familycomparison2.
1FeatureSetThisfamilyofdevicessupportsthefollowingfeatures:Table1.
FeatureSetFeatureS32V234S32V232ARMCortex-A53CoreUpto1000MHzQuadARMCortex-A5332KB/32KBI-/D-L1CacheNEONMPEco-processorDualprecisionFPU256KBL2CacheperclusterMMUGICinterruptcontrollerUpto1000MHzDualARMCortex-A53(singlecluster)TheremainingfeaturesaresameasS32V234Tablecontinuesonthenextpage.
.
.
BlockdiagramS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors5Table1.
FeatureSet(continued)FeatureS32V234S32V232ECC/parityerrorsupportforitsmemoriesGenerictimersARMCortex-M4CoreUpto133MHz16KB/16KBI-/D-L1Cache32+32KBtightlycoupledmemory(TCM)ECC/paritysupportforitsmemoriesSameasS32V234ClocksPhaseLockedLoops(PLLs)1externalcrystalocillators(FXOSC)1FIRCSameasS32V234System,protectionandpowermanagementfeaturesFlexiblerunmodestoconsumelowerpowerbasedonapplicationneeds.
Peripheralclockenableregisterscandisableclockstounusedmodules,therebyreducingcurrentsLowandhighvoltagewarninganddetectHardwareCRCmoduletosupportfastcyclicredundancychecks(CRC)120-bituniquechipidentifierHardwarewatchdogSafeeDMAcontrollerwith32channels(withDMAMUX)ExtendedResourceDomainControllerSameasS32V234SafetyconceptISO26262,ASILleveltargetaspersafetyconceptMeasuresdetectingfaultsinmemoryandlogicMeasurestodetectsinglepointandlatentfaultsQuantitativeoutofcontextanalysisoffunctionalsafety(FMEDA)tailoredtoapplicationspecificsSafetymanualandFMEDAreportavailableBootflashauthenticationandfaultdetectionandcorrectionusingAES-128andtwo-dimensionalparity.
DoubleandtriplefaultdetectionandsinglefaultcorrectionschemeforexternalDDR-RAMincludingaddress/pagefaultdetection.
Faultencapsulationbyhardwareforredundantexecutedapplicationsoftwareonmultiplecorecluster.
Structuralsoftwarebasedselftestroutinesprovidinghighdiagnosticcoverage.
SameasS32V234DebugStandardJTAG16-bitTraceport,SerialWireOutputportSameasS32V234TimersGeneralpurposetimers(FTM)SameasS32V234Tablecontinuesonthenextpage.
.
.
FamilycomparisonS32V234DataSheet,Rev.
9,03/20206NXPSemiconductorsTable1.
FeatureSet(continued)FeatureS32V234S32V232TwoPeriodicInterruptTimer(PIT)IEEE1588Timers(partofEthernetSubsystem)CommunicationsUART(w/LIN2.
1l)Serialperipheralinterface(SPI)I2CblocksPCIexpress2.
0withendpointandrootcomplexsupportLFASTseriallink1GBitEthernetwithPTPIEEE1588FD-CANFlexrayDualChannel,Version2.
1RevASameasS32V234MemoryInterfaces32-bitDRAMControllerwithsupportforLPDDR2/DDR3/DDR3L-Datarateofupto1066MT/sat533MHzclockfrequencywithECC(SEC-DED-TED)singleerrorcorrection,doubleerrordetection,andtripleerrordetectionsupportforsubregionDualQuadSPIsupportingExecute-In-Place(XIP)SameasS32V234Videoinputinterfaces,Imageprocessing,graphicsprocessing,displayDisplayControlUnit(2D-ACE)with24-bitRGB,GPUframebufferdecodingGPUGC3000withframebuffercompression2xVideointerfaceunit(VIU)forcamerainput2xCSIwith4lanesforcamerainput(support1080p@30fps)Imagesignalprocessor(ISP),supporting2x1or1x2MPixel@30fpsand4x1MPixelforsubsetoffunctions(exposurecontrol,gammacorrection)2xAPEX2-CLImagecognitionprocessor(dual32-bitarrayprocessor)JPEGvideodecoder(8/12-bit)H.
264videodecoder(8/10/12-bit),High-intraandconstrainedbaselineformatsH.
264videoencoder(8/10/12-bit),I-framesonlySafeFastDMAfordatatransfersbetweenDRAMandSystemRAMwithCRCSameasS32V234Analog1x12-bitSARADCwithself-testSameasS32V234Human-MachineInterface(HMI)SIUL,GPIOpinswithinterruptsupport,DMArequestcapability,digitalglitchfilter.
ConfigurableslewrateanddrivestrengthonalloutputpinsSameasS32V234SystemRAM4MBOn-ChipSystemRAMwithECC3MBOn-ChipSystemRAMwithECCPowerConsumptionRunmodes:SameasS32V234FamilycomparisonS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors7Table1.
FeatureSetFeatureS32V234S32V232FrequencyscalingandclockgatingforprocessingblocksandperipheralsinrunmodeOrderingparts3.
1OrderinginformationFS32V23DeviceconfigurationShippingmethodR=Tapeandreel(blank)=TraysDeviceFamily4BKN1VUBRCoreconfigurationTemepratureoptionsShippingmethodC=-40to105°CV=-40to125°CCoreconfigurationTemperatureoptions2=DualArmCortex-A534=QuadArmCortex-A53SpeedconfigurationSpeedconfigurationB=ArmCortex-A53@800MHzC=ArmCortex-A53@1GHzDeviceconfiguration*ISP3DGPUCSELowpower(leakagebased)eIQAutoKLMOJYesNoYesNoKbecomesQYesYesYesYesYesYesYesYesYesYesNoNoNoNoNoNoLbecomesRMbecomesSObecomesTJbecomesU*AllcombinationsarenotorderableNOTENotallcombinationsareorderable.
Forthelatestinformationonorderablepartscheckhttps://www.
nxp.
com/s32v234Buy/Parametricssection.
General4.
1Operationabovemaximumoperatingconditions34OrderingpartsS32V234DataSheet,Rev.
9,03/20208NXPSemiconductorsTable2.
Operationabovemaximumoperatingconditions1.
8VDGOVoltageDomainElectricalSpecificationsValueConditionsJunctTempAbsoluteMaximumSupplyVoltage3.
0VVDD_HV_IO_VIU0VDD_HV_IO_VIU1VDD_HV_IO_DISVDD_HV_IO_FLA1.
8Vinput/outputsupplyvoltage—1.
711.
95V3.
3Vinput/outputsupplyvoltage—3.
153.
6VVDD_HV_IO_ETH1.
5VI/Osupplyvoltage—1.
4251.
575V1.
8VI/Osupplyvoltage—1.
711.
95V2.
5VI/Osupplyvoltage—2.
3752.
625V3.
3VI/Osupplyvoltage—3.
153.
6VVSSCommongroundvoltage1—00VVDD_LV_CORE_SOC,VDD_LV_CORE_ARM,VDD_LV_CORE_GPU1.
0Vcoredomainsupplyvoltage2—0.
951.
05VVDD_HV_CSI1.
8Vsupplyvoltage(forMIPICSI2DPHY)—1.
711.
95VVDD_LV_CSI1.
0Vsupplyvoltage(forMIPICSI2DPHY)—0.
951.
05VVDD_HV_PLL,1.
8Vsupplyvoltage(foranalogcircuits,PLLs)—1.
711.
95VTablecontinuesonthenextpage.
.
.
GeneralS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors9Table3.
Recommendedoperatingconditions(continued)SymbolParameterConditionsMinMaxUnitVDD_HV_LFASTPLL,VDD_HV_FXOSC,VDD_HV_PMC,VDDIO_LFAST,VDD_HV_EFUSE,VDD_HV_DDRVDD_LV_PLLVDD_LV_POST1.
0Vsupplyvoltage(foranalogcircuits,PLLs)—0.
951.
05VVREFH_ADC1.
8VADChighreferencevoltage—1.
711.
95VVDD_HV_ADV1.
8VADCsupplyvoltage—1.
711.
95VVSS_HV_ADVADCgroundandlowreferencevoltage—00VVREFL_ADC1.
8VADCsupplyground—00VVDD_DDR_IODDRI/OsupplyvoltageLPDDR2—1.
141.
30VDDRI/OsupplyvoltageDDR3—1.
4251.
575VDDRI/OsupplyvoltageDDR3L—1.
2831.
45VPCIE_VPPCIesupplyvoltages—0.
951.
05VPCIE_VPH—1.
711.
95VTAAmbienttemperature—-401053°CTJJunctiontemperatureunderbias—-40125°CTVDDSupplyramprateforallsuppliesonthedevice—0.
0525V/ms1.
Allthegroundsviz.
VSS,VSS_FXOSC,andVSS_HV_ADVaretiedtogetheratthepackagelevel.
2.
VDD_LV_CORE_SOC,VDD_LV_CORE_ARM,andVDD_LV_CORE_GPUsupplyballsshouldallbeconnectedtogethertoonepowerplaneandoneregulatortoavoidvoltageleveldifferences.
IftheGPUispowergatedasitisnotused,theVDD_LV_CORE_GPUsupplyballshavetobestaticallyconnectedtothegroundplane.
IfthesecondARMCPUsperclusterispowergatedastheyarenotused,theVDD_LV_CORE_ARMsupplyballshavetobestaticallyconnectedtothegroundplane.
3.
Maximumambienttemperaturerequiresmanagementoftheheatdissipationtoensurethedevicejunctiontemperaturedoesnotexceedthemaximum.
4.
3PowerManagementController(PMC)electricalspecificationsPMCiscomposedofthefollowingblocks:Lowvoltagedetector(LVD_33_PMC)for3.
3VVDD_GPIO0supply(GPIOsegmentandPMC)andLowVoltageDetectorforFIRC(VDD_HV_FXOSC)Lowvoltagedetector(LVD_18)forVDD_HV_PMCLowvoltagedetector(LVD_18)forVDD_HV_FXOSCHighvoltagedetector(HVD_18)forVDD_HV_PMCLowvoltagedetector(LVD_CORE)forVDD_LV_CORE_SOCHighvoltagedetector(HVD_CORE)forVDD_LV_CORE_SOCPoweronReset(POR)GeneralS32V234DataSheet,Rev.
9,03/202010NXPSemiconductorsTable4.
PMCelectricalspecificationsSupplyParameterConditionsThresholdMinTypicalMaxStatusduringpower-upUnitVDD_LV_CORE_SOClowvoltagemonitoringNativeVTL1836880924EnabledmVVTH2850895940TrimmedVTL896910924VTH911925946VDD_LV_CORE_SOChighvoltagemonitoringTrimmedVTL104910651093DisabledmVVTH106410801093VDD_HV_PMCPMCsupplylowvoltagemonitorNativeVTL151115901670EnabledmVVTH152516051685TrimmedVTL162016501680VTH163516651695VDD_HV_PMCPMCsupplyhighvoltagemonitorTrimmedVTL200420452086DisabledmVVTH201920602101VDD_GPIO0lowvoltagemonitorNativeVTL272728703014EnabledmVVTH274628903035TrimmedVTL285729152973VTH287629352994VDD_HV_FXOSCFXOSCsupplylowvoltagemonitorNativeVTL151115901670EnabledmVVTH152516051685TrimmedVTL162016501680VTH163516651695PMC_BGREFPMCBandGapReferencevalueTrimmed–117612001224EnabledmV1.
Lowerthreshold/assertpoint2.
Upperthreshold/releasepoint4.
4PowerconsumptionThefollowingtableshowsthepowerconsumptiondata.
Thesespecificationsaresubjecttochangeperdevicecharacterization.
Table5.
PowerconsumptionParameterDescriptionMaxValues125CTj105CTjVDD_LV_CORE(Static)1,232V234BLDeviceinreset3A2.
3ATablecontinuesonthenextpage.
.
.
GeneralS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors11Table5.
Powerconsumption(continued)ParameterDescriptionMaxValues125CTj105CTjS32V232BMDeviceinreset6.
0A4.
5AS32V234CODeviceinreset6.
4A4.
8AS32V234CKDeviceinreset4.
8A3.
5AS32V232BLDeviceinreset2.
7A2.
0AS32V232CKDeviceinreset4.
4A3.
2AVDD_LV_CORE(Dynamic)4xA53CPUwithDhrystoneMIPSrunningoneachCPU@1GHz31.
4AVDD_HV_CSICurrentforbothMIPICSI2interfacesoperatingasper1)RXOperationat1.
5GbpsperMIPICSI22)MIPICSI2notused(IPPoweredandDisabled)1)10mA2)1mAVDD_LV_CSICurrentforbothMIPICSI2interfacesoperatingasper1)RXOperationat1.
5GbpsperMIPICSI22)MIPICSI2notused(IPPoweredandDisabled)1)40mA2)13mAVDD_HV_PLLAllfivePLLsoperatingat1GHzVCOfrequency35mAVDD_HV_LFASTPLLUsecase:1)PLLoperatingwith320MHz(LFASTused)2)PLLnotoperational(LFASTnotused)1)26mA2).
1mAVDD_HV_FXOSCSharedsupplyforFXOSCoperatingwith40MHzcrystalandFIRCoscillator5mAVDD_HV_PMCAsperdefaultusage(nousecasedifferentiation)10mAVDD_HV_EFUSEUsecase:1)eFuseprogramminghappening1)10mAVDD_LV_PLLAllfivePLLsoperatingat1GHzVCOfrequency80mAPCIE_VPUsecase:1)5GHzoperation(PCIe2.
0)2)Reset/idle1)80mA2)30mAPCIE_VPHUsecase:1)5GHzoperation(PCIe2.
0)1)50mA2)20mATablecontinuesonthenextpage.
.
.
GeneralS32V234DataSheet,Rev.
9,03/202012NXPSemiconductorsTable5.
Powerconsumption(continued)ParameterDescriptionMaxValues125CTj105CTj2)Reset/idleVDD_HV_ADVADCoperational1mAVDD_REFH_ADCVoltagereferenceforADC80μA1.
Datarepresentedisat125°CTjand1.
01Vvddconditions2.
IncludesSoC,GPU,andARMsupplycombinationsdependingonusecasedescription.
3.
Addertothestaticiddcurrentcomponent.
4xCortexA53executingDhrystoneMIPSinAArch64andtheinterconnect,SystemRAM,FastDMA,CortexM4,peripheralbridges,FCCU,CSE,MEMU,PCIe,andSTCUareclocked-staticpowerconsumptionexcluded.
4.
5Electrostaticdischarge(ESD)specificationsElectrostaticdischargesareappliedtothepinsofeachsampleinconformitywithAEC-Q100-002/-011tomeettheHBMandCDMratingsdescribedbelow.
Table6.
ESDratings1SymbolParameterConditionsClassMaxvalue2UnitVESD(HBM)Electrostaticdischarge(HumanBodyModel)TA=25°CconformingtoAEC-Q100-002H1C2000VVESD(CDM)Electrostaticdischarge(ChargedDeviceModel)TA=25°CconformingtoAEC-Q100-011C3A500V1.
AdevicewillbedefinedasafailureifafterexposuretoESDpulsesthedevicenolongermeetsthedevicespecificationrequirements.
CompleteDCparametricandfunctionaltestingshallbeperformedperapplicabledevicespecificationatroomtemperaturefollowedbyhottemperature,unlessspecifiedotherwiseinthedevicespecification.
2.
Databasedoncharacterizationresults,nottestedinproduction.
4.
6ElectromagneticCompatibility(EMC)specificationsEMCmeasurementstoIC-levelIECstandardsareavailablefromNXPonrequest.
4.
7PCBroutingguidelinesDDR3/DDR3LPCBdesignCLK/Addess/CommandsRoutewith50ohmcontrolledimpedanceanddifferentialpair(CLK)with100ohmcontrolledimpedanceUseFlybytopologyincaseofmultiplememorycomponentsAddressandcommandlinesTerminatedtoVTTwith50ohmTobereferencedwithPower,notGroundGeneralS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors13Address/Cmdtoberoutedwithin66milswithrespecttoCLKandtobematchedfromcontrollertomemory;memorytomemoryaswellAlltracestoberoutedininternallayersPreferenceistouseonlytwolayersforroutingthisgroupLimitthevianumbertolessthanthreeNOTEThedifferentialclocklinesontheDDR3interfaceshoulduseACterminationscheme,witha0.
1FseriescapacitorandreferencedtoDDRIOsupply(VDD_DDR_IO).
Data/StrobeRoutewith50ohmcontrolledimpedanceanddifferentialpair(DQSstrobe)with100ohmcontrolledimpedanceDatatoberoutedwithin33milswithrespecttorespectivestrobeTobereferencedwithGroundAlltracestoberoutedininternallayersStrictlytoberoutedinonlytwolayersAvoidmorethantwoviasLPDDR2PCBdesignCLK/Addess/CommandsRoutewith50ohmcontrolledimpedanceanddifferentialpair(CLK)with100ohmcontrolledimpedanceTobereferencedwithPower,notGroundAddress/Cmdtoberoutedwithin66milswithrespecttoCLKandtobematchedfromcontrollertomemoryAlltracestoberoutedininternallayersanddelayshouldbelessthan150psPreferenceistouseonlytwolayersforroutingthisgroupLimitthevianumbertolessthanthreeData/StrobeRoutewith50ohmcontrolledimpedanceanddifferentialpair(DQSstrobe)with100ohmcontrolledimpedanceDatatoberoutedwithin33milswithrespecttorespectivestrobeTobereferencedwithGroundAlltracestoberoutedininternallayersanddelayshouldbelessthan150psStrictlytoberoutedinonlytwolayersAvoidmorethantwoviasGPIOInterfacesQuadSPIPut22ohmseriesterminationonboardwhenoperatingwithSIUL2_MSCRn[DSE]111GeneralS32V234DataSheet,Rev.
9,03/202014NXPSemiconductorsTRACEPut22ohmseriesterminationonboardwhenoperatingwithSIUL2_MSCRn[DSE]111ENETPut22ohmseriesterminationonboardwhenoperatingwithSIUL2_MSCRn[DSE]111I/OparametersGeneralpurposeI/Oparameters5.
1.
1GPIOspeedatvariousvoltagelevelsNOTERise/falltimesnumbersinDatasheetareguaranteedbydesign;toobtainactualrise/falltimesparameterswithspecificpackagesandboards,useappropriateI/OIBISmodel.
Table7.
GPIOrise/falltimes(1.
8Vrange)ParameterSymbolDrivestrengthSIUL2_MSCRn[DSE]SlewrateTestconditionsTypMaxUnitIOoutputtransitiontime,rise/fall1tpr001slowfast15pFCloadonpad7.
17/7.
557.
13/7.
52ns010slowfast3.
14/3.
312.
66/3.
04011slowfast2.
56/2.
511.
97/2.
20100slowfast3.
08/3.
022.
59/2.
58101slowfast2.
56/2.
421.
84/1.
96111slowfast1.
82/1.
671.
13/1.
241.
Maxcondition:wcsmodel,0.
9Vvddi,1.
62Vovdd,and125°C.
Inputtransitiontimeis120ps.
SlowslewratemeansSIUL2_MSCRn[SRE]='00',fastslewratemeansSIUL2_MSCRn[SRE]='11'55.
1I/OparametersS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors15Table8.
GPIOrise/falltimes(2.
5Vrange)ParameterSymbolDrivestrengthSIUL2_MSCRn[DSE]SlewrateTestconditionsTypMaxUnitIOoutputtransitiontime,rise/fall1tpr001slowfast15pFCloadonpad7.
41/8.
227.
36/8.
16ns010slowfast3.
30/3.
742.
76/3.
38011slowfast3.
44/3.
042.
75/2.
55100slowfast4.
05/3.
543.
56/2.
97101slowfast3.
39/2.
932.
72/2.
47111slowfast2.
31/2.
031.
80/1.
751.
Maxconditionfortpr:wcsmodel,0.
9Vvddi,2.
25Vovdd,and125°C.
Inputtransitiontimeis125ps.
SlowslewratemeansSIUL2_MSCRn[SRE]='00',fastslewratemeansSIUL2_MSCRn[SRE]='11'Table9.
GPIOrise/falltimes(3.
3Vrange)ParameterSymbolDrivestrengthSIUL2_MSCRn[DSE]SlewrateTestconditionsTypMaxUnitIOoutputtransitiontime,rise/fall1tpr001slowfast15pFCloadonpad7.
75/8.
457.
65/8.
39ns010slowfast3.
49/3.
892.
84/3.
52011slowfast3.
47/3.
162.
90/2.
73100slowfast4.
09/3.
583.
73/3.
07101slowfast3.
29/3.
002.
68/2.
37111slowfast2.
23/2.
181.
47/1.
571.
Maxconditionfortpr:wcsmodel,0.
9Vvddi,2.
97Vovdd,and125°C.
Inputtransitiontimeis120ps.
slowslewratemeansSIUL2_MSCRn[SRE]='00',fastslewratemeansSIUL2_MSCRn[SRE]='11'GeneralpurposeI/OparametersS32V234DataSheet,Rev.
9,03/202016NXPSemiconductorsNOTEThemaximumrisetimeforallGPIOpinsis1ms.
Inputpinsdonotsupporthysteresis,thereforeveryslowramps(liketheonesgeneratedbyanRCcircuitwithalargeRCvalue)caninducebouncesintheinputreadstateduringthetransitionfromlogiclowtologichighorviceversa.
5.
1.
2DCelectricalspecificationsTable10.
DCelectricalspecificationsSymbolParameterTestconditionsMinTypMaxUnitVohHigh-leveloutputvoltageIoh=-100μAovdd1-0.
15——VVolLow-leveloutputvoltageIol=100μA——0.
15VVihfHigh-LevelDCinputvoltage—0.
7*ovdd—ovddVVilLow-LevelDCinputvoltage—0—0.
2*ovddVIin2Inputcurrent(nopull-up/down)Vin=ovddor0——8μAIin_33pu2Inputcurrent(33kilohmPU)Vin=0Vin=ovdd——2206μAIin_50pu2Inputcurrent(50kilohmPU)Vin=0Vin=ovdd——1506μAIin_100pu2Inputcurrent(100kilohmPU)Vin=0Vin=ovdd——606μAIin_100pd2Inputcurrent(100kilohmPD)Vin=0Vin=ovdd——850μA1.
ovddistheIOsupplyforthepads.
2.
Maxcondition:bcsmodel,3.
6V,and125°C.
ThesevaluesareforI/Obuffers.
NOTEAfterbootup,applicationsoftwareshouldswitchtomanualvoltagedetectmodeusingVSEL_xsettingsofSRC_GPR14registertoensureoptimumperformanceoftheGPIOpads.
PleaserefertoSRCchapterintheReferenceManualfortheregisterdetails.
Table11.
Current-drawCharacteristicsforDDR_VREFSymbolParameterMinMaxUnitDDR_VREFCurrent-drawcharacteristicsforDDR_VREF—1mAGeneralpurposeI/OparametersS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors175.
2DDRpads5.
2.
1DDR3mode5.
2.
1.
1DDR3modeDCelectricalspecificationsTable12.
DDR3modeDCelectricalspecificationsParameterSymbolTestconditionsMinTypMaxUnitHigh-leveloutputvoltageVohIoh=-100μA0.
8*ovdd——VLow-leveloutputvoltageVolIol=100μA——0.
2*ovddVHigh-levelDCinputvoltageVih(DC)—Vref+0.
2—ovddVHigh-levelDCinputvoltageVil(DC)—ovss—Vref-0.
2VInputreferencevoltageVref—0.
49*ovdd0.
5*ovdd0.
51*ovddVTerminationvoltage1Vtt2——0.
5*ovdd—VInputcurrent(nopullup/pulldown)3IinVi=0orovdd——5μAPullup/pulldownimpedancemismatchMMpupd34Ohmfullstrengthdriver-10—+10%Driver240OhmunitcalibrationresolutionRres———10ΩRkeep4Padkeeperresistance—20—50kΩ1.
Vttisexpectedtotrackovdd/2.
2.
Vttisnotapplieddirectlytothedevice.
MinimumandMaximumvaluesaresystemdependant.
3.
Typcondition:typmodel,1.
5V,and25°C.
Maxcondition:bcsmodel,1.
575V,and-40°C.
Mincondition:wcsmodel,1.
425V,and125°C.
4.
Typcondition:typmodel,1.
5V,and25°C,maxcondition:wcsmodel,1.
425V,and125°C,mincondition:bcsmodel,1.
575V,and-40°C.
5.
2.
2DDR3Lmode5.
2.
2.
1DDR3LmodeDCelectricalspecificationsTable13.
DDR3LmodeDCelectricalspecificationsParameterSymbolTestconditionsMinTypMaxUnitHigh-leveloutputvoltageVohIoh=-100μA0.
8*ovdd——VLow-leveloutputvoltageVolIol=100μA——0.
2*ovddVHigh-levelDCinputvoltageVih(DC)—Vref+0.
2—ovddVTablecontinuesonthenextpage.
.
.
GeneralpurposeI/OparametersS32V234DataSheet,Rev.
9,03/202018NXPSemiconductorsTable13.
DDR3LmodeDCelectricalspecifications(continued)ParameterSymbolTestconditionsMinTypMaxUnitHigh-levelDCinputvoltageVil(DC)—ovss—Vref-0.
2VInputreferencevoltageVref—0.
49*ovdd0.
5*ovdd0.
51*ovddVVrefcurrentdrawIcc-vref———1mATerminationvoltageVtt1——0.
5*ovdd—VInputcurrent(nopullup/pulldown)IinVi=0orovdd——5μAPullup/pulldownimpedancemismatch(fullstrengthdriver)MMpupd—-10—+10%Driverunit(240Ohm)calibrationresolutionRres———10ΩRkeepPadkeeperresistance—20—50kΩ1.
Vttisnotapplieddirectlytothedevice.
MinimumandMaximumvaluesaresystemdependant.
LPDDR2mode5.
2.
3.
1LPDDR2modeDCelectricalspecificationsTable14.
LPDDR2modeDCelectricalspecificationsParameterSymbolTestconditionsMinTypMaxUnitHigh-leveloutputvoltageVohIoh=-100μA0.
9*ovdd——VLow-leveloutputvoltageVolIol=100μA——0.
1*ovddVInputreferencevoltageVref—0.
49*ovdd0.
5*ovdd0.
51*ovddVHigh-levelDCinputvoltageVih(DC)—Vref+0.
17—ovddVHigh-levelDCinputvoltageVil(DC)—ovss—Vref-0.
17VInputcurrent(nopullup/pulldown)1IinVi=ovddor0——5μAPullup/pulldownimpedancemismatchMMpupd34Ohmfullstrengthdriver-15—+15%Driver240OhmunitcalibrationresolutionRres———10ΩRkeep2Padkeeperresistance—20—50kΩ1.
Typcondition:typmodel,1.
2V,and25°C.
Maxcondition:bcsmodel,1.
32V,and-40°C.
Mincondition:wcsmodel,1.
14V,and125°C.
2.
Typcondition:typmodel,1.
2V,and25°C,maxcondition:wcsmodel,1.
14V,and125°C,mincondition:bcsmodel,1.
32V,and-40°C.
5.
2.
3LPDDR2modeS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors195.
3BootConfigurationPinsSpecificationValuedrivenonRCONandBOOTMODpinsshouldbestableforatleast1safterRESETpinisdeasserted.
NOTEExternalpullup/downresistorsmustbeusedontheBOOTMODpinsinordertoensurelatchingatthecorrectstate.
NOTENXPwouldanticipatethatmostcustomerswouldusethebootfromfusesoptioninaproductionenvironment.
However,thereisnoreliabilityimpactifthedeviceisconfiguredbyRCONratherthanfuses.
PeripheraloperatingrequirementsandbehaviorsAnalogmodules6.
1.
1ADCelectricalspecificationsThedeviceprovidesa12-bitSuccessiveApproximationRegister(SAR)Analog-to-DigitalConverter.
66.
1PeripheraloperatingrequirementsandbehaviorsS32V234DataSheet,Rev.
9,03/202020NXPSemiconductors(2)(1)(3)(4)(5)OffsetErrorOSEOffsetErrorOSEGainErrorGE1LSB(ideal)Vin(A)(LSBideal)(1)Exampleofanactualtransfercurve(2)Theidealtransfercurve(3)Differentialnon-linearityerror(DNL)(4)Integralnon-linearityerror(INL)(5)Centerofastepoftheactualtransfercurvecodeout40954094409340924091409054321076123456740894090409140924093409440951LSBideal=(VrefH-VrefL)/4096=1.
8V/4096=.
439mVTotalUnadjustedErrorTUE=+/-10LSB=+/-4.
39mVFigure2.
ADCcharacteristicsanderrordefinitionsNOTEWhilemeasuringscaledsupplyvoltagesonADCChannels,Maximum(+5/-10%)variationcanbeexpected.
AnalogmodulesS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors216.
1.
1.
1InputequivalentcircuitRFCFRSRLRSW1CP2VDDSamplingSourceFilterCurrentLimiterEXTERNALCIRCUITINTERNALCIRCUITSCHEMERSSourceImpedanceRFFilterResistanceCFFilterCapacitanceRLCurrentLimiterResistanceRSW1ChannelSelectionSwitchImpedanceRADSamplingSwitchImpedanceCPPinCapacitance(twocontributions,CP1andCP2)CSSamplingCapacitanceCP1RADChannelSelectionVACSFigure3.
InputequivalentcircuitTable15.
ADCconversioncharacteristicsSymbolParameterConditionsMinTypMaxUnitfCKADCInputClockfrequency(Busclock)—20—80MHzfAD_clkADCConversionclockfrequency12040MHzfsSamplingfrequency———0.
5MHztsampleSampletime2500——nstconvConversiontime31400——nsCSADCinputsamplingcapacitance———5pFCP1ADCinputpincapacitance1———5pFCP2ADCinputpincapacitance2———0.
8pFRSW1Internalresistanceofanalogsource———875ΩRADInternalresistanceofanalogsource———825ΩINL4Integralnonlinearity—–3—3LSBDNLDifferentialnonlinearity—–2—2LSBOFSOffseterror—–6—6LSBGNEGainerror—–6—6LSBInput(singleADCchannel)Maxleakage125C——2000nATUETotalunadjustederror—–8—8LSBAnalogmodulesS32V234DataSheet,Rev.
9,03/202022NXPSemiconductors1.
PleaseseedescriptionofClock&resetsectioninADCchapterinReferenceManualfordetails.
UserneedtogenerateAD_clk=40MHzfor0.
5MSPSoperation.
Forexample,iffck=80MHz,configureMCR[8].
ADCLKSE=0andMCR[4].
ADCLKDIV=0(default).
2.
DuringthesampletimetheinputcapacitanceCScanbecharged/dischargedbytheexternalsource.
Theinternalresistanceoftheanalogsourcemustallowthecapacitancetoreachitsfinalvoltagelevelwithintsample.
Aftertheendofthesampletimetsample,changesoftheanaloginputvoltagehavenoeffectontheconversionresult.
Valuesforthesampleclocktsampledependonprogramming.
ForinternalADCchannels,theminimumsamplingtimerequiredis3microsecond.
3.
Thisparameterdoesnotincludethesampletimetsample,butonlythetimefordeterminingthedigitalresultandthetimetoloadtheresultregisterwiththeconversionresult.
4.
Specificationsarequotedhereforinputsignalrangingfrom150mVtoVDD_HV_ADC-150mV.
Forsignalsoutsidethisrange,theSpecificationsmaydegradebeyondlimitsspecifiedinthistable.
6.
1.
2ThermalMonitoringUnit(TMU)ThefollowingtabledescribesTMUelectricalcharacteristics.
Table16.
TMUelectricalcharacteristicsSymbolParameterConditionsValueUnitMinTypMaxTjTemperaturemonitoringrange—-40—125°CTSENSSensitivity——2.
5—mV/°CTACCAccuracyTJ=-40°Cto40°C-10—+10°CTJ=40°Cto125°C-6—+6°CClocksandPLLinterfacesmodules6.
2.
1MainoscillatorelectricalcharacteristicsThedeviceprovidesanoscillator/resonatordriverofaPierce-typestructure.
Table17.
MainoscillatorelectricalcharacteristicsSymbolParameterConditionsValueUnitMinTypMaxfFXOSCHSOscillatorfrequency——40.
0n/aMHzTFXOSCHSSUOscillatorstart-uptimefFXOSCHS=40MHz——21msVIHInputhighlevelCMOSSchmittTriggerVref=0.
5*VDD_HV_FXOSCwhereVDD_HV_FXOSCisFXOSCHVSupplyVref+0.
5—VDD_HV_FXOSCVVILInputlowlevelCMOSSchmittTriggerVref=0.
5*VDD_HV_FXOSCwhereVDD_HV_FXOSCisFXOSCHVSupply0—Vref–0.
5V6.
2ClocksandPLLinterfacesmodulesS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors231.
Thestart-uptimeisdependentuponcrystalcharacteristics,boardleakage,etc,highESRandexcessivecapacitiveloadscancauselongstart-uptimeFollowingcrystalsareusedininternalcrystaloscillatorvalidation:NX3225–40MHz;Loadcapacitance=8pFNX5032–40MHz;Loadcapacitance=8pF6.
2.
248MHzFIRCelectricalcharacteristicsTable18.
FIRCelectricalspecificationsSymbolParameterConditionsValueUnitMinTypMaxFTargetFIRCtargetfrequency(trimmed)——48—MHzδFvar_TFIRCfrequencyvariationwithrespecttosupplyandtemperatureafterprocesstrimming—-10—+10%6.
2.
3PLLelectricalspecificationsTable19.
PLLelectricalcharacteristics1SymbolParameterConditionsValueUnitMinTypMaxfPLLINPLLinputclock2—203—403MHzΔPLLINPLLinputclockdutycycle2—40—60%tPLLLOCKPLLlocktime———100sΔPLLTPeriodjitter———150psΔPLLTIETIE———560psfPLLMODSSCGmodulationfrequency———32kHzδPLLMODSSCGmodulationdepth(DownSpread)—0.
50—2.
74%1.
Thejittervaluesaregauranteedforfollowingconditions:1.
MeasurementbeingdoneonLFASTTXpadwithobservedfrequencygreaterthan250Mandlessthan320M2.
MinimumSOCactivity-Operationsrequiredtoobserveclockmustbefunctional.
3.
MaximumfrequencychangeinSSCGmodulationislimitedbyfollowingrelation:ModulationDepth*VCOFrequency=3.
2.
SlaveReceiveOnlyModecanoperateatamaximumfrequencyof60MHz.
Inthismode,theDSPIcanreceivedataonSIN,butnovaliddataistransmittedonSOUT.
3.
Thisvalueof16nsiswiththeconfigurationprescalervalues:SPI_CTARn[PCSSCK]-"PCStoSCKDelayPrescaler"configurationis"3"(01h)andSPI_CTARn[CSSCK]-"PCStoSCKDelayScaler"configurationis"2"(0000h).
4.
Thisvalueof16nsiswiththeconfigurationprescalervalues:SPI_CTARn[PASC]-"AfterSCKDelayPrescaler"configurationis"3"(01h)andSPI_CTARn[ASC]-"AfterSCKDelayScaler"configurationis"2"(0000h).
NOTEDSPITimingspecsonthischiparevalidwithSlaveinClassicModeonly.
DataLastDataFirstDataFirstDataDataLastDataSINSOUTPCSxSCKOutput4912111104SCKOutput(CPOL=0)(CPOL=1)32Figure16.
DSPIclassicSPItiming—master,CPHA=0CommunicationmodulesS32V234DataSheet,Rev.
9,03/202040NXPSemiconductorsDataLastDataFirstDataSINSOUT121110LastDataDataFirstDataSCKOutputSCKOutputPCSx9(CPOL=0)(CPOL=1)Figure17.
DSPIclassicSPItiming—master,CPHA=1LastDataFirstData341DataDataSINSOUTSS4569111012SCKInputFirstDataLastDataSCKInput2(CPOL=0)(CPOL=1)Figure18.
DSPIclassicSPItiming—slave,CPHA=0CommunicationmodulesS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors41569121110LastDataLastDataSINSOUTSSFirstDataFirstDataDataDataSCKInputSCKInput(CPOL=0)(CPOL=1)Figure19.
DSPIclassicSPItiming—slave,CPHA=1PCSx31410491211SCKOutputSCKOutputSINSOUTFirstDataDataLastDataFirstDataDataLastData2(CPOL=0)(CPOL=1)Figure20.
DSPImodifiedtransferformattiming—master,CPHA=0CommunicationmodulesS32V234DataSheet,Rev.
9,03/202042NXPSemiconductorsPCSx1091211SCKOutputSCKOutputSINSOUTFirstDataDataLastDataFirstDataDataLastData(CPOL=0)(CPOL=1)Figure21.
DSPImodifiedtransferformattiming—master,CPHA=1PCSx78PCSSFigure22.
DSPIPCSstrobe(PCSS)timing6.
5.
2UltraHighSpeedSD/SDIO/MMCHostInterface(uSDHC)BootingfromeMMCmustbeatvoltageof3.
3V.
Theoperationat1.
8Vispossibleonlyduringrun-time,thatisaftertheboothascompleted.
ThisvoltagerestrictionduringbootingdoesnotapplytoSD/SDIO/SDHC/SDXCmodes.
Measurementsarewithaloadof40pFonoutputpins.
Inputslew=1ns,SIUL2_MSCRn[DSE]=101,andSIUL2_MSCRn[SRE]=11.
uSDHC_VEND_SPEC[CMD_OE_PRE_EN]fieldshouldbeprogrammedto1forproperfunctioningofuSDHCexternalinterface.
NOTEThesearenotnecessarilythedefaultconfigurationafterchipresets.
Youmustensuretheabovechipconfigurationtomatchthemeasurementsinthissection.
CommunicationmodulesS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors436.
5.
2.
1SDRmodetimingspecificationsFigure23.
SDRCMD-DATxReadTimingFigure24.
SDRCMD-DATxWriteTimingTable36.
SDRmodetimingspecificationIDParameterSymbolsMinMaxUnitCardInputClockSD1ClockFrequency(LowSpeed)fPP10400kHzClockFrequency(SD/SDIOFullSpeed/HighSpeed)fPP2025/50MHzClockFrequency(MMCFullSpeed/HighSpeed)fPP3020/52MHzClockFrequency(IdentificationMode)fOD100400kHzSD2ClockDutyCycletDC4555%eSDHCOutput/CardInputsCMD,DAT(ReferencetoCLK)Tablecontinuesonthenextpage.
.
.
CommunicationmodulesS32V234DataSheet,Rev.
9,03/202044NXPSemiconductorsTable36.
SDRmodetimingspecification(continued)IDParameterSymbolsMinMaxUnitSD3CLKtoData/CMDValidtDVO—3.
2nsSD4CLKtoData/CMDInvalidtHO-6.
3—nseSDHCInput/CardOutputsCMD,DAT(ReferencetoCLK)SD5DATA/CMDInputSetuptimetSUI4.
5—nsSD6DATA/CMDInputHoldtimetHI0—ns1.
Inlowspeedmode,cardclockmustbelowerthan400kHz,voltagerangesfrom2.
7to3.
6V.
2.
Innormal(full)speedmodeforSD/SDIOcard,clockfrequencycanbeanyvaluebetween0–25MHz.
Inhigh-speedmode,clockfrequencycanbeanyvaluebetween0–50MHz.
3.
Innormal(full)speedmodeforMMCcard,clockfrequencycanbeanyvaluebetween0–20MHz.
Inhigh-speedmode,clockfrequencycanbeanyvaluebetween0–52MHz.
6.
5.
2.
2DDRmodetimingspecificationsFigure25.
DDRDataReadtimingCommunicationmodulesS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors45Figure26.
DDRDATAWritetimingFigure27.
DDRCMDReadTimingFigure28.
DDRCMDWriteTimingCommunicationmodulesS32V234DataSheet,Rev.
9,03/202046NXPSemiconductorsTable37.
DDRmodetimingspecificationIDParameterSymbolsMinMaxUnitCardInputClockDD1ClockFrequency(eMMC4.
4DDR)fPP052MHzDD1ClockFrequency(SD3.
0DDR)fPP050MHzDD2ClockDutyCycletDC4555%uSDHCOutput/CardInputsCMD,DAT(ReferencetoCLK)DD3CLKtoDataValidtDVO—6.
2nsDD4CLKtoDataInvalidtHO2.
5—nsDD5CLKtoCMDValidtDVO—3.
25nsDD6CLKtoCMDInvalidtHO–6.
2—nsuSDHCInput/CardOutputsCMD,DAT(ReferencetoCLK)DD7DataInputSetupTimetSUI2.
3—nsDD8DataInputHoldTimetHI1.
5—nsDD9CMDInputSetupTimetSUI4.
5—nsDD10CMDInputHoldTimetHI0—nsCommunicationmodulesS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors47LFASTelectricalcharacteristics6.
5.
3.
1LFASTinterfacetimingdiagramsFigure29.
LFASTtimingdefinition6.
5.
3LFASTelectricalcharacteristicsS32V234DataSheet,Rev.
9,03/202048NXPSemiconductorsDifferentialTXDataLinespad_p/pad_nTriseTfall90%10%VIHVILFigure30.
Rise/falltime6.
5.
3.
2LFASTInterfaceelectricalcharacteristicsTable38.
LFASTelectricalcharacteristicsSymbolParameterConditionsValue1UnitMinTypMaxVDDIO_LFASTOperatingsupplyconditions—1.
71—1.
95VDataRateDATARATEDatarate——312/320Typ+0.
1%MbpsSTARTUPTSTRT_BIASBiasstartuptime2——0.
53sTRANSMITTERVOS_DRFCommonmodevoltage—1.
11.
21.
475V|ΔVOD_DRF|Differentialoutputvoltageswing(terminated)—250350450mVTTR_DRFRise/Falltime(20%-80%ofswing)3—0.
1—0.
73nsCOUT_DRFCapacitance4———5pFRECEIVERVICOM_DRFCommonmodevoltage—0.
155—1.
56V|ΔVI_DRF|DifferentialinputvoltageVICOM_DRF>1.
4VVICOM_DRF1.
5MHzNotspecified0.
15(max)UITTX-LF-RMSTxRMSjitter1Gbps.
2.
whenD-PHYissupportingmaximumdatarate=1Gbps.
6.
6.
3.
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Debugspecifications6.
7.
1JTAGinterfacetimingMeasurementsarewithaloadof45pFonoutputpins.
Inputslew=1ns,SIUL2_MSCRn[DSE]=101,andSIUL2_MSCRn[SRE]=11.
6.
7DebugspecificationsS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors69NOTEThesearenotnecessarilythedefaultconfigurationafterchipresets.
Youmustensuretheabovechipconfigurationtomatchthemeasurementsinthissection.
Table58.
JTAGpinACelectricalcharacteristics1#SymbolCharacteristicMinMaxUnit1tJCYCJTAG/SWDTCKCycleTime2253-nsCJTAGTCKCycleTime504-ns2tJDCTCKClockPulseWidth4060%3tTCKRISETCKRiseandFallTimes(40%-70%)-1ns4tTMSS,tTDISTMS,TDIDataSetupTime5-ns5tTMSH,tTDIHTMS,TDIDataHoldTime5-ns6tTDOVTCKLowtoTDODataValid-185ns7tTDOITCKLowtoTDODataInvalid0-ns8tTDOHZTCKLowtoTDOHighImpedance-18ns9tJCMPPWJCOMPAssertionTime100-ns10tJCMPSJCOMPSetupTimetoTCKLow40-ns11tBSDVTCKFallingEdgetoOutputValid-6006ns12tBSDVZTCKFallingEdgetoOutputValidoutofHighImpedance-600ns13tBSDHZTCKFallingEdgetoOutputHighImpedance-600ns14tBSDSTBoundaryScanInputValidtoTCKRisingEdge15-ns15tBSDHTTCKRisingEdgetoBoundaryScanInputInvalid15-ns1.
Thesespecificationsapplytoboundaryscan,JTAGandCJTAG,andserialwiredebugmodes.
2.
ThistimingappliestoTDI,TDO,TMSpins,however,actualfrequencyislimitedbypadtypeforEXTESTinstructions.
Refertopadspecificationforallowedtransitionfrequency3.
Cycletimeis25nsassumingfullcycletiming.
Cycletimeis50nsassuminghalfcycletiming4.
Cycletimeis50nsassumingfullcycletiming.
Cycletimeis100nsassuminghalfcycletiming5.
TimingincludesTCKpaddelay,clocktreedelay,logicdelayandTDOoutputpaddelay.
6.
Appliestoallpins,limitedbypadslewrate.
RefertoIOdelayandtransitionspecificationandadd20nsforJTAGdelay.
Table59.
PCIeJTAGACelectricalcharacteristics1#SymbolCharacteristicMinMaxUnit1tJCYCTCKCycleTime2253-ns2tJDCTCKClockPulseWidth4060%3tTCKRISETCKRiseandFallTimes(40%-70%)-1ns4tTMSS,tTDISTMS,TDIDataSetupTime5-ns5tTMSH,tTDIHTMS,TDIDataHoldTime5-ns6tTDOVTCKLowtoTDODataValid-214ns7tTDOITCKLowtoTDODataInvalid0-ns8tTDOHZTCKLowtoTDOHighImpedance-21ns9tJCMPPWJCOMPAssertionTime100-nsTablecontinuesonthenextpage.
.
.
DebugspecificationsS32V234DataSheet,Rev.
9,03/202070NXPSemiconductorsTable59.
PCIeJTAGACelectricalcharacteristics1(continued)#SymbolCharacteristicMinMaxUnit10tJCMPSJCOMPSetupTimetoTCKLow40-ns11tBSDVTCKFallingEdgetoOutputValid-6005ns12tBSDVZTCKFallingEdgetoOutputValidoutofHighImpedance-600ns13tBSDHZTCKFallingEdgetoOutputHighImpedance-600ns14tBSDSTBoundaryScanInputValidtoTCKRisingEdge15-ns15tBSDHTTCKRisingEdgetoBoundaryScanInputInvalid15-ns1.
Thesespecificationsapplytoboundaryscan,JTAGandCJTAG,andserialwiredebugmodes.
2.
ThistimingappliestoTDI,TDO,TMSpins,however,actualfrequencyislimitedbypadtypeforEXTESTinstructions.
Refertopadspecificationforallowedtransitionfrequency3.
Cycletimeis25nsassumingfullcycletiming.
Cycletimeis50nsassuminghalfcycletiming.
4.
TimingincludesTCKpaddelay,clocktreedelay,logicdelayandTDOoutputpaddelay.
5.
Appliestoallpins,limitedbypadslewrate.
RefertoIOdelayandtransitionspecificationandadd20nsforJTAGdelay.
TCK12233Figure52.
JTAGtestclockinputtimingDebugspecificationsS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors71TCK45678TMS,TDITDOFigure53.
JTAGtestaccessporttimingTCKJCOMP910Figure54.
JTAGJCOMPtimingDebugspecificationsS32V234DataSheet,Rev.
9,03/202072NXPSemiconductorsTCKOutputSignalsInputSignalsOutputSignals1112131415Figure55.
JTAGboundaryscantiming6.
7.
2DebugtracetimingspecificationsMeasurementsarewithaloadof20pFonoutputpins.
Inputslew=1ns,SIUL2_MSCRn[DSE]=111,andSIUL2_MSCRn[SRE]=11.
NOTEThesearenotnecessarilythedefaultconfigurationafterchipresets.
Youmustensuretheabovechipconfigurationtomatchthemeasurementsinthissection.
Table60.
DebugtraceoperatingbehaviorsSymbolDescriptionMin.
Max.
TypicalUnitTcycClockfrequency—150—MHzTwlLowpulsewidth2.
8—2.
95nsTablecontinuesonthenextpage.
.
.
DebugspecificationsS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors73Table60.
Debugtraceoperatingbehaviors(continued)SymbolDescriptionMin.
Max.
TypicalUnitTwhHighpulsewidth2.
8—2.
95nstDVDataoutputvalid—2.
21.
3nstHODataoutputhold0—0nsFigure56.
TRACE_CLKOUTspecifications6.
8WakeupUnit(WKPU)ACspecificationsTable61.
WKPUglitchfilterspecificationsSymbolParameterMinTypMaxUnitWFNMINMIpulsewidththatisrejected--20nsWNFNMINMIpulsewidththatispassed400--ns6.
9RESETpinglitchfilterspecificationsTable62.
RESETpinglitchfilterspecificationsSymbolParameterMinTypMaxUnitWFRESETRESETpulsewidththatisrejected--20nsWNFRESETRESETpulsewidththatispassed400--ns6.
10Externalinterrupttiming(IRQpin)Table63.
ExternalinterrupttimingNo.
SymbolParameterConditionsMinMaxUnit1tIPWLIRQpulsewidthlow-3-tCYCTablecontinuesonthenextpage.
.
.
DebugspecificationsS32V234DataSheet,Rev.
9,03/202074NXPSemiconductorsTable63.
Externalinterrupttiming(continued)No.
SymbolParameterConditionsMinMaxUnit2tIPWHIRQpulsewidthhigh-3-tCYC3tICYCIRQedgetoedgetime1-6-tCYC1.
ApplieswhenIRQpinsareconfiguredforrisingedgeorfallingedgeevents,butnotboth.
IRQ123Figure57.
ExternalinterrupttimingThermalattributes7.
1ThermalattributesTable64.
ThermalResistanceDataSymbolParameterConditionsEstimates(w/Lid)UnitRθJAJunctiontoAmbientNaturalConvection1Singlelayerboard(1s)29°C/WRθJAJunctiontoAmbientNaturalConvection1Fourlayerboard(2s2p)18°C/WRθJMAJunctiontoAmbient(@200ft/min)1Singlelayerboard(1s)20°C/WRθJMAJunctiontoAmbient(@200ft/min)1Fourlayerboard(2s2p)13°C/WRθJBJunctiontoBoard2Fourlayerboard(2s2p)6°C/WRθJCtopJunctiontoCase(Top)2Fourlayerboard(2s2p)1°C/WJunctiontoLidTop3Fourlayerboard(2s2p)0.
32°C/W1.
Junction-to-AmbientThermalResistancedeterminedperJEDECJESD51-3andJESD51-6.
ThermaltestboardmeetsJEDECspecificationforthispackage.
2.
Junction-to-CaseatthetopofthepackagedeterminedusingMIL-STD883Method1012.
1.
Thecoldplatetemperatureisusedforthecasetemperature.
Reportedvalueincludesthethermalresistanceoftheinterfacelayer.
3.
Junction-to-Lid-TopthermalresistancedeterminedusingtheusingMIL-STD883Method1012.
1.
However,insteadofthecoldplate,thelidtoptemperatureisusedhereforthereferencecasetemperature.
Reportedvaluedoesnotincludethethermalresistanceoftheinterfacelayerbetweenthepackageandcoldplate.
7ThermalattributesS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors75Dimensions8.
1ObtainingpackagedimensionsPackagedimensionsareprovidedinpackagedrawings.
Tofindapackagedrawing,gotonxp.
comandperformakeywordsearchforthedrawing'sdocumentnumber:PackageBodysizePitchNXPdocumentnumber621FC-BGA17mmx17mm0.
65mm98ASA00819DPinouts9.
1PackagepinoutsandsignaldescriptionsForpackagepinoutsandsignaldescriptions,refertotheReferenceManual.
10ResetsequenceThissectiondescribesdifferentresetsequencesanddetailsthedurationforwhichthedeviceremainsinresetconditionineachofthoseconditions.
10.
1ResetsequencedurationTable65specifiestheminimumandthemaximumresetsequencedurationforthefivedifferentresetsequencesdescribedinResetsequencedescription.
Table65.
RESETsequences1No.
SymbolParameterTResetUnitMinTypMax1TDRBDestructiveResetSequence,AllLBIST/MBISTenabled25—~50ms2TDRDestructiveResetSequence,BISTdisabled50—90s3TERLBExternalResetSequenceLong,UnsecureBoot,BISTenabled25—~50msTablecontinuesonthenextpage.
.
.
89DimensionsS32V234DataSheet,Rev.
9,03/202076NXPSemiconductorsTable65.
RESETsequences1(continued)No.
SymbolParameterTResetUnitMinTypMax4TFRLFunctionalResetSequenceLong,UnsecureBoot,BISTdisabled50—90s5TFRSFunctionalResetSequenceShort,UnsecureBoot,BISTdisabled2—7s1.
AlltheResetdurationsassumebootcodeexecutiontimeforExecute-in-placeforQuadSPIbooting,UnsecuremodewithTrimmedFIRCmodule.
BootcodeisusingexecutionusingPLLandnoDCDdownloadisassumed.
SecureBootdurationandDCDdownloadtimeisdependentonthegivenapplicationimage.
DCDdownloadsandapplicationimagedownload/authenticationtimeswillbeoverandabovethesedurations.
10.
2BootperformancematrixTotalBootexecutiontimewillbetheadditionofDCDexecutiontimetoconfigureDDRandapplicationimagedownloadtime.
Table66.
BootexecutiontimeBootsourceQSPI_CLOCKCSE_CLOCKCM4clock(corecounterregisterclock)QSPIconfigurationSRAM(FASTBOOT)NonsecureDCDexecutiontimeforDDRDDR(FASTBOOT)DDR(FASTBOOT)DDR(FASTBOOT)DDR(FASTBOOT)AuthenticationtimefromDDRAuthenticationtimefromDDRAuthenticationtimefromDDRBootLengthinbytes100MHz133MHz133MHzHyperFlash4MbytesNA4MB256KB128KB32KBNANANAAuthenticationLengthinbytes100MHz133MHz133MHzHyperFlashNANANANANANA256KB128KB32KBTimeinms100MHz133MHz133MHzHyperFlash27.
3023.
4725.
3471.
630.
8190.
2117.
4165254.
1540551.
7064075ResetsequenceS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors771.
74.
17.
40510CSEAUTHENTICATIONTIMEFROMDDRTimeinmsAuthenticationLength256kB128kB32kB0.
20.
821.
625.
3DDR(FASTBOOT)TimeinmsBootLength4MB256kB128kB32kB3.
47msCLOCKINITIALIZATIONANDQSPIINITRESETAFTERSELFTESTJUMPTOAPPLICATIONCODECSEFIRMWAREDOWNLOAD+APPLICATIONIMAGEAUTHENTICATION(SECUREBOOT)APPLICATIONIMAGEDOWNLOADDCDEXECUTIONTOCONFIGUREDDRFigure58.
Bootdiagram10.
3ResetsequencedescriptionThefiguresinthissectionshowtheinternalstatesofthedeviceduringthefivedifferentresetsequences.
ThedotedlinesinthefiguresindicatethestartingpointandtheendpointforwhichthedurationisspecifiedinTable65.
Theapplicationcodeexecutionstartswhenbootcodehasfinishedallthemandatorytasksandjumpsoverthedownloadedimage.
ThedownloadtimeandauthenticationtimewillvaryasperApplicationcodeimagesize.
"EXT_POR"pin(ActiveLow)isrecommendedtobede-assertedafterexternalsuppliesbecamestable.
DeassertionofEXT_PORpintriggersthestartofresetsequence.
ThefollowingfiguresshowtheinternalstatesofthedeviceduringtheexecutionoftheresetsequenceandthepossiblestatesoftheRESET(Active-low)signalpin.
NOTERESET(Active-low)isabidirectionalpin.
Thevoltagelevelonthispincaneitherbedrivenlowbyanexternalresetgeneratororbythedeviceinternalresetcircuitry.
Ahighlevelonthispincanonlybegeneratedbyanexternalpullupresistor(10-15kiloohm)whichisstrongenoughtooverdrivetheweakinternalpulldownresistor.
TherisingedgeonRESET(Active-low)inthefollowingfiguresindicatesthetimewhenthedevicestopsResetsequenceS32V234DataSheet,Rev.
9,03/202078NXPSemiconductorsdrivingitlow.
TheresetsequencedurationsgiveninTable65areapplicableonlyiftheinternalresetsequenceisnotprolongedbyanexternalresetgeneratorkeepingRESET(Active-low)assertedlowbeyondthelastPhase3.
PHASE0PHASE1,2PHASE3PHASE1,2PHASE3DRUNBISTResetSequenceTriggerResetSequenceStartConditionRESETEstablishFuseDeviceApplicationFIRCandPWRInitConfigFuseInitDeviceConfigTDRB,minchangedtoSIUL2_MSCRn[DSE].
FSEL[1:0]changedtoSIUL2_MSCRn[SRE].
ipp_fselchangedtoSIUL2_MSCRn[SRE].
Deletedthetestconditionaboutipp_do.
Addedanotetothefollowingsectionstoclarifythattomatchwiththemeasurementsgiveninthesectionyoumustensuretheconfigurationmentioned.
Thatmaynotbethedefaultconfigurationofthechipafterreset.
QuadSPIACspecificationsDSPItimingUltraHighSpeedSD/SDIO/MMCHostInterface(uSDHC)EthernetSwitchingSpecificationsMII/RMIISerialManagementchanneltiming(MDC/MDIO)InterfacetoTFTpanelsTablecontinuesonthenextpage.
.
.
RevisionhistoryS32V234DataSheet,Rev.
9,03/202088NXPSemiconductorsTable68.
Revisionhistory(continued)RevisionDateDescriptionofchangesJTAGinterfacetimingDebugtracetimingspecificationsElectrostaticdischarge(ESD)specifications-RemovedtheVESD(CDM)specsforcornerpins.
708/2018GPIOspeedatvariousvoltagelevels-Addedthetext"ThemaximumrisetimeforallGPIOpinsis1ms"totheexistingnote.
Powersequencingrequirements-Updatedthelastbulletto"ThemaximumrisetimeforthePORandRESET.
thispincanincreasetheproblem.
".
812/2018ChangedallinstancesofXOSCtoFXOSCthroughoutthedocument.
InTable1-ForS32V232changed"Upto800MHzDualARMCortex-A53(singlecluster)"to"Upto1000MHzDualARMCortex-A53(singlecluster)"andincommunicationsrowremovedallthetextandaddedtext"SameasS32V234"forS32V232.
InOrderinginformation-Changedtextfrom"Theorderablepartnumbersofthischipareinthetablebelow"to"Anexampleoforderablepartnumbersofthischipareinthetablebelow".
InGPIOspeedatvariousvoltagelevels-AddedtheDriveStrength"001"and"010"inthe"GPIOrise/falltimes(1.
8Vrange)","GPIOrise/falltimes(2.
5Vrange)"and"GPIOrise/falltimes(3.
3Vrange)"tables.
InFeatures-Removedthetext"ARMTrustZone(TZ)architecturesupport"andaddedtext"Securevsnon-secureapplicationsseparationsupportedviaARMv8exceptionlevelsupportintheARMCortexA53clustersanditsextensionviaXRDConSoClevel".
InTable5updatedthefollowing:Replaceddescriptivetextwithorderablepartnumber.
Removed@125Cfromeachrow.
Splittherow"DD_LV_CORE"into"DD_LV_CORE(static)"and"DD_LV_CORE(dynamic)"intoseparaterows.
Added"Tj"asthetemperatureinthefootnote.
Addedfurtherstaticpowerentries.
Addedvaluesfor125Tjand105TjforVDD_LV_CORE(Static).
Addedparameters"VDD_HV_ADV"and"VDD_REFH_ADC".
InDDR3andDDR3LtimingparametersaddedNote"DDR3andDDR3LtimingparametersarecompliantwithJESD79-3FandJESD79-3-1A.
01specificationsrespectively".
InLPDDR2timingparameteraddedNote"LPDDR2timingparametersarecompliantwithJESD209-2Bspecification".
901/2020InOrderinginformation:AddedFigure1.
Addedanote"Forthelatestinformationonorderablepartspleasecheckhttps://www.
nxp.
com/s32v234Buy/Parametricssection".
InFeatureschangedthetextfrom"Securevsnon-secureapplicationsseparationsupportedviaARMv8exceptionlevelsupportintheARMCortexA53clustersanditsextensionviaXRDConchiplevel"to"ARMTrustZone(TZ)architecturesupport".
InTable2removedthe"OperatingMaxSupplyVoltage"rows.
RemovedtheMaximumandMinimumvaluesofVttandaddedafootnoteinTable13andTable12.
Updatedthetextfrom"Supplydomainsbelongingtothesamesupplygrouparesupposedtobegangedtogetheronboardlevel(withappropriatenoiseisolation)toallowthisgrouptopowerup/downtogether"to"Powersuppliesinthesamegroupmustbepoweredup/downtogether.
Supplygroupsbelongingtothesamesupplydomaincanbegangedtogetheronboardlevel(withappropriatenoiseisolation)toallowthesegroupstopowerup/downtogether"inPowersequencingrequirements.
InTable38for|ΔVI_DRF|addedtheconditions"VICOM_DRF>1.
4V"and"VICOM_DRF<=1.
4V".
RevisionhistoryS32V234DataSheet,Rev.
9,03/2020NXPSemiconductors89HowtoReachUs:HomePage:nxp.
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DocumentNumberS32V234Revision9,03/2020