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Si5345/44/42RevDDataSheet10-Channel,Any-Frequency,Any-OutputJitterAttenuator/ClockMultiplierThesejitterattenuatingclockmultiplierscombinefourth-generationDSPLLandMultiSynthtechnologiestoenableany-frequencyclockgenerationandjitterattenu-ationforapplicationsrequiringthehighestlevelofjitterperformance.
Thesedevicesareprogrammableviaaserialinterfacewithin-circuitprogrammablenon-volatilememory(NVM)sotheyalwayspowerupwithaknownfrequencyconfiguration.
Theysupportfree-run,synchronous,andholdovermodesofoperation,andofferbothau-tomaticandmanualinputclockswitching.
Theloopfilterisfullyintegratedon-chip,eliminatingtheriskofnoisecouplingassociatedwithdiscretesolutions.
Furthermore,thejitterattenuationbandwidthisdigitallyprogrammable,providingjitterperform-anceoptimizationattheapplicationlevel.
ProgrammingtheSi5345/44/42iseasywithSiliconLabs'ClockBuilderProsoftware.
Factorypreprogrammeddevicesarealsoavailable.
Applications:OTNmuxpondersandtransponders10/40/100GnetworkinglinecardsGbE/10GbE/100GbESynchronousEthernet(ITU-TG.
8262)CarrierEthernetswitchesSONET/SDHlinecardsBroadcastvideoTestandmeasurementITU-TG.
8262(SyncE)compliantKEYFEATURESGeneratesanycombinationofoutputfrequenciesfromanyinputfrequencyUltra-lowjitterof90fsrmsExternalCrystal:25to54MHzInputfrequencyrangeDifferential:8kHzto750MHzLVCMOS:8kHzto250MHzOutputfrequencyrangeDifferential:100Hzto1028MHzLVCMOS:100Hzto250MHzMeetsG.
8262EECOption1,2(SyncE)HighlyconfigurableoutputscompatiblewithLVDS,LVPECL,LVCMOS,CML,andHCSLwithprogrammablesignalamplitudeSi5345:4input,10output,64-QFN9*9mmSi5344:4input,4output,44-QFN7*7mmSi5342:4input,2output,44-QFN7*7mmUpto10OutputClocksSi5344Si5345I2C/SPIControlNVMStatusFlagsStatusMonitorXBXA25-54MHzXTALOSCMultiSynthMultiSynthMultiSynthMultiSynthMultiSynthDSPLLSi53424InputClocksIN0IN1IN2IN3/FB_INOUT7OUT6OUT5OUT1OUT4OUT3OUT2OUT0÷INT÷INT÷INT÷INT÷INT÷INT÷INT÷INTOUT9OUT8÷INT÷INT÷FRAC÷FRAC÷FRAC÷FRACsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
21.
FeaturesListTheSi5345/44/42RevDfeaturesarelistedbelow:Generatesanycombinationofoutputfrequenciesfromanyin-putfrequencyUltra-lowjitterof90fsrmsInputfrequencyrangeDifferential:8kHz–750MHzLVCMOS:8kHz–250MHzOutputfrequencyrangeDifferential:100Hzto1028MHzLVCMOS:100Hzto250MHzProgrammablejitterattenuationbandwidth:0.
1Hzto4kHzMeetsG.
8262EECOption1,2(SyncE)HighlyconfigurableoutputscompatiblewithLVDS,LVPECL,LVCMOS,CML,andHCSLwithprogrammablesignalampli-tudeStatusmonitoring(LOS,OOF,LOL)Hitlessinputclockswitching:automaticormanualLockstogappedclockinputsFree-runandholdovermodesOptionalzerodelaymodeFastlockfeatureforlownominalbandwidthsGlitchlessontheflyoutputfrequencychangesDCOmode:aslowas0.
001ppbstepsizeCorevoltageVDD:1.
8V±5%VDDA:3.
3V±5%Independentoutputclocksupplypins3.
3V,2.
5V,or1.
8VSerialinterface:I2CorSPIIn-circuitprogrammablewithnon-volatileOTPmemoryClockBuilderProsoftwaresimplifiesdeviceconfigurationSi5345:4input,10output,64-QFN9*9mmSi5344:4input,4output,44-QFN7*7mmSi5342:4input,2output,44-QFN7*7mmTemperaturerange:–40to+85°CPb-free,RoHS-6compliantSi5345/44/42RevDDataSheetFeaturesListsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|22.
OrderingGuideOrderingPartNumber(OPN)NumberofInput/OutputClocksOutputClockFrequencyRange(MHz)SupportedFrequencySynthesisModesPackageTemperatureRangeSi5345Si5345A-D-GM1,24/100.
001to1028MHzIntegerandFractional64-QFN9*9mm–40to85°CSi5345B-D-GM1,20.
001to350MHzSi5345C-D-GM1,20.
001to1028MHzIntegerOnlySi5345D-D-GM1,20.
001to350MHzSi5344Si5344A-D-GM1,24/40.
001to1028MHzIntegerandFractional44-QFN7*7mm–40to85°CSi5344B-D-GM1,20.
001to350MHzSi5344C-D-GM1,20.
001to1028MHzIntegerOnlySi5344D-D-GM1,20.
001to350MHzSi5342Si5342A-D-GM1,24/20.
001to1028MHzIntegerandFractional44-QFN7*7mm–40to85°CSi5342B-D-GM1,20.
001to350MHzSi5342C-D-GM1,20.
001to1028MHzIntegerOnlySi5342D-D-GM1,20.
001to350MHzSi5345/44/42-D-EVBSi5345-D-EVB———EvaluationBoard—Si5344-D-EVBSi5342-D-EVBNotes:1.
AddanRattheendoftheOPNtodenotetapeandreelorderingoptions.
2.
Custom,factorypreprogrammeddevicesareavailable.
OrderingpartnumbersareassignedbySiliconLabsandtheClockBuilderProsoftware.
Custompartnumberformatis"Si5345A-Dxxxxx-GM"where"xxxxx"isauniquenumericalsequencerepresentingthepreprogrammedconfiguration.
Si5345/44/42RevDDataSheetOrderingGuidesilabs.
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Rev.
1.
2|3Figure2.
1.
OrderingPartNumberFieldsSi5345/44/42RevDDataSheetOrderingGuidesilabs.
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Rev.
1.
2|4TableofContents1.
FeaturesList22.
OrderingGuide33.
FunctionalDescription.
73.
1FrequencyConfiguration73.
2DSPLLLoopBandwidth73.
3FastlockFeature73.
4ModesofOperation73.
4.
1InitializationandReset83.
4.
2FreerunMode83.
4.
3LockAcquisitionMode83.
4.
4LockedMode83.
4.
5HoldoverMode93.
5ExternalReference(XA/XB)93.
6DigitallyControlledOscillator(DCO)Mode103.
7Inputs(IN0,IN1,IN2,IN3)103.
7.
1ManualInputSwitching(IN0,IN1,IN2,IN3)103.
7.
2AutomaticInputSelection(IN0,IN1,IN2,IN3)113.
7.
3HitlessInputSwitching113.
7.
4RampedInputSwitching113.
7.
5GlitchlessInputSwitching113.
7.
6InputConfigurationandTerminations123.
7.
7SynchronizingtoGappedInputClocks133.
8FaultMonitoring133.
8.
1InputLOSDetection.
143.
8.
2XA/XBLOSDetection143.
8.
3OOFDetection143.
8.
4LOLDetection.
153.
8.
5InterruptPin(INTRb)163.
9Outputs163.
9.
1OutputCrosspoint173.
9.
2OutputSignalFormat173.
9.
3DifferentialOutputTerminations.
183.
9.
4LVCMOSOutputTerminations183.
9.
5ProgrammableCommonModeVoltageForDifferentialOutputs183.
9.
6LVCMOSOutputImpedanceSelection193.
9.
7LVCMOSOutputSignalSwing193.
9.
8LVCMOSOutputPolarity193.
9.
9OutputEnable/Disable193.
9.
10OutputDriverStateWhenDisabled193.
9.
11SynchronousOutputDisableFeature193.
9.
12ZeroDelayMode203.
9.
13OutputDivider(R)Synchronization20silabs.
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10PowerManagement.
203.
11In-CircuitProgramming.
203.
12SerialInterface213.
13CustomFactoryPreprogrammedParts213.
14EnablingFeaturesand/orConfigurationSettingsUnavailableinClockBuilderProforFactoryPreprogrammedDevices214.
RegisterMap235.
ElectricalSpecifications246.
TypicalApplicationSchematic397.
DetailedBlockDiagrams408.
TypicalOperatingCharacteristics439.
PinDescriptions4510.
PackageOutlines5110.
1Si53459x9mm64-QFNPackageDiagram5110.
2Si5344andSi53427x7mm44-QFNPackageDiagram.
5211.
PCBLandPattern5312.
TopMarking5513.
DeviceErrata5614.
RevisionHistory.
57silabs.
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2|63.
FunctionalDescriptionTheSi5345'sinternalDSPLLprovidesjitterattenuationandany-frequencymultiplicationoftheselectedinputfrequency.
Fractionalin-putdividers(P)allowtheDSPLLtoperformhitlessswitchingbetweeninputclocks(INx)thatarefractionallyrelated.
Inputswitchingiscontrolledmanuallyorautomaticallyusinganinternalstatemachine.
Theoscillatorcircuit(OSC)providesafrequencyreferencewhichdeterminesoutputfrequencystabilityandaccuracywhilethedeviceisinfree-runorholdovermode.
Thehigh-performanceMultiSynthdividers(N)generateintegerorfractionallyrelatedoutputfrequenciesfortheoutputstage.
AcrosspointswitchconnectsanyoftheMultiSynthgeneratedfrequenciestoanyoftheoutputs.
Additionalintegerdivision(R)determinesthefinaloutputfrequency.
3.
1FrequencyConfigurationThefrequencyconfigurationoftheDSPLLisprogrammablethroughtheserialinterfaceandcanalsobestoredinnon-volatilememory.
Thecombinationoffractionalinputdividers(Pn/Pd),fractionalfrequencymultiplication(Mn/Md),fractionaloutputMultiSynthdivision(Nn/Nd),andintegeroutputdivision(Rn)allowsthegenerationofvirtuallyanyoutputfrequencyonanyoftheoutputs.
AlldividervaluesforaspecificfrequencyplanareeasilydeterminedusingtheClockBuilderProsoftware.
3.
2DSPLLLoopBandwidthTheDSPLLloopbandwidthdeterminestheamountofinputclockjitterattenuation.
RegisterconfigurableDSPLLloopbandwidthset-tingsintherangeof0.
1Hzto4kHzareavailableforselection.
Sincetheloopbandwidthiscontrolleddigitally,theDSPLLwillalwaysremainstablewithlessthan0.
1dBofpeakingregardlessoftheloopbandwidthselection.
3.
3FastlockFeatureSelectingalowDSPLLloopbandwidth(e.
g.
0.
1Hz)willgenerallylengthenthelockacquisitiontime.
ThefastlockfeatureallowssettingatemporaryFastlockLoopBandwidththatisusedduringthelockacquisitionprocess.
Higherfastlockloopbandwidthsettingswillena-bletheDSPLLstolockfaster.
FastlockLoopBandwidthsettingsofintherangeof100Hzto4kHzareavailableforselection.
TheDSPLLwillreverttoitsnormalloopbandwidthoncelockacquisitionhascompleted.
3.
4ModesofOperationOnceinitializationiscompletetheDSPLLoperatesinoneoffourmodes:Free-runMode,LockAcquisitionMode,LockedMode,orHoldoverMode.
AstatediagramshowingthemodesofoperationisshowninFigure3.
1ModesofOperationonpage8.
Thefollow-ingsectionsdescribeeachofthesemodesingreaterdetail.
Si5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|73.
4.
1InitializationandResetOncepowerisapplied,thedevicebeginsaninitializationperiodwhereitdownloadsdefaultregistervaluesandconfigurationdatafromNVMandperformsotherinitializationtasks.
Communicatingwiththedevicethroughtheserialinterfaceispossibleoncethisinitializa-tionperiodiscomplete.
Noclockswillbegenerateduntiltheinitializationiscomplete.
Therearetwotypesofresetsavailable.
Ahardresetisfunctionallysimilartoadevicepower-up.
AllregisterswillberestoredtothevaluesstoredinNVM,andallcircuitsincludingtheserialinterfacewillberestoredtotheirinitialstate.
AhardresetisinitiatedusingtheRSTbpinorbyassertingthehardresetregisterbit.
AsoftresetbypassestheNVMdownload.
Itissimplyusedtoinitiateregisterconfigurationchanges.
NovalidinputclocksselectedLockAcquisition(FastLock)LockedModeHoldoverModePhaselockonselectedinputclockisachievedAninputisqualifiedandavailableforselectionNovalidinputclocksavailableforselectionFree-runValidinputclockselectedResetandInitializationPower-UpSelectedinputclockfailsYesNoHoldoverHistoryValidOtherValidClockInputsAvailableNoYesInputClockSwitchFigure3.
1.
ModesofOperation3.
4.
2FreerunModeTheDSPLLwillautomaticallyenterfreerunmodeoncepowerisappliedtothedeviceandinitializationiscomplete.
Thefrequencyac-curacyofthegeneratedoutputclocksinfreerunmodeisentirelydependentonthefrequencyaccuracyoftheexternalcrystalorrefer-enceclockontheXA/XBpins.
Forexample,ifthecrystalfrequencyis±100ppm,thenalltheoutputclockswillbegeneratedattheirconfiguredfrequency±100ppminfreerunmode.
Anydriftofthecrystalfrequencywillbetrackedattheoutputclockfrequencies.
ATCXOorOCXOisrecommendedforapplicationsthatneedbetterfrequencyaccuracyandstabilitywhileinfreerunorholdovermodes.
3.
4.
3LockAcquisitionModeThedevicemonitorsallinputsforavalidclock.
Ifatleastonevalidclockisavailableforsynchronization,theDSPLLwillautomaticallystartthelockacquisitionprocess.
Ifthefastlockfeatureisenabled,theDSPLLwillacquirelockusingtheFastlockLoopBandwidthsettingandthentransitiontotheDSPLLLoopBandwidthsettingwhenlockacquisitioniscomplete.
DuringlockacquisitiontheoutputswillgenerateaclockthatfollowstheVCOfrequencychangeasitpullsintotheinputclockfrequency.
3.
4.
4LockedModeOncelocked,theDSPLLwillgenerateoutputclocksthatarebothfrequencyandphaselockedtotheirselectedinputclocks.
Atthispoint,anyXTALfrequencydriftwillnotaffecttheoutputfrequency.
Alossoflockpin(LOL)andstatusbitindicatewhenlockisach-ieved.
See3.
8.
4LOLDetectionformoredetailsontheoperationoftheloss-of-lockcircuit.
Si5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
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Rev.
1.
2|83.
4.
5HoldoverModeTheDSPLLwillautomaticallyenterholdovermodewhentheselectedinputclockbecomesinvalidandnoothervalidinputclocksareavailableforselection.
TheDSPLLusesanaveragedinputclockfrequencyasitsfinalholdoverfrequencytominimizethedisturbanceoftheoutputclockphaseandfrequencywhenaninputclocksuddenlyfails.
TheholdovercircuitfortheDSPLLstoresupto120sec-ondsofhistoricalfrequencydatawhilelockedtoavalidclockinput.
Thefinalaveragedholdoverfrequencyvalueiscalculatedfromaprogrammablewindowwithinthestoredhistoricalfrequencydata.
Boththewindowsizeandthedelayareprogrammableasshowninthefigurebelow.
Thewindowsizedeterminestheamountofholdoverfrequencyaveraging.
Thedelayvalueallowsignoringfrequencydatathatmaybecorruptjustbeforetheinputclockfailure.
ProgrammabledelayClockFailureandEntryintoHoldovertime0HistoricalFrequencyDataCollectedProgrammablehistoricaldatawindowusedtodeterminethefinalholdovervalue120secondsFigure3.
2.
ProgrammableHoldoverWindowWhenenteringholdover,theDSPLLwillpullitsoutputclockfrequencytothecalculatedaveragedholdoverfrequency.
Whileinhold-over,theoutputfrequencydriftisentirelydependentontheexternalcrystalorexternalreferenceclockconnectedtotheXA/XBpins.
Iftheclockinputbecomesvalid,theDSPLLwillautomaticallyexittheholdovermodeandre-acquirelocktothenewinputclock.
Thisprocessinvolvespullingtheoutputclockfrequencytoachievefrequencyandphaselockwiththeinputclock.
Thispull-inprocessisglitchlessanditsrateiscontrolledbytheDSPLLortheFastlockbandwidth.
TheDSPLLoutputfrequencywhenexitingholdovercanberamped(recommend).
Justbeforetheexitisinitiated,thedifferencebe-tweenthecurrentholdoverfrequencyandthenewdesiredfrequencyismeasured.
Usingthecalculateddifferenceandauser-selecta-bleramprate,theoutputislinearlyrampedtothenewfrequency.
Therampratecanbe0.
2ppm/s,40,000ppm/s,oranyofabout40valuesinbetween.
TheDSPLLloopBWdoesnotlimitoraffectramprateselections(andviceversa).
CBProdefaultstorampedexitfromholdover.
Thesamerampratesettingsareusedforbothexitfromholdoverandrampedinputswitching.
Formoreinformationonrampedinputswitching,see3.
7.
4RampedInputSwitching.
Note:Iframpedholdoverexitisnotselected,theholdoverexitisgovernedeitherby(1)theDSPLLloopBWor(2)auser-selectableholdoverexitBW.
3.
5ExternalReference(XA/XB)Anexternalcrystal(XTAL)isusedincombinationwiththeinternaloscillator(OSC)toproduceanultralowjitterreferenceclockfortheDSPLLandforprovidingastablereferenceforthefree-runandholdovermodes.
AsimplifieddiagramisshowninFigure3.
3CrystalResonatorandExternalReferenceClockConnectionOptionsonpage10.
ThedeviceincludesinternalXTALloadingcapacitorswhicheliminatestheneedforexternalcapacitorsandalsohasthebenefitofreducednoisecouplingfromexternalsources.
RefertoTable5.
12CrystalSpecificationsonpage37forcrystalspecifications.
Acrystalintherangeof48MHzto54MHzisrecommendedforbestjitterperformance.
TheSi5345/44/42RevDFamilyReferenceManualprovidesadditionalinformationonPCBlayoutrecom-mendationsforthecrystaltoensureoptimumjitterperformance.
ToachieveoptimaljitterperformanceandminimizeBOMcost,acrystalisrecommendedontheXA/XBreferenceinput.
ForSyncEpizzaboxapplications(e.
g.
loopbandwidthsetto0.
1Hz),aTCXOisrequiredontheXA/XBreferencetominimizewanderandtopro-videastableholdoverreference.
SeetheSi5345/44/42RevDFamilyReferenceManualformoreinformation.
SelectionbetweentheexternalXTALorREFCLKiscontrolledbyregisterconfiguration.
Theinternalcrystalloadingcapacitors(CL)aredisabledintheREFCLKmode.
RefertoTable5.
3InputClockSpecificationsonpage26forREFCLKrequirementswhenusingthismode.
APREFdividerisavailabletoaccommodateexternalclockfrequencieshigherthan54MHz.
Frequenciesintherangeof48MHzto54MHzwillachievethebestoutputjitterperformance.
Si5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|93.
6DigitallyControlledOscillator(DCO)ModeTheoutputMultiSynthssupportaDCOmodewheretheiroutputfrequenciesareadjustableinpredefinedstepsdefinedbyfrequencystepwords(FSW).
Thefrequencyadjustmentsarecontrolledthroughtheserialinterfaceorbypincontrolusingfrequencyincrement(FINC)ordecrement(FDEC).
AFINCwilladdthefrequencystepwordtotheDSPLLoutputfrequency,whileaFDECwilldecrementit.
AnynumberofMultiSynthscanbeupdatedatonceorindependentlycontrolled.
TheDCOmodeisavailablewhentheDSPLLisoperat-ingineitherfree-runorlockedmode.
DifferentialXO/ClockConnection2xCL2xCLXBXAOSC÷PREF25-54MHzXO/ClockLVCMOSXO/ClockConnection2xCL2xCLXBXAOSC÷PREFR2R1C125-54MHzXO/ClockLVCMOSCrystalResonatorConnection2xCL2xCLXBXAOSC÷PREF25-54MHzXTALX1X2X1X2NCNCX1X2NCNCNote:SeePinDescriptionsforX1/X2connectionsC1isrecommendedtoincreasetheslewrateatXaSeetheReferenceManualfortherecommendedR1,R2,C1valuesFigure3.
3.
CrystalResonatorandExternalReferenceClockConnectionOptionsNote:SeeTable5.
3InputClockSpecificationsonpage26.
3.
7Inputs(IN0,IN1,IN2,IN3)TherearefourinputsthatcanbeusedtosynchronizetheDSPLL.
Theinputsacceptbothdifferentialandsingle-endedclocks.
Inputselectioncanbemanual(pinorregistercontrolled)orautomaticwithuserdefinablepriorities.
3.
7.
1ManualInputSwitching(IN0,IN1,IN2,IN3)InputclockselectioncanbemademanuallyusingtheIN_SEL[1:0]pinsorthrougharegister.
Aregisterbitdeterminesinputselectionaspinselectableorregisterselectable.
TheIN_SELpinsareselectedbydefault.
Ifthereisnoclocksignalontheselectedinput,thedevicewillautomaticallyenterfree-runorholdovermode.
Whenthezerodelaymodeisenabled,IN3becomesthefeedbackinput(FB_IN)andisnotavailableforselectionasaclockinput.
Table3.
1.
ManualInputSelectionUsingIN_SEL[1:0]PinsIN_SEL[1:0]SelectedInputZeroDelayModeDisabledZeroDelayModeEnabled00IN0IN001IN1IN110IN2IN211IN3ReservedSi5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
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Rev.
1.
2|103.
7.
2AutomaticInputSelection(IN0,IN1,IN2,IN3)Anautomaticinputselectionstatemachineisavailableinadditiontothemanualswitchingoption.
Inautomaticmode,theselectioncriteriaisbasedoninputclockqualification,inputpriority,andtherevertiveoption.
Onlyinputclocksthatarevalidcanbeselectedbytheautomaticclockselectionstatemachine.
IftherearenovalidinputclocksavailabletheDSPLLwillentertheholdovermode.
Withrevertiveswitchingenabled,thehighestpriorityinputwithavalidinputclockisalwaysselected.
Ifaninputwithahigherprioritybe-comesvalidthenanautomaticswitchovertothatinputwillbeinitiated.
Withnon-revertiveswitching,theactiveinputwillalwaysremainselectedwhileitisvalid.
Ifitbecomesinvalidanautomaticswitchovertoavalidinputwiththehighestprioritywillbeinitiated.
3.
7.
3HitlessInputSwitchingHitlessswitchingisafeaturethatpreventsaphaseoffsetfrompropagatingtotheoutputwhenswitchingbetweentwoclockinputsthathaveafixedphaserelationship.
Ahitlessswitchcanonlyoccurwhenthetwoinputfrequenciesarefrequencylockedmeaningthattheyhavetobeexactlyatthesamefrequency,oratafractionalfrequencyrelationshiptoeachother.
Whenhitlessswitchingisenabled,theDSPLLsimplyabsorbsthephasedifferencebetweenthetwoinputclocksduringainputswitch.
Whendisabled,thephasedifferencebetweenthetwoinputsispropagatedtotheoutputataratedeterminedbytheDSPLLLoopBandwidth.
Thehitlessswitchingfeaturesupportsclockfrequenciesdowntotheminimuminputfrequencyof8kHz.
3.
7.
4RampedInputSwitchingWhenswitchingbetweentwoplesiochronousinputclocks(i.
e.
,thefrequenciesare"almostthesame"butnotquite),rampedinputswitchingshouldbeenabledtoensureasmoothtransitionbetweenthetwoinputs.
RampedinputswitchingavoidsfrequencytransientsandovershootwhenswitchingbetweenfrequenciesandsoisthedefaultswitchingmodeinCBPro.
Thefeatureshouldbeturnedoffwhenswitchingbetweeninputclocksthatarealwaysfrequencylocked(i.
e.
,arealwaysthesameexactfrequency).
Thesamerampratesettingsareusedforbothholdoverexitandclockswitching.
Formoreinformationonrampedexitfromholdoversee3.
4.
5HoldoverMode.
3.
7.
5GlitchlessInputSwitchingTheDSPLLhastheabilityofswitchingbetweentwoinputclockfrequenciesthatareupto±500ppmapart.
TheDSPLLwillpull-intothenewfrequencyusingtheDSPLLLoopBandwidthorusingtheFastlockLoopBandwidthifenabled.
Thelossoflock(LOL)indicatorwillassertwhiletheDSPLLispulling-intothenewclockfrequency.
Therewillbenoabruptphasechangeattheoutputduringthetransi-tion.
Si5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
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Rev.
1.
2|113.
7.
6InputConfigurationandTerminationsEachoftheinputscanbeconfiguredasdifferentialorsingle-endedLVCMOS.
TherecommendedinputterminationschemesareshowninFigure14.
Differentialsignalsmustbeac-coupled,whilesingle-endedLVCMOSsignalscanbeac-ordc-coupled.
Unusedinputscanbedisabledandleftunconnectedwhennotinuse.
3.
3V,2.
5V,1.
8VLVCMOSINx50StandardAC-CoupledDifferential(IN0-IN3)INx50PulsedCMOSStandard50R1PulsedCMOSStandardSeetheReferenceManualfordetailsonR1andR2values.
RSmatchestheCMOSdrivertoa50ohmtransmissionline(ifused)StandardAC-CoupledSingle-Ended(IN0-IN3)PulsedCMOSDC-CoupledSingleEndedonlyforFrequencies1MHz,consultyourCBProdesignreportfortheFpfdfrequencyofyourcon-figuration.
6.
Delayisdependentonfrequencyconfiguration.
UsingFpfd<64kHzwillresultinhigherdelayvalues.
Si5345/44/42RevDDataSheetElectricalSpecificationssilabs.
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Rev.
1.
2|32Table5.
9.
I2CTimingSpecifications(SCL,SDA)ParameterSymbolTestConditionStandardMode100kbpsFastMode400kbpsUnitMinMaxMinMaxSCLClockFrequencyfSCL—100—400kHzSMBusTimeout—WhenTimeoutisEnabled25352535msHoldtime(Repeated)STARTconditiontHD:STA4.
0—0.
6—sLowPeriodoftheSCLClocktLOW4.
7—1.
3—sHIGHPeriodoftheSCLClocktHIGH4.
0—0.
6—sSetupTimeforaRepeatedSTARTConditiontSU:STA4.
7—0.
6—sDataHoldTimetHD:DAT100—100—nsDataSetupTimetSU:DAT250—100—nsRiseTimeofbothSDAandSCLSignalstr—100020300nsFallTimeofbothSDAandSCLSignalstf—300—300nsSetupTimeforSTOPCondi-tiontSU:STO4.
0—0.
6—sBusFreeTimebetweenaSTOPandSTARTConditiontBUF4.
7—1.
3—sDataValidTimetVD:DAT—3.
45—0.
9sDataValidAcknowledgeTimetVD:ACK—3.
45—0.
9sSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
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Rev.
1.
2|33Figure5.
1.
I2CSerialPortTimingStandardandFastModesSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
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Rev.
1.
2|34Table5.
10.
SPITimingSpecifications(4-Wire)VDD=1.
8V±5%,VDDA=3.
3V±5%,TA=–40to85°CParameterSymbolMinTypMaxUnitSCLKFrequencyfSPI——20MHzSCLKDutyCycleTDC40—60%SCLKPeriodTC50——nsDelayTime,SCLKFalltoSDOActiveTD1—12.
518nsDelayTime,SCLKFalltoSDOTD2—1015nsDelayTime,CSbRisetoSDOTri-StateTD3—1015nsSetupTime,CSbtoSCLKTSU15——nsHoldTime,SCLKFalltoCSbTH15——nsSetupTime,SDItoSCLKRiseTSU25——nsHoldTime,SDItoSCLKRiseTH25——nsDelayTimeBetweenChipSelects(CSb)TCS2——TCSCLKCSbSDISDOTSU1TD1TSU2TD2TCTCSTD3TH2TH1Figure5.
2.
4-WireSPISerialInterfaceTimingSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
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Rev.
1.
2|35Table5.
11.
SPITimingSpecifications(3-Wire)VDD=1.
8V±5%,VDDA=3.
3V±5%,TA=–40to85°CParameterSymbolMinTypMaxUnitSCLKFrequencyfSPI——20MHzSCLKDutyCycleTDC40—60%SCLKPeriodTC50——nsDelayTime,SCLKFalltoSDIOTurn-onTD1—12.
520nsDelayTime,SCLKFalltoSDIONext-bitTD2—1015nsDelayTime,CSbRisetoSDIOTri-StateTD3—1015nsSetupTime,CSbtoSCLKTSU15——nsHoldTime,CSbtoSCLKFallTH15——nsSetupTime,SDItoSCLKRiseTSU25——nsHoldTime,SDItoSCLKRiseTH25——nsDelayTimeBetweenChipSelects(CSb)TCS2——TCSCLKCSbSDIOTSU1TD1TSU2TD2TCTCSTD3TH2TH1Figure5.
3.
3-WireSPISerialInterfaceTimingSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
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Rev.
1.
2|36Table5.
12.
CrystalSpecificationsParameterSymbolTestConditionMinTypMaxUnitCrystalFrequencyRangefXTALFulloperatingrange.
Jit-terperformancemaybereduced.
24.
97—54.
06MHzRangeforbestjitter.
48—54MHzLoadCapacitanceCL—8—pFCrystalDriveLeveldL——200WEquivalentSeriesResistanceShuntCapacitancerESRCORefertotheSi5345-44-42FamilyReferenceManualtodetermineESRandshuntcapacitance.
Note:1.
RefertotheSi534x/8xJitterAttenuatorsRecommendedCrystal,TCXOandOCXOsReferenceManualforrecommended48to54MHzcrystals.
TheSi5345/44/42aredesignedtoworkwithcrystalsthatmeetthesespecifications.
Table5.
13.
ThermalCharacteristicsParameterSymbolTestCondition1ValueUnitSi5345-64QFNThermalResistanceJunctiontoAmbientθJAStillAir22°C/WAirFlow1m/s19.
4°C/WAirFlow2m/s18.
3°C/WThermalResistanceJunctiontoCaseθJC9.
5°C/WThermalResistanceJunctiontoBoardθJB9.
4°C/WΨJB9.
3°C/WThermalResistanceJunctiontoTopCenterΨJT0.
2°C/WSi5344,Si5342-44QFNThermalResistanceJunctiontoAmbientθJAStillAir22.
3°C/WAirFlow1m/s19.
4°C/WAirFlow2m/s18.
4°C/WThermalResistanceJunctiontoCaseθJC10.
9°C/WThermalResistanceJunctiontoBoardθJB9.
3°C/WΨJB9.
2°C/WThermalResistanceJunctiontoTopCenterΨJT0.
23°C/WSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|37ParameterSymbolTestCondition1ValueUnitNote:1.
BasedonPCBDimension:3"x4.
5"PCBThickness:1.
6mm,PCBLand/Via:36,NumberofCuLayers:4Table5.
14.
AbsoluteMaximumRatings1,2,3ParameterSymbolTestConditionValueUnitDCSupplyVoltageVDD–0.
5to3.
8VVDDA–0.
5to3.
8VVDDO–0.
5to3.
8VVDDS–0.
5to3.
8VInputVoltageRangeVI14IN0–IN3/FB_IN–1.
0to3.
8VVI2IN_SEL1,IN_SEL0,RSTb,OEb,I2C_SEL,FINC,FDEC,SDI,SCLK,A0/CSb,A1,SDA/SDIO–0.
5to3.
8VVI3XA/XB–0.
5to2.
7VLatch-upToleranceLUJESD78CompliantESDToleranceHBM100pF,1.
5kΩ2.
0kVStorageTemperatureRangeTSTG–55to150°CMaximumJunctionTemperatureinOperationTJCT125°CSolderingTemperature(Pb-freeprofile)5TPEAK260°CSolderingTemperatureTimeatTPEAK(Pb-freeprofile)5TP20–40sNote:1.
Permanentdevicedamagemayoccuriftheabsolutemaximumratingsareexceeded.
Functionaloperationshouldberestrictedtotheconditionsasspecifiedintheoperationalsectionsofthisdatasheet.
Exposuretoabsolutemaximumratingconditionsforex-tendedperiodsmayaffectdevicereliability.
2.
64-QFNand44-QFNpackagesareRoHS-6compliant.
3.
MoisturesensitivitylevelisMSL2.
Formorepackaginginformation,gototheSiliconLabsRoHSinformationpage.
4.
Theminimumvoltageatthesepinscanbeaslowas–1.
0Vwhenanacinputsignalof8kHzorgreaterisapplied.
SeeTable5.
3InputClockSpecificationsonpage26forsingle-endedac-coupledfIN<250MHz.
5.
ThedeviceiscompliantwithJEDECJ-STD-020.
Si5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|386.
TypicalApplicationSchematicCPU/NPUFPGA/ASIC/SWITCH1GPHY1GPHY10GPHY10GPHY125MHz(LVPECL)125MHz(LVPECL)100MHz(HCSL)133.
333MHz(CMOS)83.
333MHZ(CMOS)50MHz(CMOS)156.
25MHz(LVDS)156.
25MHz(LVDS)2.
048MHz19.
44MHz125MHz100MHz156.
525MHz(LVDS)155.
52MHz(LVDS)PCIe3.
0DSPLLSi5345MultiSynthMultiSynthMultiSynthMultiSynthMultiSynthFigure6.
1.
10GEthernetDataCenterSwitchandComputeBladeSchematicSi5348TelecomorEthernetBackplaneWanderFilteringHitlessSwitchingHoldover8kHz19.
44MHz25MHzABBITSALineRecoveredTimingBITSBLAN/WANSyncELineCardLineRecoveredClocks155.
52MHz156.
25MHz161.
1328125MHz10GbEPHYSi5345TxTimingPathRxTimingPath8kHz19.
44MHz25MHzJitterFilteringHitlessSwitchingFrequencyTranslation10GbEPHYABRedundantTimingCardsSONET/SDH/PDHLineCardLineRecoveredClocks77.
76/155.
52MHz1.
544/2.
048MHzOC-3/12Si5345TxTimingPathRxTimingPath8kHz19.
44MHz25MHzJitterFilteringHitlessSwitchingFrequencyTranslationABT1/E1Si5348TCXO/OCXOFigure6.
2.
SyncELineCardSi5345/44/42RevDDataSheetTypicalApplicationSchematicsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|397.
DetailedBlockDiagramsSi5345IN_SEL[1:0]DSPLLLPFPDOptionalExternalFeedbackVDDVDDA3OUT2bVDDO2OUT2VDDO3VDDO0OUT0bOUT0÷R2OUT3bOUT3÷R3OUT1bVDDO1OUT1÷R1OUT5bVDDO5OUT5VDDO6÷R5OUT6bOUT6÷R6OUT4bVDDO4OUT4÷R4OUT7bVDDO7OUT7VDDO8÷R7OUT8bOUT8÷R8÷R0StatusMonitorsINTRbMultiSynth÷N0nN0dMultiSynthMultiSynthMultiSynth÷N2nN2d÷N3nN3d÷N4nN4dMultiSynth÷N1nN1dIN0IN0bIN1IN1b÷P0nP0d÷P1nP1dIN2IN2bIN3/FB_ININ3/FB_INb÷P3nP3d÷P2nP2dOUT9bOUT9÷R9VDDO9RSTbOEbFDECFINC÷MnMdSDA/SDIOA1/SDOSCLKA0/CSbI2C_SELSPI/I2CNVMLOLb48-54MHzXTALorREFCLKOSCXBXA÷PREFFigure7.
1.
Si5345BlockDiagramSi5345/44/42RevDDataSheetDetailedBlockDiagramssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|40Si5344IN_SEL[1:0]DSPLLLPFPDOptionalExternalFeedbackIN0IN0bIN1IN1b÷P0nP0d÷P1nP1dIN2IN2bIN3/FB_ININ3/FB_INb÷P3nP3d÷P2nP2dRSTbOEbVDDVDDA42OUT2bVDDO2OUT2VDDO3VDDO0OUT0bOUT0÷R2OUT3bOUT3÷R3OUT1bVDDO1OUT1÷R1÷R0MultiSynth÷N0nN0dMultiSynthMultiSynth÷N2nN2d÷N3nN3dMultiSynth÷N1nN1dSDA/SDIOA1/SDOSCLKA0/CSbI2C_SELSPI/I2CNVM÷MnMdStatusMonitorsLOS_XAXBbVDDSLOLbINTRb48-54MHzXTALorREFCLKOSCXBXA÷PREFFigure7.
2.
Si5344BlockDiagramSi5345/44/42RevDDataSheetDetailedBlockDiagramssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|41Si5342IN_SEL[1:0]DSPLLLPFPDOptionalExternalFeedbackIN0IN0bIN1IN1b÷P0nP0d÷P1nP1dIN2IN2bIN3/FB_ININ3/FB_INb÷P3nP3d÷P2nP2dRSTbOEbVDDVDDA42VDDO0OUT0bOUT0OUT1bVDDO1OUT1÷R1÷R0MultiSynth÷N0nN0dMultiSynth÷N1nN1d÷MnMdStatusMonitorsLOS0bLOS1bLOS2bLOS_XAXBbSDA/SDIOA1/SDOSCLKA0/CSbI2C_SELSPI/I2CNVMLOS3bVDDSLOLbINTRb348-54MHzXTALorREFCLKOSCXBXA÷PREFFigure7.
3.
Si5342BlockDiagramSi5345/44/42RevDDataSheetDetailedBlockDiagramssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|428.
TypicalOperatingCharacteristicsThephasenoiseplotsbelowweretakenunderthefollowingconditions:VDD=1.
8V;VDDA=3.
3V;VDDS=3.
3V,1.
8V;TA=25°C.
Figure8.
1.
Input=25MHz;Output=625MHz,2.
5VLVDSSi5345/44/42RevDDataSheetTypicalOperatingCharacteristicssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|43Figure8.
2.
Input=25MHz;Output=156.
25MHz,2.
5VLVDSFigure8.
3.
Input=25MHz;Output=155.
52MHz,2.
5VLVDSSi5345/44/42RevDDataSheetTypicalOperatingCharacteristicssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|449.
PinDescriptionsGNDPadIN1IN1bIN_SEL0IN_SEL1RSVDRSTbX1XAXBX2OEbINTRbVDDAIN2IN2bSCLKFINCLOLbVDDOUT6OUT6bVDDO6OUT5OUT5bVDDO5I2C_SELOUT4OUT4bVDDO4OUT3OUT3bVDDO3VDDO7OUT7bOUT7VDDO8OUT8bOUT8OUT9bOUT9VDDO9VDDIN3/FB_ININ3b/FB_INbIN0IN0bSi5345TopView12345678910111213141516484746454443424140393837363534331718192021222324252627282930313264636261605958575655545352515049A0/CSbSDA/SDIOVDDRSVDRSVDVDDO0OUT0bOUT0VDDO1OUT1bOUT1FDECVDDO2OUT2bOUT2A1/SDORSVDRSVDGNDPadIN1IN1bIN_SEL0INTRbX1XAXBX2OEbRSTbVDDAVDDAIN2A0/CSbSDA/SDIOA1/SDOOUT0bOUT0VDDO0I2C_SELOUT1OUT1bVDDO1VDDO3OUT3bOUT3IN3/FB_ININ3b/FB_INbIN0IN0bSi534444QFNTopView12345678910333231302928272625241213141516171819202144434241403938373635VDDOUT2OUT2bVDDO2VDDSLOLbLOS_XAXBbVDDIN_SEL1IN2b1123NC22VDDVDD34SCLKGNDPadIN1IN1bIN_SEL0INTRbX1XAXBX2OEbRSTbVDDAVDDAIN2A0/CSbSDA/SDIOA1/SDOOUT0bOUT0VDDO0I2C_SELOUT1OUT1bVDDO1VDDSLOS2bLOS3bIN3/FB_ININ3b/FB_INbIN0IN0bSi534244QFNTopView12345678910333231302928272625241213141516171819202144434241403938373635VDDLOS1bLOS0bVDDSVDDSLOLbLOS_XAXBbVDDIN_SEL1IN2b1123NC22VDDVDD34SCLKSi5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|45Table9.
1.
Si5345/44/42PinDescriptionsPinNamePinNumberPinType1FunctionSi5345Si5344Si5342InputsXA855ICrystalInput.
Inputpinsforexternalcrystal(XTAL).
Alternativelythesepinscanbedrivenwithanexternalreferenceclock(REFCLK).
AninternalregisterbitselectsXTALorREFCLKmode.
DefaultisXTALmode.
XB966IX1744IXTALShield.
ConnectthesepinsdirectlytotheXTALgroundpins.
X1,X2andtheXTALgroundpinsshouldbeseparatedfromthePCBgroundplane.
RefertotheSi5345/44/42RevDFamilyReferenceManualforlayoutguidelines.
ThesepinsshouldbeleftdisconnectedwhenconnectingXA/XBpinstoanexternalrefer-enceclock(REFCLK).
X21077IIN0634343IClockInputs.
Thesepinsacceptaninputclockforsynchronizingthedevice.
Theysupportbothdifferentialandsingle-endedclocksignals.
Referto3.
7.
6InputConfigurationandTerminationsforinputterminationoptions.
Thesepinsarehigh-impedanceandmustbeterminatedexternally.
Thenegativesideofthedifferen-tialinputmustbegroundedthroughacapacitorwhenacceptingasingle-endedclock.
IN0b644444IIN1111IIN1b222IIN2141010IIN2b151111IIN3/FB_IN614141IClockInput3/ExternalFeedbackInput.
Bydefaultthesepinsareusedasthefourthclockinput(IN3/IN3b).
Theycanalsobeusedastheexternalfeedbackinput(FB_IN/FB_INb)fortheop-tionalzerodelaymode.
See3.
9.
12ZeroDelayModefordetailsontheoptionalzerodelaymode.
IN3b/FB_INb624242ISi5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|46Table9.
2.
Si5345/44/42PinDescriptionsPinNamePinNumberPinType1FunctionSi5345Si5344Si5342OutputsOUT0242020OOutputClocks.
Theseoutputclockssupportaprogrammablesignalswingandcommonmodevoltage.
Desiredoutputsignalformatisconfigurableusingregistercontrol.
Terminationrecom-mendationsareprovidedin3.
9.
3DifferentialOutputTerminationsand3.
9.
4LVCMOSOutputTerminations.
Unusedoutputsshouldbeleftunconnected.
OUT0b231919OOUT1282525OOUT1b272424OOUT23131—OOUT2b3030—OOUT33536—OOUT3b3435—OOUT438——OOUT4b37——OOUT542——OOUT5b41——OOUT645——OOUT6b44——OOUT751——OOUT7b50——OOUT854——OOUT8b53——OOUT959——OOUT9b58——OSerialInterfaceI2C_SEL393838II2CSelect2.
ThispinselectstheserialinterfacemodeasI2C(I2C_SEL=1)orSPI(I2C_SEL=0).
Thispinisinternallypulledupbya~20kΩresistortothevoltageselectedbytheIO_VDD_SELregisterbit.
SDA/SDIO181313I/OSerialDataInterface2Thisisthebidirectionaldatapin(SDA)fortheI2Cmode,orthebidirectionaldatapin(SDIO)inthe3-wireSPImode,ortheinputdatapin(SDI)in4-wireSPImode.
WheninI2Cmode,thispinmustbepulled-upusinganexternalresistorofatleast1kΩ.
Nopull-upresistorisneededwhenisSPImode.
Tielowwhenun-used.
Si5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|47PinNamePinNumberPinType1FunctionSi5345Si5344Si5342A1/SDO171515I/OAddressSelect1/SerialDataOutput2InI2Cmode,thispinfunctionsastheA1addressinputpinanddoesnothaveaninternalpull-uporpull-downresistor.
In4-wireSPImodethisistheserialdataoutput(SDO)pinanddriveshightothevoltageselectedbytheIO_VDD_SELbit.
Leavediscon-nectedwhenunused.
SCLK161414ISerialClockInput2ThispinfunctionsastheserialclockinputforbothI2CandSPImodes.
WheninI2Cmode,thispinmustbepulled-upusinganexternalresistorofatleast1kΩ.
Nopull-upresistorisneededwheninSPImode.
Tiehighorlowwhenunused.
A0/CSb191616IAddressSelect0/ChipSelect2ThispinfunctionsasthehardwarecontrolledaddressA0inI2Cmode.
InSPImode,thispinfunctionsasthechipselectinput(ac-tivelow).
Thispinisinternallypulled-upbya~20kΩresistorandcanbeleftunconnectedwhennotinuse.
Control/StatusINTRb123333OInterrupt2Thispinisassertedlowwhenachangeindevicestatushasoc-curred.
Itshouldbeleftunconnectedwhennotinuse.
RSTb61717IDeviceReset2Activelowinputthatperformspower-onreset(POR)ofthede-vice.
Resetsallinternallogictoaknownstateandforcesthede-viceregisterstotheirdefaultvalues.
Clockoutputsaredisabledduringreset.
Thispinisinternallypulled-upandcanbeleftun-connectedwhennotinuse.
OEb111212IOutputEnable2Thispindisablesalloutputswhenheldhigh.
Thispinisinternallypulledlowandcanbeleftunconnectedwhennotinuse.
LOLb47——OLossOfLock(Si5345)2ThisoutputpinindicateswhentheDSPLLislocked(high)orout-of-lock(low).
Itcanbeleftunconnectedwhennotinuse.
—2727OLossOfLock(Si5344/42)3ThisoutputpinindicateswhentheDSPLLislocked(high)orout-of-lock(low).
Itcanbeleftunconnectedwhennotinuse.
LOS0b——30OLossOfSignalforIN03ThispinindicatealossofclockattheIN0pinwhenlow.
LOS1b——31OLossOfSignalforIN13ThispinindicatealossofclockattheIN1pinwhenlow.
LOS2b——35OLossOfSignalforIN23ThispinindicatealossofclockattheIN2pinwhenlow.
Si5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|48PinNamePinNumberPinType1FunctionSi5345Si5344Si5342LOS3b——36OLossOfSignalforIN33ThispinindicatealossofclockattheIN3pinwhenlow.
LOS_XAXBb—2828OLossOfSignalonXA/XBPins3ThispinindicatesalossofsignalattheXA/XBpinswhenlow.
FINC48——IFrequencyIncrementPin2Thispinisusedtostep-uptheoutputfrequencyofaselectedout-put.
Theaffectedoutputanditsfrequencychangestepsizeisregisterconfigurable.
Thispinisinternallypulledlowandcanbeleftunconnectedwhennotinuse.
FDEC25——IFrequencyDecrementPin2Thispinisusedtostep-downtheoutputfrequencyofaselectedoutput.
Theaffectedoutputdriveranditsfrequencychangestepsizeisregisterconfigurable.
Thispinisinternallypulledlowandcanbeleftunconnectedwhennotinuse.
IN_SEL0333IInputReferenceSelect2TheIN_SEL[1:0]pinsareusedinmanualpincontrolledmodetoselecttheactiveclockinputasshowninTable3.
1ManualInputSelectionUsingIN_SEL[1:0]Pinsonpage10.
Thesepinsarein-ternallypulledlow.
IN_SEL143737IRSVD5———ReservedThesepinsareconnectedtothedie.
Leavedisconnected.
20———21———55———56———NC—2222NoConnectThesepinsarenotconnectedtothedie.
Leavedisconnected.
PowerVDD322121PCoreSupplyVoltageThedeviceoperatesfroma1.
8Vsupply.
A1.
0Fbypasscapac-itorshouldbeplacedveryclosetothispin.
SeetheSi5345/44/42RevDFamilyReferenceManualforpowersupplyfilteringrecom-mendations.
463232P603939P—4040PVDDA1388PCoreSupplyVoltage3.
3VThiscoresupplypinrequiresa3.
3Vpowersource.
A1Fby-passcapacitorshouldbeplacedveryclosetothispin.
SeetheSi5345/44/42RevDFamilyReferenceManualforpowersupplyfilteringrecommendations.
—99PVDDS—2626PStatusOutputVoltageThevoltageonthispindeterminesVOL/VOHontheSi5342/44LOL_AandLOL_Boutputs.
Connecttoeither3.
3Vor1.
8V.
A1.
0Fbypasscapacitorshouldbeplacedveryclosetothispin.
——29P——34PSi5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|49PinNamePinNumberPinType1FunctionSi5345Si5344Si5342VDDO0221818POutputClockSupplyVoltageSupplyvoltage(3.
3V,2.
5V,1.
8V)forOUTn,OUTnoutputs.
Forunusedoutputs,leaveVDDOpinsunconnected.
AnalternativeoptionistoconnecttheVDDOpintoapowersupplyanddisabletheoutputdrivertominimizecurrentconsumption.
VDDO1262323PVDDO22929—PVDDO33334—PVDDO436——PVDDO540——PVDDO643——PVDDO749——PVDDO852——PVDDO957——PGNDPAD———PGroundPadThispadprovidesconnectiontogroundandmustbeconnectedforproperoperation.
Useasmanyviasaspractical,andkeepthevialengthtoaninternalgroundplaneasshortaspossible.
Note:1.
I=Input,O=Output,P=Power.
2.
TheIO_VDD_SELcontrolbit(0x0943bit0)selects3.
3Vor1.
8Voperation.
3.
ThevoltageontheVDDSpin(s)determines3.
3Vor1.
8Voperation.
4.
RefertotheSi5345/44/42RevDFamilyReferenceManualformoreinformationonregistersettingnames.
5.
AllstatuspinsexceptI2CandSPIarepush-pull.
Si5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5010.
PackageOutlines10.
1Si53459x9mm64-QFNPackageDiagramThefollowingfigureillustratesthepackagedetailsfortheSi5345.
Thetableliststhevaluesforthedimensionsshownintheillustration.
Figure10.
1.
64-PinQuadFlatNo-Lead(QFN)Table10.
1.
PackageDimensionsDimensionMinNomMaxA0.
800.
850.
90A10.
000.
020.
05b0.
180.
250.
30D9.
00BSCD25.
105.
205.
30e0.
50BSCE9.
00BSCE25.
105.
205.
30L0.
300.
400.
50aaa——0.
10bbb——0.
10ccc——0.
08ddd——0.
10Note:1.
Alldimensionsshownareinmillimeters(mm)unlessotherwisenoted.
2.
DimensioningandTolerancingperANSIY14.
5M-1994.
3.
ThisdrawingconformstotheJEDECSolidStateOutlineMO-220.
4.
RecommendedcardreflowprofileispertheJEDEC/IPCJ-STD-020specificationforSmallBodyComponents.
Si5345/44/42RevDDataSheetPackageOutlinessilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5110.
2Si5344andSi53427x7mm44-QFNPackageDiagramThefollowingfigureillustratesthepackagedetailsfortheSi5344andSi5342.
Thetableliststhevaluesforthedimensionsshownintheillustration.
Figure10.
2.
44-PinQuadFlatNo-Lead(QFN)Table10.
2.
PackageDimensionsDimensionMinNomMaxA0.
800.
850.
90A10.
000.
020.
05b0.
180.
250.
30D7.
00BSCD25.
105.
205.
30e0.
50BSCE7.
00BSCE25.
105.
205.
30L0.
300.
400.
50aaa——0.
10bbb——0.
10ccc——0.
08ddd——0.
10Note:1.
Alldimensionsshownareinmillimeters(mm)unlessotherwisenoted.
2.
DimensioningandTolerancingperANSIY14.
5M-1994.
3.
ThisdrawingconformstotheJEDECSolidStateOutlineMO-220.
4.
RecommendedcardreflowprofileispertheJEDEC/IPCJ-STD-020specificationforSmallBodyComponents.
Si5345/44/42RevDDataSheetPackageOutlinessilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5211.
PCBLandPatternThefollowingfigureillustratesthePCBlandpatterndetailsforthedevices.
Thetableliststhevaluesforthedimensionsshownintheillustration.
Si5345Si5344andSi5342Figure11.
1.
PCBLandPatternSi5345/44/42RevDDataSheetPCBLandPatternsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|53Table11.
1.
PCBLandPatternDimensionsDimensionSi5345(Max)Si5344/42(Max)C18.
906.
90C28.
906.
90E0.
500.
50X10.
300.
30Y10.
850.
85X25.
305.
30Y25.
305.
30Notes:General1.
Alldimensionsshownareinmillimeters(mm)unlessotherwisenoted.
2.
ThisLandPatternDesignisbasedontheIPC-7351guidelines.
3.
AlldimensionsshownareatMaximumMaterialCondition(MMC).
LeastMaterialConditioniscalculatedbasedonafabricationAllowanceof0.
05mm.
SolderMaskDesign1.
Allmetalpadsaretobenon-soldermaskdefined(NSMD).
Clearancebetweenthesoldermaskandthemetalpadistobe60mminimum,allthewayaroundthepad.
StencilDesign1.
Astainlesssteel,laser-cutandelectropolishedstencilwithtrapezoidalwallsshouldbeusedtoassuregoodsolderpasterelease.
2.
Thestencilthicknessshouldbe0.
125mm(5mils).
3.
Theratioofstencilaperturetolandpadsizeshouldbe1:1forallperimeterpads.
4.
A3x3arrayof1.
25mmsquareopeningson1.
80mmpitchshouldbeusedforthecentergroundpad.
CardAssembly1.
ANo-Clean,Type-3solderpasteisrecommended.
2.
TherecommendedcardreflowprofileispertheJEDEC/IPCJ-STD-020specificationforSmallBodyComponents.
Si5345/44/42RevDDataSheetPCBLandPatternsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5412.
TopMarkingFigure12.
1.
Si5345/44/42TopMarkingTable12.
1.
TopMarkingExplanationLineCharactersDescription1Si534fg-BasepartnumberandDeviceGradeforAny-frequency,Any-output,JitterCleaningClock(singlePLL):f=5:10-outputSi5345:64-QFNf=4:4-outputSi5344:44-QFNf=2:2-outputSi5342:44-QFNg=DeviceGrade(A,B,C,D).
See2.
OrderingGuideformoreinformation.
–=Dashcharacter.
2Rxxxxx-GMR=Productrevision.
(Referto2.
OrderingGuideforlatestrevision).
xxxxx=CustomerspecificNVMsequencenumber.
OptionalNVMcodeas-signedforcustom,factorypre-programmeddevices.
Charactersarenotincludedforstandard,factorydefaultconfigureddevices.
See2.
OrderingGuideformoreinformation.
-GM=Package(QFN)andtemperaturerange(–40to+85°C)3YYWWTTTTTTYYWW=Characterscorrespondtotheyear(YY)andworkweek(WW)ofpackageassembly.
TTTTTT=Manufacturingtracecode.
4Circlew/1.
6mm(64-QFN)or1.
4mm(44-QFN)diameterPin1indicator;left-justifiede4TWPb-freesymbol;Center-JustifiedTW=Taiwan;CountryofOrigin(ISOAbbreviation)Si5345/44/42RevDDataSheetTopMarkingsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5513.
DeviceErrataLoginorregisteratwww.
silabs.
comtoaccessthedeviceerratadocument.
Si5345/44/42RevDDataSheetDeviceErratasilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5614.
RevisionHistoryRevision1.
2September,2018UpdatedFigure3.
3CrystalResonatorandExternalReferenceClockConnectionOptionsonpage10.
UpdatedFigure3.
4TerminationofDifferentialandLVCMOSInputSignalsonpage12.
UpdatedFigure3.
13SupportedDifferentialOutputTerminationsonpage18.
RemovedOutputSkewControlsection.
UpdatedTable5.
2DCCharacteristicsonpage25UpdatedNote5andLVCMOSOutputTestConfigurationcircuit.
UpdatedTable5.
3InputClockSpecificationsonpage26.
UpdatedTable5.
4ControlInputPinSpecificationsonpage27.
UpdatedInputCapacitancespecification.
UpdatedTable5.
5DifferentialClockOutputSpecificationsonpage28.
UpdatedTable5.
6LVCMOSClockOutputSpecificationsonpage30.
UpdatedLVCMOSOutputTestConfigurationunderNote3.
UpdatedTable5.
8PerformanceCharacteristicsonpage32.
Changed"Input-to-OutputDelay"specificationto"Zero-DelayModeInput-to-OutputDelay".
UpdatedTable5.
12CrystalSpecificationsonpage37.
UpdatedTable5.
14AbsoluteMaximumRatings1,2,3onpage38.
Revision1.
1August,2017RefertoAN1006foralistofchangesfromRevBtoRevD.
Updatedblockdiagramonthefrontpage.
Minorchangestothefollowingtables:Table5.
3InputClockSpecificationsonpage26Table5.
8PerformanceCharacteristicsonpage32Table5.
12CrystalSpecificationsonpage37Table5.
14AbsoluteMaximumRatings1,2,3onpage38Revision1.
0July,2016Initialrelease.
Si5345/44/42RevDDataSheetRevisionHistorysilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|57
Thesedevicesareprogrammableviaaserialinterfacewithin-circuitprogrammablenon-volatilememory(NVM)sotheyalwayspowerupwithaknownfrequencyconfiguration.
Theysupportfree-run,synchronous,andholdovermodesofoperation,andofferbothau-tomaticandmanualinputclockswitching.
Theloopfilterisfullyintegratedon-chip,eliminatingtheriskofnoisecouplingassociatedwithdiscretesolutions.
Furthermore,thejitterattenuationbandwidthisdigitallyprogrammable,providingjitterperform-anceoptimizationattheapplicationlevel.
ProgrammingtheSi5345/44/42iseasywithSiliconLabs'ClockBuilderProsoftware.
Factorypreprogrammeddevicesarealsoavailable.
Applications:OTNmuxpondersandtransponders10/40/100GnetworkinglinecardsGbE/10GbE/100GbESynchronousEthernet(ITU-TG.
8262)CarrierEthernetswitchesSONET/SDHlinecardsBroadcastvideoTestandmeasurementITU-TG.
8262(SyncE)compliantKEYFEATURESGeneratesanycombinationofoutputfrequenciesfromanyinputfrequencyUltra-lowjitterof90fsrmsExternalCrystal:25to54MHzInputfrequencyrangeDifferential:8kHzto750MHzLVCMOS:8kHzto250MHzOutputfrequencyrangeDifferential:100Hzto1028MHzLVCMOS:100Hzto250MHzMeetsG.
8262EECOption1,2(SyncE)HighlyconfigurableoutputscompatiblewithLVDS,LVPECL,LVCMOS,CML,andHCSLwithprogrammablesignalamplitudeSi5345:4input,10output,64-QFN9*9mmSi5344:4input,4output,44-QFN7*7mmSi5342:4input,2output,44-QFN7*7mmUpto10OutputClocksSi5344Si5345I2C/SPIControlNVMStatusFlagsStatusMonitorXBXA25-54MHzXTALOSCMultiSynthMultiSynthMultiSynthMultiSynthMultiSynthDSPLLSi53424InputClocksIN0IN1IN2IN3/FB_INOUT7OUT6OUT5OUT1OUT4OUT3OUT2OUT0÷INT÷INT÷INT÷INT÷INT÷INT÷INT÷INTOUT9OUT8÷INT÷INT÷FRAC÷FRAC÷FRAC÷FRACsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
21.
FeaturesListTheSi5345/44/42RevDfeaturesarelistedbelow:Generatesanycombinationofoutputfrequenciesfromanyin-putfrequencyUltra-lowjitterof90fsrmsInputfrequencyrangeDifferential:8kHz–750MHzLVCMOS:8kHz–250MHzOutputfrequencyrangeDifferential:100Hzto1028MHzLVCMOS:100Hzto250MHzProgrammablejitterattenuationbandwidth:0.
1Hzto4kHzMeetsG.
8262EECOption1,2(SyncE)HighlyconfigurableoutputscompatiblewithLVDS,LVPECL,LVCMOS,CML,andHCSLwithprogrammablesignalampli-tudeStatusmonitoring(LOS,OOF,LOL)Hitlessinputclockswitching:automaticormanualLockstogappedclockinputsFree-runandholdovermodesOptionalzerodelaymodeFastlockfeatureforlownominalbandwidthsGlitchlessontheflyoutputfrequencychangesDCOmode:aslowas0.
001ppbstepsizeCorevoltageVDD:1.
8V±5%VDDA:3.
3V±5%Independentoutputclocksupplypins3.
3V,2.
5V,or1.
8VSerialinterface:I2CorSPIIn-circuitprogrammablewithnon-volatileOTPmemoryClockBuilderProsoftwaresimplifiesdeviceconfigurationSi5345:4input,10output,64-QFN9*9mmSi5344:4input,4output,44-QFN7*7mmSi5342:4input,2output,44-QFN7*7mmTemperaturerange:–40to+85°CPb-free,RoHS-6compliantSi5345/44/42RevDDataSheetFeaturesListsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|22.
OrderingGuideOrderingPartNumber(OPN)NumberofInput/OutputClocksOutputClockFrequencyRange(MHz)SupportedFrequencySynthesisModesPackageTemperatureRangeSi5345Si5345A-D-GM1,24/100.
001to1028MHzIntegerandFractional64-QFN9*9mm–40to85°CSi5345B-D-GM1,20.
001to350MHzSi5345C-D-GM1,20.
001to1028MHzIntegerOnlySi5345D-D-GM1,20.
001to350MHzSi5344Si5344A-D-GM1,24/40.
001to1028MHzIntegerandFractional44-QFN7*7mm–40to85°CSi5344B-D-GM1,20.
001to350MHzSi5344C-D-GM1,20.
001to1028MHzIntegerOnlySi5344D-D-GM1,20.
001to350MHzSi5342Si5342A-D-GM1,24/20.
001to1028MHzIntegerandFractional44-QFN7*7mm–40to85°CSi5342B-D-GM1,20.
001to350MHzSi5342C-D-GM1,20.
001to1028MHzIntegerOnlySi5342D-D-GM1,20.
001to350MHzSi5345/44/42-D-EVBSi5345-D-EVB———EvaluationBoard—Si5344-D-EVBSi5342-D-EVBNotes:1.
AddanRattheendoftheOPNtodenotetapeandreelorderingoptions.
2.
Custom,factorypreprogrammeddevicesareavailable.
OrderingpartnumbersareassignedbySiliconLabsandtheClockBuilderProsoftware.
Custompartnumberformatis"Si5345A-Dxxxxx-GM"where"xxxxx"isauniquenumericalsequencerepresentingthepreprogrammedconfiguration.
Si5345/44/42RevDDataSheetOrderingGuidesilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|3Figure2.
1.
OrderingPartNumberFieldsSi5345/44/42RevDDataSheetOrderingGuidesilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|4TableofContents1.
FeaturesList22.
OrderingGuide33.
FunctionalDescription.
73.
1FrequencyConfiguration73.
2DSPLLLoopBandwidth73.
3FastlockFeature73.
4ModesofOperation73.
4.
1InitializationandReset83.
4.
2FreerunMode83.
4.
3LockAcquisitionMode83.
4.
4LockedMode83.
4.
5HoldoverMode93.
5ExternalReference(XA/XB)93.
6DigitallyControlledOscillator(DCO)Mode103.
7Inputs(IN0,IN1,IN2,IN3)103.
7.
1ManualInputSwitching(IN0,IN1,IN2,IN3)103.
7.
2AutomaticInputSelection(IN0,IN1,IN2,IN3)113.
7.
3HitlessInputSwitching113.
7.
4RampedInputSwitching113.
7.
5GlitchlessInputSwitching113.
7.
6InputConfigurationandTerminations123.
7.
7SynchronizingtoGappedInputClocks133.
8FaultMonitoring133.
8.
1InputLOSDetection.
143.
8.
2XA/XBLOSDetection143.
8.
3OOFDetection143.
8.
4LOLDetection.
153.
8.
5InterruptPin(INTRb)163.
9Outputs163.
9.
1OutputCrosspoint173.
9.
2OutputSignalFormat173.
9.
3DifferentialOutputTerminations.
183.
9.
4LVCMOSOutputTerminations183.
9.
5ProgrammableCommonModeVoltageForDifferentialOutputs183.
9.
6LVCMOSOutputImpedanceSelection193.
9.
7LVCMOSOutputSignalSwing193.
9.
8LVCMOSOutputPolarity193.
9.
9OutputEnable/Disable193.
9.
10OutputDriverStateWhenDisabled193.
9.
11SynchronousOutputDisableFeature193.
9.
12ZeroDelayMode203.
9.
13OutputDivider(R)Synchronization20silabs.
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1.
2|53.
10PowerManagement.
203.
11In-CircuitProgramming.
203.
12SerialInterface213.
13CustomFactoryPreprogrammedParts213.
14EnablingFeaturesand/orConfigurationSettingsUnavailableinClockBuilderProforFactoryPreprogrammedDevices214.
RegisterMap235.
ElectricalSpecifications246.
TypicalApplicationSchematic397.
DetailedBlockDiagrams408.
TypicalOperatingCharacteristics439.
PinDescriptions4510.
PackageOutlines5110.
1Si53459x9mm64-QFNPackageDiagram5110.
2Si5344andSi53427x7mm44-QFNPackageDiagram.
5211.
PCBLandPattern5312.
TopMarking5513.
DeviceErrata5614.
RevisionHistory.
57silabs.
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Rev.
1.
2|63.
FunctionalDescriptionTheSi5345'sinternalDSPLLprovidesjitterattenuationandany-frequencymultiplicationoftheselectedinputfrequency.
Fractionalin-putdividers(P)allowtheDSPLLtoperformhitlessswitchingbetweeninputclocks(INx)thatarefractionallyrelated.
Inputswitchingiscontrolledmanuallyorautomaticallyusinganinternalstatemachine.
Theoscillatorcircuit(OSC)providesafrequencyreferencewhichdeterminesoutputfrequencystabilityandaccuracywhilethedeviceisinfree-runorholdovermode.
Thehigh-performanceMultiSynthdividers(N)generateintegerorfractionallyrelatedoutputfrequenciesfortheoutputstage.
AcrosspointswitchconnectsanyoftheMultiSynthgeneratedfrequenciestoanyoftheoutputs.
Additionalintegerdivision(R)determinesthefinaloutputfrequency.
3.
1FrequencyConfigurationThefrequencyconfigurationoftheDSPLLisprogrammablethroughtheserialinterfaceandcanalsobestoredinnon-volatilememory.
Thecombinationoffractionalinputdividers(Pn/Pd),fractionalfrequencymultiplication(Mn/Md),fractionaloutputMultiSynthdivision(Nn/Nd),andintegeroutputdivision(Rn)allowsthegenerationofvirtuallyanyoutputfrequencyonanyoftheoutputs.
AlldividervaluesforaspecificfrequencyplanareeasilydeterminedusingtheClockBuilderProsoftware.
3.
2DSPLLLoopBandwidthTheDSPLLloopbandwidthdeterminestheamountofinputclockjitterattenuation.
RegisterconfigurableDSPLLloopbandwidthset-tingsintherangeof0.
1Hzto4kHzareavailableforselection.
Sincetheloopbandwidthiscontrolleddigitally,theDSPLLwillalwaysremainstablewithlessthan0.
1dBofpeakingregardlessoftheloopbandwidthselection.
3.
3FastlockFeatureSelectingalowDSPLLloopbandwidth(e.
g.
0.
1Hz)willgenerallylengthenthelockacquisitiontime.
ThefastlockfeatureallowssettingatemporaryFastlockLoopBandwidththatisusedduringthelockacquisitionprocess.
Higherfastlockloopbandwidthsettingswillena-bletheDSPLLstolockfaster.
FastlockLoopBandwidthsettingsofintherangeof100Hzto4kHzareavailableforselection.
TheDSPLLwillreverttoitsnormalloopbandwidthoncelockacquisitionhascompleted.
3.
4ModesofOperationOnceinitializationiscompletetheDSPLLoperatesinoneoffourmodes:Free-runMode,LockAcquisitionMode,LockedMode,orHoldoverMode.
AstatediagramshowingthemodesofoperationisshowninFigure3.
1ModesofOperationonpage8.
Thefollow-ingsectionsdescribeeachofthesemodesingreaterdetail.
Si5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|73.
4.
1InitializationandResetOncepowerisapplied,thedevicebeginsaninitializationperiodwhereitdownloadsdefaultregistervaluesandconfigurationdatafromNVMandperformsotherinitializationtasks.
Communicatingwiththedevicethroughtheserialinterfaceispossibleoncethisinitializa-tionperiodiscomplete.
Noclockswillbegenerateduntiltheinitializationiscomplete.
Therearetwotypesofresetsavailable.
Ahardresetisfunctionallysimilartoadevicepower-up.
AllregisterswillberestoredtothevaluesstoredinNVM,andallcircuitsincludingtheserialinterfacewillberestoredtotheirinitialstate.
AhardresetisinitiatedusingtheRSTbpinorbyassertingthehardresetregisterbit.
AsoftresetbypassestheNVMdownload.
Itissimplyusedtoinitiateregisterconfigurationchanges.
NovalidinputclocksselectedLockAcquisition(FastLock)LockedModeHoldoverModePhaselockonselectedinputclockisachievedAninputisqualifiedandavailableforselectionNovalidinputclocksavailableforselectionFree-runValidinputclockselectedResetandInitializationPower-UpSelectedinputclockfailsYesNoHoldoverHistoryValidOtherValidClockInputsAvailableNoYesInputClockSwitchFigure3.
1.
ModesofOperation3.
4.
2FreerunModeTheDSPLLwillautomaticallyenterfreerunmodeoncepowerisappliedtothedeviceandinitializationiscomplete.
Thefrequencyac-curacyofthegeneratedoutputclocksinfreerunmodeisentirelydependentonthefrequencyaccuracyoftheexternalcrystalorrefer-enceclockontheXA/XBpins.
Forexample,ifthecrystalfrequencyis±100ppm,thenalltheoutputclockswillbegeneratedattheirconfiguredfrequency±100ppminfreerunmode.
Anydriftofthecrystalfrequencywillbetrackedattheoutputclockfrequencies.
ATCXOorOCXOisrecommendedforapplicationsthatneedbetterfrequencyaccuracyandstabilitywhileinfreerunorholdovermodes.
3.
4.
3LockAcquisitionModeThedevicemonitorsallinputsforavalidclock.
Ifatleastonevalidclockisavailableforsynchronization,theDSPLLwillautomaticallystartthelockacquisitionprocess.
Ifthefastlockfeatureisenabled,theDSPLLwillacquirelockusingtheFastlockLoopBandwidthsettingandthentransitiontotheDSPLLLoopBandwidthsettingwhenlockacquisitioniscomplete.
DuringlockacquisitiontheoutputswillgenerateaclockthatfollowstheVCOfrequencychangeasitpullsintotheinputclockfrequency.
3.
4.
4LockedModeOncelocked,theDSPLLwillgenerateoutputclocksthatarebothfrequencyandphaselockedtotheirselectedinputclocks.
Atthispoint,anyXTALfrequencydriftwillnotaffecttheoutputfrequency.
Alossoflockpin(LOL)andstatusbitindicatewhenlockisach-ieved.
See3.
8.
4LOLDetectionformoredetailsontheoperationoftheloss-of-lockcircuit.
Si5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|83.
4.
5HoldoverModeTheDSPLLwillautomaticallyenterholdovermodewhentheselectedinputclockbecomesinvalidandnoothervalidinputclocksareavailableforselection.
TheDSPLLusesanaveragedinputclockfrequencyasitsfinalholdoverfrequencytominimizethedisturbanceoftheoutputclockphaseandfrequencywhenaninputclocksuddenlyfails.
TheholdovercircuitfortheDSPLLstoresupto120sec-ondsofhistoricalfrequencydatawhilelockedtoavalidclockinput.
Thefinalaveragedholdoverfrequencyvalueiscalculatedfromaprogrammablewindowwithinthestoredhistoricalfrequencydata.
Boththewindowsizeandthedelayareprogrammableasshowninthefigurebelow.
Thewindowsizedeterminestheamountofholdoverfrequencyaveraging.
Thedelayvalueallowsignoringfrequencydatathatmaybecorruptjustbeforetheinputclockfailure.
ProgrammabledelayClockFailureandEntryintoHoldovertime0HistoricalFrequencyDataCollectedProgrammablehistoricaldatawindowusedtodeterminethefinalholdovervalue120secondsFigure3.
2.
ProgrammableHoldoverWindowWhenenteringholdover,theDSPLLwillpullitsoutputclockfrequencytothecalculatedaveragedholdoverfrequency.
Whileinhold-over,theoutputfrequencydriftisentirelydependentontheexternalcrystalorexternalreferenceclockconnectedtotheXA/XBpins.
Iftheclockinputbecomesvalid,theDSPLLwillautomaticallyexittheholdovermodeandre-acquirelocktothenewinputclock.
Thisprocessinvolvespullingtheoutputclockfrequencytoachievefrequencyandphaselockwiththeinputclock.
Thispull-inprocessisglitchlessanditsrateiscontrolledbytheDSPLLortheFastlockbandwidth.
TheDSPLLoutputfrequencywhenexitingholdovercanberamped(recommend).
Justbeforetheexitisinitiated,thedifferencebe-tweenthecurrentholdoverfrequencyandthenewdesiredfrequencyismeasured.
Usingthecalculateddifferenceandauser-selecta-bleramprate,theoutputislinearlyrampedtothenewfrequency.
Therampratecanbe0.
2ppm/s,40,000ppm/s,oranyofabout40valuesinbetween.
TheDSPLLloopBWdoesnotlimitoraffectramprateselections(andviceversa).
CBProdefaultstorampedexitfromholdover.
Thesamerampratesettingsareusedforbothexitfromholdoverandrampedinputswitching.
Formoreinformationonrampedinputswitching,see3.
7.
4RampedInputSwitching.
Note:Iframpedholdoverexitisnotselected,theholdoverexitisgovernedeitherby(1)theDSPLLloopBWor(2)auser-selectableholdoverexitBW.
3.
5ExternalReference(XA/XB)Anexternalcrystal(XTAL)isusedincombinationwiththeinternaloscillator(OSC)toproduceanultralowjitterreferenceclockfortheDSPLLandforprovidingastablereferenceforthefree-runandholdovermodes.
AsimplifieddiagramisshowninFigure3.
3CrystalResonatorandExternalReferenceClockConnectionOptionsonpage10.
ThedeviceincludesinternalXTALloadingcapacitorswhicheliminatestheneedforexternalcapacitorsandalsohasthebenefitofreducednoisecouplingfromexternalsources.
RefertoTable5.
12CrystalSpecificationsonpage37forcrystalspecifications.
Acrystalintherangeof48MHzto54MHzisrecommendedforbestjitterperformance.
TheSi5345/44/42RevDFamilyReferenceManualprovidesadditionalinformationonPCBlayoutrecom-mendationsforthecrystaltoensureoptimumjitterperformance.
ToachieveoptimaljitterperformanceandminimizeBOMcost,acrystalisrecommendedontheXA/XBreferenceinput.
ForSyncEpizzaboxapplications(e.
g.
loopbandwidthsetto0.
1Hz),aTCXOisrequiredontheXA/XBreferencetominimizewanderandtopro-videastableholdoverreference.
SeetheSi5345/44/42RevDFamilyReferenceManualformoreinformation.
SelectionbetweentheexternalXTALorREFCLKiscontrolledbyregisterconfiguration.
Theinternalcrystalloadingcapacitors(CL)aredisabledintheREFCLKmode.
RefertoTable5.
3InputClockSpecificationsonpage26forREFCLKrequirementswhenusingthismode.
APREFdividerisavailabletoaccommodateexternalclockfrequencieshigherthan54MHz.
Frequenciesintherangeof48MHzto54MHzwillachievethebestoutputjitterperformance.
Si5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|93.
6DigitallyControlledOscillator(DCO)ModeTheoutputMultiSynthssupportaDCOmodewheretheiroutputfrequenciesareadjustableinpredefinedstepsdefinedbyfrequencystepwords(FSW).
Thefrequencyadjustmentsarecontrolledthroughtheserialinterfaceorbypincontrolusingfrequencyincrement(FINC)ordecrement(FDEC).
AFINCwilladdthefrequencystepwordtotheDSPLLoutputfrequency,whileaFDECwilldecrementit.
AnynumberofMultiSynthscanbeupdatedatonceorindependentlycontrolled.
TheDCOmodeisavailablewhentheDSPLLisoperat-ingineitherfree-runorlockedmode.
DifferentialXO/ClockConnection2xCL2xCLXBXAOSC÷PREF25-54MHzXO/ClockLVCMOSXO/ClockConnection2xCL2xCLXBXAOSC÷PREFR2R1C125-54MHzXO/ClockLVCMOSCrystalResonatorConnection2xCL2xCLXBXAOSC÷PREF25-54MHzXTALX1X2X1X2NCNCX1X2NCNCNote:SeePinDescriptionsforX1/X2connectionsC1isrecommendedtoincreasetheslewrateatXaSeetheReferenceManualfortherecommendedR1,R2,C1valuesFigure3.
3.
CrystalResonatorandExternalReferenceClockConnectionOptionsNote:SeeTable5.
3InputClockSpecificationsonpage26.
3.
7Inputs(IN0,IN1,IN2,IN3)TherearefourinputsthatcanbeusedtosynchronizetheDSPLL.
Theinputsacceptbothdifferentialandsingle-endedclocks.
Inputselectioncanbemanual(pinorregistercontrolled)orautomaticwithuserdefinablepriorities.
3.
7.
1ManualInputSwitching(IN0,IN1,IN2,IN3)InputclockselectioncanbemademanuallyusingtheIN_SEL[1:0]pinsorthrougharegister.
Aregisterbitdeterminesinputselectionaspinselectableorregisterselectable.
TheIN_SELpinsareselectedbydefault.
Ifthereisnoclocksignalontheselectedinput,thedevicewillautomaticallyenterfree-runorholdovermode.
Whenthezerodelaymodeisenabled,IN3becomesthefeedbackinput(FB_IN)andisnotavailableforselectionasaclockinput.
Table3.
1.
ManualInputSelectionUsingIN_SEL[1:0]PinsIN_SEL[1:0]SelectedInputZeroDelayModeDisabledZeroDelayModeEnabled00IN0IN001IN1IN110IN2IN211IN3ReservedSi5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|103.
7.
2AutomaticInputSelection(IN0,IN1,IN2,IN3)Anautomaticinputselectionstatemachineisavailableinadditiontothemanualswitchingoption.
Inautomaticmode,theselectioncriteriaisbasedoninputclockqualification,inputpriority,andtherevertiveoption.
Onlyinputclocksthatarevalidcanbeselectedbytheautomaticclockselectionstatemachine.
IftherearenovalidinputclocksavailabletheDSPLLwillentertheholdovermode.
Withrevertiveswitchingenabled,thehighestpriorityinputwithavalidinputclockisalwaysselected.
Ifaninputwithahigherprioritybe-comesvalidthenanautomaticswitchovertothatinputwillbeinitiated.
Withnon-revertiveswitching,theactiveinputwillalwaysremainselectedwhileitisvalid.
Ifitbecomesinvalidanautomaticswitchovertoavalidinputwiththehighestprioritywillbeinitiated.
3.
7.
3HitlessInputSwitchingHitlessswitchingisafeaturethatpreventsaphaseoffsetfrompropagatingtotheoutputwhenswitchingbetweentwoclockinputsthathaveafixedphaserelationship.
Ahitlessswitchcanonlyoccurwhenthetwoinputfrequenciesarefrequencylockedmeaningthattheyhavetobeexactlyatthesamefrequency,oratafractionalfrequencyrelationshiptoeachother.
Whenhitlessswitchingisenabled,theDSPLLsimplyabsorbsthephasedifferencebetweenthetwoinputclocksduringainputswitch.
Whendisabled,thephasedifferencebetweenthetwoinputsispropagatedtotheoutputataratedeterminedbytheDSPLLLoopBandwidth.
Thehitlessswitchingfeaturesupportsclockfrequenciesdowntotheminimuminputfrequencyof8kHz.
3.
7.
4RampedInputSwitchingWhenswitchingbetweentwoplesiochronousinputclocks(i.
e.
,thefrequenciesare"almostthesame"butnotquite),rampedinputswitchingshouldbeenabledtoensureasmoothtransitionbetweenthetwoinputs.
RampedinputswitchingavoidsfrequencytransientsandovershootwhenswitchingbetweenfrequenciesandsoisthedefaultswitchingmodeinCBPro.
Thefeatureshouldbeturnedoffwhenswitchingbetweeninputclocksthatarealwaysfrequencylocked(i.
e.
,arealwaysthesameexactfrequency).
Thesamerampratesettingsareusedforbothholdoverexitandclockswitching.
Formoreinformationonrampedexitfromholdoversee3.
4.
5HoldoverMode.
3.
7.
5GlitchlessInputSwitchingTheDSPLLhastheabilityofswitchingbetweentwoinputclockfrequenciesthatareupto±500ppmapart.
TheDSPLLwillpull-intothenewfrequencyusingtheDSPLLLoopBandwidthorusingtheFastlockLoopBandwidthifenabled.
Thelossoflock(LOL)indicatorwillassertwhiletheDSPLLispulling-intothenewclockfrequency.
Therewillbenoabruptphasechangeattheoutputduringthetransi-tion.
Si5345/44/42RevDDataSheetFunctionalDescriptionsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|113.
7.
6InputConfigurationandTerminationsEachoftheinputscanbeconfiguredasdifferentialorsingle-endedLVCMOS.
TherecommendedinputterminationschemesareshowninFigure14.
Differentialsignalsmustbeac-coupled,whilesingle-endedLVCMOSsignalscanbeac-ordc-coupled.
Unusedinputscanbedisabledandleftunconnectedwhennotinuse.
3.
3V,2.
5V,1.
8VLVCMOSINx50StandardAC-CoupledDifferential(IN0-IN3)INx50PulsedCMOSStandard50R1PulsedCMOSStandardSeetheReferenceManualfordetailsonR1andR2values.
RSmatchestheCMOSdrivertoa50ohmtransmissionline(ifused)StandardAC-CoupledSingle-Ended(IN0-IN3)PulsedCMOSDC-CoupledSingleEndedonlyforFrequencies1MHz,consultyourCBProdesignreportfortheFpfdfrequencyofyourcon-figuration.
6.
Delayisdependentonfrequencyconfiguration.
UsingFpfd<64kHzwillresultinhigherdelayvalues.
Si5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|32Table5.
9.
I2CTimingSpecifications(SCL,SDA)ParameterSymbolTestConditionStandardMode100kbpsFastMode400kbpsUnitMinMaxMinMaxSCLClockFrequencyfSCL—100—400kHzSMBusTimeout—WhenTimeoutisEnabled25352535msHoldtime(Repeated)STARTconditiontHD:STA4.
0—0.
6—sLowPeriodoftheSCLClocktLOW4.
7—1.
3—sHIGHPeriodoftheSCLClocktHIGH4.
0—0.
6—sSetupTimeforaRepeatedSTARTConditiontSU:STA4.
7—0.
6—sDataHoldTimetHD:DAT100—100—nsDataSetupTimetSU:DAT250—100—nsRiseTimeofbothSDAandSCLSignalstr—100020300nsFallTimeofbothSDAandSCLSignalstf—300—300nsSetupTimeforSTOPCondi-tiontSU:STO4.
0—0.
6—sBusFreeTimebetweenaSTOPandSTARTConditiontBUF4.
7—1.
3—sDataValidTimetVD:DAT—3.
45—0.
9sDataValidAcknowledgeTimetVD:ACK—3.
45—0.
9sSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|33Figure5.
1.
I2CSerialPortTimingStandardandFastModesSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|34Table5.
10.
SPITimingSpecifications(4-Wire)VDD=1.
8V±5%,VDDA=3.
3V±5%,TA=–40to85°CParameterSymbolMinTypMaxUnitSCLKFrequencyfSPI——20MHzSCLKDutyCycleTDC40—60%SCLKPeriodTC50——nsDelayTime,SCLKFalltoSDOActiveTD1—12.
518nsDelayTime,SCLKFalltoSDOTD2—1015nsDelayTime,CSbRisetoSDOTri-StateTD3—1015nsSetupTime,CSbtoSCLKTSU15——nsHoldTime,SCLKFalltoCSbTH15——nsSetupTime,SDItoSCLKRiseTSU25——nsHoldTime,SDItoSCLKRiseTH25——nsDelayTimeBetweenChipSelects(CSb)TCS2——TCSCLKCSbSDISDOTSU1TD1TSU2TD2TCTCSTD3TH2TH1Figure5.
2.
4-WireSPISerialInterfaceTimingSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|35Table5.
11.
SPITimingSpecifications(3-Wire)VDD=1.
8V±5%,VDDA=3.
3V±5%,TA=–40to85°CParameterSymbolMinTypMaxUnitSCLKFrequencyfSPI——20MHzSCLKDutyCycleTDC40—60%SCLKPeriodTC50——nsDelayTime,SCLKFalltoSDIOTurn-onTD1—12.
520nsDelayTime,SCLKFalltoSDIONext-bitTD2—1015nsDelayTime,CSbRisetoSDIOTri-StateTD3—1015nsSetupTime,CSbtoSCLKTSU15——nsHoldTime,CSbtoSCLKFallTH15——nsSetupTime,SDItoSCLKRiseTSU25——nsHoldTime,SDItoSCLKRiseTH25——nsDelayTimeBetweenChipSelects(CSb)TCS2——TCSCLKCSbSDIOTSU1TD1TSU2TD2TCTCSTD3TH2TH1Figure5.
3.
3-WireSPISerialInterfaceTimingSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|36Table5.
12.
CrystalSpecificationsParameterSymbolTestConditionMinTypMaxUnitCrystalFrequencyRangefXTALFulloperatingrange.
Jit-terperformancemaybereduced.
24.
97—54.
06MHzRangeforbestjitter.
48—54MHzLoadCapacitanceCL—8—pFCrystalDriveLeveldL——200WEquivalentSeriesResistanceShuntCapacitancerESRCORefertotheSi5345-44-42FamilyReferenceManualtodetermineESRandshuntcapacitance.
Note:1.
RefertotheSi534x/8xJitterAttenuatorsRecommendedCrystal,TCXOandOCXOsReferenceManualforrecommended48to54MHzcrystals.
TheSi5345/44/42aredesignedtoworkwithcrystalsthatmeetthesespecifications.
Table5.
13.
ThermalCharacteristicsParameterSymbolTestCondition1ValueUnitSi5345-64QFNThermalResistanceJunctiontoAmbientθJAStillAir22°C/WAirFlow1m/s19.
4°C/WAirFlow2m/s18.
3°C/WThermalResistanceJunctiontoCaseθJC9.
5°C/WThermalResistanceJunctiontoBoardθJB9.
4°C/WΨJB9.
3°C/WThermalResistanceJunctiontoTopCenterΨJT0.
2°C/WSi5344,Si5342-44QFNThermalResistanceJunctiontoAmbientθJAStillAir22.
3°C/WAirFlow1m/s19.
4°C/WAirFlow2m/s18.
4°C/WThermalResistanceJunctiontoCaseθJC10.
9°C/WThermalResistanceJunctiontoBoardθJB9.
3°C/WΨJB9.
2°C/WThermalResistanceJunctiontoTopCenterΨJT0.
23°C/WSi5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|37ParameterSymbolTestCondition1ValueUnitNote:1.
BasedonPCBDimension:3"x4.
5"PCBThickness:1.
6mm,PCBLand/Via:36,NumberofCuLayers:4Table5.
14.
AbsoluteMaximumRatings1,2,3ParameterSymbolTestConditionValueUnitDCSupplyVoltageVDD–0.
5to3.
8VVDDA–0.
5to3.
8VVDDO–0.
5to3.
8VVDDS–0.
5to3.
8VInputVoltageRangeVI14IN0–IN3/FB_IN–1.
0to3.
8VVI2IN_SEL1,IN_SEL0,RSTb,OEb,I2C_SEL,FINC,FDEC,SDI,SCLK,A0/CSb,A1,SDA/SDIO–0.
5to3.
8VVI3XA/XB–0.
5to2.
7VLatch-upToleranceLUJESD78CompliantESDToleranceHBM100pF,1.
5kΩ2.
0kVStorageTemperatureRangeTSTG–55to150°CMaximumJunctionTemperatureinOperationTJCT125°CSolderingTemperature(Pb-freeprofile)5TPEAK260°CSolderingTemperatureTimeatTPEAK(Pb-freeprofile)5TP20–40sNote:1.
Permanentdevicedamagemayoccuriftheabsolutemaximumratingsareexceeded.
Functionaloperationshouldberestrictedtotheconditionsasspecifiedintheoperationalsectionsofthisdatasheet.
Exposuretoabsolutemaximumratingconditionsforex-tendedperiodsmayaffectdevicereliability.
2.
64-QFNand44-QFNpackagesareRoHS-6compliant.
3.
MoisturesensitivitylevelisMSL2.
Formorepackaginginformation,gototheSiliconLabsRoHSinformationpage.
4.
Theminimumvoltageatthesepinscanbeaslowas–1.
0Vwhenanacinputsignalof8kHzorgreaterisapplied.
SeeTable5.
3InputClockSpecificationsonpage26forsingle-endedac-coupledfIN<250MHz.
5.
ThedeviceiscompliantwithJEDECJ-STD-020.
Si5345/44/42RevDDataSheetElectricalSpecificationssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|386.
TypicalApplicationSchematicCPU/NPUFPGA/ASIC/SWITCH1GPHY1GPHY10GPHY10GPHY125MHz(LVPECL)125MHz(LVPECL)100MHz(HCSL)133.
333MHz(CMOS)83.
333MHZ(CMOS)50MHz(CMOS)156.
25MHz(LVDS)156.
25MHz(LVDS)2.
048MHz19.
44MHz125MHz100MHz156.
525MHz(LVDS)155.
52MHz(LVDS)PCIe3.
0DSPLLSi5345MultiSynthMultiSynthMultiSynthMultiSynthMultiSynthFigure6.
1.
10GEthernetDataCenterSwitchandComputeBladeSchematicSi5348TelecomorEthernetBackplaneWanderFilteringHitlessSwitchingHoldover8kHz19.
44MHz25MHzABBITSALineRecoveredTimingBITSBLAN/WANSyncELineCardLineRecoveredClocks155.
52MHz156.
25MHz161.
1328125MHz10GbEPHYSi5345TxTimingPathRxTimingPath8kHz19.
44MHz25MHzJitterFilteringHitlessSwitchingFrequencyTranslation10GbEPHYABRedundantTimingCardsSONET/SDH/PDHLineCardLineRecoveredClocks77.
76/155.
52MHz1.
544/2.
048MHzOC-3/12Si5345TxTimingPathRxTimingPath8kHz19.
44MHz25MHzJitterFilteringHitlessSwitchingFrequencyTranslationABT1/E1Si5348TCXO/OCXOFigure6.
2.
SyncELineCardSi5345/44/42RevDDataSheetTypicalApplicationSchematicsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|397.
DetailedBlockDiagramsSi5345IN_SEL[1:0]DSPLLLPFPDOptionalExternalFeedbackVDDVDDA3OUT2bVDDO2OUT2VDDO3VDDO0OUT0bOUT0÷R2OUT3bOUT3÷R3OUT1bVDDO1OUT1÷R1OUT5bVDDO5OUT5VDDO6÷R5OUT6bOUT6÷R6OUT4bVDDO4OUT4÷R4OUT7bVDDO7OUT7VDDO8÷R7OUT8bOUT8÷R8÷R0StatusMonitorsINTRbMultiSynth÷N0nN0dMultiSynthMultiSynthMultiSynth÷N2nN2d÷N3nN3d÷N4nN4dMultiSynth÷N1nN1dIN0IN0bIN1IN1b÷P0nP0d÷P1nP1dIN2IN2bIN3/FB_ININ3/FB_INb÷P3nP3d÷P2nP2dOUT9bOUT9÷R9VDDO9RSTbOEbFDECFINC÷MnMdSDA/SDIOA1/SDOSCLKA0/CSbI2C_SELSPI/I2CNVMLOLb48-54MHzXTALorREFCLKOSCXBXA÷PREFFigure7.
1.
Si5345BlockDiagramSi5345/44/42RevDDataSheetDetailedBlockDiagramssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|40Si5344IN_SEL[1:0]DSPLLLPFPDOptionalExternalFeedbackIN0IN0bIN1IN1b÷P0nP0d÷P1nP1dIN2IN2bIN3/FB_ININ3/FB_INb÷P3nP3d÷P2nP2dRSTbOEbVDDVDDA42OUT2bVDDO2OUT2VDDO3VDDO0OUT0bOUT0÷R2OUT3bOUT3÷R3OUT1bVDDO1OUT1÷R1÷R0MultiSynth÷N0nN0dMultiSynthMultiSynth÷N2nN2d÷N3nN3dMultiSynth÷N1nN1dSDA/SDIOA1/SDOSCLKA0/CSbI2C_SELSPI/I2CNVM÷MnMdStatusMonitorsLOS_XAXBbVDDSLOLbINTRb48-54MHzXTALorREFCLKOSCXBXA÷PREFFigure7.
2.
Si5344BlockDiagramSi5345/44/42RevDDataSheetDetailedBlockDiagramssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|41Si5342IN_SEL[1:0]DSPLLLPFPDOptionalExternalFeedbackIN0IN0bIN1IN1b÷P0nP0d÷P1nP1dIN2IN2bIN3/FB_ININ3/FB_INb÷P3nP3d÷P2nP2dRSTbOEbVDDVDDA42VDDO0OUT0bOUT0OUT1bVDDO1OUT1÷R1÷R0MultiSynth÷N0nN0dMultiSynth÷N1nN1d÷MnMdStatusMonitorsLOS0bLOS1bLOS2bLOS_XAXBbSDA/SDIOA1/SDOSCLKA0/CSbI2C_SELSPI/I2CNVMLOS3bVDDSLOLbINTRb348-54MHzXTALorREFCLKOSCXBXA÷PREFFigure7.
3.
Si5342BlockDiagramSi5345/44/42RevDDataSheetDetailedBlockDiagramssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|428.
TypicalOperatingCharacteristicsThephasenoiseplotsbelowweretakenunderthefollowingconditions:VDD=1.
8V;VDDA=3.
3V;VDDS=3.
3V,1.
8V;TA=25°C.
Figure8.
1.
Input=25MHz;Output=625MHz,2.
5VLVDSSi5345/44/42RevDDataSheetTypicalOperatingCharacteristicssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|43Figure8.
2.
Input=25MHz;Output=156.
25MHz,2.
5VLVDSFigure8.
3.
Input=25MHz;Output=155.
52MHz,2.
5VLVDSSi5345/44/42RevDDataSheetTypicalOperatingCharacteristicssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|449.
PinDescriptionsGNDPadIN1IN1bIN_SEL0IN_SEL1RSVDRSTbX1XAXBX2OEbINTRbVDDAIN2IN2bSCLKFINCLOLbVDDOUT6OUT6bVDDO6OUT5OUT5bVDDO5I2C_SELOUT4OUT4bVDDO4OUT3OUT3bVDDO3VDDO7OUT7bOUT7VDDO8OUT8bOUT8OUT9bOUT9VDDO9VDDIN3/FB_ININ3b/FB_INbIN0IN0bSi5345TopView12345678910111213141516484746454443424140393837363534331718192021222324252627282930313264636261605958575655545352515049A0/CSbSDA/SDIOVDDRSVDRSVDVDDO0OUT0bOUT0VDDO1OUT1bOUT1FDECVDDO2OUT2bOUT2A1/SDORSVDRSVDGNDPadIN1IN1bIN_SEL0INTRbX1XAXBX2OEbRSTbVDDAVDDAIN2A0/CSbSDA/SDIOA1/SDOOUT0bOUT0VDDO0I2C_SELOUT1OUT1bVDDO1VDDO3OUT3bOUT3IN3/FB_ININ3b/FB_INbIN0IN0bSi534444QFNTopView12345678910333231302928272625241213141516171819202144434241403938373635VDDOUT2OUT2bVDDO2VDDSLOLbLOS_XAXBbVDDIN_SEL1IN2b1123NC22VDDVDD34SCLKGNDPadIN1IN1bIN_SEL0INTRbX1XAXBX2OEbRSTbVDDAVDDAIN2A0/CSbSDA/SDIOA1/SDOOUT0bOUT0VDDO0I2C_SELOUT1OUT1bVDDO1VDDSLOS2bLOS3bIN3/FB_ININ3b/FB_INbIN0IN0bSi534244QFNTopView12345678910333231302928272625241213141516171819202144434241403938373635VDDLOS1bLOS0bVDDSVDDSLOLbLOS_XAXBbVDDIN_SEL1IN2b1123NC22VDDVDD34SCLKSi5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|45Table9.
1.
Si5345/44/42PinDescriptionsPinNamePinNumberPinType1FunctionSi5345Si5344Si5342InputsXA855ICrystalInput.
Inputpinsforexternalcrystal(XTAL).
Alternativelythesepinscanbedrivenwithanexternalreferenceclock(REFCLK).
AninternalregisterbitselectsXTALorREFCLKmode.
DefaultisXTALmode.
XB966IX1744IXTALShield.
ConnectthesepinsdirectlytotheXTALgroundpins.
X1,X2andtheXTALgroundpinsshouldbeseparatedfromthePCBgroundplane.
RefertotheSi5345/44/42RevDFamilyReferenceManualforlayoutguidelines.
ThesepinsshouldbeleftdisconnectedwhenconnectingXA/XBpinstoanexternalrefer-enceclock(REFCLK).
X21077IIN0634343IClockInputs.
Thesepinsacceptaninputclockforsynchronizingthedevice.
Theysupportbothdifferentialandsingle-endedclocksignals.
Referto3.
7.
6InputConfigurationandTerminationsforinputterminationoptions.
Thesepinsarehigh-impedanceandmustbeterminatedexternally.
Thenegativesideofthedifferen-tialinputmustbegroundedthroughacapacitorwhenacceptingasingle-endedclock.
IN0b644444IIN1111IIN1b222IIN2141010IIN2b151111IIN3/FB_IN614141IClockInput3/ExternalFeedbackInput.
Bydefaultthesepinsareusedasthefourthclockinput(IN3/IN3b).
Theycanalsobeusedastheexternalfeedbackinput(FB_IN/FB_INb)fortheop-tionalzerodelaymode.
See3.
9.
12ZeroDelayModefordetailsontheoptionalzerodelaymode.
IN3b/FB_INb624242ISi5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|46Table9.
2.
Si5345/44/42PinDescriptionsPinNamePinNumberPinType1FunctionSi5345Si5344Si5342OutputsOUT0242020OOutputClocks.
Theseoutputclockssupportaprogrammablesignalswingandcommonmodevoltage.
Desiredoutputsignalformatisconfigurableusingregistercontrol.
Terminationrecom-mendationsareprovidedin3.
9.
3DifferentialOutputTerminationsand3.
9.
4LVCMOSOutputTerminations.
Unusedoutputsshouldbeleftunconnected.
OUT0b231919OOUT1282525OOUT1b272424OOUT23131—OOUT2b3030—OOUT33536—OOUT3b3435—OOUT438——OOUT4b37——OOUT542——OOUT5b41——OOUT645——OOUT6b44——OOUT751——OOUT7b50——OOUT854——OOUT8b53——OOUT959——OOUT9b58——OSerialInterfaceI2C_SEL393838II2CSelect2.
ThispinselectstheserialinterfacemodeasI2C(I2C_SEL=1)orSPI(I2C_SEL=0).
Thispinisinternallypulledupbya~20kΩresistortothevoltageselectedbytheIO_VDD_SELregisterbit.
SDA/SDIO181313I/OSerialDataInterface2Thisisthebidirectionaldatapin(SDA)fortheI2Cmode,orthebidirectionaldatapin(SDIO)inthe3-wireSPImode,ortheinputdatapin(SDI)in4-wireSPImode.
WheninI2Cmode,thispinmustbepulled-upusinganexternalresistorofatleast1kΩ.
Nopull-upresistorisneededwhenisSPImode.
Tielowwhenun-used.
Si5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|47PinNamePinNumberPinType1FunctionSi5345Si5344Si5342A1/SDO171515I/OAddressSelect1/SerialDataOutput2InI2Cmode,thispinfunctionsastheA1addressinputpinanddoesnothaveaninternalpull-uporpull-downresistor.
In4-wireSPImodethisistheserialdataoutput(SDO)pinanddriveshightothevoltageselectedbytheIO_VDD_SELbit.
Leavediscon-nectedwhenunused.
SCLK161414ISerialClockInput2ThispinfunctionsastheserialclockinputforbothI2CandSPImodes.
WheninI2Cmode,thispinmustbepulled-upusinganexternalresistorofatleast1kΩ.
Nopull-upresistorisneededwheninSPImode.
Tiehighorlowwhenunused.
A0/CSb191616IAddressSelect0/ChipSelect2ThispinfunctionsasthehardwarecontrolledaddressA0inI2Cmode.
InSPImode,thispinfunctionsasthechipselectinput(ac-tivelow).
Thispinisinternallypulled-upbya~20kΩresistorandcanbeleftunconnectedwhennotinuse.
Control/StatusINTRb123333OInterrupt2Thispinisassertedlowwhenachangeindevicestatushasoc-curred.
Itshouldbeleftunconnectedwhennotinuse.
RSTb61717IDeviceReset2Activelowinputthatperformspower-onreset(POR)ofthede-vice.
Resetsallinternallogictoaknownstateandforcesthede-viceregisterstotheirdefaultvalues.
Clockoutputsaredisabledduringreset.
Thispinisinternallypulled-upandcanbeleftun-connectedwhennotinuse.
OEb111212IOutputEnable2Thispindisablesalloutputswhenheldhigh.
Thispinisinternallypulledlowandcanbeleftunconnectedwhennotinuse.
LOLb47——OLossOfLock(Si5345)2ThisoutputpinindicateswhentheDSPLLislocked(high)orout-of-lock(low).
Itcanbeleftunconnectedwhennotinuse.
—2727OLossOfLock(Si5344/42)3ThisoutputpinindicateswhentheDSPLLislocked(high)orout-of-lock(low).
Itcanbeleftunconnectedwhennotinuse.
LOS0b——30OLossOfSignalforIN03ThispinindicatealossofclockattheIN0pinwhenlow.
LOS1b——31OLossOfSignalforIN13ThispinindicatealossofclockattheIN1pinwhenlow.
LOS2b——35OLossOfSignalforIN23ThispinindicatealossofclockattheIN2pinwhenlow.
Si5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|48PinNamePinNumberPinType1FunctionSi5345Si5344Si5342LOS3b——36OLossOfSignalforIN33ThispinindicatealossofclockattheIN3pinwhenlow.
LOS_XAXBb—2828OLossOfSignalonXA/XBPins3ThispinindicatesalossofsignalattheXA/XBpinswhenlow.
FINC48——IFrequencyIncrementPin2Thispinisusedtostep-uptheoutputfrequencyofaselectedout-put.
Theaffectedoutputanditsfrequencychangestepsizeisregisterconfigurable.
Thispinisinternallypulledlowandcanbeleftunconnectedwhennotinuse.
FDEC25——IFrequencyDecrementPin2Thispinisusedtostep-downtheoutputfrequencyofaselectedoutput.
Theaffectedoutputdriveranditsfrequencychangestepsizeisregisterconfigurable.
Thispinisinternallypulledlowandcanbeleftunconnectedwhennotinuse.
IN_SEL0333IInputReferenceSelect2TheIN_SEL[1:0]pinsareusedinmanualpincontrolledmodetoselecttheactiveclockinputasshowninTable3.
1ManualInputSelectionUsingIN_SEL[1:0]Pinsonpage10.
Thesepinsarein-ternallypulledlow.
IN_SEL143737IRSVD5———ReservedThesepinsareconnectedtothedie.
Leavedisconnected.
20———21———55———56———NC—2222NoConnectThesepinsarenotconnectedtothedie.
Leavedisconnected.
PowerVDD322121PCoreSupplyVoltageThedeviceoperatesfroma1.
8Vsupply.
A1.
0Fbypasscapac-itorshouldbeplacedveryclosetothispin.
SeetheSi5345/44/42RevDFamilyReferenceManualforpowersupplyfilteringrecom-mendations.
463232P603939P—4040PVDDA1388PCoreSupplyVoltage3.
3VThiscoresupplypinrequiresa3.
3Vpowersource.
A1Fby-passcapacitorshouldbeplacedveryclosetothispin.
SeetheSi5345/44/42RevDFamilyReferenceManualforpowersupplyfilteringrecommendations.
—99PVDDS—2626PStatusOutputVoltageThevoltageonthispindeterminesVOL/VOHontheSi5342/44LOL_AandLOL_Boutputs.
Connecttoeither3.
3Vor1.
8V.
A1.
0Fbypasscapacitorshouldbeplacedveryclosetothispin.
——29P——34PSi5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|49PinNamePinNumberPinType1FunctionSi5345Si5344Si5342VDDO0221818POutputClockSupplyVoltageSupplyvoltage(3.
3V,2.
5V,1.
8V)forOUTn,OUTnoutputs.
Forunusedoutputs,leaveVDDOpinsunconnected.
AnalternativeoptionistoconnecttheVDDOpintoapowersupplyanddisabletheoutputdrivertominimizecurrentconsumption.
VDDO1262323PVDDO22929—PVDDO33334—PVDDO436——PVDDO540——PVDDO643——PVDDO749——PVDDO852——PVDDO957——PGNDPAD———PGroundPadThispadprovidesconnectiontogroundandmustbeconnectedforproperoperation.
Useasmanyviasaspractical,andkeepthevialengthtoaninternalgroundplaneasshortaspossible.
Note:1.
I=Input,O=Output,P=Power.
2.
TheIO_VDD_SELcontrolbit(0x0943bit0)selects3.
3Vor1.
8Voperation.
3.
ThevoltageontheVDDSpin(s)determines3.
3Vor1.
8Voperation.
4.
RefertotheSi5345/44/42RevDFamilyReferenceManualformoreinformationonregistersettingnames.
5.
AllstatuspinsexceptI2CandSPIarepush-pull.
Si5345/44/42RevDDataSheetPinDescriptionssilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5010.
PackageOutlines10.
1Si53459x9mm64-QFNPackageDiagramThefollowingfigureillustratesthepackagedetailsfortheSi5345.
Thetableliststhevaluesforthedimensionsshownintheillustration.
Figure10.
1.
64-PinQuadFlatNo-Lead(QFN)Table10.
1.
PackageDimensionsDimensionMinNomMaxA0.
800.
850.
90A10.
000.
020.
05b0.
180.
250.
30D9.
00BSCD25.
105.
205.
30e0.
50BSCE9.
00BSCE25.
105.
205.
30L0.
300.
400.
50aaa——0.
10bbb——0.
10ccc——0.
08ddd——0.
10Note:1.
Alldimensionsshownareinmillimeters(mm)unlessotherwisenoted.
2.
DimensioningandTolerancingperANSIY14.
5M-1994.
3.
ThisdrawingconformstotheJEDECSolidStateOutlineMO-220.
4.
RecommendedcardreflowprofileispertheJEDEC/IPCJ-STD-020specificationforSmallBodyComponents.
Si5345/44/42RevDDataSheetPackageOutlinessilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5110.
2Si5344andSi53427x7mm44-QFNPackageDiagramThefollowingfigureillustratesthepackagedetailsfortheSi5344andSi5342.
Thetableliststhevaluesforthedimensionsshownintheillustration.
Figure10.
2.
44-PinQuadFlatNo-Lead(QFN)Table10.
2.
PackageDimensionsDimensionMinNomMaxA0.
800.
850.
90A10.
000.
020.
05b0.
180.
250.
30D7.
00BSCD25.
105.
205.
30e0.
50BSCE7.
00BSCE25.
105.
205.
30L0.
300.
400.
50aaa——0.
10bbb——0.
10ccc——0.
08ddd——0.
10Note:1.
Alldimensionsshownareinmillimeters(mm)unlessotherwisenoted.
2.
DimensioningandTolerancingperANSIY14.
5M-1994.
3.
ThisdrawingconformstotheJEDECSolidStateOutlineMO-220.
4.
RecommendedcardreflowprofileispertheJEDEC/IPCJ-STD-020specificationforSmallBodyComponents.
Si5345/44/42RevDDataSheetPackageOutlinessilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5211.
PCBLandPatternThefollowingfigureillustratesthePCBlandpatterndetailsforthedevices.
Thetableliststhevaluesforthedimensionsshownintheillustration.
Si5345Si5344andSi5342Figure11.
1.
PCBLandPatternSi5345/44/42RevDDataSheetPCBLandPatternsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|53Table11.
1.
PCBLandPatternDimensionsDimensionSi5345(Max)Si5344/42(Max)C18.
906.
90C28.
906.
90E0.
500.
50X10.
300.
30Y10.
850.
85X25.
305.
30Y25.
305.
30Notes:General1.
Alldimensionsshownareinmillimeters(mm)unlessotherwisenoted.
2.
ThisLandPatternDesignisbasedontheIPC-7351guidelines.
3.
AlldimensionsshownareatMaximumMaterialCondition(MMC).
LeastMaterialConditioniscalculatedbasedonafabricationAllowanceof0.
05mm.
SolderMaskDesign1.
Allmetalpadsaretobenon-soldermaskdefined(NSMD).
Clearancebetweenthesoldermaskandthemetalpadistobe60mminimum,allthewayaroundthepad.
StencilDesign1.
Astainlesssteel,laser-cutandelectropolishedstencilwithtrapezoidalwallsshouldbeusedtoassuregoodsolderpasterelease.
2.
Thestencilthicknessshouldbe0.
125mm(5mils).
3.
Theratioofstencilaperturetolandpadsizeshouldbe1:1forallperimeterpads.
4.
A3x3arrayof1.
25mmsquareopeningson1.
80mmpitchshouldbeusedforthecentergroundpad.
CardAssembly1.
ANo-Clean,Type-3solderpasteisrecommended.
2.
TherecommendedcardreflowprofileispertheJEDEC/IPCJ-STD-020specificationforSmallBodyComponents.
Si5345/44/42RevDDataSheetPCBLandPatternsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5412.
TopMarkingFigure12.
1.
Si5345/44/42TopMarkingTable12.
1.
TopMarkingExplanationLineCharactersDescription1Si534fg-BasepartnumberandDeviceGradeforAny-frequency,Any-output,JitterCleaningClock(singlePLL):f=5:10-outputSi5345:64-QFNf=4:4-outputSi5344:44-QFNf=2:2-outputSi5342:44-QFNg=DeviceGrade(A,B,C,D).
See2.
OrderingGuideformoreinformation.
–=Dashcharacter.
2Rxxxxx-GMR=Productrevision.
(Referto2.
OrderingGuideforlatestrevision).
xxxxx=CustomerspecificNVMsequencenumber.
OptionalNVMcodeas-signedforcustom,factorypre-programmeddevices.
Charactersarenotincludedforstandard,factorydefaultconfigureddevices.
See2.
OrderingGuideformoreinformation.
-GM=Package(QFN)andtemperaturerange(–40to+85°C)3YYWWTTTTTTYYWW=Characterscorrespondtotheyear(YY)andworkweek(WW)ofpackageassembly.
TTTTTT=Manufacturingtracecode.
4Circlew/1.
6mm(64-QFN)or1.
4mm(44-QFN)diameterPin1indicator;left-justifiede4TWPb-freesymbol;Center-JustifiedTW=Taiwan;CountryofOrigin(ISOAbbreviation)Si5345/44/42RevDDataSheetTopMarkingsilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5513.
DeviceErrataLoginorregisteratwww.
silabs.
comtoaccessthedeviceerratadocument.
Si5345/44/42RevDDataSheetDeviceErratasilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|5614.
RevisionHistoryRevision1.
2September,2018UpdatedFigure3.
3CrystalResonatorandExternalReferenceClockConnectionOptionsonpage10.
UpdatedFigure3.
4TerminationofDifferentialandLVCMOSInputSignalsonpage12.
UpdatedFigure3.
13SupportedDifferentialOutputTerminationsonpage18.
RemovedOutputSkewControlsection.
UpdatedTable5.
2DCCharacteristicsonpage25UpdatedNote5andLVCMOSOutputTestConfigurationcircuit.
UpdatedTable5.
3InputClockSpecificationsonpage26.
UpdatedTable5.
4ControlInputPinSpecificationsonpage27.
UpdatedInputCapacitancespecification.
UpdatedTable5.
5DifferentialClockOutputSpecificationsonpage28.
UpdatedTable5.
6LVCMOSClockOutputSpecificationsonpage30.
UpdatedLVCMOSOutputTestConfigurationunderNote3.
UpdatedTable5.
8PerformanceCharacteristicsonpage32.
Changed"Input-to-OutputDelay"specificationto"Zero-DelayModeInput-to-OutputDelay".
UpdatedTable5.
12CrystalSpecificationsonpage37.
UpdatedTable5.
14AbsoluteMaximumRatings1,2,3onpage38.
Revision1.
1August,2017RefertoAN1006foralistofchangesfromRevBtoRevD.
Updatedblockdiagramonthefrontpage.
Minorchangestothefollowingtables:Table5.
3InputClockSpecificationsonpage26Table5.
8PerformanceCharacteristicsonpage32Table5.
12CrystalSpecificationsonpage37Table5.
14AbsoluteMaximumRatings1,2,3onpage38Revision1.
0July,2016Initialrelease.
Si5345/44/42RevDDataSheetRevisionHistorysilabs.
com|Buildingamoreconnectedworld.
Rev.
1.
2|57
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