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SMSCCOM20020IRevDPage1Revision12-05-06DATASHEETCOM20020IRevD5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetProductFeaturesNewFeaturesforRev.
DDataRatesupto5MbpsProgrammableReconfigurationTimes28PinPLCCand48PinTQFPPackages;Lead-freeRoHSCompliantPackagesalsoAvailableIdealforIndustrial/Factory/BuildingAutomationandTransportationApplicationsDeterministic,(ANSI878.
1),TokenPassingARCNETProtocolMinimalMicrocontrollerandMediaInterfaceLogicRequiredFlexibleInterfaceForUseWithAllMicrocontrollersorMicroprocessorsAutomaticallyDetectsTypeofMicrocontrollerInterface2Kx8On-ChipDualPortRAMCommandChainingforPacketQueuingSequentialAccesstoInternalRAMSoftwareProgrammableNodeIDEight,256BytePagesAllowFourPagesTXandRXPlusScratch-PadMemoryNextIDReadableInternalClockScalerandClockMultiplierforAdjustingNetworkSpeedOperatingTemperatureRangeof-40oCto+85oCSelf-ReconfigurationProtocolSupportsupto255NodesSupportsVariousNetworkTopologies(Star,Tree,Bus.
.
.
)CMOS,Single+5VSupplyDuplicateNodeIDDetectionPowerfulDiagnosticsReceiveAllPacketsModeFlexibleMediaInterface:TraditionalHybridInterfaceForLongDistancesuptoFourMilesat2.
5MbpsRS485DifferentialDriverInterfaceForLowCost,LowPower,HighReliabilityORDERINGINFORMATIONOrderNumbers:COM20020ILJPfor28pinPLCCpackageCOM20020I-DZDfor28pinPLCClead-freeRoHScompliantpackageCOM20020I-HDfor48pinTQFPpackageCOM20020I-HTfor48pinTQFPlead-freeRoHScompliantpackage5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page2SMSCCOM20020IRevDDATASHEET80ArkayDriveHauppauge,NY11788(631)435-6000FAX(631)273-3123Copyright2006SMSCoritssubsidiaries.
Allrightsreserved.
CircuitdiagramsandotherinformationrelatingtoSMSCproductsareincludedasameansofillustratingtypicalapplications.
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ContactyourlocalSMSCsalesofficetoobtainthelatestspecificationsbeforeplacingyourproductorder.
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com.
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INNOEVENTSHALLSMSCBELIABLEFORANYDIRECT,INCIDENTAL,INDIRECT,SPECIAL,PUNITIVE,ORCONSEQUENTIALDAMAGES;ORFORLOSTDATA,PROFITS,SAVINGSORREVENUESOFANYKIND;REGARDLESSOFTHEFORMOFACTION,WHETHERBASEDONCONTRACT;TORT;NEGLIGENCEOFSMSCOROTHERS;STRICTLIABILITY;BREACHOFWARRANTY;OROTHERWISE;WHETHERORNOTANYREMEDYOFBUYERISHELDTOHAVEFAILEDOFITSESSENTIALPURPOSE,ANDWHETHERORNOTSMSCHASBEENADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage3Revision12-05-06DATASHEETTableofContentsChapter1GeneralDescription.
6Chapter2PinConfigurations.
7Chapter3DescriptionofPinFunctions9Chapter4ProtocolDescription124.
1NetworkProtocol.
124.
2DataRates124.
2.
1SelectingClockFrequenciesAbove2.
5Mbps.
124.
3NetworkReconfiguration.
134.
4BroadcastMessages.
144.
5ExtendedTimeoutFunction144.
5.
1ResponseTime.
144.
5.
2IdleTime144.
5.
3ReconfigurationTime.
144.
6LineProtocol144.
6.
1InvitationsToTransmit.
154.
6.
2FreeBufferEnquiries154.
6.
3DataPackets.
154.
6.
4Acknowledgements.
164.
6.
5NegativeAcknowledgements.
16Chapter5SystemDescription175.
1MicrocontrollerInterface.
175.
1.
1HighSpeedCPUBusTimingSupport205.
2TransmissionMediaInterface215.
2.
1TraditionalHybridInterface215.
2.
2BackplaneConfiguration215.
2.
3DifferentialDriverConfiguration235.
2.
4ProgrammableTXENPolarity23Chapter6FunctionalDescription.
266.
1Microsequencer.
266.
2InternalRegisters276.
2.
1InterruptMaskRegister(IMR)276.
2.
2DataRegister286.
2.
3TentativeIDRegister286.
2.
4NodeIDRegister.
286.
2.
5NextIDRegister.
286.
2.
6StatusRegister.
296.
2.
7DiagnosticStatusRegister.
296.
2.
8CommandRegister296.
2.
9AddressPointerRegisters296.
2.
10ConfigurationRegister.
296.
2.
11Sub-AddressRegister296.
2.
12Setup1Register.
306.
2.
13Setup2Register.
306.
3InternalRAM406.
3.
1SequentialAccessMemory.
406.
3.
2AccessSpeed406.
4SoftwareInterface406.
4.
1SelectingRAMPageSize416.
4.
2TransmitSequence.
426.
4.
3ReceiveSequence.
446.
5CommandChaining.
456.
5.
1TransmitCommandChaining456.
5.
2ReceiveCommandChaining466.
6ResetDetails.
476.
6.
1InternalResetLogic476.
7InitializationSequence476.
7.
1BusDetermination.
475MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page4SMSCCOM20020IRevDDATASHEET6.
8ImprovedDiagnostics.
486.
8.
1NormalResults:486.
8.
2AbnormalResults:486.
9Oscillator49Chapter7OperationalDescription.
507.
1MaximumGuaranteedRatings*507.
2DCElectricalCharacteristics.
50Chapter8TimingDiagrams53Chapter9PackageOutlines66AppendixA.
68AppendixB-ExampleofInterfaceCircuitDiagramtoISABus.
71AppendixC-SoftwareIdentificationoftheCOM20020RevB,RevCandRevD.
72ListofFiguresFigure2.
1-PinConfiguration-COM20020I28-PinPLCC7Figure2.
2-PinConfiguration-COM20020I48-PinTQFP.
8Figure3.
1-COM20020IDOperation11Figure5.
1–Multiplexed,8051-LikeBusInterfacewithRS-485Interface.
18Figure5.
2–Non-Multiplexed,6801-LikeBusInterfacewithRS-485Interface19Figure5.
3–HighSpeedCPUBusTiming–IntelCPUMode.
20Figure5.
4-COM20020IDNetworkUsingRS-485DifferentialTransceivers.
22Figure5.
5–DipulseWaveformforDataof1-1-0.
22Figure5.
6-InternalBlockDiagram.
24Figure6.
1-SequentialAccessOperation.
39Figure6.
2-RAMBufferPacketConfiguration42Figure6.
3–CommandChainingStatusRegisterQueue.
44Figure8.
1–MultiplexedBus,68XX-LikeControlSignals;ReadCycle.
53Figure8.
2–MultiplexedBus,80XX-LikeControlSignals;ReadCycle.
54Figure8.
3-MultiplexedBus,68XX-LikeControlSignals;WriteCycle.
55Figure8.
4-MultiplexedBus,80XX-LikeControlSignals;WriteCycle.
56Figure8.
5-Non-MultiplexedBus,80XX-LikeControlSignals;ReadCycle.
57Figure8.
6-Non-MultiplexedBus,80XX-LikeControlSignals;ReadCycle.
58Figure8.
7-Non-MultiplexedBus,68XX-LikeControlSignals;ReadCycle.
59Figure8.
8-Non-MultiplexedBus,68XX-LikeControlSignals;ReadCycle.
60Figure8.
9-Non-MultiplexedBus,80XX-LikeControlSignals;WriteCycle.
61Figure8.
10-Non-MultiplexedBus,68XX-LikeControlSignals;WriteCycle.
62Figure8.
11-NormalModeTransmitorReceiveTiming.
63Figure8.
12-BackplaneModeTransmitorReceiveTiming64Figure8.
13-TTLInputTimingonXTAL1Pin.
65Figure8.
14-ResetandInterruptTiming65Figure9.
1-28PinPLCCPackageDimensions.
66Figure9.
2-48PinTQFPPackageOutline.
67Figure0.
1-EffectoftheEFBitontheTA/RIBit.
70ListofTablesTable5.
1-TypicalMedia.
24Table6.
1-ReadRegisterSummary.
26Table6.
2-WriteRegisterSummary.
27Table6.
3-StatusRegister.
31Table6.
4-DiagnosticStatusRegister.
32Table6.
5-CommandRegister.
33Table6.
6-AddressPointerHighRegister.
34Table6.
7-AddressPointerLowRegister.
34Table6.
8-SubAddressRegister.
34Table6.
9-ConfigurationRegister355MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage5Revision12-05-06DATASHEETTable6.
10-Setup1Register.
36Table6.
11-Setup2Register.
37Table9.
1-48PinTQFPPackageParameters.
67FormoredetailsontheARCNETprotocolengineandtraditionaldipulsesignalingschemes,pleaserefertotheARCNETLocalAreaNetworkStandard,availablefromStandardMicrosystemsCorporationortheARCNETDesigner'sHandbook,availablefromDatapointCorporation.
FormoredetailedinformationoncablingoptionsincludingRS485,transformer-coupledRS-485andFiberOpticinterfaces,pleaserefertothefollowingtechnicalnotewhichisavailablefromStandardMicrosystemsCorporation:TechnicalNote7-5-CablingGuidelinesfortheCOM20020ULANC.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page6SMSCCOM20020IRevDDATASHEETChapter1GeneralDescriptionSMSC'sCOM20020IDisamemberofthefamilyofEmbeddedARCNETControllersfromStandardMicrosystemsCorporation.
Thedeviceisageneralpurposecommunicationscontrollerfornetworkingmicrocontrollersandintelligentperipheralsinindustrial,automotive,andembeddedcontrolenvironmentsusinganARCNETprotocolengine.
Thesmall28pinpackage,flexiblemicrocontrollerandmediainterfaces,eight-pagemessagesupport,andextendedtemperaturerangeoftheCOM20020IDmakeittheonlytruenetworkcontrolleroptimizedforuseinindustrial,embedded,andautomotiveapplications.
UsinganARCNETprotocolengineistheidealsolutionforembeddedcontrolapplicationsbecauseitprovidesadeterministictoken-passingprotocol,ahighlyreliableandprovennetworkingscheme,andadatarateofupto5MbpswhenusingtheCOM20020ID.
Atoken-passingprotocolprovidespredictableresponsetimesbecauseeachnetworkeventoccurswithinapredeterminedtimeinterval,baseduponthenumberofnodesonthenetwork.
ThedeterministicnatureofARCNETisessentialinrealtimeapplications.
Theintegrationofthe2Kx8RAMbufferon-chip,theCommandChainingfeature,the5Mbpsmaximumdatarate,andtheinternaldiagnosticsmaketheCOM20020IDthehighestperformanceembeddedcommunicationsdeviceavailable.
WithonlyoneCOM20020IDandonemicrocontroller,acompletecommunicationsnodemaybeimplemented.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage7Revision12-05-06DATASHEETChapter2PinConfigurations26272812341817161514131256789101125242322212019nPULSE1XTAL2XTAL1VDDVSSN/CD7nWR/DIRnRD/nDSVDDA0/nMUXA1A2/ALEAD0nCSnINTRnRESETINVSSnTXENRXINnPULSE2AD1AD2VSSD3D4D5D6Package:28-PinPLCCCOM20020ILJPPACKAGETYPE:"LJP"=Standard(Sn/Pb)platedPLCC"-DZD"=Pb-freeplatedPLCCTEMPRANGE:(Blank)=Commercial=0°Cto+70°C"I"=Industrial=-40°Cto+85°CDEVICETYPE:20020=UniversalLocalAreaNetworkController(with2Kx8RAM)OrderingInformation:Figure2.
1-PinConfiguration-COM20020I28-PinPLCC5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page8SMSCCOM20020IRevDDATASHEETFigure2.
2-PinConfiguration-COM20020I48-PinTQFP484746454443424140393837131415161718192021222324123456789101112363534333231302928272625N/CN/CA2/ALEA1A0/nMUXVDDN/CVSSN/CnRD/nDSVDDnWR/DIRD7N/CN/CN/CN/CVSSN/CVDDXTAL1XTAL2VSSnPULSE1AD0AD1N/CAD2N/CVSSD3VDDD4D5VSSD6nCSVDDnINTRN/CVDDnRESETVSSnTXENRXINN/CBUSTMGnPULSE2COM20020I48PINTQFP5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage9Revision12-05-06DATASHEETChapter3DescriptionofPinFunctionsPLCCPINNO.
NAMESYMBOLDESCRIPTIONMICROCONTROLLERINTERFACE1-3Address0-2A0/nMUX,A1,A2/ALEInput.
Onanon-multiplexedmode,A0-A2areaddressinputbits.
(A0istheLSB)Onamultiplexedaddress/databus,nMUXtiedLow,A1isleftopen,andALEistiedtotheAddressLatchEnablesignal.
A1isconnectedtoaninternalpull-upresistor.
4-6,8-12Data0-7AD0-AD2,D3-D7Input/Output.
Onanon-multiplexedbus,thesesignalsareusedasthedatalinesforthedevice.
Onamultiplexedaddress/databus,AD0-AD2actastheaddresslines(latchedbyALE)andasthelowdatalinesforthedevice.
D3-D7arealwaysusedfordataonly.
Thesesignalsareconnectedtointernalpull-upresistors.
27nRead/nDataStrobenRD/nDSInput.
Ona68XX-likebus,nDSisanactivelowsignalissuedbythemicrocontrollerasthedatastrobesignaltostrobethedataontothebus.
Ona80XX-likebus,nRDisanactivelowsignalissuedbythemicrocontrollertoindicateareadoperation.
26nWrite/DirectionnWR/DIRInput.
Ona68XX-likebus,DIRisissuedbythemicrocontrollerastheRead/nWritesignaltodeterminethedirectionofdatatransfer.
Inthiscase,alogic"1"selectsareadoperation,whilealogic"0"selectsawriteoperation.
Inthiscase,dataisactuallystrobedbythenDSsignal.
Onan80XX-likebus,nWRisanactivelowsignalissuedbythemicrocontrollertoindicateawriteoperation.
Inthiscase,alogic"0"onthispin,whentheCOM20020IDisaccessed,enablesdatafromthedatabustobewrittentothedevice.
23nResetinnRESETInput.
Thisactivelowsignalexecutesahardwarereset.
24nInterruptnINTROutput.
ThisactivelowsignalisgeneratedbytheCOM20020IDwhenanenabledinterruptconditionoccurs.
25nChipSelectnCSInput.
ThisactivelowsignalselectstheCOM20020IDforanaccess.
TRANSMISSIONMEDIAINTERFACE19,18nPulse2,nPulse1nPULSE2,nPULSE1Output(nPULSE1),Input/Output(nPULSE2).
InNormalMode,theseactivelowsignalscarrythetransmitdatainformation,encodedinpulseformat,asDIPULSEwaveform.
WhenthedeviceisinBackplaneMode,thenPULSE1signaldriverisprogrammable(push/pulloropen-drain),whilethenPULSE2signalprovidesaclockwithfrequencyofdoublethedatarate.
nPULSE1isconnectedtoaweakinternalpull-upresistorontheopen/draindriverinbackplanemode.
20ReceiveInRXINInput.
Thissignalcarriesthereceivedatainformationfromthelinetransceiver.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page10SMSCCOM20020IRevDDATASHEETPLCCPINNO.
NAMESYMBOLDESCRIPTION21nTransmitnEnablenTXENOutput.
ThissignalisusedpriortothePower-uptoenablethelinedriversfortransmission.
ThepolarityofthesignalisprogrammablethroughthenPULSE2pin.
nPULSE2floatingbeforePower-up:nTXENactivelow(Defaultoption)nPULSE2groundedbeforePower-up:nTXENactivehigh(ThisoptionisonlyavailableinBackplaneMode)16,17CrystalOscillatorXTAL1,XTAL2Anexternalcrystalshouldbeconnectedtothesepins.
Oscillationfrequencyrangeisfrom10to20MHz.
IfanexternalTTLclockisusedinstead,itmustbeconnectedtoXTAL1witha390Ωpull-upresistor,andXTAL2shouldbeleftfloating.
15,28PowerSupplyVDD+5VoltPowerSupplypin.
7,14,22GroundVSSGroundpin.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage11Revision12-05-06DATASHEETFigure3.
1-COM20020IDOperationInvitationtoTransmittothisIDYNFreeBufferEnquirytothisIDSOHYNYNRIWriteSIDtoBufferDID=0DID=IDWriteBufferwithPacketCRCOKLENGTHOKDID=0DID=IDSENDACKNYNYNYNBroadcastEnabledNYNNoActivityfor41uSYNSetNID=IDStartTimer:T=(255-ID)ActivityOnLineYNT=0SetRIRITransmitNAKTransmitACKSetNID=IDWriteIDtoRAMBufferSendReconfigureBurstPowerOnReconfigureTimerhasTimedOutStartReconfigurationTimer(420mS)*TABroadcastTransmitFreeBufferEnquiryNoActivityPasstheTokenSetTAYNACKNAK1NoActivityNYIncrementNIDSendPacketWasPacketBroadcastNoActivityNACKSetTMASetTAx73usfor37.
4usfor37.
4usfor37.
4usYNNYYNNYNNNN1YYYYYYYNYReadNodeIDIDreferstotheidentificationnumberoftheIDassignedtothisnode.
NIDreferstothenextidentificationnumberthatreceivesthetokenafterthisIDpassesit.
----SIDreferstothesourceidentification.
DIDreferstothedestinationidentification.
SOHreferstothestartofheadercharacter;preceedsalldatapackets.
-YN*Reconfigtimerisprogrammableviasetup2registerbits1,0.
Note-Alltimevaluesarevalidfor5Mbps.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page12SMSCCOM20020IRevDDATASHEETChapter4ProtocolDescription4.
1NetworkProtocolCommunicationonthenetworkisbasedonatokenpassingprotocol.
EstablishmentofthenetworkconfigurationandmanagementofthenetworkprotocolarehandledentirelybytheCOM20020ID'sinternalmicrocodedsequencer.
AprocessororintelligentperipheraltransmitsdatabysimplyloadingadatapacketanditsdestinationIDintotheCOM20020ID'sinternalRAMbuffer,andissuingacommandtoenablethetransmitter.
WhentheCOM20020IDnextreceivesthetoken,itverifiesthatthereceivingnodeisreadybyfirsttransmittingaFREEBUFFERENQUIRYmessage.
IfthereceivingnodetransmitsanACKnowledgemessage,thedatapacketistransmittedfollowedbya16-bitCRC.
Ifthereceivingnodecannotacceptthepacket(typicallyitsreceiverisinhibited),ittransmitsaNegativeAcKnowledgemessageandthetransmitterpassesthetoken.
Onceithasbeenestablishedthatthereceivingnodecanacceptthepacketandtransmissioniscomplete,thereceivingnodeverifiesthepacket.
Ifthepacketisreceivedsuccessfully,thereceivingnodetransmitsanACKnowledgemessage(ornothingifitisnotreceivedsuccessfully)allowingthetransmittertosettheappropriatestatusbitstoindicatesuccessfulorunsuccessfuldeliveryofthepacket.
AninterruptmaskpermitstheCOM20020IDtogenerateaninterrupttotheprocessorwhenselectedstatusbitsbecometrue.
Figure3.
1isaflowchartillustratingtheinternaloperationoftheCOM20020IDconnectedtoa20MHzcrystaloscillator.
4.
2DataRatesTheCOM20020IDiscapableofsupportingdataratesfrom156.
25Kbpsto5Mbps.
Thefollowingprotocoldescriptionassumesa5Mbpsdatarate.
Toattainthefasterdatarates,theclockfrequencymaybedoubledbytheinternalclockmultiplier(seenextsection).
Forslowerdatarates,aninternalclockdividerscalesdowntheclockfrequency.
Thusalltimeoutvaluesarescaledasshowninthefollowingtable:Example:IDLELINETimeout@5Mbps=41μs.
IDLELINETimeoutfor156.
2Kbpsis41μs*32=1.
3msINTERNALCLOCKFREQUENCYCLOCKPRESCALERDATARATETIMEOUTSCALINGFACTOR(MULTIPLYBY)40MHzDiv.
by85Mbps120MHzDiv.
by8Div.
by16Div.
by32Div.
by64Div.
by1282.
5Mbps1.
25Mbps625Kbps312.
5Kbps156.
25Kbps24816324.
2.
1SelectingClockFrequenciesAbove2.
5MbpsTorealizea5Mbpsnetwork,anexternal40MHzclockmustbeinput.
However,since40MHzisnearthefrequencyofFMradioband,itisnotpracticalforusefornoiseemissionreasons.
Therefore,higherfrequencyclocksaregeneratedfromthe20MHzcrystalasselectedthroughtwobitsintheSetup2register,CKUP[1,0]asshownbelow.
TheselectedclockissuppliedtotheARCNETcontroller.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage13Revision12-05-06DATASHEETCKUP1CKUP0CLOCKFREQUENCY(DATARATE)0020MHz(Upto2.
5Mbps)Default(Bypass)0140MHz(Upto5Mbps)10Reserved11ReservedThisclockmultiplierispowered-down(bypassed)ondefault.
AfterchangingtheCKUP1andCKUP0bits,theARCNETcoreoperationisstoppedandtheinternalPLLintheclockgeneratorisawakenedanditstartstogeneratethe40MHz.
ThelockouttimeoftheinternalPLLis8uSectypically.
Aftermorethan8μsec(thiswaittimeisdefinedas1msecinthisdatasheet),itisnecessarytowritecommanddata'18H'tothecommandregistertore-starttheARCNETcoreoperation.
Thisclockgeneratoriscalled"clockmultiplier".
ChangingtheCKUP1andCKUP0bitsmustbeonetimeorlessafterreleasinghardwarereset.
TheEFbitintheSETUP2registermustbesetwhenthedatarateisover5Mbps.
4.
3NetworkReconfigurationAsignificantadvantageoftheCOM20020IDisitsabilitytoadapttochangesonthenetwork.
Wheneveranewnodeisactivatedordeactivated,aNETWORKRECONFIGURATIONisperformed.
WhenanewCOM20020IDisturnedon(creatinganewactivenodeonthenetwork),oriftheCOM20020IDhasnotreceivedanINVITATIONTOTRANSMITfor420mS,orifasoftwareresetoccurs,theCOM20020IDcausesaNETWORKRECONFIGURATIONbysendingaRECONFIGUREBURSTconsistingofeightmarksandonespacerepeated765times.
Thepurposeofthisburstistoterminateallactivityonthenetwork.
Sincethisburstislongerthananyothertypeoftransmission,theburstwillinterferewiththenextINVITATIONTOTRANSMIT,destroythetokenandkeepanyothernodefromassumingcontroloftheline.
WhenanyCOM20020IDsensesanidlelineforgreaterthan41μS,whichoccursonlywhenthetokenIslost,eachCOM20020IDstartsaninternaltimeoutequalto73μstimesthequantity255minusitsownID.
TheCOM20020IDstartsnetworkreconfigurationbysendinganinvitationtotransmitfirsttoitselfandthentoallothernodesbydecrementingthedestinationNodeID.
Ifthetimeoutexpireswithnolineactivity,theCOM20020IDstartssendingINVITATIONTOTRANSMITwiththeDestinationID(DID)equaltothecurrentlystoredNID.
Withinagivennetwork,onlyoneCOM20020IDwilltimeout(theonewiththehighestIDnumber).
AftersendingtheINVITATIONTOTRANSMIT,theCOM20020IDwaitsforactivityontheline.
Ifthereisnoactivityfor37.
4μS,theCOM20020IDincrementstheNIDvalueandtransmitsanotherINVITATIONTOTRANSMITusingtheNIDequaltotheDID.
Ifactivityappearsbeforethe37.
4μStimeoutexpires,theCOM20020IDreleasescontroloftheline.
DuringNETWORKRECONFIGURATION,INVITATIONSTOTRANSMITaresenttoallNIDs(1-255).
EachCOM20020IDonthenetworkwillfinallyhavesavedaNIDvalueequaltotheIDoftheCOM20020IDthatitreleasedcontrolto.
Atthispoint,controlispasseddirectlyfromonenodetothenextwithnowastedINVITATIONSTOTRANSMITbeingsenttoID'snotonthenetwork,untilthenextNETWORKRECONFIGURATIONoccurs.
Whenanodeispoweredoff,thepreviousnodeattemptstopassthetokentoitbyissuinganINVITATIONTOTRANSMIT.
Sincethisnodedoesnotrespond,thepreviousnodetimesoutandtransmitsanotherINVITATIONTOTRANSMITtoanincrementedIDandeventuallyaresponsewillbereceived.
TheNETWORKRECONFIGURATIONtimedependsonthenumberofnodesinthenetwork,thepropagationdelaybetweennodes,andthehighestIDnumberonthenetwork,butistypicallywithintherangeof12to30.
5mS.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page14SMSCCOM20020IRevDDATASHEET4.
4BroadcastMessagesBroadcastinggivesaparticularnodetheabilitytotransmitadatapackettoallnodesonthenetworksimultaneously.
IDzeroisreservedforthisfeatureandnonodeonthenetworkcanbeassignedIDzero.
Tobroadcastamessage,thetransmittingnode'sprocessorsimplyloadstheRAMbufferwiththedatapacketandsetstheDIDequaltozero.
Figure5.
3–HighSpeedCPUBusTiming–IntelCPUMode,pg.
20illustratesthepositionofeachbyteinthepacketwiththeDIDresidingataddress0X01or1Hexofthecurrentpageselectedinthe"EnableTransmitfromPagefnn"command.
Eachindividualnodehastheabilitytoignorebroadcastmessagesbysettingthemostsignificantbitofthe"EnableReceivetoPagefnn"commandtoalogic"0".
4.
5ExtendedTimeoutFunctionTherearethreetimeoutsassociatedwiththeCOM20020IDoperation.
Thevaluesofthesetimeoutsarecontrolledbybits3and4oftheConfigurationRegisterandbit5oftheSetup1Register.
4.
5.
1ResponseTimeTheResponseTimedeterminesthemaximumpropagationdelayallowedbetweenanytwonodes,andshouldbechosentobelargerthantheroundtrippropagationdelaybetweenthetwofurthestnodesonthenetworkplusthemaximumturnaroundtime(thetimeittakesaparticularCOM20020IDtostartsendingamessageinresponsetoareceivedmessage)whichisapproximately6.
4μS.
Theroundtrippropagationdelayisafunctionofthetransmissionmediaandnetworktopology.
ForatypicalsystemusingRG62coaxinabasebandsystem,aonewaycablepropagationdelayof15.
5μStranslatestoadistanceofabout2miles.
TheflowchartinFigure3.
1usesavalueof37.
4μS(15.
5+15.
5+6.
4)todetermineifanynodewillrespond.
4.
5.
2IdleTimeTheIdleTimeisassociatedwithaNETWORKRECONFIGURATION.
Figure3.
1illustratesthatduringaNETWORKRECONFIGURATIONonenodewillcontinuallytransmitINVITATIONSTOTRANSMITuntilitencountersanactivenode.
Allothernodesonthenetworkmustdistinguishbetweenthisoperationandanentirelyidleline.
DuringNETWORKRECONFIGURATION,activitywillappearonthelineevery41μS.
This41μSisequaltotheResponseTimeof37.
4μSplusthetimeittakestheCOM20020IDtostartretransmittinganothermessage(usuallyanotherINVITATIONTOTRANSMIT).
4.
5.
3ReconfigurationTimeIfanynodedoesnotreceivethetokenwithintheReconfigurationTime,thenodewillinitiateaNETWORKRECONFIGURATION.
TheET2andET1bitsoftheConfigurationRegisterallowthenetworktooperateoverlongerdistancesthanthe2milesstatedearlier.
ThelogiclevelsonthesebitscontrolthemaximumdistancesoverwhichtheCOM20020IDcanoperatebycontrollingthethreetimeoutvaluesdescribedabove.
Forpropernetworkoperation,allCOM20020ID'sconnectedtothesamenetworkmusthavethesameResponseTime,IdleTime,andReconfigurationTime.
4.
6LineProtocolTheARCNETlineprotocolisconsideredisochronousbecauseeachbyteisprecededbyastartintervalandendedwithastopinterval.
Unlikeasynchronousprotocols,thereisaconstantamountoftimeseparatingeachdatabyte.
Ona5Mbpsnetwork,eachbytetakesexactly11clockintervalsof200ns5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage15Revision12-05-06DATASHEETeach.
Asaresult,onebyteistransmittedevery2.
2μSandthetimetotransmitamessagecanbepreciselydetermined.
Thelineidlesinaspacing(logic"0")condition.
Alogic"0"isdefinedasnolineactivityandalogic"1"isdefinedasanegativepulseof100nSduration.
AtransmissionstartswithanALERTBURSTconsistingof6unitintervalsofmark(logic"1").
Eightbitdatacharactersarethensent,witheachcharacterprecededby2unitintervalsofmarkandoneunitintervalofspace.
Fivetypesoftransmissioncanbeperformedasdescribedbelow:4.
6.
1InvitationsToTransmitAnInvitationToTransmitisusedtopassthetokenfromonenodetoanotherandissentbythefollowingsequence:AnALERTBURSTAnEOT(EndOfTransmission:ASCIIcode04H)Two(repeated)DID(DestinationID)charactersALERTBURSTEOTDIDDID4.
6.
2FreeBufferEnquiriesAFreeBufferEnquiryisusedtoaskanothernodeifitisabletoacceptapacketofdata.
Itissentbythefollowingsequence:AnALERTBURSTAnENQ(ENQuiry:ASCIIcode85H)Two(repeated)DID(DestinationID)charactersALERTBURSTENQDIDDID4.
6.
3DataPacketsADataPacketconsistsoftheactualdatabeingsenttoanothernode.
Itissentbythefollowingsequence:AnALERTBURSTAnSOH(StartOfHeader--ASCIIcode01H)AnSID(SourceID)characterTwo(repeated)DID(DestinationID)charactersAsingleCOUNTcharacterwhichisthe2'scomplementofthenumberofdatabytestofollowifashortpacketissent,or00HfollowedbyaCOUNTcharacterifalongpacketissent.
NdatabyteswhereCOUNT=256-N(or512-Nforalongpacket)TwoCRC(CyclicRedundancyCheck)characters.
TheCRCpolynomialusedis:X16+X15+X2+1.
ALERTBURSTSOHSIDDIDDIDCOUNTdatadataCRCCRC5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page16SMSCCOM20020IRevDDATASHEET4.
6.
4AcknowledgementsAnAcknowledgementisusedtoacknowledgereceptionofapacketorasanaffirmativeresponsetoFREEBUFFERENQUIRIESandissentbythefollowingsequence:AnALERTBURSTAnACK(ACKnowledgement--ASCIIcode86H)characterALERTBURSTACK4.
6.
5NegativeAcknowledgementsANegativeAcknowledgementisusedasanegativeresponsetoFREEBUFFERENQUIRIESandissentbythefollowingsequence:AnALERTBURSTANAK(NegativeAcknowledgement--ASCIIcode15H)characterALERTBURSTNAK5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage17Revision12-05-06DATASHEETChapter5SystemDescription5.
1MicrocontrollerInterfaceThetophalvesofFigure5.
1andFigure5.
2illustratetypicalCOM20020IDinterfacestothemicrocontrollers.
Theinterfacesconsistofa8-bitdatabus,anaddressbusandacontrolbus.
Inordertosupportawiderangeofmicrocontrollerswithoutrequiringgluelogicandwithoutincreasingthenumberofpins,theCOM20020IDautomaticallydetectsandadaptstothetypeofmicrocontrollerbeingused.
Uponhardwarereset,theCOM20020IDfirstdetermineswhetherthereadandwritecontrolsignalsareseparateREADandWRITEsignals(likethe80XX)orDIRECTIONandDATASTROBE(likethe68XX).
Todeterminethetypeofcontrolsignals,thedevicerequiresthesoftwaretoexecuteatleastonewriteaccesstoexternalmemorybeforeattemptingtoaccesstheCOM20020ID.
Thedevicedefaultsto80XX-likesignals.
Oncethetypeofcontrolsignalsaredetermined,theCOM20020IDremainsinthisinterfacemodeuntilthenexthardwareresetoccurs.
TheseconddeterminationtheCOM20020IDmakesiswhetherthebusismultiplexedornon-multiplexed.
Todeterminethetypeofbus,thedevicerequiresthesoftwaretowritetoanoddmemorylocationfollowedbyareadfromanoddlocationbeforeattemptingtoaccesstheCOM20020ID.
ThesignalontheA0pinduringtheoddlocationaccesstellstheCOM20020IDthetypeofbus.
SincemultiplexedoperationrequiresA0tobeactivelow,activityontheA0linetellstheCOM20020IDthatthebusisnon-multiplexed.
Thedevicedefaultstomultiplexedoperation.
BothdeterminationsmaybemadesimultaneouslybyperformingaWRITEfollowedbyaREADoperationtoanoddlocationwithintheCOM20020IDAddressspace20020Dregisters.
Oncethetypeofbusisdetermined,theCOM20020IDremainsinthisinterfacemodeuntilhardwareresetoccurs.
WhenevernCSandnRDareactivated,thepresetdeterminationsareassumedasfinalandwillnotbechangeduntilhardwarereset.
RefertoDescriptionofPinFunctionssectionfordetailsontherelatedsignals.
AllaccessestotheinternalRAMandtheinternalregistersarecontrolledbytheCOM20020ID.
TheinternalRAMisaccessedviaapointer-basedscheme(refertotheSequentialAccessMemorysection),andtheinternalregistersareaccessedviadirectaddressing.
Manyperipheralsarenotfastenoughtotakeadvantageofhigh-speedmicrocontrollers.
SincemicrocontrollersdonottypicallyhaveREADYinputs,standardperipheralscannotextendcyclestoextendtheaccesstime.
TheaccesstimeoftheCOM20020ID,ontheotherhand,issofastthatitdoesnotneedtolimitthespeedofthemicrocontroller.
TheCOM20020IDisdesignedtobeflexiblesothatitisindependentofthemicrocontrollerspeed.
TheCOM20020IDprovidesfornowaitstatearbitrationviadirectaddressingtoitsinternalregistersandapointerbasedaddressingschemetoaccessitsinternalRAM.
Thepointermaybeusedinauto-incrementmodefortypicalsequentialbufferemptyingorloading,oritcanbetakenoutofauto-incrementmodetoperformrandomaccessestotheRAM.
ThedatawithintheRAMisaccessedthroughthedataregister.
Databeingreadisprefetchedfrommemoryandplacedintothedataregisterforthemicrocontrollertoread.
Itisimportanttonoticethatonlybywritinganewaddresspointer(writingtoanaddresspointerlow),oneobtainsthecontentsofCOM20020IDinternalRAM.
PerformingonlyreadfromtheDataRegisterdoesnotloadnewdatafromtheinternalRAM.
Duringawriteoperation,thedataisstoredinthedataregisterandthenwrittenintomemory.
Wheneverthepointerisloadedforreadswithanewvalue,dataisimmediatelyprefetchedtoprepareforthefirstreadoperation.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page18SMSCCOM20020IRevDDATASHEETFigure5.
1–Multiplexed,8051-LikeBusInterfacewithRS-485InterfaceRXINnPULSEnPULSETXENGND+5V100BACKPLANEFIGUREARXINnPULSEFIGUREBReceiveHFD3212-2+5V76TransmitteHFE4211-+5V32Fiber(ST267NOTE:COM20020mustbeinbackplanemodeAD0-nINT1RESETnRDnWRA15AD0-AD2,D3-nCSnRESETnRD/nDnWR/DInINTRA2/BALALEXTAL1XTAL2GNDRXINnPULSEnPULSEnTXEN8051COM20020IDDifferentialConfiguratioMediamaybewithFigureA,Bor*75176BorEquiv.
A0/nMU27pF27pFXTAL2XTAL120MHzXTAL5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage19Revision12-05-06DATASHEETFigure5.
2–Non-Multiplexed,6801-LikeBusInterfacewithRS-485InterfaceD0-D7nIRQ1nRESnIOSR/nWA7D0-D7A0/nMUXA0XTAL1XTAL2A1A1nCSnRESETnRD/nDSnWR/nDIRnINTRA2/BALEA2RXINnPULSE1nPULSE2TXENGNDDifferentialDriverConfiguration6801COM20020IDMediaInterfacemaybereplacedwithFigureA,BorC.
*75176BorEquiv.
XTAL1XTAL227pF27pF20MHzXTALRXINnPULSE1nPULSE2nTXENGNDTraditionalHybridConfigurationRXINnPULSE1nPULSE217,19,4,13,145.
6K1/2W5.
6K1/2W0.
01uF1KV1211-5V0.
47uF10uF+30.
47uF++5VuF106FIGURECHYC9088HYC9068orN/C*Validfor2.
5Mbpsonly.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page20SMSCCOM20020IRevDDATASHEET5.
1.
1HighSpeedCPUBusTimingSupportHighspeedCPUbussupportwasaddedtotheCOM20020ID.
Thereasoningbehindthisisasfollows:WiththeHostinterfaceinNon-multiplexedBusmode,I/OaddressandChipSelectsignalsmustbestablebeforethereadsignalisactiveandremainafterthereadsignalisinactive.
ButtheHighSpeedCPUbustimingdoesn'tadheretothesetimings.
Forexample,aRISCtypesinglechipmicrocontroller(liketheHITACHISH-1series)changesI/Oaddressatthesametimeasthereadsignal.
Therefore,severalexternallogicICswouldberequiredtoconnecttothismicrocontroller.
Inaddition,theDiagnosticStatus(DIAG)registerisclearedautomaticallybyreadingitself.
TheinternalDIAGregisterreadsignalisgeneratedbydecodingtheAddress(A2-A0),ChipSelect(nCS)andRead(nRD)signals.
Thedecoderwillgenerateanoisespikeattheabovetighttiming.
TheDIAGregisterisclearedbythespikesignalwithoutreadingitself.
Thisisunexpectedoperation.
ReadingtheinternalRAMandNextIdRegisterhavethesamemechanismasreadingtheDIAGregister.
Therefore,theaddressdecodeandhostinterfacemodeblocksweremodifiedtofittheaboveCPUinterfacetosupporthighspeedCPUbustiming.
InIntelCPUmode(nRD,nWRmode),3bitI/Oaddress(A2-A0)andChipSelect(nCS)aresampledinternallybyFlip-FlopsonthefallingedgeoftheinternaldelayednRDsignal.
TheinternalrealreadsignalisthemoredelayednRDsignal.
ButtherisingedgeofnRDdoesn'tdelay.
Bythismodification,theinternalrealaddressandChipSelectarestablewhiletheinternalrealreadsignalisactive.
RefertoFigure5.
3below.
Figure5.
3–HighSpeedCPUBusTiming–IntelCPUModeTheI/OaddressandChipSelectsignals,whicharesuppliedtothedataoutputlogic,arenotsampled.
Also,thenRDsignalisnotdelayed,becausetheabovesamplinganddelayingpathsdecreasethedataaccesstimeofthereadcycle.
TheabovesamplinganddelayingsignalsaresuppliedtotheReadPulseGenerationlogicwhichgeneratestheclearingpulsefortheDiagnosticregisterandgeneratesthestartingpulseoftheRAMArbitration.
TypicaldelaytimebetweennRDandnRD1isaround15nSandbetweennRD1andnRD2isaround10nS.
LongerpulsewidthsareneededduetothesedelaysonnRDsignal.
However,theCPUcaninsertsomewaitcyclestoextendthewidthwithoutanyimpactonperformance.
TheRBUSTMGbitwasaddedtoDisable/EnabletheHighSpeedCPUReadfunction.
Itisdefinedas:RBUSTMG=0,Disabled(Default);RBUSTMG=1,Enabled.
A2-A0,nCSnRDDelayednRD(nRD1)SampledA2-A0,nCSMoredelayednRD(nRD2)VALIDVALID5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage21Revision12-05-06DATASHEETIntheMOTOROLACPUmode(DIR,nDSmode),thesamemodificationsapply.
RBUSTMGBITBUSTIMINGMODE0NormalSpeedCPUReadandWrite1HighSpeedCPUReadandNormalSpeedCPUWrite5.
2TransmissionMediaInterfaceThebottomhalvesofFigure5.
1andFigure5.
2illustratetheCOM20020IDinterfacetothetransmissionmediausedtoconnectthenodetothenetwork.
Table5.
1-TypicalMediaonpage24listsdifferenttypesofcablewhicharesuitableforARCNETapplications.
1Theusermayinterfacetothecableofchoiceinoneofthreeways:5.
2.
1TraditionalHybridInterfaceTheTraditionalHybridInterfaceisthatwhichisusedwithpreviousARCNETdevices.
TheHybridInterfaceisrecommendedifthenodeistobeplacedinanetworkwithotherHybrid-Interfacednodes.
TheTraditionalHybridInterfaceisforusewithnodesoperatingat2.
5Mbpsonly.
ThetransformercouplingoftheHybridoffersisolationforthesafetyofthesystemandoffershighCommonModeRejection.
TheTraditionalHybridInterfaceusescircuitslikeSMSC'sHYC9068orHYC9088totransferthepulse-encodeddatabetweenthecableandtheCOM20020ID.
TheCOM20020IDtransmitsalogic"1"bygeneratingtwo100nSnon-overlappingnegativepulses,nPULSE1andnPULSE2.
Lackofpulsesindicatesalogic"0".
ThenPULSE1andnPULSE2signalsaresenttotheHybrid,whichcreatesa200nSdipulsesignalonthemedia.
Alogic"0"istransmittedbytheabsenceofthedipulse.
Duringreception,the200nSdipulseappearingonthemediaiscoupledthroughtheRFtransformeroftheLANDriver,whichproducesapositivepulseattheRXINpinoftheCOM20020ID.
ThepulseontheRXINpinrepresentsalogic"1".
Lackofpulserepresentsalogic"0".
Typically,RXINpulsesoccuratmultiplesof400nS.
TheCOM20020IDcantoleratedistortionofplusorminus100nSandstillcorrectlycaptureandconverttheRXINpulsestoNRZformat.
Figure5.
4illustratestheeventswhichoccurintransmissionorreceptionofdataconsistingof1,1,0.
Note:PleaserefertoTN7-5–CablingGuidelinesfortheCOM20020ULANC,availablefromSMSC,forrecommendedcablingdistance,termination,andnodecountforARCNETnodes.
5.
2.
2BackplaneConfigurationTheBackplaneOpenDrainConfigurationisrecommendedforcost-sensitive,short-distanceapplicationslikebackplanesandinstrumentation.
Thismodeisadvantageousbecauseitsavescomponents,cost,andpower.
SincetheBackplaneConfigurationencodesdatadifferentlythanthetraditionalHybridConfiguration,nodesutilizingtheBackplaneConfigurationcannotcommunicatedirectlywithnodesutilizingtheTraditionalHybridConfiguration.
TheBackplaneConfigurationdoesnotisolatethenodefromthemedianorprotectsitfromCommonModenoise,butCommonModeNoiseislessofaprobleminshortdistances.
TheCOM20020IDsuppliesaprogrammableoutputdriverforBackplaneModeoperation.
Apush/pulloropendraindrivercanbeselectedbyprogrammingtheP1MODEbitoftheSetup1Register(seeregisterdescriptionsfordetails).
TheCOM20020IDdefaultstoanopendrainoutput.
TheBackplaneConfigurationprovidesfordirectconnectionbetweentheCOM20020IDandthemedia.
Onlyonepull-upresistor(inopendrainconfigurationoftheoutputdriver)isrequiredsomewhereonthe5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page22SMSCCOM20020IRevDDATASHEETmedia(notoneachindividualnode).
ThenPULSE1signal,inthismode,isanopendrainorpush/pulldriverandisusedtodirectlydrivethemedia.
Itissuesa200nSnegativepulsetotransmitalogic"1".
Notethatwhenusedintheopen-drainmode,theCOM20020IDdoesnothaveafail/safeinputontheRXINpin.
ThenPULSE1signalactuallycontainsaweakpull-upresistor.
Thispull-upshouldnottaketheplaceoftheresistorrequiredonthemediaforopendrainmode.
Figure5.
4-COM20020IDNetworkUsingRS-485DifferentialTransceiversFigure5.
5–DipulseWaveformforDataof1-1-0Intypicalapplications,theserialbackplaneisterminatedatbothendsandabiasisprovidedbytheexternalpull-upresistor.
TheRXINsignalisdirectlyconnectedtothecableviaaninternalSchmitttrigger.
Anegativepulseonthisinputindicatesalogic"1".
Lackofpulseindicatesalogic"0".
Fortypicalsingle-endedbackplaneapplications,RXINisconnectedtonPULSE1tomaketheserialbackplanedataline.
Agroundline(fromthecoaxortwistedpair)shouldruninparallelwiththesignal.
ForapplicationsrequiringdifferenttreatmentCOM20020ID+VCCRBIAS+VCC+VCCRBIASRBIASRTRT75176BorEquiv.
COM20020IDCOM20020ID20MHZCLOCK(FORREF.
ONLY)nPULSE1nPULSE2DIPULSERXIN10100ns100ns200ns400ns15MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage23Revision12-05-06DATASHEETofthereceivesignal(likefilteringorsquelching),nPULSE1andRXINremainasindependentpins.
Externaldifferentialdrivers/receiversforincreasedrangeandcommonmodenoiserejection,forexample,wouldrequirethesignalstobeindependentofoneanother.
WhenthedeviceisinBackplaneMode,theclockprovidedbythenPULSE2signalmaybeusedforencodingthedataintoadifferentencodingschemeorothersynchronousoperationsneededontheserialdatastream.
5.
2.
3DifferentialDriverConfigurationTheDifferentialDriverConfigurationisaspecialcaseoftheBackplaneMode.
Itisadccoupledconfigurationrecommendedforapplicationslikecar-areanetworksorothercost-sensitiveapplicationswhichdonotrequiredirectcompatibilitywithexistingARCNETnodesanddonotrequireisolation.
TheDifferentialDriverConfigurationcannotcommunicatedirectlywithnodesutilizingtheTraditionalHybridConfiguration.
LiketheBackplaneConfiguration,theDifferentialDriverConfigurationdoesnotisolatethenodefromthemedia.
TheDifferentialDriverinterfaceincludesaRS485Driver/ReceivertotransferthedatabetweenthecableandtheCOM20020ID.
ThenPULSE1signaltransmitsthedata,providedtheTransmitEnablesignalisactive.
ThenPULSE1signalissuesa200nS(at2.
5Mbps)negativepulsetotransmitalogic"1".
Lackofpulseindicatesalogic"0".
TheRXINsignalreceivesthedata,thetransmitterportionoftheCOM20020IDisdisabledduringresetandthenPULSE1,nPULSE2andnTXENpinsareinactive.
5.
2.
4ProgrammableTXENPolarityToaccommodatetransceiverswithactivehighENABLEpins,theCOM20020IDcontainsaprogrammableTXENoutput.
ToprogramtheTXENpinforanactivehighpulse,thenPULSE2pinshouldbeconnectedtoground.
Toretainthenormalactivelowpolarity,nPULSE2shouldbeleftopen.
ThepolaritydeterminationismadeatpoweronresetandisvalidonlyforBackplaneModeoperation.
ThenPULSE2pinshouldremaingroundedatalltimesifanactivehighpolarityisdesired.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page24SMSCCOM20020IRevDDATASHEETFigure5.
6-InternalBlockDiagramTable5.
1-TypicalMediaCABLETYPENOMINALIMPEDANCEATTENUATIONPER1000FT.
AT5MHZRG-62Belden#8626293Ω5.
5dBRG-59/UBelden#8910875Ω7.
0dBRG-11/UBelden#8910875Ω5.
5dBIBMType1*Belden#89688150Ω7.
0dBIBMType3*TelephoneTwistedPairBelden#1155A100Ω17.
9dBCOMCODE26AWGTwistedPairPart#105-064-703105Ω16.
0dB*Non-plenum-ratedcablesofthistypearealsoavailable.
MICRO-SEQUENCERANDWORKINGREGISTERSSTATUS/COMMANDREGISTERRESETLOGICRECONFIGURATIONTIMERNODEIDLOGICOSCILLATORTX/RXLOGICADDITIONALREGISTERSADDRESSDECODINGCIRCUITRY2Kx8AD0-AD2,BUSARBITRATIONCIRCUITRYnPULSE1nPULSE2nTXENnINTRnRESETRAMA0/nMUXA1A2/BALEnRD/nDSnWR/DIRnCSD3-D7RXINXTAL1XTAL25MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage25Revision12-05-06DATASHEETNote:FormoredetailedinformationonCablingoptionsincludingRS-485,transformer-coupledRS-485andFiberOpticinterfaces,pleaserefertoTN7-5–CablingGuidelinesfortheCOM20020ULANC,availablefromStandardMicrosystemsCorporation.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page26SMSCCOM20020IRevDDATASHEETChapter6FunctionalDescription6.
1MicrosequencerTheCOM20020IDcontainsaninternalmicrosequencerwhichperformsallofthecontroloperationsnecessarytocarryouttheARCNETprotocol.
Itconsistsofaclockgenerator,a544x8ROM,aprogramcounter,twoinstructionregisters,aninstructiondecoder,ano-opgenerator,jumplogic,andreconfigurationlogic.
TheCOM20020IDderivesa10MHzanda5MHzclockfromtheoutputclockoftheClockMultiplier.
TheseclocksprovidetherateatwhichtheinstructionsareexecutedwithintheCOM20020ID.
The10MHzclockistherateatwhichtheprogramcounteroperates,whilethe5MHzclockistherateatwhichtheinstructionsareexecuted.
ThemicroprogramisstoredintheROMandtheinstructionsarefetchedandthenplacedintotheinstructionregisters.
Oneregisterholdstheopcode,whiletheotherholdstheimmediatedata.
Oncetheinstructionisfetched,itisdecodedbytheinternalinstructiondecoder,atwhichpointtheCOM20020IDproceedstoexecutetheinstruction.
Whenano-opinstructionisencountered,themicrosequencerentersatimedloopandtheprogramcounteristemporarilystoppeduntiltheloopiscomplete.
Whenajumpinstructionisencountered,theprogramcounterisloadedwiththejumpaddressfromtheROM.
TheCOM20020IDcontainsaninternalreconfigurationtimerwhichinterruptsthemicrosequencerifithastimedout.
AtthispointtheprogramcounterisclearedandtheMYRECONbitoftheDiagnosticStatusRegisterisset.
Table6.
1-ReadRegisterSummaryREGISTERMSBREADLSBADDRSTATUSRI/TRIX/RIX/TAPORTESTRECONTMATA/TTA00DIAG.
STATUSMY-RECONDUPIDRCV-ACTTOKENEXC-NAKTENTIDNEWNEXTIDX01ADDRESSPTRHIGHRD-DATAAUTO-INCXXXA10A9A802ADDRESSPTRLOWA7A6A5A4A3A2A1A003DATAD7D6D5D4D3D2D1D004SUBADR(R/W)Note6.
1000(R/W)Note6.
1SUB-AD2SUB-AD1SUB-AD005CONFIG-URATIONRESETCCHENTXENET1ET2BACK-PLANESUB-AD1SUB-AD006TENTIDTID7TID6TID5TID4TID3TID2TID1TID007-0NODEIDNID7NID6NID5NID4NID3NID2NID1NID007-1SETUP1P1MODEFOURNAKSXRCV-ALLCKP3CKP2CKP1SLOW-ARB07-2NEXTIDNXTID7NXTID6NXTID5NXTID4NXTID3NXTID2NXTID1NXTID007-3SETUP2RBUS-TMGXCKUP1CKUP0EFNO-SYNCRCN-TM1RCM-TM207-45MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage27Revision12-05-06DATASHEETNote6.
1(R/W)ThisbitcanbeWrittenorRead.
FormoreinformationseeAppendixC-SoftwareIdentificationoftheCOM20020RevB,RevCandRevD.
Table6.
2-WriteRegisterSummaryADDRMSBWRITELSBREGISTER00RI/TR1000EXCNAKRECONNEWNEXTIDTA/TTAINTERRUPTMASK01C7C6C5C4C3C2C1C0COMMAND02RD-DATAAUTO-INC000A10A9A8ADDRESSPTRHIGH03A7A6A5A4A3A2A1A0ADDRESSPTRLOW04D7D6D5D4D3D2D1D0DATA05(R/W)Note6.
2000(R/W)Note6.
2SUB-AD2SUB-AD1SUB-AD0SUBADR06RESETCCHENTXENET1ET2BACK-PLANESUB-AD1SUB-AD0CONFIG-URATION07-0TID7TID6TID5TID4TID3TID2TID1TID0TENTID07-1NID7NID6NID5NID4NID3NID2NID1NID0NODEID07-2P1-MODEFOURNAKS0RCV-ALLCKP3CKP2CKP1SLOW-ARBSETUP107-300000000TEST07-4RBUS-TMG0CKUP1CKUP0EFNO-SYNCRCN-TM1RCN-TM0SETUP2Note6.
2(R/W)ThisbitcanbeWrittenorRead.
FormoreinformationseeAppendixC-SoftwareIdentificationoftheCOM20020RevB,RevCandRevD.
6.
2InternalRegistersTheCOM20020IDcontains14internalregisters.
Table6.
1andTable6.
2illustratetheCOM20020IDregistermap.
Allundefinedbitsarereadasundefinedandmustbewrittenaslogic"0".
6.
2.
1InterruptMaskRegister(IMR)TheCOM20020IDiscapableofgeneratinganinterruptsignalwhencertainstatusbitsbecometrue.
AwritetotheIMRspecifieswhichstatusbitswillbeenabledtogenerateaninterrupt.
ThebitpositionsintheIMRareinthesamepositionastheircorrespondingstatusbitsintheStatusRegisterandDiagnosticStatusRegister.
Alogic"1"inaparticularpositionenablesthecorrespondinginterrupt.
TheStatusbitscapableofgeneratinganinterruptincludetheReceiverInhibitedbit,NewNextIDbit,ExcessiveNAKbit,ReconfigurationTimerbit,andTransmitterAvailablebit.
NootherStatusorDiagnosticStatusbitscangenerateaninterrupt.
ThesixmaskablestatusbitsareANDedwiththeirrespectivemaskbits,andtheresultsareORedtoproducetheinterruptsignal.
AnRIorTAinterruptismaskedwhenthecorrespondingmaskbitisresettologic"0",butwillreappearwhenthecorrespondingmaskbitissettologic"1"again,unlesstheinterruptstatusconditionhasbeenclearedbythistime.
ARECONinterruptisclearedwhenthe"ClearFlags"commandisissued.
AnEXCNAKinterruptisclearedwhenthe"PORClearFlags"commandisissued.
A5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page28SMSCCOM20020IRevDDATASHEETNewNextIDinterruptisclearedbyreadingtheNextIDRegister.
TheInterruptMaskRegisterdefaultstothevalue00000000uponhardwarereset.
6.
2.
2DataRegisterThisread/write8-bitregisterisusedasthechannelthroughwhichthedatatoandfromtheRAMpasses.
Thedataisplacedinorretrievedfromtheaddresslocationpresentlyspecifiedbytheaddresspointer.
ThecontentsoftheDataRegisterareundefineduponhardwarereset.
IncaseofREADoperation,theDataRegisterisloadedwiththecontentsofCOM20020IDInternalMemoryuponwritingAddressPointerlowonlyonce.
6.
2.
3TentativeIDRegisterTheTentativeIDRegisterisaread/write8-bitregisteraccessedwhentheSubAddressBitsaresetupaccordingly(pleaserefertotheConfigurationRegisterandSUBADRRegister).
TheTentativeIDRegistercanbeusedwhilethenodeison-linetobuildanetworkmapofthosenodesexistingonthenetwork.
Itminimizestheneedforoperatorinteractionwiththenetwork.
ThenodedeterminestheexistenceofothernodesbyplacingaNodeIDvalueintheTentativeIDRegisterandwaitingtoseeiftheTentativeIDbitoftheDiagnosticStatusRegistergetsset.
Thenetworkmapdevelopedbythismethodisonlyvalidforashortperiodoftime,sincenodesmayjoinordepartfromthenetworkatanytime.
WhenusingtheTentativeIDfeature,anodecannotdetecttheexistenceofthenextlogicalnodetowhichitpassesthetoken.
TheNextIDRegisterwillholdtheIDvalueofthatnode.
TheTentativeIDRegisterdefaultstothevalue00000000uponhardwareresetonly.
6.
2.
4NodeIDRegisterTheNodeIDRegisterisaread/write8-bitregisteraccessedwhentheSubAddressBitsaresetupaccordingly(pleaserefertotheConfigurationRegisterandSUBADRRegister).
TheNodeIDRegistercontainstheuniquevaluewhichidentifiesthisparticularnode.
EachnodeonthenetworkmusthaveauniqueNodeIDvalueatalltimes.
TheDuplicateIDbitoftheDiagnosticStatusRegisterhelpstheuserfindauniqueNodeID.
RefertotheInitializationSequencesectionforfurtherdetailontheuseoftheDUPIDbit.
ThecoreoftheCOM20020IDdoesnotwakeupuntilaNodeIDotherthanzeroiswrittenintotheNodeIDRegister.
Duringthistime,nomicrocodeisexecuted,notokensarepassedbythisnode,andnoreconfigurationsarecausedbythisnode.
Onceanon-zeroNodeIDisplacedintotheNodeIDRegister,thecorewakesupbutwillnotjointhenetworkuntiltheTXENbitoftheConfigurationRegisterisset.
WhiletheTransmitterisdisabled,theReceiverportionofthedeviceisstillfunctionalandwillprovidetheuserwithusefulinformationaboutthenetwork.
TheNodeIDRegisterdefaultstothevalue00000000uponhardwareresetonly.
6.
2.
5NextIDRegisterTheNextIDRegisterisan8-bit,read-onlyregister,accessedwhenthesub-addressbitsaresetupaccordingly(pleaserefertotheConfigurationRegisterandSUBADRRegister).
TheNextIDRegisterholdsthevalueoftheNodeIDtowhichtheCOM20020IDwillpassthetoken.
WhenusedinconjunctionwiththeTentativeIDRegister,theNextIDRegistercanprovideacompletenetworkmap.
TheNextIDRegisterisupdatedeachtimeanodeenters/leavesthenetworkorwhenanetworkreconfigurationoccurs.
EachtimethemicrosequencerupdatestheNextIDRegister,aNewNextIDinterruptisgenerated.
ThisbitisclearedbyreadingtheNextIDRegister.
Defaultvalueis00000000uponhardwareorsoftwarereset.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage29Revision12-05-06DATASHEET6.
2.
6StatusRegisterTheCOM20020IDStatusRegisterisan8-bitread-onlyregister.
Allofthebits,exceptforbits5and6,aresoftwarecompatiblewithpreviousSMSCARCNETdevices.
InpreviousSMSCARCNETdevicestheExtendedTimeoutstatuswasprovidedinbits5and6oftheStatusRegister.
IntheCOM20020ID,theCOM20020,theCOM90C66,andtheCOM90C165,COM20020-5,COM20051andCOM20051+thesebitsexistinandarecontrolledbytheConfigurationRegister.
TheStatusRegistercontentsaredefinedasinTable6.
3,butaredefineddifferentlyduringtheCommandChainingoperation.
PleaserefertotheCommandChainingsectionforthedefinitionoftheStatusRegisterduringCommandChainingoperation.
TheStatusRegisterdefaultstothevalue1XX10001uponeitherhardwareorsoftwarereset.
6.
2.
7DiagnosticStatusRegisterTheDiagnosticStatusRegistercontainssevenread-onlybitswhichhelptheusertroubleshootthenetworkornodeoperation.
VariouscombinationsofthesebitsandtheTXENbitoftheConfigurationRegisterrepresentdifferentsituations.
Allofthesebits,excepttheExcessiveNAcKbitandtheNewNextIDbit,areresettologic"0"uponreadingtheDiagnosticStatusRegisteroruponsoftwareorhardwarereset.
TheEXCNAKbitisresetbythe"PORClearFlags"commandoruponsoftwareorhardwarereset.
TheDiagnosticStatusRegisterdefaultstothevalue0000000Xuponeitherhardwareorsoftwarereset.
6.
2.
8CommandRegisterExecutionofcommandsareinitiatedbyperformingmicrocontrollerwritestothisregister.
AnycombinationsofwrittendataotherthanthoselistedinTable6.
4arenotpermittedandmayresultinincorrectchipand/ornetworkoperation.
6.
2.
9AddressPointerRegistersTheseread/writeregistersareeach8-bitswideandareusedforaddressingtheinternalRAM.
NewpointeraddressesshouldbewrittenbyfirstwritingtotheHighRegisterandthenwritingtotheLowRegisterbecausewritingtotheLowRegisterloadstheaddress.
ThecontentsoftheAddressPointerHighandLowRegistersareundefineduponhardwarereset.
WritingtoAddressPointerlowloadstheaddress.
6.
2.
10ConfigurationRegisterTheConfigurationRegisterisaread/writeregisterwhichisusedtoconfigurethedifferentmodesoftheCOM20020ID.
TheConfigurationRegisterdefaultstothevalue00011000uponhardwareresetonly.
SUBAD0andSUBAD1pointtotheselectioninRegister7.
6.
2.
11Sub-AddressRegisterThesub-addressregisterisnewtotheCOM20020ID,previouslyareservedregister.
Bits2,1and0areusedtoselectoneoftheregistersassignedtoaddress7h.
SUBAD1andSUBAD0alreadyexistintheConfigurationregisterontheCOM20020B.
TheyareexactlysameasthoseintheSub-Addressregister.
IftheSUBAD1andSUBAD0bitsintheConfigurationregisterarechanged,theSUBAD1andSUBAD0intheSub-Addressregisterarealsochanged.
SUBAD2isanewsub-addressbit.
ItIsusedtoaccessthe1newSetUpregister,SETUP2.
ThisregisterisselectedbysettingSUBAD2=1.
TheSUBAD2bitisclearedautomaticallybywritingtheConfigurationregister.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page30SMSCCOM20020IRevDDATASHEET6.
2.
12Setup1RegisterTheSetup1Registerisaread/write8-bitregisteraccessedwhentheSubAddressBitsaresetupaccordingly(seethebitdefinitionsoftheConfigurationRegister).
TheSetup1Registerallowstheusertochangethenetworkspeed(datarate)orthearbitrationspeedindependently,invoketheReceiveAllfeatureandchangethenPULSE1drivertype.
Thedataratemaybeslowedto156.
25Kbpsand/orthearbitrationspeedmaybeslowedbyafactoroftwo.
TheSetup1Registerdefaultstothevalue00000000uponhardwareresetonly.
6.
2.
13Setup2RegisterTheSetup2RegisterisnewtotheCOM20020ID.
Itisan8-bitread/writeregisteraccessedwhentheSubAddressBitsSUBAD[2:0]aresetupaccordingly(seethebitdefinitionsoftheSubAddressRegister).
Thisregistercontainsbitsforvariousfunctions.
TheCKUP1,0bitsselecttheclocktobegeneratedfromthe20MHzcrystal.
TheRBUSTMGbitisusedtoDisable/EnableFastReadfunctionforHighSpeedCPUbussupport.
TheEFbitisusedtoenablethenewtimingforcertainfunctionsintheCOM20020ID(ifEF=0,thetimingisthesameasintheCOM20020Rev.
B).
SeeAppendixA.
TheNOSYNCbitisusedtoenabletheNOSYNCfunctionduringinitialization.
Ifthisbitisreset,thelinehastobeidlefortheRAMinitializationsequencetobewritten.
Ifset,thelinedoesnothavetobeidlefortheinitializationsequencetobewritten.
SeeAppendixA,pg68.
TheRCNTM[1,0]bitsareusedtosetthetime-outperiodoftherecontimer.
Programmingthistimerforshortertimeperiodshasthebenefitofshortenednetworkreconfigurationperiods.
Thetimeperiodsshowninthetableonthefollowingpagearelimitedbyamaximumnumberofnodesinthenetwork.
Thesetime-outperiodvaluesarefor5Mbps.
Forotherdatarates,scalethetime-outperiodtimevaluesaccordingly;themaximumnodecountremainsthesame.
RCNTM1RCNTM0TIME-OUTPERIODMAXNODECOUNT00420mSUpto255nodes01105mSUpto64nodes1052.
5mSUpto32nodes1126.
25mS*Upto16nodesNote6.
3Note6.
3ThenodeIDvalue255mustexistinthenetworkforthe26.
25mStime-outtobevalid.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage31Revision12-05-06DATASHEETTable6.
3-StatusRegisterBITBITNAMESYMBOLDESCRIPTION7ReceiverInhibitedRIThisbit,ifhigh,indicatesthatthereceiverisnotenabledbecauseeitheran"EnableReceivetoPagefnn"commandwasneverissued,orapackethasbeendepositedintotheRAMbufferpagefnnasspecifiedbythelast"EnableReceivetoPagefnn"command.
Nomessageswillbereceiveduntilthiscommandisissued,andoncethemessagehasbeenreceived,theRIbitisset,therebyinhibitingthereceiver.
TheRIbitisclearedbyissuingan"EnableReceivetoPagefnn"command.
Thisbit,whenset,willcauseaninterruptifthecorrespondingbitoftheInterruptMaskRegister(IMR)isalsoset.
Whenthisbitissetandanotherstationattemptstosendapackettothisstation,thisstationwillsendaNAK.
6,5(Reserved)Thesebitsareundefined.
4PowerOnResetPORThisbit,ifhigh,indicatesthattheCOM20020IDhasbeenresetbyeitherasoftwarereset,ahardwarereset,orwriting00HtotheNodeIDRegister.
ThePORbitisclearedbythe"ClearFlags"command.
3TestTESTThisbitisintendedfortestanddiagnosticpurposes.
Itisalogic"0"undernormaloperatingconditions.
2ReconfigurationRECONThisbit,ifhigh,indicatesthattheLineIdleTimerhastimedoutbecausetheRXINpinwasidlefor41μS.
TheRECONbitisclearedduringa"ClearFlags"command.
Thisbit,whenset,willcauseaninterruptifthecorrespondingbitintheIMRisalsoset.
TheinterruptserviceroutineshouldconsistofexaminingtheMYRECONbitoftheDiagnosticStatusRegistertodeterminewhetherthereareconsecutivereconfigurationscausedbythisnode.
1TransmitterMessageAcknowledgedTMAThisbit,ifhigh,indicatesthatthepackettransmittedasaresultofan"EnableTransmitfromPagefnn"commandhasbeenacknowledged.
ThisbitshouldonlybeconsideredvalidaftertheTAbit(bit0)isset.
Broadcastmessagesareneveracknowledged.
TheTMAbitisclearedbyissuingthe"EnableTransmitfromPagefnn"command.
0TransmitterAvailableTAThisbit,ifhigh,indicatesthatthetransmitterisavailablefortransmitting.
Thisbitissetwhenthelastbyteofscheduledpackethasbeentransmittedout,oruponexecutionofa"DisableTransmitter"command.
TheTAbitisclearedbyissuingthe"EnableTransmitfromPagefnn"commandafterthenodenextreceivesthetoken.
Thisbit,whenset,willcauseaninterruptifthecorrespondingbitintheIMRisalsoset.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page32SMSCCOM20020IRevDDATASHEETTable6.
4-DiagnosticStatusRegisterBITBITNAMESYMBOLDESCRIPTION7MyReconfigurationMY-RECONThisbit,ifhigh,indicatesthatapastreconfigurationwascausedbythisnode.
ItissetwhentheLostTokenTimertimesout,andshouldbetypicallyreadfollowinganinterruptcausedbyRECON.
RefertotheImprovedDiagnosticssectionforfurtherdetail.
6DuplicateIDDUPIDThisbit,ifhigh,indicatesthatthevalueintheNodeIDRegistermatchesbothDestinationIDcharactersofthetokenandaresponsetothistokenhasoccurred.
Trailingzero'sarealsoverified.
Alogic"1"onthisbitindicatesaduplicateNodeID,thustheusershouldwriteanewvalueintotheNodeIDRegister.
ThisbitisonlyusefulforduplicateIDdetectionwhenthedeviceisoffline,thatis,whenthetransmitterisdisabled.
Whenthedeviceisonlinethisbitwillbeseteverytimethedevicegetsthetoken.
ThisbitisresetautomaticallyuponreadingtheDiagnosticStatusRegister.
RefertotheImprovedDiagnosticssectionforfurtherdetail.
5ReceiveActivityRCVACTThisbit,ifhigh,indicatesthatdataactivity(logic"1")wasdetectedontheRXINpinofthedevice.
RefertotheImprovedDiagnosticssectionforfurtherdetail.
4TokenSeenTOKENThisbit,ifhigh,indicatesthatatokenhasbeenseenonthenetwork,sentbyanodeotherthanthisone.
RefertotheImprovedDiagnosticsectionforfurtherdetail.
3ExcessiveNAKEXCNAKThisbit,ifhigh,indicatesthateither128or4NegativeAcknowledgementshaveoccurredinresponsetotheFreeBufferEnquiry.
Thisbitiscleareduponthe"PORClearFlags"command.
ReadingtheDiagnosticStatusRegisterdoesnotclearthisbit.
Thisbit,whenset,willcauseaninterruptifthecorrespondingbitintheIMRisalsoset.
RefertotheImprovedDiagnosticssectionforfurtherdetail.
2TentativeIDTENTIDThisbit,ifhigh,indicatesthataresponsetoatokenwhoseDIDmatchesthevalueintheTentativeIDRegisterhasoccurred.
ThesecondDIDandthetrailingzero'sarenotchecked.
Sinceeachnodeseeseverytokenpassedaroundthenetwork,thisfeaturecanbeusedwiththedeviceon-lineinordertobuildandupdateanetworkmap.
RefertotheImprovedDiagnosticssectionforfurtherdetail.
1NewNextIDNEWNXTIDThisbit,ifhigh,indicatesthattheNextIDRegisterhasbeenupdatedandthatanodehaseitherjoinedorleftthenetwork.
ReadingtheDiagnosticStatusRegisterdoesnotclearthisbit.
Thisbit,whenset,willcauseaninterruptifthecorrespondingbitintheIMRisalsoset.
ThebitisclearedbyreadingtheNextIDRegister.
1,0(Reserved)Thesebitsareundefined.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage33Revision12-05-06DATASHEETTable6.
5-CommandRegisterDATACOMMANDDESCRIPTION00000000ClearTransmitInterruptThiscommandisusedonlyintheCommandChainingoperation.
PleaserefertotheCommandChainingsectionfordefinitionofthiscommand.
00000001DisableTransmitterThiscommandwillcancelanypendingtransmitcommand(transmissionthathasnotyetstarted)andwillsettheTA(TransmitterAvailable)statusbittologic"1"whentheCOM20020IDnextreceivesthetoken.
00000010DisableReceiverThiscommandwillcancelanypendingreceivecommand.
IftheCOM20020IDisnotyetreceivingapacket,theRI(ReceiverInhibited)bitwillbesettologic"1"thenexttimethetokenisreceived.
Ifpacketreceptionisalreadyunderway,receptionwillruntoitsnormalconclusion.
b0fnn100EnableReceivetoPagefnnThiscommandallowstheCOM20020IDtoreceivedatapacketsintoRAMbufferpagefnnandresetstheRIstatusbittologic"0".
Thevaluesplacedinthe"nn"bitsindicatethepagethatthedatawillbereceivedinto(page0,1,2,or3).
Ifthevalueof"f"isalogic"1",anoffsetof256byteswillbeaddedtothatpagespecifiedin"nn",allowingafinerresolutionofthebuffer.
RefertotheSelectingRAMPageSizesectionforfurtherdetail.
Ifthevalueof"b"islogic"1",thedevicewillalsoreceivebroadcasts(transmissionstoIDzero).
TheRIstatusbitissettologic"1"uponsuccessfulreceptionofamessage.
00fnn011EnableTransmitfromPagefnnThiscommandpreparestheCOM20020IDtobeginatransmitsequencefromRAMbufferpagefnnthenexttimeitreceivesthetoken.
Thevaluesofthe"nn"bitsindicatewhichpagetotransmitfrom(0,1,2,or3).
If"f"islogic"1",anoffsetof256bytesisthestartofthepagespecifiedin"nn",allowingafinerresolutionofthebuffer.
RefertotheSelectingRAMPageSizesectionforfurtherdetail.
Whenthiscommandisloaded,theTAandTMAbitsareresettologic"0".
TheTAbitissettologic"1"uponcompletionofthetransmitsequence.
TheTMAbitwillhavebeensetbythistimeifthedevicehasreceivedanACKfromthedestinationnode.
TheACKisstrictlyhardwarelevel,sentbythereceivingnodebeforeitsmicrocontrollerisevenawareofmessagereception.
RefertoFigure3.
1fordetailsofthetransmitsequenceanditsrelationtotheTAandTMAstatusbits.
0000c101DefineConfigurationThiscommanddefinesthemaximumlengthofpacketsthatmaybehandledbythedevice.
If"c"isalogic"1",thedevicehandlesbothlongandshortpackets.
If"c"isalogic"0",thedevicehandlesonlyshortpackets.
000rp110ClearFlagsThiscommandresetscertainstatusbitsoftheCOM20020ID.
Alogic"1"on"p"resetsthePORstatusbitandtheEXCNAKDiagnosticstatusbit.
Alogic"1"on"r"resetstheRECONstatusbit.
00001000ClearReceiveInterruptThiscommandisusedonlyintheCommandChainingoperation.
PleaserefertotheCommandChainingsectionfordefinitionofthiscommand.
00011000StartInternalOperationThiscommandrestartsthestoppedinternaloperationafterchangingCKUP1orCKUP0bit.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page34SMSCCOM20020IRevDDATASHEETTable6.
6-AddressPointerHighRegisterBITBITNAMESYMBOLDESCRIPTION7ReadDataRDDATAThisbittellstheCOM20020IDwhetherthefollowingaccesswillbeareadorwrite.
Alogic"1"preparesthedeviceforaread,alogic"0"preparesitforawrite.
6AutoIncrementAUTOINCThisbitcontrolswhethertheaddresspointerwillincrementautomatically.
Alogic"1"onthisbitallowsautomaticincrementofthepointeraftereachaccess,whilealogic"0"disablesthisfunction.
PleaserefertotheSequentialAccessMemorysectionforfurtherdetail.
5-3(Reserved)Thesebitsareundefined.
2-0Address10-8A10-A8ThesebitsholdtheupperthreeaddressbitswhichprovideaddressestoRAM.
Table6.
7-AddressPointerLowRegisterBITBITNAMESYMBOLDESCRIPTION7-0Address7-0A7-A0Thesebitsholdthelower8addressbitswhichprovidetheaddressestoRAM.
Table6.
8-SubAddressRegisterBITBITNAMESYMBOLDESCRIPTION7-3ReservedThesebitsareundefined.
2,1,0SubAddress2,1,0SUBAD2,1,0Thesebitsdeterminewhichregisterataddress07maybeaccessed.
Thecombinationsareasfollows:SUBAD2SUBAD1SUBAD0Register000TentativeID\(Same001NodeID\asin010Setup1/Config011NextID/Register)100Setup2101Reserved110Reserved111ReservedSUBAD1andSUBAD0areexactlythesameasexistintheConfigurationRegister.
SUBAD2isclearedautomaticallybywritingtheConfigurationRegister.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage35Revision12-05-06DATASHEETTable6.
9-ConfigurationRegisterBITBITNAMESYMBOLDESCRIPTION7ResetRESETAsoftwareresetoftheCOM20020IDisexecutedbywritingalogic"1"tothisbit.
Asoftwareresetdoesnotresetthemicrocontrollerinterfacemode,nordoesitaffecttheConfigurationRegister.
TheonlyregistersthatthesoftwareresetaffectaretheStatusRegister,theNextIDRegister,andtheDiagnosticStatusRegister.
Thisbitmustbebroughtbacktologic"0"toreleasethereset.
6CommandChainingEnableCCHENThisbit,ifhigh,enablestheCommandChainingoperationofthedevice.
PleaserefertotheCommandChainingsectionforfurtherdetails.
AlowlevelonthisbitensuressoftwarecompatibilitywithpreviousSMSCARCNETdevices.
5TransmitEnableTXENWhenlow,thisbitdisablestransmissionsbykeepingnPULSE1,nPULSE2ifinnon-BackplaneMode,andnTXENpininactive.
Whenhigh,itenablestheabovesignalstobeactivatedduringtransmissions.
Thisbitdefaultslowuponreset.
ThisbitistypicallyenabledoncetheNodeIDisdetermined,andneverdisabledduringnormaloperation.
PleaserefertotheImprovedDiagnosticssectionfordetailsonevaluatingnetworkactivity.
4,3ExtendedTimeout1,2ET1,ET2Thesebitsallowthenetworktooperateoverlongerdistancesthanthedefaultmaximum2milesbycontrollingtheResponse,Idle,andReconfigurationTimes.
Allnodesshouldbeconfiguredwiththesametimeoutvaluesforpropernetworkoperation.
FortheCOM20020IDwitha20MHzcrystaloscillator,thebitcombinationsfollow:ET20011ET10101ResponseTime(μS)596.
6298.
4149.
237.
4IdleTime(μS)65632816441ReconfigTime(mS)840840840420Note:Thesevaluesarefor5MbpsandRCNTMR[1,0]=00.
ReconfigurationtimeischangedbytheRCNTMR1andRCNTMR0bits.
2BackplaneBACK-PLANEAlogic"1"onthisbitputsthedeviceintoBackplaneModesignalingwhichisusedforOpenDrainandDifferentialDriverinterfaces.
1,0SubAddress1,0SUBAD1,0Thesebitsdeterminewhichregisterataddress07maybeaccessed.
Thecombinationsareasfollows:SUBAD1SUBAD0Register00TentativeID01NodeID10Setup111NextIDSeealsotheSubAddressRegister.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page36SMSCCOM20020IRevDDATASHEETTable6.
10-Setup1RegisterBITBITNAMESYMBOLDESCRIPTION7Pulse1ModeP1MODEThisbitdeterminesthetypeofPULSE1outputdriverusedinBackplaneMode.
Whenhigh,apush/pulloutputisused.
Whenlow,anopendrainoutputisused.
Thedefaultisopendrain.
6FourNACKSFOURNACKSThisbit,whenset,willcausetheEXNACKbitintheDiagnosticStatusRegistertosetafterfourNACKstoFreeBufferEnquiryaredetectedbytheCOM20020ID.
Thisbit,whenreset,willsettheEXNACKbitafter128NACKstoFreeBufferEnquiry.
Thedefaultis128.
5ReservedDonotset.
4ReceiveAllRCVALLThisbit,whenset,allowstheCOM20020IDtoreceiveallvaliddatapacketsonthenetwork,regardlessoftheirdestinationID.
Thismodecanbeusedtoimplementanetworkmonitorwiththetransmitteron-oroff-line.
NotethatACKsareonlysentforpacketsreceivedwithadestinationIDequaltotheCOM20020ID'sprogrammednodeID.
ThisfeaturecanbeusedtoputtheCOM20020IDina'listen-only'mode,wherethetransmitterisdisabledandtheCOM20020IDisnotpassingtokens.
Defaultslow.
3,2,1ClockPrescalerBits3,2,1CKP3,2,1ThesebitsareusedtodeterminethedatarateoftheCOM20020ID.
Thefollowingtableisfora20MHzcrystal:(ClockMultiplierisbypassed)CKP300001CKP200110CKP101010DIVISOR8163264128SPEED2.
5Mbs1.
25Mbs625Kbs312.
5Kbs156.
25KbsNOTE:ThelowestdatarateachievablebytheCOM20020IDis156.
25Kbs.
Defaultsto000or2.
5Mbs.
ForClockMultiplieroutputclockspeedgreaterthan20MHz,CKP3,CKP2andCKP1mustallbezero.
0SlowArbitrationSelectSLOWARBThisbit,whenset,willdividethearbitrationclockby2.
Memorycycletimeswillincreasewhenslowarbitrationisselected.
NOTE:Forclockmultiplieroutputclockspeedsgreaterthan40MHz,SLOWARBmustbeset.
Defaultstolow.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage37Revision12-05-06DATASHEETTable6.
11-Setup2RegisterBITBITNAMESYMBOLDESCRIPTION7ReadBusTimingSelectRBUSTMGThisbitisusedtoDisable/EnabletheHighSpeedCPUReadfunctionforHighSpeedCPUbussupport.
RBUSTMG=0:Disable(Default),RBUSTMG=1:Enable.
Itdoesnotinfluencewriteoperation.
HighspeedCPUReadoperationisonlyfornon-multiplexedbus.
6ReservedThisbitisundefined.
5,4ClockMultiplierCKUP1,0Higherfrequencyclocksaregeneratedfromthe20MHzcrystalthroughtheselectionofthesetwobitsasshown.
Thisclockmultiplierispowered-downondefault.
AfterchangingtheCKUP1andCKUP0bits,theARCNETcoreoperationisstoppedandtheinternalPLLintheclockmultiplierisawakenedanditstartstogeneratethe40MHz.
ThelockouttimeoftheinternalPLLis8μSectypically.
After1mSitisnecessarytowritecommanddata'18H'tocommandregisterforre-startingtheARCNETcoreoperation.
EFbitmustbe'1'ifthedatarateisover5Mbps.
CAUTION:ChangingtheCKUP1andCKUP0bitsmustbeonetimeorlessafterreleasingahardwarereset.
CKUP1CKUP0ClockFrequency(DataRate)0020MHz(Upto2.
5Mbps)Default0140MHz(Upto5Mbps)10Reserved11ReservedNote:AfterchangingtheCKUP1orCKUP0bits,itisnecessarytowriteacommanddata'18H'tothecommandregister.
BecauseafterchangingtheCKUP[1,0]bits,theinternaloperationisstoppedtemporarily.
Thewritingofthecommandistostarttheoperation.
Theseinitializingstepsareshownbelow.
Hardwarereset(PowerON)ChangeCKUP[1,0]bitWait1mSec(waituntilstableoscillation)Writecommand'18H'(startinternaloperation)Startinitializingroutine(Executeexistingsoftware)3EnhancedFunctionsEFThisbitisusedtoenablethenewenhancedfunctionsintheCOM20020ID.
EF=0:Disable(Default),EF=1:Enable.
IfEF=0,thetimingandfunctionisthesameasintheCOM20020,RevisionB.
SeeAppendixA.
EFbitmustbe'1'ifthedatarateisover5Mbps.
EFbitshouldbe'1'fornewdesigncustomers.
EFbitshouldbe'0'forreplacementcustomers.
2NoSynchronousNOSYNCThisbitisusedtoenabletheSYNCcommandduringinitialization.
NOSYNC=0,Enable(Default)ThelinemustbeidlefortheRAMinitializationsequencetobewritten.
NOSYNC=1,Disable:)ThelinedoesnothavetobeidlefortheRAMinitializationsequencetobewritten.
SeeAppendixA.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page38SMSCCOM20020IRevDDATASHEETBITBITNAMESYMBOLDESCRIPTION1,0ReconfigurationTimer1,0RCNTM1,0Thesebitsareusedtoprogramthereconfigurationtimerasafunctionofmaximumnodecount.
Thesebitssetthetimeoutperiodofthereconfigurationtimerasshownbelow.
Thetimeoutperiodsshownarefor5Mbps.
RCNTM1RCNTM0TimeOutPeriodMaxNodeCount00420mSUpto255nodes01105mSUpto64nodes1052.
5mSUpto32nodes1126.
25mS*Upto16nodesNote*:ThenodeIDvalue255mustexistinthenetworkfor26.
25mStimeouttobevalid.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage39Revision12-05-06DATASHEETFigure6.
1-SequentialAccessOperationAddressPointerRegisterLow2Kx8RAM11DataRegister8I/OAddress04HI/OAddress03H11-BitCounterMemoryAddressBusMemoryDataBusD0-D7HighI/OAddress02HINTERNAL5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page40SMSCCOM20020IRevDDATASHEET6.
3InternalRAMTheintegrationofthe2Kx8RAMintheCOM20020IDrepresentssignificantrealestatesavings.
Themostobviousbenefitisthe48pinpackageinwhichthedeviceisnowplaced(adirectresultoftheintegrationofRAM).
Inaddition,thePCboardisnowfreeofthecumbersomeexternalRAM,externallatch,andmultiplexedaddress/databusandcontrolfunctionswhichwerenecessarytointerfacetotheRAM.
TheintegrationofRAMrepresentssignificantcostsavingsbecauseitisolatesthesystemdesignerfromthechangingcostsofexternalRAManditminimizesreliabilityproblems,assemblytimeandcosts,andlayoutcomplexity.
6.
3.
1SequentialAccessMemoryTheinternalRAMisaccessedviaapointer-basedscheme.
Ratherthaninterferingwithsystemmemory,theinternalRAMisindirectlyaccessedthroughtheAddressHighandLowPointerRegisters.
Thedataischanneledtoandfromthemicrocontrollerviathe8-bitdataregister.
Forexample:apacketintheinternalRAMbufferisreadbythemicrocontrollerbywritingthecorrespondingaddressintotheAddressPointerHighandLowRegisters(offsets02Hand03H).
NotethattheHighRegistershouldbewrittenfirst,followedbytheLowRegister,becausewritingtotheLowRegisterloadstheaddress.
Atthispointthedeviceaccessesthatlocationandplacesthecorrespondingdataintothedataregister.
Themicrocontrollerthenreadsthedataregister(offset04H)toobtainthedataatthespecifiedlocation.
IftheAutoIncrementbitissettologic"1",thedevicewillautomaticallyincrementtheaddressandplacethenextbyteofdataintothedataregister,againtobereadbythemicrocontroller.
ThisprocessiscontinueduntiltheentirepacketisreadoutofRAM.
RefertoFigure6.
1foranillustrationoftheSequentialAccessoperation.
Whenswitchingbetweenreadsandwrites,thepointermustfirstbewrittenwiththestartingaddress.
Atleastonecycletimeshouldseparatethepointerbeingloadedandthefirstread(seetimingparameters).
6.
3.
2AccessSpeedTheCOM20020IDisabletoaccommodateveryfastaccesscyclestoitsregistersandbuffers.
Arbitrationtothebufferdoesnotslowdownthecyclebecausethepointerbasedaccessmethodallowsdatatobeprefetchedfrommemoryandstoredinatemporaryregister.
Likewise,datatobewrittenisstoredinthetemporaryregisterandthenwrittentomemory.
Forsystemswhichdonotrequirequickaccesstime,thearbitrationclockmaybesloweddownbysettingbit0oftheSetup1Registerequaltologic"1".
SincetheSlowArbitrationfeaturedividestheinputclockbytwo,thedutycycleoftheinputclockmayberelaxed.
6.
4SoftwareInterfaceThemicrocontrollerinterfacestotheCOM20020IDviasoftwarebyaccessingthevariousregisters.
TheseactionsaredescribedintheInternalRegisterssection.
ThesoftwareflowforaccessingthedatabufferisbasedontheSequentialAccessscheme.
Thebasicsequenceisasfollows:DisableInterruptsWritetoPointerRegisterHigh(specifyingAuto-Incrementmode)WritetoPointerRegisterLow(thisloadstheaddress)EnableInterruptsReadorWritetheDataRegister(repeatasmanytimesasnecessarytoemptyorfillthebuffer)Thepointermaynowbereadtodeterminehowmanytransferswerecompleted.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage41Revision12-05-06DATASHEETThesoftwareflowforcontrollingtheConfiguration,NodeID,TentativeID,andNextIDregistersisgenerallylimitedtotheinitializationsequenceandthemaintenanceofthenetworkmap.
Additionally,itisnecessarytounderstandthedetailsofhowtheotherInternalRegistersareusedinthetransmitandreceivesequencesandtoknowhowtheinternalRAMbufferisproperlysetup.
Thesequenceofeventsthattietheseactionstogetherisdiscussedasfollows.
6.
4.
1SelectingRAMPageSizeDuringnormaloperation,the2Kx8ofRAMisdividedintofourpagesof512byteseach.
Thepagetobeusedisspecifiedinthe"EnableTransmit(Receive)from(to)Pagefnn"command,where"nn"specifiespage0,1,2,or3.
ThisallowstheusertohaveconstantcontrolovertheallocationofRAM.
WhentheOffsetbit"f"(bit5ofthe"EnableTransmit(Receive)from(to)Pagefnn"commandword)issettologic"1",anoffsetof256bytesisaddedtothepagespecified.
Forexample:totransmitfromthesecondhalfofpage0,thecommand"EnableTransmitfromPagefnn"(fnn=100inthiscase)isissuedbywriting00100011totheCommandRegister.
Thisallowsafinerresolutionofthebufferpageswithoutaffectingsoftwarecompatibility.
Thisschemeisusefulforapplicationswhichfrequentlyusepacketsizesof256bytesorless,especiallyformicrocontrollersystemswithlimitedmemorycapacity.
Theremainingportionsofthebufferpageswhicharenotallocatedforcurrenttransmitorreceivepacketsmaybeusedastemporarystorageforpreviousnetworkdata,packetstobesentlater,orasextramemoryforthesystem,whichmaybeindirectlyaccessed.
Ifthedeviceisconfiguredtohandlebothlongandshortpackets(see"DefineConfiguration"command),thenreceivepagesshouldalwaysbe512byteslongbecausetheuserneverknowswhatthelengthofthereceivepacketwillbe.
Inthiscase,thetransmitpagesmaybemade256byteslong,leavingatleast512bytesfreeatanygiventime.
EveniftheCommandChainingoperationisbeingused,512bytesisstillguaranteedtobefreebecauseCommandChainingonlyrequirestwopagesfortransmitandtwoforreceive(inthiscase,two256bytepagesfortransmitandtwo512bytepagesforreceive,leaving512bytesfree).
Pleasenotethatitistheresponsibilityofsoftwaretoreserve512bytesforeachreceivepageifthedeviceisconfiguredtohandlelongpackets.
TheCOM20020IDdoesnotcheckpageboundariesduringreception.
Ifthedeviceisconfiguredtohandleonlyshortpackets,thenbothtransmitandreceivepagesmaybeallocatedas256byteslong,freeingatleast1KByteatanygiventime.
EveniftheCommandChainingoperationisbeingused,1KByteisstillguaranteedtobefreebecauseCommandChainingonlyrequirestwopagesfortransmitandtwoforreceive(inthiscase,atotaloffour256bytepages,leaving1Kfree).
ThegeneralrulewhichmaybeappliedtodeterminewhereinRAMapagebeginsisasfollows:Address=(nnx512)+(fx256).
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page42SMSCCOM20020IRevDDATASHEETSIDDIDCOUNT=256-NNOTUSEDDATABYTE1DATABYTE2DATABYTEN-1DATABYTENNOTUSEDSIDDID0COUNT=512-NNOTUSEDDATABYTE1DATABYTE2DATABYTEN-1DATABYTENSHORTPACKETFORMATLONGPACKETFORMATADDRESSADDRESS012COUNT255511N=DATAPACKETLENGTHSID=SOURCEIDDID=DESTINATIONID(DID=0FORBROADCASTS)012COUNT5113Figure6.
2-RAMBufferPacketConfiguration6.
4.
2TransmitSequenceDuringatransmitsequence,themicrocontrollerselectsa256or512bytesegmentoftheRAMbufferandwritesintoit.
Theappropriatebuffersizeisspecifiedinthe"DefineConfiguration"command.
Whenlongpacketsareenabled,theCOM20020IDinterpretsthepacketaseitheralongorshortpacket,dependingonwhetherthebufferaddress2containsazeroornon-zerovalue.
TheformatofthebufferisshowninFigure6.
2.
Address0containstheSourceIdentifier(SID);Address1containstheDestinationIdentifier(DID);Address2(COUNT)contains,forshortpackets,thevalue256-N,whereNrepresentsthenumberofinformationbytesinthemessage,orforlongpackets,thevalue0,indicatingthatitisindeedalongpacket.
Inthelattercase,Address3(COUNT)wouldcontainthevalue512-N,whereNrepresentsthe5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage43Revision12-05-06DATASHEETnumberofinformationbytesinthemessage.
TheSIDinAddress0isusedbythereceivingnodetoreplytothetransmittingnode.
TheCOM20020IDputsthelocalIDinthislocation,thereforeitisnotnecessarytowriteintothislocation.
Pleasenotethatashortpacketmaycontainbetween1and253databytes,whilealongpacketmaycontainbetween257and508databytes.
Aminimumvalueof257existsonalongpacketsothattheCOUNTisexpressibleineightbits.
Thisleavesthreeexceptionpacketlengthswhichdonotfitintoeitherashortorlongpacket;packetlengthsof254,255,or256bytes.
Ifpacketsoftheselengthsmustbesent,theusermustadddummybytestothepacketinordertomakethepacketfitintoalongpacket.
Oncethepacketiswrittenintothebuffer,themicrocontrollerawaitsalogic"1"ontheTAbit,indicatingthataprevioustransmitcommandhasconcludedandanothermaybeissued.
Eachtimethemessageisloadedandatransmitcommandissued,itwilltakeavariableamountoftimebeforethemessageistransmitted,dependingonthetrafficonthenetworkandthelocationofthetokenatthetimethetransmitcommandwasissued.
TheconclusionoftheTransmitCommandwillgenerateaninterruptiftheInterruptMaskallowsit.
IfthedeviceisconfiguredfortheCommandChainingoperation,pleaseseetheCommandChainingsectionforfurtherdetailonthetransmitsequence.
OncetheTAbitbecomesalogic"1",themicrocontrollermayissuethe"EnableTransmitfromPagefnn"command,whichresetstheTAandTMAbitstologic"0".
IfthemessageisnotaBROADCAST,theCOM20020IDautomaticallysendsaFREEBUFFERENQUIRYtothedestinationnodeinordertosendthemessage.
Atthispoint,oneoffourpossibilitiesmayoccur.
Thefirstpossibilityisifafreebufferisavailableatthedestinationnode,inwhichcaseitrespondswithanACKnowledgement.
Atthispoint,theCOM20020IDfetchesthedatafromtheTransmitBufferandperformsthetransmitsequence.
Ifasuccessfultransmitsequenceiscompleted,theTMAbitandtheTAbitaresettologic"1".
Ifthepacketwasnottransmittedsuccessfully,TMAwillnotbeset.
AsuccessfultransmissionoccurswhenthereceivingnoderespondstothepacketwithanACK.
Anunsuccessfultransmissionoccurswhenthereceivingnodedoesnotrespondtothepacket.
ThesecondpossibilityisifthedestinationnoderespondstotheFreeBufferEnquirywithaNegativeAcKnowledgement.
ANAKoccurswhentheRIbitofthedestinationnodeisalogic"1".
Inthiscase,thetokenispassedonfromthetransmittingnodetothenextnode.
Thenexttimethetransmitterreceivesthetoken,itwillagaintransmitaFREEBUFFERENQUIRY.
IfaNAKisagainreceived,thetokenisagainpassedontothenextnode.
TheExcessiveNAKbitoftheDiagnosticStatusRegisterisusedtopreventanendlesssendingofFBE'sandNAK's.
IfnolimitofFBE-NAKsequencesexisted,thetransmittingnodewouldcontinueissuingaFreeBufferEnquiry,eventhoughitwouldcontinuouslyreceiveaNAKasaresponse.
TheEXCNAKbitgeneratesaninterrupt(ifenabled)inordertotellthemicrocontrollertodisablethetransmitterviathe"DisableTransmitter"command.
ThiscausesthetransmissiontobeabandonedandtheTAbittobesettoalogic"1"whenthenodenextreceivesthetoken,whiletheTMAbitremainsatalogic"0".
PleaserefertotheImprovedDiagnosticssectionforfurtherdetailontheEXCNAKbit.
ThethirdpossibilitywhichmayoccurafteraFREEBUFFERENQUIRYisissuedisifthedestinationnodedoesnotrespondatall.
Inthiscase,theTAbitissettoalogic"1",whiletheTMAbitremainsatalogic"0".
Theusershoulddeterminewhetherthenodeshouldtrytoreissuethetransmitcommand.
Thefourthpossibilityisifanon-traditionalresponseisreceived(somepatternotherthanACKorNAK,suchasnoise).
Inthiscase,thetokenisnotpassedontothenextnode,whichcausestheLostTokenTimerofthenextnodetotimeout,thusgeneratinganetworkreconfiguration.
The"DisableTransmitter"commandmaybeusedtocancelanypendingtransmitcommandwhentheCOM20020IDnextreceivesthetoken.
Normally,inanactivenetwork,thiscommandwillsettheTAstatusbittoalogic"1"whenthetokenisreceived.
Ifthe"DisableTransmitter"commanddoesnotcausetheTAbittobesetinthetimeittakesthetokentomakearoundtripthroughthenetwork,oneofthreesituationsexists.
Eitherthenodeisdisconnectedfromthenetwork,ortherearenoothernodesonthenetwork,ortheexternalreceivecircuitryhasfailed.
ThesesituationscanbedeterminedbyeitherusingtheimproveddiagnosticfeaturesoftheCOM20020IDorusinganothersoftwaretimeoutwhichisgreaterthantheworstcasetimeforaroundtriptokenpass,whichoccurswhenallnodestransmitamaximumlengthmessage.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page44SMSCCOM20020IRevDDATASHEET6.
4.
3ReceiveSequenceAreceivesequencebeginswiththeRIstatusbitbecomingalogic"1",whichindicatesthatapreviousreceptionhasconcluded.
ThemicrocontrollerwillbeinterruptedifthecorrespondingbitintheInterruptMaskRegisterissettologic"1".
Otherwise,themicrocontrollermustperiodicallychecktheStatusRegister.
Oncethemicrocontrollerisalertedtothefactthatthepreviousreceptionhasconcluded,itmayissuethe"EnableReceivetoPagefnn"command,whichresetstheRIbittologic"0"andselectsanewpageintheRAMbuffer.
Again,theappropriatebuffersizeisspecifiedinthe"DefineConfiguration"command.
Typically,thepagewhichjustreceivedthedatapacketwillbereadbythemicrocontrolleratthispoint.
Oncethe"EnableReceivetoPagefnn"commandisissued,themicrocontrollerattendstootherduties.
Thereisnowayofknowinghowlongthenewreceptionwilltake,sinceanothernodemaytransmitapacketatanytime.
Whenanothernodedoestransmitapackettothisnode,andifthe"DefineConfiguration"commandhasenabledthereceptionoflongpackets,theCOM20020IDinterpretsthepacketaseitheralongorshortpacket,dependingonwhetherthecontentofthebufferlocation2iszeroornon-zero.
TheformatofthebufferisshowninFigure6.
3.
Address0containstheSourceIdentifier(SID),Address1containstheDestinationIdentifier(DID),andAddress2contains,forshortpackets,thevalue256-N,whereNrepresentsthemessagelength,orforlongpackets,thevalue0,indicatingthatitisindeedalongpacket.
Inthelattercase,Address3containsthevalue512-N,whereNrepresentsthemessagelength.
Notethatonreception,theCOM20020IDdepositspacketsintotheRAMbufferinthesameformatthatthetransmittingnodearrangesthem,whichallowsforamessagetobereceivedandthenretransmittedwithoutrearranginganybytesintheRAMbufferotherthantheSIDandDID.
Oncethepacketisreceivedandstoredcorrectlyintheselectedbuffer,theCOM20020IDsetstheRIbittologic"1"tosignalthemicrocontrollerthatthereceptioniscomplete.
Figure6.
3–CommandChainingStatusRegisterQueueTRIRITAPORTESTRECONTMATTATMATTATRIMSBLSB5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage45Revision12-05-06DATASHEET6.
5CommandChainingTheCommandChainingoperationallowsconsecutivetransmissionsandreceptionstooccurwithouthostmicrocontrollerintervention.
Throughtheuseofadualtwo-levelFIFO,commandstobetransmittedandreceived,aswellasthestatusbits,arepipelined.
InorderfortheCOM20020IDtobecompatiblewithpreviousSMSCARCNETdevicedrivers,thedevicedefaultstothenon-chainingmode.
InordertotakeadvantageoftheCommandChainingoperation,theCommandChainingModemustbeenabledviaalogic"1"onbit6oftheConfigurationRegister.
InCommandChaining,theStatusRegisterappearsasinFigure6.
3.
ThefollowingisalistofCommandChainingguidelinesforthesoftwareprogrammer.
FurtherdetailcanbefoundintheTransmitCommandChainingandReceiveCommandChainingsections.
Thedeviceisdesignedsuchthattheinterruptserviceroutinelatencydoesnotaffectperformance.
Uptotwooutstandingtransmissionsandtwooutstandingreceptionscanbependingatanygiventime.
Thecommandsmaybegiveninanyorder.
Uptotwooutstandingtransmitinterruptsandtwooutstandingreceiveinterruptsarestoredbythedevice,alongwiththeirrespectivestatusbits.
TheInterruptMaskbitsactonTTA(RisingTransitiononTransmitterAvailable)fortransmitoperationsandTRI(RisingTransitionofReceiverInhibited)forreceiveoperations.
TTAissetuponcompletionofapackettransmissiononly.
TRIissetuponcompletionofapacketreceptiononly.
TypicallythereisnoneedtomasktheTTAandTRIbitsafterclearingtheinterrupt.
ThetraditionalTAandRIbitsarestillavailabletoreflectthepresentstatusofthedevice.
6.
5.
1TransmitCommandChainingWhentheprocessorissuesthefirst"EnableTransmittoPagefnn"command,theCOM20020IDrespondsintheusualmannerbyresettingtheTAandTMAbitstoprepareforthetransmissionfromthespecifiedpage.
TheTAbitcanbeusedtoseeifthereiscurrentlyatransmissionpending,buttheTAbitisreallymeanttobeusedinthenon-chainingmodeonly.
TheTTAbitsprovidetherelevantinformationforthedeviceintheCommandChainingmode.
IntheCommandChainingMode,atanytimeafterthefirstcommandisissued,theprocessorcanissueasecond"EnableTransmitfromPagefnn"command.
TheCOM20020IDstoresthefactthatthesecondtransmitcommandwasissued,alongwiththepagenumber.
Afterthefirsttransmissioniscompleted,theCOM20020IDupdatestheStatusRegisterbysettingtheTTAbit,whichgeneratesaninterrupt.
TheinterruptserviceroutineshouldreadtheStatusRegister.
Atthispoint,theTTAbitwillbefoundtobealogic"1"andtheTMA(TransmitMessageAcknowledge)bitwilltelltheprocessorwhetherthetransmissionwassuccessful.
AfterreadingtheStatusRegister,the"ClearTransmitInterrupt"commandisissued,thusresettingtheTTAbitandclearingtheinterrupt.
Notethatonlythe"ClearTransmitInterrupt"commandwillcleartheTTAbitandtheinterrupt.
Itisnotnecessary,however,toclearthebitortheinterruptrightawaybecausethestatusofthetransmitoperationisdoublebufferedinordertoretaintheresultsofthefirsttransmissionforanalysisbytheprocessor.
ThisinformationwillremainintheStatusRegisteruntilthe"ClearTransmitInterrupt"commandisissued.
Notethattheinterruptwillremainactiveuntilthecommandisissued,andthesecondinterruptwillnotoccuruntilthefirstinterruptisacknowledged.
TheCOM20020IDguaranteesaminimumof200nS(atEF=1)interruptinactivetimeintervalbetweeninterrupts.
TheTMAbitisalsodoublebufferedtoreflectwhethertheappropriatetransmissionwasasuccess.
TheTMAbitshouldonlybeconsideredvalidafterthecorrespondingTTAbithasbeensettoalogic"1".
TheTMAbitnevercausesaninterrupt.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page46SMSCCOM20020IRevDDATASHEETWhenthetokenisreceivedagain,thesecondtransmissionwillbeautomaticallyinitiatedafterthefirstiscompletedbyusingthestored"EnableTransmitfromPagefnn"command.
Theoperationisasifanew"EnableTransmitfromPagefnn"commandhasjustbeenissued.
AfterthefirstTransmitstatusbitsarecleared,theStatusRegisterwillagainbeupdatedwiththeresultsofthesecondtransmissionandasecondinterruptresultingfromthesecondtransmissionwilloccur.
TheCOM20020IDguaranteesaminimumof200ns(atEF=1)interruptinactivetimeintervalbeforethefollowingedge.
TheTransmitterAvailable(TA)bitoftheInterruptMaskRegisternowmasksonlytheTTAbitoftheStatusRegister,nottheTAbitasinthenon-chainingmode.
SincetheTTAbitisonlysetupontransmissionofapacket(notbyRESET),andsincetheTTAbitmayeasilyberesetbyissuinga"ClearTransmitInterrupt"command,thereisnoneedtousetheTAbitoftheInterruptMaskRegistertomaskinterruptsgeneratedbytheTTAbitoftheStatusRegister.
InCommandChainingmode,the"DisableTransmitter"commandwillcanceltheoldesttransmission.
Thispermitscancelingapacketdestinedforanodenotreadytoreceive.
Ifbothpacketsshouldbecanceled,two"DisableTransmitter"commandsshouldbeissued.
6.
5.
2ReceiveCommandChainingLiketheTransmitCommandChainingoperation,theprocessorcanissuetwoconsecutive"EnableReceivefromPagefnn"commands.
Afterthefirstpacketisreceivedintothefirstspecifiedpage,theTRIbitoftheStatusRegisterwillbesettologic"1",causinganinterrupt.
Again,theinterruptneednotbeservicedimmediately.
Typically,theinterruptserviceroutinewillreadtheStatusRegister.
Atthispoint,theRIbitwillbefoundtobealogic"1".
AfterreadingtheStatusRegister,the"ClearReceiveInterrupt"commandshouldbeissued,thusresettingtheTRIbitandclearingtheinterrupt.
Notethatonlythe"ClearReceiveInterrupt"commandwillcleartheTRIbitandtheinterrupt.
Itisnotnecessary,however,toclearthebitortheinterruptrightawaybecausethestatusofthereceiveoperationisdoublebufferedinordertoretaintheresultsofthefirstreceptionforanalysisbytheprocessor,thereforetheinformationwillremainintheStatusRegisteruntilthe"ClearReceiveInterrupt"commandisissued.
Notethattheinterruptwillremainactiveuntilthe"ClearReceiveInterrupt"commandisissued,andthesecondinterruptwillbestoreduntilthefirstinterruptisacknowledged.
Aminimumof200nS(atEF=1)interruptinactivetimeintervalbetweeninterruptsisguaranteed.
Thesecondreceptionwilloccurassoonasasecondpacketissenttothenode,aslongasthesecond"EnableReceivetoPagefnn"commandwasissued.
Theoperationisasifanew"EnableReceivetoPagefnn"commandhasjustbeenissued.
AfterthefirstReceivestatusbitsarecleared,theStatusRegisterwillagainbeupdatedwiththeresultsofthesecondreceptionandasecondinterruptresultingfromthesecondreceptionwilloccur.
IntheCOM20020ID,theReceiveInhibit(RI)bitoftheInterruptMaskRegisternowmasksonlytheTRIbitoftheStatusRegister,nottheRIbitasinthenon-chainingmode.
SincetheTRIbitisonlysetuponreceptionofapacket(notbyRESET),andsincetheTRIbitmayeasilyberesetbyissuinga"ClearReceiveInterrupt"command,thereisnoneedtousetheRIbitoftheInterruptMaskRegistertomaskinterruptsgeneratedbytheTRIbitoftheStatusRegister.
InCommandChainingmode,the"DisableReceiver"commandwillcanceltheoldestreception,unlessthereceptionhasalreadybegun.
Ifbothreceptionsshouldbecanceled,two"DisableReceiver"commandsshouldbeissued.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage47Revision12-05-06DATASHEET6.
6ResetDetails6.
6.
1InternalResetLogicTheCOM20020IDincludesspecialresetcircuitrytoguaranteesmoothoperationduringreset.
Specialcareistakentoassureproperoperationinavarietyofsystemsandmodesofoperation.
TheCOM20020IDcontainsdigitalfiltercircuitryandaSchmittTriggeronthenRESETsignaltorejectglitchesinordertoensurefault-freeoperation.
TheCOM20020IDsupportstworesetoptions;softwareandhardwarereset.
Asoftwareresetisgeneratedwhenalogic"1"iswrittentobit7oftheConfigurationRegister.
Thedeviceremainsinresetaslongasthisbitisset.
Thesoftwareresetdoesnotaffectthemicrocontrollerinterfacemodesdeterminedafterhardwarereset,nordoesitaffectthecontentsoftheAddressPointerRegisters,theConfigurationRegister,ortheSetup1Register.
AhardwareresetoccurswhenalowsignalisassertedonthenRESETinput.
Theminimumresetpulsewidthis5TXTL.
Thispulsewidthisusedbytheinternaldigitalfilter,whichfiltersshortglitchestoallowonlyvalidresetstooccur.
Uponreset,thetransmitterportionofthedeviceisdisabledandtheinternalregistersassumethosestatesoutlinedintheInternalRegisterssection.
AfterthenRESETsignalisremovedtheusermaywritetotheinternalregisters.
Sincewritinganon-zerovaluetotheNodeIDRegisterwakesuptheCOM20020IDcore,theSetup1RegistershouldbewrittenbeforetheNodeIDRegister.
OncetheNodeIDRegisteriswrittento,theCOM20020IDreadsthevalueandexecutestwowritecyclestotheRAMbuffer.
Address0iswrittenwiththedataD1Handaddress1iswrittenwiththeNodeID.
ThedatapatternD1Hwaschosenarbitrarily,andismeanttoprovideassuranceofpropermicrosequenceroperation.
6.
7InitializationSequence6.
7.
1BusDeterminationWritingtoandreadingfromanoddaddresslocationfromtheCOM20020ID'saddressspacecausestheCOM20020IDtodeterminetheappropriatebusinterface.
WhentheCOM20020IDispoweredontheinternalregistersmaybewrittento.
Sincewritinganon-zerovaluetotheNodeIDRegisterwakesupthecore,theSetup1RegistershouldbewrittentobeforetheNodeIDRegister.
Untilanon-zerovalueisplacedintotheNIDRegister,nomicrocodeisexecuted,notokensarepassedbythisnode,andnoreconfigurationsaregeneratedbythisnode.
Onceanon-zerovalueisplacedintheregister,thecorewakesup,butthenodewillnotattempttojointhenetworkuntiltheTXEnablebitoftheConfigurationRegisterisset.
BeforesettingtheTXEnablebit,thesoftwaremaymakesomedeterminations.
ThesoftwaremayfirstobservetheReceiveActivityandtheTokenSeenbitsoftheDiagnosticStatusRegistertoverifythehealthofthereceiverandthenetwork.
Next,theuniquenessoftheNodeIDvalueplacedintheNodeIDRegisterisdetermined.
TheTXEnablebitshouldstillbealogic"0"untilitisensuredthattheNodeIDisunique.
IfthisnodeIDalreadyexists,theDuplicateIDbitoftheDiagnosticStatusRegisterissetafteramaximumof420mS(or840mSiftheET1andET2bitsareotherthan1,1).
TodetermineifanothernodeonthenetworkalreadyhasthisID,theCOM20020IDcomparesthevalueintheNodeIDRegisterwiththeDID'softhetoken,anddetermineswhetherthereisaresponsetoit.
OncetheDiagnosticStatusRegisterisread,theDUPIDbitiscleared.
TheusermaythenattemptanewIDvalue,wait420mSbeforecheckingtheDuplicateIDbit,andrepeattheprocessuntilauniqueNodeIDisfound.
Atthispoint,theTXEnablebitmaybesettoallowthenodetojointhenetwork.
Oncethenodejoinsthenetwork,areconfigurationoccurs,asusual,thussettingtheMYRECONbitoftheDiagnosticStatusRegister.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page48SMSCCOM20020IRevDDATASHEETTheTentativeIDRegistermaybeusedtobuildanetworkmapofallthenodesonthenetwork,evenoncetheCOM20020IDhasjoinedthenetwork.
OnceavalueisplacedintheTentativeIDRegister,theCOM20020IDlooksforaresponsetoatokenwhoseDIDmatchestheTentativeIDRegister.
ThesoftwarecanrecordthisinformationandcontinueplacingTentativeIDvaluesintotheregistertocontinuebuildingthenetworkmap.
Acompletenetworkmapisonlyvaliduntilnodesareaddedtoordeletedfromthenetwork.
NotethatanodecannotdetecttheexistenceofthenextlogicalnodeonthenetworkwhenusingtheTentativeID.
Todeterminethenextlogicalnode,thesoftwareshouldreadtheNextIDRegister.
6.
8ImprovedDiagnosticsTheCOM20020IDallowstheusertobettermanagetheoperationofthenetworkthroughtheuseoftheinternalDiagnosticStatusRegister.
AhighlevelontheMyReconfiguration(MYRECON)bitindicatesthattheTokenReceptionTimerofthisnodeexpired,causingareconfigurationbythisnode.
AftertheReconfiguration(RECON)bitoftheStatusRegisterinterruptsthemicrocontroller,theinterruptserviceroutinewilltypicallyreadtheMYRECONbitoftheDiagnosticStatusRegister.
ReadingtheDiagnosticStatusRegisterresetstheMYRECONbit.
Successiveoccurrencesofalogic"1"ontheMYRECONbitindicatesthataproblemexistswiththisnode.
Atthatpoint,thetransmittershouldbedisabledsothattheentirenetworkisnothelddownwhilethenodeisbeingevaluated.
TheDuplicateID(DUPID)bitisusedbeforethenodejoinsthenetworktoensurethatanothernodewiththesameIDdoesnotexistonthenetwork.
OnceitisdeterminedthattheIDintheNodeIDRegisterisunique,thesoftwareshouldwritealogic"1"tobit5oftheConfigurationRegistertoenablethebasictransmitfunction.
Thisallowsthenodetojointhenetwork.
TheReceiveActivity(RCVACT)bitoftheDiagnosticStatusRegisterwillbesettoalogic"1"wheneveractivity(logic"1")isdetectedontheRXINpin.
TheTokenSeen(TOKEN)bitissettoalogic"1"wheneveranytokenhasbeenseenonthenetwork(exceptthosetokenstransmittedbythisnode).
TheRCVACTandTOKENbitsmayhelptheusertotroubleshootthenetworkorthenode.
Ifunusualeventsareoccurringonthenetwork,theusermayfinditvaluabletousetheTXENbitoftheConfigurationRegistertoqualifyevents.
DifferentcombinationsoftheRCVACT,TOKEN,andTXENbits,asshownindicatedifferentsituations:6.
8.
1NormalResults:RCVACT=1,TOKEN=1,TXEN=0:Thenodeisnotpartofthenetwork.
Thenetworkisoperatingproperlywithoutthisnode.
RCVACT=1,TOKEN=1,TXEN=1:Thenodeseesreceiveactivityandseesthetoken.
Thebasictransmitfunctionisenabled.
Networkandnodeareoperatingproperly.
MYRECON=0,DUPID=0,RCVACT=1,TXEN=0,TOKEN=1:Singlenodenetwork.
6.
8.
2AbnormalResults:RCVACT=1,TOKEN=0,TXEN=X:Thenodeseesreceiveactivity,butdoesnotseethetoken.
Eithernoothernodesexistonthenetwork,sometypeofdatacorruptionexists,themediadriverismalfunctioning,thetopologyissetupincorrectly,thereisnoiseonthenetwork,orareconfigurationisoccurring.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage49Revision12-05-06DATASHEETRCVACT=0,TOKEN=0,TXEN=1:Noreceiveactivityisseenandthebasictransmitfunctionisenabled.
Thetransmitterand/orreceiverarenotfunctioningproperly.
RCVACT=0,TOKEN=0,TXEN=0:Noreceiveactivityandbasictransmitfunctiondisabled.
Thisnodeisnotconnectedtothenetwork.
TheExcessiveNAK(EXCNAK)bitisusedtoreplaceatimeoutfunctiontraditionallyimplementedinsoftware.
ThisfunctionisnecessarytolimitthenumberoftimesasenderissuesaFBEtoanodewithnoavailablebuffer.
Whenthedestinationnoderepliesto128FBEswith128NAKsor4FBEswith4NAKs,theEXCNAKbitofthesenderisset,generatinganinterrupt.
Atthispointthesoftwaremayabandonthetransmissionviathe"DisableTransmitter"command.
ThissetstheTAbittologic"1"whenthenodenextreceivesthetoken,toallowadifferenttransmissiontooccur.
ThetimeoutvaluefortheEXNACKbit(128or4)isdeterminedbytheFOUR-NAKSbitontheSetup1Register.
TheusermaychoosetowaitformoreNAK'sbeforedisablingthetransmitterbytakingadvantageofthewraparoundcounteroftheEXCNAKbit.
WhentheEXCNAKbitgoeshigh,indicating128or4NAKs,the"PORClearFlags"commandmaybeissuedtoresetthebitsothatitwillgohighagainafteranothercountof128or4.
ThesoftwaremaycountthenumberoftimestheEXCNAKbitgoeshigh,andoncethefinalcountisreached,the"DisableTransmitter"commandmaybeissued.
TheNewNextIDbitpermitsthesoftwaretodetectthewithdrawaloradditionofnodestothenetwork.
TheTentativeIDbitallowstheusertobuildanetworkmapofthosenodesexistingonthenetwork.
Thisfeatureisusefulbecauseitminimizestheneedforhumanintervention.
WhenavalueplacedintheTentativeIDRegistermatchestheNodeIDofanothernodeonthenetwork,theTENTIDbitisset,tellingthesoftwarethatthisNODEIDalreadyexistsonthenetwork.
ThesoftwareshouldperiodicallyplacevaluesintheTentativeIDRegisterandmonitortheNewNextIDbittomaintainanupdatednetworkmap.
6.
9OscillatorTheCOM20020IDcontainscircuitrywhich,inconjunctionwithanexternalparallelresonantcrystalorTTLclock,formsanoscillator.
Ifanexternalcrystalisused,twocapacitorsareneeded(onefromeachlegofthecrystaltoground).
Noexternalresistorisrequired,sincetheCOM20020IDcontainsaninternalresistor.
Thecrystalmusthaveanaccuracyof0.
020%orbetter.
Theoscillationfrequencyrangeisfrom10MHzto20MHz.
Thecrystalmusthaveanaccuracyof0.
010%orbetterwhentheinternalclockmultiplieristurnedon.
Theoscillationfrequencymustbe20MHzwhentheinternalclockmultiplieristurnedon.
TheXTAL2sideofthecrystalmaybeloadedwithasingle74HC-typebufferinordertogenerateaclockforotherdevices.
TheusermayattachanexternalTTLclock,ratherthanacrystal,totheXTAL1signal.
Inthiscase,a390Ωpull-upresistorisrequiredonXTAL1,whileXTAL2shouldbeleftunconnected.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page50SMSCCOM20020IRevDDATASHEETChapter7OperationalDescription7.
1MaximumGuaranteedRatings*OperatingTemperatureRange0oCto+70oCStorageTemperatureRange55oCto+150oCLeadTemperature(soldering,10seconds)325oCPositiveVoltageonanypin,withrespecttogroundVDD+0.
3VNegativeVoltageonanypin,withrespecttoground.
0.
3VMaximumVDD7V*Stressesabovethoselistedmaycausepermanentdamagetothedevice.
Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.
Note:Whenpoweringthisdevicefromlaboratoryorsystempowersupplies,itisimportantthattheAbsoluteMaximumRatingsnotbeexceededordevicefailurecanresult.
Somepowersuppliesexhibitvoltagespikesor"glitches"ontheiroutputswhentheACpowerisswitchedonoroff.
Inaddition,voltagetransientsontheACpowerlinemayappearontheDCoutput.
Ifthispossibilityexistsitissuggestedthataclampcircuitbeused.
7.
2DCElectricalCharacteristicsVDD=5.
0V±10%COM20020:TA=0oCto+70oC,COM20020I:TA=-40oCto+85oCPARAMETERSYMBOLMINTYPMAXUNITCOMMENTLowInputVoltage1(AllinputsexceptA2,XTAL1,nRESET,nRD,nWR,andRXIN)HighInputVoltage1(AllinputsexceptA2,XTAL1,nRESET,nRD,nWR,andRXIN)VIL1VIH12.
00.
8VVTTLLevelsTTLLevelsLowInputVoltage2(XTAL1)HighInputVoltage2(XTAL1)VIL2VIH24.
01.
0VVTTLClockInputLowtoHighThresholdInputVoltage(A2,nRESET,nRD,nWR,andRXIN)HightoLowThresholdInputVoltage(A2,nRESET,nRD,nWR,andRXIN)VILHVIHL1.
81.
2VVSchmittTrigger,AllValuesatVDD=5V5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage51Revision12-05-06DATASHEETPARAMETERSYMBOLMINTYPMAXUNITCOMMENTLowOutputVoltage1(nPULSE1inPush/PullMode,nPULSE2,NTXEN)HighOutputVoltage1(nPULSE1inPush/PullMode,nPULSE2,nTXEN)VOL1VOH1VOH1C2.
40.
8xVDD0.
4VVISINK=4mAISOURCE=-2mAISOURCE=-200ALowOutputVoltage2(D0-D7)HighOutputVoltage2(D0-D7)VOL2VOH22.
40.
4VVISINK=16mAISOURCE=-12mALowOutputVoltage3(nINTR)HighOutputVoltage3(nINTR)VOL3VOH32.
40.
8VVISINK=24mAISOURCE=-10mALowOutputVoltage4(nPULSE1inOpen-DrainMode)VOL40.
5VISINK=48mAOpenDrainDriverDynamicVDDSupplyCurrentIDD40mA5MbpsAllOutputsOpenInputPull-upCurrent(nPULSE1inOpen-DrainMode,A1,AD0-AD2,D3-D7)InputLeakageCurrent(AllinputsexceptA1,AD0-AD2,D3-D7,XTAL1,XTAL2IPIL80200±10μAμAVIN=0.
0VVSS1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page52SMSCCOM20020IRevDDATASHEETCAPACITANCE(TA=25°C;fC=1MHz;VDD=0V)OutputandI/Opinscapacitiveloadspecifiedasfollows:PARAMETERSYMBOLMINTYPMAXUNITCOMMENTInputCapacitanceCIN5.
0pFOutputCapacitance1(AlloutputsexceptXTAL2,nPULSE1inPush/PullMode)OutputCapacitance2(nPULSE1,inBackPlaneModeOnly-OpenDrain)COUT1COUT245400pFpFMaximumCapacitiveLoadwhichcanbesupportedbyeachoutput.
0.
4VACMeasurementsaretakenatthefollowingpoints:Inputs:2.
4V1.
4V50%50%0.
4V2.
4V1.
4V0.
8VOutputs:2.
0V0.
8V2.
0VInputsaredrivenat2.
4Vforlogic"1"and0.
4Vforlogic"0"exceptXTAL1pin.
Outputsaremeasuredat2.
0Vmin.
forlogic"1"and0.
8Vmax.
forlogic"0".
tttt5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage53Revision12-05-06DATASHEETChapter8TimingDiagramsFigure8.
1–MultiplexedBus,68XX-LikeControlSignals;ReadCycleAD0-AD2,VALIDnCSt1t3t8ALEVALIDDATAt2,t6t5t4t7D3-D7DIRt9t10nDSt11t12t13t14Note2Parameterminmaxunitst1t2t3t4t5t6t7t8t9t10t11t12t13t14AddressSetuptoALELowAddressHoldfromALELownCSSetuptoALELownCSHoldfromALELowALELowtonDSLownDSLowtoValidDatanDSHightoDataHighImpedanceCycleTime(nDSLowtoNextTimeLow)DIRSetuptonDSActiveDIRHoldfromnDSInactiveALEHighWidthALELowWidthnDSLowWidthnDSHighWidth201010101504TARB*1010202060204020nSnSnSnSnSnSnSnSnSnSnSnSnSnSMUSTBE:RBUSTMGbit=0TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1TheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsNote2:ReadcycleforAddressPointerLow/HighRegistersoccurringafteranaccesstoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnDStotheleadingedgeofthenextnDS.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page54SMSCCOM20020IRevDDATASHEETFigure8.
2–MultiplexedBus,80XX-LikeControlSignals;ReadCycleAD0-AD2,VALIDnCSt1t3t8ALEVALIDDATAt2,t6t5t4t7D3-D7nRDt9t10nWRt13t11t12Note3Note2ALEHighWidthALELowWidthnRDLowWidthnRDHighWidthnWRtonRDLowParameterminmaxunitst1t2t3t4t5t6t7t8t9t10t11t12t13AddressSetuptoALELowAddressHoldfromALELownCSSetuptoALELownCSHoldfromALELowALELowtonRDLownRDLowtoValidDatanRDHightoDataHighImpedanceCycleTime(nRDLowtoNextTimeLow)201010101504TARB*4020nSnSnSnSnSnSnSnSnSnSnSnSnSMUSTBE:RBUSTMGbit=02020602020TheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsNote2:ReadcycleforAddressPointerLow/HighRegistersoccurringafterareadfromDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnRDtotheleadingedgeofthenextnRD.
Note3:ReadcycleforAddressPointerLow/HighRegistersoccurringafterawritetoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnWRtotheleadingedgeofnRD.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage55Revision12-05-06DATASHEETFigure8.
3-MultiplexedBus,68XX-LikeControlSignals;WriteCycleAD0-AD2,VALIDnCSt1t3t8ALEVALIDDATAt2,t6t5t4t7D3-D7DIRt9t10Note2t8**nDSt11t12t13t14Parameterminmaxunitst1t2t3t4t5t6t7t8t9t10t11t12t13t142010101015104TARB*101020202020nSnSnSnSnSnSnSnSnSnSnSnSnSnSAddressSetuptoALELowAddressHoldfromALELownCSSetuptoALELownCSHoldfromALELowALELowtonDSLowValidDataSetuptonDSHighDataHoldfromnDSHighDIRSetuptonDSActiveDIRHoldfromnDSInactive30ALEHighWidthALELowWidthnDSLowWidthnDSHighWidthCycleTime(nDStoNext)**TheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:AnycycleoccurringafterawritetoAddressPointerLowRegisterrequiresaminimumof4TARBfromthetrailingedgeofnDStotheleadingedgeofthenextnDS.
Note2:**TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsWritecycleforAddressPointerLowRegisteroccurringafteranaccesstoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnDStotheleadingedgeofthenextnDS.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page56SMSCCOM20020IRevDDATASHEETFigure8.
4-MultiplexedBus,80XX-LikeControlSignals;WriteCycleAD0-AD2,VALIDnCSt1t3ALEVALIDDATAt2,t6t5t4t7D3-D7Note2t8**nWRt9t10nRDt13t11t12t8Note3Parameterminmaxunitst1t2t3t4t5t6t7t8t9t10t11t12t132010101015104TARB*2020202020nSnSnSnSnSnSnSnSnSnSnSnSnSAddressSetuptoALELowAddressHoldfromALELownCSSetuptoALELownCSHoldfromALELowALELowtonDSLowValidDataSetuptonDSHighDataHoldfromnDSHigh30ALEHighWidthALELowWidthnWRLowWidthnWRHighWidthnRDtonWRLowCycleTime(nWRtoNext)**TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsTheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:AnycycleoccurringafterawritetoAddressPointerLowRegisterrequiresaminimumof4TARBfromthetrailingedgeofnWRtotheleadingedgeofthenextnWR.
Note2:**WritecycleforAddressPointerLowRegisteroccurringafterawritetoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnWRtotheleadingedgeofthenextnWR.
Note3:WritecycleforAddressPointerLowRegisteroccurringafterareadfromDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnRDtotheleadingedgeofnWR.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage57Revision12-05-06DATASHEETFigure8.
5-Non-MultiplexedBus,80XX-LikeControlSignals;ReadCycleA0-A2VALIDDATAVALIDD0-D7nCSt6t1t7t3t5t4t2nRDnWRt10t8t9Note3Note2Parameterminmaxunitst1t2t3t4t5t6t7t8t9t1015105**0nSnSnSnSAddressSetuptonRDActiveAddressHoldfromnRDInactivenCSSetuptonRDActivenCSHoldfromnRDInactiveCycleTime(nRDLowtoNextTimeLow)nRDLowtoValidDatanRDHightoDataHighImpedance4TARB*060202040**20nSnSnSnSnSnSCASE1:RBUSTMGbit=0nRDLowWidthnRDHighWidthnWRtonRDLowTARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsnCSmaybecomeactiveaftercontrolbecomesactive,buttheaccesstime(t6)willnowbe45nSmeasuredfromtheleadingedgeofnCS.
**TheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:Note2:ReadcycleforAddressPointerLow/HighRegistersoccurringafterareadfromDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnRDtotheleadingedgeofthenextnRD.
Note3:ReadcycleforAddressPointerLow/HighRegistersoccurringafterawritetoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnWRtotheleadingedgeofnRD.
**5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page58SMSCCOM20020IRevDDATASHEETFigure8.
6-Non-MultiplexedBus,80XX-LikeControlSignals;ReadCycleA0-A2VALIDDATAVALIDD0-D7nCSt6t1t7t3t5t4t2nRDnWRt10t8t9Note3Note2Parameterminmaxunitst1t2t3t4t5t6t7t8t9t10-50-50nSnSnSnSAddressSetuptonRDActiveAddressHoldfromnRDInactivenCSSetuptonRDActivenCSHoldfromnRDInactiveCycleTime(nRDLowtoNextTimeLow)nRDLowtoValidDatanRDHightoDataHighImpedance4TARB*+300100302060**20nSnSnSnSnSnSnRDLowWidthnRDHighWidthnWRtonRDLowCASE2:RBUSTMGbit=1TheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:t6ismeasuredfromthelatestactive(valid)timingamongnCS,nRD,A0-A2.
**TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsNote2:ReadcycleforAddressPointerLow/HighRegistersoccurringafterareadfromDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnRDtotheleadingedgeofthenextnRD.
Note3:ReadcycleforAddressPointerLow/HighRegistersoccurringafterawritetoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnWRtotheleadingedgeofnRD.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage59Revision12-05-06DATASHEETFigure8.
7-Non-MultiplexedBus,68XX-LikeControlSignals;ReadCycleA0-A2VALIDDATAVALIDD0-D7nCSt8t1t9t3t6t4t2nDSDIRt5t7t10t11Note2Parameterminmaxunitst1t2t3t4t5t6t715105**0nSAddressSetuptonDSActiveAddressHoldfromnDSInactivenCSSetuptonDSActivenCSHoldfromnDSInactiveDIRSetuptonDSActiveCycleTime(nDSLowtoNextTimeLow)DIRHoldfromnDSInactive4TARB*nSnSnSnSnSnSt8nSnDSLowtoValidData40**t9t10t11nSnSnSnDSHightoDataHighImpedencenDSLowWidthnDSHighWidth20101006020CASE1:RBUSTMGbit=0TheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:nCSmaybecomeactiveaftercontrolbecomesactive,buttheaccesstime(t8)willnowbe45nSmeasuredfromtheleadingedgeofnCS.
**TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsNote2:ReadcycleforAddressPointerLow/HighRegistersoccurringafteranaccesstoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnDStotheleadingedgeofthenextnDS.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page60SMSCCOM20020IRevDDATASHEETFigure8.
8-Non-MultiplexedBus,68XX-LikeControlSignals;ReadCycleA0-A2VALIDDATAVALIDD0-D7nCSt8t1t9t3t6t4t2nDSDIRt5t7t10t11Note2Parameterminmaxunitst1t2t3t4t5t6t7-50-50nSAddressSetuptonDSActiveAddressHoldfromnDSInactivenCSSetuptonDSActivenCSHoldfromnDSInactiveDIRSetuptonDSActiveCycleTime(nDSLowtoNextTimeLow)DIRHoldfromnDSInactive4TARB*+30nSnSnSnSnSnSt8nSnDSLowtoValidData60**t9t10t11nSnSnSnDSHightoDataHighImpedencenDSLowWidthnDSHighWidth201010010030CASE2:RBUSTMGbit=1TheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:**t8ismeasuredfromthelatestactive(valid)timingamongnCS,nDS,A0-A2.
TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsNote2:ReadcycleforAddressPointerLow/HighRegistersoccurringafteranaccesstoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnDStotheleadingedgeofthenextnDS.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage61Revision12-05-06DATASHEETDataHoldfromnWRHighnWRLowWidthnWRHighWidthnRDtonWRLowA0-A2VALIDDATAVALIDD0-D7nCSt6t1t7t3t4t2Note2nWRnRDt10t8t9t5Note3t5**t1t3t5t6t7t8t9t10ParameterAddressSetuptonWRActivenCSSetuptoWRActiveValidDataSetuptonWRHighmin15510202020max4TARB*30***unitsnSnSnSnSnSnSnSnSt4nCSHoldfromnWRInactive0nSt2AddressHoldfromnWRInactive10nSCycleTime(nWRtoNext)*****:nCSmaybecomeactiveaftercontrolbecomesactive,butthedatasetuptimewillnowbe30nSmeasuredfromthelaterofnCSfallingorValidDataavailable.
TheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:Note2:AnycycleoccurringafterawritetotheAddressPointerLowRegisterrequiresaminimumof4TARBfromthetrailingedgeofnWRtotheleadingedgeofthenextnWR.
TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsWritecycleforAddressPointerLowRegisteroccurringafterawritetoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnWRtotheleadingedgeofthenextnWR.
Note3:WritecycleforAddressPointerLowRegisteroccurringafterareadfromDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnRDtotheleadingedgeofnWR.
**Figure8.
9-Non-MultiplexedBus,80XX-LikeControlSignals;WriteCycle5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page62SMSCCOM20020IRevDDATASHEETA0-A2VALIDDATAVALIDD0-D7nCSt8t1t9t3t10t4t2Note2t5DIRt7nDSt11t6t6**ParameterminmaxunitsAddressSetuptonDSActiveAddressHoldfromnDSInactivenCSSetuptonDSActivenCSHoldfromnDSInactiveDIRSetuptonDSActiveCycleTime(nDStoNextTime)**DIRHoldfromnDSInactiveValidDataSetuptonDSHighDataHoldfromnDSHighnDSLowWidthnDSHighWidtht1t2t3t4t5t6t7t8t9t10t11151050104TARB*1030***102020nSnSnSnSnSnSnSnSnSnSnS***:nCSmaybecomeactiveaftercontrolbecomesactive,butthedatasetuptimewillnowbe30nSmeasuredfromthelaterofnCSfallingorValidDataavailable.
TARBistheArbitrationClockPeriodTARBisidenticaltoToprifSLOWARB=0*TARBistwiceToprifSLOWARB=1Topristheperiodofoperationclock.
ItdependsonCKUP1andCKUP0bitsTheMicrocontrollertypicallyaccessestheCOM20020oneveryothercycle.
Therefore,thecycletimespecifiedinthemicrocontroller'sdatasheetshouldbedoubledwhenconsideringback-to-backCOM20020cycles.
Note1:**Note2:AnycycleoccurringafterawritetotheAddressPointerLowRegisterrequiresaminimumof4TARBfromthetrailingedgeofnDStotheleadingedgeofthenextnDS.
WritecycleforAddressPointerLowRegistersoccurringafteranaccesstoDataRegisterrequiresaminimumof5TARBfromthetrailingedgeofnDStotheleadingedgeofthenextnDS.
Figure8.
10-Non-MultiplexedBus,68XX-LikeControlSignals;WriteCycle5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage63Revision12-05-06DATASHEETnPULSE2t1t3t7t8ParameternPULSE1,nPULSE2PulseWidthnPULSE1,nPULSE2OverlapRXINPeriodRXINInactivePulseWidthmin100-10maxunitsnSnSnPULSE1t1t6RXINActivePulseWidtht2t2nPULSE1,nPULSE2PeriodnSt1t34000+10typRXINt6t710400nTXENnSnSt2t4t5LASTBIT(400nSBITTIME)t4nTXENLowtonPULSE1Low850950nSt5BeginningofLastBitTimetonTXENHigh250350nS100t820nSNote:UseOnly2.
5MbpsFigure8.
11-NormalModeTransmitorReceiveTiming(Thesesignalsaretoandfromthehybrid)5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page64SMSCCOM20020IRevDDATASHEETnPULSE1t2t3RXINt10t11nPULSE2t5t6(InternalClk)t4Parametermintypmaxunitst2t3t4t5t6t7t8t10t11t12nPULSE1PulseWidthnPULSE1PeriodnPULSE2LowtonPULSE1LownPULSE2HighTimenPULSE2LowTimenPULSE2PeriodnPULSE2HightonTXENHighRXINActivePulseWidthRXINPeriodnSnSnSnSnSnSnSnSnS200*400*100*100*200*200*400*5050-2510t1t7nTXENt9t8LASTBIT(400nSBITTIME)t1nPULSE2HightonTXENLow-2550nS(FirstRisingEdgeonnPULSE2afterLastBitTime)t9nTXENLowtofirstnPULSE1Low**650750nSt13t12-25RXINInactivePulseWidth20nSt13BeginningLastBitTimetonTXENHigh**450nSAbovevaluesarefor2.
5Mbps.
OtherDataRatesareshownbelow.
550TDRistheDataRatePeriod*t5,t6=TDR/4*t2,t7,t10=TDR/2*t3,t11=TDR**t9=xTDR+/-50nS74**t13=xTDR+/-50nS54Figure8.
12-BackplaneModeTransmitorReceiveTiming(Thesesignalsaretoandfromthedifferentialdriverorthecable)5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage65Revision12-05-06DATASHEETt1t3ParameterInputClockHighTimeInputClockPeriodmin1025maxunitsnSnSXTAL1t1t4InputClockFrequency100t2InputClockLowTimenSt310typ10t240MHzt5FrequencyAccuracy*-200200ppmNote*:Inputclockfrequencymustbe20MHz(100ppmorbetter)tousetheinternalClockMultiplier.
+-t5isappliedtocrystaloscillaton.
4.
0V1.
0V50%ofVDDFigure8.
13-TTLInputTimingonXTAL1Pint1ParameternRESETPulseWidth***minmaxunitsnRESETt1t2nINTRHightoNextnINTRLowtypt2nINTR5TXTL*EF=0EF=1TDR**/24TXTL*Note*:TXTLisperiodofexternalXTALoscillationfrequency.
Note**:TDRisperiodofDataRate(i.
e.
at2.
5Mbps,TDR=400nS)Note***:Whenthepoweristurnedon,t1ismeasuredfromstableXTALoscillationafterVDDwasover4.
5V.
Figure8.
14-ResetandInterruptTiming5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page66SMSCCOM20020IRevDDATASHEETChapter9PackageOutlinesFigure9.
1-28PinPLCCPackageDimensionsAA1BB1CDD1D2D3EFGR.
160-.
180.
090-.
120.
013-.
021.
026-.
032.
020-.
045.
485-.
495.
450-.
456.
390-.
430.
300REF.
050BSC.
042-.
056.
042-.
048.
025-.
045DIM28LJ.
000-.
020NOTES:Alldimensionsareininches.
Circleindicatingpin1canappearonatopsurfaceasshownonthedrawingorrightaboveitonabevelededge.
1.
2.
PINNO.
1GEJD3JD1DJB1BAA1CD2FRBasePlaneSeatingPlane5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage67Revision12-05-06DATASHEETFigure9.
2-48PinTQFPPackageOutlineTable9.
1-48PinTQFPPackageParametersMINNOMINALMAXREMARKA~~1.
6OverallPackageHeightA10.
050.
100.
15StandoffA21.
351.
401.
45BodyThicknessD8.
809.
009.
20XSpanD/24.
404.
504.
601/2XSpanMeasurefromCenterlineD16.
907.
007.
10XbodySizeE8.
809.
009.
10YSpanE/24.
404.
504.
601/2YSpanMeasurefromCenterlineE16.
907.
007.
10YbodySizeH0.
09~0.
20LeadFrameThicknessL0.
450.
600.
75LeadFootLengthfromCenterlineL1~1.
00~LeadLengthe0.
50BasicLeadPitchθ0o~7oLeadFootAngleW0.
17~0.
27LeadWidthR10.
08~~LeadShoulderRadiusR20.
08~0.
20LeadFootRadiusccc~~0.
0762Coplanarity(Assemblers)ccc~~0.
08Coplanarity(TestHouse)Note1:ControllingUnit:millimeter5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page68SMSCCOM20020IRevDDATASHEETAppendixAThisappendixdescribesthefunctionoftheNOSYNCandEFbits.
NOSYNCBitTheNOSYNCbitcontrolswhetherornottheRAMinitializationsequencerequiresthelinetobeidlebyenablingordisablingtheSYNCcommandduringinitialization.
Itisdefinedasfollows:NOSYNC:Enable/DisableSYNCcommandduringinitialization.
NOSYNC=0,Enable(Default):thelinehastobeidlefortheRAMinitializationsequencetobewritten,NOSYNC=1,Disable:thelinedoesnothavetobeidlefortheRAMinitializationsequencetobewritten.
Thefollowingdiscussiondescribesthefunctionofthisbit:Duringinitialization,aftertheCPUwritestheNodeID,theCOM20020IDwillwrite"D1"hdatatoAddress000handNode-IDtoAddress001hofitsinternalRAMwithin6uS.
Thesevaluesarereadaspartofthediagnostictest.
IftheD1andNode-IDinitializationsequencecannotberead,theinitializationroutinewillreportitasadevicediagnosticfailure.
Thesewritesarecontrolledbyamicro-programwhichsometimeswaitsifthelineisactive;SYNCisthemicro-programcommandthatcausesthewait.
Whenthemicro-programwaits,theinitialRAMwritedoesnotoccur,whichcausesthediagnosticerror.
Thusinthiscase,ifthelineisnotidle,theinitializationsequencemaynotbewritten,whichwillbereportedasadevicediagnosticfailure.
However,theinitializationsequenceanddiagnosticsoftheCOM20020IDshouldbeindependentofthenetworkstatus.
Thisisaccomplishedthroughsomeadditionallogictodecodetheprogramcounter,enabledbytheNOSYNCbit.
Whenitfindsthatthemicro-programisintheinitializationroutine,itdisablestheSYNCcommand.
Inthiscase,theinitializationwillnotbeheldupbythelinestatus.
Thus,bysettingtheNOSYNCbit,thelinedoesnothavetobeidlefortheRAMinitializationsequencetobewritten.
EFBitTheEFbitcontrolsseveralmodificationstointernaloperationtimingandlogic.
Itisdefinedasfollows:EF:Enable/Disablethenewinternaloperationtimingandlogicrefinements.
EF=0:(Default)Disablethenewinternaloperationtiming(thetimingisthesameasintheCOM20020Rev.
B);EF=1:Enablethenewinternaloperationtiming.
TheEFbitcontrolsthefollowingtiming/logicrefinementsintheCOM20020ID:a)ExtendInterruptDisableTimeWhiletheinterruptisactive(nINTRpin=0),theinterruptisdisabledbywritingtheClearTx/RxinterruptandClearFlagcommandandbyreadingtheNext-IDregister.
ThisminimumdisabletimeischangedbytheDataRate.
Forexample,itis200nSat2.
5Mbpsand100nSat5Mbps.
The100nSwidthwillbetooshorttofortheInterrupttobeseen.
SettingtheEFbitwillchangetheminimumdisabletimetoalwaysbemorethan200nSeveniftheDataRateis5Mbps.
ThisisdonebychangingtheclockwhichissuppliedtotheInterruptDisablelogic.
Thefrequencyofthisclockisalwayslessthan20MHzevenifthedatarateis5Mbps.
b)SynchronizethePre-ScalarOutputThePre-Scalarisusedtochangethedatarate.
TheoutputclockisselectedbyCKP3-1bitsintheSet-Upregister.
TheCKP3-1bitsarechangedbywritingtheSet-UpregisterfromoutsidetheCPU.
It'snot5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage69Revision12-05-06DATASHEETsynchronizedbetweentheCPUandCOM20020ID.
Thus,changingtheCKP3-1timingdoesnotsynchronizewiththeinternalclocksofPre-Scalar,andchangingCKP3-1maycausespikenoisetoappearontheoutputclockline.
SettingtheEFbitwillincludeflip-flopsinsertedbetweentheConfigurationregisterandPre-ScalarforsynchronizingtheCKP3-1withPre-Scalar'sinternalclocks.
NeverchangetheCKP3-1whenthedatarateisover5Mbps.
Theymustallbezero.
c)ShortenTheWriteIntervalTimeToTheCommandRegisterTheCOM20020IDlimitsthewriteintervaltimeforcontinuouswritingtotheCommandregister.
TheminimumintervaltimeischangedbytheDataRate.
It's100nSatthe2.
5Mbpsand1.
6μSatthe156.
25Kbps.
This1.
6μSisverylongforCPU.
SettingtheEFbitwillchangetheclocksourcefromOSCKclock(8timesfrequencyofdatarate)toXTALclockwhichisnotchangedbythedatarate,suchthattheminimumintervaltimebecomes100nS.
d)EliminateTheWriteProhibitionPeriodForTheEnableTx/RxCommandsTheCOM20020IDhasawriteprohibitionperiodforwritingtheEnableTransmit/ReceiveCommands.
ThisperiodisstartedbytheTAorRIbit(StatusReg.
)returningtoHigh.
ThisprohibitionperiodiscausedbysettingtheTA/RIbitwithapulsesignal.
Itis3.
2μSat156.
25Kbps.
Thisperiodmaybeaproblemwhenusinginterruptprocessing.
TheinterruptoccurrswhentheRIbitreturnstoHigh.
TheCPUwritesthenextEnableReceiveCommandtotheotherpageimmediately.
Inthiscase,theintervaltimebetweentheinterruptandwritingCommandisshorterthan3.
2μS.
SettingtheEFbitwillcausetheTA/RIbittoreturntoHighuponreleaseofthepulsesignalforsettingtheTA/RIbit,insteadofatthestartofthepulse.
ThisisillustratedinFigure0.
1onthefollowingpage.
TheEFbitalsocontrolstheresolutionofthefollowingissuesfromtheCOM20020Rev.
B:a)NetworkMAPGenerationTentativeIDisusedforgeneratingtheNetworkMAP,butitsometimesdetectsanon-existentnode.
EverytimetheTentative-IDregisteriswritten,theeffectoftheoldTentative-IDremainsactiveforawhile,whichresultsinanincorrectnetworkmap.
Itcanbeavoidedbyacarefullycodedsoftwareroutine,butthisrequirestheprogrammertohavedeepknowledgeofhowtheCOM20020IDworks.
Duplicate-IDismainlyusedforgeneratingtheNetworkMAP.
ThishasthesameissueasTentative-ID.
AminorlogicchangeclearsalltheremainingeffectsoftheoldTentative-IDandtheoldDuplicate-ID,whentheCOM20020IDdetectsawriteoperationtoTentative-IDorNode-IDregister.
Withthischange,programmerscanusetheTentative-IDorDuplicate-IDforgeneratingthenetworkMAPwithoutanyissues.
ThischangeisEnabled/DisabledbytheEFbit.
b)MaskRegisterResetTheMaskregisterisresetbyasoftresetintheCOM20020Rev.
A,butisnotresetinRev.
B.
TheMaskregisterisrelatedtotheStatusandDiagnosticregister,soitshouldberesetbyasoftreset.
Otherwise,everytimethesoftresethappens,theCOM20020Rev.
BgeneratesanunnecessaryinterruptsincethestatusbitsRIandTAarebacktoonebythesoftreset.
ThisisresolvedbychangingthelogictoresettheMaskregisterbothbythehardresetandbythesoftreset.
ThesoftresetisactivatedbytheNode-IDregistergoingto00horbytheRESETbitgoingtoHighintheConfigurationregister.
ThissolutionisEnabled/DisabledbytheEFbit.
5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page70SMSCCOM20020IRevDDATASHEETTx/RxcompletedTA/RIbitSettingPulsenINTRpinprohibitionperiodEF=1Tx/RxcompletedTA/RIbitSettingPulsenINTRpinEF=0Figure0.
1-EffectoftheEFBitontheTA/RIBit5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetSMSCCOM20020IRevDPage71Revision12-05-06DATASHEETAppendixB-ExampleofInterfaceCircuitDiagramtoISABusISABusAENSA15-SA4SD7-SD0nIORnIOWSA2-SA0IRQmnIOCS16DRQnnDACKTCnREFRESHRESETDRV1212bitComparatorsLS688x2nGPP=QQI/OAddressSeeting(DIPSwitches)16bitBusTransceiversLS245ABDIRnG3D7-D0nRDnWRA2-A0nINTRnRESETnCS83Schmitt-TriggerBuffer12COM200208A5MbpsARCNET(ANSI878.
1)Controllerwith2Kx8On-ChipRAMDatasheetRevision12-05-06Page72SMSCCOM20020IRevDDATASHEETAppendixC-SoftwareIdentificationoftheCOM20020RevB,RevCandRevDInordertoproperlywritesoftwaretoworkwiththeCOM20020RevB,CandDitisnecessarytobeabletoidentifythedifferentrevisionsofthepart.
ToidentifytheCOM20020Revisionfollowthefollowingprocedure:1.
Write0x98toRegister-6(Address=6)2.
Write0x02toRegister-5(Address=5)3.
ReadRegister-6*IfthevaluereadfromRegister-6is0x98thenthepartisaCOM20020RevBorearlier*IfthevaluereadfromRegister-6is0x9Athengotonextstepbelow4.
Write0x80toRegister-55.
ReadRegister-5*IfthevaluereadfromRegister-5is0x00thenthepartisaCOM20020RevC*IfthevaluereadfromRegister-5is0x80thenthepartisaCOM20020RevDMouserElectronicsAuthorizedDistributorClicktoViewPricing,Inventory,Delivery&LifecycleInformation:Microchip:COM20020I-DZD-TRCOM20020I-HTCOM20020I-DZD