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JitterCleanerandClockGeneratorwith6Differentialor13LVCMOSOutputsDataSheetAD9524Rev.
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analog.
comFEATURESOutputfrequency:250MHz200mVp-pCapacitivecouplingrequired;canaccommodatesingle-endedinputbyacgroundingofunusedinput;theinstantaneousvoltageoneitherpinmustnotexceedthe1.
8VdcsupplyrailsDifferentialInputResistance4.
8kDifferentialInputCapacitance1pFDutyCycleDutycycleboundsaresetbypulsewidthhighandpulsewidthlowPulseWidthLow1nsPulseWidthHigh1nsCMOSMODESINGLE-ENDEDINPUTInputFrequencyRange250MHzInputHighVoltage1.
6VInputLowVoltage0.
52VInputThresholdVoltage1.
0VWhenaccouplingtotheinputreceiver,theusermustdcbiastheinputto1V;thesingle-endedCMOSinputis3.
3VcompatibleDataSheetAD9524Rev.
F|Page7of56ParameterMinTypMaxUnitTestConditions/CommentsInputCapacitance1pFDutyCycleDutycycleboundsaresetbypulsewidthhighandpulsewidthlowPulseWidthLow1.
6nsPulseWidthHigh1.
6nsOSC_CTRLOUTPUTCHARACTERISTICSTable5.
ParameterMinTypMaxUnitTestConditions/CommentsOUTPUTVOLTAGEHighVDD3_PLL10.
15VRLOAD>20kLow150mVREF_TESTINPUTCHARACTERISTICSTable6.
ParameterMinTypMaxUnitTestConditions/CommentsREF_TESTINPUTInputFrequencyRange250MHzInputHighVoltage2.
0VInputLowVoltage0.
8VPLL1CHARACTERISTICSTable7.
ParameterMinTypMaxUnitTestConditions/CommentsPLL1FIGUREOFMERIT(FOM)226dBc/HzMAXIMUMPFDFREQUENCYHighistheinitialPLL1antibacklashpulsewidthsetting.
TheusermustprogramRegister0x019[4]=1btoenableSPIcontroloftheantibacklashpulsewidthtothesettingdefinedinRegister0x019[3:2]andTable40.
AntibacklashPulseWidthMinimum130MHzLow90MHzHigh65MHzMaximum45MHzPLL1OUTPUTCHARACTERISTICSTable8.
Parameter1MinTypMaxUnitTestConditions/CommentsMAXIMUMOUTPUTFREQUENCY250MHzRise/FallTime(20%to80%)387665ps15pFloadDutyCycle455055%f=250MHzOUTPUTVOLTAGEHIGHOutputdriverstaticVDD3_PLL10.
25VLoadcurrent=10mAVDD3_PLL10.
1VLoadcurrent=1mAOUTPUTVOLTAGELOWOutputdriverstatic0.
2VLoadcurrent=10mA0.
1VLoadcurrent=1mA1CMOSdriverstrength=strong(seeTable53).
AD9524DataSheetRev.
F|Page8of56DISTRIBUTIONOUTPUTCHARACTERISTICS(OUT0,OUT0TOOUT5,OUT5)Dutycycleperformanceisspecifiedwiththeinvertdividerbitsetto1,andthedividerphasebitssetto0.
5.
(Forexample,forChannel0,0x196[7]=1and0x198[7:2]=000001.
)OutputVoltageReferenceVDDinTable9referstothe3.
3VsupplyVDD3_OUT[x:y]supply.
Table9.
ParameterMinTypMaxUnitTestConditions/CommentsLVPECLMODE1MaximumOutputFrequency1GHzMinimumVCO/maximumdividersRiseTime/FallTime(20%to80%)117147ps100terminationacrossoutputpairDutyCycle475052%f<500MHz434852%f=500MHzto800MHz404954%f=800MHzto1GHzDifferentialOutputVoltageMagnitude643775924mVVoltageacrosspins;outputdriverstaticCommon-ModeOutputVoltageVDD1.
5VDD1.
4VDD1.
25VOutputdriverstaticSCALEDHSTLMODE,16mAMaximumOutputFrequency1GHzMinimumVCO/maximumdividersRiseTime/FallTime(20%to80%)112141ps100terminationacrossoutputpairDutyCycle475052%f<500MHz444851%f=500MHzto800MHz404954%f=800MHzto1GHzDifferentialOutputVoltageMagnitude1.
31.
61.
7VVoltageacrosspins,outputdriverstatic;nominalsupplySupplySensitivity0.
6mV/mVChangeinoutputswingvs.
VDD3_OUT[x:y](ΔVOD/ΔVDD3)Common-ModeOutputVoltageVDD1.
76VDD1.
6VDD1.
42VLVDSMODE,3.
5mAMaximumOutputFrequency1GHzRiseTime/FallTime(20%to80%)138161ps100terminationacrossoutputpairDutyCycle485153%f<500MHz434953%f=500MHzto800MHz414955%f=800MHzto1GHzDifferentialOutputVoltageMagnitudeBalanced247454mVVoltageacrosspins;outputdriverstaticUnbalanced50mVAbsolutedifferencebetweenvoltagemagnitudeofnormalpinandinvertedpinCommon-ModeOutputVoltage1.
1251.
375VOutputdriverstaticCommon-ModeDifference50mVVoltagedifferencebetweenoutputpins;outputdriverstaticShort-CircuitOutputCurrent3.
524mAOutputdriverstaticCMOSMODEMaximumOutputFrequency250MHzRiseTime/FallTime(20%to80%)387665ps15pFloadDutyCycle455055%f=250MHzOutputVoltageHighOutputdriverstaticVDD0.
25VLoadcurrent=10mAVDD0.
1VLoadcurrent=1mAOutputVoltageLowOutputdriverstatic0.
2VLoadcurrent=10mA0.
1VLoadcurrent=1mA1SeetheMultimodeOutputDriverssection.
DataSheetAD9524Rev.
F|Page9of56TIMINGALIGNMENTCHARACTERISTICSTable10.
ParameterMinTypMaxUnitTestConditions/CommentsOUTPUTTIMINGSKEWDelayoffonalloutputs;maximumdeviationbetweenrisingedgesofoutputs;alloutputsareon,unlessotherwisenoted.
BetweenLVPECL,HSTL,andLVDSOutputs38234psBetweenCMOSOutputs100300psSingle-endedtruephasehigh-ZmodeAdjustableDelay063StepsResolutionstep;forexample,8*0.
5/1GHzResolutionStep500psperiodof1GHzZeroDelayBetweenInputClockEdgeonREFAorREFBtoZD_INInputClockEdge,ExternalZeroDelayMode150500psPLL1settings:PFD=7.
68MHz,ICP=63.
5A,RZERO=10k,antibacklashpulsewidthisatmaximum,BW=40Hz,REFAandZD_INaresettodifferentialmodeJITTERANDNOISECHARACTERISTICSTable11.
ParameterMinTypMaxUnitTestConditions/CommentsOUTPUTABSOLUTERMSTIMEJITTERApplicationexamplebasedonatypicalsetup(seeTable3);f=122.
88MHzLVPECLMode,HSTLMode,LVDSMode125fsIntegratedBW=200kHzto5MHz136fsIntegratedBW=200kHzto10MHz169fsIntegratedBW=12kHzto20MHz212fsIntegratedBW=10kHzto61MHz223fsIntegratedBW=1kHzto61MHzPLL2CHARACTERISTICSTable12.
ParameterMinTypMaxUnitTestConditions/CommentsVCO(ONCHIP)FrequencyRange36004000MHzGain45MHz/VPLL2FIGUREOFMERIT(FOM)226dBc/HzMAXIMUMPFDFREQUENCYHighistheinitialPLL1antibacklashpulsewidthsetting.
TheusermustprogramRegister0x019[4]=1btoenableSPIcontroloftheantibacklashpulsewidthtothesettingdefinedinRegister0x0F2[3:2]andTable47.
AntibacklashPulseWidthMinimum259MHzLow200MHzHigh135MHzMaximum80MHzAD9524DataSheetRev.
F|Page10of56LOGICINPUTPINS—PD,SYNC,RESET,EEPROM_SEL,REF_SELTable13.
ParameterMinTypMaxUnitTestConditions/CommentsVOLTAGEInputHigh2.
0VInputLow0.
8VINPUTLOWCURRENT±80±250ATheminussignindicatesthat,duetotheinternalpull-upresistor,currentisflowingoutoftheAD9524CAPACITANCE3pFRESETTIMINGPulseWidthLow50nsInactivetoStartofRegisterProgramming100nsSYNCTIMINGPulseWidthLow1.
5nsHighspeedclockisCLKinputsignalSTATUSOUTPUTPINS—STATUS1,STATUS0Table14.
ParameterMinTypMaxUnitTestConditions/CommentsVOLTAGEOutputHigh2.
94VOutputLow0.
4VSERIALCONTROLPORT—SPIMODETable15.
ParameterMinTypMaxUnitTestConditions/CommentsCS(INPUT)CShasaninternal40kpull-upresistorVoltageInputLogic12.
0VInputLogic00.
8VCurrentInputLogic130AInputLogic0110ATheminussignindicatesthat,duetotheinternalpull-upresistor,currentisflowingoutoftheAD9524InputCapacitance2pFSCLK(INPUT)INSPIMODESCLKhasaninternal40kpull-downresistorinSPImodebutnotinI2CmodeVoltageInputLogic12.
0VInputLogic00.
8VCurrentInputLogic1240AInputLogic01AInputCapacitance2pFSDIO(WHENINPUTISINBIDIRECTIONALMODE)VoltageInputLogic12.
0VInputLogic00.
8VCurrentInputLogic11AInputLogic01AInputCapacitance2pFDataSheetAD9524Rev.
F|Page11of56ParameterMinTypMaxUnitTestConditions/CommentsSDIO,SDO(OUTPUTS)OutputLogic1Voltage2.
7VOutputLogic0Voltage0.
4VTIMINGClockRate(SCLK,1/tSCLK)25MHzPulseWidthHigh,tHIGH8nsPulseWidthLow,tLOW12nsSDIOtoSCLKSetup,tDS3.
3nsSCLKtoSDIOHold,tDH0nsSCLKtoValidSDIOandSDO,tDV14nsCStoSCLKSetup,tS10nsCStoSCLKSetupandHold,tS,tC0nsCSMinimumPulseWidthHigh,tPWH6nsSERIALCONTROLPORT—ICMODEVDD=VDD3_REF,unlessotherwisenoted.
Table16.
ParameterMinTypMaxUnitTestConditions/CommentsSDA,SCL(WHENINPUTTINGDATA)InputLogic1Voltage0.
7*VDDVInputLogic0Voltage0.
3*VDDVInputCurrentwithanInputVoltageBetween0.
1*VDDand0.
9*VDD10+10AHysteresisofSchmittTriggerInputs0.
015*VDDVPulseWidthofSpikesThatMustBeSuppressedbytheInputFilter,tSPIKE50nsSDA(WHENOUTPUTTINGDATA)OutputLogic0Voltageat3mASinkCurrent0.
4VOutputFallTimefromVIHMINtoVILMAXwithaBusCapacitancefrom10pFto400pF20+0.
1CB1250nsTIMINGNotethatallI2CtimingvaluesarereferredtoVIHMIN(0.
3*VDD)andVILMAXlevels(0.
7*VDD)ClockRate(SCL,fI2C)400kHzBusFreeTimeBetweenaStopandStartCondition,tIDLE1.
3sSetupTimeforaRepeatedStartCondition,tSET;STR0.
6sHoldTime(Repeated)StartCondition,tHLD;STR0.
6sAfterthisperiod,thefirstclockpulseisgeneratedSetupTimeforStopCondition,tSET;STP0.
6sLowPeriodoftheSCLClock,tLOW1.
3sHighPeriodoftheSCLClock,tHIGH0.
6sSCL,SDARiseTime,tRISE20+0.
1CB1300nsSCL,SDAFallTime,tFALL20+0.
1CB1300nsDataSetupTime,tSET;DAT100nsDataHoldTime,tHLD;DAT100880nsThisisaminordeviationfromtheoriginalICspecificationof0nsminimum2CapacitiveLoadforEachBusLine,CB1400pF1CBisthecapacitanceofonebuslineinpicofarads(pF).
2AccordingtotheoriginalI2Cspecification,anI2Cmastermustalsoprovideaminimumholdtimeof300nsfortheSDAsignaltobridgetheundefinedregionoftheSCLfallingedge.
AD9524DataSheetRev.
F|Page12of56ABSOLUTEMAXIMUMRATINGSTable17.
ParameterRatingVDD3_PLL1,VDD3_PLL2,VDD3_REF,VDD3_OUT,LDO_VCOtoGND0.
3Vto+3.
6VREFA,REFA,REFIN,REFB,REFBtoGND0.
3Vto+3.
6VSCLK/SCL,SDIO/SDA,SDO,CStoGND0.
3Vto+3.
6VOUT0,OUT0,OUT1,OUT1,OUT2,OUT2,OUT3,OUT3,OUT4,OUT4,OUT5,OUT5,toGND0.
3Vto+3.
6VSYNC,RESET,PDtoGND0.
3Vto+3.
6VSTATUS0,STATUS1toGND0.
3Vto+3.
6VSP0,SP1,EEPROM_SELtoGND0.
3Vto+3.
6VVDD1.
8_OUT,LDO_PLL1,LDO_PLL2toGND2VStorageTemperatureRange65°Cto+150°CLeadTemperature(10sec)300°CStressesatorabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetotheproduct.
Thisisastressratingonly;functionaloperationoftheproductattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthisspecificationisnotimplied.
Operationbeyondthemaximumoperatingconditionsforextendedperiodsmayaffectproductreliability.
THERMALRESISTANCEθJAisspecifiedfortheworst-caseconditions,thatis,adevicesolderedinacircuitboardforsurface-mountpackages.
Table18.
ThermalResistancePackageTypeAirflowVelocity(m/sec)θJA1,2θJC1,3θJB1,4ΨJT1,2Unit48-LeadLFCSP,7mm*7mm026.
11.
713.
80.
2°C/W1.
022.
80.
2°C/W2.
520.
40.
3°C/W1PerJEDEC51-7,plusJEDEC51-52S2Ptestboard.
2PerJEDECJESD51-2(stillair)orJEDECJESD51-6(movingair).
3PerMIL-Std883,Method1012.
1.
4PerJEDECJESD51-8(stillair).
Forinformationaboutpowerdissipation,refertothePowerDissipationandThermalConsiderationssection.
ESDCAUTIONDataSheetAD9524Rev.
F|Page13of56PINCONFIGURATIONANDFUNCTIONDESCRIPTIONS1234567242322212019181716151413444546474843424140393837TOPVIEW(NottoScale)AD95242526272829303132333435368910111209081-002REFAREFAREFBREFBLF1_EXT_CAPOSC_CTRLOSC_INOSC_INLF2_EXT_CAPLDO_PLL2VDD3_PLL2LDO_VCOSYNCVDD3_REFCSSCLK/SCLSDIO/SDASDOOUT5OUT5VDD3_OUT[4:5]OUT4OUT4VDD1.
8_OUT[4:5]VDD1.
8_OUT[2:3]OUT2OUT2VDD3_OUT[2:3]OUT3OUT3EEPROM_SELPDRESETREF_TESTPLL1_OUTLDO_PLL1VDD3_PLL1REF_SELZD_INZD_INVDD1.
8_OUT[0:1]OUT0OUT0VDD3_OUT[0:1]OUT1OUT1STATUS0/SP0STATUS1/SP1NOTES1.
PINSLABELEDNCCANBEALLOWEDTOFLOAT,BUTITISBETTERTOCONNECTTHESEPINSTOGROUND.
AVOIDROUTINGHIGHSPEEDSIGNALSTHROUGHTHESEPINSBECAUSENOISECOUPLINGMAYRESULT.
ONEXISTINGPCBDESIGNS,ITISACCEPTABLETOLEAVEPIN42CONNECTEDTO1.
8VSUPPLY.
2.
THEEXPOSEDPADDLEISTHEGROUNDCONNECTIONONTHECHIP.
ITMUSTBESOLDEREDTOTHEANALOGGROUNDOFTHEPCBTOENSUREPROPERFUNCTIONALITYANDHEATDISSIPATION,NOISE,ANDMECHANICALSTRENGTHBENEFITS.
Figure2.
PinConfigurationTable19.
PinFunctionDescriptionsPinNo.
MnemonicType1Description1REFAIReferenceClockInputA.
AlongwithREFA,thispinisthedifferentialinputforthePLLreference.
Alternatively,thispincanbeprogrammedasasingle-ended3.
3VCMOSinput.
2REFAIComplementaryReferenceClockInputA.
AlongwithREFA,thispinisthedifferentialinputforthePLLreference.
Alternatively,thispincanbeprogrammedasasingle-ended3.
3VCMOSinput.
3REFBIReferenceClockInputB.
AlongwithREFB,thispinisthedifferentialinputforthePLLreference.
Alternatively,thispincanbeprogrammedasasingle-ended3.
3VCMOSinput.
4REFBIComplementaryReferenceClockInputB.
AlongwithREFB,thispinisthedifferentialinputforthePLLreference.
Alternatively,thispincanbeprogrammedasasingle-ended3.
3VCMOSinput.
5LF1_EXT_CAPOPLL1ExternalLoopFilterCapacitor.
Connectaloopfiltercapacitortothispinandtoground.
6OSC_CTRLOOscillatorControlVoltage.
Connectthispintothevoltagecontrolpinoftheexternaloscillator.
7OSC_INIPLL1OscillatorInput.
AlongwithOSC_IN,thispinisthedifferentialinputforthePLLreference.
Alternatively,thispincanbeprogrammedasasingle-ended3.
3VCMOSinput.
8OSC_INIComplementaryPLL1OscillatorInput.
AlongwithOSC_IN,thispinisthedifferentialinputforthePLLreference.
Alternatively,thispincanbeprogrammedasasingle-ended3.
3VCMOSinput.
9LF2_EXT_CAPOPLL2ExternalLoopFilterCapacitorConnection.
ConnectacapacitortothispinandLDO_VCO.
10LDO_PLL2P/OLDODecouplingPinforPLL21.
8VInternalRegulator.
Connecta0.
47μFdecouplingcapacitorfromthispintoground.
Notethatforbestperformance,theLDObypasscapacitormustbeplacedincloseproximitytothedevice.
11VDD3_PLL2P3.
3VSupplyforPLL2.
12LDO_VCOP/O2.
5VLDOInternalRegulatorDecouplingPinforVCO.
Connecta0.
47μFdecouplingcapacitorfromthispintoground.
Notethat,forbestperformance,theLDObypasscapacitormustbeplacedincloseproximitytothedevice.
13SYNCIManualSynchronization.
Thispininitiatesamanualsynchronizationandhasaninternal40kΩpull-upresistor.
14VDD3_REFP3.
3VSupplyforOutputClockDriversReference.
15CSISerialControlPortChipSelect,ActiveLow.
Thispinhasaninternal40kΩpull-upresistor.
AD9524DataSheetRev.
F|Page14of56PinNo.
MnemonicType1Description16SCLK/SCLISerialControlPortClockSignalforSPIMode(SCLK)orI2CMode(SCL).
Dataclockforserialprogramming.
Thispinhasaninternal40kpull-downresistorinSPImodebutishighimpedanceinICmode.
17SDIO/SDAI/OSerialControlPortBidirectionalSerialDataIn/DataOutforSPIMode(SDIO)orICMode(SDA).
18SDOOSerialDataOutput.
Usethispintoreaddatain4-wiremode(highimpedancein3-wiremode).
Thereisnointernalpull-up/pull-downresistoronthispin.
19OUT5OComplementaryClockOutput5.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
20OUT5OClockOutput5.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
21VDD3_OUT[4:5]P3.
3VSupplyforOutput4andOutput5ClockDrivers.
22OUT4OComplementaryClockOutput4.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
23OUT4OClockOutput4.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
24VDD1.
8_OUT[4:5]P1.
8VSupplyforOutput4andOutput5ClockDividers.
25REF_TESTITestInputtoPLL1PhaseDetector.
26RESETIDigitalInput,ActiveLow.
Resetsinternallogictodefaultstates.
Thispinhasaninternal40kpull-upresistor.
27PDChipPower-Down,ActiveLow.
Thispinhasaninternal40kpull-upresistor.
28EEPROM_SELIEEPROMSelect.
SettingthispinhighselectstheregistervaluesstoredintheinternalEEPROMtobeloadedatresetand/orpower-up.
SettingthispinlowcausestheAD9524toloadthehard-codeddefaultregistervaluesatpower-up/reset.
Thispinhasaninternal40kpull-downresistor.
29OUT3OComplementaryClockOutput3.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
30OUT3OSquareWaveClockingOutput3.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
31VDD3_OUT[2:3]P3.
3VSupplyOutput2andSupplyOutput3ClockDrivers.
32OUT2OComplementaryClockOutput2.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
33OUT2OClockOutput2.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
34VDD1.
8_OUT[2:3]P1.
8VSupplyforOutput2andOutput3ClockDividers.
35STATUS1/SP1I/OLockDetectandOtherStatusSignals(STATUS1)/I2CAddress(SP1).
36STATUS0/SP0I/OLockDetectandOtherStatusSignals(STATUS0)/I2CAddress(SP0).
37OUT1OComplementaryClockOutput1.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
38OUT1OClockOutput1.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
39VDD3_OUT[0:1]P3.
3VSupplyOutput0andSupplyOutput1ClockDrivers.
40OUT0OComplementaryClockOutput0.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
41OUT0OClockOutput0.
ThispincanbeconfiguredasonesideofadifferentialLVPECL/LVDS/HSTLoutputorasasingle-endedCMOSoutput.
42VDD1.
8_OUT[0:1]P1.
8VSupplyforOutput0andOutput1ClockDividers.
43ZD_INIExternalZeroDelayClockInput.
AlongwithZD_IN,thispinisthedifferentialinputforthePLLreference.
Alternatively,thispincanbeprogrammedasasingle-ended3.
3VCMOSinput.
44ZD_INIComplementaryExternalZeroDelayClockInput.
AlongwithZD_IN,thispinisthedifferentialinputforthePLLreference.
Alternatively,thispincanbeprogrammedasasingle-ended3.
3VCMOSinput.
45REF_SELIReferenceInputSelect.
Thispinhasaninternal40kpull-downresistor.
46PLL1_OUTOSingle-EndedCMOSOutputfromPLL1.
ThispinhassettingsforweakandstronginRegister0x1BA,Bit4(seeTable53).
47LDO_PLL1P/O1.
8VInternalLDORegulatorDecouplingPinforPLL1.
Connecta0.
47Fdecouplingcapacitorfromthispintoground.
Notethat,forbestperformance,theLDObypasscapacitormustbeplacedincloseproximitytothedevice.
48VDD3_PLL1P3.
3VSupplyPLL1.
UsethesamesupplyasVCXO.
EPEP,GNDGNDExposedPaddle.
Theexposedpaddleisthegroundconnectiononthechip.
ItmustbesolderedtotheanaloggroundofthePCBtoensureproperfunctionalityandheatdissipation,noise,andmechanicalstrengthbenefits.
1P=power,I=input,O=output,I/O=input/output,P/O=power/output,GND=ground.
DataSheetAD9524Rev.
F|Page15of56TYPICALPERFORMANCECHARACTERISTICSfVCXO=122.
88MHz,REFAdifferentialat30.
72MHz,fVCO=3686.
4MHz,anddoublerisoff,unlessotherwisenoted.
0102030405060020040060080010001200CURRENT(mA)FREQUENCY(MHz)HSTL=16mAHSTL=8mA09081-003Figure3.
VDD3_OUT[x:y]Current(Typical)vs.
Frequency;HSTLMode,16mAand8mA051015202530354045020040060080010001200CURRENT(mA)FREQUENCY(MHz)LVDS=3.
5mALVDS=7mA09081-004Figure4.
VDD3_OUT[x:y]Current(Typical)vs.
Frequency;LVDSMode,7mAand3.
5mA051015202530354045020040060080010001200CURRENT(mA)FREQUENCY(MHz)09081-005Figure5.
VDD3_OUT[x:y]Current(Typical)vs.
Frequency,LVPECLMode0100200300400500CURRENT(mA)FREQUENCY(MHz)10pF20pF0510152025303509081-0062pFFigure6.
VDD3_OUT[x:y]Current(Typical)vs.
Frequency;CMOSMode,20pF,10pF,and2pFLoad00.
51.
01.
52.
02.
53.
03.
5020040060080010001200DIFFERENTIALSWING(Vp-p)FREQUENCY(MHz)HSTL=8mAHSTL=16mA09081-007Figure7.
DifferentialVoltageSwingvs.
Frequency;HSTLMode,16mAand8mA00.
20.
40.
60.
81.
01.
21.
41.
6020040060080010001200DIFFERENTIALSWING(Vp-p)FREQUENCY(MHz)09081-008Figure8.
DifferentialVoltageSwingvs.
Frequency,LVPECLModeAD9524DataSheetRev.
F|Page16of5600.
20.
40.
60.
81.
01.
21.
4020040060080010001200DIFFERENTIALSWING(Vp-p)FREQUENCY(MHz)LVDS=3.
5mALVDS=7mA09081-009Figure9.
DifferentialVoltageSwingvs.
Frequency;LVDSMode,7mAand3.
5mA0100200300400500AMPLITUDE(V)FREQUENCY(MHz)20pF2pF10pF09081-0101.
71.
92.
12.
32.
52.
72.
93.
13.
33.
5Figure10.
Amplitudevs.
FrequencyandCapacitiveLoad;CMOSMode,2pF,10pF,and20pFCH1200mV2.
5ns/DIV40.
0GS/sACH1104mV109081-013Figure11.
OutputWaveform(Differential),LVPECLat122.
88MHz–70–80–90–100–110–120–130–140–150–160–1701001k10k100k1M10MPHASENOISE(dBc/Hz)FREQUENCY(Hz)1:100Hz,–85.
0688dBc/Hz2:1kHz,–113.
3955dBc/Hz3:8kHz,–125.
8719dBc/Hz4:16kHz,–129.
5942dBc/Hz5:100kHz,–134.
5017dBc/Hz6:1MHz,–145.
2872dBc/Hz7:10MHz,–156.
2706dBc/Hz8:40MHz,–157.
4153dBc/Hzx:START12kHzSTOP80MHzCENTER40.
006MHzSPAN79.
988MHzNOISE:ANALYSISRANGEX:BANDMARKERANALYSISRANGEY:BANDMARKERINTGNOISE:–75.
94595dBc/39.
99MHzRMSNOISE:225.
539RAD12.
9224mdegRMSJITTER:194.
746fsecRESIDUALFM:2.
81623kHz135709081-015Figure12.
PhaseNoise,Output=184.
32MHz(VCXO=122.
88MHz,CrystekVCXOCVHD-950)–70–80–90–100–110–120–130–140–150–160–1701001k10k100k1M10MPHASENOISE(dBc/Hz)FREQUENCY(Hz)1:100Hz,–89.
0260dBc/Hz2:1kHz,–116.
9949dBc/Hz3:8kHz,–129.
5198dBc/Hz4:16kHz,–133.
3916dBc/Hz5:100kHz,–137.
7680dBc/Hz6:1MHz,–148.
3519dBc/Hz7:10MHz,–158.
3307dBc/Hz8:40MHz,159.
1629–dBc/Hzx:START12kHzSTOP80MHzCENTER40.
006MHzSPAN79.
988MHzNOISE:ANALYSISRANGEX:BANDMARKERANALYSISRANGEY:BANDMARKERINTGNOISE:–78.
8099dBc/39.
99MHzRMSNOISE:162.
189RAD9.
29276mdegRMSJITTER:210.
069fsecRESIDUALFM:2.
27638kHz135709081-016Figure13.
PhaseNoise,Output=122.
88MHz(VCXO=122.
88MHz,CrystekVCXOCVHD-950;DoublerIsOff)CH1500mV2.
5ns/DIV40.
0GS/sACH180mV109081-017Figure14.
OutputWaveform(Differential),HSTLat16mA,122.
88MHzDataSheetAD9524Rev.
F|Page17of56INPUT/OUTPUTTERMINATIONRECOMMENDATIONS1000.
1F0.
1FDOWNSTREAMDEVICELVDSOUTPUTHIGHIMPEDANCEINPUTAD952409081-142Figure15.
AC-CoupledLVDSOutputDriver100DOWNSTREAMDEVICELVDSOUTPUTAD9524HIGHIMPEDANCEINPUT09081-143Figure16.
DC-CoupledLVDSOutputDriver1000.
1F0.
1FDOWNSTREAMDEVICELVPECL-COMPATIBLEOUTPUTHIGHIMPEDANCEINPUT09081-044AD9524Figure17.
AC-CoupledLVPECLOutputDriver100DOWNSTREAMDEVICELVPECL-COMPATIBLEOUTPUTHIGHIMPEDANCEINPUTAD952409081-045Figure18.
DC-CoupledLVPECLOutputDriver1000.
1F0.
1FDOWNSTREAMDEVICEHSTLOUTPUTHIGHIMPEDANCEINPUT09081-046AD9524Figure19.
AC-CoupledHSTLOutputDriver100DOWNSTREAMDEVICEHSTLOUTPUTHIGHIMPEDANCEINPUTAD952409081-047Figure20.
DC-CoupledHSTLOutputDriver100(OPTIONAL1)1RESISTORVALUEDEPENDSUPONREQUIREDTERMINATIONOFSOURCE.
0.
1F0.
1FSELF-BIASEDREF,VCXO,ZERODELAYINPUTSAD952409081-048Figure21.
REF,VCXO,andZeroDelayInput,DifferentialMode(WhenInCMOSSingle-EndedInputMode,theUnusedInputCanBeLeftUnconnected)AD9524DataSheetRev.
F|Page18of56TERMINOLOGYPhaseJitterandPhaseNoiseAnidealsinewavecanbethoughtofashavingacontinuousandevenprogressionofphasewithtimefrom0°to360°foreachcycle.
Actualsignals,however,displayacertainamountofvariationfromidealphaseprogressionovertime.
Thisphenomenoniscalledphasejitter.
Althoughmanycausescancontributetophasejitter,onemajorcauseisrandomnoise,whichischaracterizedstatisticallyasbeingGaussian(normal)indistribution.
Thisphasejitterleadstoaspreadingoutoftheenergyofthesinewaveinthefrequencydomain,producingacontinuouspowerspectrum.
ThispowerspectrumisusuallyreportedasaseriesofvalueswhoseunitsaredBc/Hzatagivenoffsetinfrequencyfromthesinewave(carrier).
Thevalueisaratio(expressedindecibels)ofthepowercontainedwithina1Hzbandwidthwithrespecttothepoweratthecarrierfrequency.
Foreachmeasurement,theoffsetfromthecarrierfrequencyisalsogiven.
Itismeaningfultointegratethetotalpowercontainedwithinsomeintervalofoffsetfrequencies(forexample,10kHzto10MHz).
Thisiscalledtheintegratedphasenoiseoverthatfrequencyoffsetintervalandcanbereadilyrelatedtothetimejitterduetothephasenoisewithinthatoffsetfrequencyinterval.
PhasenoisehasadetrimentaleffectontheperformanceofADCs,DACs,andRFmixers.
Itlowerstheachievabledynamicrangeoftheconvertersandmixers,althoughtheyareaffectedinsomewhatdifferentways.
TimeJitterPhasenoiseisafrequencydomainphenomenon.
Inthetimedomain,thesameeffectisexhibitedastimejitter.
Whenobservingasinewave,thetimeofsuccessivezerocrossingsvaries.
Inasquarewave,thetimejitterisadisplacementoftheedgesfromtheirideal(regular)timesofoccurrence.
Inbothcases,thevariationsintimingfromtheidealarethetimejitter.
Becausethesevariationsarerandominnature,thetimejitterisspecifiedinsecondsrootmeansquare(rms)or1sigma(Σ)oftheGaussiandistribution.
TimejitterthatoccursonasamplingclockforaDACoranADCdecreasesthesignal-to-noiseratio(SNR)anddynamicrangeoftheconverter.
Asamplingclockwiththelowestpossiblejitterprovidesthehighestperformancefromagivenconverter.
AdditivePhaseNoiseAdditivephasenoiseistheamountofphasenoisethatcanbeattributedtothedeviceorsubsystembeingmeasured.
Thephasenoiseofanyexternaloscillatorsorclocksourcesissubtracted.
Thismakesitpossibletopredictthedegreetowhichthedeviceimpactsthetotalsystemphasenoisewhenusedinconjunctionwiththevariousoscillatorsandclocksources,eachofwhichcontributesitsownphasenoisetothetotal.
Inmanycases,thephasenoiseofoneelementdominatesthesystemphasenoise.
Whentherearemultiplecontributorstophasenoise,thetotalisthesquarerootofthesumofsquaresoftheindividualcontributors.
AdditiveTimeJitterAdditivetimejitteristheamountoftimejitterthatcanbeattributedtothedeviceorsubsystembeingmeasured.
Thetimejitterofanyexternaloscillatorsorclocksourcesissubtracted.
Thismakesitpossibletopredictthedegreetowhichthedeviceimpactsthetotalsystemtimejitterwhenusedinconjunctionwiththevariousoscillatorsandclocksources,eachofwhichcontributesitsowntimejittertothetotal.
Inmanycases,thetimejitteroftheexternaloscillatorsandclocksourcesdominatesthesystemtimejitter.
DataSheetAD9524Rev.
F|Page19of56THEORYOFOPERATIONDETAILEDBLOCKDIAGRAMCHARGEPUMP*2÷D1VCXOSWITCH-OVERCONTROLRESYNCH÷M1STATUSMONITORLOCKDETECT/SERIALPORTADDRESSCONTROLINTERFACE(SPIANDI2C)SCLK/SCLSDOSDIO/SDA÷N2PLL2LDO_PLL2LOOPFILTERTOSYNCLOOPFILTERCHARGEPUMPPLL1LOCKDETECTLOCKDETECTPFDZD_INZD_INPDRESETSYNC÷DΔtEDGE÷DΔtEDGE÷DΔtEDGE÷DΔtEDGE÷DΔtEDGE÷DΔtEDGESYNCSIGNALPLL1_OUTVDD1.
8_OUT[X:Y]REFAREFAREFBREFBAD9524REF_SELSTATUS0/SP0STATUS1/SP1EEPROMEEPROM_SELLF2_EXT_CAPLF1_EXT_CAPREF_TESTOSC_CTRLOSC_INCS÷R÷R÷R÷N1LDO_PLL1LDO_VCOVDD3_OUT[X:Y]VDD3_PLL1VDD3_PLL2NCVCOPFDOUT5OUT5OUT4OUT4OUT3OUT3OUT2OUT2OUT1OUT1OUT0OUT009081-020Figure22.
TopLevelDiagramOVERVIEWTheAD9524isaclockgeneratorthatemploysinteger-N-basedphase-lockedloops(PLL).
ThedevicearchitectureconsistsoftwocascadedPLLstages.
Thefirststage,PLL1,consistsofanintegerdivisionPLLthatusesanexternalvoltage-controlledcrystaloscillator(VCXO)ofupto250MHz.
PLL1hasanarrow-loopbandwidththatprovidesinitialjittercleanupoftheinputreferencesignal.
Thesecondstage,PLL2,isafrequencymultiplyingPLLthattranslatesthefirststageoutputfrequencytoarangeof3.
6GHzto4.
0GHz.
PLL2incorporatesaninteger-basedfeedbackdividerthatenablesintegerfrequencymultipli-cation.
Programmableintegerdividers(1to1024)followPLL2,establishingafinaloutputfrequencyof1GHzorless.
TheAD9524includesreferencesignalprocessingblocksthatenableasmoothswitchingtransitionbetweentworeferenceinputs.
Thiscircuitryautomaticallydetectsthepresenceofthereferenceinputsignals.
Ifonlyoneinputispresent,thedeviceusesitastheactivereference.
Ifbotharepresent,onebecomestheactivereferenceandtheotherbecomesthebackupreference.
Iftheactivereferencefails,thecircuitryautomaticallyswitchestothebackupreference(ifavailable),makingitthenewactivereference.
Aregistersettingdetermineswhatactiontotakeifthefailedreferenceisonceagainavailable:eitherstayonReferenceBorreverttoReferenceA.
Ifneitherreferencecanbeused,theAD9524supportsaholdovermode.
Areferenceselectpin(REF_SEL,Pin45)isavailabletomanuallyselectwhichinputreferenceisactive(seeTable43).
TheaccuracyoftheholdoverisdependentontheexternalVCXOfrequencystabilityathalfsupplyvoltage.
Anyofthedividersettingsareprogrammableviatheserialprogrammingport,enablingawiderangeofinput/outputfrequencyratiosunderprogramcontrol.
Thedividersalsoincludeaprogrammabledelaytoadjusttimingoftheoutputsignals,ifrequired.
TheoutputiscompatiblewithLVPECL,LVDS,orHSTLlogiclevels(seetheInput/OutputTerminationRecommendationssection);however,theAD9524isimplementedonlyinCMOS.
TheloopfiltersofeachPLLareintegratedandprogrammable.
OnlyasingleexternalcapacitorforeachofthetwoPLLloopfiltersisrequired.
TheAD9524operatesovertheextendedindustrialtemperaturerangeof40°Cto+85°C.
AD9524DataSheetRev.
F|Page20of56COMPONENTBLOCKS—INPUTPLL(PLL1)PLL1GeneralDescriptionFundamentally,theinputPLL(referredtoasPLL1)consistsofaphase-frequencydetector(PFD),chargepump,passiveloopfilter,andanexternalVCXOoperatinginaclosedloop.
PLL1hastheflexibilitytooperatewithaloopbandwidthofapproximately10Hzto100Hz.
ThisrelativelynarrowloopbandwidthgivestheAD9524theabilitytosuppressjitterthatappearsontheinputreferences(REFAandREFB).
TheoutputofPLL1thenbecomesalowjitterphase-lockedversionofthereferenceinputsystemclock.
PLL1ReferenceClockInputsTheAD9524featurestwoseparatedifferentialreferenceclockinputs,REFAandREFB.
Theseinputscanbeconfiguredtooperateinfulldifferentialmodeorsingle-endedCMOSmode.
Indifferentialmode,thesepinsareinternallyselfbiased.
IfREFAorREFBisdrivensingle-ended,theunusedside(REFA,REFB)shouldbedecoupledviaasuitablecapacitortoaquietground.
Figure21showstheequivalentcircuitofREFAorREFB.
Itispossibletodccoupletotheseinputs,butthedcoperationpointshouldbesetasspecifiedintheSpecificationstables.
TooperateeithertheREFAortheREFBinputsin3.
3VCMOSmode,theusermustsetBit5orBit6,respectively,inRegister0x01A(seeTable41).
Thesingle-endedinputscanbedrivenbyeitheradc-coupledCMOSlevelsignaloranac-coupledsinewaveorsquarewave.
Thedifferentialreferenceinputreceiverispowereddownwhenthedifferentialreferenceinputisnotselected,orwhenthePLLispowereddown.
Thesingle-endedbufferspower-downwhenthePLLispowereddown,whentheirrespectiveindividualpower-downregistersareset,orwhenthedifferentialreceiverisselected.
TheREFBRdividerusesthesamevalueastheREFARdividerunlessBit7,theenableREFBRdividerindependentdivisioncontrolbitinRegister0x01C,isprogrammedasshowninTable43.
PLL1LoopFilterThePLL1loopfilterrequirestheconnectionofanexternalcapacitorfromLF1_EXT_CAP(Pin5)toground.
ThevalueoftheexternalcapacitordependsontheuseofanexternalVCXO,aswellassuchconfigurationparametersasinputclockrateanddesiredbandwidth.
Normally,a0.
3Fcapacitorallowstheloopbandwidthtorangefrom10Hzto100Hzandensuresloopstabilityovertheintendedoperatingparametersofthedevice(seeTable44forRZEROvalues).
RZEROCPOLE1RPOLE2CPOLE2CHARGEPUMPLF1_EXT_CAPLDO_PLL1BUFFER1k0.
3FOSC_CTRLTOVCXOVTUNEAD952409081-022Figure23.
PLL1LoopFilterTable20.
PLL1LoopFilterProgrammableValuesRZERO(k)CPOLE1(nF)RPOLE2(k)CPOLE2(nF)LF1_EXT_CAP1(F)8831.
5fixed165fixed0.
337fixed0.
367734113510External1Externalloopfiltercapacitor.
AnexternalR-Clow-passfiltershouldbeusedattheOSC_CTRLoutput.
ThevaluesshowninFigure23addanadditionallow-passpoleat~530Hz.
ThisR-CnetworkfiltersthenoiseassociatedwiththeOSC_CTRLbuffertoachievethebestnoiseperformanceatthe1kHzoffsetregion.
RZEROCPOLE1RPOLE2LF1_EXT_CAPSWITCH-OVERCONTROLREFAREFBREFAREFBREF_SELREF_TESTDIVIDEBY1,2,.
.
.
1024CHARGEPUMP7BITS,0.
5ALSBVDD3_PLL1LDO_PLL11.
8VLDO3.
3VCMOSOR1.
8VDIFFERENTIALOSC_CTRLOSC_INDIVIDEBY1,2,.
.
.
1024DIVIDEBY1,2,.
.
.
1024DIVIDEBY1,2,.
.
.
63PFDVCXOCPOLE2AD952409081-021Figure24.
InputPLL(PLL1)BlockDiagramDataSheetAD9524Rev.
F|Page21of56PLL1InputDividersEachreferenceinputfeedsadedicatedreferencedividerblock.
Theinputdividersprovidedivisionofthereferencefrequencyinintegerstepsfrom1to1023.
TheyprovidethebulkofthefrequencyprescalingthatisnecessarytoreducethereferencefrequencytoaccommodatethebandwidththatistypicallydesiredforPLL1.
PLL1ReferenceSwitchoverThereferencemonitorverifiesthepresence/absenceoftheprescaledREFAandREFBsignals(thatis,afterdivisionbytheinputdividers).
Thestatusofthereferencemonitorguidestheactivityoftheswitchovercontrollogic.
TheAD9524supportsautomaticandmanualPLLreferenceclockswitchingbetweenREFA(theREFAandREFApins)andREFB(theREFBandREFBpins).
Thisfeaturesupportsnetworkingandinfrastructureapplicationsthatrequireredundantreferences.
Thereareseveralconfigurablemodesofreferenceswitchover.
ThemanualswitchoverisachievedeitherviaaprogrammingregistersettingorbyusingtheREF_SELpin.
TheautomaticswitchoveroccurswhenREFAdisappearsandthereisareferenceonREFB.
Thereferenceautomaticswitchovercanbesettoworkasfollows:Nonrevertive:stayonREFB.
SwitchfromREFAtoREFBwhenREFAdisappears,butdonotswitchbacktoREFAifitreappears.
IfREFBdisappears,thengobacktoREFA.
ReverttoREFA.
SwitchfromREFAtoREFBwhenREFAdisappears.
ReturntoREFAfromREFBwhenREFAreturns.
SeeTable43forthePLL1miscellaneouscontrolregisterbitsettings.
PLL1HoldoverIntheabsenceofbothinputreferences,thedeviceentersholdovermode.
HoldoverisasecondaryfunctionthatisprovidedbyPLL1.
BecausePLL1hasanexternalVCXOavailableasafrequencysource,itcontinuestooperateintheabsenceoftheinputreferencesignals.
Whenthedeviceswitchestoholdover,thechargepumptristates.
Thedevicecontinuesoperatinginthismodeuntilareferencesignalbecomesavailable.
Thenthedeviceexitsholdovermode,andPLL1resynchronizeswiththeactivereference.
Inadditiontotristate,thechargepumpcanbeforcedtoVCC/2duringholdover(seeTable43,Bit6inRegister0x01C).
COMPONENTBLOCKS—OUTPUTPLL(PLL2)PLL2GeneralDescriptionTheoutputPLL(referredtoasPLL2)consistsofanoptionalinputreferencedoubler,phase-frequencydetector(PFD),apartiallyintegratedanalogloopfilter(seeFigure25),anintegratedvoltage-controlledoscillator(VCO),andafeedbackdivider.
TheVCOproducesanominal3.
8GHzsignalwithanoutputdividerthatiscapableofdivisionratiosof4to11.
ThePFDoftheoutputPLLdrivesachargepumpthatincreases,decreases,orholdsconstantthechargestoredontheloopfiltercapacitors(bothinternalandexternal).
ThestoredchargeresultsinavoltagethatsetstheoutputfrequencyoftheVCO.
ThefeedbackloopofthePLLcausestheVCOcontrolvoltagetovaryinawaythatphaselocksthePFDinputsignals.
ThegainofPLL2isproportionaltothecurrentdeliveredbythechargepump.
TheloopfilterbandwidthischosentoreducenoisecontributionsfromPLLsourcesthatcoulddegradephasenoiserequirements.
TheoutputPLLhasaVCOwithmultiplebandsspanningarangeof3.
6GHzto4.
0GHz.
However,theactualoperatingfrequencywithinaparticularbanddependsonthecontrolvoltagethatappearsontheloopfiltercapacitor.
ThecontrolvoltagecausestheVCOoutputfrequencytovarylinearlywithintheselectedband.
ThisfrequencyvariabilityallowsthecontrolloopoftheoutputPLLtosynchronizetheVCOoutputsignalwiththereferencesignalappliedtothePFD.
Typically,thedeviceautomaticallyselectstheappropriatebandaspartofitscalibrationprocess(invokedviatheVCOcontrolregisteratAddress0x0F3).
NDIVIDERTODIST/RESYNC*2PLL1_OUTLDOLDOPLL_1.
8VLDO_PLL2VDD3_PLL2LDO_VCODIVIDEBY1,2,4,8,16DIVIDEBY4,5,6,.
.
.
11DIVIDE-BY-4PRESCALERA/BCOUNTERSCHARGEPUMP8BITS,3.
5ALSBPFDRZERORPOLE2CPOLE1CPOLE2LF2_EXT_CAPAD952409081-023Figure25.
OutputPLL(PLL2)BlockDiagramAD9524DataSheetRev.
F|Page22of56Input2*FrequencyMultiplierThe2*frequencymultiplierprovidestheoptiontodoublethefrequencyatthePLL2input.
ThisallowstheusertotakeadvantageofahigherfrequencyattheinputtothePLL(PFD)and,thus,allowsforreducedin-bandphasenoiseandgreaterseparationbetweenthefrequencygeneratedbythePLLandthemodulationspurassociatedwithPFD.
However,increasedreferencespurseparationresultsinharmonicspursintroducedbythefrequencymultiplierthatincreaseasthedutycycledeviatesfrom50%attheOSC_INinputs.
Assuch,beneficialuseofthefrequencymultiplierisapplication-specific.
Typically,aVCXOwithproperinterfacinghasadutycyclethatisapproximately50%attheOSC_INinputs.
Notethatthemaximumoutputfrequencyofthe2*frequencymultipliersmustnotexceedthemaximumPFDratethatisspecifiedinTable12.
PLL2FeedbackDividerPLL2hasafeedbackdivider(Ndivider)thatenablesittoprovideintegerfrequencyup-conversion.
ThePLL2Ndividerisacom-binationofaprescaler(P)andtwocounters,AandB.
ThetotaldividervalueisN=(P*B)+AwhereP=4.
Thefeedbackdividerisadualmodulusprescalerarchitecture,withanonprogrammablePthatisequalto4.
ThevalueoftheBcountercanbefrom4to63,andthevalueoftheAcountercanbefrom0to3.
However,duetothearchitectureofthedivider,thereareconstraints,aslistedinTable46.
PLL2LoopFilterThePLL2loopfilterrequirestheconnectionofanexternalcapacitorfromLF2_EXT_CAP(Pin9)toLDO_VCO(Pin12),asillustratedinFigure25.
Thevalueoftheexternalcapacitordependsontheoperatingmodeandthedesiredphasenoiseperformance.
Forexample,aloopbandwidthofapproximately500kHzproducesthelowestintegratedjitter.
Alowerbandwidthproduceslowerphasenoiseat1MHzbutincreasesthetotalintegratedjitter.
Table21.
PLL2LoopFilterProgrammableValuesRZERO()CPOLE1(pF)RPOLE2()CPOLE2(pF)LF2_EXT_CAP1(pF)325048900Fixedat16Typicalat1000300040450275032300250024225225016210082000018501Externalloopfiltercapacitor.
VCODividerTheVCOdividerprovidesfrequencydivisionbetweentheinternalVCOandtheclockdistribution.
TheVCOdividercanbesettodivideby4,5,6,7,8,9,10,or11.
VCOCalibrationTheAD9524on-chipVCOmustbemanuallycalibratedtoensureproperoperationoverprocessandtemperature.
Thisisaccom-plishedbysettingthecalibrateVCObit(Register0x0F3,Bit1)to1.
(Thisbitisnotselfclearing.
)ThesettingcanbeperformedaspartoftheinitialsetupbeforeexecutingtheIO_Updatebit(Register0x234,Bit0=1).
Areadbackbit,VCOcalibrationinprogress(Register0x22D,Bit0),indicateswhenaVCOcalibrationisinprogressbyreturningalogictrue(thatis,Bit0=1).
IftheEEPROMisinuse,settingthecalibrateVCObit(Register0x0F3,Bit1)to1beforesavingtheregistersettingstotheEEPROMensuresthattheVCOcalibratesautomaticallyaftertheEEPROMhasloaded.
Aftercalibration,itisrecommendedthatasyncbeinitiated(formoreinformation,seetheClockDistributionSynchronizationsection).
NotethatthecalibrateVCObitdefaultsto0.
Thisbitmustchangefrom0to1toinitiateacalibrationsequence.
Therefore,anysubsequentcalibrationsrequirethefollowingsequence:1.
Register0x0F3,Bit1(calibrateVCObit)=02.
Register0x234,Bit0(IO_Updatebit)=13.
Register0x0F3,Bit1(calibrateVCObit)=14.
Register0x234,Bit0(IO_Updatebit)=1VCOcalibrationiscontrolledbyacalibrationcontrollerthatrunsofftheVCXOinputclock.
ThecalibrationrequiresthatPLL2besetupproperlytolockthePLL2loopandthattheVCXOclockbepresent.
Duringpower-uporreset,thedistributionsectionisautomaticallyheldinsyncuntilthefirstVCOcalibrationisfinished.
Therefore,nooutputscanoccuruntilVCOcalibrationiscompleteandPLL2islocked.
InitiateaVCOcalibrationunderthefollowingconditions:AfterchanginganyofthePLL2BcounterandAcountersettingsorafterachangeinthePLL2referenceclockfrequency.
ThismeansthataVCOcalibrationshouldbeinitiatedanytimethataPLL2registerorreferenceclockchangessuchthatadifferentVCOfrequencyistheresult.
Wheneversystemcalibrationisdesired.
TheVCOisdesignedtooperateproperlyoverextremesoftemperatureevenwhenitisfirstcalibratedattheoppositeextreme.
However,aVCOcalibrationcanbeinitiatedatanytime,ifdesired.
DataSheetAD9524Rev.
F|Page23of56CLOCKDISTRIBUTIONTheclockdistributionblockprovidesanintegratedsolutionforgeneratingmultipleclockoutputsbasedonfrequencydividingthePLL2VCOdivideroutput.
Thedistributionoutputconsistsofsixchannels(OUT0toOUT5).
Eachoftheoutputchannelshasadedicateddividerandoutputdriver,asshowninFigure25.
TheAD9524alsohasthecapabilitytoroutetheVCXOoutputtotwooftheoutputs(OUT0andOUT1).
ClockDividersTheoutputclockdistributiondividersarereferredtoasD0toD5,correspondingtooutputchannelsOUT0throughOUT5,respectively.
Eachdividerisprogrammablewith10bitsofdivisiondepththatisequalto1to1024.
Dividershavedutycyclecorrectiontoalwaysgive50%dutycycle,evenforodddivides.
OutputPower-DownEachoftheoutputchannelsoffersindependentcontrolofthepower-downfunctionalityviatheChannel0toChannel5controlregisters(seeTable52).
Eachoutputchannelhasadedicatedpower-downbitforpoweringdowntheoutputdriver.
However,ifallsixoutputsarepowereddown,theentiredistributionoutputentersadeepsleepmode.
Althougheachchannelhasachannelpower-downcontrolsignal,itmaysometimesbedesirabletopowerdownanoutputdriverwhilemaintainingthedivider'ssynchronizationwiththeotherchanneldividers.
Thisisaccom-plishedbyplacingtheoutputintristatemode(thisworksinCMOSmode,aswell).
MultimodeOutputDriversTheuserhasindependentcontroloftheoperatingmodeofeachofthefourteenoutputchannelsviatheChannel0toChannel5controlregisters(seeTable52).
Theoperatingmodecontrolincludesthefollowing:LogicfamilyandpinfunctionalityOutputdrivestrengthOutputpolarityThefourleastsignificantbits(LSBs)ofeachofthesixChannel0toChannel5controlregisterscomprisethedrivermodebits.
Themodevalueselectsthedesiredlogicfamilyandpinfunctionalityofanoutputchannel,aslistedinTable52.
Thisdriverdesignallowsacommon100externalresistorforallthedifferentdrivermodesofoperationthatareillustratedinFigure26.
Iftheoutputchannelisac-coupledtothecircuittobeclocked,changingthemodevariesthevoltageswingtodeterminesensi-tivitytothedrivelevel.
Forexample,inLVDSmode,acurrentof3.
5mAcausesa350mVpeakvoltage.
Likewise,inLVPECLcompatiblemode,acurrentof8mAcausesan800mVpeakvoltageatthe100loadresistor.
UsinganyterminationotherthanthosespecifiedintheInput/OutputTerminationRecommendationssectionmayresultsindamageordecreaseendoflifeperformance.
Inadditiontothefourmodebits,eachofthesixChannel0toChannel5controlregistersincludesthefollowingcontrolbits:Invertdivideroutput.
Enablestheusertochoosebetweennormalpolarityandinvertedpolarity.
Normalpolarityisthedefaultstate.
InvertedpolarityreversestherepresentationofLogic0andLogic1,regardlessofthelogicfamily.
Ignoresync.
MakesthedividerignoretheSYNCsignalfromanysource.
Power-downchannel.
Powersdowntheentirechannel.
Lowerpowermode.
Drivermode.
Channeldivider.
Dividerphase.
3.
5mA/8mALVDS/LVPECLENABLEDHSTLENABLEDHSTLENABLED5050PNNP100LOADCMVDD3_OUT[x:y]1.
25VLVDSVDD–1.
3VLVPECLCMCOMMON-MODECIRCUIT+–08439-031Figure26.
MultimodeDriverAD9524DataSheetRev.
F|Page24of56ClockDistributionSynchronizationAblockdiagramoftheclockdistributionsynchronizationfunctionalityisshowninFigure27.
Thesynchronizationsequencebeginswiththeprimarysynchronizationsignal,whichultimatelyresultsindeliveryofasynchronizationstrobetotheclockdistributionlogic.
Asindicated,theprimarysynchronizationsignaloriginatesfromoneofthefollowingsources:Directsynchronizationsourceviathesyncdividersbit(seeRegister0x232,Bit0inTable56)Devicepin,SYNC(Pin13)AnautomaticsynchronizationofthedividerisinitiatedthefirsttimethatPLL2locksafterapower-uporresetevent.
Subsequentlock/unlockeventsdonotinitiatearesynchronizationofthedistributiondividersunlesstheyareprecededbyapower-downorresetofthepart.
FANOUTVCOOUTPUTDIVIDERSYNC(PIN13)SYNCDIVIDERDRIVEROUTxOUTxOUTSYNCPHASEDIVIDESYNCDIVIDERSBIT09081-025Figure27.
ClockOutputSynchronizationBlockDiagramDIVIDE=2,PHASE=0DIVIDE=2,PHASE=6VCODIVIDEROUTPUTCLOCKSYNCCONTROL6*0.
5PERIODS08439-026Figure28.
ClockOutputSynchronizationTimingDiagramDataSheetAD9524Rev.
F|Page25of56BothsourcesoftheprimarysynchronizationsignalarelogicOR'd;therefore,anyoneofthemcansynchronizetheclockdistributionoutputatanytime.
Whenusingthesyncdividersbit,theuserfirstsetsandthenclearsthebit.
Thesynchronizationeventistheclearingoperation(thatis,theLogic1toLogic0transitionofthebit).
ThedividersareallautomaticallysynchronizedtoeachotherwhenPLL2isready.
Thedividerssupportprogrammablephaseoffsetsfrom0to63steps,inhalfperiodsoftheinputclock(forexample,theVCOdivideroutputclock).
Thephaseoffsetsareincorporatedinthedividersthroughapresetforthefirstoutputclockperiodofeachdivider.
Phaseoffsetsaresupportedonlybyprogrammingtheinitialphaseanddividevalueandthenissuingasynctothedistribution(automaticallyatstartupormanually,ifdesired).
WhenusingtheSYNCpin(Pin17),thereare11VCOdivideroutputpipelinedelaysplusoneperiodoftheclockfromtherisingedgeofSYNCtotheclockoutput.
ThereisatleastoneextraVCOdividerperiodofuncertaintybecausetheSYNCsignalandtheVCOdivideroutputareasynchronous.
Innormaloperation,thephaseoffsetsarealreadyprogrammedthroughtheEEPROMortheSPI/I2CportbeforetheAD9524startstoprovideoutputs.
Althoughtheusercannotadjustthephaseoffsetswhilethedividersareoperating,itispossibletoadjustthephaseofalltheoutputstogetherwithoutpoweringdownPLL1andPLL2.
Thisisaccomplishedbyprogrammingthenewphaseoffset,usingBits[7:2]inRegister0x198(seeTable52)andthenissuingadividesyncsignalbyusingtheSYNCpinorthesyncdividersbit(Register0x232,Bit0).
Alloutputsthatarenotprogrammedtoignorethesyncaredisabledtemporarilywhilethesyncisactive.
Notethat,ifanoutputisusedforthezerodelaypath,italsodisappearsmomentarily.
However,thisisdesirablebecauseitensuresthatallthesynchronizedoutputshaveadeterministicphaserelation-shipwithrespecttothezerodelayoutputand,therefore,alsowithrespecttotheinput.
ZERODELAYOPERATIONZerodelayoperationalignsthephaseoftheoutputclockswiththephaseoftheexternalPLLreferenceinput.
TheOUT0outputisdesignedtobeusedastheoutputforzerodelay.
TherearetwozerodelaymodesontheAD9524:internalandexternal(seeFigure29).
Notethattheexternaldelaymodeprovidesbettermatchingthantheinternaldelaymodebecausetheoutputdriversareincludedinthezerodelaypath.
SettingtheanitbacklashpulsewidthcontrolofPLL1tomaximumgivesthebestzerodelaymatching.
InternalZeroDelayModeTheinternalzerodelayfunctionoftheAD9524isachievedbyfeedingtheoutputofChannelDivider0backtothePLL1Ndivider.
Bit5inRegister0x01Bisusedtoselectinternalzerodelaymode(seeTable42).
Intheinternalzerodelaymode,theoutputofChannelDivider0isroutedbacktothePLL1(Ndivider)throughamux.
PLL1synchronizesthephase/edgeoftheoutputofChannelDivider0withthephase/edgeofthereferenceinput.
Becausethechanneldividersaresynchronizedtoeachother,theoutputsofthechanneldivideraresynchronouswiththereferenceinput.
INTERNALFBZD_INREFAREFAAD9524FEEDBACKDELAYREFDELAYENBPFDOUT0OUT0ZD_IN09081-027Figure29.
ZeroDelayFunctionExternalZeroDelayModeTheexternalzerodelayfunctionoftheAD9524isachievedbyfeedingOUT0backtotheZD_INinputand,ultimately,backtothePLL1Ndivider.
InFigure29,thechangeinsignalroutingforexternalzerodelayisexternaltotheAD9524.
Bit5inRegister0x01Bisusedtoselecttheexternalzerodelaymode.
Inexternalzerodelaymode,OUT0mustberoutedbacktoPLL1(theNdivider)throughtheZD_INandZD_INpins.
PLL1synchronizesthephase/edgeofthefeedbackoutputclockwiththephase/edgeofthereferenceinput.
Becausethechanneldividersaresynchronizedtoeachother,theclockoutputsaresynchronouswiththereferenceinput.
BoththereferencepathdelayandthefeedbackdelayfromZD_INaredesignedtohavethesamepropagationdelayfromtheoutputdriversandPLLcomponentstominimizethephaseoffsetbetweentheclockoutputandthereferenceinputtoachievezerodelay.
LOCKDETECTPLL1andPLL2lockdetectorsissueanunlockconditionwhenthefrequencyerrorisgreaterthanthethresholdofthelockdetector.
WhenthePLLisunlocked,thereisarandomphasebetweenthereferenceclockandfeedbackclock.
Duetotherandomphaserelationshipthatexiststheunlockconditioncouldtakebetween215*TPFDcyclesto1*TPFDcycles.
Foralockconditionitwillalwaystake216*TPFDtolock,butitcouldpotentiallytake231*TPFDcyclesdependingonhowbigthephasejumpisandwhenitoccursinrelationtothelockdetectrestart.
AD9524DataSheetRev.
F|Page26of56RESETMODESTheAD9524hasapower-onreset(POR)andseveralotherwaystoapplyaresetconditiontothechip.
Power-OnResetDuringchippower-up,apower-onresetpulseisissuedwhen3.
3Vsupplyreaches~2.
6V(<2.
8V)andrestoresthechipeithertothesettingstoredinEEPROM(EEPROMpin=1)ortotheon-chipsetting(EEPROMpin=0).
Atpower-on,theAD9524executesaSYNCoperation,whichbringstheoutputsintophasealignmentaccordingtothedefaultsettings.
Theoutputdriversareheldinsyncforthedurationoftheinternallygeneratedpower-upsynctimer(~70ms).
Theoutputsbegintotoggleafterthisperiod.
ResetviatheRESETPinRESET,areset(anasynchronoushardresetisexecutedbybrieflypullingRESETlow),restoresthechipeithertothesettingstoredinEEPROM(EEPROMpin=1)ortotheon-chipsetting(EEPROMpin=0).
Aresetalsoexecutesasyncoperation,whichbringstheoutputsintophasealignmentaccordingtothedefaultsettings.
WhenEEPROMisinactive(EEPROMpin=0),ittakes~2sfortheoutputstobegintogglingafterRESETisissued.
WhenEEPROMisactive(EEPROMpin=1),ittakes~40msfortheoutputstotoggleafterRESETisbroughthigh.
ResetviatheSerialPortTheserialportcontrolregisterallowsforaresetbysettingBit2andBit5inRegister0x000.
WhenBit5andBit2areset,thechipentersaresetmodeandrestoresthechipeithertothesettingstoredinEEPROM(EEPROMpin=1)ortotheon-chipsetting(EEPROMpin=0),exceptforRegister0x000.
Exceptfortheselfclearingbits,Bit2andBit5,Register0x000retainsitspreviousvaluepriortoreset.
Duringtheinternalreset,theoutputsholdstatic.
Bit2andBit5areselfclearing.
However,theselfclearingoperationdoesnotcompleteuntilanadditionalserialportSCLKcyclecompletes,andtheAD9524isheldinresetuntilBit2andBit5selfclear.
ResettoSettingsinEEPROMwhenEEPROMPin=0viatheSerialPortTheserialportcontrolregisterallowsthechiptoberesettosettingsinEEPROMwhentheEEPROMpin=1viaRegister0xB02,Bit1.
Thisbitisselfclearing.
ThisbitdoesnothaveanyeffectwhentheEEPROMpin=0.
Ittakes~40msfortheoutputstobegintogglingaftertheSoft_EEPROMregisteriscleared.
POWER-DOWNMODEChipPower-DownviaPDPlacetheAD9524intoapower-downmodebypullingthePDpinlow.
Power-downturnsoffmostofthefunctionsandcurrentsinsidetheAD9524.
Thechipremainsinthispower-downstateuntilPDisreturnedtoalogichighstate.
Whentakenoutofpower-downmode,theAD9524returnstothesettingsprogrammedintoitsregisterspriortothepower-down,unlesstheregistersarechangedbynewprogrammingwhilethePDpinisheldlow.
DataSheetAD9524Rev.
F|Page27of56SERIALCONTROLPORTTheAD9524serialcontrolportisaflexible,synchronousserialcommunicationsportthatallowsaneasyinterfacewithmanyindustry-standardmicrocontrollersandmicroprocessors.
TheAD9524serialcontrolportiscompatiblewithmostsynchronoustransferformats,includingPhilipsI2C,MotorolaSPI,andIntelSSRprotocols.
TheAD9524I2CimplementationdeviatesfromtheclassicI2Cspecificationintwospecifications,andthesedeviationsaredocumentedinTable16ofthisdatasheet.
Theserialcontrolportallowsread/writeaccesstoallregistersthatconfiguretheAD9524.
SPI/ICPORTSELECTIONTheAD9524hastwoserialinterfaces,SPIandI2C.
UserscanselecteithertheSPIorI2C,dependingonthestates(logichigh,logiclow)ofthetwologiclevelinputpins,SP1andSP0,whenpowerisappliedorafteraRESET(eachpinhasaninternal40kΩpull-downresistor).
WhenbothSP1andSP0arelow,theSPIinterfaceisactive.
Otherwise,I2CisactivewiththreedifferentI2Cslaveaddresssettings(sevenbitswide),asshowninTable22.
ThefiveMSBsoftheslaveaddressarehardwarecodedas11000,andthetwoLSBsaredeterminedbythelogiclevelsoftheSP1andSP0pins.
Table22.
SerialPortModeSelectionSP1SP0AddressLowLowSPILowHighI2C:1100000HighLowI2C:1100001HighHighI2C:1100010ICSERIALPORTOPERATIONTheAD9524I2CportisbasedontheI2Cfastmodestandard.
TheAD9524supportsbothI2Cprotocols:standardmode(100kHz)andfastmode(400kHz).
TheAD9524I2Cporthasa2-wireinterfaceconsistingofaserialdataline(SDA)andaserialclockline(SCL).
InanI2Cbussystem,theAD9524isconnectedtotheserialbus(databusSDAandclockbusSCL)asaslavedevice,meaningthatnoclockisgeneratedbytheAD9524.
TheAD9524usesdirect16-bit(twobytes)memoryaddressinginsteadoftraditional8-bit(onebyte)memoryaddressing.
I2CBusCharacteristicsTable23.
I2CBusDefinitionsAbbreviationDefinitionSStartSrRepeatedstartPStopAAcknowledgeANoacknowledgeWWriteRReadOnepulseontheSCLclocklineisgeneratedforeachdatabitthatistransferred.
ThedataontheSDAlinemustnotchangeduringthehighperiodoftheclock.
ThestateofthedatalinecanchangeonlywhentheclockontheSCLlineislow.
SDASCLDATALINESTABLE;DATAVALIDCHANGEOFDATAALLOWED09081-160Figure30.
ValidBitTransferAstartconditionisatransitionfromhightolowontheSDAlinewhileSCLishigh.
Thestartconditionisalwaysgeneratedbythemastertoinitializethedatatransfer.
AstopconditionisatransitionfromlowtohighontheSDAlinewhileSCLishigh.
Thestopconditionisalwaysgeneratedbythemastertoendthedatatransfer.
STARTCONDITIONSSTOPCONDITIONPSDASCL09081-161Figure31.
StartandStopConditionsAbyteontheSDAlineisalwayseightbitslong.
Anacknowledgebitmustfolloweverybyte.
BytesaresentMSBfirst.
AD9524DataSheetRev.
F|Page28of56SDAMSBACKNOWLEDGEFROMSLAVE-RECEIVERACKNOWLEDGEFROMSLAVE-RECEIVERSCLSP12891283TO73TO791009081-162Figure32.
AcknowledgeBitSDAMSB=0ACKNOWLEDGEFROMSLAVE-RECEIVERACKNOWLEDGEFROMSLAVE-RECEIVERSCLSP12891283TO73TO791009081-163Figure33.
DataTransferProcess(MasterWriteMode,2-ByteTransferUsedforIllustration)SDAACKNOWLEDGEFROMMASTER-RECEIVERNOACKNOWLEDGEFROMSLAVE-RECEIVERSCLSP12891283TO73TO7910MSB=109081-164Figure34.
DataTransferProcess(MasterReadMode,2-ByteTransferUsedforIllustration)Theacknowledgebitistheninthbitattachedtoany8-bitdatabyte.
Anacknowledgebitisalwaysgeneratedbythereceivingdevice(receiver)toinformthetransmitterthatthebytehasbeenreceived.
ItisaccomplishedbypullingtheSDAlinelowduringtheninthclockpulseaftereach8-bitdatabyte.
Thenoacknowledgebitistheninthbitattachedtoany8-bitdatabyte.
Anoacknowledgebitisalwaysgeneratedbythereceivingdevice(receiver)toinformthetransmitterthatthebytehasnotbeenreceived.
ItisaccomplishedbyleavingtheSDAlinehighduringtheninthclockpulseaftereach8-bitdatabyte.
DataTransferProcessThemasterinitiatesdatatransferbyassertingastartcondition.
Thisindicatesthatadatastreamfollows.
AllI2Cslavedevicesconnectedtotheserialbusrespondtothestartcondition.
Themasterthensendsan8-bitaddressbyteovertheSDAline,consistingofa7-bitslaveaddress(MSBfirst),plusanR/Wbit.
Thisbitdeterminesthedirectionofthedatatransfer,thatis,whetherdataiswrittentoorreadfromtheslavedevice(0=write,1=read).
Theperipheralwhoseaddresscorrespondstothetransmittedaddressrespondsbysendinganacknowledgebit.
Allotherdevicesonthebusremainidlewhiletheselecteddevicewaitsfordatatobereadfromorwrittentoit.
IftheR/Wbitis0,themaster(transmitter)writestotheslavedevice(receiver).
IftheR/Wbitis1,themaster(receiver)readsfromtheslavedevice(trans-mitter).
TheformatforthesecommandsisdescribedintheDataTransferFormatsection.
Dataisthensentovertheserialbusintheformatofnineclockpulses:onedatabyte(eightbits)fromeithermaster(writemode)orslave(readmode),followedbyanacknowledgebitfromthereceivingdevice.
Thenumberofbytesthatcanbetransmittedpertransferisunrestricted.
Inwritemode,thefirsttwodatabytesimmediatelyaftertheslaveaddressbytearetheinternalmemory(controlregisters)addressbyteswiththehighaddressbytefirst.
Thisaddressingschemegivesamemoryaddressofupto2161=65,535.
Thedatabytesafterthesetwomemoryaddressbytesareregisterdatawrittenintothecontrolregisters.
Inreadmode,thedatabytesaftertheslaveaddressbyteareregisterdatareadfromthecontrolregisters.
AsingleI2Ctransfercancontainmultipledatabytesthatcanbereadfromorwrittentocontrolregisterswhoseaddressisautomaticallyincrementedstartingfromthebasememoryaddress.
Whenalldatabytesarereadorwritten,stopconditionsareestablished.
Inwritemode,themaster(transmitter)assertsastopconditiontoenddatatransferduringthe10thclockpulsefollowingtheacknowledgebitforthelastdatabytefromtheslavedevice(receiver).
Inreadmode,themasterdevice(receiver)receivesthelastdatabytefromtheslavedevice(transmitter)butdoesnotpullitlowduringtheninthclockpulse.
Thisisknownasanoacknowl-edgebit.
Uponreceivingthenoacknowledgebit,theslavedeviceknowsthatthedatatransferisfinishedandreleasestheSDAline.
Themasterthentakesthedatalinelowduringthelowperiodbeforethe10thclockpulseandhighduringthe10thclockpulsetoassertastopcondition.
Arepeatedstart(Sr)conditioncanbeusedinplaceofastopcondition.
Furthermore,astartorstopconditioncanoccuratanytime,andpartiallytransferredbytesarediscarded.
ForanI2Cdatawritetransfercontainingmultipledatabytes,theperipheraldrivesanoacknowledgeforthedatabytethatfollowsawritetoRegister0x234,therebyendingtheI2Ctransfer.
ForanI2Cdatareadtransfercontainingmultipledatabytes,theperipheraldrivesdatabytesof0x00forsubsequentreadsthatfollowareadfromRegister0x234.
DataSheetAD9524Rev.
F|Page29of56DataTransferFormatSendbyteformat.
Thesendbyteprotocolisusedtosetuptheregisteraddressforsubsequentcommands.
SSlaveAddressWARAMAddressHighByteARAMAddressLowByteAPWritebyteformat.
ThewritebyteprotocolisusedtowritearegisteraddresstotheRAM,startingfromthespecifiedRAMaddress.
SSlaveAddressWARAMAddressHighByteARAMAddressLowByteARAMData0ARAMData1ARAMData2APReceivebyteformat.
Thereceivebyteprotocolisusedtoreadthedatabyte(s)fromtheRAM,startingfromthecurrentaddress.
SSlaveAddressRARAMData0ARAMData1ARAMData2APReadbyteformat.
Thecombinedformatofthesendbyteandthereceivebyte.
SSlaveAddressWARAMAddressHighByteARAMAddressLowByteASrSlaveAddressRARAMData0ARAMData1ARAMData2APICSerialPortTimingSDASCLSSrPStFALLtSET;DATtLOWtRISEtHLD;STRtHLD;DATtHIGHtFALLtSET;STRtHLD;STRtSPIKEtSET;STPtRISEtIDLE09081-165Figure35.
ICSerialPortTimingTable24.
I2CTimingDefinitionsParameterDescriptionfI2CICclockfrequencytIDLEBusidletimebetweenstopandstartconditionstHLD;STRHoldtimeforrepeatedstartconditiontSET;STRSetuptimeforrepeatedstartconditiontSET;STPSetuptimeforstopconditiontHLD;DATHoldtimefordatatSET;DATSetuptimefordatatLOWDurationofSCLclocklowtHIGHDurationofSCLclockhightRISESCL/SDArisetimetFALLSCL/SDAfalltimetSPIKEVoltagespikepulsewidththatmustbesuppressedbytheinputfilterAD9524DataSheetRev.
F|Page30of56SPISERIALPORTOPERATIONPinDescriptionsSCLK(serialclock)istheserialshiftclock.
Thispinisaninput.
SCLKisusedtosynchronizeserialcontrolportreadsandwrites.
Writedatabitsareregisteredontherisingedgeofthisclock,andreaddatabitsareregisteredonthefallingedge.
Thispinisinternallypulleddownbya40kresistortoground.
SDIO(serialdatainput/output)isadual-purposepinandactseitherasaninputonly(unidirectionalmode)orasaninput/output(bidirectionalmode).
TheAD9524defaultstothebidirectionalI/Omode.
SDO(serialdataout)isusedonlyintheunidirectionalI/Omodeasaseparateoutputpinforreadingbackdata.
CS(chipselectbar)isanactivelowcontrolthatgatesthereadandwritecycles.
WhenCSishigh,theSDOandSDIOpinsenterahighimpedancestate.
Thispinisinternallypulledupbya40kresistortoVDD3_REF.
AD9524SERIALCONTROLPORTCSSCLK/SCLSDIO/SDASDO09081-034Figure36.
SerialControlPortSPIModeOperationInSPImode,singleormultiplebytetransfersaresupported,aswellasMSBfirstorLSBfirsttransferformats.
TheAD9524serialcontrolportcanbeconfiguredforasinglebidirectionalI/Opin(SDIOonly)orfortwounidirectionalI/Opins(SDIO/SDO).
Bydefault,theAD9524isinbidirectionalmode.
Shortinstructionmode(8-bitinstructions)isnotsupported.
Onlylong(16-bit)instructionmodeissupported.
AwriteorareadoperationtotheAD9524isinitiatedbypullingCSlow.
TheCSstalledhighmodeissupportedindatatransferswherethreeorfewerbytesofdata(plusinstructiondata)aretransferred(seeTable25).
Inthismode,theCSpincantemporarilyreturnhighonanybyteboundary,allowingtimeforthesystemcontrollertoprocessthenextbyte.
CScangohighonlyonbyteboundaries;however,itcangohighduringeitherphase(instructionordata)ofthetransfer.
Duringthisperiod,theserialcontrolportstatemachineentersawaitstateuntilalldataissent.
Ifthesystemcontrollerdecidestoabortthetransferbeforeallofthedataissent,thestatemachinemustbereseteitherbycompletingtheremainingtransfersorbyreturningCSlowforatleastonecompleteSCLKcycle(butfewerthaneightSCLKcycles).
RaisingtheCSpinonanonbyteboundaryterminatestheserialtransferandflushesthebuffer.
Instreamingmode(seeTable25),anynumberofdatabytescanbetransferredinacontinuousstream.
Theregisteraddressisautomaticallyincrementedordecremented(seetheSPIMSB/LSBFirstTransferssection).
CSmustberaisedattheendofthelastbytetobetransferred,therebyendingstreamingmode.
CommunicationCycle—InstructionPlusDataTherearetwopartstoacommunicationcyclewiththeAD9524.
Thefirstpartwritesa16-bitinstructionwordintotheAD9524,coincidentwiththefirst16SCLKrisingedges.
TheinstructionwordprovidestheAD9524serialcontrolportwithinformationregardingthedatatransfer,whichisthesecondpartofthecommunicationcycle.
Theinstructionworddefineswhethertheupcomingdatatransferisareadorawrite,thenumberofbytesinthedatatransfer,andthestartingregisteraddressforthefirstbyteofthedatatransfer.
WriteIftheinstructionwordisforawriteoperation,thesecondpartisthetransferofdataintotheserialcontrolportbufferoftheAD9524.
DatabitsareregisteredontherisingedgeofSCLK.
Thelengthofthetransfer(one,two,orthreebytesorstreamingmode)isindicatedbytwobits(W1,W0)intheinstructionbyte.
Whenthetransferisone,two,orthreebytes,butnotstreaming,CScanberaisedaftereachsequenceofeightbitstostallthebus(exceptafterthelastbyte,whereitendsthecycle).
Whenthebusisstalled,theserialtransferresumeswhenCSislowered.
RaisingtheCSpinonanonbyteboundaryresetstheserialcontrolport.
Duringawrite,streamingmodedoesnotskipoverreservedorblankregisters,andtheusercanwrite0x00tothereservedregisteraddresses.
Becausedataiswrittenintoaserialcontrolportbufferarea,andnotdirectlyintotheactualcontrolregistersoftheAD9524,anadditionaloperationisneededtotransfertheserialcontrolportbuffercontentstotheactualcontrolregistersoftheAD9524,therebycausingthemtobecomeactive.
TheupdateregistersoperationconsistsofsettingtheselfclearingIO_Updatebit,Bit0ofRegister0x234(seeTable58).
Anynumberofdatabytescanbechangedbeforeexecutinganupdateregistersoperation.
Theupdateregisterssimultaneouslyactuatesallregisterchangesthathavebeenwrittentothebuffersinceanypreviousupdate.
ReadTheAD9524supportsonlythelonginstructionmode.
Iftheinstructionwordisforareadoperation,thenextN*8SCLKcyclesclockoutthedatafromtheaddressspecifiedintheinstructionword,whereNis1to3asdeterminedbyBits[W1:W0].
IfN=4,thereadoperationisinstreamingmode,continuinguntilCSisraised.
DuringanSPIread,serialdataonSDIO(orSDOinthecaseof4-wiremode)transitionsontheSCLKfallingedge,andisnormallysampledontheSCLKrisingedge.
Toreadthelastbitcorrectly,theSPIhostmustbeabletotolerateazeroholdtime.
Incaseswherezeroholdtimeisnotpossible,theusercaneitherusestreamingmodeanddelaytherisingedgeofCS,orsampletheserialdataontheSCLKfallingedge.
However,tosamplethedatacorrectlyontheSCLKfallingedge,theusermustensurethatthesetuptimeisgreaterthantDV(timedatavalid).
Streamingmodedoesnotskipoverreservedorblankregisters.
DataSheetAD9524Rev.
F|Page31of56ThedefaultmodeoftheAD9524serialcontrolportisthebidirectionalmode.
Inbidirectionalmode,boththesentdataandthereadbackdataappearontheSDIOpin.
ItisalsopossibletosettheAD9524tounidirectionalmode.
Inunidirectionalmode,thereadbackdataappearsontheSDOpin.
Areadbackrequestreadsthedatathatisintheserialcontrolportbufferareaorthedatathatisintheactiveregisters(seeFigure37).
SERIALCONTROLPORTBUFFERREGISTERSUPDATEREGISTERSACTIVEREGISTERSSCLK/SCLSDOSDIO/SDACS09081-035Figure37.
RelationshipBetweenSerialControlPortBufferRegistersandActiveRegistersSPIINSTRUCTIONWORD(16BITS)TheMSBoftheinstructionwordisR/W,whichindicateswhethertheinstructionisareadorawrite.
Thenexttwobits([W1:W0])indicatethelengthofthetransferinbytes.
Thefinal13bitsaretheaddress([A12:A0])atwhichtobeginthereadorwriteoperation.
Forawrite,theinstructionwordisfollowedbythenumberofbytesofdataindicatedbyBits[W1:W0](seeTable25).
Table25.
ByteTransferCountW1W0BytestoTransfer00101210311StreamingmodeBits[A12:A0]selecttheaddresswithintheregistermapthatiswrittentoorreadfromduringthedatatransferportionofthecommunicationscycle.
OnlyBits[A11:A0]areneededtocovertherangeofthe0x234registersusedbytheAD9524.
BitA12mustalwaysbe0.
Formultibytetransfers,thisaddressisthestartingbyteaddress.
InMSBfirstmode,subsequentbytesdecrementtheaddress.
SPIMSB/LSBFIRSTTRANSFERSTheAD9524instructionwordandbytedatacanbeMSBfirstorLSBfirst.
AnydatawrittentoRegister0x000mustbemirrored:Bit7ismirroredtoBit0,Bit6toBit1,Bit5toBit2,andBit4toBit3.
ThismakesitirrelevantwhetherLSBfirstorMSBfirstisineffect.
ThedefaultfortheAD9524isMSBfirst.
WhenLSBfirstissetbyRegister0x000,Bit1andRegister0x000,Bit6,ittakeseffectimmediatelybecauseitaffectsonlytheoperationoftheserialcontrolportanddoesnotrequirethatanupdatebeexecuted.
WhenMSBfirstmodeisactive,theinstructionanddatabytesmustbewrittenfromMSBtoLSB.
MultibytedatatransfersinMSBfirstformatstartwithaninstructionbytethatincludestheregisteraddressofthemostsignificantdatabyte.
Subsequentdatabytesmustfollowinorderfromthehighaddresstothelowaddress.
InMSBfirstmode,theserialcontrolportinternaladdressgeneratordecrementsforeachdatabyteofthemultibytetransfercycle.
WhenLSBfirstmodeisactive,theinstructionanddatabytesmustbewrittenfromLSBtoMSB.
MultibytedatatransfersinLSBfirstformatstartwithaninstructionbytethatincludestheregisteraddressoftheleastsignificantdatabyte,followedbymultipledatabytes.
Inamultibytetransfercycle,theinternalbyteaddressgeneratoroftheserialportincrementsforeachbyte.
TheAD9524serialcontrolportregisteraddressdecrementsfromtheregisteraddressjustwrittentoward0x000formultibyteI/OoperationsiftheMSBfirstmodeisactive(default).
IftheLSBfirstmodeisactive,theregisteraddressoftheserialcontrolportincrementsfromtheaddressjustwrittentoward0x234formultibyteI/Ooperations.
Unusedaddressesarenotskippedfortheseoperations.
FormultibyteaccessesthatcrossAddress0x234orAddress0x000inMSBfirstmode,theSPIinternallydisableswritestosubsequentregistersandreturnszerosforreadstosubsequentregisters.
Streamingmodealwaysterminateswhencrossingaddressboundaries(asshowninTable26).
Table26.
StreamingMode(NoAddressesAreSkipped)WriteModeAddressDirectionStopSequenceMSBFirstDecrement…,0x001,0x000,stopTable27.
SerialControlPort,16-BitInstructionWord,MSBFirstMSBLSBI15I14I13I12I11I10I9I8I7I6I5I4I3I2I1I0R/WW1W0A12=0A11A10A9A8A7A6A5A4A3A2A1A0AD9524DataSheetRev.
F|Page32of56tSDON'TCAREDON'TCAREW1W0A12A11A10A9A8A7A6A5D4D3D2D1D0HIGH-IMEPDANCER/WtDStDHtHIGHtLOWtSCLKtCCSSCLKSDIO09081-138Figure38.
SerialControlPortRead—MSBFirst,16-BitInstruction,OneByteofDataCSSCLKDON'TCARESDIOA12W0W1R/WA11A10A9A8A7A6A5A4A3A2A1A0D7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0DON'TCAREDON'TCAREDON'TCARE16-BITINSTRUCTIONHEADERREGISTER(N)DATAREGISTER(N–1)DATA09081-038Figure39.
SerialControlPortWrite—MSBFirst,16-BitInstruction,TwoBytesofDataCSSCLKSDIOSDOREGISTER(N)DATA16-BITINSTRUCTIONHEADERREGISTER(N–1)DATAREGISTER(N–2)DATAREGISTER(N–3)DATAA12W0W1R/WA11A10A9A8A7A6A5A4A3A2A1A0DON'TCAREDON'TCAREDON'TCAREDON'TCARED7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D009081-039Figure40.
SerialControlPortRead—MSBFirst,16-BitInstruction,FourBytesofDatatSDON'TCAREDON'TCAREW1W0A12A11A10A9A8A7A6A5D4D3D2D1D0DON'TCAREDON'TCARER/WtDStDHtHIGHtLOWtCLKtCCSSCLKSDIO09081-040Figure41.
SerialControlPortWrite—MSBFirst,16-BitInstruction,TimingMeasurementsDATABITN–1DATABITNCSSCLKSDIOSDOtDV09081-041Figure42.
TimingDiagramforSerialControlPortRegisterReadCSSCLKDON'TCAREDON'TCARE16-BITINSTRUCTIONHEADERREGISTER(N)DATAREGISTER(N+1)DATASDIODON'TCAREDON'TCAREA0A1A2A3A4A5A6A7A8A9A10A11A12D1D0R/WW1W0D2D3D4D5D6D7D0D1D2D3D4D5D6D709081-042Figure43.
SerialControlPortWrite—LSBFirst,16-BitInstruction,TwoBytesofDataDataSheetAD9524Rev.
F|Page33of56CSSCLKSDIOtHIGHtLOWtCLKtStDStDHtCBITNBITN+109081-043Figure44.
SerialControlPortTiming—WriteTable28.
SerialControlPortTimingParameterDescriptiontDSSetuptimebetweendataandrisingedgeofSCLKtDHHoldtimebetweendataandrisingedgeofSCLKtCLKPeriodoftheclocktSSetuptimebetweentheCSfallingedgeandSCLKrisingedge(startofcommunicationcycle)tCSetuptimebetweentheSCLKrisingedgeandCSrisingedge(endofcommunicationcycle)tHIGHMinimumperiodthatSCLKshouldbeinalogichighstatetLOWMinimumperiodthatSCLKshouldbeinalogiclowstatetDVSCLKtovalidSDIOandSDO(seeFigure42)AD9524DataSheetRev.
F|Page34of56EEPROMOPERATIONSTheAD9524containsaninternalEEPROM(nonvolatilememory).
TheEEPROMcanbeprogrammedbytheusertocreateandstoreauserdefinedregistersettingfilewhenthepowerisoff.
Thissettingfilecanbeusedforpower-upandchipresetasadefaultsetting.
TheEEPROMsizeis512bytes.
DescriptionsoftheEEPROMregistersthatcontrolEEPROMoperationcanbefoundinTable59andTable60.
Duringthedatatransferprocess,thewriteandreadregistersaregenerallynotavailableviatheserialport,exceptforonereadbackbit:Status_EEPROM(Register0xB00,Bit0).
TodeterminethedatatransferstatethroughtheserialportinSPImode,userscanreadthevalueoftheStatus_EEPROMbit(1=datatransferinprocessand0=datatransfercomplete).
InICmode,theusercanaddresstheAD9524slaveportwiththeexternalICmaster(sendanaddressbytetotheAD9524).
IftheAD9524respondswithanoacknowledgebit,thedatatransferwasnotreceived.
IftheAD9524respondswithanacknowledgebit,thedatatransferprocessiscomplete.
TheusercanmonitortheStatus_EEPROMbitoruseRegister0x232,Bit4toprogramtheSTATUS0pintomonitorthestatusofthedatatransfer(seeTable56).
Totransferall512bytestotheEEPROM,ittakesapproximately46ms.
TotransferthecontentsoftheEEPROMtotheactiveregister,ittakesapproximately40ms.
RESET,ahardreset(anasynchronoushardresetisexecutedbybrieflypullingRESETlow),restoresthechipeithertothesettingstoredinEEPROM(theEEPROMpin=1)ortotheon-chipsetting(theEEPROMpin=0).
AhardresetalsoexecutesaSYNCoperation,whichbringstheoutputsintophasealignmentaccordingtothedefaultsettings.
WhenEEPROMisinactive(theEEPROMpin=0),ittakes~2sfortheoutputstobegintogglingafterRESETisissued.
WhenEEPROMisactive(theEEPROMpin=1),ittakes~40msfortheoutputstotoggleafterRESETisbroughthigh.
WRITINGTOTHEEEPROMTheEEPROMcannotbeprogrammeddirectlythroughtheserialportinterface.
ToprogramtheEEPROMandstorearegistersettingfile,followthesesteps:1.
ProgramtheAD9524registerstothedesiredcircuitstate.
IftheuserwantsPLL2tolockautomaticallyafterpower-up,thecalibrateVCObit(Bit1,Register0x0F3)mustbesetto1.
ThisallowsVCOcalibrationtostartautomaticallyafterregisterloading.
NotethatavalidinputreferencesignalmustbepresentduringVCOcalibration.
2.
SettheIO_Updatebit(Bit0,Register0x234)to1.
3.
ProgramtheEEPROMbufferregisters,ifnecessary(seetheProgrammingtheEEPROMBufferSegmentsection).
ThisstepisnecessaryonlyifuserswanttousetheEEPROMtocontrolthedefaultsettingsofsome(butnotall)oftheAD9524registers,oriftheywanttocontroltheregistersettingupdatesequenceduringpower-uporchipreset.
4.
SettheenableEEPROMwritebit(Bit0,Register0xB02)to1toenabletheEEPROM.
5.
SettheREG2EEPROMbit(Bit0,Register0xB03)to1.
ThisstartstheprocessofwritingdataintotheEEPROMtocreatetheEEPROMsettingfile.
ThisenablestheEEPROMcontrollertotransferthecurrentregistervalues,aswellasthememoryaddressandinstructionbytesfromtheEEPROMbuffersegment,intotheEEPROM.
Afterthewriteprocessiscompleted,theinternalcontrollersetsbitREG2EEPROMbackto0.
Bit0oftheStatus_EEPROMregister(Register0xB00)isusedtoindicatethedatatransferstatusbetweentheEEPROMandthecontrolregisters(1=datatransferinprocess,and0=datatransfercomplete).
Atthebeginningofthedatatransfer,theStatus_EEPROMbitissetto1bytheEEPROMcontrollerandclearedto0attheendofthedatatransfer.
TheusercanaccessStatus_EEPROMviatheSTATUS0pinwhentheSTATUS0pinisprogrammedtomonitortheStatus_EEPROMbit.
Alternatively,theusercanmonitortheStatus_EEPROMbitdirectly.
6.
Whenthedatatransferiscomplete(Status_EEPROM=0),settheenableEEPROMwritebit(Bit0inRegister0xB02)to0.
ClearingtheenableEEPROMwritebitto0disableswritingtotheEEPROM.
Toensurethatthedatatransferhascompletedcorrectly,verifythattheEEPROMdataerrorbit(Bit0inRegister0xB01)=0.
Avalueof1inthisbitindicatesadatatransfererror.
READINGFROMTHEEEPROMThefollowingreset-relatedeventscanstarttheprocessofrestoringthesettingsstoredintheEEPROMtothecontrolregisters.
WhentheEEPROM_SELpinissethigh,doanyofthefollowingtoinitiateanEEPROMread:PoweruptheAD9524.
PerformahardwarechipresetbypullingtheRESETpinlowandthenreleasingRESET.
Settheselfclearingsoftresetbit(Bit5,Register0x000)to1.
WhentheEEPROM_SELpinissetlow,settheselfclearingSoft_EEPROMbit(Bit1,Register0xB02)to1.
TheAD9524thenstartstoreadtheEEPROMandloadsthevaluesintotheAD9524registers.
IftheEEPROM_SELpinislowduringresetorpower-up,theEEPROMisnotactive,andtheAD9524defaultvaluesareloadedinstead.
WhenusingtheEEPROMtoautomaticallyloadtheAD9524registervaluesandlockthePLL,thecalibrateVCObit(Bit1,Register0x0F3)mustbesetto1whentheregistervaluesarewrittentotheEEPROM.
ThisallowsVCOcalibrationtostartautomaticallyafterregisterloading.
AvalidinputreferencesignalmustbepresentduringVCOcalibration.
DataSheetAD9524Rev.
F|Page35of56Toensurethatthedatatransferhascompletedcorrectly,verifythattheEEPROMdataerrorbit(Bit0inRegister0xB01)issetto0.
Avalueof1inthisbitindicatesadatatransfererror.
PROGRAMMINGTHEEEPROMBUFFERSEGMENTTheEEPROMbuffersegmentisaregisterspacethatallowstheusertospecifywhichgroupsofregistersarestoredtotheEEPROMduringEEPROMprogramming.
Normally,thissegmentdoesnotneedtobeprogrammedbytheuser.
Instead,thedefaultpower-upvaluesfortheEEPROMbuffersegmentallowtheusertostorealloftheregistervaluesfromRegister0x000toRegister0x234totheEEPROM.
Forexample,iftheuserwantstoloadonlytheoutputdriversettingsfromtheEEPROMwithoutdisturbingthePLLregistersettingscurrentlystoredintheEEPROM,theEEPROMbuffersegmentcanbemodifiedtoincludeonlytheregistersthatapplytotheoutputdriversandexcludetheregistersthatapplytothePLLconfiguration.
TherearetwopartstotheEEPROMbuffersegment:registersectiondefinitiongroupsandoperationalcodes.
EachregistersectiondefinitiongroupcontainsthestartingaddressandnumberofbytestobewrittentotheEEPROM.
IftheAD9524registermapwerecontinuousfromAddress0x000toAddress0x234,onlyoneregistersectiondefinitiongroupwouldconsistofastartingaddressof0x000andalengthof563bytes.
However,thisisnotthecase.
TheAD9524registermapisnoncontiguous,andtheEEPROMisonly512byteslong.
Therefore,theregistersectiondefinitiongrouptellstheEEPROMcontrollerhowtheAD9524registermapissegmented.
Therearethreeoperationalcodes:IO_Update,end-of-data,andpseudo-end-of-data.
ItisimportantthattheEEPROMbuffersegmentalwayshaveeitheranend-of-dataorapseudo-end-of-dataoperationalcodeandthatanIO_Updateoperationcodeappearatleastoncebeforetheend-of-dataoperationalcode.
RegisterSectionDefinitionGroupTheregistersectiondefinitiongroupisusedtodefineacontinuousregistersectionfortheEEPROMprofile.
Itconsistsofthreebytes.
Thefirstbytedefineshowmanycontinuousregisterbytesareinthisgroup.
Iftheuserputs0x000inthefirstbyte,itmeansthereisonlyonebyteinthisgroup.
Iftheuserputs0x001,itmeanstherearetwobytesinthisgroup.
Themaximumnumberofregistersinonegroupis128.
Thenexttwobytesarethehighbyteandlowbyteofthememoryaddress(16bits)ofthefirstregisterinthisgroup.
IO_Update(OperationalCode0x80)TheEEPROMcontrollerusesthisoperationalcodetogenerateanIO_Updatesignaltoupdatetheactivecontrolregisterbankfromthebufferregisterbankduringthedownloadprocess.
Ataminimum,thereshouldbeatleastoneIO_Updateoperationalcodeaftertheendofthefinalregistersectiondefinitiongroup.
ThisisneededsothatatleastoneIO_UpdateoccursafteralloftheAD9524registersareloadedwhentheEEPROMisread.
IfthisoperationalcodeisabsentduringawritetotheEEPROM,theregistervaluesloadedfromtheEEPROMarenottransferredtotheactiveregisterspace,andthesevaluesdonottakeeffectaftertheyareloadedfromtheEEPROMtotheAD9524.
End-of-Data(OperationalCode0xFF)TheEEPROMcontrollerusesthisoperationalcodetoterminatethedatatransferprocessbetweenEEPROMandthecontrolregisterduringtheuploadanddownloadprocess.
ThelastitemappearingintheEEPROMbuffersegmentshouldbeeitherthisoperationalcodeorthepseudo-end-of-dataoperationalcode.
Pseudo-End-of-Data(OperationalCode0xFE)TheAD9524EEPROMbuffersegmenthas23bytesthatcancontainuptosevenregistersectiondefinitiongroups.
Ifuserswanttodefinemorethansevenregistersectiondefinitiongroups,thepseudo-end-of-dataoperationalcodecanbeused.
Duringtheuploadprocess,whentheEEPROMcontrollerreceivesthepseudo-end-of-dataoperationalcode,ithaltsthedatatransferprocess,clearstheREG2EEPROMbit(Bit0,Register0xB03),andenablestheAD9524serialport.
UserscanthenprogramtheEEPROMbuffersegmentagainandreinitiatethedatatransferprocessbysettingtheREG2EEPROMbitto1andtheIO_Updatebit(Bit0,Register0x234)to1.
TheinternalICmasterthenbeginswritingtotheEEPROM,startingfromtheEEPROMaddressheldfromthelastwriting.
ThissequenceenablesmorediscreteinstructionstobewrittentotheEEPROMthanwouldotherwisebepossibleduetothelimitedsizeoftheEEPROMbuffersegment.
Italsopermitstheusertowritetothesameregistermultipletimeswithadifferentvalueeachtime.
AD9524DataSheetRev.
F|Page36of56Table29.
ExampleofanEEPROMBufferSegmentRegisterAddress(Hex)Bit7(MSB)Bit6Bit5Bit4Bit3Bit2Bit1Bit0(LSB)StartEEPROMBufferSegment0xA000Numberofbytesofthefirstgroupofregisters(Bits[6:0])0xA01Addressofthefirstgroupofregisters(Bits[15:8])0xA02Addressofthefirstgroupofregisters(Bits[7:0])0xA030Numberofbytesofthesecondgroupofregisters(Bits[6:0])0xA04Addressofthesecondgroupofregisters(Bits[15:8])0xA05Addressofthesecondgroupofregisters(Bits[7:0])0xA060Numberofbytesofthethirdgroupofregisters(Bits[6:0])0xA07Addressofthethirdgroupofregisters(Bits[15:8])0xA08Addressofthethirdgroupofregisters(Bits[7:0])0xA09IO_Updateoperationalcode(0x80)0xA0AEnd-of-dataoperationalcode(0xFF)DataSheetAD9524Rev.
F|Page37of56POWERDISSIPATIONANDTHERMALCONSIDERATIONSTheAD9524isamultifunctional,highspeeddevicethattargetsawidevarietyofclockapplications.
Thenumerousinnovativefeaturescontainedinthedeviceeachconsumeincrementalpower.
Ifalloutputsareenabledinthemaximumfrequencyandmodethathavethehighestpower,thesafethermaloperatingconditionsofthedevicemaybeexceeded.
CarefulanalysisandconsiderationofpowerdissipationandthermalmanagementarecriticalelementsinthesuccessfulapplicationoftheAD9524device.
TheAD9524deviceisspecifiedtooperatewithintheindustrialambienttemperaturerangeof–40°Cto+85°C.
Thisspecificationisconditional,however,suchthattheabsolutemaximumjunctiontemperatureisnotexceeded(asspecifiedinTable17).
Athighoperatingtemperatures,extremecaremustbetakenwhenoperatingthedevicetoavoidexceedingthejunctiontemperatureandpotentiallydamagingthedevice.
AmaximumjunctiontemperatureislistedinTable1withtheambientoperatingrange.
TheambientrangeandmaximumjunctiontemperaturespecificationsensuretheperformanceofthedeviceasguaranteedintheSpecificationssection.
Manyvariablescontributetotheoperatingjunctiontemperaturewithinthedevice,includingSelecteddrivermodeofoperationOutputclockspeedSupplyvoltageAmbienttemperatureThecombinationofthesevariablesdeterminesthejunctiontemperaturewithintheAD9524deviceforagivensetofoperatingconditions.
TheAD9524isspecifiedforanambienttemperature(TA).
ToensurethatTAisnotexceeded,anairflowsourcecanbeused.
UsethefollowingequationtodeterminethejunctiontemperatureontheapplicationPCB:TJ=TCASE+(ΨJT*PD)where:TJisthejunctiontemperature(°C).
TCASEisthecasetemperature(°C)measuredbytheuseratthetopcenterofthepackage.
ΨJTisthevaluefromTable18.
PDisthepowerdissipationoftheAD9524.
ValuesofθJAareprovidedforpackagecomparisonandPCBdesignconsiderations.
θJAcanbeusedforafirst-orderapproximationofTJbytheequationTJ=TA+(θJA*PD)whereTAistheambienttemperature(°C).
ValuesofθJCareprovidedforpackagecomparisonandPCBdesignconsiderationswhenanexternalheatsinkisrequired.
ValuesofΨJBareprovidedforpackagecomparisonandPCBdesignconsiderations.
CLOCKSPEEDANDDRIVERMODEClockspeeddirectlyandlinearlyinfluencesthetotalpowerdissipationofthedeviceand,therefore,thejunctiontemperature.
TwooperatingfrequenciesarelistedundertheincrementalpowerdissipationparameterinTable3.
Usinglinearinterpretationisasufficientapproximationforfrequencynotlistedinthetable.
Whencalculatingpowerdissipationforthermalconsideration,theamountofpowerdissipatedinthe100resistorshouldberemoved.
IfusingthedatainTable2,thispowerisalreadyremoved.
Ifusingthecurrentvs.
frequencygraphsprovidedintheTypicalPerformanceCharacteristicssection,thepowerintotheloadmustbesubtracted,usingthefollowingequation:1002SwingVoltageOutputalDifferentiEVALUATIONOFOPERATINGCONDITIONSThefirststepinevaluatingtheoperatingconditionsistodeterminethemaximumpowerconsumption(PD)internaltotheAD9524.
ThemaximumPDexcludespowerdissipatedintheloadresistorsofthedriversbecausesuchpowerisexternaltothedevice.
UsethepowerdissipationspecificationslistedinTable3tocalculatethetotalpowerdissipatedforthedesiredconfiguration.
ThebasetypicalconfigurationparameterinTable3listsapowerof428mW,whichincludesoneLVPECLoutputat122.
88MHz.
IfthefrequencyofoperationisnotlistedinTable3,seetheTypicalPerformanceCharacteristicssection,currentvs.
frequencyanddrivermode,tocalculatethepowerdissipation;thenadd20%formaximumcurrentdraw.
RemovethepowerdissipatedintheloadresistortoachievethemostaccuratepowerdissipationinternaltotheAD9524.
SeeTable30forasummaryoftheincrementalpowerdissipationfromthebasepowerconfigurationfortwodifferentexamples.
Table30.
TemperatureGradientExamplesDescriptionModeFrequency(MHz)MaximumPower(mW)Example1BaseTypicalConfiguration428OutputDriver5*LVPECL122.
88275TotalPower703Example2BaseTypicalConfiguration428OutputDriver5*LVPECL983.
04795TotalPower1223Thesecondstepistomultiplythepowerdissipatedbythethermalimpedancetodeterminethemaximumpowergradient.
Forthisexample,athermalimpedanceofθJA=20.
1°C/Wwasused.
AD9524DataSheetRev.
F|Page38of56Example1(703mW*20.
1°C/W)=14.
1°CWithanambienttemperatureof85°C,thejunctiontemperatureisTJ=85°C+14.
1°C=99°CThisjunctiontemperatureisbelowthemaximumallowable.
Example2(1223mW*20.
1°C/W)=24.
6°CWithanambienttemperatureof85°C,thejunctiontemperatureisTJ=85°C+24.
6°C=109°CThisjunctiontemperatureisbelowthemaximumallowable.
THERMALLYENHANCEDPACKAGEMOUNTINGGUIDELINESRefertotheAN-772ApplicationNote,ADesignandManufacturingGuidefortheLeadFrameChipScalePackage(LFCSP),formoreinformationaboutmountingdeviceswithanexposedpaddle.
DataSheetAD9524Rev.
F|Page39of56CONTROLREGISTERSCONTROLREGISTERMAPRegisteraddressesthatarenotlistedinTable31arenotused,andwritingtothoseregistershasnoeffect.
Registersthataremarkedasreservedshouldneverhavetheirvalueschanged.
Whenwritingtoregisterswithbitsthataremarkedreserved,theusershouldtakecaretoalwayswritethedefaultvalueforthereservedbits.
Table31.
ControlRegisterMapAddr(Hex)RegisterName(MSB)Bit7Bit6Bit5Bit4Bit3Bit2Bit1(LSB)Bit0DefaultValue(Hex)SerialPortConfiguration0x000SPImodeserialportconfigurationSDOactiveLSBfirst/addressincrementSoftresetReservedReservedSoftresetLSBfirst/addressincrementSDOactive0x00I2CmodeserialportconfigurationReservedReservedSoftresetReservedReservedSoftresetReservedReserved0x000x004ReadbackcontrolReservedReservedReservedReservedReservedReservedReservedReadbackactiveregisters0x000x005EEPROMcustomerversionIDEEPROMcustomerversionID[7:0](LSB)0x000x006EEPROMcustomerversionID[15:8](MSB)0x00InputPLL(PLL1)0x010PLL1REFARdividercontrol10-bitREFARdivider[7:0](LSB)0x000x011Reserved10-bitREFARdivider[9:8](MSB)0x000x012PLL1REFBRdividercontrol10-bitREFBRdivider[7:0](LSB)0x000x013Reserved10-bitREFBRdivider[9:8](MSB)0x000x014PLL1referencetestdividerReservedReservedREF_TESTdivider0x000x015PLL1reservedReservedReservedReservedReservedReservedReservedReservedReserved0x000x016PLL1feedbackNdividercontrol10-bitPLL1feedbackdivider[7:0](LSB)0x000x017Reserved10-bitPLL1feedbackdivider[9:8](MSB)0x000x018PLL1chargepumpcontrolPLL1chargepumptristatePLL1chargepumpcontrol0x0C0x019ReservedReservedReservedEnableSPIcontrolofantibacklashpulsewidthAntibacklashpulsewidthcontrolPLL1chargepumpmode0x000x01APLL1inputreceivercontrolREF_TESTinputreceiverenableREFBdifferentialreceiverenableREFAdifferentialreceiverenableREFBreceiverenableREFAreceiverenableInputREFA,REFBreceiverpower-downcontrolenableOSC_INsingle-endedreceivermodeenable(CMOSmode)OSC_INdifferentialreceivermodeenable0x000x01BREF_TEST,REFA,REFB,andZD_INcontrolReservedReservedZerodelaymodeOSC_INsignalfeedbackforPLL1ZD_INsingle-endedreceivermodeenable(CMOSmode)ZD_INdifferen.
receivermodeenableREFBsingle-endedreceivermodeenable(CMOSmode)REFAsingle-endedreceivermodeenable(CMOSmode)0x000x01CPLL1miscellaneouscontrolEnableREFBRdividerindepen.
divisioncontrolOSC_CTRLcontrolvoltagetoVCC/2whenrefclockfailsReservedReferenceselectionmodeReservedReserved0x00AD9524DataSheetRev.
F|Page40of56Addr(Hex)RegisterName(MSB)Bit7Bit6Bit5Bit4Bit3Bit2Bit1(LSB)Bit0DefaultValue(Hex)0x01DPLL1loopfilterzeroresistorcontrolReservedReservedReservedReservedPLL1loopfilter,RZERO0x00OutputPLL(PLL2)0x0F0PLL2chargepumpcontrolPLL2chargepumpcontrol0x000x0F1PLL2feedbackNdividercontrolAcounterBcounter0x040x0F2PLL2controlPLL2lockdetectorpower-downReservedEnablefrequencydoublerEnableSPIcontrolofantibacklashpulsewidthAntibacklashpulsewidthcontrolPLL2chargepumpmode0x030x0F3VCOcontrolReservedReservedReservedForcereleaseofdistributionsyncwhenPLL2isunlockedReservedForceVCOtomidpointfrequencyCalibrateVCO(notauto-clearing)Reserved0x000x0F4VCOdividercontrolReservedReservedReservedReservedVCOdividerpower-downVCOdivider0x000x0F5PLL2loopfiltercontrol(9bits)Pole2resistor(RPOLE2)Zeroresistor(RZERO)Pole1capacitor(CPOLE1)0x000x0F6ReservedReservedReservedReservedReservedReservedReservedBypassinternalRZEROresistor0x000x0F9ReservedReservedReservedReservedReservedReservedReservedReservedReserved0x00ClockDistribution0x190ReservedReserved0x000x196Channel0controlInvertdivideroutputIgnoresyncPower-downchannelLowerpowermodeDrivermode0x000x19710-bitchanneldivider[7:0](LSB)0x1F0x198Dividerphase[5:0]10-bitchanneldivider[9:8](MSB)0x040x199Channel1controlInvertdivideroutputIgnoresyncPower-downchannelLowerpowermodeDrivermode0x200x19A10-bitchanneldivider[7:0](LSB)0x1F0x19BDividerphase[5:0]10-bitchanneldivider[9:8](MSB)0x040x19CChannel2controlInvertdivideroutputIgnoresyncPower-downchannelLowerpowermodeDrivermode0x000x19D10-bitchanneldivider[7:0](LSB)0x1F0x19EDividerphase[5:0]10-bitchanneldivider[9:8](MSB)0x040x19FChannel3controlInvertdivideroutputIgnoresyncPower-downchannelLowerpowermodeDrivermode[3:0]0x200x1A010-bitchanneldivider[7:0](LSB)0x1F0x1A1Dividerphase[5:0]10-bitchanneldivider[9:8](MSB)0x040x1AEChannel4controlInvertdivideroutputIgnoresyncPower-downchannelLowerpowermodeDrivermode0x000x1AF10-bitchanneldivider[7:0](LSB)0x1F0x1B0Dividerphase[5:0]10-bitchanneldivider[9:8](MSB)0x040x1B1Channel5controlInvertdivideroutputIgnoresyncPower-downchannelLowerpowermodeDrivermode0x200x1B210-bitchanneldivider[7:0](LSB)0x1F0x1B3Dividerphase[5:0]10-bitchanneldivider[9:8](MSB)0x04DataSheetAD9524Rev.
F|Page41of56Addr(Hex)RegisterName(MSB)Bit7Bit6Bit5Bit4Bit3Bit2Bit1(LSB)Bit0DefaultValue(Hex)0x1BAPLL1outputcontrolReservedReservedReservedPLL1outputCMOSdriverstrengthPLL1outputdivider0x000x1BBPLL1outputchannelcontrolPLL1outputdriverpower-downReservedReservedReservedReservedReservedRouteVCXOclocktoCh1dividerinputRouteVCXOclocktoCh0dividerinput0x80Readback0x22CReadback0StatusPLL2referenceclockStatusPLL1feedbackclockStatusVCXOStatusREF_TESTStatusREFBStatusREFALockdetectPLL2LockdetectPLL10x22DReadback1ReservedReservedReservedReservedHoldoveractiveSelectedreference(inautomode)ReservedVCOcalibrationinprogressOther0x230StatussignalsReservedReservedStatusMonitor0control0x000x231ReservedReservedStatusMonitor1control0x000x232ReservedReservedReservedEnableStatus_EEPROMonSTATUS0pinSTATUS1pindividerenableSTATUS0pindividerenableReservedSyncdividers(manualcontrol)0:syncsignalinactive1:dividersheldinsync(sameasSYNCpinlow)0x000x233Power-downcontrolReservedReservedReservedReservedReservedPLL1power-downPLL2power-downDistributionpower-down0x070x234UpdateallregistersReservedIO_Update0x00EEPROMBuffer0xA00SerialportconfigurationSizeoftransfer:onebyte0x000xA01Startingaddress:0x00000x000xA020x000xA03ReadbackcontrolandEEPROMcustomerversionIDSizeoftransfer:threebytes0x020xA04Startingaddress:0x00040x000xA050x040xA06PLL1Sizeoftransfer:15bytes0x0E0xA07Startingaddress:0x00100x000xA080x100xA09PECL/CMOSoutputSizeoftransfer:15bytes0x0E0xA0AStartingaddress:0x00F00x000xA0B0xF00xA0CDividersSizeoftransfer:44bytes0x2B0xA0DStartingaddress:0x01900x010xA0E0x90AD9524DataSheetRev.
F|Page42of56Addr(Hex)RegisterName(MSB)Bit7Bit6Bit5Bit4Bit3Bit2Bit1(LSB)Bit0DefaultValue(Hex)0xA0FClockinputandREFSizeoftransfer:twobytes0x010xA10Startingaddress:0x01E00x010xA110xE00xA12OtherSizeoftransfer:fourbytes0x030xA13Startingaddress:0x02300x020xA140x300xA15IO_UPDATECommand:IO_UPDATE0x800xA16EndofdataCommand:Endofdata0xFFEEPROMControl0xB00Status_EEPROM(readonly)ReservedReservedReservedReservedReservedReservedReservedStatus_EEPROM(readonly)0x000xB01EEPROMerrorcheckingreadback(readonly)ReservedReservedReservedReservedReservedReservedReservedEEPROMdataerror(readonly)0x000xB02EEPROMControl1ReservedReservedReservedReservedReservedReservedSoft_EEPROMEnableEEPROMwrite0x000xB03EEPROMControl2ReservedReservedReservedReservedReservedReservedReservedREG2EEPROM0x00DataSheetAD9524Rev.
F|Page43of56CONTROLREGISTERMAPBITDESCRIPTIONSSerialPortConfiguration(Address0x000toAddress0x006)Table32.
SPIModeSerialPortConfigurationAddressBitsBitNameDescription0x0007SDOactiveSelectsunidirectionalorbidirectionaldatatransfermode.
ThisbitisignoredinI2Cmode.
0:SDIOpinusedforwriteandread;SDOishighimpedance(default).
1:SDOusedforread;SDIOusedforwrite;unidirectionalmode.
6LSBfirst/addressincrementSPIMSBorLSBdataorientation.
ThisbitisignoredinI2Cmode.
0:data-orientedMSBfirst;addressingdecrements(default).
1:data-orientedLSBfirst;addressingincrements.
5SoftresetSoftreset.
1(selfclearing):softreset;restoresdefaultvaluestointernalregisters.
4ReservedReserved.
[3:0]Mirror[7:4]Bits[3:0]shouldalwaysmirrorBits[7:4]sothatitdoesnotmatterwhetherthepartisinMSBfirstorLSBfirstmode(seeRegister0x000,Bit6).
Setbitsasfollows:Bit0=Bit7.
Bit1=Bit6.
Bit2=Bit5.
Bit3=Bit4.
0x0040ReadbackactiveregistersForbufferedregisters,serialportreadbackreadsfromactual(active)registersinsteadoffromthebuffer.
0(default):readsvaluescurrentlyappliedtotheinternallogicofthedevice.
1:readsbufferedvaluesthattakeeffectonthenextassertionoftheI/Oupdate.
Table33.
I2CModeSerialPortConfigurationAddressBitsBitNameDescription0x000[7:6]ReservedReserved.
5SoftresetSoftreset.
1(selfclearing):softreset;restoresdefaultvaluestointernalregisters.
4ReservedReserved.
[3:0]Mirror[7:4]Bits[3:0]shouldalwaysmirrorBits[7:4].
Setbitsasfollows:Bit0=Bit7.
Bit1=Bit6.
Bit2=Bit5.
Bit3=Bit4.
0x0040ReadbackactiveregistersForbufferedregisters,serialportreadbackreadsfromactual(active)registersinsteadoffromthebuffer.
0(default):readsvaluescurrentlyappliedtotheinternallogicofthedevice.
1:readsbufferedvaluesthattakeeffectonthenextassertionoftheI/Oupdate.
Table34.
EEPROMCustomerVersionIDAddressBitsBitNameDescription0x005[7:0]EEPROMcustomerversionID(LSB)16-bitEEPROMID,Bits[7:0].
Thisregister,alongwithRegister0x006,allowstheusertostoreauniqueIDtoidentifywhichversionoftheAD9524registersettingsisstoredintheEEPROM.
ItdoesnotaffectAD9524operationinanyway(default:0x00).
0x006[7:0]EEPROMcustomerversionID(MSB)16-bitEEPROMID,Bits[15:8].
Thisregister,alongwithRegister0x005,allowstheusertostoreauniqueIDtoidentifywhichversionoftheAD9524registersettingsisstoredintheEEPROM.
ItdoesnotaffectAD9524operationinanyway(default:0x00).
AD9524DataSheetRev.
F|Page44of56InputPLL(PLL1)(Address0x010toAddress0x01D)Table35.
PLL1REFARDividerControlAddressBitsBitNameDescription0x010[7:0]REFARdivider10-bitREFARdivider,Bits[7:0](LSB).
Divide-by-1todivide-by-1023.
00000000,00000001:divide-by-1.
0x011[1:0]10-bitREFARdivider,Bits[9:8](MSB)Table36.
PLL1REFBRDividerControl1AddressBitsBitNameDescription0x012[7:0]REFBRdivider10-bitREFBRdivider,Bits[7:0](LSB).
Divide-by-1todivide-by-1023.
00000000,00000001:divide-by-1.
0x013[1:0]10-bitREFBRdivider,Bits[9:8](MSB)1RequiresRegister0x01C,Bit7=1fordivisionthatisindependentofREFAdivision.
Table37.
PLL1ReferenceTestDividerAddressBitsBitNameDescription0x014[7:6]ReservedReserved[5:0]REF_TESTdivider6-bitreferencetestdivider.
Divide-by-1todivide-by-63.
000000,000001:divide-by-1.
Table38.
PLL1ReservedAddressBitsBitNameDescription0x015[7:0]ReservedReservedTable39.
PLL1FeedbackNDividerControlAddressBitsBitNameDescription0x016[7:0]PLL1feedbackNdividercontrol(N_PLL1)10-bitfeedbackdivider,Bits[7:0](LSB).
Divide-by-1todivide-by-1023.
00000000,00000001:divide-by-1.
0x017[1:0]10-bitfeedbackdivider,Bits[1:0](MSB)Table40.
PLL1ChargePumpControlAddressBitsBitNameDescription0x0187PLL1chargepumptristateTristatesthePLL1chargepump.
[6:0]PLL1chargepumpcontrolThesebitssetthemagnitudeofthePLL1chargepumpcurrent.
Granularityis~0.
5μAwithafull-scalemagnitudeof~63.
5μA.
0x019[7:5]ReservedReserved.
4EnableSPIcontrolofantibacklashpulsewidthControlsthefunctionalityofRegister0x019,Bits[3:2].
0(default):thedeviceautomaticallycontrolstheantibacklashperiodtohigh(equivalenttoRegister0x019,Bits[3:2]=10).
1:antibacklashperioddefinedbyRegister0x019,Bits[3:2].
[3:2]AntibacklashpulsewidthcontrolControlsthePFDantibacklashperiod.
ThesebitsdefaulttothehighsettingunlessreprogrammedusingRegister0x019[4]=1b.
ThehighsettingdecreasesthemaximumallowablePLL1PFDrate.
SeeTable7forranges.
00:minimum.
01:low.
10:high(initialstateunlesschangedviaRegister0x019[4]=1b).
11:maximum.
[1:0]PLL1chargepumpmodeControlsthemodeofthePLL1chargepump.
00:(default)tristate.
01:pumpup.
10:pumpdown.
11:normal.
DataSheetAD9524Rev.
F|Page45of56Table41.
PLL1InputReceiverControlAddressBitsBitNameDescription0x01A7REF_TESTinputreceiverenable1:enabled.
0:disabled(default).
6REFBdifferentialreceiverenable1:differentialreceivermode.
0:single-endedreceivermode(alsodependsonRegister0x01B,Bit1)(default).
5REFAdifferentialreceiverenable1:differentialreceivermode.
0:single-endedreceivermode(alsodependsonRegister0x01B,Bit0)(default).
4REFBreceiverenableREFBreceiverpower-downcontrolmodeonlywhenBit2=1.
1:enableREFBreceiver.
0:power-down(default).
3REFAreceiverenableREFAreceiverpower-downcontrolmodeonlywhenBit2=1.
1:enableREFAreceiver.
0:power-down(default).
2InputREFAandREFBreceiverpower-downcontrolenableEnablespower-downcontroloftheinputreceivers,REFAandREFB.
1:power-downcontrolenabled.
0:bothreceiversenabled(default).
1OSC_INsingle-endedreceivermodeenable(CMOSmode)Selectswhichsingle-endedinputpinisenabledwheninthesingle-endedreceivermode(Register0x01A,Bit0=0).
1:negativereceiverfromoscillatorinput(OSC_INpin)selected.
0:positivereceiverfromoscillatorinput(OSC_INpin)selected(default).
0OSC_INdifferentialreceivermodeenable1:differentialreceivermode.
0:single-endedreceivermode(alsodependsonBit1)(default).
Table42.
REF_TEST,REFA,REFB,andZD_INControlAddressBitsBitNameDescription0x01B[7:6]Reserved0:reserved(default).
5ZerodelaymodeSelectsthezerodelaymodeused(viatheZD_INpin)whenRegister0x01B,Bit4=0.
Otherwise,thisbitisignored.
1:internalzerodelaymode.
Thezerodelayreceiverispowereddown.
TheinternalzerodelaypathfromDistributionDividerChannel0isused.
0:externalzerodelaymode.
TheZD_INreceiverisenabled.
4OSC_INsignalfeedbackforPLL1ControlstheinputPLLfeedbackpath,localfeedbackfromtheOSC_INreceiverorzerodelaymode.
1:OSC_INreceiverinputusedfortheinputPLLfeedback(non-zerodelaymode).
0:zerodelaymodeenabled(alsodependsonRegister0x01B,Bit4toselectthezerodelaypath.
3ZD_INsingle-endedreceivermodeenable(CMOSmode)Selectswhichsingle-endedinputpinisenabledwheninthesingle-endedreceivermode(Register0x01B,Bit2=0).
1:ZD_INpinenabled.
0:ZD_INpinenabled.
2ZD_INdifferentialreceivermodeenable1:differentialreceivermode.
0:single-endedreceivermode(alsodependsonRegister0x01B,Bit3).
1REFBsingle-endedreceivermodeenable(CMOSmode)Selectswhichsingle-endedinputpinisenabledwheninsingle-endedreceivermode(Register0x01A,Bit6=0).
1:REFBpinenabled.
0:REFBpinenabled.
0REFAsingle-endedreceivermodeenable(CMOSmode)Selectswhichsingle-endedinputpinisenabledwheninsingle-endedreceivermode(Register0x01A,Bit5=0).
1:REFApinenabled.
0:REFApinenabled.
AD9524DataSheetRev.
F|Page46of56Table43.
PLL1MiscellaneousControlAddressBitsBitNameDescription0x01C7EnableREFBRdividerindependentdivisioncontrol1:REFBRdivideriscontrolledbyRegister0x012andRegister0x013.
0:REFBRdividerissettothesamesettingastheREFARdivider(Register0x010andRegister0x011).
Thisrequiresthat,forthelooptostaylocked,theREFAandREFBinputfrequenciesmustbethesame.
6OSC_CTRLcontrolvoltagetoVCC/2whenreferenceclockfailsHighpermitstheOSC_CTRLcontrolvoltagetobeforcedtomidsupplywhenthefeedbackorinputclocksfail.
Lowtristatesthechargepumpoutput.
1:OSC_CTRLcontrolvoltagegoestoVCC/2.
0:OSC_CTRLcontrolvoltagetracksthetristated(highimpedance)chargepump(throughthebuffer).
5ReservedReserved.
[4:2]ReferenceselectionmodeProgramstheREFA,REFBmodeselection(default=000).
REF_SELPinBit4Bit3Bit2DescriptionX1000Nonrevertive:stayonREFB.
X1001ReverttoREFA.
X1010SelectREFA.
X1011SelectREFB.
01X1X1REF_SELpin=0(low):REFA.
11X1X1REF_SELpin=1(high):REFB.
[1:0]Reserved0:reserved(default).
1X=don'tcare.
Table44.
PLL1LoopFilterZeroResistorControlAddressBitsBitNameDescription0x01D[7:4]ReservedReserved.
[3:0]PLL1loopfilter,RZEROProgramsthevalueofthezeroresistor,RZERO.
Bit3Bit2Bit1Bit0RZEROValue(k)00008830001677001034100111350100100101100110100111101000UseexternalresistorDataSheetAD9524Rev.
F|Page47of56OutputPLL(PLL2)(Address0x0F0toAddress0x0F9)Table45.
PLL2ChargePumpControlTable46.
PLL2FeedbackNDividerControlTable47.
PLL2ControlAddressBitsBitNameDescription0x0F27PLL2lockdetectorpower-downControlspower-downofthePLL2lockdetector.
1:lockdetectorpowereddown.
0:lockdetectoractive.
6ReservedDefault=0;valuemustremain0.
5EnablefrequencydoublerEnablesdoublingofthePLL2referenceinputfrequency.
1:enabled.
0:disabled.
4EnableSPIcontrolofantibacklashpulsewidthControlsthefunctionalityofRegister0x0F2,Bits[3:2].
Settheantibacklashpulsewidthtotheminimumsetting.
BysettingBit4to1fromthedefaultof0,Bits[3:2]consequentlydefaultto00.
0(default):deviceautomaticallycontrolstheantibacklashperiodtohigh(equivalenttoRegister0x0F2,Bits[3:2]=10).
1:antibacklashperioddefinedbyRegister0x0F2,Bits[2:1](recommendedsetting).
[3:2]AntibacklashpulsewidthcontrolControlsthePFDantibacklashperiod.
ThesebitsdefaulttothehighsettingunlessreprogrammedusingRegister0x0F2[4]=1b.
ThehighsettingdecreasesthemaximumallowablePLL2PFDrate.
SeeTable12forranges.
00minimum.
01:low.
10:high(initialstateunlesschangedviaRegister0x0F2[4]=1b).
11:maximum.
[1:0]PLL2chargepumpmodeControlsthemodeofthePLL2chargepump.
00:tristate.
01:pumpup.
10:pumpdown.
11(default):normal.
AddressBitsBitNameDescription0x0F0[7:0]PLL2chargepumpcontrolThesebitssetthemagnitudeofthePLL2chargepumpcurrent.
Granularityis~3.
5μAwithafull-scalemagnitudeof~900μA.
AddressBitsBitNameDescription0x0F1[7:6]AcounterAcounterword[5:0]BcounterBcounterwordFeedbackDividerConstraintsACounter(Bits[7:6])BCounter(Bits[5:0])AllowedNDivision(4*B+A)A=0orA=1B=416,17A=0toA=2B=520,21,22A=0toA=2B=624,25,26A=0toA=3B≥728,29…continuousto255AD9524DataSheetRev.
F|Page48of56Table48.
VCOControlAddressBitsBitNameDescription0x0F3[7:5]ReservedReserved.
4ForcereleaseofdistributionsyncwhenPLL2isunlocked0(default):distributionisheldinsync(static)untiltheoutputPLLlocks.
Thenitisautomaticallyreleasedfromsyncwithalldividerssynchronized.
1:overridesthePLL2lockdetectorstate;forcesreleaseofthedistributionfromsync.
3Reserved0(default):valuemustremain0.
2ForceVCOtomidpointfrequencySelectsVCOcontrolvoltagefunctionality.
0(default):normalVCOoperation.
1:forcesVCOcontrolvoltagetomidscale.
1CalibrateVCO(notautoclearing)1:initiatesVCOcalibration(thisisnotanautoclearingbit).
0:resetstheVCOcalibration.
0ReservedReserved.
Table49.
VCODividerControlAddressBitsBitNameDescription0x0F4[7:4]ReservedReserved.
3VCOdividerpower-down1:powersdownthedivider.
0:normaloperation.
[2:0]VCOdividerNotethattheVCOdividerconnectstoalloutputchannels.
Bit2Bit1Bit0DividerValue000Divide-by-4001Divide-by-5010Divide-by-6011Divide-by-7100Divide-by-8101Divide-by-9110Divide-by-10111Divide-by-11DataSheetAD9524Rev.
F|Page49of56Table50.
PLL2LoopFilterControlAddressBitsBitNameDescription0x0F5[7:6]Pole2resistor(RPOLE2)Bit7Bit6RPOLE2()00900014501030011225[5:3]Zeroresistor(RZERO)Bit5Bit4Bit3RZERO()00032500012750010225001121001003000101250011020001111850[2:0]Pole1capacitor(CPOLE1)Bit2Bit1Bit0CPOLE1(pF)000000180101601124100241013211040111480x0F6[7:1]ReservedReserved.
0BypassinternalRZEROresistorBypassestheinternalRZEROresistor(RZERO=0).
Requirestheuseofaseriesexternalzeroresistor.
ThisbitistheMSBoftheloopfiltercontrolregister(Address0x0F5andAddress0x0F6).
AD9524DataSheetRev.
F|Page50of56Reserved(Address0x190)Table51.
ReservedRegisterAddressBitsBitNameDescription0x190[7:5]ReservedReserved.
Thedefaultvalueforthisregisteris0x00.
Itisrecommendedtowriteavalueof0x20tothisregister.
ClockDistribution(Address0x196toAddress0x1A1,Address0x1AEtoAddress0x1B3,Address0x1BA,andAddress0x1BB)Table52.
Channel0toChannel5Control(Thissamemapappliestoallsixchannels.
)AddressBitsBitNameDescription0x1967InvertdivideroutputInvertsthepolarityofthedivider'soutputclock.
6Ignoresync0:obeyschip-levelSYNCsignal(default).
1:ignoreschip-levelSYNCsignal.
5Power-downchannel1:powersdowntheentirechannel.
0:normaloperation.
4Lowerpowermode(differentialmodesonly)Reducespowerusedinthedifferentialoutputmodes(LVDS/LVPECL/HSTL).
Thisreductionmayresultinpowersavings,butattheexpenseofperformance.
Notethatthisbitdoesnotaffectoutputswingandcurrent,justtheinternaldriverpower.
1:lowstrength/lowerpower.
0:normaloperation.
[3:0]DrivermodeDrivermode.
Bit3Bit2Bit1Bit0DriverMode0000Tristateoutput0001LVPECL(8mA)0010LVDS(3.
5mA)0011LVDS(7mA)0100HSTL-0(16mA)0101HSTL-1(8mA)0110CMOS(bothoutputsinphase)+Pin:truephaserelativetodivideroutputPin:truephaserelativetodivideroutput0111CMOS(oppositephasesonoutputs)+Pin:truephaserelativetodivideroutputPin:complementphaserelativetodivideroutput1000CMOS+Pin:truephaserelativetodivideroutputPin:high-Z1001CMOS+Pin:high-ZPin:truephaserelativetodivideroutput1010CMOS+Pin:high-ZPin:high-Z1011CMOS(bothoutputsinphase)+Pin:complementphaserelativetodivideroutputPin:complementphaserelativetodivideroutput1100CMOS(bothoutputsoutofphase)+Pin:complementphaserelativetodivideroutputPin:truephaserelativetodivideroutput1101CMOS+Pin:complementphaserelativetodivideroutputPin:high-Z1110CMOS+Pin:high-ZPin:complementphaserelativetodivideroutputDataSheetAD9524Rev.
F|Page51of56AddressBitsBitNameDescription1111Tristateoutput0x197[7:0]Channeldivider,Bits[7:0](LSB)Division=ChannelDividerBits[9:0]+1.
Forexample,[9:0]=0isdividedby1,[9:0]=1isdividedby2…[9:0]=1023isdividedby1024.
10-bitchanneldivider,Bits[7:0](LSB).
0x198[7:2]DividerphaseDividerinitialphaseafterasyncisassertedrelativetothedividerinputclock(fromtheVCOdivideroutput).
LSB=ofaperiodofthedividerinputclock.
Phase=0:nophaseoffset.
Phase=1:periodoffset,…Phase=63:31periodoffset.
[1:0]Channeldivider,Bits[9:8](MSB)10-bitchanneldivider,Bits[9:8](MSB).
Table53.
PLL1OutputControl(PLL1_OUT,Pin46)AddressBitsBitNameDescription0x1BA[7:5]ReservedReserved4PLL1outputCMOSdriverstrengthCMOSdriverstrength1:weak0:strong[3:0]PLL1outputdivider0000:divide-by-10001:divide-by-2(default)0010:divide-by-40100:divide-by-81000:divide-by-16NootherinputspermittedTable54.
PLL1OutputChannelControlAddressBitsBitNameDescription0x1BB7PLL1outputdriverpower-downPLL1outputdriverpower-down[6:2]ReservedReserved1RouteVCXOclocktoChannel1dividerinput1:channelusesVCXOclock.
RoutesVCXOclocktodividerinput0:channelusesVCOdivideroutputclock0RouteVCXOclocktoChannel0dividerinput1:channelusesVCXOclock.
RoutesVCXOclocktodividerinput0:channelusesVCOdivideroutputclockReadback(Address0x22CtoAddress0x22D)Table55.
ReadbackRegisters(Readback0andReadback1)AddressBitsBitNameDescription0x22C7StatusPLL2referenceclock1:OK0:off/clocksaremissing6StatusPLL1feedbackclock1:OK0:off/clocksaremissing5StatusVCXO1:OK0:off/clocksaremissing4StatusREF_TEST1:OK0:off/clocksaremissing3StatusREFB1:OK0:off/clocksaremissing2StatusREFA1:OK0:off/clocksaremissing1LockdetectPLL21:locked0:unlocked0LockdetectPLL11:locked0:unlockedAD9524DataSheetRev.
F|Page52of56AddressBitsBitNameDescription0x22D[7:4]ReservedReserved3Holdoveractive1:holdoverisactive(bothreferencesaremissing)0:normaloperation2Selectedreference(inautomode)Selectedreference(appliesonlywhenthedeviceautomaticallyselectsthereference;forexample,notinmanualcontrolmode)1:REFB0:REFA1ReservedReserved0VCOcalibrationinprogress1:VCOcalibrationinprogress0:VCOcalibrationnotinprogressOther(Address0x230toAddress0x234)Table56.
StatusSignalsAddressBitsBitNameDescription0x230[7:6]ReservedReserved[5:0]StatusMonitor0controlBit5Bit4Bit3Bit2Bit1Bit0Muxout000000GND000001PLL1andPLL2locked000010PLL1locked000011PLL2locked000100Bothreferencesaremissing(REFAandREFB)000101BothreferencesaremissingandPLL2islocked000110REFBselected(appliesonlytoautoselectmode)000111REFAisOK001000REFBisOK001001REF_TESTisOK001010VCXOisOK001011PLL1feedbackisOK001100PLL2referenceclockisOK001101Reserved001110REFAandREFBareOK001111AllclocksareOK(exceptREF_TEST)010000PLL1feedbackisdivide-by-2010001PLL1PFDdowndivide-by-2010010PLL1REFdivide-by-2010011PLL1PFDupdivide-by-2010100GND010101GND010110GND010111GNDNotethatallbitcombinationsafter010111arereserved.
DataSheetAD9524Rev.
F|Page53of56AddressBitsBitNameDescription0x231[7:6]ReservedReserved.
[5:0]StatusMonitor1controlBit5Bit4Bit3Bit2Bit1Bit0Muxout000000GND000001PLL1andPLL2locked000010PLL1locked000011PLL2locked000100Bothreferencesaremissing(REFAandREFB)000101BothreferencesaremissingandPLL2islocked000110REFBselected(appliesonlytoautoselectmode)000111REFAisOK001000REFBisOK001001REF_TESTisOK001010VCXOisOK001011PLL1feedbackisOK001100PLL2referenceclockisOK001101Reserved001110REFAandREFBareOK001111AllclocksareOK(exceptREF_TEST)010000GND010001GND010010GND010011GND010100PLL2feedbackisdivide-by-2010101PLL2PFDdowndivide-by-2010110PLL2REFdivide-by-2010111PLL2PFDupdivide-by-2Notethatallbitcombinationsafter010111arereserved.
0x232[7:5]ReservedReserved.
4EnableStatus_EEPROMonSTATUS0pinEnablestheEEPROMstatusontheSTATUS0pin.
1:enablestatus.
3STATUS1pindividerenableEnablesadivide-by-4ontheSTATUS1pin,allowingdynamicsignalstobeviewedatalowerfrequency(suchasthePFDinputclocks).
Nottobeusedwithdcstatesonthestatuspins,whichoccurwhenthesettingsofRegister0x231,Bits[5:0]areintherangeof000000to001111.
1:enabled.
0:disabled.
2STATUS0pindividerenableEnablesadivide-by-4ontheSTATUS0pin,allowingdynamicsignalstobeviewedatalowerfrequency(suchasthePFDinputclocks).
Nottobeusedwithdcstatesonthestatuspins,whichoccurwhenthesettingsofRegister0x230,Bits[5:0]areintherangeof000000to001111.
1:enable.
0:disable.
1ReservedReserved.
0Syncdividers(manualcontrol)Setbittoputdividersinsync;clearbittorelease.
FunctionslikeSYNCpinlow.
1:sync.
0:normal.
AD9524DataSheetRev.
F|Page54of56Table57.
Power-DownControlAddressBitsBitNameDescription0x233[7:3]ReservedReserved.
2PLL1power-down1:power-down(default).
0:normaloperation.
1PLL2power-down1:power-down(default).
0:normaloperation.
0Distributionpower-downPowersdownthedistribution.
1:power-down(default).
0:normaloperation.
Table58.
UpdateAllRegistersAddressBitsBitNameDescription0x234[7:1]ReservedReserved.
0IO_UpdateThisbitmustbesetto1totransferthecontentsofthebufferregistersintotheactiveregisters,whichhappensonthenextSCLKrisingedge.
Thisbitisselfclearing;thatis,itdoesnothavetobesetbackto0.
1(selfclearing):updateallactiveregisterstothecontentsofthebufferregisters.
EEPROMBuffer(Address0xA00toAddress0xA16)Table59.
EEPROMBufferSegmentAddressBitsBitNameDescription0xA00to0xA16[7:0]EEPROMBufferSegmentRegister1toEEPROMBufferSegmentRegister23TheEEPROMbuffersegmentsectionstoresthestartingaddressandnumberofbytesthataretobestoredandreadbacktoandfromtheEEPROM.
Becausetheregisterspaceisnoncontiguous,theEEPROMcontrollerneedstoknowthestartingaddressandnumberofbytesintheregisterspacetostoreandretrievefromtheEEPROM.
Inaddition,therearespecialinstructionsfortheEEPROMcontroller:operationalcodes(thatis,IO_Updateandend-of-data)thatarealsostoredintheEEPROMbuffersegment.
Theon-chipdefaultsettingoftheEEPROMbuffersegmentregistersisdesignedsuchthatallregistersaretransferredto/fromtheEEPROM,andanIO_Updateisissuedafterthetransfer(seetheProgrammingtheEEPROMBufferSegmentsection).
EEPROMControl(Address0xB00toAddress0xB03)Table60.
Status_EEPROMAddressBitsBitNameDescription0xB00[7:1]ReservedReserved.
0Status_EEPROM(readonly)Thisread-onlybitindicatesthestatusofthedatatransferredbetweentheEEPROMandthebufferregisterbankduringthewritingandreadingoftheEEPROM.
ThissignalisalsoavailableattheSTATUS0pinwhenRegister0x232,Bit4isset.
0:datatransferiscomplete.
1:datatransferisnotcomplete.
Table61.
EEPROMErrorCheckingReadbackAddressBitsBitNameDescription0xB01[7:1]ReservedReserved.
0EEPROMdataerror(readonly)Thisread-onlybitindicatesanerrorduringthedatatransferbetweentheEEPROMandthebuffer.
0:noerror;dataiscorrect.
1:incorrectdatadetected.
DataSheetAD9524Rev.
F|Page55of56Table62.
EEPROMControl1AddressBitsBitNameDescription0xB02[7:2]ReservedReserved.
1Soft_EEPROMWhentheEEPROM_SELpinistiedlow,settingtheSoft_EEPROMbitresetstheAD9524usingthesettingssavedinEEPROM.
1:softresetwithEEPROMsettings(selfclearing).
0EnableEEPROMwriteEnablestheusertowritetotheEEPROM.
0:EEPROMwriteprotectionisenabled.
UsercannotwritetoEEPROM(default).
1:EEPROMwriteprotectionisdisabled.
UsercanwritetoEEPROM.
Table63.
EEPROMControl2AddressBitsBitNameDescription0xB03[7:1]ReservedReserved.
0REG2EEPROMTransfersdatafromthebufferregistertotheEEPROM(selfclearing).
1:settingthisbitinitiatesthedatatransferfromthebufferregistertotheEEPROM(writingprocess);itisresetbytheICmasterafterthedatatransferisdone.
AD9524DataSheetRev.
F|Page56of56OUTLINEDIMENSIONSCOMPLIANTTOJEDECSTANDARDSMO-220-VKKD-21481213373624255.
255.
10SQ4.
950.
500.
400.
300.
300.
230.
180.
80MAX0.
65TYP5.
50REFCOPLANARITY0.
080.
20REF1.
000.
850.
800.
05MAX0.
02NOMSEATINGPLANE12°MAXTOPVIEW0.
60MAX0.
60MAXPIN1INDICATOR0.
50REFPIN1INDICATOR0.
25MIN7.
107.
00SQ6.
906.
856.
75SQ6.
6506-05-2012-AFORPROPERCONNECTIONOFTHEEXPOSEDPAD,REFERTOTHEPINCONFIGURATIONANDFUNCTIONDESCRIPTIONSSECTIONOFTHISDATASHEET.
EXPOSEDPADFigure45.
48-LeadLeadFrameChipScalePackage[LFCSP_VQ]7*7mmBody,VeryThinQuad(CP-48-1)DimensionsshowninmillimetersORDERINGGUIDEModel1TemperatureRangePackageDescriptionPackageOptionAD9524BCPZ40°Cto+85°C48-LeadLeadFrameChipScalePackage[LFCSP_VQ]CP-48-1AD9524BCPZ-REEL740°Cto+85°C48-LeadLeadFrameChipScalePackage[LFCSP_VQ]CP-48-1AD9524/PCBZEvaluationBoard1Z=RoHSCompliantPart.
I2CreferstoacommunicationsprotocoloriginallydevelopedbyPhilipsSemiconductors(nowNXPSemiconductors).
2010–2015AnalogDevices,Inc.
Allrightsreserved.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
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