SMBusintelxeon

ReferenceNumber:338846-001USSecondGenerationIntelXeonScalableProcessorsDatasheet,VolumeTwo:RegistersApril20192IntelXeonScalableProcessorsDatasheet,VolumeTwo:Registers,April2019LegalLinesandDisclaimersInteltechnologies'featuresandbenefitsdependonsystemconfigurationandmayrequireenabledhardware,softwareorserviceactivation.
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IntelXeonScalableProcessors3Datasheet,VolumeTwo:Registers,April2019Contents1Introduction71.
1RegistersOverviewandConfigurationProcess.
71.
2RelatedPublications.
81.
2.
1Terminology81.
4StateofData122RegistersOverview132.
1ConfigurationRegisterRules132.
1.
1CSRAccess132.
1.
2PCIBusNumber.
142.
1.
3UncoreBusNumber.
142.
1.
4DeviceMapping.
142.
1.
5UnimplementedDevices/FunctionsandRegisters142.
1.
6MSRAccess142.
1.
7Memory-MappedI/ORegisters152.
2RegisterTerminology152.
4NotationalConventions163IntegratedMemoryController(iMC)ConfigurationRegisters193.
1Device:10,12Function0.
193.
1.
1pxpcap193.
1.
2mcmtr203.
1.
3tadwayness_[0:7]203.
1.
4mc_init_state_g213.
1.
5rcomp_timer.
223.
1.
6mh_ext_stat.
233.
1.
7smb_stat_[0:1]233.
1.
8smbcmd_[0:1]253.
1.
9smbcntl_[0:1]263.
1.
10smb_tsod_poll_rate_cntr_[0:1]273.
1.
11smb_period_cfg273.
1.
12smb_period_cntr283.
1.
13smb_tsod_poll_rate283.
1.
14pxpcap283.
1.
15spareaddresslo.
293.
1.
16sparectl293.
1.
17ssrstatus.
303.
1.
18scrubaddresslo.
303.
1.
19scrubaddresshi.
313.
1.
20scrubctl.
313.
1.
21spareinterval323.
1.
22rasenables.
323.
1.
23smisparectl.
333.
1.
24leaky_bucket_cfg333.
1.
25leaky_bucket_cntr_lo.
353.
1.
26leaky_bucket_cntr_hi.
363.
2Device10,12Functions2,3,4,5363.
2.
1pxpcap363.
2.
2pxpenhcap373.
3Device10,11,12Functions2,6373.
3.
1pxpcap373.
3.
2chn_temp_cfg.
373.
3.
3chn_temp_stat.
384IntelXeonScalableProcessorsDatasheet,VolumeTwo:Registers,April20193.
3.
4dimm_temp_oem_[0:1]383.
3.
5dimm_temp_th_[0:2]393.
3.
6dimm_temp_thrt_lmt_[0:1]393.
3.
7dimm_temp_ev_ofst_[0:1]403.
3.
8dimmtempstat_[0:1]403.
3.
9thrt_pwr_dimm_[0:1]413.
4Device10,12Functions3,7413.
4.
1correrrcnt_0.
413.
4.
2correrrcnt_1.
423.
4.
3correrrcnt_2.
423.
4.
4correrrcnt_3.
433.
4.
5correrrthrshld_0433.
4.
6correrrthrshld_1433.
4.
7correrrthrshld_2443.
4.
8correrrthrshld_3443.
4.
9correrrorstatus443.
4.
10leaky_bkt_2nd_cntr_reg.
453.
4.
11devtag_cntl_[0:7]464IntelUPIRegisters494.
1Bus:3,Device:16,14,Function:3.
494.
1.
1ktimiscstat.
495ConfigurationAgent(Ubox)Registers.
515.
1Bus:0,Device:8,Function:0515.
1.
1VID.
515.
1.
2DID515.
1.
3CPUNODEID.
515.
1.
4IntControl.
525.
1.
5GIDNIDMAP525.
1.
6UBOXErrSts535.
2Bus:0,Device:8,Function:2VID.
535.
2.
1DID535.
2.
2CPUBUSNO545.
2.
3CPUBUSNO1545.
2.
4SMICtrl546PowerControlUnit(PCU)Registers556.
1Bus:B1,Device:30,Function:0556.
1.
1VID.
556.
1.
2DID556.
1.
3PACKAGE_ENERGY_STATUS.
556.
1.
4MEM_TRML_TEMPERATURE_REPORT_0.
556.
1.
5MEM_TRML_TEMPERATURE_REPORT_1.
566.
1.
6MEM_TRML_TEMPERATURE_REPORT_2.
566.
1.
7PACKAGE_TEMPERATURE.
566.
1.
8TEMPERATURE_TARGET.
576.
2Bus:B(1),Device:30,Function:2576.
2.
1VID.
576.
2.
2DID576.
2.
3DRAM_ENERGY_STATUS.
576.
2.
4PACKAGE_RAPL_PERF_STATUS.
586.
2.
5DRAM_POWER_INFO.
586.
2.
6DRAM_RAPL_PERF_STATUS586.
2.
7THERMTRIP_CONFIG.
58IntelXeonScalableProcessors5Datasheet,VolumeTwo:Registers,April2019Tables1-1RelatedPublications.
82-1RegisterAttributesDefinitions.
156IntelXeonScalableProcessorsDatasheet,VolumeTwo:Registers,April2019RevisionHistory§DocumentNumberRevisionNumberDescriptionDate338846001InitialReleaseApril2019SecondGenerationIntelXeonProcessorScalableFamily7Datasheet,VolumeTwo:Registers,April20191IntroductionTheDatasheetVolume2providesconfigurationspaceregisters(CSRs).
Note:Unlessspecifiedotherwise,"processor"willrepresentthefollowingprocessorsthroughouttherestofthedocument.
SecondGenerationIntelXeonBronze3XXXprocessorSecondGenerationIntelXeonSilver4XXXprocessorSecondGenerationIntelXeonGold5XXXprocessorSecondGenerationIntelXeonGold6XXXprocessorSecondGenerationIntelXeonPlatinum8XXXprocessorTheSecondGenerationIntelXeonScalableProcessorsisthenextgenerationof64-bit,multi-coreserverprocessorbuilton14-nmprocesstechnology.
Theprocessorsupportsupto46bitsofphysicaladdressspaceand48bitsofvirtualaddressspace.
TheprocessorisdesignedforaplatformconsistingofatleastoneIntelXeonProcessorScalableProcessorsandthePlatformControllerHub(PCH).
Includedinthisfamilyofprocessorsareintegratedmemorycontroller(IMC)andanIntegratedI/O(IIO)onasinglesilicondie.
Allprocessortypessupportupto48lanesofPCIExpress*3.
0linkscapableof8.
0GT/s,and4lanesofDMI3/PCIExpress3.
0.
Itfeatures2IntegratedMemoryControllers(IMC),eachIMCsupportsuptothreeDDR4channelswithupto2DIMMsperchannel.
Note:Forsupportedprocessorconfigurationsreferto:SecondGenerationIntelXeonScalableProcessorsDatasheet:Volume1-Electrical,338845.
1.
1RegistersOverviewandConfigurationProcessThisisvolumetwo(Vol2)oftheprocessorpublicdocument,whichprovidesuncoreregisterandcoreMSRinformationfortheprocessor.
ThisvolumedocumentstheConfigurationSpaceRegisters(CSRs)ofeachindividualfunctionalblockintheUncorelogic,MMIORegistersfortheIIO,andcoreMSRs.
TheprocessorcontainsoneormorePCIdeviceswithineachfunctionalblock.
TheconfigurationregistersforthesedevicesaremappedasdevicesresidingonthePCIBusassignedtotheprocessorsocket.
CSRsarethebasichardwareelementsthatconfiguretheuncorelogictosupportvarioussystemtopologies,memoryconfigurationanddensities,andhardwarehooksrequiredforRASoperations.
Note:Thecontentcontainedinthisvolumecomprehendsthedifferentprocessortypes.
Someregisterandfielddescriptionswillapplyonlytothespecificprocessortypes.
Notallfeaturesspecificforeachprocessortypehavebeenexplicitlyidentifiedinthisvolume,andnotallfeaturesdocumentedareavailableforallSKUs.
8SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April2019Note:SomeDefaultvalueswillvarybasedonprocessortypeandSKU,andinmostcasesthesearethereadonlyregisterfieldswhichprovideprocessorsupportvisibilitytofirmware.
FirmwareshouldnotrelyontheseDefaultvaluesprovidedinthisdocument,andinsteadverifythesevaluesbyreadingthemwithfirmware.
1.
2RelatedPublicationsRefertothefollowingdocumentsforadditionalinformation.
1.
2.
1TerminologyTable1-1.
RelatedPublicationsDocumentDocumentNumber/LocationSecondGenerationIntelXeonScalableProcessorsDatasheet:Volume1-Electrical338845SecondGenerationIntelXeonScalableProcessorsSpecificationUpdate338848SecondGenerationIntelXeonScalableProcessorsThermalMechanicalDesignGuidelines338847IntelC620SeriesChipsetDatasheet336067IntelC620SeriesChipsetThermalMechanicalDesignGuidelines336068Intel64andIA-32ArchitecturesSoftwareDeveloper'sManualsVolume1:BasicArchitectureVolume2A:InstructionSetReference,A-MVolume2B:InstructionSetReference,N-ZVolume3A:SystemProgrammingGuideVolume3B:SystemProgrammingGuideIntel64andIA-32ArchitecturesOptimizationReferenceManual325462http://www.
intel.
com/products/processor/manuals/index.
htmIntelVirtualizationTechnologySpecificationforDirectedI/OArchitectureSpecificationhttp://www.
intel.
com/content/www/us/en/intelligent-systems/intel-technology/vt-directed-io-spec.
htmlIntelTrustedExecutionTechnologySoftwareDevelopmentGuidehttp://www.
intel.
com/technology/security/TermDescriptionACReadandWriteAccessControlASPMActiveStatePowerManagementIntelAVXIntelAdvancedVectorExtensions(AVX)promoteslegacy128-bitSIMDinstructionsetsthatoperateonXMMregistersettousea"vectorextension"(VEX)prefixandoperateson256-bitvectorregisters(YMM).
IntelAVX512Thebaseofthe512-bitSIMDinstructionextensionsarereferredtoasIntelAVX-512foundationinstructions.
TheyincludeextensionsoftheAVXfamilyofSIMDinstructionsbutareencodedusinganewencodingschemewithsupportfor512-bitvectorregisters,upto32vectorregistersin64-bitmode,andconditionalprocessingusingopmaskregisters.
BMCBaseboardManagementControllerSecondGenerationIntelXeonProcessorScalableFamily9Datasheet,VolumeTwo:Registers,April2019CACoherencyAgent.
InsomecasesthisisreferredtoasaCachingAgentthoughaCAisnotactuallyrequiredtohaveacache.
ItisatermusedfortheinternallogicprovidingmeshinterfacetoLLCandCore.
TheCAisafunctionalunitintheCHA.
CHAThefunctionalmodulethatincludestheCA(CoherencyAgent)andHA(HomeAgent).
CPControlPolicyDDR4FourthgenerationDoubleDataRateSDRAMmemorytechnology.
DMADirectMemoryAccessDMI3DirectMediaInterfaceGen3operatingatPCIExpress3.
0speed.
DTLBDataTranslationLook-asideBuffer.
Partoftheprocessorcorearchitecture.
DTSDigitalThermalSensorECCErrorCorrectionCodeEnhancedIntelSpeedStepTechnologyAllowstheoperatingsystemtoreducepowerconsumptionwhenperformanceisnotneeded.
ExecuteDisableBitTheExecuteDisablebitallowsmemorytobemarkedasexecutableornon-executable,whencombinedwithasupportingoperatingsystem.
Ifcodeattemptstoruninnon-executablememorytheprocessorraisesanerrortotheoperatingsystem.
Thisfeaturecanpreventsomeclassesofvirusesorwormsthatexploitbufferoverrunvulnerabilitiesandcanthushelpimprovetheoverallsecurityofthesystem.
SeetheIntel64andIA-32ArchitecturesSoftwareDeveloper'sManualsformoredetailedinformation.
FLITFlowControlUnit.
TheIntelUPILinklayer'sunitoftransfer.
AFLITismadeofmultiplePHITS.
AFlitisalwaysafixedamountofinformation(192bits).
FunctionalOperationReferstothenormaloperatingconditionsinwhichallprocessorspecifications,includingDC,AC,systembus,signalquality,mechanical,andthermal,aresatisfied.
GSSEExtensionoftheSSE/SSE2(StreamingSIMDExtensions)floatingpointinstructionsetto256boperands.
HAAHomeAgent(HA)ordersreadandwriterequeststoapieceofcoherentmemory.
TheHAisimplementedintheCHAlogic.
ICUInstructionCacheUnit.
Partoftheprocessorcorearchitecture.
IFUInstructionFetchUnit.
Partoftheprocessorcore.
IIOIntegratedI/OController.
AnI/Ocontrollerthatisintegratedintheprocessordie.
TheIIOconsistsoftheDMI3module,PCIemodules,andMCP(IceLakeServerwithFabricSKUsonly)modules.
IMCIntegratedMemoryController.
AMemoryControllerthatisintegratedintheprocessordie.
IntelQuickDataTechnologyIntelQuickDataTechnologyisaplatformsolutiondesignedtomaximizethethroughputofserverdatatrafficacrossabroaderrangeofconfigurationsandserverenvironmentstoachievefaster,scalable,andmorereliableI/O.
IntelUltraPathInterconnect(IntelUPI)Acache-coherent,link-basedInterconnectspecificationforIntelprocessors.
AlsoknownasIntelUPI.
Intel64Technology64-bitmemoryextensionstotheIA-32architecture.
FurtherdetailsonIntel64architectureandprogrammingmodelcanbefoundathttp://developer.
intel.
com/technology/intel64/TermDescription10SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April2019IntelSPSFWIntelServerPlatformServicesFirmware.
TheprocessorusesIntelSPSFWinserverconfigurations.
IntelTurboBoostTechnologyAfeaturethatopportunisticallyenablestheprocessortorunafasterfrequency.
Thisresultsinincreasedperformanceofbothsingleandmulti-threadedapplications.
IntelTXTIntelTrustedExecutionTechnologyIntelVirtualizationTechnology(IntelVT)ProcessorVirtualizationwhichwhenusedinconjunctionwithVirtualMachineMonitorsoftwareenablesmultiple,robustindependentsoftwareenvironmentsinsideasingleplatform.
IntelVT-dIntelVirtualizationTechnology(IntelVT)forDirectedI/O.
IntelVT-disahardwareassist,undersystemsoftware(VirtualMachineManagerorOS)control,forenablingI/OdeviceVirtualization.
IntelVT-dalsobringsrobustsecuritybyprovidingprotectionfromerrantDMAsbyusingDMAremapping,akeyfeatureofIntelVT-d.
IntegratedHeatSpreader(IHS)Acomponentoftheprocessorpackageusedtoenhancethethermalperformanceofthepackage.
ComponentthermalsolutionsinterfacewiththeprocessorattheIHSsurface.
IOVI/OVirtualizationIVRIntegratedVoltageRegulation(IVR):Theprocessorsupportsseveralintegratedvoltageregulators.
IntelUPIIntelUltraPathInterconnect(IntelUPI)Agent.
AninternallogicblockprovidinginterfacebetweeninternalmeshandexternalIntelUPI.
LLCLastLevelCacheLRDIMMLoadReducedDualIn-lineMemoryModuleLRULeastRecentlyUsed.
Atermusedinconjunctionwithcacheallocationpolicy.
M2MMeshtoMemory.
LogicintheIMCwhichinterfacestheIMCtothemesh.
M2PCIeThelogicintheIIOmoduleswhichinterfacethemodulestothemesh.
MCPAmoduleintheIIOenabledinIceLakeServerwithFabricwhichisusedtointerfacetotheonpackageIntelOmni-Path.
MESHTheondieinterconnectwhichconnectsmodulesintheprocessor.
MESIModified/Exclusive/Shared/Invalid.
StatesusedinconjunctionwithcachecoherencyMLCMidLevelCacheNCTFNon-CriticaltoFunction:NCTFlocationsaretypicallyredundantgroundornon-criticalreserved,sothelossofthesolderjointcontinuityatendoflifeconditionswillnotaffecttheoverallproductfunctionality.
NID\NodeIDNodeID(NID)orNodeID(NID).
Theprocessorimplementsupto4-bitsofNodeID(NID).
PcodePcodeismicrocodewhichisrunonthededicatedmicrocontrollerwithinthePCU.
PCHPlatformControllerHub.
ThenextgenerationchipsetwithcentralizedplatformcapabilitiesincludingthemainI/Ointerfacesalongwithdisplayconnectivity,audiofeatures,powermanagement,manageability,securityandstoragefeatures.
PCUPowerControlUnit.
TermDescriptionSecondGenerationIntelXeonProcessorScalableFamily11Datasheet,VolumeTwo:Registers,April2019PCIExpress3.
0ThethirdgenerationPCIExpressspecificationthatoperatesattwicethespeedofPCIExpress2.
0(8Gb/s);PCIExpress3.
0iscompletelybackwardcompatiblewithPCIExpress1.
0and2.
0.
PCIExpress2.
0PCIExpressGeneration2.
0PECIPlatformEnvironmentControlInterfacePhitThedatatransferunitonIntelUPIatthePhysicallayeriscalledaPhit(physicalunit).
APhitwillbeeither20bits,or8bitsdependingonthenumberofactivelanes.
ProcessorIncludesthe64-bitcores,uncore,I/OsandpackageProcessorCoreTheterm"processorcore"referstoSidieitselfwhichcancontainmultipleexecutioncores.
EachexecutioncorehasaninstructioncacheanddatacacheandMLCcache.
AllexecutioncoressharetheL3cache.
RACReadAccessControlRankAunitofDRAMcorrespondingfourtoeightdevicesinparallel,ignoringECC.
Thesedevicesareusually,butnotalways,mountedonasinglesideofaDDR4DIMM.
RDIMM\LRDIMMRegisteredDualIn-lineMemoryModule\LoadReducedDIMMRTIDRequestTransactionIDsarecreditsissuedbytheCHAtotrackoutstandingtransaction,andtheRTIDsallocatedtoaCHAaretopologydependent.
SCISystemControlInterrupt.
UsedinACPIprotocol.
SKUStockKeepingUnit(SKU)isasubsetofaprocessortypewithspecificfeatures,electrical,powerandthermalspecifications.
NotallfeaturesaresupportedonallSKUs.
ASKUisbasedonspecificuseconditionassumption.
SSEIntelStreamingSIMDExtensions(IntelSSE)SMBusSystemManagementBus.
Atwo-wireinterfacethroughwhichsimplesystemandpowermanagementrelateddevicescancommunicatewiththerestofthesystem.
StorageConditionsAnon-operationalstate.
Theprocessormaybeinstalledinaplatform,inatray,orloose.
Processorsmaybesealedinpackagingorexposedtofreeair.
Undertheseconditions,processorlandingsshouldnotbeconnectedtoanysupplyvoltages,haveanyI/Osbiasedorreceiveanyclocks.
Uponexposureto"freeair"(thatis,unsealedpackagingoradeviceremovedfrompackagingmaterial)theprocessormustbehandledinaccordancewithmoisturesensitivitylabeling(MSL)asindicatedonthepackagingmaterial.
TACThermalAveragingConstantTDPThermalDesignPowerTSODTemperatureSensorOnDIMMUDIMMUnbufferedDualIn-lineMemoryModuleUncoreTheportionoftheprocessorcomprisingthesharedLLCcache,CHA,IMC,PCU,Ubox,IIOandIntelUPImodules.
UnitIntervalSignalingconventionthatisbinaryandunidirectional.
Inthisbinarysignaling,onebitissentforeveryedgeoftheforwardedclock,whetheritbearisingedgeorafallingedge.
Ifanumberofedgesarecollectedatinstancest1,t2,tn,.
.
.
.
,tkthentheUIatinstance"n"isdefinedas:UIn=tn-tn-1TermDescription12SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April20191.
4StateofDataThedatacontainedwithinthisdocumentispreliminary.
Itisthemostaccurateinformationavailablebythepublicationdateofthisdocument.
Theinformationinthisrevisionofthedocumentisbasedonearlydevelopmentdata.
Informationmaychangepriortoproduction.
§VolumeManagementDevice(VMD)VolumeManagementDevice(VMD)isanewtechnologyusedtoimprovePCIemanagement.
VMDmapsthePCIe*configurationspaceforchilddevices/adaptersforaparticularPCIex16moduleintoitsownaddressspace,controlledbyaVMDdriver.
VCCINPrimaryvoltageinputtothevoltageregulatorsintegratedintotheprocessor.
VSSProcessorgroundVSSASystemagentsupplyforIntelUPIandPCIeVCCIOIOvoltagesupplyinputVCCDDDRpowerrailWACWriteAccessControlx1,x4,x8,x16ReferstoaLinkorPortwithone,two,fouroreightPhysicalLane(s)TermDescriptionSecondGenerationIntelXeonProcessorScalableFamily13Datasheet,VolumeTwo:Registers,April20192RegistersOverviewThisisvolumetwo(Vol2)oftheprocessordatasheetdocumentwhichprovidestheConfigurationSpaceRegisters(CSRs)ofeachindividualfunctionalblockintheuncorelogic,MMIORegistersfortheIIO,andcoreMSRinformationfortheprocessor.
Note:ThecontentcontainedinthisvolumecomprehendsmultipleproducttypesandSKUs.
SomeregisterandfielddescriptionswillapplyonlytothespecificproducttypesandSKUs.
Notallfeaturesspecificforeachprocessortypehavebeenexplicitlyidentifiedinthisvolume,andnotallfeaturesdocumentedareavailableforallSKUs.
Note:SomeDefaultvalueswillvarybasedonprocessortypeandSKU,andinmostcasesthesearethereadonlyregisterfieldswhichprovideprocessorsupportvisibilitytofirmware.
FirmwareshouldnotrelyontheseDefaultvaluesprovidedinthisdocument,andinsteadverifythesevaluesbyreadingthemwithfirmware.
Note:Thereare2busrangessupportedfortheuncore[1-0].
TheBusNumberisconfigurableintheUbox,CSRCPUBUSNO_CFG(B(30);Device:0;Function:2,Offset:0xCC).
Thisdocumentusesthenotation:B(30)istheUncoreBus0,andB(31)istheUncoreBus1.
BydefaulttheBusNumberforCPUBUSNO0is0andCPUBUSNO1is1.
2.
1ConfigurationRegisterRulesTheprocessorsupportsthefollowingconfigurationregistertypes:PCIConfigurationRegisters(CSRs):CSRsarechipsetspecificregistersthatarelocatedatPCIdefinedaddressspace.
TheprocessorcontainsPCIdeviceswithineachfunctionalblock.
TheconfigurationregistersforthesedevicesaremappedasdevicesresidingonthePCIBusassignedtotheprocessorsocket.
CSRsarethebasichardwareelementsthatconfiguretheuncorelogictosupportvarioussystemtopologies,memoryconfigurationanddensities,andhardwarehooksrequiredforRASoperations.
—WhenVMDisenabledforaparticularrootbusintheIIO,theVMDexposestheconfigurationspaceofitschilddevicesthroughCFGBARandtheMMIOspaceofchilddevicesthroughMEMBAR.
CfgRd\Wraccessestothechilddevicewillbedropped.
AVMDdrivercanresurfacesVMDasanadditionalPCIsegment,allowingchilddevicesbehindVMDtobevisibleviastandardmethods.
Memory-mappedI/Oregisters:TheseregistersaremappedintothesystemmemorymapasMMIOloworMMIOhigh.
Theyareaccessedbyanycode,typicallyanOSdriverrunningontheplatform.
Thisregisterspaceisintroducedwiththeintegrationofsomeofthechipsetfunctionality.
TheseMMIOregistersarelocatedintheIIOmoduleforthePCIesegments.
MachineSpecificRegisters(MSRs)arearchitecturalandonlyaccessedbyusingspecificReadMSR/WriteMSRinstructionsarelocatedinthecore.
2.
1.
1CSRAccessConfigurationspaceregistersareaccessedviathewellknownconfigurationtransactionmechanismdefinedinthePCIspecificationandthisusesthebus:device:functionnumberconcepttoaddressaspecificdevice'sconfigurationspace.
IfinitiatedbyaremoteCPU,accessestoPCIconfigurationregistersareachievedviaNcCfgRd/WrtransactionsonIntelQuickPathInterconnect(IntelQPI).
14SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April2019AllconfigurationregisteraccessesareaccessedoverMessageChannelthroughtheUboxbutmightcomefromavarietyofdifferentsources:LocalcoresRemotecores(overIntelQPI)ConfigurationregisterscanbereadorwritteninByte,WORD(16-bit),orDWORD(32-bit)quantities.
AccesseslargerthanaDWORDtoPCIExpressconfigurationspacewillresultinunexpectedbehavior.
Allmulti-bytenumericfieldsuse"little-endian"ordering(thatis,loweraddressescontaintheleastsignificantpartsofthefield).
2.
1.
2PCIBusNumberInthetablesshownforIIOdevices(0-7),thePCIBusnumbersareallmarkedas"Bus0".
Thismeansthattheactualbusnumberisvariabledependingonwhichsocketisused.
ThespecificbusnumberforallPCIedevicesintheSecondGenerationIntelXeonProcessorE5v4productfamilyisspecifiedintheCPUBUSNOregisterwhichexistsintheI/Omodule'sconfigurationspace.
Busnumberisderivedbythemaxbusrangesettingandprocessorsocketnumber.
2.
1.
3UncoreBusNumberThePCIBusnumbersareallmarkedas"bus1".
ThismeansthattheactualbusnumberisCPUBUSNO(1),whereCPUBUSNO(1)isprogrammablebyBIOSdependingonwhichsocketisused.
ThespecificbusnumberforallPCIedevicesintheSecondGenerationIntelXeonProcessorE5v4productfamilyisspecifiedintheCPUBUSNOregister.
2.
1.
4DeviceMappingEachcomponentintheprocessorisuniquelyidentifiedbyaPCIbusaddressconsistingofBusNumber,DeviceNumberandFunctionNumber.
DeviceconfigurationisbasedonthePCIType0configurationconventions.
AllprocessorregistersappearonthePCIbusassignedfortheprocessorsocket.
Busnumberisderivedbythemaxbusrangesettingandprocessorsocketnumber.
2.
1.
5UnimplementedDevices/FunctionsandRegistersConfigurationreadstounimplementedfunctionsanddeviceswillreturnallonesemulatingamasterabortresponse.
Notethatthereisnoasynchronouserrorreportingthathappenswhenaconfigurationreadmasteraborts.
Configurationwritestounimplementedfunctionsanddeviceswillreturnanormalresponse.
Softwareshouldnotattemptorrelyonreadsorwritestounimplementedregistersorregisterbits.
Unimplementedregistersshouldreturnallzeroeswhenread.
Writestounimplementedregistersareignored.
Forconfigurationwritestotheseregister(requireacompletion),thecompletionisreturnedwithanormalcompletionstatus(notmaster-aborted).
2.
1.
6MSRAccessMachinespecificregistersarearchitecturalandonlyaccessedbyusingspecificReadMSR/WriteMSRinstructions.
MSRsarealwaysaccessedasanaturallyaligned4or8bytequantity.
SecondGenerationIntelXeonProcessorScalableFamily15Datasheet,VolumeTwo:Registers,April2019ForcommonIA-32architecturalMSRs,pleaserefertotheIntel64andIA-32SoftwareDeveloper'sManual.
2.
1.
7Memory-MappedI/ORegistersThePCIstandardprovidesnotonlyconfigurationspaceregistersbutalsoregisterswhichresideinmemory-mappedspace.
ForPCIdevices,thisistypicallywherethemajorityofthedriverprogrammingoccursandthespecificregisterdefinitionsandcharacteristicsareprovidedbythedevicemanufacturer.
AccesstotheseregistersaretypicallyaccomplishedviaCPUreadsandwritestonon-coherent(UC)orwritecombining(WC)space.
Readsandwritestomemory-mappedregisterscanbeaccomplishedwith1,2,4or8bytetransactions.
2.
2RegisterTerminologyThebitsinconfigurationregisterdescriptionswillhaveanassignedattributefromthefollowingtable.
BitswithoutaStickyattributearesettotheirdefaultvaluebyahardreset.
Table2-1.
RegisterAttributesDefinitions(Sheet1of2)AttributeDescriptionROReadOnly:Thesebitscanonlybereadbysoftware,writeshavenoeffect.
Thevalueofthebitsisdeterminedbythehardwareonly.
RWRead/Write:Thesebitscanbereadandwrittenbysoftware.
RCReadClearVariant:Thesebitscanbereadbysoftware,andtheactofreadingthemautomaticallyclearsthem.
HWisresponsibleforwritingthesebits,andthereforethe-Vmodifierisimplied.
W1SWrite1toSet:Writinga1tothesebitswillsetthemto1.
Writing0willhavenoeffect.
Readingwillreturnindeterminatevalues.
WOWriteOnly:Thesebitscanonlybewrittenbymicrocode,readsreturnindeterminatevalues.
Microcodethatwantstoensurethisbitwaswrittenmustreadwherevertheside-effecttakesplace.
RW-ORead/WriteOnce:Thesebitscanbereadbysoftware.
Afterreset,thesebitscanonlybewrittenbysoftwareonce,afterwhichthebitsbecomes'ReadOnly'.
RW-LRead/WriteLock:Thesebitscanbereadandwrittenbysoftware.
Thebitscanbemadetobe'ReadOnly'viaaseparateconfigurationbitorotherlogic.
RW-KLRead/WriteLock:Thesebitscanbereadandwrittenbysoftware.
Thebitscanbemadetobe'ReadOnly'viaaseparateconfigurationbitorotherlogic.
Fieldswiththisattributealsoactasthelockingagentforotherfields.
RW1CRead/Write1toClear:Thesebitscanbereadandclearedbysoftware.
Writinga'1'toabitclearsit,whilewritinga'0'toabithasnoeffect.
RW0CRead/Write0toClear:Thesebitscanbereadandclearedbysoftware.
Writinga'0'toabitclearsitwhilewritinga'1'hasnoeffect.
ROSROSticky:Thesebitscanonlybereadbysoftware,writeshavenoeffect.
Thevalueofthebitsisdeterminedbythehardwareonly.
Thesebitsareonlyre-initializedtotheirdefaultvaluebyaPWRGOODreset.
RW1SRead,Write1toSet:Thesebitscanberead.
Writinga1toagivenbitwillsetitto1.
Writinga0toagivenbitwillhavenoeffect.
Itisnotpossibleforsoftwaretosetabitto"0".
The1->0transitioncanonlybeperformedbyhardware.
Theseregistersareimplicitly-V.
RWSR/WSticky:Thesebitscanbereadandwrittenbysoftware.
Thesebitsareonlyre-initializedtotheirdefaultvaluebyaPWRGOODreset.
RW1CSR/W1CSticky:Thesebitscanbereadandclearedbysoftware.
Writinga'1'toabitclearsit,whilewritinga'0'toabithasnoeffect.
Thesebitsareonlyre-initializedtotheirdefaultvaluebyaPWRGOODreset.
16SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April20192.
4NotationalConventionsHexadecimalandBinaryNumbersBase16numbersarerepresentedbyastringofhexadecimaldigitsfollowedbythecharacterH(forexample,F82EH).
Ahexadecimaldigitisacharacterfromthefollowingset:0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,andF.
Hexadecimalnumberscanalsobeshownusingan"x"character(forexample0x2A).
Base2(binary)numbersarerepresentedbyastringof1sand0s,sometimesfollowedbythecharacterB(forexample,101B).
The"B"designationisonlyusedinsituationswhereconfusionastothetypeofthenumbermightarise.
RW-LBRead/WriteLockBypass:SimilartoRWL,thesebitscanbereadandwrittenbysoftware.
HWcanmakethesebits"ReadOnly"viaaseparateconfigurationbitorotherlogic.
However,RW-LBisaspecialcasewherethelockingiscontrolledbythelock-bypasscapabilitythatiscontrolledbythelock-bypassenablebits.
Eachlock-bypassenablebitenablesasetofconfigrequestsourcesthatcanbypassthelock.
Therequestssourcedfromthecorrespondingbypassenablebitswillbelock-bypassed(i.
e.
RW)whilerequestssourcedfromothersourcesareunderlockcontrol(RO).
ThelockbitandbypassenablebitaregenerallydefinedwithRWOattributes.
Stickycanbeusedwiththisattribute(RW-SWB).
ThesebitsareonlyreinitializedtotheirdefaultvaluesafterPWRGOOD.
Notethatthelockbitsmaynotbesticky,anditisimportantthattheyarewrittentoafterresettoguaranteethatsoftwarewillnotbeabletochangetheirvaluesafterareset.
RO-FWReadOnlyForcedWrite:Thesebitsarereadonlyfromtheperspectiveofthecores.
RWS-OIfaregisterisbothstickyand"once"thenthestickyvalueappliestoboththeregistervalueandthe"once"characteristic.
OnlyaPWRGOODresetwillresetboththevalueandthe"once"sothattheregistercanbewrittentoagain.
RW-V/RO-VThesebitsmaybemodifiedbyhardware.
Softwarecannotexpectthevaluestostayunchanged.
Thisissimilarto"volatile"insoftwareland.
RWS-VThesebitscanbereadorwrittenbysoftwareandmaybemodifiedbyhardware.
Softwarecannotexpectthevaluestostayunchanged.
Thesebitsarere-initializedtotheirdefaultvaluesbyaPWRGOODreset.
RWS-LIfaregisterisbothstickyandlocked,thenthestickybehavioronlyappliestothevalue.
Thestickybehaviorofthelockisdeterminedbytheregisterthatcontrolsthelock.
RWS-LVThesebitscanbereadorwrittenbysoftwareandmaybemodifiedbyhardware.
Softwarecannotexpectthevaluestostayunchanged.
Thesebitsarere-initializedtotheirdefaultvaluesbyaPWRGOODreset.
Ifaregisterisbothstickyandlocked,thenthestickybehavioronlyappliestothevalue.
Thestickybehaviorofthelockisdeterminedbytheregisterthatcontrolsthelock.
SMM-ROReadOnlyinSMM:ThesebitscanonlybereadbysoftwarewhileinSMM.
WritesinSMMhavenoeffect.
AttemptingtoreadorwritethesebitsoutsideofSMMwillcausea#GPexceptiontoberaised.
R/SMM-WRead/WriteOnlyinSMM:ThesebitscanbereadbysoftwareinsideoroutsideofSMMbutcanonlybewrittenbysoftwarewhileinSMM.
AttemptingtowritethesebitsoutsideofSMMwillcausea#GPexceptiontoberaised.
SMM-RWReadOnlyinSMM/WriteOnlyinSMM:ThesebitscanonlybereadandwrittenbysoftwarewhileinSMM.
AttemptingtowritethesebitsoutsideofSMMwillcausea#GPexceptiontoberaised.
SMM-RW1CRead/Write1toClearinSMM:ThesebitscanbereadandclearedbysoftwareonlywhileinSMM.
Writinga'1'toabitclearsit,whilewritinga'0'toabithasnoeffect.
RSVD-PReserved-Protected:Thesebitsarereservedforfutureexpansionandtheirvaluemustnotbemodifiedbysoftware.
Whenwritingthesebits,softwaremustpreservethevalueread.
RSVD-ZReserved-Don'tCare:Thesebitsarereservedforfutureexpansionandmodifyingtheirvaluehasnoeffect.
Softwaredoesnotneedtopreservethevalueread.
Table2-1.
RegisterAttributesDefinitions(Sheet2of2)AttributeDescriptionSecondGenerationIntelXeonProcessorScalableFamily17Datasheet,VolumeTwo:Registers,April2019Base10numbersarerepresentedbyastringofdecimaldigitsfollowedbythecharacterD(forexample,23D).
The"D"designationisonlyusedinsituationswhereconfusionastothetypeofthenumbermightarise.
§18SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April2019IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily19Datasheet,VolumeTwo:RegistersApril20193IntegratedMemoryController(iMC)ConfigurationRegistersTheIntegratedMemoryControllerregistersarelistedbelowandarespecifictoTheSecondGenerationIntelXeonProcessorscalablefamilyimplement2MemoryControllerseachwith3DDR4memorychannels,2DIMMsperchannel.
—TheIMCRegistersareimplementedinthefollowingBus,Device,Functions:Bus:B(2),Device:10,12,Function:0—Device10appliestoIMC0—Device12appliestoIMC1.
ForDevice10and12Functions0-5foroffsets>=256,PCIeextendedconfigurationspacearenotdesignedfordirectusagebyOSordevicedrivers,andmaynotbeaccessibledirectlybyOScomponentssuchasdevicedrivers.
ThePCICapabilityPointerRegister(CAPPTR)issettoavalueof40h.
BIOS/firmwareand/orBMCcanaccesstheseregisters,combinetheinformationobtainedwithsystemimplementationspecifics,andifrequired,makeitavailabletotheOSthroughfirmwareand/orBMCinterfaces.
3.
1Device:10,12Function03.
1.
1pxpcapPCIExpressCapability.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0x40BitAttrDefaultDescription29:25RO0x0InterruptMessageNumber(interrupt_message_number):N/Aforthisdevice24:24RO0x0SlotImplemented(slot_implemented):N/Aforintegratedendpoints23:20RO0x9Device/PortType(device_port_type):DevicetypeisRootComplexIntegratedEndpoint19:16RO0x1CapabilityVersion(capability_version):PCIExpressCapabilityisCompliantwithVersion1.
0ofthePCIExpressSpec.
Note:ThiscapabilitystructureisnotcompliantwithVersionsbeyond1.
0,sincetheyrequireadditionalcapabilityregisterstobereserved.
Theonlypurposeforthiscapabilitystructureistomakeenhancedconfigurationspaceavailable.
Minimizingthesizeofthisstructureisaccomplishedbyreportingversion1.
0complianceandreportingthatthisisanintegratedrootportdevice.
Assuch,onlythreeDwordsofconfigurationspacearerequiredforthisstructure.
15:8RO0x0NextCapabilityPointer(next_ptr):Pointertothenextcapability.
Setto0toindicatetherearenomorecapabilitystructures.
IntegratedMemoryController(iMC)ConfigurationRegisters20SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
1.
2mcmtrMemoryTechnology3.
1.
3tadwayness_[0:7]TADRangeWayness,LimitandTarget.
Therearetotalof8TADranges(N+P+1=numberofTADranges;P=howmanytimeschannelinterleavechangeswithintheSADranges.
).
7:0RO0x10CapabilityID(capability_id):ProvidesthePCIExpresscapabilityIDassignedbyPCI-SIG.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0x40BitAttrDefaultDescriptionType:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0x87cBitAttrDefaultDescription21:18RW_LB0x0CHN_DISABLE(chn_disable):Channeldisablecontrol.
Whenset,thecorrespondingchannelisdisabled.
17:16RW_LB0x0pass76(pass76):00:donotalterChnAddcalculation01:replaceChnAdd[6]withSysAdd[6]10:Reserved11:replaceChnAdd[7:6]withSysAdd[7:6]14RW_LB0x0ddr4(ddr4):DDR4mode13:12RW_LB0x0IMC_MODE(imc_mode):Memorymode:00:NativeDDRAllothersreserved.
8:8RW_LB0x0NORMAL(normal):0:Trainingmode1:NormalMode3:3RW_LBV0x0DIR_EN(dir_en):IfthedirectorydisabledinSKU,thisregisterbitissettoRead-Only(RO)with0value,thatis,thedirectoryisdisabled.
Whenthisbitissettozero,IMCECCcodeusesthenon-directoryCRC-16.
IftheSKUsupportsdirectoryandenabled,thatis,thedirectoryisnotdisabled,theDIR_ENbitcanbesetbyBIOS,MCECCusesCRC-15inthefirst32Bcodewordtoyieldonedirectorybit.
ItisimportanttoknowthatchangingthisbitwillrequireBIOStore-initializethememory.
2:2RW_LBV0x0ECC_EN(ecc_en):ECCenable.
DISECCwillforceoverridethisbitto0.
1:1RW_LBV0x0LS_EN(ls_en):Uselock-stepchannelmodeifset;otherwise,independentchannelmode.
ThisfieldshouldonlybesetfornativeDDRlockstep.
0:0RW_LB0x0CLOSE_PG(close_pg):Useclosepageaddressmappingifset;otherwise,openpage.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily21Datasheet,VolumeTwo:RegistersApril2019Noteformirroringconfiguration:For1-wayinterleave,channel0-2mirrorpair:targetlist,TADways="00"For1-wayinterleave,channel1-3mirrorpair:targetlist,TADways="00"For2-wayinterleave,0-2mirrorpairand1-3mirrorpair:targetlist,TADways="01"For1-wayinterleave,lockstepmirroring,targetlist,TADways="00"3.
1.
4mc_init_state_gInitializationstateforbootandtraining.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0x80,0x84,0x88,0x8c,0x90,0x94,0x98,0x9c,0xa0,0xa4,0xa8,0xacBitAttrDefaultDescription31:12RW_LB0x0TAD_LIMIT(tad_limit):Highestaddressoftherangeinsystemaddressspace,64MBgranularity,i.
e.
TADRANGLIMIT[45:26].
11:10RW_LB0x0ReservedTAD_SKT_WAY(tad_skt_way):socketinterleavewayness00=1way,01=2way,10=4way,11=8way.
9:8RW_LB0x0TAD_CH_WAY(tad_ch_way):Channelinterleavewayness00-interleaveacross1channelormirrorpair01-interleaveacross2channelsormirrorpairs10-interleaveacross3channels11-interleaveacross4channelsThisparametereffectivelytellsiMChowmuchtodividethesystemaddressbywhenadjustingforthechannelinterleave.
Sincebothchannelsinapairstoreeverylineofdata,divideby1wheninterleavingacrossonepairand2wheninterleavingacrosstwopairs.
ForHA,ittellshowmaychannelstodistributethereadrequestsacross.
Wheninterleavingacross1pair,thisdistributesthereadstotwochannels,wheninterleavingacross2pairs,thisdistributesthereadsacross4pairs.
Writesalwaysgotobothchannelsinthepairwhenthereadtargetiseitherchannel.
7:6RW_LB0x0Reserved5:4RW_LB0x0Reserved3:2RW_LB0x0Reserved1:0RW_LB0x0ReservedIntegratedMemoryController(iMC)ConfigurationRegisters22SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
1.
5rcomp_timerRCOMPwaittimer.
DefinesthetimefromIOstartingtorunRCOMPevaluationuntilRCOMPresultsaredefinitelyready.
Thiscounterisaddedinordertokeepdeterminismoftheprocessifoperatedindifferentmode.
ThisregisteralsoindicatesthatfirstRCOMPhasbeendone-requiredbyBIOS.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0x8b4BitAttrDefaultDescription12:9RWS_L0x0cs_oe_en:8:8RWS_L0x1MCisinSR(safe_sr):ThisbitindicatesifitissafetokeeptheMCinselfrefresh(SR)duringMC-reset.
Ifitisclearwhenresetoccurs,itmeansthattheresetiswithoutwarningandtheDDR-resetshouldbeasserted.
Ifsetwhenresetoccurs,itindicatesthatDDRisalreadyinSRanditcankeepitthisway.
ThisbitcanalsoindicateMRCifresetwithoutwarninghasoccurred,andifithas,cold-resetflowshouldbeselected.
BIOSneedtoclearthisbitatMRCentry.
7:7RW_L0x0MRC_DONE(mrc_done):ThisbitindicatesthePCUthattheMRCisdone,IMCisinnormalmode,readytoserve.
MRCshouldsetthisbitwhenMRCisdone,butitdoesn'tneedtowaituntiltrainingresultsaresavedinBIOSflash.
5:5RW_L0x1DDRIOReset(reset_io):TrainingResetforDDRIO.
MakesurethisbitisclearedbeforeenablingDDRIO.
3:3RW_L0x0RefreshEnable(refresh_enable):Ifcoldreset,thisbitshouldbesetbyBIOSafter:1)Initializingtherefreshtimingparameters2)RunningDDRthroughresetadinitsequence.
IfwarmresetorS3exit,thisbitshouldbesetimmediatelyafterSRexit.
2:2RW_L0x0DCLKEnable(forallchannels)(dclk_enable):1:1RW_L0x1DDR_RESET(ddr_reset):DIMMreset.
Controlsallchannels.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0x8c0BitAttrDefaultDescription31:31RW_V0x0rcomp_in_progress:RCOMPinprogressstatusbit30:30RW0x0rcomp:RCOMPstartviamessagechannelcontrolforBIOS.
RCOMPstartonlytriggeredwhentheregisterbitoutputischangingfrom0->1.
iMCisnotberesponsibleforclearingthisbit.
WhenRcompisdoneviafirst_rcomp_donebitfield.
21:21RW0x0ignore_mdll_locked_bitIgnoreDDRIOMDLLlockstatusduringrcompwhenset.
20:20RW0x0no_mdll_fsm_override:DonotforceDDRIOMDLLonduringrcompwhenset.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily23Datasheet,VolumeTwo:RegistersApril20193.
1.
6mh_ext_statCaptureexternallyassertedMEM_HOT[1:0]#assertiondetection.
3.
1.
7smb_stat_[0:1]SMBusStatus.
ThisregisterprovidestheinterfacetotheSMBus/I2C*SCLandSDAsignalsthatisusedtoaccesstheSerialPresenceDetectEEPROM(SPD)orThermalSensoronDIMM(TSOD)thatdefinesthetechnology,configuration,andspeedoftheDIMMscontrolledbyiMC.
16:16RW_LV0x0FirstRCOMPhasbeendoneinDDRIO(first_rcomp_done):ThisisastatusbitthatindicatesthefirstRCOMPhasbeencompleted.
Itisclearedonreset,andsetbyIMCHWwhenthefirstRCOMPiscompleted.
BIOSshouldwaituntilthisbitissetbeforeexecutinganyDDRcommand.
15:0RW0xc00COUNT(count):DCLKcyclecountthatIMCneedstowaitfromthepointithastriggeredRCOMPevaluationuntilitcantriggertheloadtoregisters.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0x8c0BitAttrDefaultDescriptionType:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xe24BitAttrDefaultDescription1:1RW1C0x0MH_EXT_STAT_1(mh_ext_stat_1):MEM_HOT[1]#assertionstatusatthissenseperiod.
SetifMEM_HOT[1]#isassertedexternallyforthissenseperiod,thisrunningstatusbitwillautomaticallyupdatedwiththenextsensedvalueinthenextMEMHOTinputsensephase.
0:0RW1C0x0MH_EXT_STAT_0(mh_ext_stat_0):MEM_HOT[0]#assertionstatusatthissenseperiod.
SetifMEM_HOT[0]#isassertedexternallyforthissenseperiod,thisrunningstatusbitwillautomaticallyupdatedwiththenextsensedvalueinthenextMEMHOTinputsensephase.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xe80,0xe90BitAttrDefaultDescription31:31RO_V0x0SMB_RDO(smb_rdo):ReadDataValidThisbitissetbyiMCwhentheDatafieldofthisregisterreceivesreaddatafromtheSPD/TSODaftercompletionofanSMBusreadcommand.
ItisclearedbyiMCwhenasubsequentSMBusreadcommandisissued.
30:30RO_V0x0SMB_WOD(smb_wod):WriteOperationDoneThisbitissetbyiMCwhenaSMBusWritecommandhasbeencompletedontheSMBus.
ItisclearedbyiMCwhenasubsequentSMBusWritecommandisissued.
IntegratedMemoryController(iMC)ConfigurationRegisters24SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril201929:29RO_V0x0SMB_SBE(smb_sbe):SMBusErrorThisbitissetbyiMCifanSMBustransaction(includingtheTSODpollingormessagechannelinitiatedSMBusaccess)thatdoesnotcompletesuccessfully(non-AckhasbeenreceivedfromslaveatexpectedAckslotofthetransfer).
Ifaslavedeviceisassertingclockstretching,IMCdoesnothavelogictodetectthisconditiontosettheSBEbitdirectly;however,theSMBusmasterwilldetecttheerroratthecorrespondingtransaction'sexpectedACKslot.
OnceSMBUS_SBEbitisset,iMCstopsissuinghardwareinitiatedTSODpollingSMBUStransactionsuntiltheSMB_SBEiscleared.
iMCwillnotincrementtheSMB_STAT_x.
TSOD_SAuntiltheSMB_SBEiscleared.
ManualSMBuscommandinterfaceisnotaffected,thatis,newcommandissuewillcleartheSMB_SBElikeA0siliconbehavior.
28:28ROS_V0x0SMB_BUSY(smb_busy):SMBusBusystate.
ThisbitissetbyiMCwhileanSMBus/I2Ccommand(includingTSODcommandissuedfromIMChardware)isexecuting.
Anytransactionthatiscompletednormallyorgracefullywillclearthisbitautomatically.
BysettingtheSMB_SOFT_RSTwillalsoclearthisbit.
ThisregisterbitisstickyacrossresetsoanysurpriseresetduringpendingSMBusoperationwillsustainthebitassertionacrosssurprisedwarm-reset.
BIOSresethandlercanreadthisbitbeforeissuinganySMBustransactiontodeterminewhetheraslavedevicemayneedspecialcaretoforcetheslavetoidlestate(forexample,viaclockoverridetogglingSMB_CKOVRDand/orviainducedtime-outbyassertingSMB_CKOVRDfor25-35ms).
27:24RO_V0x7LastIssuedTSODSlaveAddress(tsod_sa):ThisfieldcapturesthelastissuedTSODslaveaddress.
HereistheslaveaddressandtheDDRCHNandDIMMslotmapping:SlaveAddress:0--Channel:EvenChn;Slot#:0SlaveAddress:1--Channel:EvenChn;Slot#:1SlaveAddress:2--Channel:EvenChn;Slot#:2SlaveAddress:3--Channel:EvenChn;Slot#:3(reserved)SlaveAddress:4--Channel:OddChn;Slot#:0SlaveAddress:5--Channel:OddChn;Slot#:1SlaveAddress:6--Channel:OddChn;Slot#:2SlaveAddress:7--Channel:OddChn;Slot#:3(reserved)SincethisfieldonlycapturestheTSODpollingslaveaddress.
DuringSMBerrorhandling,softwareshouldcheckthehungSMB_TSOD_POLL_ENstatebeforedisablingtheSMB_TSOD_POLL_ENinordertoqualifywhetherthisfieldisvalid.
15:0RO_V0x0SMB_RDATA(smb_rdata):ReadDataHoldsdatareadfromSMBusReadcommands.
SinceTSOD/EEPROMareI2C*devicesandthebyteorderisMSBytefirstinawordread,readingofI2CusingwordreadshouldreturnSMB_RDATA[15:8]=I2C_MSBandSMB_RDATA[7:0]=I2C_LSB.
IfreadingofI2Cusingbyteread,theSMB_RDATA[15:8]=dontcare;SMB_RDATA[7:0]=readbyte.
IfthereisaSMBslaveconnectedonthebus,readingoftheSMBusslaveusingwordreadreturnsSMB_RDATA[15:8]=SMB_LSBandSMB_RDATA[7:0]=SMB_MSB.
IfthesoftwareisnotsurewhetherthetargetisI2CorSMBusslave,pleaseusebyteaccess.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xe80,0xe90BitAttrDefaultDescriptionIntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily25Datasheet,VolumeTwo:RegistersApril20193.
1.
8smbcmd_[0:1]AwritetothisregisterinitiatesaDIMMEEPROMaccessthroughtheSMBus/I2C.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xe84,0xe94BitAttrDefaultDescription31:31RW_V0x0SMB_CMD_TRIGGER(smb_cmd_trigger):CMDtrigger:Aftersettingthisbitto1,theSMBusmasterwillissuetheSMBuscommandusingtheotherfieldswritteninSMBCMD_[0:1]andSMBCntl_[0:1].
Note:The'-V'intheattributeimpliesthehardwarewillresetthisbitwhentheSMBuscommandisbeingstarted.
30:30RWS0x0SMB_PNTR_SEL(smb_pntr_sel):PointerSelection:SMBus/I2Cpresentpointer-basedaccessenablewhenset;otherwise,userandomaccessprotocol.
HardwarebasedTSODpollingwillalsousethisbittoenablethepointerwordread.
ImportantNote:CPUhardware-basedTSODpollingcanbeconfiguredwithpointerbasedaccess.
IfsoftwaremanuallyissueSMBustransactiontootheraddress,i.
e.
changingthepointerintheslavedevice,itissoftware'sresponsibilitytorestorethepointerineachTSODbeforereturningtohardwarebasedTSODpollingwhilekeepingtheSMB_PNTR_SEL=1.
29:29RWS0x0SMB_WORD_ACCESS(smb_word_access):Wordaccess:SMBus/I2Cword2Baccesswhenset;otherwise,itisabyteaccess.
28:28RWS0x0SMB_WRT_PNTR(smb_wrt_pntr):Bit[28:27]=00:SMBusReadBit[28:27]=01:SMBusWriteBit[28:27]=10:illegalcombinationBit[28:27]=11:WritetopointerregisterSMBus/I2Cpointerupdate(byte).
bit30,and29areignored.
Note:SMBCntl_[0:1][26]willNOTdisableWrtPntrupdatecommand.
27:27RWS0x0SMB_WRT_CMD(smb_wrt_cmd):When'0',it'sareadcommandWhen'1',it'sawritecommand26:24RWS0x0SMB_SA(smb_sa):SlaveAddress:ThisfieldidentifiestheDIMMSPD/TSODtobeaccessed.
23:16RWS0x0SMB_BA(smb_ba):BusTxnAddress:Thisfieldidentifiesthebustransactionaddresstobeaccessed.
Note:InWORDaccess,23:16specifies2Baccessaddress.
InByteaccess,23:16specified1Baccessaddress.
15:0RWS0x0SMB_WDATA(smb_wdata):WriteData:HoldsdatatobewrittenbySPDWcommands.
SinceTSOD/EEPROMareI2CdevicesandthebyteorderisMSBytefirstinawordwrite,writingofI2CusingwordwriteshoulduseSMB_WDATA[15:8]=I2C_MSBandSMB_WDATA[7:0]=I2C_LSB.
IfwritingofI2Cusingbytewrite,theSMB_WDATA[15:8]=dontcare;SMB_WDATA[7:0]=writebyte.
IfwehaveaSMBslaveconnectedonthebus,writingoftheSMBusslaveusingwordwriteshoulduseSMB_WDATA[15:8]=SMB_LSBandSMB_WDATA[7:0]=SMB_MSB.
Itissoftwareresponsibilitytofigureoutthebyteorderoftheslaveaccess.
IntegratedMemoryController(iMC)ConfigurationRegisters26SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
1.
9smbcntl_[0:1]SMBusControl.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xe88,0xe98BitAttrDefaultDescription31:28RWS0xaSMB_DTI(smb_dti):DeviceTypeIdentifier:Thisfieldspecifiesthedevicetypeidentifier.
Onlydeviceswiththisdevice-typewillrespondtocommands.
'0011'specifiesTSOD.
'1010'specifiesEEPROM's.
'0110'specifiesawrite-protectoperationforanEEPROM.
Otheridentifierscanbespecifiedtotargetnon-EEPROMdevicesontheSMBus.
Note:IMCbasedhardwareTSODpollinguseshardcodedDTI.
ChangingthisfieldhasnoeffectonthehardwarebasedTSODpolling.
27:27RWS_V0x1SMB_CKOVRD(smb_ckovrd):ClockOverride'0'Clocksignalisdrivenlow,overridingwritinga'1'toCMD.
'1'Clocksignalisreleasedhigh,allowingnormaloperationofCMD.
Togglingthisbitcanbeusedto'budge'theportoutofa'stuck'state.
Softwarecanwritethisbitto0andtheSMB_SOFT_RSTto1toforcehungSMBuscontrollerandtheSMBslavestoidlestatewithoutusingpowergoodresetorwarmreset.
Note:SoftwareneedtosettheSMB_CKOVRDbackto1after35msinordertoforceslavedevicestotime-outincasethereisanypendingtransaction.
ThecorrespondingSMB_STAT_x.
SMB_SBEerrorstatusbitmaybesetiftherewassuchpendingtransactiontime-out(non-gracefultermination).
Ifthependingtransactionwasawriteoperation,theslavedevicecontentmaybecorruptedbythisclockoverrideoperation.
AsubsequentSMBcommandwillautomaticallyclearedtheSMB_SBE.
iMCaddedSMBustime-outcontroltimerinB0.
Whenthetime-outcontroltimerexpired,theSMBCKOVRD#will"de-assert",i.
e.
returnto1valueandcleartheSMBSBE0.
26:26RW_LB0x1SMB_DIS_WRT(smb_dis_wrt):DisableSMBusWriteWritinga'0'tothisbitenablesCMDtobesetto1;Writinga1toforceCMDbittobealways0,i.
e.
disablingSMBuswrite.
ThisbitcanonlybewritteninSMMode.
SMBusReadisnotaffected.
I2CWritePointerUpdateCommandisnotaffected.
ImportantNotetoBIOS:SinceBIOSisthesourcetoupdateSMBCNTL_xregisterinitiallyafterreset,itisimportanttodeterminewhethertheSMBuscanhavewritecapabilitybeforewritinganyupperbits(bit24-31)viabyte-enableconfigwrite(orwritinganybitwithinthisregistervia32bconfigwrite)withintheSMBCNTLregister.
10:10RW0x0SMB_SOFT_RST(smb_soft_rst):SMBussoftwareresetstrobetogracefulterminatependingtransactionafterACKandkeeptheSMBfromissuinganytransactionuntilthisbitiscleared.
Ifslavedeviceishung,softwarecanwritethisbitto1andtheSMB_CKOVRDto0(formorethan35ms)toforcehungtheSMBslavestotime-outandputitinidlestatewithoutusingpowergoodresetorwarmreset.
Note:SoftwareneedtosettheSMB_CKOVRDbackto1after35msinordertoforceslavedevicestotime-outincasethereisanypendingtransaction.
ThecorrespondingSMB_STAT_x.
SMB_SBEerrorstatusbitmaybesetiftherewassuchpendingtransactiontime-out(non-gracefultermination).
Ifthependingtransactionwasawriteoperation,theslavedevicecontentmaybecorruptedbythisclockoverrideoperation.
AsubsequentSMBcommandwillautomaticallyclearedtheSMB_SBE.
IftheIMCHWperformSMBtime-outwiththeSMB_SBE_EN=1.
SoftwareshouldsimplycleartheSMB_SBEandSMB_SOFT_RSTsequentiallyafterwritingtheSMB_CKOVRD=0andSMB_SOFT_RST=1assertingclockoverrideandperformgracefultxntermination.
Hardwarewillautomaticallyde-asserttheSMB_CKOVRDupdateto1afterthepre-configured35ms/65mstime-out.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily27Datasheet,VolumeTwo:RegistersApril20193.
1.
10smb_tsod_poll_rate_cntr_[0:1]3.
1.
11smb_period_cfgSMBusClockPeriodConfig.
9:9RW_LB0x0start_tsod_poll:Thisbitstartsthereadingofallenableddevices.
NotethatthehardwarewillresetthisbitwhentheSMBuspollinghasstarted.
8:8RW_LB0x0SMB_TSOD_POLL_EN(smb_tsod_poll_en):TSODpollingenable'0':disableTSODpollingandenableSPDCMDaccesses.
'1':disableSPDCMDaccessandenableTSODpolling.
ItisimportanttomakesurenopendingSMBustransactionandtheTSODpollingmustbedisabled(andpendingTSODpollingmustbedrained)beforechangingtheTSOD_POLL_EN.
7:0RW_LB0x0TSOD_PRESENTforthelowerandupperchannels(tsod_present):DIMMslotmasktoindicatewhethertheDIMMisequippedwithTSODsensor.
Bit7:mustbeprogrammedtozero.
Upperchannelslot#3isnotsupportedBit6:TSODPRESENTatupperchannel(ch1orch3)slot#2Bit5:TSODPRESENTatupperchannel(ch1orch3)slot#1Bit4:TSODPRESENTatupperchannel(ch1orch3)slot#0Bit3:mustbeprogrammedtozero.
Lowerchannelslot#3isnotsupportedBit2:TSODPRESENTatlowerchannel(ch0orch2)slot#2Bit1:TSODPRESENTatlowerchannel(ch0orch2)slot#1Bit0:TSODPRESENTatlowerchannel(ch0orch2)slot#0Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xe8c,0xe9cBitAttrDefaultDescription17:0RW_LV0x0SMB_TSOD_POLL_RATE_CNTR(smb_tsod_poll_rate_cntr):TSODpollratecounter.
Whenitisdecrementedtozero,resettozeroorwrittentozero,SMB_TSOD_POLL_RATEvalueisloadedintothiscounterandappeartheupdatedvalueinthenextDCLK.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xe88,0xe98BitAttrDefaultDescriptionType:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xea0BitAttrDefaultDescription31:16RWS0x445cReserved15:0RWS0xfa0SMB_CLK_PRD(smb_clk_prd):ThisfieldspecifiesbothSMBusClockinnumberofDCLK.
Note:Inordertogeneratea50%dutycycleSCL,halfoftheSMB_CLK_PRDisusedtogenerateSCLhigh.
SCLmuststaylowforatleastanotherhalfoftheSMB_CLK_PRDbeforepullinghigh.
Itisrecommendtoprogramanevenvalueinthisfieldsincethehardwareissimplydoingarightshiftforthedividedby2operation.
Notethe100KHzSMB_CLK_PRDdefaultvalueiscalculatedbasedon800MTs(400MHz)DCLK.
IntegratedMemoryController(iMC)ConfigurationRegisters28SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
1.
12smb_period_cntrSMBusClockPeriodCounter.
3.
1.
13smb_tsod_poll_rate3.
1.
14pxpcapType:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0xea4BitAttrDefaultDescription31:16RO_V0x0SMB1_CLK_PRD_CNTR(smb1_clk_prd_cntr):SMBus#1ClockPeriodCounterforCh23.
ThisfieldisthecurrentSMBusClockPeriodCounterValue.
15:0RO_V0x0SMB0_CLK_PRD_CNTR(smb0_clk_prd_cntr):SMBus#0ClockPeriodCounterforCh01.
ThisfieldisthecurrentSMBusClockPeriodCounterValue.
Type:CFGPortID:N/ABus:2Device:10,12Function:0Offset:0x1a8BitAttrDefaultDescription17:0RWS0x3e800SMB_TSOD_POLL_RATE(smb_tsod_poll_rate):TSODpollrateconfigurationbetweenconsecutiveTSODaccessestotheTSODdevicesonthesameSMBussegment.
ThisfieldspecifiestheTSODpollrateinnumberof500nsperCNFG_500_NANOSECregisterfielddefinition.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x40BitAttrDefaultDescription29:25RO0x0InterruptMessageNumber(interrupt_message_number):NAforthisdevice24:24RO0x0SlotImplemented(slot_implemented):NAforintegratedendpoints23:20RO0x9Device/PortType(device_port_type):DevicetypeisRootComplexIntegratedEndpoint19:16RO0x1CapabilityVersion(capability_version):PCIExpressCapabilityisCompliantwithVersion1.
0ofthePCIExpressSpec.
Note:ThiscapabilitystructureisnotcompliantwithVersionsbeyond1.
0,sincetheyrequireadditionalcapabilityregisterstobereserved.
Theonlypurposeforthiscapabilitystructureistomakeenhancedconfigurationspaceavailable.
Minimizingthesizeofthisstructureisaccomplishedbyreportingversion1.
0complianceandreportingthatthisisanintegratedrootportdevice.
Assuch,onlythreeDwordsofconfigurationspacearerequiredforthisstructure.
15:8RO0x0NextCapabilityPointer(next_ptr):Pointertothenextcapability.
Setto0toindicatetherearenomorecapabilitystructures.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily29Datasheet,VolumeTwo:RegistersApril20193.
1.
15spareaddressloSpareAddressLowAlwayspointstotheloweraddressforthenextsparingoperation.
ThisregisterisnotaffectedbytheHAaccesstothesparesourcerankduringtheHAwindow.
3.
1.
16sparectl7:0RO0x10CapabilityID(capability_id):ProvidesthePCIExpresscapabilityIDassignedbyPCI-SIG.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x40BitAttrDefaultDescriptionType:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x900BitAttrDefaultDescription31:0RW_LV0x0RANKADD(rankadd):Alwayspointstotheloweraddressforthenextsparingoperation.
ThisregisterwillnotbeaffectedbytheHAaccesstothesparesourcerankduringtheHAwindow.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x904BitAttrDefaultDescription29:29RW_LB0x0DisWPQWM(diswpqwm):DisableWPQlevelbasedwatermark,sothatsparingwmisonlybasedonHaFifoWM.
IfDisWPQWMisclear,thesparewindowisstartedwhenthenumberofhitstothefailedDIMMexceedmax(#ofcreditsinWPQnotyetreturnedtotheHA,HaFifoWM).
IfDisWPQWMisset,thesparewindowstartswhenthenumberofhitstothefailedDIMMexceedHaFifoWM.
Ineithercase,ifthenumberofhitstothefailedDIMMdonothittheWM,thesparewindowwillstillstartafterSPAREINTERVAL.
NORMOPDURtimerexpiration.
28:24RW_LB0x0HaFifoWM(hafifowm):minimumwatermarkforHAwritestofailedrank.
ActualwmismaxofWPQcreditlevelandHaFifoWM.
WhenwmishittheHAisbackpressuredandasparingwindowisstarted.
IfDisWPQWMisclear,thesparewindowisstartedwhenthenumberofhitstothefailedDIMMexceedmax(#ofcreditsinWPQnotyetreturnedtotheHA,HaFifoWM).
IfDisWPQWMisset,thesparewindowstartswhenthenumberofhitstothefailedDIMMexceedHaFifoWM.
23:16RW0x0SCRATCH_PAD(scratch_pad):Thisfieldisavailableasascratchpad.
10:8RW_LB0x0DST_RANK(dst_rank):Destinationlogicalrankusedforthememorycopy.
6:4RW_LB0x0SRC_RANK(src_rank):Sourcelogicalrankthatprovidesthedatatobecopied.
IntegratedMemoryController(iMC)ConfigurationRegisters30SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
1.
17ssrstatusProvidesthestatusofaspare-copymemoryInitoperation.
3.
1.
18scrubaddressloScrubAddressLow.
Thisregistercontainspartoftheaddressofthelastpatrolscrubrequestissued.
Whenrunningmemtest,thefailingaddressisloggedinthisregisteronmemtesterrors.
Softwarecanwritethenextaddresstobescrubbedintothisregister.
TheSTARTSCRUBbitwillthentriggerthespecifiedaddresstobescrubbed.
Patrolscrubsmustbedisabledtoreliablywritethisregister.
3:2RW_LB0x0CHANNELSELECTFORTHESPARECOPY(chn_sel):Sincethereisonlyonespare-copylogicforallchannels,thisfieldselectsthechannelorchannel-pairforthespare-copyoperation.
Forindependentchanneloperation:00=channel0isselectedforthespare-copyoperation01=channel1isselectedforthespare-copyoperation10=channel2isselectedforthespare-copyoperation11=channel3isselectedforthespare-copyoperationForlock-stepchanneloperation:0x=channel0andchannel1areselectedforthespare-copyoperation1x=channel2andchannel3areselectedforthespare-copyoperation0:0RW_LBV0x0SPARE_ENABLE(spare_enable):Spareenablewhensetto1.
Hardwareclearafterthesparingcompletion.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x904BitAttrDefaultDescriptionType:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x94BitAttrDefaultDescription2:2RW1C0x0PATCMPLT(patcmplt):Allmemoryhasbeenscrubbed.
Hardwaresetsthisbiteachtimethepatrolenginestepsthroughallmemorylocations.
Ifsoftwarewantstomonitor0--->1transitionafterthebithasbeenset,thesoftwarewillneedtoclearthebitbywritingaonetoclearthisbitinordertodistinguishthenextpatrolscrubcompletion.
Clearingthebitwillnotaffectthepatrolscruboperation.
1:1RO_V0x0SPRCMPLT(sprcmplt):SpareOperationComplete.
Setbyhardwareonceoperationiscomplete.
Bitisclearedbyhardwarewhenanewoperationisenabled.
Note:justbeforeMCreleasetheHAblockpriortothecompletionofthesparingoperation,iMClogicwillautomaticallyupdatethecorrespondingRIR_RNK_TGTtargettoreflectnewDST_RANK.
0:0RO_V0x0SPRINPROGRESS(sprinprogress):SpareOperationinprogress.
Thisbitissetbyhardwareonceoperationhasstarted.
Itisclearedonceoperationiscompleteorfails.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily31Datasheet,VolumeTwo:RegistersApril20193.
1.
19scrubaddresshiScrubAddressHigh.
Thisregisterpaircontainspartoftheaddressofthelastpatrolscrubrequestissued.
Softwarecanwritethenextaddressintothisregister.
Scrubbingmustbedisabledtoreliablyreadandwritethisregister.
TheSTARTSCRUBbitwillthentriggerthespecifiedaddresstobescrubbed.
3.
1.
20scrubctlThisregistercontainstheScrubcontrolparametersandstatus.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x90CBitAttrDefaultDescription31:0RW_LBV0x0RANKADD(rankadd):Containstherankaddressofthelastscrubissued.
CanbewrittentospecifythenextscrubaddresswithSTARTSCRUB.
PatrolScrubsmustbedisabledwhenwritingtothisfield.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x910BitAttrDefaultDescription17:16RW_LBV0x0CHNL(chnl):CanbewrittentospecifythenextscrubaddresswithSTARTSCRUB.
Thisregisterisupdatedwithchanneladdressofthelastscrubaddressissued.
PatrolScrubsmustbedisabledwhenwritingtothisfield.
Onlyusedforlegacy(nonsystemaddress)patrolmode.
15:12RW_LBV0x0RANK(rank):ContainsthephysicalrankIDofthelastscrubissued.
CanbewrittentospecifythenextscrubaddresswithSTARTSCRUB.
RESTRICTION:PatrolScrubsmustbedisabledwhenwritingtothisfield.
Onlyusedforlegacy(nonsystemaddress)patrolmode.
11RW_LBV0x1PIMARYINDICATOR(mirr_pri)Containstheprimaryindicationwhenmirroringisenabled.
Canbewrittentospecifythenextscrubaddress.
RESTRICTION:PatrolScrubsmustbedisabledwhenwritingtothisfield.
Onlyusedforsystemaddresspatrolmode.
8:0RW_LBV0x0RANKADDHI(rankaddhi):ContainsthephysicalrankIDofthelastscrubissued.
CanbewrittentospecifythenextscrubaddresswithSTARTSCRUB.
PatrolScrubsmustbedisabledwhenwritingtothisfield.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x914BitAttrDefaultDescription31:31RW_L0x0ScrubEnable(scrub_en):ScrubEnablewhenset.
IntegratedMemoryController(iMC)ConfigurationRegisters32SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
1.
21spareintervalDefinestheintervalbetweennormalandsparingoperations.
Intervalisdefinedindclk.
3.
1.
22rasenablesRASEnablesRegister30:30RW_LB0x0Stoponcomplete(stop_on_cmpl):Stoppatrolscrubatendofmemoryrange.
Thismodeismeanttobeusedaspartofmemorymigrationflow.
IntelScalableMemoryInterconnect(IntelSMI)issignaledbydefault.
29:29RW_LBV0x0patrolrangecomplete(ptl_cmpl):Whenstop_on_cmplisenabled,patrolwillstopattheendoftheaddressrangeandsetthisbit.
Patrolwillresumefrombeginningofaddressrangewhenthisbitorstop_on_cmplisclearedbyBIOSandpatrolscrubisstillenabledbyscrub_en.
28:28RW_LB0x0Stoponerror(stop_on_err):Stoppatrolscrubonpoisonoruncorrectable.
Onpoison,patrolwilllogerrorthenstop.
Onuncorr,patrolwillconverttopoisonifenabledthenstop.
Thismodeismeanttobeusedaspartofmemorymigrationflow.
IntelSMIissignaledbydefault.
27:27RW_LBV0x0patrolstopped(ptl_stopped):Whenstop_on_errisset,patrolwillstoponerrorandsetthisbit.
Patrolwillresumeatthenextaddresswhenthisbitorstop_on_errisclearedbyBIOSandpatrolscrubisstillenabledbyscrub_en.
26:26RW_LBV0x0SCRUBISSUED(scrubissued):WhenSet,thescrubaddressregisterscontainthelastscrubaddressissued.
25:25RW_LB0x0ISSUEONCE(issueonce):WhenSet,thepatrolscrubenginewillissuetheaddressinthescrubaddressregistersonlyonceandstop.
24:24RW_LBV0x0STARTSCRUB(startscrub):WhenSet,thePatrolscrubenginewillstartfromtheaddressinthescrubaddressregisters.
Oncethescrubisissuedthisbitisreset.
23:0RW_LB0x0SCRUBINTERVAL(scrubinterval):DefinestheintervalinDCLKSbetweenpatrolscrubrequests.
Thecalculationforthisregistertogetascrubtoeverylinein24hoursis:((86400)/(memorycapacity/64))/cycletimeofDCLK.
RESTRICTIONS:Canonlybechangedwhenpatrolscrubsaredisabled.
Settoaminimumvalueof1500.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x914BitAttrDefaultDescriptionType:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x91cBitAttrDefaultDescription28:16RW-LB0x320NUMSPARE(numspare):Sparingoperationduration.
Systemrequestswillbeblockedduringthisintervalandonlysparingcopyoperationswillbeserviced.
15:0RW-LB0xc80NORMALOPERATIONDURATION(normopdur):Normaloperationduration.
Systemrequestswillbeservicedduringthisinterval.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily33Datasheet,VolumeTwo:RegistersApril20193.
1.
23smisparectlSystemManagementInterruptandSparecontrolregister.
3.
1.
24leaky_bucket_cfgTheleakybucketisimplementedasa53-bitDCLKcounter.
Theupper42-bitofthe53-bitcounteriscapturedinLEAKY_BUCKET_CNTR_LOandLEAKY_BUCKET_CNTR_HIregisters.
Thecarry"strobe"fromthenot-shownleastsignificant11-bitcounterwilltriggerthis42-bitcounter-pairtocount.
LEAKY_BUCKET_CFGcontainstwohotencodingthresholdsLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO.
The42-bitcounter-pairiscomparedwiththetwothresholdspairspecifiedbyLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x920BitAttrDefaultDescription0:0RW_LB0x0MIRROREN(mirroren):Mirrormodeenable.
ThechannelmappingmustbesetupbeforethisbitwillhaveaneffectoniMCoperation.
Thischangestheerrorpolicy.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0xb4BitAttrDefaultDescription17:17RW-LB0x0INTRPT_SEL_PIN(intrpt_sel_pin):Enablepinsignaling.
WhensettheinterruptissignaledviatheERROR_N[0]pintogettheattentionofaBMC.
16:16RW-LB0x0INTRPT_SEL_CMCI(intrpt_sel_cmci):(CMCIusedasaproxyforNMIsignaling).
SettoenableNMIsignaling.
CleartodisableNMIsignaling.
IfbothNMIandIntelSMIenablebitsaresetthenonlyIntelSMIissent.
15:15RW-LB0x0INTRPT_SEL_SMI(intrpt_sel_smi):IntelSMIenable.
SettoenableIntelSMIsignaling.
CleartodisableIntelSMIsignaling.
IntegratedMemoryController(iMC)ConfigurationRegisters34SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril2019Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x928BitAttrDefaultDescription11:6RW0x0LEAKY_BKT_CFG_HI(leaky_bkt_cfg_hi):Thisisthehigherorderbitselectmaskofthetwohotencodingthreshold.
Thevalueofthisfieldspecifythebitpositionofthemask:00h:reserved01h:LEAKY_BUCKET_CNTR_LObit1,i.
e.
bit12ofthefull53bcounter.
.
.
1Fh:LEAKY_BUCKET_CNTR_LObit31,i.
e.
bit42ofthefull53bcounter20h:LEAKY_BUCKET_CNTR_HIbit0,i.
e.
bit43ofthefull53bcounter.
.
.
29h:LEAKY_BUCKET_CNTR_HIbit9,i.
e.
bit52ofthefull53bcounter2Ah-3F:reservedWhenbothcounterbitsselectedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LOareset,the53bleakybucketcounterwillberesetandthelogicwillgenerateaprimaryleakStrobewhichisusedbya2-bitLEAKY_BKT_2ND_CNTR.
LEAKY_BKT_2ND_CNTR_LIMITspecifiesthevaluetogenerateLEAKpulsewhichisusedtodecrementthecorrectableerrorcounterby1asshownbelow:LEAKY_BKT_2ND_CNTR_LIMITLEAKpulsetodecrementCEcounterby100b(default):4xPrimaryleakstrobe(fourtimesthevalueprogrammedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO)01b:1xPrimaryleakstrobe(sameasthevalueprogrammedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO)10b:2xPrimaryleakstrobe(twotimesthevalueprogrammedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO)11b:3xPrimaryleakstrobe(twotimesthevalueprogrammedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO)Note:AvalueofallzerosinLEAKY_BUCKET_CFGregisterisequivalenttonoleakybucketing.
BIOSmustprogramthisregistertoanynon-zerovaluebeforeswitchingtoNORMALmode.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily35Datasheet,VolumeTwo:RegistersApril20193.
1.
25leaky_bucket_cntr_lo5:0RW0x0LEAKY_BKT_CFG_LO(leaky_bkt_cfg_lo):Thisisthelowerorderbitselectmaskofthetwohotencodingthreshold.
Thevalueofthisfieldspecifythebitpositionofthemask:00h:reserved01h:LEAKY_BUCKET_CNTR_LObit1,i.
e.
bit12ofthefull53bcounter.
.
.
1Fh:LEAKY_BUCKET_CNTR_LObit31,i.
e.
bit42ofthefull53bcounter20h:LEAKY_BUCKET_CNTR_HIbit0,i.
e.
bit43ofthefull53bcounter.
.
.
29h:LEAKY_BUCKET_CNTR_HIbit9,i.
e.
bit52ofthefull53bcounter2Ah-3F:reservedWhenbothcounterbitsselectedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LOareset,the53bleakybucketcounterwillberesetandthelogicwillgenerateaprimaryleakStrobewhichisusedbya2-bitLEAKY_BKT_2ND_CNTR.
LEAKY_BKT_2ND_CNTR_LIMITspecifiesthevaluetogenerateLEAKpulsewhichisusedtodecrementthecorrectableerrorcounterby1asshownbelow:LEAKY_BKT_2ND_CNTR_LIMITLEAKpulsetodecrementCEcounterby100b(default):4xPrimaryleakstrobe(fourtimesthevalueprogrammedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO)01b:1xPrimaryleakstrobe(sameasthevalueprogrammedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO)10b:2xPrimaryleakstrobe(twotimesthevalueprogrammedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO)11b:3xPrimaryleakstrobe(twotimesthevalueprogrammedbytheLEAKY_BKT_CFG_HIandLEAKY_BKT_CFG_LO)Note:AvalueofallzerosinLEAKY_BUCKET_CFGregisterisequivalenttonoleakybucketing.
MRCBIOSmustprogramthisregistertoanynon-zerovaluebeforeswitchingtoNORMALmode.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x930BitAttrDefaultDescription31:0RW_V0x0LeakyBucketCounterLow(leaky_bkt_cntr_lo):Thisisthelowerhalfoftheleakybucketcounter.
Thefullcounterisactuallya53b"DCLK"counter.
Thereisaleastsignificant11bofthe53bcounterisnotcapturedinCSR.
Thecarry"strobe"fromthenot-shownleastsignificant11bcounterwilltriggerthis42bcounterpairtocount.
The42bcounter-pairiscomparedwiththetwo-hotencodingthresholdspecifiedbytheLEAKY_BUCKET_CFG_HIandLEAKY_BUCKET_CFG_LOpair.
WhenthecounterbitsspecifiedbytheLEAKY_BUCKET_CFG_HIandLEAKY_BUCKET_CFG_LOarebothset,the53bcounterisresetandtheleakybucketlogicwillgenerateaLEAKstrobelastfor1DCLK.
Type:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x928BitAttrDefaultDescriptionIntegratedMemoryController(iMC)ConfigurationRegisters36SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
1.
26leaky_bucket_cntr_hi3.
2Device10,12Functions2,3,4,53.
2.
1pxpcapType:CFGPortID:N/ABus:2Device:10,12Function:1Offset:0x934BitAttrDefaultDescription9:0RW_V0x0LeakyBucketCounterHighLimit(leaky_bkt_cntr_hi):Thisistheupperhalfoftheleakybucketcounter.
Thefullcounterisactuallya53b"DCLK"counter.
Thereisaleastsignificant11bofthe53bcounterisnotcapturedinCSR.
Thecarry"strobe"fromthenot-shownleastsignificant11bcounterwilltriggerthis42bcounterpairtocount.
The42bcounter-pairiscomparedwiththetwo-hotencodingthresholdspecifiedbytheLEAKY_BUCKET_CFG_HIandLEAKY_BUCKET_CFG_LOpair.
WhenthecounterbitsspecifiedbytheLEAKY_BUCKET_CFG_HIandLEAKY_BUCKET_CFG_LOarebothset,the53bcounterisresetandtheleakybucketlogicwillgenerateaLEAKstrobelastfor1DCLK.
Type:CFGPortID:N/ABus:2Device:10,12Function:2,3,4,5Offset:0x40BitAttrDefaultDescription29:25RO0x0InterruptMessageNumber(interrupt_message_number):NAforthisdevice24:24RO0x0SlotImplemented(slot_implemented):NAforintegratedendpoints23:20RO0x9Device/PortType(device_port_type):DevicetypeisRootComplexIntegratedEndpoint19:16RO0x1CapabilityVersion(capability_version):PCIExpressCapabilityisCompliantwithVersion1.
0ofthePCIExpressSpec.
Note:ThiscapabilitystructureisnotcompliantwithVersionsbeyond1.
0,sincetheyrequireadditionalcapabilityregisterstobereserved.
Theonlypurposeforthiscapabilitystructureistomakeenhancedconfigurationspaceavailable.
Minimizingthesizeofthisstructureisaccomplishedbyreportingversion1.
0complianceandreportingthatthisisanintegratedrootportdevice.
Assuch,onlythreeDwordsofconfigurationspacearerequiredforthisstructure.
15:8RO0x0NextCapabilityPointer(next_ptr):Pointertothenextcapability.
Setto0toindicatetherearenomorecapabilitystructures.
7:0RO0x10CapabilityID(capability_id):ProvidesthePCIExpresscapabilityIDassignedbyPCI-SIG.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily37Datasheet,VolumeTwo:RegistersApril20193.
2.
2pxpenhcapThisfieldpointstothenextCapabilityinextendedconfigurationspace.
3.
3Device10,11,12Functions2,63.
3.
1pxpcap3.
3.
2chn_temp_cfgType:CFGPortID:N/ABus:2Device:10,12Function:2,3,4,5Offset:0x100BitAttrDefaultDescription31:20RO0x0NextCapabilityOffset(next_capability_offset):19:16RO0x0CapabilityVersion(capability_version):Indicatestherearenocapabilitystructuresintheenhancedconfigurationspace.
15:0RO0x0CapabilityID(capability_id):Indicatestherearenocapabilitystructuresintheenhancedconfigurationspace.
Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x40BitAttrDefaultDescription7:0RO0x10CapabilityID(capability_id):ProvidesthePCIExpresscapabilityIDassignedbyPCI-SIG.
Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x108BitAttrDefaultDescription31:31RW0x1OLTT_EN(oltt_en):EnableOLTTtemperaturetracking.
29:29RW0x0CLTT_OR_PCODE_TEMP_MUX_SEL(cltt_or_pcode_temp_mux_sel):TheTEMP_STATbyteupdatemuxselectcontroltodirectthesourcetoupdateDIMMTEMPSTAT_[0:3][7:0]:0:CorrespondingtotheDIMMTEMP_STATbytefromPCODE_TEMP_OUTPUT.
1:TSODtemperaturereadingfromCLTTlogic.
28:28RW_O0x1CLTT_DEBUG_DISABLE_LOCK(cltt_debug_disable_lock):LockbitofDIMMTEMPSTAT_[0:3][7:0]:SetthislockbittodisableconfigurationwritetoDIMMTEMPSTAT_[0:3][7:0].
27:27RW0x1Enablesthermalbandwidththrottlinglimit(bw_limit_thrt_en):23:16RW0x0THRT_EXT(thrt_ext):MaxnumberofthrottledtransactionstobeissuedduringBWLIMITTFduetoexternallyassertedMEMHOT#.
IntegratedMemoryController(iMC)ConfigurationRegisters38SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
3.
3chn_temp_stat3.
3.
4dimm_temp_oem_[0:1]15:15RW0x0THRT_ALLOW_ISOCH(thrt_allow_isoch):Whenthisbitiszero,MCwilllowerCKEduringThermalThrottling,andISOCHisblocked.
Whenthisbitisone,MCwillNOTlowerCKEduringThermalThrottling,andISOCHwillbeallowedbaseonbandwidththrottlingsetting.
However,settingthisbitwouldmeanmorepowerconsumptionduetoCKEisassertedduringthermalorpowerthrottling.
10:0RW0x3ffBW_LIMIT_TF(bw_limit_tf):BWThrottleWindowSizeinDCLK.
Note:Thisvalueisleftshifted3bitsbeforebeingused.
Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x10cBitAttrDefaultDescription1:1RW1C0x0EventAssertedonDIMMID1(ev_asrt_dimm1):EventAssertedonDIMMID10:0RW1C0x0EventAssertedonDIMMID0(ev_asrt_dimm0):EventAssertedonDIMMID0Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x110,0x114BitAttrDefaultDescription26:24RW0x0TEMP_OEM_HI_HYST(temp_oem_hi_hyst):PositivegoingThresholdHysteresisValue.
ThisvalueissubtractedfromTEMPOEMHItodeterminethepointwheretheassertedstatusforthatthresholdwillclear.
Setto00hifsensordoesnotsupportpositive-goingthresholdhysteresis18:16RW0x0TEMP_OEM_LO_HYST(temp_oem_lo_hyst):NegativegoingThresholdHysteresisValue.
ThisvalueisaddedtoTEMPOEMLOtodeterminethepointwheretheassertedstatusforthatthresholdwillclear.
Setto00hifsensordoesnotsupportnegative-goingthresholdhysteresis.
15:8RW0x50TEMP_OEM_HI(temp_oem_hi):UpperThresholdvalue-TCasethresholdatwhichtoInitiateSystemInterrupt(IntelSMIorMEMHOT#)ata+goingrate.
Note:Thedefaultvalueislistedindecimal.
Validrange:32-127indegree(C).
Others:reserved.
7:0RW0x4bTEMP_OEM_LO(temp_oem_lo):LowerThresholdValue-TCasethresholdatwhichtoInitiateSystemInterrupt(IntelSMIorMEMHOT#)ata-goingrate.
Note:thedefaultvalueislistedindecimal.
Validrange:32-127indegree(C).
Others:reserved.
Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x108BitAttrDefaultDescriptionIntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily39Datasheet,VolumeTwo:RegistersApril20193.
3.
5dimm_temp_th_[0:2]3.
3.
6dimm_temp_thrt_lmt_[0:1]AllthreeTHRT_CRIT,THRT_HIandTHRT_MIDareperDIMMBWlimit,i.
e.
allactivities(ACT,READ,WRITE)fromallrankswithinaDIMMaretrackedtogetherinoneDIMMactivitycounter.
Thesethrottlelimitsforhiandcritarealsousedduringscalablememorybufferthermalthrottling.
Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x120,0x124BitAttrDefaultDescription26:24RW-LB0x0TEMP_THRT_HYST(temp_thrt_hyst):PositivegoingThresholdHysteresisValue.
Setto00hifsensordoesnotsupportpositive-goingthresholdhysteresis.
ThisvalueissubtractedfromTEMP_THRT_XXtodeterminethepointwheretheassertedstatusforthatthresholdwillclear.
23:16RW-LB0x5fTEMP_HI(temp_hi):TCasethresholdatwhichtoInitiateTHRTCRITandassertTHERMTRIP#validrange:32-127indegree(C).
Note:thedefaultvalueislistedindecimal.
FF:DisabledOthers:reserved.
TEMP_HIshouldbeprogrammedsoitisgreaterthanTEMP_MID.
15:8RW0x5aTEMP_MID(temp_mid):TCasethresholdatwhichtoInitiateTHRTHIandassertvalidrange:32-127indegree(C).
Note:Thedefaultvalueislistedindecimal.
FF:DisabledOthers:reserved.
TEMP_MIDshouldbeprogrammedsoitislessthanTEMP_HI.
7:0RW0x55TEMP_LO(temp_lo):TCasethresholdatwhichtoInitiate2xrefreshandorTHRTMIDandinitiateInterrupt(MEMHOT#).
Note:Thedefaultvalueislistedindecimal.
validrange:32-127indegree(C).
FF:DisabledOthers:reserved.
TEMP_LOshouldbeprogrammedsoitislessthanTEMP_MIDType:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x130,0x134BitAttrDefaultDescription23:16RW-LB0x0THRT_CRIT(thrt_crit):Maxnumberofthrottledtransactions(ACT,READ,WRITE)tobeissuedduringBWLIMITTF.
15:8RW-LB0xfTHRT_HI(thrt_hi):Maxnumberofthrottledtransactions(ACT,READ,WRITE)tobeissuedduringBWLIMITTF.
7:0RW0xffTHRT_MID(thrt_mid):Maxnumberofthrottledtransactions(ACT,READ,WRITE)tobeissuedduringBWLIMITTF.
IntegratedMemoryController(iMC)ConfigurationRegisters40SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
3.
7dimm_temp_ev_ofst_[0:1]3.
3.
8dimmtempstat_[0:1]Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x140,0x144BitAttrDefaultDescription31:24RO0x0TEMP_AVG_INTRVL(temp_avg_intrvl):Temperaturedataisaveragedoverthisperiod.
Attheendofaveragingperiod(ms),averagingprocessstartsagain.
0x1-0xFFAveragingdataisreadviaTEMPDIMMSTATUSREGISTER(Byte1/2)aswellasusedforgeneratinghysteresisbasedinterrupts.
00InstantaneousData(non-averaged)isreadviaTEMPDIMMSTATUSREGISTER(Byte1/2)aswellasusedforgeneratinghysteresisbasedinterrupts.
Note:CPUdoesnotsupporttempaveraging.
14:14RW0x0InitiateTHRTMIDonTEMPLO(ev_thrtmid_templo):InitiateTHRTMIDonTEMPLO13:13RW0x1Initiate2XrefreshonTEMPLO(ev_2x_ref_templo_en):Initiate2XrefreshonTEMPLODIMMwithextendedtemperaturerangecapabilitywillneeddoublerefreshrateinordertoavoiddatalostwhenDIMMtemperatureisabove85Cbutbelow95C.
Warning:Ifthe2xrefreshisdisablewithextendedtemperaturerangeDIMMconfiguration,systemcoolingandpowerthermalthrottlingschememustguaranteetheDIMMtemperaturewillnotexceed85C.
12:12RW0x0AssertMEMHOTEventonTEMPHI(ev_mh_temphi_en):AssertMEMHOT#EventonTEMPHI11:11RW0x0AssertMEMHOTEventonTEMPMID(ev_mh_tempmid_en):AssertMEMHOT#EventonTEMPMID10:10RW0x0AssertMEMHOTEventonTEMPLO(ev_mh_templo_en):AssertMEMHOT#EventonTEMPLO9:9RW0x0AssertMEMHOTEventonTEMPOEMHI(ev_mh_tempoemhi_en):AssertMEMHOT#EventonTEMPOEMHI8:8RW0x0AssertMEMHOTEventonTEMPOEMLO(ev_mh_tempoemlo_en):AssertMEMHOT#EventonTEMPOEMLO3:0RW0x0DIMM_TEMP_OFFSET(dimm_temp_offset):TemperatureOffsetRegister.
Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x150,0x154BitAttrDefaultDescription28:28RW1C0x0EventAssertedonTEMPHIgoingHIGH(ev_asrt_temphi):EventAssertedonTEMPHIgoingHIGHItisassumedthateachoftheeventassertionisgoingtotriggerConfigurableinterrupt(EitherMEMHOT#onlyorbothIntelSMIandMEMHOT#)definedinbit30ofCHN_TEMP_CFG.
27:27RW1C0x0EventAssertedonTEMPMIDgoingHigh(ev_asrt_tempmid):EventAssertedonTEMPMIDgoingHighItisassumedthateachoftheeventassertionisgoingtotriggerconfigurableinterrupt(EitherMEMHOT#onlyorbothIntelSMIandMEMHOT#)definedinbit30ofCHN_TEMP_CFG.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily41Datasheet,VolumeTwo:RegistersApril20193.
3.
9thrt_pwr_dimm_[0:1]bit[10:0]:Maxnumberoftransactions(ACT,READ,WRITE)tobeallowedduringthe1usecthrottlingtimeframeperpowerthrottling.
3.
4Device10,12Functions3,73.
4.
1correrrcnt_0PerRankcorrectederrorcounters.
26:26RW1C0x0EventAssertedonTEMPLOGoingHigh(ev_asrt_templo):EventAssertedonTEMPLOGoingHighItisassumedthateachoftheeventassertionisgoingtotriggerConfigurableinterrupt(EitherMEMHOT#onlyorbothIntelSMIandMEMHOT#)definedinbit30ofCHN_TEMP_CFG.
25:25RW1C0x0EventAssertedonTEMPOEMLOGoingLow(ev_asrt_tempoemlo):EventAssertedonTEMPOEMLOGoingLowItisassumedthateachoftheeventassertionisgoingtotriggerConfigurableinterrupt(EitherMEMHOT#onlyorbothIntelSMIandMEMHOT#)definedinbit30ofCHN_TEMP_CFG.
24:24RW1C0x0EventAssertedonTEMPOEMHIGoingHigh(ev_asrt_tempoemhi):EventAssertedonTEMPOEMHIGoingHighItisassumedthateachoftheeventassertionisgoingtotriggerConfigurableinterrupt(EitherMEMHOT#onlyorbothIntelSMIandMEMHOT#)definedinbit30ofCHN_TEMP_CFG.
7:0RW_LV0x55DIMM_TEMP(dimm_temp):CurrentDIMMTemperatureforthermalthrottling.
LockbyCLTT_DEBUG_DISABLE_LOCK.
WhentheCLTT_DEBUG_DISABLE_LOCKisset,thisfieldbecomesread-only,i.
e.
configurationwritetothisbyteisaborted.
Thisbyteisupdatedfrominternallogicfroma2:1MuxwhichcanbeselectedfromeitherCLTTtemperatureorfromthecorrespondingtemperatureregistersoutput(PCODE_TEMP_OUTPUT)updatedfrompcode.
ThemuxselectiscontrolledbyCLTT_OR_PCODE_TEMP_MUX_SELdefinedinCHN_TEMP_CFGregister.
Validrangefrom0to127i.
e.
0Cto+127C.
AnynegativevaluereadfromTSODisforcedto0.
TSODdecimalpointvalueisalsotruncatedtointegervalue.
Type:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x150,0x154BitAttrDefaultDescriptionType:CFGPortID:N/ABus:2Device:10,11,12Function:2,6Offset:0x190,0x192BitAttrDefaultDescription15:15RW0x1THRT_PWR_EN(thrt_pwr_en):bit[15]:settoonetoenablethepowerthrottlingfortheDIMM.
11:0RW0xfffPowerThrottlingControl(thrt_pwr):bit[11:0]:Maxnumberoftransactions(ACT,READ,WRITE)tobeallowed(perDIMM)duringthe1micro-secthrottlingtimeframeperpowerthrottling.
IntegratedMemoryController(iMC)ConfigurationRegisters42SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
4.
2correrrcnt_1PerRankcorrectederrorcounters.
3.
4.
3correrrcnt_2PerRankcorrectederrorcounters.
Type:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x104BitAttrDefaultDescription31:31RW1CS0x0RANK1OVERFLOW(overflow_1):Thecorrectederrorcountforthisrankhasbeenoverflowed.
OncesetitcanonlybeclearedviaawritefromBIOS.
30:16RWS_LV0x0RANK1CORRECTABLEERRORCOUNT(cor_err_cnt_1):Thecorrectederrorcountforthisrank.
HardwareautomaticallyclearsthisfieldwhenthecorrespondingOVERFLOW_xbitischangingfrom0to1.
15:15RW1CS0x0RANK0OVERFLOW(overflow_0):Thecorrectederrorcountforthisrankhasbeenoverflowed.
OncesetitcanonlybeclearedviaawritefromBIOS.
14:0RWS_LV0x0RANK0CORRECTABLEERRORCOUNT(cor_err_cnt_0):Thecorrectederrorcountforthisrank.
HardwareautomaticallyclearthisfieldwhenthecorrespondingOVERFLOW_xbitischangingfrom0to1.
Type:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x108BitAttrDefaultDescription31:31RW1CS0x0RANK3OVERFLOW(overflow_3):Thecorrectederrorcounthascrestedoverthelimitforthisrank.
OncesetitcanonlybeclearedviaawritefromBIOS.
30:16RWS_LV0x0RANK3COR_ERR_CNT(cor_err_cnt_3):Thecorrectederrorcountforthisrank.
15:15RW1CS0x0RANK2OVERFLOW(overflow_2):Thecorrectederrorcounthascrestedoverthelimitforthisrank.
OncesetitcanonlybeclearedviaawritefromBIOS.
14:0RWS_LV0x0RANK2COR_ERR_CNT(cor_err_cnt_2):Thecorrectederrorcountforthisrank.
Type:CFGPortID:N/ABus:1Device:20,21,23Function:2,3Offset:0x10cBitAttrDefaultDescription31:31RW1CS0x0RANK5OVERFLOW(overflow_5):Thecorrectederrorcounthascrestedoverthelimitforthisrank.
OncesetitcanonlybeclearedviaawritefromBIOS.
30:16RWS_LV0x0RANK5COR_ERR_CNT(cor_err_cnt_5):Thecorrectederrorcountforthisrank.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily43Datasheet,VolumeTwo:RegistersApril20193.
4.
4correrrcnt_3PerRankcorrectederrorcounters.
3.
4.
5correrrthrshld_0Thisregisterholdstheperrankcorrectederrorthresholdingvalue.
3.
4.
6correrrthrshld_1Thisregisterholdstheperrankcorrectederrorthresholdingvalue.
15:15RW1CS0x0RANK4OVERFLOW(overflow_4):Thecorrectederrorcounthascrestedoverthelimitforthisrank.
OncesetitcanonlybeclearedviaawritefromBIOS.
14:0RWS_LV0x0RANK4COR_ERR_CNT(cor_err_cnt_4):Thecorrectederrorcountforthisrank.
Type:CFGPortID:N/ABus:1Device:20,21,23Function:2,3Offset:0x10cBitAttrDefaultDescriptionType:CFGPortID:N/ABus:1Device:20,21,23Function:2,3Offset:0x110BitAttrDefaultDescription31:31RW1CS0x0RANK7OVERFLOW(overflow_7):Thecorrectederrorcountforthisrank.
30:16RWS_LV0x0RANK7COR_ERR_CNT_7(cor_err_cnt_7):Thecorrectederrorcountforthisrank.
15:15RW1CS0x0RANK6OVERFLOW(overflow_6):Thecorrectederrorcounthascrestedoverthelimitforthisrank.
OncesetitcanonlybeclearedviaawritefromBIOS.
14:0RWS_LV0x0RANK6COR_ERR_CNT(cor_err_cnt_6):Thecorrectederrorcountforthisrank.
Type:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x11cBitAttrDefaultDescription30:16RW-LB0x7fffRANK1COR_ERR_TH(cor_err_th_1):Thecorrectederrorthresholdforthisrankthatwillbecomparedtotheperrankcorrectederrorcounter.
14:0RW-LB0x7fffRANK0COR_ERR_TH(cor_err_th_0):Thecorrectederrorthresholdforthisrankthatwillbecomparedtotheperrankcorrectederrorcounter.
IntegratedMemoryController(iMC)ConfigurationRegisters44SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
4.
7correrrthrshld_2Thisregisterholdstheperrankcorrectederrorthresholdingvalue.
3.
4.
8correrrthrshld_3Thisregisterholdstheperrankcorrectederrorthresholdingvalue.
3.
4.
9correrrorstatusPerrankcorrectederrorstatus.
Thesebitsareresetbybios.
Type:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x120BitAttrDefaultDescription30:16RW-LB0x7fffRANK3COR_ERR_TH(cor_err_th_3):Thecorrectederrorthresholdforthisrankthatwillbecomparedtotheperrankcorrectederrorcounter.
14:0RW-LB0x7fffRANK2COR_ERR_TH(cor_err_th_2):Thecorrectederrorthresholdforthisrankthatwillbecomparedtotheperrankcorrectederrorcounter.
Type:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x124BitAttrDefaultDescription30:16RW-LB0x7fffRANK5COR_ERR_TH(cor_err_th_5):Thecorrectederrorthresholdforthisrankthatwillbecomparedtotheperrankcorrectederrorcounter.
14:0RW-LB0x7fffRANK4COR_ERR_TH(cor_err_th_4):Thecorrectederrorthresholdforthisrankthatwillbecomparedtotheperrankcorrectederrorcounter.
Type:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x128BitAttrDefaultDescription30:16RW-LB0x7fffRANK7COR_ERR_TH(cor_err_th_7):Thecorrectederrorthresholdforthisrankthatwillbecomparedtotheperrankcorrectederrorcounter.
14:0RW-LB0x7fffRANK6COR_ERR_TH(cor_err_th_6):Thecorrectederrorthresholdforthisrankthatwillbecomparedtotheperrankcorrectederrorcounter.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily45Datasheet,VolumeTwo:RegistersApril20193.
4.
10leaky_bkt_2nd_cntr_regType:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x134BitAttrDefaultDescription31:24RW_V0x0ddr4crc_rank_log:Thisfieldgetsetwith1'b1ifthecorrespondingrankdetectedDDR4CRCinoneofitswritedata.
ThiswillbeclearedbyBIOS.
7:0RW1C0x0ERR_OVERFLOW_STAT(err_overflow_stat):This8bitfieldistheperrankerrorover-thresholdstatusbits.
Theorganizationisasfollows:Bit0:Rank0Bit1:Rank1Bit2:Rank2Bit3:Rank3Bit4:Rank4Bit5:Rank5Bit6:Rank6Bit7:Rank7Note:TheregistertrackswhichrankhasreachedorexceededthecorrespondingCORRERRTHRSHLDthresholdsettings.
Type:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x138BitAttrDefaultDescription31:16RW0x0LEAKY_BKT_2ND_CNTR_LIMIT(leaky_bkt_2nd_cntr_limit):SecondaryLeakyBucketCounterLimit(2bperDIMM).
Thisregisterdefinessecondaryleakybucketcounterlimitforall8logicalrankswithinchannel.
ThecounterlogicwillgeneratethesecondaryLEAKpulsetodecrementtherank'scorrectableerrorcounterby1whenthecorrespondingrankleakybucketrankcounterrolloveratthepredefinedcounterlimit.
ThecounterincrementattheprimaryleakpulsefromtheLEAKY_BUCKET_CNTR_LOandLEAKY_BUCKET_CNTR_HIlogic.
Bit[31:30]:Rank7SecondaryLeakyBucketCounterLimitBit[29:28]:Rank6SecondaryLeakyBucketCounterLimitBit[27:26]:Rank5SecondaryLeakyBucketCounterLimitBit[25:24]:Rank4SecondaryLeakyBucketCounterLimitBit[23:22]:Rank3SecondaryLeakyBucketCounterLimitBit[21:20]:Rank2SecondaryLeakyBucketCounterLimitBit[19:18]:Rank1SecondaryLeakyBucketCounterLimitBit[17:16]:Rank0SecondaryLeakyBucketCounterLimitThevalueofthelimitisdefinedasthefollowing:0:TheLEAKpulseisgeneratedoneDCLKaftertheprimaryLEAKpulseisasserted.
1:theLEAKpulseisgeneratedoneDCLKafterthecounterrolloverat1.
2:theLEAKpulseisgeneratedoneDCLKafterthecounterrolloverat2.
3:theLEAKpulseisgeneratedoneDCLKafterthecounterrolloverat3.
IntegratedMemoryController(iMC)ConfigurationRegisters46SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril20193.
4.
11devtag_cntl_[0:7]SDDCUsagemodelWhenthenumberofcorrectableerrors(CORRERRCNT_x)fromaparticularrankexceedsthecorrespondingthreshold(CORRERRTHRSHLD_y),hardwarewillgenerateaLINKinterruptandlog(andpreserve)thefailingdeviceintheFailDevicefield.
SMMsoftwarewillreadthefailingdeviceontheparticularrank.
SoftwarethensettheENbittoenablesubstituionofthefailingdevice/rankwiththeparityfromtherestofthedevicesinline.
Forindependentchannelconfiguration,eachrankcantagonce.
Upto8rankscanbetagged.
Forlock-stepchannelconfiguration,onlyonex8devicecanbetaggedperrank-pair.
SMMsoftwaremustidentifywhichchannelshouldbetaggedforthisrankandonlysetthevalidbitforthechannelfromthechannel-pair.
Thereisnohardwarelogictoreportincorrectprogrammingerror.
Unpredicableerrorand/orsilentdatacorruptionwillbetheconsequenceofsuchprogrammingerror.
Iftherank-sparingisenabled,itisrecommendtoprioritizetherank-sparingbeforetriggeringthedevicetaggingduetothenatureofthedevicetaggingwoulddropthecorrectioncapabilityandanysubsequentECCerrorfromthisrankwouldcauseuncorrectableerror.
15:0RW_V0x0LEAKY_BKT_2ND_CNTR(leaky_bkt_2nd_cntr):Perranksecondaryleakybucketcounter(2bperrank)bit[15:14]:rank7secondaryleakybucketcounterbit[13:12]:rank6secondaryleakybucketcounterbit[11:10]:rank5secondaryleakybucketcounterbit[9:8]:rank4secondaryleakybucketcounterbit[7:6]:rank3secondaryleakybucketcounterbit[5:4]:rank2secondaryleakybucketcounterbit[3:2]:rank1secondaryleakybucketcounterbit[1:0]:rank0secondaryleakybucketcounterType:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x138BitAttrDefaultDescriptionType:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x140,0x141,0x142,0x143,0x144,0x145,0x146,0x147BitAttrDefaultDescription7:7RWS_L0x0Devicetaggingenableforthisrank(en):DevicetaggingSDDCenableforthisrank.
Onceset,theparitydeviceoftherankisusedforthereplacementdevicecontent.
Aftertagging,therankwillnolongerhavethe"correction"capability.
ECCerror"detection"capabilitywillnotdegradeaftersettingthisbit.
Forlock-stepchannelconfiguration,onlyonex8devicecanbetaggedperrank-pair.
SMMsoftwaremustidentifywhichchannelshouldbetaggedforthisrankandonlysetthecorrespondingDEVTAG_CNTL_x.
ENbitforthechannelcontainsthefaildevice.
TheDEVTAG_CNTL_x.
ENontheotherchannelofthecorrespondingrankmustnotbeset.
IntegratedMemoryController(iMC)ConfigurationRegistersSecondGenerationIntelXeonProcessorScalableFamily47Datasheet,VolumeTwo:RegistersApril2019§5:0RWS_V0x3fFailDeviceIDforthisrank(faildevice):Onceset,theparitydeviceoftherankisusedforthereplacementdevicecontent.
Aftertagging,therankwillnolongerhavethe"correction"capability.
ECCerror"detection"capabilitywillnotdegradeaftersettingthisbit.
Warning:Forlock-stepchannelconfiguration,onlyonex8devicecanbetaggedperrank-pair.
SMMsoftwaremustidentifywhichchannelshouldbetaggedforthisrankandonlysetthecorrespondingDEVTAG_CNTL_x.
ENbitforthechannelcontainsthefaildevice.
TheDEVTAG_CNTL_x.
ENontheotherchannelofthecorrespondingrankmustnotbeset.
DDDC:(EXprocessoronly)OnDDDCsupportedsystems,BIOShastheoptiontoenableSDDCinconjunctionwithDDDC_CNTL:SPARINGtoenablefastersparingwithSDDCsubstitution.
ThisfieldisclearedbyHWoncompletionofDDDCsparing.
Type:CFGPortID:N/Aus:2Device:10,12Function:3,7Offset:0x140,0x141,0x142,0x143,0x144,0x145,0x146,0x147BitAttrDefaultDescriptionIntegratedMemoryController(iMC)ConfigurationRegisters48SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:RegistersApril2019SecondGenerationIntelXeonProcessorScalableFamily49Datasheet,VolumeTwo:Registers,April20194IntelUPIRegistersIntelUPImoduleisthecoherentcommunicationinterfacebetweenprocessors.
ThenumberofsupportedIntelUPIlinksvariesperprocessortype.
Bus:B(3),Device:16-14,Function:0(IntelUPI)4.
1Bus:3,Device:16,14,Function:34.
1.
1ktimiscstatIntelUPIMiscStatus§Bus:B(3)Device:16-14Function:3Offset:D4BitAttrDefaultDescription31:3RSVD-Z00000000hReserved—don'tcare.
2:0RO-V3hkti_rate—ThisreflectsthesupportedcurrentIntelUPIratesettingintothePLL.
100-9.
6GT/s101-10.
4GT/sother-ReservedNote:Thedefaultvalueof3'b011doesnotreflecttheactualIntelUPIrate.
Readsofthisregisterfieldwillalwaysreportoneofthelegaldefinedvaluesabove.
50SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April2019SecondGenerationIntelXeonProcessorScalableFamily51Datasheet,VolumeTwo:Registers,April20195ConfigurationAgent(Ubox)RegistersTheUboxhandlestransactionssuchasregisteraccesses,interruptflows,lockflowsandevents.
Thisincludestransactionsliketheregisteraccesses,interruptflows,lockflowsandevents.
TheUboxhousescoordinationfortheperformancearchitecture,andscratchpadandsemaphoreregisters.
5.
1Bus:0,Device:8,Function:05.
1.
1VIDPCIVendorIDRegister5.
1.
2DIDPCIDeviceIdentificationNumber5.
1.
3CPUNODEIDNodeIDConfigurationRegisterBus:B(0)Device:8Function:0Offset:0BitAttrDefaultDescription15:0RO8086hVendor_Identification_Number—ThevalueisassignedbyPCI-SIGtoIntel.
Bus:B(0)Device:8Function:0Offset:2BitAttrDefaultDescription15:0RO2014hDevice_Identification_Number—Bus:B(0)Device:8Function:0Offset:C0BitAttrDefaultDescription31:16RSVD-Z0000hReserved—don'tcare.
15:13RW-LB0hNodeCtrlId—NodeIDoftheNodeController.
SetbytheBIOS.
12:10RW-LB0hLgcNodeId—NodeIDofthelegacysocket9:8RSVD-Z0hReserved—don'tcare.
7:5RW-LB0hLockNodeId—NodeIdofthelockmaster4:3RSVD-Z0hReserved—don'tcare.
2:0RW-LB0hLclNodeId—NodeIdofthelocalSocket52SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April20195.
1.
4IntControlInterruptConfigurationRegister5.
1.
5GIDNIDMAPMappingbetweengroupidandnodeidBus:B(0)Device:8Function:0Offset:C8BitAttrDefaultDescription31:19RSVD-Z0000hReserved—don'tcare.
18RW-LB0hLogFlatClustOvrEn—0:IA32LogicalFlatorClusterModebitislockedasReadonlybit.
1:IA32LogicalFlatorClusterModebitmaybewrittenbySW,valueswrittenbyxTPRupdateareignored.
ForonetimeoverrideoftheIA32LogicalFlatorClusterModevalue,returnthisbittoit'sdefaultstateafterthebitischanged.
Leavingthisbitas'1'willpreventautomaticupdateofthefilter.
17RW-LBV0hLogFltClustMod—SetbyBIOStoindicateiftheOSisrunninglogicalflatorlogicalclustermode.
ThisbitcanalsobeupdatedbyIntPrioUpdmessages.
Thisbitreflectsthesetupofthefilteratanygiventime.
0-flat,1-cluster.
16RW-LB0hClastChkSmpMod—0:DisablecheckingforLogical_APICID[31:0]beingnon-zerowhensamplingflat/clustermodebitintheIntPrioUpdmessageaspartofsettingbit1inthisregister1:Enabletheabovechecking15:11RSVD-Z00hReserved—don'tcare.
10:8RW0hHashModCtr—Indicatesthehashmodecontrolfortheinterruptcontrol.
SelectthehushfunctionfortheVectorbasedHashModeinterruptredirectioncontrol:000selectbits7:4/5:4forvectorcluster/flatalgorithm001selectbits6:3/4:3010selectbits4:1/2:1011selectbits3:0/1:0other-reserved7RSVD-Z0hReserved—don'tcare.
6:4RW0hRdrModSel—SelectstheredirectionmodeusedforMSIinterruptswithlowest-prioritydeliverymode.
Thefollowingschemesareused:000:FixedPriority-selectthefirstenabledAPICinthecluster.
001:Redirectlast-lastvectorselected(applicableonlyinextendedmode)010:HashVector-selectthefirstenabledAPICinroundrobinmannerstartingformthehashofthevectornumber.
default:FixedPriority3:2RSVD-Z0hReserved—don'tcare.
1RW-LB0hForceX2APIC—Write:1:ForcesthesystemtomoveintoX2APICMode.
0:Noaffect0RW-LB1hxApicEn—SetthisbitifyouwouldlikeextendedXAPICconfigurationtobeused.
Thisbitcanbewrittendirectly,andcanalsobeupdatedusingXTPRmessagesBus:B(0)Device:8Function:0Offset:D4BitAttrDefaultDescription31:24RSVD-Z00hReserved—don'tcare.
23:21RW-LB0hNodeId7—NodeIdforgroupid720:18RW-LB0hNodeId6—NodeIdforgroup617:15RW-LB0hNodeId5—NodeIdforgroup514:12RW-LB0hNodeId4—NodeIdforgroupid4SecondGenerationIntelXeonProcessorScalableFamily53Datasheet,VolumeTwo:Registers,April20195.
1.
6UBOXErrStsThisiserrorstatusregisterintheUboxandcoversmostoftheinterruptrelatederrors5.
2Bus:0,Device:8,Function:2VIDPCIVendorIDRegister5.
2.
1DIDPCIDeviceIdentificationNumber11:9RW-LB0hNodeId3—NodeIdforgroup38:6RW-LB0hNodeID2—NodeIdforgroupId25:3RW-LB0hNodeId1—NodeIdforgroupId12:0RW-LB0hNodeId0—NodeIdforgroup0Bus:B(0)Device:8Function:0Offset:D4BitAttrDefaultDescriptionBus:B(0)Device:8Function:0Offset:C8BitAttrDefaultDescription31:24RSVD-Z00hReserved—don'tcare.
23:18RWS-V00hMsg_Ch_Tkr_TimeOut—MessageChannelTrackerTimeOut.
ThiserroroccurswhenanyNPrequestdoesn'treceiveresponsein4Kcycles.
17RWS-V0hMsg_Ch_Tkr_Err—MessageChannelTrackerError.
ThiserroroccurssuchcasethatillegalbroadcastportIDaccesstothemessagechannel.
16RW-V0hSMI_delivery_valid—SMIinterruptdeliverystatusvalid,write1'b0toclearvalidstatus15:8RO-V00hreserved—reserved7RWS-V0hMasterLockTimeOut—MasterLockTimeoutreceivedbyUbox6RWS-V0hSMITimeOut—SMITimeoutreceivedbyUbox5RWS-V0hCFGWrAddrMisAligned—MMCFGWriteAddressMisalignmentreceivedbyUbox.
AllMMCFGaccessmustbelessthanorequalto4Binlengthandcannotcrossa4Bboundary.
WhenUboxseesamisalignedMMCFGaccess,itwillbeabortingthetransaction.
4RWS-V0hCFGRdAddrMisAligned—MMCFGReadAddressMisalignmentreceivedbyUbox.
AllMMCFGaccessmustbelessthanorequalto4Binlengthandcannotcrossa4Bboundary.
WhenUboxseesamisalignedMMCFGaccess,itwillbeabortingthetransaction.
3RWS-V0hUnsupportedOpcode—UnsupportedopcodereceivedbyUbox2RWS-V0hPoisonRsvd—Uboxreceivedapoisonedtransaction1RWS-V0hSMISrciMC—SMIiscausedduetoanindicationfromtheIMC0RWS-V0hSMISrcUMC—ThisisabitthatindicatesthatanSMIwascausedduetoalocallygeneratedUMCBus:B(0)Device:8Function:2Offset:0BitAttrDefaultDescription15:0RO8086hVendor_Identification_Number—ThevalueisassignedbyPCI-SIGtoIntel.
54SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April20195.
2.
2CPUBUSNOBusNumberConfiguration5.
2.
3CPUBUSNO1BusNumberConfiguration15.
2.
4SMICtrlSMIgenerationcontrol§Bus:B(0)Device:8Function:2Offset:2BitAttrDefaultDescription15:0RO2016hDevice_Identification_Number—Bus:B(0)Device:8Function:2Offset:CCBitAttrDefaultDescription31:24RW-LB03hCPUBUSNO3—BusNumber323:16RW-LB02hCPUBUSNO2—BusNumber215:8RW-LB01hCPUBUSNO1—BusNumber17:0RW-LB00hCPUBUSNO0—BusNumber0Bus:B(0)Device:8Function:2Offset:D0BitAttrDefaultDescription31:16RSVD-Z0000hReserved—don'tcare.
15:8RW-LB05hCPUBUSNO5—BusNumber57:0RW-LB04hCPUBUSNO4—BusNumber4Bus:B(0)Device:8Function:2Offset:D8BitAttrDefaultDescription31:29RSVD-Z0hReserved—don'tcare.
28RW-LB0hSMIDis4—DisableGenerationofSMIfromCSMIfromMsgCh27RW-LB0hSMIDis3—DisableGenerationofSMIfrommessagechannel26RW-LB1hSMIDis2—DisablegenerationofSMIforlocktimeout,cfgwritemis-alignaccess,andcfgreadmis-alignaccess.
25RW-LB0hSMIDis—DisablegenerationofSMI24RSVD-P0hReserved—protected.
23:20RSVD-Z0hReserved—don'tcare.
19:0RSVD-P00000hReserved—protected.
SecondGenerationIntelXeonProcessorScalableFamily55Datasheet,VolumeTwo:Registers,April20196PowerControlUnit(PCU)RegistersThePowerControlUnit(PCU)isadedicatedcontrollerthatprovidespowerandthermalmanagementfortheprocessor.
ThePCUimplementsaPECIinterfaceforout-of-bandmanagement.
ThePCUconsistsofadedicatedmicrocontroller,ROMandRAMforPcode(PCUmicrocode),HWstatemachines,I/Oregistersforinterfacingtothemicrocontrollerandinterfacestothehardwareunitsintheprocessor.
6.
1Bus:B1,Device:30,Function:06.
1.
1VIDPCIVendorIDRegister6.
1.
2DIDPCIDeviceIdentificationNumber6.
1.
3PACKAGE_ENERGY_STATUSPackageenergyconsumedbytheentireCPU(includingCoreandUncore).
Thecounterwillwraparoundandcontinuecountingwhenitreachesitslimit.
6.
1.
4MEM_TRML_TEMPERATURE_REPORT_0Thisregisterisusedtoreportthethermalstatusofthememory.
Thechannelmaxtemperaturefieldisusedtoreportthemaximaltemperatureofallranks.
Bus:B(1)Device:30Function:0Offset:0BitAttrDefaultDescription15:0RO8086hVendor_Identification_Number—ThevalueisassignedbyPCI-SIGtoIntel.
Bus:B(1)Device:30Function:0Offset:2BitAttrDefaultDescription15:0RO2080hDevice_Identification_Number—Bus:B(1)Device:30Function:0Offset:90BitAttrDefaultDescription31:0RO-V00000000hDATA—RefertoMSR611hwhichthisisamirroroffordescription.
56SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April2019MEM_TRML_TEMPERATURE_REPORT_0isusedforchanneltemperatureofDIMMsunderIMC0.
6.
1.
5MEM_TRML_TEMPERATURE_REPORT_1Thisregisterisusedtoreportthethermalstatusofthememory.
Thechannelmaxtemperaturefieldisusedtoreportthemaximaltemperatureofallranks.
MEM_TRML_TEMPERATURE_REPORT_1isusedforchanneltemperatureofDIMMsunderIMC16.
1.
6MEM_TRML_TEMPERATURE_REPORT_2Thisregisterisusedtoreportthethermalstatusofthememory.
Thechannelmaxtemperaturefieldisusedtoreportthemaximaltemperatureofallranks.
6.
1.
7PACKAGE_TEMPERATUREPackagetemperatureindegrees(C).
ThisfieldisupdatedbyFW.
Bus:B(1)Device:30Function:0Offset:94BitAttrDefaultDescription31:24RSVD-P00hReserved—protected.
23:16RO-V00hChannel2_Max_Temperature—TemperatureinDegrees(C).
15:8RO-V00hChannel1_Max_Temperature—TemperatureinDegrees(C).
7:0RO-V00hChannel0_Max_Temperature—TemperatureinDegrees(C).
Bus:B(1)Device:30Function:0Offset:98BitAttrDefaultDescription31:24RSVD-P00hReserved—protected.
23:16RO-V00hChannel2_Max_Temperature—TemperatureinDegrees(C).
15:8RO-V00hChannel1_Max_Temperature—TemperatureinDegrees(C).
7:0RO-V00hChannel0_Max_Temperature—TemperatureinDegrees(C).
Bus:B(1)Device:30Function:0Offset:9CBitAttrDefaultDescription31:24RSVD-P00hReserved—protected.
23:16RO-V00hChannel2_Max_Temperature—TemperatureinDegrees(C).
15:8RO-V00hChannel1_Max_Temperature—TemperatureinDegrees(C).
7:0RO-V00hChannel0_Max_Temperature—TemperatureinDegrees(C).
Bus:B(1)Device:30Function:0Offset:C8BitAttrDefaultDescription31:8RSVD-Z000000hReserved—don'tcare.
7:0RO-V00hDATA—Packagetemperatureindegrees(C).
SecondGenerationIntelXeonProcessorScalableFamily57Datasheet,VolumeTwo:Registers,April20196.
1.
8TEMPERATURE_TARGETLegacyregisterholdingtemperaturerelatedconstantsforPlatformuse.
6.
2Bus:B(1),Device:30,Function:26.
2.
1VIDPCIVendorIDRegister6.
2.
2DIDPCIDeviceIdentificationNumber6.
2.
3DRAM_ENERGY_STATUSDRAMenergyconsumedbyalltheDIMMSinalltheChannels.
Thecounterwillwraparoundandcontinuecountingwhenitreachesitslimit.
ENERGY_UNITforDRAMdomainis15.
3uJ.
ThedataisupdatedbyPCODEandisReadOnlyforallSW.
Bus:B(1)Device:30Function:0Offset:E4BitAttrDefaultDescription31:28RSVD-Z0hReserved—don'tcare.
27:24RW0hTJ_MAX_TCC_OFFSET—RefertoMSR1A2hwhichthisisamirroroffordescription.
23:16RO-V00hREF_TEMP—RefertoMSR1A2hwhichthisisamirroroffordescription.
15:8RO-V00hFAN_TEMP_TARGET_OFST—RefertoMSR1A2hwhichthisisamirroroffordescription.
7:0RSVD-Z00hReserved—don'tcare.
Bus:B(1)Device:30Function:2Offset:0BitAttrDefaultDescription15:0RO8086hVendor_Identification_Number—ThevalueisassignedbyPCI-SIGtoIntel.
Bus:B(1)Device:30Function:2Offset:2BitAttrDefaultDescription15:0RO2082hDevice_Identification_Number—58SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April20196.
2.
4PACKAGE_RAPL_PERF_STATUSThisregisterisusedtoreportPackagePowerlimitviolations.
6.
2.
5DRAM_POWER_INFO6.
2.
6DRAM_RAPL_PERF_STATUSThisregisterisusedbyPcodetoreportDRAMPlanePowerlimitviolationsinthePlatform.
6.
2.
7THERMTRIP_CONFIGThisregisterisusedtoconfigurewhethertheThermtripsignalonlycarriestheprocessorTripinformation,ordoesitcarrytheMemtripinformationaswell.
TheregisterwillbeusedbyHWtoenableORingofthememtripinfointothethermtripORtree.
Bus:B(1)Device:30Function:2Offset:7CBitAttrDefaultDescription31:0RO-V00000000hDATA—RefertoMSR619hwhichthisisamirroroffordescription.
Bus:B(1)Device:30Function:2Offset:88BitAttrDefaultDescription31:0RO-V00000000hPWR_LIMIT_THROTTLE_CTR—RefertoMSR613hwhichthisisamirroroffordescription.
Bus:B(1)Device:30Function:2Offset:A8BitAttrDefaultDescription63RW-KL0hLock—RefertoMSR61Chwhichthisisamirroroffordescription.
62:55RSVD-Z00hReserved—don'tcare.
54:48RW-L28hDRAM_MAX_WIN—RefertoMSR61Chwhichthisisamirroroffordescription.
47RSVD-Z0hReserved—don'tcare.
46:32RW-L0258hDRAM_MAX_PWR—RefertoMSR61Chwhichthisisamirroroffordescription.
31RSVD-Z0hReserved—don'tcare.
30:16RW-L0078hDRAM_MIN_PWR—RefertoMSR61Chwhichthisisamirroroffordescription.
15RSVD-Z0hReserved—don'tcare.
14:0RW-L0118hDRAM_TDP—RefertoMSR61Chwhichthisisamirroroffordescription.
Bus:B(1)Device:30Function:2Offset:D8BitAttrDefaultDescription31:0RO-V00000000hPWR_LIMIT_THROTTLE_CTR—RefertoMSR61Bhwhichthisisamirroroffordescription.
SecondGenerationIntelXeonProcessorScalableFamily59Datasheet,VolumeTwo:Registers,April2019§Bus:B(1)Device:30Function:2Offset:F8BitAttrDefaultDescription31:4RSVD-Z0000000hReserved—don'tcare.
3:1RSVD-P0hReserved—protected.
0RW-LB0hEN_MEMTRIP—Ifsetto1,PCUwillORintheMEMtripinformationintotheThermTripORTreeIfsetto0,PCUwillignoretheMEMtripinformationandThermTripwilljusthavetheprocessorindication.
ExpectBIOStoEnablethisinPhase460SecondGenerationIntelXeonProcessorScalableFamilyDatasheet,VolumeTwo:Registers,April2019