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SED1278LCDController/DriversTechnicalManual–i–SED1278ContentsOVERVIEW9–1FEATURES9–1BLOCKDIAGRAM9–2PACKAGEOUTLINE9–2PINOUT9–3PINDESCRIPTION9–4TERMINALCONFIGURATION9–5INSTRUCTIONDESCRIPTION9–6SPECIFICATIONS9–10OPERATION9–16THECHARACTERGENERATOR9–21LCDINTERFACE9–23MPUINTERFACE9–30COMPARISONWITHHD44780BYHITACHI9–31APPENDIXA:CHARACTERCODESANDFONTS9–32APPENDIXB:PINCONSTRUCTION9–38EPSON9–1SED1278SED1278FEATURESInterfacefor4-and8-bitMPUsDisplayRAM–80bytes(80characters)CharactergeneratorROM–240characters–5*8pixelfontCharactergenratorRAM–64bytes–5*8pixelfont,8characters.
–5*10pixelfont,4characters.
NumberofcharactersusedPowerfuldisplaycontrolinstructionsLCDdriveroutputs–40segmentdriveroutputs–16commondriveroutputsLowLCDdrivevoltage–3Vminimum(VDD–V5)Dual-frameACdriveOn-chippower-onresetOn-chipRCoscillatorSingle5VoperationChip(SED1278D)and80-pinQFP(SED1278F)packages(CompatiblewithHD44780andHD66780byHitachiLimited)TheSED1278isequivalenttotheHD44780andHD66780byHitachiLimited.
Beforeuse,makesurethatthereisnoproblemforpracticaluse.
Itshouldbenotedthatthisisnotintendedtoguaranteeenforcementofindustrialpropertyandotherrights,ortograntlicensefortheuseofthisproduct.
OVERVIEWTheSED1278isadedicatedcharacterdisplaycontroller/driverwhich,whenusedwiththeSED1181FortheSED1681segmentdrivres,isabletodisplayupto80charactersunder4-or8-bitMPUcontrol.
Theinternalcharactergenerator(CG)ROMhasanextended240,5*10pixel,characterset,plusCGRAMspaceforanadditionaleightuserdefinable5*8pixelcharacters.
Thesememoryfeaturescombinedwiththerichsetofcontrolinstructionsofferthepotentialforahighlyflexiblecharacterdisplaysystem.
TheSED1278featuresaguaranteedminimumLCDdrivevoltageof3VmakingitsuitableforusewithlowvoltageLCDpanels.
DutySED1278FSED1181FLANo.
ofcharactersusedOne-line1/8,108columnsdisplay1/11*1line680columns*1lineTwo-line1/16108columnsdisplay*2lines340columns*2lines9–2EPSONSED1278BLOCKDIAGRAMDB0toDB7ER/WRSVSSVDCV1V2V3V4V5COM1toCOM16SEG1toSEG40XSCLLPFRDOOSC1OSC2855577I/OBufferI/OControlInstructionDecoderCursor/PrinterControlInstructionRegisterDaiaRegisterMPXMPXMPXCharacterGeneratorRAM(CGRAM)64BitsCharacterGeneratorRAM(CGROM)5x10x240BitsDisplayDataRAMDDRAM80BytesParallel/SerialDataConverterAddressCounterACCRefreshAddressCounterTimingGeneratorShiftRegister16BitsCommonDrivingOutputCircuitSegmentDrivingOutputCircuitLatchCircuit40BitsShiftRegister40BitsOscillationCircuitPACKAGEOUTLINE654080254164241EPSON9–3SED1278SED127825SED1278D2414164408065PINOUTPinNumberName1SEG222SEG213SEG204SEG195SEG186SEG177SEG168SEG159SEG1410SEG1311SEG1212SEG1113SEG1014SEG915SEG816SEG717SEG618SEG519SEG420SEG3PinNumberName21SEG222SEG123GND24OSC125OSC226V127V228V329V430V531LP32XSCL33VDD34FR35DO36RS37R/W38E39DB040DB1PinNumberName41DB242DB343DB444DB545DB646DB747COM148COM249COM350COM451COM552COM653COM754COM855COM956COM1057COM1158COM1259COM1360COM14PinNumberName61COM1562COM1663SEG4064SEG3965SEG3866SEG3767SEG3668SEG3569SEG3470SEG3371SEG3272SEG3173SEG3074SEG2975SEG2876SEG2777SEG2678SEG2579SEG2480SEG239–4EPSONSED1278PINDESCRIPTIONMPUInterfaceRSRegisterselectsignalinput.
SelectsbetweenthedataandinstructionregistersduringCPUaccess.
RS=0:InstructionregisteraccesscycleRS=1:DataregisteraccesscycleR/WThisinputselectsbetweenSED1278registerreadandwritecycles.
R/W=0:RegisterwritecycleR/W=1:RegisterreadcycleERead/writeexecutesignalinput.
LCDPanelInterfaceCOM1toCOM16CommondriveroutputstotheLCDpanel.
SEG1toSEG40SegmentdriveroutputstotheLCDpanel.
OSC1IftheinternalRCoscillatorisusedtogeneratetheLCDdrivesignals,thefeedbackresistor,Rf,isconnectedtothispin.
Ifanexternalclocksourceisused,theclockisconnectedtothispin.
OSC2IftheinternalRCoscillatorisusedtogeneratetheLCDdrivesignals,thefeedbackresistor,Rf,isconnectedtothispin.
Ifanexternalclocksourceisused,thispinisleftopen.
DB0toDB7TTLleveldatainput/outputlines,forconnectiontothesystemMPUdatabus.
TABLE1TheFunctionoftheESignalRS0011R/W0101E11InstructionwritecycleDDRAMorCGRAMdatawritecycleDDRAMorCGRAMdatareadcycleBusyflagreadcycleAddresscounterreadcycleOperationExternalSegmentDriverInterfaceLPDatalatchpulseoutputforanexternalX-driver.
XSCLDatashiftclockoutputforanexternalX-driver.
FRLCDAC-drivewaveformforanexternalX-driver.
DODisplaydataoutputforanexternalX-driver.
EPSON9–5SED1278SED1278TERMINALCONFIGURATION1.
Inputterminalconfiguration(1)VDDInternalApplicableterminal·E·OSCIVSS2.
Inputterminalconfiguration(2)Withpull-upMOSresistorVDDApplicableterminal·RS,R/WVSSInternal3.
OutputterminalconfigurationVDDApplicableterminal·OSC2·XSCL,LP,FR,DOVSSInternal9–6EPSONSED12784.
Input/OutputterminalconfigurationVDDApplicableterminal·DBOtoDB7InternalVSSINSTRUCTIONDESCRIPTIONInstructionSummary*Don'tcareInstructionCodeDescriptionCycleTimeRSR/WDB7DB6DB5DB4DB3DB2DB1DB0(max.
)ClearDisplay0000000001ClearsalldisplaydataandsetsDDRAM410clocksaddress0intheaddresscounter.
SetDDRAMaddress0intheaddressReturnHome000000001*counter.
Alsoreturnsanyshifteddatato410clockshome.
ThecontentsofDDRAMremainunchanged.
SpecifiesthedirectioninwhichthecursorEntryModeSet00000001I/DSmovesandwhetherthedisplayistobe10clocksshiftedornot,whendataiswritentoorreadfrommemorySetsalldisplayon/off(D)cursoron/off(C),DisplayON/OFF0000001DCBandcharacterblinkinginthecursorposition10clocks(B).
Cursoror000001S/CR/L**Movesthecursorandshiftsthedisplay10clocksDisplayShiftwithoutchangingthecontentsofDDRAM.
Setstheinterfacedatalength(IF),numberofSystemSet00001IFNF**characterstobedisplayed(N),andcharacter10clocksfont(F).
SetCGRAM0001ACGSetCGRAMaddresses,followedby10clocksAddresstransferofCGRAMdata.
SetDDRAM001ADDSetsDDRAMaddress,followedby10clocksAddresstransferofDDRAMdata.
ReadBusyFlagReadsthebusyflag(BF)whichindicatesandAddress01BFACCinternaloperationandthecontentsofthe0addresscounter.
WriteDatato10WriteDataWritesdatatoDDRAMorCGRAM.
10clocksCGorDDRAMReadDatafrom11ReadDataReadsdatafromDDRAMorCGRAM.
10clocksCGorDDRAMEPSON9–7SED1278SED1278WriteOnlyInstructionsClearDisplayDB7DB6DB5DB4DB3DB2DB1DB00000000101HRS=0Thisinstruction1.
loadsalllocationsinthedisplaydata(DD)RAMwith20H.
2.
clearsthecontentsoftheaddresscounterto0H.
3.
setsthedisplayforzerocharactershift.
4.
setstheaddresscountertopointtotheDDRAM.
5.
,ifthecursorisdisplayed,movesthecursortotheleftmostcharacterinthedisplayor,ifatwolinedisplayisused,movesthecursortotheleftmostcharacterinthetopline(line1).
6.
setstheaddresscountertoincrementoneachaccessofDDRAMorCGRAM.
CursorHomeDB7DB6DB5DB4DB3DB2DB1DB00000001*02H,03HRS=0Thisinstruction1.
clearsthecontentsoftheaddresscounterto0H.
2.
setstheaddresscountertopointtotheDDRAM.
3.
setsthedisplayforzerocharactershift.
4.
,ifthecursorisdisplayed,movesthecursortotheleftmostcharacterinthedisplayor,ifatwolinedisplayisused,theleftmostcharacterinthetopline(line1).
EntryModeSetDB7DB6DB5DB4DB3DB2DB1DB0000001I/DS04Hto07HRS=0TheI/DbitselectsthewayinwhichthecontentsoftheaddresscounteraremodifiedaftereveryaccesstoDDRAMorCGRAM.
I/D=1:Theaddresscounterisincremented.
I/D=0:Theaddresscounterisdecremented.
TheSbitenablesdisplayshift,insteadofcursorshift,aftereachwriteorreadtotheDDRAM.
S=1:Displayshiftenabled.
S=0:Cursorshiftenabled.
Thedirectioninwhichthedisplayisshiftedisoppositeinsensetothatofthecursor.
ForexampleifS=0andI/D=1thecursorwouldshiftonecharactertotherightafteranMPUwritetoDDRAM.
HoweverifS=1andI/D=1,thedisplaywouldshiftonecharactertotheleftandthecursorwouldmaintainitspositiononthepanel.
ThecursorwillalreadybeshiftedinthedirectionselectedbyI/DduringreadsoftheDDRAM,irrespectiveofthevalueofS.
SimilarlyreadingandwritingtheCGRAMalwaysshiftsthecursor.
Notethatifatwolinedisplayisusedbothlineswillbeshiftedsimultaneously.
DisplayON/OFFDB7DB6DB5DB4DB3DB2DB1DB000001DCB08Hto0FHRS=0Thisinstructioncontrolsvariousfeaturesofthedisplay.
TheDbitturnstheentiredisplayonoroff.
D=1:DisplayonD=0:DisplayoffTheCbitturnsthecursoronoroff.
C=1:CursoronC=0:CursoroffTheBbitenablesblinkingofthecharacterthecursorcoincideswith.
B=1:BlinkingonB=0:BlinkingoffBlinkingisachievedbyalternatingbetweenanormalandalldarkdisplayofacharacter.
Theblinkingperiodissetat204800fOSC.
ForexampleiffOSC=250kHzthecursorwillblinkwithaperiodof0.
8192seconds,orabout1.
2Hz.
Cursor/DisplayShiftDB7DB6DB5DB4DB3DB2DB1DB00001S/CR/L**10Hto1FHRS=0Thisinstructionshiftsthedisplayand/ormovesthecursor,oncharactertotheleftorright,regardlessofaDDRAMready/write.
TheS/Cbitselectsmovementofthecursorormovementofboththecursorandthedisplay.
S/C=1:ShiftbothcursoranddisplayS/C=0:ShiftcursoronlyTheR/Lbitselectsleftwardorrightwardmovementofthedisplayand/orcursor.
R/L=1:ShiftonecharacterrightR/L=0:ShiftonecharacterleftSystemSetDB7DB6DB5DB4DB3DB2DB1DB0001IFNF**20Hto3FHRS=0Thisinstructioninitializesthesystem,andmustbethefirstinstructionexecutedafterpower-on.
TheIFbitselectsbetweenan8-bitora4-bitMPUinterface.
IF=1:8-bitMPUinterfaceusingDB7toDB0.
IF=0:4-bitMPUinterfaceusingDB7toDB4.
TheNandFbitsselectthenumberofdisplaylinesandthecorrespondingdutycycle,aslistedintable2.
9–8EPSONSED1278SetCGRAMAddressDB7DB6DB5DB4DB3DB2DB1DB001ACR40Hto7FHRS=0Thisinstruction1.
loadsanew6-bitaddressintotheaddresscounter.
2.
setstheaddresscountertoaddressCGRAM.
Once"SetCGRAMAddress"hasbeenexecuted,thecontentsoftheaddresscounterwillbeautomaticallymodifiedaftereveryaccessofCGRAM,asdeterminedbythe"EntryModeSet"instruction.
Ifthe"SetCGRAMAddress"instructionisissuedbythesystemMPUwhilethedisplayisenabled,andifeitherthecursorisonorblinkison,pseudo-cursororpseudo-blinkappears.
Topreventthis,turnboththecursoranddisplayblinkoffbeforeloadinganewCGRAMaddress.
Theactivewidthoftheaddresscounter,whenitisaddressingCGRAM,is6-bitssothecounterwillwraparoundto00Hfrom3FHifmorethan64bytesofdataarewrittentoCGRAM.
SetDDRAMAddressDB7DB6DB5DB4DB3DB2DB1DB01ADDRS=080HtoCFH…1line80HtoA7Hline1…2lineC0HtoE7Hline2…2lineThisinstruction1.
loadsanew7-bitaddressintotheaddresscounter.
2.
setstheaddresscountertopointtotheDDRAM.
Oncethe"SetDDRAMAddress"instructionhasbeenexecuted,thecontentsoftheaddresscounterwillbeautomaticallymodifiedaftereachaccessofDDRAM,asselectedbythe"EntryModeSet"instruction.
TheSED1278hasonly80DDRAMlocations.
Thevalidaddressspacesforvariousdisplayconfigurationsarelistedintable3.
TABLE3ValidCGRAMAddressRangesWriteDataDB7DB6DB5DB4DB3DB2DB1DB0DATARS=1ThisinstructionwritesthedatainDB7toDB0intoeithertheCGRAMortheDDRAM.
TheRAMspace(CGorDD),andtheaddressinthatspace,thatisaccesseddependsonwhethera"SetCGRAMAddress"ora"SetDDRAMAddress"instructionwaslastexecuted,andontheparametersofthatinstruction.
Thecontentsoftheaddresscounterwillbeautomaticallymodifiedaftereach"WriteData",asdeterminedby"EntryModeSet".
WhendataiswrittentotheCGRAM,theDB7,DB6andDB5bitsarenotdisplayeddirectlyascharacters.
TABLE2CombinationsofDisplayLinesandDutyCycleNFNumberofDutyCommonOutputNon-SelectedCommonLineRatioSignalOutputSignal001line1/8COM1toCOM8COM9toCOM16011line1/11COM1toCOM11COM12toCOM161*2lines1/16COM1toCOM16—NumberofLinesCharactersADR1-line8000Hto4FH2-line1stline4000Hto27H2ndline4040Hto67HEPSON9–9SED1278SED1278ReadOnlyInstructionsReadBusyFlag/AddressCounterDB7DB6DB5DB4DB3DB2DB1DB0BFACCRS=1Readingtheinstructionregisteryieldsthecurrentvalueoftheaddresscounterandthebusyflag.
Thisinstructionmustbeexecutedpriortoanyotherinstructions.
ACC,theaddresscountervalue,willpointtoalocationineitherCGRAMorDDRAM,dependingonthetypeof"SetRAMAddress"instructionlastsent.
In"BusyFlagCheck"immediatelyafterexecuting"RAMAddressSet"instruction,avalidaddresscountervaluecanberead5clockcyclesafterthebusyflag(BF)goeslow.
In"BusyFlagCheck"immediatelyafterexecuting"WriteData"instruction,avalidaddresscountervaluecanbereadyassoonasBFgoeslow.
TheBFbitshowsthestatusofthebusyflag.
BF=1:SED1278busy.
BF=0:SED1278readyfornextinstruction.
ReadDataDB7DB6DB5DB4DB3DB2DB1DB0DATARS=1ThisinstructionreadsdatafromeitherCGRAMorDDRAM,dependingonthetypeof"SetRAMAddress"instructionslastsent.
Theaddressinthatspacedependsonthe"SetRAMAddress"instructionsparameters.
Immediatelybeforeexecuting"ReadData","SetCGRAMAddress"or"SetDDRAMAddress"mustbeexecuted.
Thecontentsoftheaddresscounteraremodifiedaftereach"ReadData",asdeterminedby"EntryModeSet".
Displayshiftisnotexecuted,independentlyof"EntryModeSet".
9–10EPSONSED1278SPECIFICATIONSAbsoluteMaximumRatingsNotes:1.
VDD>V1>V2>V3>V4>V5>VSS2.
Aflatpackageproductcanbecomelessresistanttomoistureifexposedtoextremetemperatures.
Whenmountingthispackageonaprintedcircuitboard,useasolderingtechniquewhichavoidsexcessivethermalloadingofthepackageresin.
3.
AllvoltagesassumeVSS=0V.
DCCharacteristics(VDD=5.
0V±10%,VSS=0V,Ta=–20to+75°C)ParameterSymbolConditionRatingUnitApplicablePinsmintypmax"H"levelinputvoltage(1)(TTL)VIH12.
0—VDDVDB0toDB7,RS,"L"levelinputvoltage(1)(TTL)VIL1VSS—0.
8VR/W,E"H"levelinputvoltage(2)(CMOS)VIH2VDD–1.
0—VDDVOSC1"L"levelinputvoltage(2)(CMOS)VIL2VSS—1.
0V"H"leveloutputvoltage(1)(TTL)VOH1–IOH=0.
205mA2.
4——VDB0toDB7"L"leveloutputvoltage(1)(TTL)VOL1IOL=1.
6mA——0.
4V"H"leveloutputvoltage(2)VOH2–IOH=0.
04mA0.
9VDD——V(CMOS)XSCL,LP,DO"L"leveloutputvoltage(2)VOL2IOL=0.
04mA——0.
1VDDV(CMOS)Driver-onresistor(COM)RCOM|VCOM–Vn|=0.
5V—210kCOM1toCOM16Driver-onresistor(SEG)RSEG|VSEG–Vn|=0.
5V—2.
510kSEG1toSEG40I/OleakagecurrentIILVIN=0toVDD——1APull-upMOScurrent–IPVDD=5V50125250ADB0toCB7,RS,R/WRfoscillation,fromSupplycurrentIOPexternalclock—0.
50.
8mAVDDVDD=5V,fOSC=fCP=270kHzParameterSymbolRatingUnitSupplyvoltage(1)VDD–3to+7.
0VSupplyvoltage(2)*V1toV5–0.
3toVDD+0.
3VInputvoltageVIN–0.
3toVDD+0.
3VOperatingtemperatureTopr–20to+75°CStoragetemperatureTstg–65to+150°CSolderingtemperature*time**Tsol260,10°C,sPowerdissipationPD300mWEPSON9–11SED1278SED1278ACCharacteristicsMPUwritecycletiming(writetoSED1278)R/WtAStWEHtAHtAHVIL1VIL1VIH1VIH1tcycEVIL1tDStDHtrEtFEVIL1VIH1RSEDB0toDB7ValidDataMPUreadcycletiming(readfromSED1278)R/WRSVIH1VIH1tWEHVIH1VOH1tcycEVOL1trEtRDtDHRVIL1tfEtAHtAHtASVIL1EDB0toDB7ValidData(VDD=5.
0V±10%,VSS=0V,Ta=–20to70°C)ParameterSymbolConditionRatingUnitminmaxEnablecycletimetcycE500—nsEnable"H"levelpulsewidthtWEH220—nsEnablerise/falltimetrE,tfE—25nsRS,R/WsetuptimetAS40—nsRS,R/WaddressholdtimetAH10—nsDatasetuptimetDS60—nsWritedataholdtimetDH10—ns9–12EPSONSED1278ExternalsegmentdriversignaltimingLP0.
9VDD0.
1VDD0.
1VDD0.
9VDD0.
1VDD0.
9VDD0.
9VDD0.
9VDD0.
1VDD0.
9VDD0.
1VDDtWCLHtWCLHtWCLLtDSLPtDHXtOSXtDFRtDSLP0.
1VDDXSCLDOFR(VDD=5.
0V±10%,VSS=0V,Ta=–20to75°C)ParameterSymbolConditionRatingUnitminmaxEnablecycletimetcycE500—nsEnable"H"levelpulsewidthtWEH220—nsEnablerise/falltimetrE,tfE—25nsRS,R/WsetuptimetAS40—nsRS,R/WaddressholdtimetAH10—nsReaddatasetuptimetRDCL=100pF—120nsReaddataholdtimetDHR20—ns(VDD=5.
0V±10%,VSS=0V,Ta=–20to70°C)ParameterSymbolConditionRatingUnitminmaxClockpulsewidth:HighleveltWCLH0.
8/2fOSC—nsClockpulsewidth:LowleveltWCLL0.
8/2fOSC—nsLatchpulsesetuptimetDSLP0.
7/2fOSC—nsDatasetuptimetOSX0.
7/2fOSC—nsDataholdtimetDHX0.
7/2fOSC—nsFRdelaytDFR–10001000nsEPSON9–13SED1278SED1278Power-onresettiming0.
1ms≤tr≤10ms(Ta=–20to75deg.
C)toff≥1mstrtoff0.
2V4.
5VLCDDriveVoltagesMechanicalSpecificationsSED1278FPackageDimensions65804025640.
992±0.
016(25.
2±0.
4)0.
787±0.
004(20.
0±0.
1)0.
756±0.
016(19.
2±0.
4)0.
551±0.
004(14.
0±0.
1)0.
031±0.
006(0.
8±0.
15)0.
006±0.
002(0.
15±0.
05)0.
079±0.
004(2.
0±0.
1)0.
102(2.
6)0.
014±0.
004(0.
35±0.
1)0to12°0.
047±0.
012(1.
2±0.
3)411Index24PinDuty1/8or1/11Duty1/16V13/4(VDD–V5)4/5(VDD–V5)V22/4(VDD–V5)3/5(VDD–V5)V32/4(VDD–V5)2/5(VDD–V5)V41/4(VDD–V5)1/5(VDD–V5)V5V5V59–14EPSONSED1278SED1278DPackageDimensionsChipsize:4.
50mm*3.
67mmChipthickness:400mPadsize:109m*109mPadpitch:182m25YX2414164408065EPSON9–15SED1278SED1278PadX(m)Y(m)NumberName41DB2–2087–167142DB3–1905–167143DB4–1723–167144DB5–1541–167145DB6–1359–167146DB7–1177–167147COM1–995–167148COM2–814–167149COM3–633–167150COM4–452–167151COM5–272–167152COM6–91–167153COM791–167154COM8272–167155COM9452–167156COM10633–167157COM11814–167158COM12995–167159COM131177–167160COM141359–167161COM151541–167162COM161723–167163SEG401905–167164SEG392087–167165SEG382087–136566SEG372087–118367SEG362087–100168SEG352087–81969SEG342087–63770SEG332087–45571SEG322087–27372SEG312087–9173SEG3020879174SEG29208727375SEG28208745576SEG27208763777SEG26208781978SEG252087100179SEG242087118380SEG2320871365PadX(m)Y(m)NumberName1SEG22208716712SEG21190516713SEG20172316714SEG19154116715SEG18135916716SEG17117716717SEG1699516718SEG1581416719SEG14633167110SEG13452167111SEG12272167112SEG1191167113SEG10–91167114SEG9–272167115SEG8–452167116SEG7–633167117SEG6–814167118SEG5–995167119SEG4–1177167120SEG3–1359167121SEG2–1541167122SEG1–1723167123GND–1905167124OSC1–2087167125OSC2–2087136526V1–2087118327V2–2087100128V3–208781929V4–208763730V5–208745531LP–208727332XSCL–20879133VDD–2087–9134FR–2087–27335DO–2087–45536RS–2087–63737R/W–2087–81938E–2087–100139DB0–2087–118340DB1–2087–13659–16EPSONSED1278OPERATIONTheBusyFlagTheSED1278takesbetween10and410clockcyclestoexecuteinstructions.
Duringthatperiodadditionalinstructionsshouldnotbeissued.
Thedeviceisprovidedwithabusyflagtolettheuserchecktheinternalstateofthechip.
BFshouldbe0beforeanotherinstructionisissued.
Ifthebusyflagisnotcheckedbetweeninstructionstheusermustarrangeforaguaranteeddelayofmorethantheinstructionexecutiontime,beforeissuingthenextinstruction.
4-BitMPUInterfaceIfa"SystemSet"instructionisissuedwithbit4setto0,thentheSED1278willoperatewitha4-bitMPUdatabusinterface.
Ifa4-bitinterfaceisused,the8-bitinstructionsarewrittennibblebynibble;thehigh-ordernibblebeingwrittenfirst,followedbythelow-ordernibble.
Itisnotnecessarytocheckthebusyflagbetweenwritingseparatenibblesofindividualinstructions.
ReadingtheBusyFlag/AddressCounteryieldsthehigh-ordernibblefirst,followedbythelow-ordernibble.
SystemInitializationPower-onresetAlthoughtheSED1278hasnoexternalresetinput,itwillautomaticallyresetonsystempower-on.
ThesequencestartsonceVDDcommendedthatasoftwareinitializationsequenceisfollowed.
SoftwareInitialization(8-bitMPUbus,fOSC=250kHz)[1]000011**************DB7RSR/WEDB030msormore4.
1msormore100sormore40sormoreSystemsetSystemset[2][3][4][5][7]000011DB7RSR/WEDB0000011DB7RSR/WEDB0Systemset[6]000011NFDB7RSR/WEDB0BF=0BF011DB7RSR/WEDB0BusyflagBF=0BF=1BF=1BF011DB7RSR/WEDB0BusyflagPower-onSystemsetACCACC9–18EPSONSED12780000001000DB7·RSR/WEDB0DisplayClear[8][10][11][9][13]0000000001DB7RSR/WEDB0EntryModeset[12]00000001I/DSDB7RSR/WEDB0Initializeend[14]BF=0BF011DB7RSR/WEDB0BusyflagBF=0BF=1BF=1BF=0BusyflagDisplayoffBF=1BF011DB7RSR/WEDB0BusyflagDisplayon/offACCBF00DB7RSR/WEDB0ACCACCEPSON9–19SED1278SED1278SoftwareInitialization(4-bitMPUbus,fOSC=250kHz)[1]000011DB7RSR/WE··DB430msormore4.
1msormore100sormore40sormoreSystemsetSystemset[2][3][4][6][8]000011DB7RSR/WE··DB4000011DB7RSR/WE··DB4Systemset[7]NF**0010DB7··DB440sormoreSystemset[5]000010DB7RSR/WE··DB4BF=0(High-order)(Low-order)(High-order)(Low-order)(High-order)(Low-order)BF011DB7RSR/WE··DB4BusyflagBF=0BF=1BF=1BusyflagPower-onSystemsetACC01100RSR/WE00ACCBF011DB7RSR/WE··DB4ACC011ACC9–20EPSONSED1278[9][10][12]Displayclear[11]00010000DB7··DB4BF=0(High-order)(Low-order)(High-order)(Low-order)(High-order)(Low-order)BF011DB7RSR/WE··DB4BusyflagBF=0BF=1BF=1BusyflagDisplayon/offACC01100RSR/WE0010000000DB7··DB4(High-order)(Low-order)00RSR/WE00ACCBF011DB7RSR/WE··DB4ACC011ACC[14]EntryModeset[13]Initializeend[15]01I/DS0000DB7··DB4(High-order)(Low-order)(High-order)(Low-order)BF=0BF=1Busyflag00RSR/WE00BF011DB7RSR/WE··DB4ACC011ACCEPSON9–21SED1278SED1278THECHARACTERGENERATORCharacterGeneratorROM(CGROM)TheSED1278containsa240character,maskedCGROM.
Eachcharacteris5*10pixels,for1/11dutycyclecompatibility.
RefertoAppendixAforavailablecodesandtheircorrespondingfonts.
BecausetheCGROMismasked,customersmayarrangetohavetheirownCGROMmasksmade.
Acustommaskallowstheusertohavetheirowncharacterset.
acharactersetofupto256characters.
PleasecontacttheSEIKOEPSONMarketingDepartmentforfurtherinformation.
IfacustomCGROMisused,twothingsshouldbenoted.
1.
The"ClearDisplay"instructionreliesonthecharacterwhosecodeis20Hbeingablank.
2.
Ifmorethan240ROMedcharactersarespecified,thenthenumberofCGRAMcharactersavailableiscorrespondinglyreduced.
ThephysicalRAMspaceisstillavailable,andisavailableforuseasmemory,howeveritwillnolongerhaveanassociatedcharactercode.
3.
ThecharacterROMimplementedinaparticularchipisindicatedbyatwocharactersuffixattachedtothedevicenumber,forexampleSED1278F0A.
CharacterGeneratorRAM(CGRAM)TheSED1278has64bytesofCGRAM,allowingtheusertoprogramupto8characters.
5*8pixelfont(1/8or1/16dutycycle)Themaximumcharacterheightis8pixels,howeverifacursorisusedrow7shouldbeallzeros.
8suchcharactersareavailabletotheuser.
TheCGRAMaddressismadeupofthefollowingcomponents.
Theleastsignificantthreebits,a2toa0,specifytherownumberofthecharacterdata.
Bitsa5toa3aremadeupoftheleastsignificantthreebitsofthecharactercode.
Themostsignificantbit,a7,isignored.
Figure1showsanexample5*8pixelfont.
Figure1A5*8PixelFontCGRAMaddressCGRAMdata(Characterpattern)A5····A0DB7DB0000000***00001000001***00001000010***01001000011***11111000100***01000000101***00000000110***00000000111***000009–22EPSONSED12785*11pixelfont(1/11dutycycle)Themaximumcharacterheightis11pixels,howeverifacursorisusedrow10mustbeleftblank.
TheSED1278requiresthat,althoughthemaximumcharacterheightis11rows,eachcharacterisallocated16rows(bytes)ofaddressspace.
Thelastfivebytesareignored.
TheCGRAMaddressismadeupofthefollowingcomponents.
Figure2A5*11PixelFontTheleastsignificant4bits,a3toa0,specifytherownumberofthecharacterdata.
Bitsa5anda4correspondtobits2and3,respectively,ofthecharactercode.
Themostsignificantbit,a7,isignored.
Figure2showsanexample5*11pixelfont.
CGRAMaddressCGRAMdataA5····A0DB7DB0000000***00001000001***00001000010***00001000011***00101000100***01001000101***11111000110***01000000111***00100001000***00000001001***00000001010***00000001011001100001101001110001111EPSON9–23SED1278SED1278LCDINTERFACELCDDriveVoltagesTheSED1278generatessegmentandcommondrivesignalsusingthevoltagessuppliedtopinsV1,V2,V3,V4andV5.
Thevoltagelevelsatthesepinsdependonthedutycycleofthedisplay.
Thespecificationsofthesevoltages.
Thesimplestwayofproducingthesevoltagesistousearesistivedividingnetwork.
Figures3and4showexamplesofnetworksfor1/8,or1/11,and1/16dutycyclesrespectively.
SED1278RRRRCCCCCOVRVDDV1V2V3V4V5VSSFigure3LCDDriveVoltageNetwork–1/8or1/11DutyCycleSED1278RRRRRCCCCCCOVRVDDV1V2V3V4V5VSSFigure4LCDDriveVoltageNetwork–1/16DutyCycleNotes:1.
V5issetusingapotentiometerand(VDD–VSS).
2.
ThepowersupplytotheSED1278shouldbebypassedwithacapacitor,CO,ofatleast0.
1Fplacedasclosetothechipaspossible.
9–24EPSONSED1278LCDDriveSignalWaveformsThesegmentandcommondrivewaveformsgeneratedbytheSED1278,forvariousdutycycleratios,areshowninfigures5,6and7.
FRtFRtFRVDDVSSVDDV1V4V5VDDV1V4V5VDDV1V4V5VDDV2,V3V5.
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COM1COM2COM8SEG1······Figure51/8DutyCycleDriveWaveformsFRtFRtFRVDDVSSVDDV1V4V5VDDV1V4V5VDDV1V4V5VDDV5,V3V5COM1COM2COM11SEG1.
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······Figure61/11DutyCycleDriveWaveformsEPSON9–25SED1278SED1278FRtFRtFRVDDVSSVDDV1V4V5VDDV1V4V5VDDV1V4V5VDDV5,V3V5COM1COM2COM16SEG1.
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······Figure71/16DutyCycleDriveWaveformsLCDInterfaceConfigurationsTheSED1278has16commonand40segmentdriveoutputs,enablingthechiptodriveupto16charactersbyitself.
Thedrivecapabilitycanbeexpandedto80characters,byusingSED1181FLAexternalsegmentdrivers.
1line8characters5*7pixels+cursor1/8dutycycleSystemset:N=0,F=0SED1278COM11No.
ofcharactersLCDpanel8COM7COM8SEG1SEG40············.
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9–26EPSONSED12781line8characters5*10pixels+cursor1/11dutycycleSystemset:N=0,F=1SED1278COM118COM10COM11SEG1SEG40No.
ofcharactersLCDpanel···············.
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1line20characters5*7pixels+cursor1/8dutycycleSystemset:N=0,F=0SED1278COM1SEG0SEG59SEG60toSEG63NCOpenDO1D0D1XSCLSED1181FLALPFRDO0COM7COM8SEG1SEG40DOXSCLLPFR18920No.
ofcharactersLCDpanel···········.
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EPSON9–27SED1278SED12781line80characters5*7pixels+cursor1/8dutycycleSystemset:N=0,F=0COM1COM7COM8SEG1SEG40DOXSCLLPFRSEG0SEG63DO1DO1D0D1XSCLSED1181FLALPFR(6)DO0SEG0SEG39D0D1XSCLSED1181FLALPFRDO0Open18980No.
ofcharactersLCDpanel.
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(1)2line8characters5*7pixels+cursor1/16dutycycleSystemset:N=1,F=don'tcareSED1278COM1COM7COM9COM8COM16COM15SEG1SEG4018No.
ofcharactersLCDpanel2ndline1stline············.
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9–28EPSONSED12782line20characters5*7pixels+cursor1/16dutycycleSystemset:N=1,F=don'tcareCOM1COM7COM8COM9COM16COM15SEG1SEG40DOXSCLLPFRSED127818920SEG0SEG63SEG59SEG60DO1OpenD0D1SED1181FLADO0NCFRLPXSCLNo.
ofcharactersLCDpanel2ndline1stline············.
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EPSON9–29SED1278SED12782line40characters5*7pixels+cursor16dutycycleSystemset:N=1,F=don'tcareSED1278COM1COM7COM8COM9COM16COM15SEG1SEG40DOXSCLLPFRSEG0SEG63SEG32toSEG63DO1DO1D0D1XSCLSED1181FLALPFR(1)(3)DO0SEG0SEG31D0D1XSCLSED1181FLALPFRDO0NCOpen18940No.
ofcharactersLCDpanel2ndline1stline·····················.
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9–30EPSONSED1278MPUINTERFACETheSED1278hasselectable8-or4-bitMPUinterface.
Anexampleofatypical8-bitMPUinterfaceisshownfigure8.
Z80SED1278G1ABCG2AG2BY0A0A4A5A6A7IORQRDWRDB0toDB7D0toD7R/WERSFigure8InterfacingtheSED1278totheZilogZ80EPSON9–31SED1278SED1278COMPARISONWITHHD44780BYHITACHIItemHD44780(Hitachi)SED1278DatadisplayRAM80bytes←CharactergeneratorROM192types240typesCharacterfont5*7:160types5*10:32types5*10:240typesCharactergeneratorRAM64bytes←LCDdriveoutput16commondriveroutputs←40segmentdriveoutputsCharacterfont(withcursor)5*8dots(1/8and1/16duty)←5*11dots(1/1duty)Conversiontoduty1/8,1/11,1/16←LCDdrivevoltage(VDD–V5)Max.
13.
5VMax.
1VDDMin.
4.
6VMin.
3VLCDdrivewaveformWaveformAWaveformD(SingleframeACdrive)(DualframeACdrive)Epulsewidth450nsec220nsecTimingtochangetheaddressThecontentsofaddresscounterareThecontentsofaddresscountersubsequenttoCGRAMdetermined1.
5clockafterreleaseofcounteraredeterminedandDDRAMdatawritingandbusystateimmediatelyafterreleasereading(6microsecondsatfOSC=250kHz).
ofbusystate.
No.
ofinstructions11←ResetterminalNotprovided←ChipselectorterminalNotprovided←Power-onresetterminalProvided←ExtensionsegmentdriverHitachiHD44100:40outputs←SED1181FLA:64outputsPackage80-pinplasticflatpackage←PinlayoutPincompatible9–32EPSONSED1278APPENDIXA:CHARACTERCODESANDFONTSSED1278F0A/SED1278D0AHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEFEPSON9–33SED1278SED1278SED1278F0B/SED1278D0BHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEF9–34EPSONSED1278SED1278F0C/SED1278D0CHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEFEPSON9–35SED1278SED1278SED1278F0E/SED1278D0EHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEF9–36EPSONSED1278SED1278F0G/SED1278D0GHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEFEPSON9–37SED1278SED1278SED1278F0H/SED1278D0HHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEF9–38EPSONSED1278APPENDIXB:PINCONSTRUCTIONInputPinType1EOSC1VDDVSSInputPinType2RSR/WVDDPinVSSEPSON9–39SED1278SED1278OutputPinOSC2XSCL,LP,FR,DOVDDVSSI/OPinDB0toDB7VDDPinVSS
–5*10pixelfont,4characters.
NumberofcharactersusedPowerfuldisplaycontrolinstructionsLCDdriveroutputs–40segmentdriveroutputs–16commondriveroutputsLowLCDdrivevoltage–3Vminimum(VDD–V5)Dual-frameACdriveOn-chippower-onresetOn-chipRCoscillatorSingle5VoperationChip(SED1278D)and80-pinQFP(SED1278F)packages(CompatiblewithHD44780andHD66780byHitachiLimited)TheSED1278isequivalenttotheHD44780andHD66780byHitachiLimited.
Beforeuse,makesurethatthereisnoproblemforpracticaluse.
Itshouldbenotedthatthisisnotintendedtoguaranteeenforcementofindustrialpropertyandotherrights,ortograntlicensefortheuseofthisproduct.
OVERVIEWTheSED1278isadedicatedcharacterdisplaycontroller/driverwhich,whenusedwiththeSED1181FortheSED1681segmentdrivres,isabletodisplayupto80charactersunder4-or8-bitMPUcontrol.
Theinternalcharactergenerator(CG)ROMhasanextended240,5*10pixel,characterset,plusCGRAMspaceforanadditionaleightuserdefinable5*8pixelcharacters.
Thesememoryfeaturescombinedwiththerichsetofcontrolinstructionsofferthepotentialforahighlyflexiblecharacterdisplaysystem.
TheSED1278featuresaguaranteedminimumLCDdrivevoltageof3VmakingitsuitableforusewithlowvoltageLCDpanels.
DutySED1278FSED1181FLANo.
ofcharactersusedOne-line1/8,108columnsdisplay1/11*1line680columns*1lineTwo-line1/16108columnsdisplay*2lines340columns*2lines9–2EPSONSED1278BLOCKDIAGRAMDB0toDB7ER/WRSVSSVDCV1V2V3V4V5COM1toCOM16SEG1toSEG40XSCLLPFRDOOSC1OSC2855577I/OBufferI/OControlInstructionDecoderCursor/PrinterControlInstructionRegisterDaiaRegisterMPXMPXMPXCharacterGeneratorRAM(CGRAM)64BitsCharacterGeneratorRAM(CGROM)5x10x240BitsDisplayDataRAMDDRAM80BytesParallel/SerialDataConverterAddressCounterACCRefreshAddressCounterTimingGeneratorShiftRegister16BitsCommonDrivingOutputCircuitSegmentDrivingOutputCircuitLatchCircuit40BitsShiftRegister40BitsOscillationCircuitPACKAGEOUTLINE654080254164241EPSON9–3SED1278SED127825SED1278D2414164408065PINOUTPinNumberName1SEG222SEG213SEG204SEG195SEG186SEG177SEG168SEG159SEG1410SEG1311SEG1212SEG1113SEG1014SEG915SEG816SEG717SEG618SEG519SEG420SEG3PinNumberName21SEG222SEG123GND24OSC125OSC226V127V228V329V430V531LP32XSCL33VDD34FR35DO36RS37R/W38E39DB040DB1PinNumberName41DB242DB343DB444DB545DB646DB747COM148COM249COM350COM451COM552COM653COM754COM855COM956COM1057COM1158COM1259COM1360COM14PinNumberName61COM1562COM1663SEG4064SEG3965SEG3866SEG3767SEG3668SEG3569SEG3470SEG3371SEG3272SEG3173SEG3074SEG2975SEG2876SEG2777SEG2678SEG2579SEG2480SEG239–4EPSONSED1278PINDESCRIPTIONMPUInterfaceRSRegisterselectsignalinput.
SelectsbetweenthedataandinstructionregistersduringCPUaccess.
RS=0:InstructionregisteraccesscycleRS=1:DataregisteraccesscycleR/WThisinputselectsbetweenSED1278registerreadandwritecycles.
R/W=0:RegisterwritecycleR/W=1:RegisterreadcycleERead/writeexecutesignalinput.
LCDPanelInterfaceCOM1toCOM16CommondriveroutputstotheLCDpanel.
SEG1toSEG40SegmentdriveroutputstotheLCDpanel.
OSC1IftheinternalRCoscillatorisusedtogeneratetheLCDdrivesignals,thefeedbackresistor,Rf,isconnectedtothispin.
Ifanexternalclocksourceisused,theclockisconnectedtothispin.
OSC2IftheinternalRCoscillatorisusedtogeneratetheLCDdrivesignals,thefeedbackresistor,Rf,isconnectedtothispin.
Ifanexternalclocksourceisused,thispinisleftopen.
DB0toDB7TTLleveldatainput/outputlines,forconnectiontothesystemMPUdatabus.
TABLE1TheFunctionoftheESignalRS0011R/W0101E11InstructionwritecycleDDRAMorCGRAMdatawritecycleDDRAMorCGRAMdatareadcycleBusyflagreadcycleAddresscounterreadcycleOperationExternalSegmentDriverInterfaceLPDatalatchpulseoutputforanexternalX-driver.
XSCLDatashiftclockoutputforanexternalX-driver.
FRLCDAC-drivewaveformforanexternalX-driver.
DODisplaydataoutputforanexternalX-driver.
EPSON9–5SED1278SED1278TERMINALCONFIGURATION1.
Inputterminalconfiguration(1)VDDInternalApplicableterminal·E·OSCIVSS2.
Inputterminalconfiguration(2)Withpull-upMOSresistorVDDApplicableterminal·RS,R/WVSSInternal3.
OutputterminalconfigurationVDDApplicableterminal·OSC2·XSCL,LP,FR,DOVSSInternal9–6EPSONSED12784.
Input/OutputterminalconfigurationVDDApplicableterminal·DBOtoDB7InternalVSSINSTRUCTIONDESCRIPTIONInstructionSummary*Don'tcareInstructionCodeDescriptionCycleTimeRSR/WDB7DB6DB5DB4DB3DB2DB1DB0(max.
)ClearDisplay0000000001ClearsalldisplaydataandsetsDDRAM410clocksaddress0intheaddresscounter.
SetDDRAMaddress0intheaddressReturnHome000000001*counter.
Alsoreturnsanyshifteddatato410clockshome.
ThecontentsofDDRAMremainunchanged.
SpecifiesthedirectioninwhichthecursorEntryModeSet00000001I/DSmovesandwhetherthedisplayistobe10clocksshiftedornot,whendataiswritentoorreadfrommemorySetsalldisplayon/off(D)cursoron/off(C),DisplayON/OFF0000001DCBandcharacterblinkinginthecursorposition10clocks(B).
Cursoror000001S/CR/L**Movesthecursorandshiftsthedisplay10clocksDisplayShiftwithoutchangingthecontentsofDDRAM.
Setstheinterfacedatalength(IF),numberofSystemSet00001IFNF**characterstobedisplayed(N),andcharacter10clocksfont(F).
SetCGRAM0001ACGSetCGRAMaddresses,followedby10clocksAddresstransferofCGRAMdata.
SetDDRAM001ADDSetsDDRAMaddress,followedby10clocksAddresstransferofDDRAMdata.
ReadBusyFlagReadsthebusyflag(BF)whichindicatesandAddress01BFACCinternaloperationandthecontentsofthe0addresscounter.
WriteDatato10WriteDataWritesdatatoDDRAMorCGRAM.
10clocksCGorDDRAMReadDatafrom11ReadDataReadsdatafromDDRAMorCGRAM.
10clocksCGorDDRAMEPSON9–7SED1278SED1278WriteOnlyInstructionsClearDisplayDB7DB6DB5DB4DB3DB2DB1DB00000000101HRS=0Thisinstruction1.
loadsalllocationsinthedisplaydata(DD)RAMwith20H.
2.
clearsthecontentsoftheaddresscounterto0H.
3.
setsthedisplayforzerocharactershift.
4.
setstheaddresscountertopointtotheDDRAM.
5.
,ifthecursorisdisplayed,movesthecursortotheleftmostcharacterinthedisplayor,ifatwolinedisplayisused,movesthecursortotheleftmostcharacterinthetopline(line1).
6.
setstheaddresscountertoincrementoneachaccessofDDRAMorCGRAM.
CursorHomeDB7DB6DB5DB4DB3DB2DB1DB00000001*02H,03HRS=0Thisinstruction1.
clearsthecontentsoftheaddresscounterto0H.
2.
setstheaddresscountertopointtotheDDRAM.
3.
setsthedisplayforzerocharactershift.
4.
,ifthecursorisdisplayed,movesthecursortotheleftmostcharacterinthedisplayor,ifatwolinedisplayisused,theleftmostcharacterinthetopline(line1).
EntryModeSetDB7DB6DB5DB4DB3DB2DB1DB0000001I/DS04Hto07HRS=0TheI/DbitselectsthewayinwhichthecontentsoftheaddresscounteraremodifiedaftereveryaccesstoDDRAMorCGRAM.
I/D=1:Theaddresscounterisincremented.
I/D=0:Theaddresscounterisdecremented.
TheSbitenablesdisplayshift,insteadofcursorshift,aftereachwriteorreadtotheDDRAM.
S=1:Displayshiftenabled.
S=0:Cursorshiftenabled.
Thedirectioninwhichthedisplayisshiftedisoppositeinsensetothatofthecursor.
ForexampleifS=0andI/D=1thecursorwouldshiftonecharactertotherightafteranMPUwritetoDDRAM.
HoweverifS=1andI/D=1,thedisplaywouldshiftonecharactertotheleftandthecursorwouldmaintainitspositiononthepanel.
ThecursorwillalreadybeshiftedinthedirectionselectedbyI/DduringreadsoftheDDRAM,irrespectiveofthevalueofS.
SimilarlyreadingandwritingtheCGRAMalwaysshiftsthecursor.
Notethatifatwolinedisplayisusedbothlineswillbeshiftedsimultaneously.
DisplayON/OFFDB7DB6DB5DB4DB3DB2DB1DB000001DCB08Hto0FHRS=0Thisinstructioncontrolsvariousfeaturesofthedisplay.
TheDbitturnstheentiredisplayonoroff.
D=1:DisplayonD=0:DisplayoffTheCbitturnsthecursoronoroff.
C=1:CursoronC=0:CursoroffTheBbitenablesblinkingofthecharacterthecursorcoincideswith.
B=1:BlinkingonB=0:BlinkingoffBlinkingisachievedbyalternatingbetweenanormalandalldarkdisplayofacharacter.
Theblinkingperiodissetat204800fOSC.
ForexampleiffOSC=250kHzthecursorwillblinkwithaperiodof0.
8192seconds,orabout1.
2Hz.
Cursor/DisplayShiftDB7DB6DB5DB4DB3DB2DB1DB00001S/CR/L**10Hto1FHRS=0Thisinstructionshiftsthedisplayand/ormovesthecursor,oncharactertotheleftorright,regardlessofaDDRAMready/write.
TheS/Cbitselectsmovementofthecursorormovementofboththecursorandthedisplay.
S/C=1:ShiftbothcursoranddisplayS/C=0:ShiftcursoronlyTheR/Lbitselectsleftwardorrightwardmovementofthedisplayand/orcursor.
R/L=1:ShiftonecharacterrightR/L=0:ShiftonecharacterleftSystemSetDB7DB6DB5DB4DB3DB2DB1DB0001IFNF**20Hto3FHRS=0Thisinstructioninitializesthesystem,andmustbethefirstinstructionexecutedafterpower-on.
TheIFbitselectsbetweenan8-bitora4-bitMPUinterface.
IF=1:8-bitMPUinterfaceusingDB7toDB0.
IF=0:4-bitMPUinterfaceusingDB7toDB4.
TheNandFbitsselectthenumberofdisplaylinesandthecorrespondingdutycycle,aslistedintable2.
9–8EPSONSED1278SetCGRAMAddressDB7DB6DB5DB4DB3DB2DB1DB001ACR40Hto7FHRS=0Thisinstruction1.
loadsanew6-bitaddressintotheaddresscounter.
2.
setstheaddresscountertoaddressCGRAM.
Once"SetCGRAMAddress"hasbeenexecuted,thecontentsoftheaddresscounterwillbeautomaticallymodifiedaftereveryaccessofCGRAM,asdeterminedbythe"EntryModeSet"instruction.
Ifthe"SetCGRAMAddress"instructionisissuedbythesystemMPUwhilethedisplayisenabled,andifeitherthecursorisonorblinkison,pseudo-cursororpseudo-blinkappears.
Topreventthis,turnboththecursoranddisplayblinkoffbeforeloadinganewCGRAMaddress.
Theactivewidthoftheaddresscounter,whenitisaddressingCGRAM,is6-bitssothecounterwillwraparoundto00Hfrom3FHifmorethan64bytesofdataarewrittentoCGRAM.
SetDDRAMAddressDB7DB6DB5DB4DB3DB2DB1DB01ADDRS=080HtoCFH…1line80HtoA7Hline1…2lineC0HtoE7Hline2…2lineThisinstruction1.
loadsanew7-bitaddressintotheaddresscounter.
2.
setstheaddresscountertopointtotheDDRAM.
Oncethe"SetDDRAMAddress"instructionhasbeenexecuted,thecontentsoftheaddresscounterwillbeautomaticallymodifiedaftereachaccessofDDRAM,asselectedbythe"EntryModeSet"instruction.
TheSED1278hasonly80DDRAMlocations.
Thevalidaddressspacesforvariousdisplayconfigurationsarelistedintable3.
TABLE3ValidCGRAMAddressRangesWriteDataDB7DB6DB5DB4DB3DB2DB1DB0DATARS=1ThisinstructionwritesthedatainDB7toDB0intoeithertheCGRAMortheDDRAM.
TheRAMspace(CGorDD),andtheaddressinthatspace,thatisaccesseddependsonwhethera"SetCGRAMAddress"ora"SetDDRAMAddress"instructionwaslastexecuted,andontheparametersofthatinstruction.
Thecontentsoftheaddresscounterwillbeautomaticallymodifiedaftereach"WriteData",asdeterminedby"EntryModeSet".
WhendataiswrittentotheCGRAM,theDB7,DB6andDB5bitsarenotdisplayeddirectlyascharacters.
TABLE2CombinationsofDisplayLinesandDutyCycleNFNumberofDutyCommonOutputNon-SelectedCommonLineRatioSignalOutputSignal001line1/8COM1toCOM8COM9toCOM16011line1/11COM1toCOM11COM12toCOM161*2lines1/16COM1toCOM16—NumberofLinesCharactersADR1-line8000Hto4FH2-line1stline4000Hto27H2ndline4040Hto67HEPSON9–9SED1278SED1278ReadOnlyInstructionsReadBusyFlag/AddressCounterDB7DB6DB5DB4DB3DB2DB1DB0BFACCRS=1Readingtheinstructionregisteryieldsthecurrentvalueoftheaddresscounterandthebusyflag.
Thisinstructionmustbeexecutedpriortoanyotherinstructions.
ACC,theaddresscountervalue,willpointtoalocationineitherCGRAMorDDRAM,dependingonthetypeof"SetRAMAddress"instructionlastsent.
In"BusyFlagCheck"immediatelyafterexecuting"RAMAddressSet"instruction,avalidaddresscountervaluecanberead5clockcyclesafterthebusyflag(BF)goeslow.
In"BusyFlagCheck"immediatelyafterexecuting"WriteData"instruction,avalidaddresscountervaluecanbereadyassoonasBFgoeslow.
TheBFbitshowsthestatusofthebusyflag.
BF=1:SED1278busy.
BF=0:SED1278readyfornextinstruction.
ReadDataDB7DB6DB5DB4DB3DB2DB1DB0DATARS=1ThisinstructionreadsdatafromeitherCGRAMorDDRAM,dependingonthetypeof"SetRAMAddress"instructionslastsent.
Theaddressinthatspacedependsonthe"SetRAMAddress"instructionsparameters.
Immediatelybeforeexecuting"ReadData","SetCGRAMAddress"or"SetDDRAMAddress"mustbeexecuted.
Thecontentsoftheaddresscounteraremodifiedaftereach"ReadData",asdeterminedby"EntryModeSet".
Displayshiftisnotexecuted,independentlyof"EntryModeSet".
9–10EPSONSED1278SPECIFICATIONSAbsoluteMaximumRatingsNotes:1.
VDD>V1>V2>V3>V4>V5>VSS2.
Aflatpackageproductcanbecomelessresistanttomoistureifexposedtoextremetemperatures.
Whenmountingthispackageonaprintedcircuitboard,useasolderingtechniquewhichavoidsexcessivethermalloadingofthepackageresin.
3.
AllvoltagesassumeVSS=0V.
DCCharacteristics(VDD=5.
0V±10%,VSS=0V,Ta=–20to+75°C)ParameterSymbolConditionRatingUnitApplicablePinsmintypmax"H"levelinputvoltage(1)(TTL)VIH12.
0—VDDVDB0toDB7,RS,"L"levelinputvoltage(1)(TTL)VIL1VSS—0.
8VR/W,E"H"levelinputvoltage(2)(CMOS)VIH2VDD–1.
0—VDDVOSC1"L"levelinputvoltage(2)(CMOS)VIL2VSS—1.
0V"H"leveloutputvoltage(1)(TTL)VOH1–IOH=0.
205mA2.
4——VDB0toDB7"L"leveloutputvoltage(1)(TTL)VOL1IOL=1.
6mA——0.
4V"H"leveloutputvoltage(2)VOH2–IOH=0.
04mA0.
9VDD——V(CMOS)XSCL,LP,DO"L"leveloutputvoltage(2)VOL2IOL=0.
04mA——0.
1VDDV(CMOS)Driver-onresistor(COM)RCOM|VCOM–Vn|=0.
5V—210kCOM1toCOM16Driver-onresistor(SEG)RSEG|VSEG–Vn|=0.
5V—2.
510kSEG1toSEG40I/OleakagecurrentIILVIN=0toVDD——1APull-upMOScurrent–IPVDD=5V50125250ADB0toCB7,RS,R/WRfoscillation,fromSupplycurrentIOPexternalclock—0.
50.
8mAVDDVDD=5V,fOSC=fCP=270kHzParameterSymbolRatingUnitSupplyvoltage(1)VDD–3to+7.
0VSupplyvoltage(2)*V1toV5–0.
3toVDD+0.
3VInputvoltageVIN–0.
3toVDD+0.
3VOperatingtemperatureTopr–20to+75°CStoragetemperatureTstg–65to+150°CSolderingtemperature*time**Tsol260,10°C,sPowerdissipationPD300mWEPSON9–11SED1278SED1278ACCharacteristicsMPUwritecycletiming(writetoSED1278)R/WtAStWEHtAHtAHVIL1VIL1VIH1VIH1tcycEVIL1tDStDHtrEtFEVIL1VIH1RSEDB0toDB7ValidDataMPUreadcycletiming(readfromSED1278)R/WRSVIH1VIH1tWEHVIH1VOH1tcycEVOL1trEtRDtDHRVIL1tfEtAHtAHtASVIL1EDB0toDB7ValidData(VDD=5.
0V±10%,VSS=0V,Ta=–20to70°C)ParameterSymbolConditionRatingUnitminmaxEnablecycletimetcycE500—nsEnable"H"levelpulsewidthtWEH220—nsEnablerise/falltimetrE,tfE—25nsRS,R/WsetuptimetAS40—nsRS,R/WaddressholdtimetAH10—nsDatasetuptimetDS60—nsWritedataholdtimetDH10—ns9–12EPSONSED1278ExternalsegmentdriversignaltimingLP0.
9VDD0.
1VDD0.
1VDD0.
9VDD0.
1VDD0.
9VDD0.
9VDD0.
9VDD0.
1VDD0.
9VDD0.
1VDDtWCLHtWCLHtWCLLtDSLPtDHXtOSXtDFRtDSLP0.
1VDDXSCLDOFR(VDD=5.
0V±10%,VSS=0V,Ta=–20to75°C)ParameterSymbolConditionRatingUnitminmaxEnablecycletimetcycE500—nsEnable"H"levelpulsewidthtWEH220—nsEnablerise/falltimetrE,tfE—25nsRS,R/WsetuptimetAS40—nsRS,R/WaddressholdtimetAH10—nsReaddatasetuptimetRDCL=100pF—120nsReaddataholdtimetDHR20—ns(VDD=5.
0V±10%,VSS=0V,Ta=–20to70°C)ParameterSymbolConditionRatingUnitminmaxClockpulsewidth:HighleveltWCLH0.
8/2fOSC—nsClockpulsewidth:LowleveltWCLL0.
8/2fOSC—nsLatchpulsesetuptimetDSLP0.
7/2fOSC—nsDatasetuptimetOSX0.
7/2fOSC—nsDataholdtimetDHX0.
7/2fOSC—nsFRdelaytDFR–10001000nsEPSON9–13SED1278SED1278Power-onresettiming0.
1ms≤tr≤10ms(Ta=–20to75deg.
C)toff≥1mstrtoff0.
2V4.
5VLCDDriveVoltagesMechanicalSpecificationsSED1278FPackageDimensions65804025640.
992±0.
016(25.
2±0.
4)0.
787±0.
004(20.
0±0.
1)0.
756±0.
016(19.
2±0.
4)0.
551±0.
004(14.
0±0.
1)0.
031±0.
006(0.
8±0.
15)0.
006±0.
002(0.
15±0.
05)0.
079±0.
004(2.
0±0.
1)0.
102(2.
6)0.
014±0.
004(0.
35±0.
1)0to12°0.
047±0.
012(1.
2±0.
3)411Index24PinDuty1/8or1/11Duty1/16V13/4(VDD–V5)4/5(VDD–V5)V22/4(VDD–V5)3/5(VDD–V5)V32/4(VDD–V5)2/5(VDD–V5)V41/4(VDD–V5)1/5(VDD–V5)V5V5V59–14EPSONSED1278SED1278DPackageDimensionsChipsize:4.
50mm*3.
67mmChipthickness:400mPadsize:109m*109mPadpitch:182m25YX2414164408065EPSON9–15SED1278SED1278PadX(m)Y(m)NumberName41DB2–2087–167142DB3–1905–167143DB4–1723–167144DB5–1541–167145DB6–1359–167146DB7–1177–167147COM1–995–167148COM2–814–167149COM3–633–167150COM4–452–167151COM5–272–167152COM6–91–167153COM791–167154COM8272–167155COM9452–167156COM10633–167157COM11814–167158COM12995–167159COM131177–167160COM141359–167161COM151541–167162COM161723–167163SEG401905–167164SEG392087–167165SEG382087–136566SEG372087–118367SEG362087–100168SEG352087–81969SEG342087–63770SEG332087–45571SEG322087–27372SEG312087–9173SEG3020879174SEG29208727375SEG28208745576SEG27208763777SEG26208781978SEG252087100179SEG242087118380SEG2320871365PadX(m)Y(m)NumberName1SEG22208716712SEG21190516713SEG20172316714SEG19154116715SEG18135916716SEG17117716717SEG1699516718SEG1581416719SEG14633167110SEG13452167111SEG12272167112SEG1191167113SEG10–91167114SEG9–272167115SEG8–452167116SEG7–633167117SEG6–814167118SEG5–995167119SEG4–1177167120SEG3–1359167121SEG2–1541167122SEG1–1723167123GND–1905167124OSC1–2087167125OSC2–2087136526V1–2087118327V2–2087100128V3–208781929V4–208763730V5–208745531LP–208727332XSCL–20879133VDD–2087–9134FR–2087–27335DO–2087–45536RS–2087–63737R/W–2087–81938E–2087–100139DB0–2087–118340DB1–2087–13659–16EPSONSED1278OPERATIONTheBusyFlagTheSED1278takesbetween10and410clockcyclestoexecuteinstructions.
Duringthatperiodadditionalinstructionsshouldnotbeissued.
Thedeviceisprovidedwithabusyflagtolettheuserchecktheinternalstateofthechip.
BFshouldbe0beforeanotherinstructionisissued.
Ifthebusyflagisnotcheckedbetweeninstructionstheusermustarrangeforaguaranteeddelayofmorethantheinstructionexecutiontime,beforeissuingthenextinstruction.
4-BitMPUInterfaceIfa"SystemSet"instructionisissuedwithbit4setto0,thentheSED1278willoperatewitha4-bitMPUdatabusinterface.
Ifa4-bitinterfaceisused,the8-bitinstructionsarewrittennibblebynibble;thehigh-ordernibblebeingwrittenfirst,followedbythelow-ordernibble.
Itisnotnecessarytocheckthebusyflagbetweenwritingseparatenibblesofindividualinstructions.
ReadingtheBusyFlag/AddressCounteryieldsthehigh-ordernibblefirst,followedbythelow-ordernibble.
SystemInitializationPower-onresetAlthoughtheSED1278hasnoexternalresetinput,itwillautomaticallyresetonsystempower-on.
ThesequencestartsonceVDDcommendedthatasoftwareinitializationsequenceisfollowed.
SoftwareInitialization(8-bitMPUbus,fOSC=250kHz)[1]000011**************DB7RSR/WEDB030msormore4.
1msormore100sormore40sormoreSystemsetSystemset[2][3][4][5][7]000011DB7RSR/WEDB0000011DB7RSR/WEDB0Systemset[6]000011NFDB7RSR/WEDB0BF=0BF011DB7RSR/WEDB0BusyflagBF=0BF=1BF=1BF011DB7RSR/WEDB0BusyflagPower-onSystemsetACCACC9–18EPSONSED12780000001000DB7·RSR/WEDB0DisplayClear[8][10][11][9][13]0000000001DB7RSR/WEDB0EntryModeset[12]00000001I/DSDB7RSR/WEDB0Initializeend[14]BF=0BF011DB7RSR/WEDB0BusyflagBF=0BF=1BF=1BF=0BusyflagDisplayoffBF=1BF011DB7RSR/WEDB0BusyflagDisplayon/offACCBF00DB7RSR/WEDB0ACCACCEPSON9–19SED1278SED1278SoftwareInitialization(4-bitMPUbus,fOSC=250kHz)[1]000011DB7RSR/WE··DB430msormore4.
1msormore100sormore40sormoreSystemsetSystemset[2][3][4][6][8]000011DB7RSR/WE··DB4000011DB7RSR/WE··DB4Systemset[7]NF**0010DB7··DB440sormoreSystemset[5]000010DB7RSR/WE··DB4BF=0(High-order)(Low-order)(High-order)(Low-order)(High-order)(Low-order)BF011DB7RSR/WE··DB4BusyflagBF=0BF=1BF=1BusyflagPower-onSystemsetACC01100RSR/WE00ACCBF011DB7RSR/WE··DB4ACC011ACC9–20EPSONSED1278[9][10][12]Displayclear[11]00010000DB7··DB4BF=0(High-order)(Low-order)(High-order)(Low-order)(High-order)(Low-order)BF011DB7RSR/WE··DB4BusyflagBF=0BF=1BF=1BusyflagDisplayon/offACC01100RSR/WE0010000000DB7··DB4(High-order)(Low-order)00RSR/WE00ACCBF011DB7RSR/WE··DB4ACC011ACC[14]EntryModeset[13]Initializeend[15]01I/DS0000DB7··DB4(High-order)(Low-order)(High-order)(Low-order)BF=0BF=1Busyflag00RSR/WE00BF011DB7RSR/WE··DB4ACC011ACCEPSON9–21SED1278SED1278THECHARACTERGENERATORCharacterGeneratorROM(CGROM)TheSED1278containsa240character,maskedCGROM.
Eachcharacteris5*10pixels,for1/11dutycyclecompatibility.
RefertoAppendixAforavailablecodesandtheircorrespondingfonts.
BecausetheCGROMismasked,customersmayarrangetohavetheirownCGROMmasksmade.
Acustommaskallowstheusertohavetheirowncharacterset.
acharactersetofupto256characters.
PleasecontacttheSEIKOEPSONMarketingDepartmentforfurtherinformation.
IfacustomCGROMisused,twothingsshouldbenoted.
1.
The"ClearDisplay"instructionreliesonthecharacterwhosecodeis20Hbeingablank.
2.
Ifmorethan240ROMedcharactersarespecified,thenthenumberofCGRAMcharactersavailableiscorrespondinglyreduced.
ThephysicalRAMspaceisstillavailable,andisavailableforuseasmemory,howeveritwillnolongerhaveanassociatedcharactercode.
3.
ThecharacterROMimplementedinaparticularchipisindicatedbyatwocharactersuffixattachedtothedevicenumber,forexampleSED1278F0A.
CharacterGeneratorRAM(CGRAM)TheSED1278has64bytesofCGRAM,allowingtheusertoprogramupto8characters.
5*8pixelfont(1/8or1/16dutycycle)Themaximumcharacterheightis8pixels,howeverifacursorisusedrow7shouldbeallzeros.
8suchcharactersareavailabletotheuser.
TheCGRAMaddressismadeupofthefollowingcomponents.
Theleastsignificantthreebits,a2toa0,specifytherownumberofthecharacterdata.
Bitsa5toa3aremadeupoftheleastsignificantthreebitsofthecharactercode.
Themostsignificantbit,a7,isignored.
Figure1showsanexample5*8pixelfont.
Figure1A5*8PixelFontCGRAMaddressCGRAMdata(Characterpattern)A5····A0DB7DB0000000***00001000001***00001000010***01001000011***11111000100***01000000101***00000000110***00000000111***000009–22EPSONSED12785*11pixelfont(1/11dutycycle)Themaximumcharacterheightis11pixels,howeverifacursorisusedrow10mustbeleftblank.
TheSED1278requiresthat,althoughthemaximumcharacterheightis11rows,eachcharacterisallocated16rows(bytes)ofaddressspace.
Thelastfivebytesareignored.
TheCGRAMaddressismadeupofthefollowingcomponents.
Figure2A5*11PixelFontTheleastsignificant4bits,a3toa0,specifytherownumberofthecharacterdata.
Bitsa5anda4correspondtobits2and3,respectively,ofthecharactercode.
Themostsignificantbit,a7,isignored.
Figure2showsanexample5*11pixelfont.
CGRAMaddressCGRAMdataA5····A0DB7DB0000000***00001000001***00001000010***00001000011***00101000100***01001000101***11111000110***01000000111***00100001000***00000001001***00000001010***00000001011001100001101001110001111EPSON9–23SED1278SED1278LCDINTERFACELCDDriveVoltagesTheSED1278generatessegmentandcommondrivesignalsusingthevoltagessuppliedtopinsV1,V2,V3,V4andV5.
Thevoltagelevelsatthesepinsdependonthedutycycleofthedisplay.
Thespecificationsofthesevoltages.
Thesimplestwayofproducingthesevoltagesistousearesistivedividingnetwork.
Figures3and4showexamplesofnetworksfor1/8,or1/11,and1/16dutycyclesrespectively.
SED1278RRRRCCCCCOVRVDDV1V2V3V4V5VSSFigure3LCDDriveVoltageNetwork–1/8or1/11DutyCycleSED1278RRRRRCCCCCCOVRVDDV1V2V3V4V5VSSFigure4LCDDriveVoltageNetwork–1/16DutyCycleNotes:1.
V5issetusingapotentiometerand(VDD–VSS).
2.
ThepowersupplytotheSED1278shouldbebypassedwithacapacitor,CO,ofatleast0.
1Fplacedasclosetothechipaspossible.
9–24EPSONSED1278LCDDriveSignalWaveformsThesegmentandcommondrivewaveformsgeneratedbytheSED1278,forvariousdutycycleratios,areshowninfigures5,6and7.
FRtFRtFRVDDVSSVDDV1V4V5VDDV1V4V5VDDV1V4V5VDDV2,V3V5.
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COM1COM2COM8SEG1······Figure51/8DutyCycleDriveWaveformsFRtFRtFRVDDVSSVDDV1V4V5VDDV1V4V5VDDV1V4V5VDDV5,V3V5COM1COM2COM11SEG1.
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······Figure61/11DutyCycleDriveWaveformsEPSON9–25SED1278SED1278FRtFRtFRVDDVSSVDDV1V4V5VDDV1V4V5VDDV1V4V5VDDV5,V3V5COM1COM2COM16SEG1.
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······Figure71/16DutyCycleDriveWaveformsLCDInterfaceConfigurationsTheSED1278has16commonand40segmentdriveoutputs,enablingthechiptodriveupto16charactersbyitself.
Thedrivecapabilitycanbeexpandedto80characters,byusingSED1181FLAexternalsegmentdrivers.
1line8characters5*7pixels+cursor1/8dutycycleSystemset:N=0,F=0SED1278COM11No.
ofcharactersLCDpanel8COM7COM8SEG1SEG40············.
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9–26EPSONSED12781line8characters5*10pixels+cursor1/11dutycycleSystemset:N=0,F=1SED1278COM118COM10COM11SEG1SEG40No.
ofcharactersLCDpanel···············.
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1line20characters5*7pixels+cursor1/8dutycycleSystemset:N=0,F=0SED1278COM1SEG0SEG59SEG60toSEG63NCOpenDO1D0D1XSCLSED1181FLALPFRDO0COM7COM8SEG1SEG40DOXSCLLPFR18920No.
ofcharactersLCDpanel···········.
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EPSON9–27SED1278SED12781line80characters5*7pixels+cursor1/8dutycycleSystemset:N=0,F=0COM1COM7COM8SEG1SEG40DOXSCLLPFRSEG0SEG63DO1DO1D0D1XSCLSED1181FLALPFR(6)DO0SEG0SEG39D0D1XSCLSED1181FLALPFRDO0Open18980No.
ofcharactersLCDpanel.
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(1)2line8characters5*7pixels+cursor1/16dutycycleSystemset:N=1,F=don'tcareSED1278COM1COM7COM9COM8COM16COM15SEG1SEG4018No.
ofcharactersLCDpanel2ndline1stline············.
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9–28EPSONSED12782line20characters5*7pixels+cursor1/16dutycycleSystemset:N=1,F=don'tcareCOM1COM7COM8COM9COM16COM15SEG1SEG40DOXSCLLPFRSED127818920SEG0SEG63SEG59SEG60DO1OpenD0D1SED1181FLADO0NCFRLPXSCLNo.
ofcharactersLCDpanel2ndline1stline············.
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EPSON9–29SED1278SED12782line40characters5*7pixels+cursor16dutycycleSystemset:N=1,F=don'tcareSED1278COM1COM7COM8COM9COM16COM15SEG1SEG40DOXSCLLPFRSEG0SEG63SEG32toSEG63DO1DO1D0D1XSCLSED1181FLALPFR(1)(3)DO0SEG0SEG31D0D1XSCLSED1181FLALPFRDO0NCOpen18940No.
ofcharactersLCDpanel2ndline1stline·····················.
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9–30EPSONSED1278MPUINTERFACETheSED1278hasselectable8-or4-bitMPUinterface.
Anexampleofatypical8-bitMPUinterfaceisshownfigure8.
Z80SED1278G1ABCG2AG2BY0A0A4A5A6A7IORQRDWRDB0toDB7D0toD7R/WERSFigure8InterfacingtheSED1278totheZilogZ80EPSON9–31SED1278SED1278COMPARISONWITHHD44780BYHITACHIItemHD44780(Hitachi)SED1278DatadisplayRAM80bytes←CharactergeneratorROM192types240typesCharacterfont5*7:160types5*10:32types5*10:240typesCharactergeneratorRAM64bytes←LCDdriveoutput16commondriveroutputs←40segmentdriveoutputsCharacterfont(withcursor)5*8dots(1/8and1/16duty)←5*11dots(1/1duty)Conversiontoduty1/8,1/11,1/16←LCDdrivevoltage(VDD–V5)Max.
13.
5VMax.
1VDDMin.
4.
6VMin.
3VLCDdrivewaveformWaveformAWaveformD(SingleframeACdrive)(DualframeACdrive)Epulsewidth450nsec220nsecTimingtochangetheaddressThecontentsofaddresscounterareThecontentsofaddresscountersubsequenttoCGRAMdetermined1.
5clockafterreleaseofcounteraredeterminedandDDRAMdatawritingandbusystateimmediatelyafterreleasereading(6microsecondsatfOSC=250kHz).
ofbusystate.
No.
ofinstructions11←ResetterminalNotprovided←ChipselectorterminalNotprovided←Power-onresetterminalProvided←ExtensionsegmentdriverHitachiHD44100:40outputs←SED1181FLA:64outputsPackage80-pinplasticflatpackage←PinlayoutPincompatible9–32EPSONSED1278APPENDIXA:CHARACTERCODESANDFONTSSED1278F0A/SED1278D0AHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEFEPSON9–33SED1278SED1278SED1278F0B/SED1278D0BHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEF9–34EPSONSED1278SED1278F0C/SED1278D0CHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEFEPSON9–35SED1278SED1278SED1278F0E/SED1278D0EHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEF9–36EPSONSED1278SED1278F0G/SED1278D0GHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEFEPSON9–37SED1278SED1278SED1278F0H/SED1278D0HHigher4-bit(D4toD7)ofCharacterCode(Hexadecimal)Lower4-bit(D0toD3)ofCharacterCode(Hexadecimal)0CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)CGRAM(1)CGRAM(2)CGRAM(3)CGRAM(4)CGRAM(5)CGRAM(6)CGRAM(7)CGRAM(8)0123456789ABCDEF123456789ABCDEF9–38EPSONSED1278APPENDIXB:PINCONSTRUCTIONInputPinType1EOSC1VDDVSSInputPinType2RSR/WVDDPinVSSEPSON9–39SED1278SED1278OutputPinOSC2XSCL,LP,FR,DOVDDVSSI/OPinDB0toDB7VDDPinVSS
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