资源论坛采集器

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EnglishDataSheet:SBAS777ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018具具有有可可编编程程双双极极输输入入范范围围的的ADS869x18位位、、高高速速、、单单电电源源、、SARADC数数据据采采集集系系统统11特特性性1具有集成模拟前端的18位ADC高速:–ADS8691:1MSPS–ADS8695:500kSPS–ADS8699:100kSPS可通过软件编程的输入范围:–双极范围:±12.
288V、±10.
24V、±6.
144V、±5.
12V和±2.
56V–单极范围:0V–12.
288V、0V–10.
24V、0V–6.
144V以及0V–5.
12V5V模拟电源:1.
65V到5VI/O电源恒定的阻性输入阻抗≥1MΩ输入过压保护:高达±20V具有低漂移的片上4.
096V基准电压出色的性能:–DNL:±0.
6LSB;INL:±1.
75LSB–SNR:92.
5dB;THD:–110dB警报→高,低阈值multiSPI接口,支持菊链式连接扩展工业温度范围:-40°C至+125°C2应应用用通道隔离的可编程逻辑控制器(PLC)模拟输入模块测试和测量电池组监视3说说明明ADS8691、ADS8695和ADS8699属于基于逐次逼近(SAR)模数转换器(ADC)的集成数据采集系统系列.
此类器件采用高速高精度SARADC、集成模拟前端(AFE)输入驱动器电路、高达±20V的过压保护电路以及一个温度漂移极低的4.
096V片上基准.
此类器件由5V模拟单电源供电,但支持±12.
288V、±6.
144V、±10.
24V、±5.
12V和±2.
56V实际双极输入范围以及0V至12.
288V、0V至10.
24V、0V至6.
144V和0V至5.
12V单极输入范围.
各输入范围的增益和偏移误差均可在特定数值范围内进行调节,确保直流精度较高.
通过针对器件内部寄存器进行编程可选择输入范围.
该器件提供恒定阻性输入阻抗(≥1MΩ),不受所选输入范围的影响.
multiSPI数字接口向后兼容传统SPI协议.
此外,该器件的可配置特性便于连接各种主机控制器.
器器件件信信息息(1)器器件件编编号号封封装装封封装装尺尺寸寸((标标称称值值))ADS869xTSSOP(16)5.
00mm*4.
40mm(1)如需了解所有可用封装,请参阅数据表末尾的可订购产品附录.
方方框框图图2ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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com.
cnCopyright2016–2018,TexasInstrumentsIncorporated目目录录1特特性性.
12应应用用.
13说说明明.
14修修订订历历史史记记录录25PinConfigurationandFunctions.
36Specifications.
46.
1AbsoluteMaximumRatings46.
2ESDRatings.
46.
3RecommendedOperatingConditions.
46.
4ThermalInformation.
46.
5ElectricalCharacteristics.
56.
6TimingRequirements:ConversionCycle.
96.
7TimingRequirements:AsynchronousReset.
96.
8TimingRequirements:SPI-CompatibleSerialInterface96.
9TimingRequirements:Source-SynchronousSerialInterface(ExternalClock)106.
10TimingRequirements:Source-SynchronousSerialInterface(InternalClock)106.
11TypicalCharacteristics.
147DetailedDescription217.
1Overview217.
2FunctionalBlockDiagram217.
3FeatureDescription.
227.
4DeviceFunctionalModes.
347.
5Programming.
397.
6RegisterMaps.
478ApplicationandImplementation558.
1ApplicationInformation.
558.
2TypicalApplication559PowerSupplyRecommendations.
599.
1PowerSupplyDecoupling.
599.
2PowerSaving.
5910Layout.
6010.
1LayoutGuidelines6010.
2LayoutExample6111器器件件和和文文档档支支持持6211.
1文档支持.
6211.
2相关链接.
6211.
3接收文档更新通知6211.
4社区资源.
6211.
5商标.
6211.
6静电放电警告.
6211.
7术语表6212机机械械、、封封装装和和可可订订购购信信息息.
624修修订订历历史史记记录录ChangesfromOriginal(December2016)toRevisionAPage已删除删除了特性部分警报→高,低阈值要点中的每通道.
1已删除删除了文档中的WQFN封装选项1DeletedRUM(WQFN)informationfromPinConfigurationandFunctionssection.
3Deletedoffersalowimpedanceof30kΩfromfootnotes2and3inAbsoluteMaximumRatingstable4DeletedRUM(WQFN)columnfromThermalInformationtable.
4ChangedtestconditionsofInputOvervoltageProtectionCircuit,VOVPparameter.
5DeletedWQFNrowfromVREFIOanddVREFIO/dTAparameters7DeletedmultichannelreferencefromOverviewsection21ChangedtheinputvoltagerangeforeachanalogchanneltotheinputvoltagerangeinAnalogInputStructuresection.
.
22ChangedInputOvervoltageProtectionLimitsWhenAVDD=5VtablenamefromInputOvervoltageProtectionLimitsWhenAVDD=5VorOffersaLowImpedanceof30kΩ.
23ChangedAVDDisfloatingwithanimpedance30kΩtoAVDDisfloatinginInputProtectionCircuitsection.
24ChangedInputOvervoltageProtectionLimitsWhenAVDD=FloatingtabletitlefromInputOvervoltageProtectionLimitsWhenAVDD=FloatingwithImpedance30kΩ.
24DeletedRUM(WQFN)packageinformationfromExternalReferencesection30AddedfootnotestoListofInputCommandstable413ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporated5PinConfigurationandFunctionsPWPackage16-PinTSSOPTopView(NottoScale)(1)AI=analoginput,AIO=analoginput/output,DI=digitalinput,DO=digitaloutput,andP=powersupply.
PinFunctionsNAMENO.
TYPE(1)DESCRIPTIONTSSOPAGND3PAnaloggroundpin.
DecouplewiththeAVDDpin.
AIN_GND8AIAnaloginput:negative.
DecouplewiththeAIN_Ppin.
AIN_P7AIAnaloginput:positive.
DecouplewiththeAIN_GNDpin.
ALARM/SDO-1/GPO14DOMulti-functionoutputpin.
Activehighalarm.
Dataoutput1forserialcommunication.
General-purposeoutputpin.
AVDD2PAnalogsupplypin.
DecouplewiththeAGNDpin.
CONVST/CS11DIDual-functionalitypin.
Activehighlogic:conversionstartinputpin;aCONVSTrisingedgebringsthedevicefromacquisitionphasetoconversionphase.
Activelowlogic:chip-selectinputpin;thedevicetakescontrolofthedatabuswhenCSislow;theSDO-xpinsgototri-statewhenCSishigh.
DGND1PDigitalgroundpin.
DecouplewiththeDVDDpin.
DVDD16PDigitalsupplypin.
DecouplewiththeDGNDpin.
REFCAP6AOADCreferencebufferdecouplingcapacitorpin.
DecouplewiththeREFGNDpin.
REFGND5PReferencegroundpin;shorttotheanaloggroundplane.
DecouplewiththeREFIOandREFCAPpins.
REFIO4AIOInternalreferenceoutputandexternalreferenceinputpin.
DecouplewithREFGND.
RST9DIActivelowlogicinputtoresetthedevice.
RVS15DOMulti-functionoutputpinforserialinterface;seetheRESETStatesection.
WithCSheldhigh,RVSreflectsthestatusoftheinternalADCSTsignal.
WithCSlow,thestatusofRVSdependsontheoutputprotocolselection.
SCLK12DISerialcommunication:clockinputpinfortheserialinterface.
Allsystem-synchronousdatatransferprotocolsaretimedwithrespecttotheSCLKsignal.
SDI10DIDualfunction:datainputpinforserialcommunication.
Chaindatainputduringserialcommunicationindaisy-chainmode.
SDO-013DOSerialcommunication:dataoutput04ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporated(1)StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.
Thesearestressratingsonly,anddonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperatingConditions.
Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2)AVDD=5V.
(3)AVDD=floating.
6Specifications6.
1AbsoluteMaximumRatingsoveroperatingfree-airtemperaturerange(unlessotherwisenoted)(1)MINMAXUNITAIN_P,AIN_GNDtoGNDAVDD=5V(2)–2020VAVDD=floating(3)–1111AVDDtoGNDorDVDDtoGND–0.
37VREFCAPtoREFGNDorREFIOtoREFGND–0.
35.
7VGNDtoREFGND–0.
30.
3VDigitalinputpinstoGND–0.
3DVDD+0.
3VDigitaloutputpinstoGND–0.
3DVDD+0.
3VTemperatureOperating,TA–40125°CStorage,Tstg–65150(1)JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2)JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
6.
2ESDRatingsVALUEUNITV(ESD)ElectrostaticdischargeHumanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1)Analoginputpins(AIN_P,AIN_GND)±4000VAllotherpins±2000Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101(2)±5006.
3RecommendedOperatingConditionsoveroperatingfree-airtemperaturerange(unlessotherwisenoted)MINNOMMAXUNITAVDDAnalogsupplyvoltage4.
7555.
25VDVDDDigitalsupplyvoltage1.
653.
3AVDDV(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplicationreport.
6.
4ThermalInformationTHERMALMETRIC(1)ADS8691,ADS8695,ADS8699UNITPW(TSSOP)16PINSRθJAJunction-to-ambientthermalresistance95.
7°C/WRθJC(top)Junction-to-case(top)thermalresistance29.
3°C/WRθJBJunction-to-boardthermalresistance41.
5°C/WψJTJunction-to-topcharacterizationparameter1.
5°C/WψJBJunction-to-boardcharacterizationparameter40.
8°C/WRθJC(bot)Junction-to-case(bottom)thermalresistanceN/A°C/W5ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporated(1)Idealinputspan,doesnotincludegainoroffseterror.
6.
5ElectricalCharacteristicsallminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITANALOGINPUTSVINFull-scaleinputspan(1)(AIN_PtoAIN_GND)Inputrange=±3*VREF–12.
28812.
288VInputrange=±2.
5*VREF–10.
2410.
24Inputrange=±1.
5*VREF–6.
1446.
144Inputrange=±1.
25*VREF–5.
125.
12Inputrange=±0.
625*VREF–2.
562.
56Inputrange=3*VREF012.
288Inputrange=2.
5*VREF010.
24Inputrange=1.
5*VREF06.
144Inputrange=1.
25*VREF05.
12AIN_POperatinginputrangeInputrange=±3*VREF–12.
28812.
288VInputrange=±2.
5*VREF–10.
2410.
24Inputrange=±1.
5*VREF–6.
1446.
144Inputrange=±1.
25*VREF–5.
125.
12Inputrange=±0.
625*VREF–2.
562.
56Inputrange=3*VREF012.
288Inputrange=2.
5*VREF010.
24Inputrange=1.
5*VREF06.
144Inputrange=1.
25*VREF05.
12AIN_GNDOperatinginputrangeAllinputranges–0.
100.
1VRINInputimpedanceAtTA=25°CInputrange=±3*VREF1.
021.
21.
38MΩInputrange=±1.
5*VREF1.
021.
21.
38Inputrange=3*VREF1.
021.
21.
38Inputrange=1.
5*VREF1.
021.
21.
38Inputrange=±2.
5*VREF0.
8511.
15Inputrange=±1.
25*VREF0.
8511.
15Inputrange=±0.
625*VREF0.
8511.
15Inputrange=2.
5*VREF0.
8511.
15Inputrange=1.
25*VREF0.
8511.
15Inputimpedancedrift725ppm/°CIINInputcurrentWithvoltageattheAIN_Ppin=VINInputrange=±3*VREF(VIN–2.
5)/RINAInputrange=±2.
5*VREF(VIN–2.
2)/RINInputrange=±1.
5*VREF(VIN–2.
0)/RINInputrange=±1.
25*VREF(VIN–2.
0)/RINInputrange=±0.
625*VREF(VIN–1.
6)/RINInputrange=3*VREF(VIN–2.
6)/RINInputrange=2.
5*VREF(VIN–2.
5)/RINInputrange=1.
5*VREF(VIN–2.
7)/RINInputrange=1.
25*VREF(VIN–2.
5)/RININPUTOVERVOLTAGEPROTECTIONCIRCUITVOVPAllinputrangesAVDD=5V,allinputranges–2020VAVDD=floating,allinputranges–1111INPUTBANDWIDTHf–3dBSmall-signalInputbandwidth–3dBAllinputranges15kHzf–0.
1dB–0.
1dBAllinputranges2.
56ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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com.
cnCopyright2016–2018,TexasInstrumentsIncorporatedElectricalCharacteristics(continued)allminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNIT(2)ThisspecificationindicatestheendpointINL,notbest-fitINL.
(3)Unipolarrangesare0V–12.
288V,0V–10.
24V,0V–6.
144V,and0V–5.
12V.
(4)Measuredrelativetoactualmeasuredreference.
(5)Bipolarrangesare±12.
288V,±10.
24V,±6.
144V,±5.
12V,and±2.
56V.
(6)Excludesinternalreferenceaccuracyerror.
(7)Excludesinternalreferencetemperaturedrift.
(8)Allspecificationsexpressedindecibels(dB)refertothefull-scaleinput(FSR)andaretestedwitha1-kHzinputsignal0.
25dBbelowfull-scale,unlessotherwisespecified.
(9)Calculatedonthefirstnineharmonicsoftheinputfrequency.
SYSTEMPERFORMANCEResolution18BitsNMCNomissingcodes18BitsDNLDifferentialnonlinearity(2)Allinputranges–0.
9±0.
61.
1LSBINLIntegralnonlinearity(2)ADS8691Inputrange=±3*VREF,±2.
5*VREF,±1.
5*VREF,±1.
25*VREF–3.
25±1.
753.
25LSBInputrange=±0.
625*VREF–4.
25±2.
254.
25Allunipolarranges(3)–3.
5±23.
5ADS8695,ADS8699Allinputranges–3±1.
53EOOffseterror(4)AtTA=25°CAllbipolarranges(5)–1±0.
21mVAllunipolarranges(3)–2±0.
22OffseterrordriftwithtemperatureAllinputranges–3±0.
753ppm/°CEGGainerror(6)AtTA=25°C,allinputranges–0.
025±0.
010.
025%FSRGainerrordriftwithtemperature(7)Allinputranges–5±15ppm/°CDYNAMICCHARACTERISTICSSNRSignal-to-noiseratio(8)Inputrange=±3*VREF9192.
5dBInputrange=±2.
5*VREF9192.
5Inputrange=±1.
5*VREF9091.
5Inputrange=±1.
25*VREF9091.
5Inputrange=±0.
625*VREF87.
7590Inputrange=3*VREF89.
591Inputrange=2.
5*VREF89.
591Inputrange=1.
5*VREF8891Inputrange=1.
25*VREF8890THDTotalharmonicdistortion(9)(8)Allinputranges–110dBSINADSignal-to-noise+distortion(8)Inputrange=±3*VREF90.
992.
5dBInputrange=±2.
5*VREF90.
992.
5Inputrange=±1.
5*VREF89.
991.
5Inputrange=±1.
25*VREF89.
991.
5Inputrange=±0.
625*VREF87.
6590Inputrange=3*VREF89.
2591Inputrange=2.
5*VREF89.
2591Inputrange=1.
5*VREF87.
7590Inputrange=1.
25*VREF87.
7590SFDRSpurious-freedynamicrange(8)Allinputranges114dB7ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedElectricalCharacteristics(continued)allminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITSAMPLINGDYNAMICStCONVConversiontimeADS8691665nsADS86951000ADS86995000tACQAcquisitiontimeADS8691335nsADS86951000ADS86995000fcycleMaximumthroughputratewithoutlatencyADS86911000kSPSADS8695500ADS8699100INTERNALREFERENCEOUTPUTVREFIOOntheREFIOpin(configuredasanoutput)AtTA=25°C4.
0954.
0964.
097VdVREFIO/dTAInternalreferencetemperaturedrift47ppm/°CCOUT_REFIODecouplingcapacitoronREFIOpin4.
7FVREFCAPReferencevoltagetotheADC(ontheREFCAPpin)AtTA=25°C4.
0954.
0964.
097VREFCAPtemperaturedrift0.
52ppm/°CCOUT_REFCAPDecouplingcapacitoronREFCAPpin10μFTurn-ontimeCOUT_REFCAP=10F,COUT_REFIO=10F20msEXTERNALREFERENCEINPUTVREFIO_EXTExternalreferencevoltageonREFIOREFIOpinconfiguredasaninput4.
0464.
0964.
146VAVDDCOMPARATORVTH_HIGHHighthresholdvoltage5.
3VVTH_LOWLowthresholdvoltage4.
7VPOWER-SUPPLYREQUIREMENTSAVDDAnalogpower-supplyvoltage4.
7555.
25VDVDDDigitalpower-supplyvoltageOperatingrange1.
653.
3AVDDSupplyrangeforspecifiedperformance2.
73.
3AVDDIAVDD_DYNAnalogsupplycurrent,deviceconvertingatmaximumthroughputInternalreferenceADS86918.
210.
5mAADS86955.
67.
25ADS869945ExternalreferenceADS86917.
08.
75ADS86954.
45.
5ADS86992.
73.
25IAVDD_STCAnalogsupplycurrent,devicenotconvertingInternalreferenceADS86914.
76.
25mAADS8695,ADS86993.
54.
7ExternalreferenceADS86913.
54.
5ADS8695,ADS86992.
33IAVDD_STDBYAnalogsupplycurrent,deviceinSTANDBYmodeInternalreference2.
8mAExternalreference1.
6IAVDD_PDAnalogsupplycurrent,deviceinPDmodeInternalreference10μAExternalreference10IDVDD_DYNDigitalsupplycurrent,maximumthroughput0.
20.
25mAIDVDD_STDBYDigitalsupplycurrent,deviceinSTANDBYmode1μAIDVDD_PDDigitalsupplycurrent,deviceinPDmode1μA8ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedElectricalCharacteristics(continued)allminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITDIGITALINPUTS(CMOS)VIHDigitalhighinputvoltagelogiclevelDVDD>2.
35V0.
7*DVDDDVDD+0.
3VDVDD≤2.
35V0.
8*DVDDDVDD+0.
3VILDigitallowinputvoltagelogiclevelDVDD>2.
35V–0.
30.
3*DVDDVDVDD≤2.
35V–0.
30.
2*DVDDInputleakagecurrent100nAInputpincapacitance5pFDIGITALOUTPUTS(CMOS)VOHDigitalhighoutputvoltagelogiclevelIO=500-μAsource0.
8*DVDDDVDDVVOLDigitallowoutputvoltagelogiclevelIO=500-μAsink00.
2*DVDDVFloatingstateleakagecurrentOnlyfordigitaloutputpins1AInternalpincapacitance5pFTEMPERATURERANGETAOperatingfree-airtemperature–40125°C9ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporated6.
6TimingRequirements:ConversionCycleallminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)MINTYPMAXUNITTIMINGREQUIREMENTSfcycleSamplingfrequencyADS86911000kSPSADS8695500ADS8699100tcycleADCcycletimeperiod1/fcycletacqAcquisitiontimeADS8691335nsADS86951000ADS86995000TIMINGSPECIFICATIONStconvConversiontimeADS8691665nsADS86951000ADS869950006.
7TimingRequirements:AsynchronousResetallminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)MINTYPMAXUNITTIMINGREQUIREMENTStwl_RSTPulseduration:RSThigh100nsTIMINGSPECIFICATIONStD_RST_PORDelaytimeforPORreset:RSTrisingtoRVSrising20mstD_RST_APPDelaytimeforapplicationreset:RSTrisingtoCONVST/CSrising1stNAP_WKUPWake-uptime:NAPmode20stPWRUPPower-uptime:PDmode20ms6.
8TimingRequirements:SPI-CompatibleSerialInterfaceallminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)MINTYPMAXUNITTIMINGREQUIREMENTSfCLKSerialclockfrequency66.
67MHztCLKSerialclocktimeperiod1/fCLKtPH_CKSCLKhightime0.
450.
55tCLKtPL_CKSCLKlowtime0.
450.
55tCLKtSU_CSCKSetuptime:CONVST/CSfallingtofirstSCLKcaptureedge7.
5nstSU_CKDISetuptime:SDIdatavalidtoSCLKcaptureedge7.
5nstHT_CKDIHoldtime:SCLKcaptureedgeto(previous)datavalidonSDI7.
5nstHT_CKCSDelaytime:lastSCLKcaptureedgetoCONVST/CSrising7.
5nsTIMINGSPECIFICATIONStDEN_CSDODelaytime:CONVST/CSfallingedgetodataenable9.
5nstDZ_CSDODelaytime:CONVST/CSrisingtoSDO-xgoingto3-state10nstD_CKDODelaytime:SCLKlaunchedgeto(next)datavalidonSDO-x12nstD_CSRVSDelaytime:CONVST/CSrisingedgetoRVSfalling14ns10ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporated6.
9TimingRequirements:Source-SynchronousSerialInterface(ExternalClock)allminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)MINTYPMAXUNITTIMINGREQUIREMENTSfCLKSerialclockfrequency66.
67MHztCLKSerialclocktimeperiod1/fCLKtPH_CKSCLKhightime0.
450.
55tCLKtPL_CKSCLKlowtime0.
450.
55tCLKTIMINGSPECIFICATIONStDEN_CSDODelaytime:CONVST/CSfallingedgetodataenable9.
5nstDZ_CSDODelaytime:CONVST/CSrisingtoSDO-xgoingto3-state10nstD_CKRVS_rDelaytime:SCLKrisingedgetoRVSrising14nstD_CKRVS_fDelaytime:SCLKfallingedgetoRVSfalling14nstD_RVSDODelaytime:RVSrisingto(next)datavalidonSDO-x2.
5nstD_CSRVSDelaytime:CONVST/CSrisingedgetoRVSdisplayinginternaldevicestate15ns6.
10TimingRequirements:Source-SynchronousSerialInterface(InternalClock)allminimumandmaximumspecificationsareatTA=–40°Cto+125°C;typicalspecificationsareatTA=25°C;AVDD=5V,DVDD=3.
3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)MINTYPMAXUNITTIMINGSPECIFICATIONStDEN_CSDODelaytime:CONVST/CSfallingedgetodataenable9.
5nstDZ_CSDODelaytime:CONVST/CSrisingtoSDO-xgoingto3-state10nstDEN_CSRVSDelaytime:CONVST/CSfallingedgetofirstrisingedgeonRVS50nstD_RVSDODelaytime:RVSrisingto(next)datavalidonSDO-x2.
5nstINTCLKTimeperiod:internalclock15nstCYC_RVSTimeperiod:RVSsignal15nstWH_RVSRVShightime0.
40.
6tINTCLKtWL_RVSRVSlowtime0.
40.
6tINTCLKtD_CSRVSDelaytime:CONVST/CSrisingedgetoRVSdisplayinginternaldevicestate15ns11ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedFigure1.
ConversionCycleTimingDiagramFigure2.
AsynchronousResetTimingDiagramFigure3.
StandardSPIInterfaceTimingDiagramforCPHA=012ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedFigure4.
StandardSPIInterfaceTimingDiagramforCPHA=1Figure5.
multiSPIInterfaceTimingDiagramforDualSDO-xandCPHA=013ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedFigure6.
multiSPIInterfaceTimingDiagramforDualSDO-xandCPHA=1Figure7.
multiSPISource-SynchronousExternalClockSerialInterfaceTimingDiagramFigure8.
multiSPISource-SynchronousInternalClockSerialInterfaceTimingDiagram14ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporated6.
11TypicalCharacteristicsatTA=25°C,AVDD=5V,DVDD=3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)Figure9.
InputI-VCharacteristicAcrossInputRangesRange=±12.
288VFigure10.
InputI-VCharacteristicAcrossTemperatureFigure11.
InputImpedanceDriftvsTemperatureNumberofsamples=3398Figure12.
TypicalDistributionofInputImpedanceMean=131076.
2,sigma=1.
9,input=0VFigure13.
DCHistogramforMid-ScaleInputs(±12.
288V)Mean=131066.
8,sigma=2.
04,input=0VFigure14.
DCHistogramforMid-ScaleInputs(±10.
24V)15ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedTypicalCharacteristics(continued)atTA=25°C,AVDD=5V,DVDD=3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)Mean=131063.
9,sigma=2.
23,input=0VFigure15.
DCHistogramforMid-ScaleInputs(±6.
144V)Mean=131073.
5,sigma=2.
23,input=0VFigure16.
DCHistogramforMid-ScaleInputs(±5.
12V)Mean=131073,sigma=3.
24,input=0VFigure17.
DCHistogramforMid-ScaleInputs(±2.
56V)Mean=131075.
5,sigma=2.
41,input=6.
144VFigure18.
DCHistogramforMid-ScaleInputs(0V–12.
288V)Mean=131073.
9,sigma=2.
49,input=5.
12VFigure19.
DCHistogramforMid-ScaleInputs(0V–10.
24V)Mean=131082,sigma=3.
17,input=3.
072VFigure20.
DCHistogramforMid-ScaleInputs(0V–6.
144V)16ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedTypicalCharacteristics(continued)atTA=25°C,AVDD=5V,DVDD=3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)Mean=131076.
8,sigma=3.
61,input=2.
56VFigure21.
DCHistogramforMid-ScaleInputs(0V–5.
12V)AllinputrangesFigure22.
TypicalDNLforAllCodesAllinputrangesFigure23.
DNLvsTemperatureFigure24.
TypicalINLforAllCodes(AllBipolarRanges)Figure25.
TypicalINLforAllCodes(AllUnipolarRanges)Figure26.
INLvsTemperature(AllBipolarRanges)17ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedTypicalCharacteristics(continued)atTA=25°C,AVDD=5V,DVDD=3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)Figure27.
INLvsTemperature(AllUnipolarRanges)Figure28.
OffsetErrorvsTemperatureAcrossInputRangesFigure29.
TypicalHistogramforOffsetDriftFigure30.
GainErrorvsTemperatureAcrossInputRangesFigure31.
TypicalHistogramforGainErrorDriftFigure32.
GainErrorvsExternalResistance(REXT)18ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedTypicalCharacteristics(continued)atTA=25°C,AVDD=5V,DVDD=3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)Numberofpoints=64k,fIN=1kHzFigure33.
TypicalFFTPlot(AllRanges)fortheADS8691Numberofpoints=64k,fIN=1kHzFigure34.
TypicalFFTPlot(AllRanges)fortheADS8695Numberofpoints=64k,fIN=1kHzFigure35.
TypicalFFTPlot(AllRanges)fortheADS8699Figure36.
SNRvsInputFrequencyfIN=1kHzFigure37.
SNRvsTemperatureFigure38.
SINADvsInputFrequency19ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedTypicalCharacteristics(continued)atTA=25°C,AVDD=5V,DVDD=3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)fIN=1kHzFigure39.
SINADvsTemperatureFigure40.
THDvsInputFrequencyfIN=1kHzFigure41.
THDvsTemperatureFigure42.
AVDDCurrentvsTemperatureFigure43.
AVDDCurrentvsThroughputFigure44.
AVDDCurrentvsTemperature(DuringSampling)20ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedTypicalCharacteristics(continued)atTA=25°C,AVDD=5V,DVDD=3V,VREF=4.
096V(internal),andmaximumthroughput(unlessotherwisenoted)Figure45.
AVDDCurrentvsTemperature(StandbyMode)Figure46.
AVDDCurrentvsTemperature(Power-DownMode)21ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporated7DetailedDescription7.
1OverviewTheADS869xdevicesbelongtoafamilyofhigh-speed,high-performance,easy-to-useintegrateddataacquisitionsystem.
Thissingle-channeldevicesupportstruebipolarinputvoltageswingsupto±12.
288V,operatingonasingle5-Vanalogsupply.
ThedevicefeaturesanenhancedSPIinterface(multiSPI)thatallowsthesamplingratetobemaximizedevenwithlowerspeedhostcontrollers.
Thedeviceconsistsofahigh-precisionsuccessiveapproximationregister(SAR)analog-to-digitalconverter(ADC)andapower-optimizedanalogfront-end(AFE)circuitforsignalconditioningthatincludes:Ahigh-resistiveinputimpedance(≥1MΩ)thatisindependentofthesamplingrateAprogrammablegainamplifier(PGA)withapseudo-differentialinputconfigurationsupportingninesoftware-programmableunipolarandbipolarinputrangesAsecond-order,low-passantialiasingfilterAnADCdriveramplifierthatensuresquicksettlingoftheSARADCinputforhighaccuracyAninputovervoltageprotectioncircuitupto±20VThedevicealsofeaturesalowtemperaturedrift,4.
096-Vinternalreferencewithafast-settlingbufferandamultiSPIserialinterfacewithdaisy-chain(DAISY)andALARMfeatures.
TheintegrationoftheprecisionAFEcircuitwithhighinputimpedanceandaprecisionADCoperatingfromasingle5-Vsupplyoffersasimplifiedendsolutionwithoutrequiringexternalhigh-voltagebipolarsuppliesandcomplicateddrivercircuits.
7.
2FunctionalBlockDiagram22ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporated7.
3FeatureDescription7.
3.
1AnalogInputStructureThedevicefeaturesapseudo-differentialinputstructure,meaningthatthesingle-endedanaloginputsignalisappliedatthepositiveinputAIN_PandthenegativeinputAIN_GNDistiedtoGND.
Figure47showsthesimplifiedcircuitschematicfortheAFEcircuit,includingtheinputovervoltageprotectioncircuit,PGA,low-passfilter(LPF),andhigh-speedADCdriver.
Figure47.
SimplifiedAnalogFront-EndCircuitSchematicThedevicecansupportmultipleunipolarorbipolar,single-endedinputvoltagerangesbasedontheconfigurationoftheprogramregisters.
AsexplainedintheRANGE_SEL_REGregister,theinputvoltagerangecanbeconfiguredtobipolar±3*VREF,±2.
5*VREF,±1.
5*VREF,±1.
25*VREF,and±0.
625*VREForunipolar0to3*VREF,0to2.
5*VREF,0to1.
5*VREFand0to1.
25*VREF.
Withtheinternalorexternalreferencevoltagesetto4.
096V,theinputrangesofthedevicecanbeconfiguredtobipolarrangesof±12.
288V,±10.
24V,±6.
144V,±5.
12V,and±2.
56Vorunipolarrangesof0Vto12.
288V,0Vto10.
24V,0Vto6.
144V,and0Vto5.
12V.
Thedevicesamplesthevoltagedifference(AIN_P–AIN_GND)betweentheanaloginputandtheAIN_GNDpin.
Thedeviceallowsa±0.
1-VrangeontheAIN_GNDpin.
Thisfeatureisusefulinmodularsystemswherethesensororsignal-conditioningblockisfurtherawayfromtheADContheboardandwhenadifferenceinthegroundpotentialofthesensororsignalconditionerfromtheADCgroundispossible.
Insuchcases,runningseparatewiresfromtheAIN_GNDpinofthedevicetothesensororsignal-conditioninggroundisrecommended.
Inordertoobtainoptimumperformance,theinputcurrentsandimpedancesalongeachinputpatharerecommendedtobematched.
Thetwosingle-endedsignalstoAIN_PandAIN_GNDmustberoutedassymmetricallyaspossiblefromthesignalsourcetotheADCinputpins.
Iftheanaloginputpin(AIN_P)tothedeviceisleftfloating,theoutputoftheADCcorrespondstoaninternalbiasingvoltage.
TheoutputfromtheADCmustbeconsideredasinvalidifthedeviceisoperatedwithfloatinginputpins.
Thisconditiondoesnotcauseanydamagetothedevice,whichbecomesfullyfunctionalwhenavalidinputvoltageisappliedtothepins.
7.
3.
2AnalogInputImpedanceThedevicepresentsaresistiveinputimpedance≥1MΩoneachoftheanaloginputs.
TheinputimpedanceisindependentoftheADCsamplingfrequencyortheinputsignalfrequency.
Theprimaryadvantageofsuchhigh-impedanceinputsistheeaseofdrivingtheADCinputswithoutrequiringdrivingamplifierswithlowoutputimpedance.
Bipolar,high-voltagepowersuppliesarenotrequiredinthesystembecausethisADCdoesnotrequireanyhigh-voltage,front-enddrivers.
Inmostapplications,thesignalsourcesorsensoroutputscanbedirectlyconnectedtotheADCinput,thussignificantlysimplifyingthedesignofthesignalchain.
Inordertomaintainthedcaccuracyofthesystem,matchingtheexternalsourceimpedanceontheAIN_PinputpinwithanequivalentresistanceontheAIN_GNDpinisrecommended.
Thismatchinghelpscancelanyadditionaloffseterrorcontributedbytheexternalresistance.
23ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedFeatureDescription(continued)(1)GND=0V,AIN_GND=0V,|VRANGE|isthemaximuminputvoltageforanyselectedinputrange,and|VOVP|isthebreak-downvoltagefortheinternalOVPcircuit.
AssumethatRSisapproximately0Ω.
7.
3.
3InputProtectionCircuitThedevicefeaturesaninternalovervoltageprotection(OVP)circuitoneachoftheanaloginputs.
Usetheinternalprotectioncircuitonlyasasecondaryprotectionscheme.
Theexternalprotectiondevicesintheendapplicationarehighlyrecommendedtobeusedtoprotectagainstsurges,electrostaticdischarge(ESD),andelectricalfasttransient(EFT)conditions.
AconceptualblockdiagramoftheinternalOVPcircuitisshowninFigure48.
Figure48.
InputOvervoltageProtectionCircuitSchematicAsshowninFigure48,thecombinationofthe1-MΩ(or,1.
2MΩforappropriateinputranges)inputresistorsalongwiththePGAgain-settingresistorsRFBandRDClimitthecurrentflowingintotheinputpin.
Acombinationofanti-paralleldiodes,D1andD2areaddedtoprotecttheinternalcircuitryandsettheovervoltageprotectionlimits.
Table1explainsthevariousoperatingconditionsforthedevicewhenpoweredon.
Thistableindicatesthatwhenthedeviceisproperlypoweredup(AVDD=5V)oroffersalowimpedanceof|VOVP|BeyondovervoltagerangeAllinputrangesSaturatedThisusageconditioncancauseirreversibledamagetothedevice.
24ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporated(1)AVDD=floating,GND=0V,AIN_GND=0V,|VRANGE|isthemaximuminputvoltageforanyselectedinputrange,and|VOVP|isthebreak-downvoltagefortheinternalOVPcircuit.
AssumethatRSisapproximately0Ω.
TheresultsindicatedinTable1arebasedonanassumptionthattheanaloginputpinisdrivenbyaverylowimpedancesource(RSisapproximately0Ω).
However,ifthesourcedrivingtheinputhashigherimpedance,thecurrentflowingthroughtheprotectiondiodesreducesfurther,therebyincreasingtheOVPvoltagerange.
Highersourceimpedancesresultingainerrorsandcontributetooverallsystemnoiseperformance.
Figure49showsthevoltageversuscurrentresponseoftheinternalovervoltageprotectioncircuitwhenthedeviceispoweredon.
Accordingtothiscurrent-to-voltage(I-V)response,thecurrentflowingintothedeviceinputpinislimitedbythe1-MΩ(or1.
2MΩforappropriateinputranges)inputimpedance.
However,forvoltagesbeyond±20V,theinternalnodevoltagessurpassthebreak-downvoltageforinternaltransistors,thussettingthelimitforovervoltageprotectionontheinputpin.
ThesameovervoltageprotectioncircuitalsoprovidesprotectiontothedevicewhenthedeviceisnotpoweredonandAVDDisfloating.
ThisconditioncanarisewhentheinputsignalsareappliedbeforetheADCisfullypoweredon.
TheovervoltageprotectionlimitsforthisconditionareshowninTable2.
Table2.
InputOvervoltageProtectionLimitsWhenAVDD=Floating(1)INPUTCONDITION(VOVP=±11V)TESTCONDITIONADCOUTPUTCOMMENTSCONDITIONRANGE|VIN||VOVP|BeyondovervoltagerangeAllinputrangesInvalidThisusageconditioncancauseirreversibledamagetothedevice.
Figure50showstheI-Vresponseoftheinternalovervoltageprotectioncircuitwhenthedeviceisnotpoweredon.
AccordingtothisI-Vresponse,thecurrentflowingintothedeviceinputpinislimitedbythe1-MΩinputimpedance.
However,forvoltagesbeyond±11V,theinternalnodevoltagesurpassesthebreak-downvoltageforinternaltransistors,thussettingthelimitforovervoltageprotectionontheinputpin.
Figure49.
I-VCurvefortheInputOVPCircuit(AVDD=5V)Figure50.
I-VCurvefortheInputOVPCircuit(AVDD=Floating)25ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporated7.
3.
4ProgrammableGainAmplifier(PGA)Thedevicefeaturesaprogrammablegainamplifier(PGA)aspartoftheanalogsignal-conditioningcircuitthatconvertstheoriginalsingle-endedinputsignalintoafully-differentialsignaltodrivetheinternalSARADC.
ThePGAalsoadjuststhecommon-modeleveloftheinputsignalbeforefeedingitintotheSARADCtoensuremaximumusageoftheADCinputdynamicrange.
Dependingontherangeoftheinputsignal,thePGAgaincanbeadjustedbysettingtheRANGE_SEL[3:0]bitsintheconfigurationregister(seetheRANGE_SEL_REGregister).
Thedefaultorpower-onstatefortheRANGE_SEL[3:0]bitsis0000,correspondingtoaninputsignalrangeof±3*VREF.
Table3liststhevariousconfigurationsoftheRANGE_SEL[3:0]bitsforthedifferentanaloginputvoltageranges.
ThePGAusesaprecisely-matchednetworkofresistorsformultiplegainconfigurations.
Matchingbetweentheseresistorsisaccuratelytrimmedtokeeptheoverallgainerrorlowacrossallinputranges.
Table3.
InputRangeSelectionBitsConfigurationANALOGINPUTRANGERANGE_SEL[3:0]BIT3BIT2BIT1BIT0±3*VREF0000±2.
5*VREF0001±1.
5*VREF0010±1.
25*VREF0011±0.
625*VREF01000–3*VREF10000–2.
5*VREF10010–1.
5*VREF10100–1.
25*VREF10117.
3.
5Second-Order,Low-PassFilter(LPF)Inordertomitigatethenoiseofthefront-endamplifierandgainresistorsofthePGA,theAFEcircuitofthedevicefeaturesasecond-order,antialiasingLPFattheoutputofthePGA.
ThemagnitudeandphaseresponseoftheanalogantialiasingfilterareshowninFigure51andFigure52,respectively.
Formaximumperformance,the–3-dBcutofffrequencyfortheantialiasingfilteristypicallysetto15kHz.
TheperformanceofthefilterisconsistentacrossallinputrangessupportedbytheADC.
Figure51.
Second-OrderLPFMagnitudeResponseFigure52.
Second-OrderLPFPhaseResponse26ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporated7.
3.
6ADCDriverInordertomeettheperformanceofthedeviceatthemaximumsamplingrate,thesample-and-holdcapacitorsattheinputoftheADCmustbesuccessfullychargedanddischargedduringtheacquisitiontimewindow.
ThisdriverequirementattheinputoftheADCnecessitatestheuseofahigh-bandwidth,low-noise,andstableamplifierbuffer.
Suchaninputdriverisintegratedinthefront-endsignalpathoftheanaloginputchannelofthedevice.
7.
3.
7ReferenceThedevicecanoperatewitheitheraninternalvoltagereferenceoranexternalvoltagereferenceusingtheinternalbuffer.
TheinternalorexternalreferenceselectionisdeterminedbyprogrammingtheINTREF_DISbitoftheRANGE_SEL_REGregister.
Theinternalreferencesourceisenabled(INTREF_DIS=0)bydefaultafterresetorwhenthedevicepowersup.
TheINTREF_DISbitmustbeprogrammedtologic1todisabletheinternalreferencesourcewheneveranexternalreferencesourceisused.
7.
3.
7.
1InternalReferenceThedevicefeaturesaninternalreferencesourcewithanominaloutputvalueof4.
096V.
Inordertoselecttheinternalreference,theINTREF_DISbitoftheRANGE_SEL_REGregistermustbeprogrammedtologic0.
Whentheinternalreferenceisused,theREFIOpinbecomesanoutputwiththeinternalreferencevalue.
A4.
7-F(minimum)decouplingcapacitorisrecommendedtobeplacedbetweentheREFIOpinandREFGND,asshowninFigure53.
ThecapacitormustbeplacedasclosetotheREFIOpinaspossible.
Theoutputimpedanceoftheinternalband-gapcircuitcreatesalow-passfilterwiththiscapacitortoband-limitthenoiseofthereference.
TheuseofasmallercapacitorvalueallowshigherreferencenoiseinthesystemthatcanpotentiallydegradeSNRandSINADperformance.
TheREFIOpinmustnotbeusedtodriveexternalacordcloadsbecauseoflimitedcurrentoutputcapability.
TheREFIOpincanbeusedasasourceiffollowedbyasuitableopampbuffer(suchastheOPA320).
Figure53.
DeviceConnectionsforUsinganInternal4.
096-VReference27ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedThedeviceinternalreferenceisfactory-trimmedtoensuretheinitialaccuracyspecification.
ThehistograminFigure54showsthedistributionoftheinternalvoltagereferenceoutputtakenfrommorethan3420productiondevices.
Figure54.
InternalReferenceAccuracyHistogramatRoomTemperatureTheinitialaccuracyspecificationfortheinternalreferencecanbedegradedifthedieisexposedtoanymechanicalorthermalstress.
Heatingthedevicewhenbeingsolderedtoaprintedcircuitboard(PCB)andanysubsequentsolderreowisaprimarycauseforshiftsintheVREFvalue.
Themaincauseofthermalhysteresisisachangeindiestressandisthereforeafunctionofthepackage,die-attachmaterial,andmoldingcompound,aswellasthelayoutofthedeviceitself.
Inordertoillustratethiseffect,30devicesweresolderedusinglead-freesolderpastewiththemanufacturersuggestedreflowprofile,asexplainedintheAN-2029Handling&ProcessRecommendationsapplicationreport.
TheinternalvoltagereferenceoutputismeasuredbeforeandafterthereflowprocessandthetypicalshiftinvalueisshowninFigure55.
Althoughalltestedunitsexhibitapositiveshiftintheiroutputvoltages,negativeshiftsarealsopossible.
ThehistograminFigure55showsthetypicalshiftforexposuretoasinglereflowprofile.
Exposuretomultiplereflows,whichiscommononPCBswithsurface-mountcomponentsonbothsides,causesadditionalshiftsintheoutputvoltage.
IfthePCBistobeexposedtomultiplereflows,soldertheADS869xinthesecondpasstominimizedeviceexposuretothermalstress.
Figure55.
SolderHeatShiftDistributionHistogram28ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedTheinternalreferenceisalsotemperaturecompensatedtoprovideexcellenttemperaturedriftoveranextendedindustrialtemperaturerangeof–40°Cto+125°C.
Figure56showsthevariationoftheinternalreferencevoltageacrosstemperaturefordifferentvaluesoftheAVDDsupplyvoltage.
Thetemperaturedriftoftheinternalreferenceisalsoafunctionofthepackagetype.
Figure57showshistogramdistributionofthereferencevoltagedrift.
Figure56.
REFIOVoltageVariationAcrossAVDDandTemperatureAVDD=5V,numberofdevices=30,ΔT=–40°Cto+125°CFigure57.
InternalReferenceTemperatureDriftHistogram29ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporated7.
3.
7.
2ExternalReferenceForapplicationsthatrequireabetterreferencevoltageoracommonreferencevoltageformultipledevices,thedeviceprovidesaprovisiontouseanexternalreferencesourcealongwithaninternalbuffertodrivetheADCreferencepin.
Inordertoselecttheexternalreferencemode,theINTREF_DISbitoftheRANGE_SEL_REGregistermustbeprogrammedtologic1.
Inthismode,anexternal4.
096-VreferencemustbeappliedattheREFIOpin,whichfunctionsasaninput.
Anylow-power,low-drift,orsmall-sizeexternalreferencecanbeusedinthismodebecausetheinternalbufferisoptimallydesignedtohandlethedynamicloadingontheREFCAPpinthatisinternallyconnectedtotheADCreferenceinput.
Theoutputoftheexternalreferencemustbeappropriatelyfilteredtominimizetheresultingeffectofthereferencenoiseonsystemperformance.
AtypicalconnectiondiagramforthismodeisshowninFigure58.
Figure58.
DeviceConnectionsforUsinganExternal4.
096-VReferenceTheoutputoftheinternalreferencebufferappearsattheREFCAPpin.
Aminimumcapacitanceof10FmustbeplacedbetweentheREFCAPandREFGNDpins.
Placeanothercapacitorof1FasclosetotheREFCAPpinaspossiblefordecouplinghigh-frequencysignals.
Donotusetheinternalbuffertodriveexternalacordcloadsbecauseofthelimitedcurrentoutputcapabilityofthisbuffer.
30ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedTheperformanceoftheinternalbufferoutputisverystableacrosstheentireoperatingtemperaturerangeof–40°Cto+125°C.
Figure59showsthevariationintheREFCAPoutputacrosstemperaturefordifferentvaluesoftheAVDDsupplyvoltage.
Thetypicalspecifiedvalueofthereferencebufferdriftovertemperatureis0.
5ppm/°C,asshowninFigure60,andthemaximumspecifiedtemperaturedriftisequalto2ppm/°C.
Figure59.
ReferenceBufferOutput(REFCAP)VariationvsSupplyandTemperatureAVDD=5V,numberofdevices=30,ΔT=–40°Cto+125°CFigure60.
ReferenceBufferTemperatureDriftHistogram31ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporated7.
3.
8ADCTransferFunctionThedevicesupportsapseudo-differentialinputsupportingbothbipolarandunipolarinputranges.
Theoutputofthedeviceisinstraight-binaryformatforbothbipolarandunipolarinputranges.
TheidealtransfercharacteristicforallinputrangesisshowninFigure61.
Thefull-scalerange(FSR)foreachinputsignalisequaltothedifferencebetweenthepositivefull-scale(PFS)inputvoltageandthenegativefull-scale(NFS)inputvoltage.
TheLSBsizeisequaltoFSR/218.
ForareferencevoltageofVREF=4.
096V,theLSBvaluescorrespondingtothedifferentinputrangesarelistedinTable4.
Figure61.
DeviceTransferFunction(Straight-BinaryFormat)Table4.
ADCLSBValuesforDifferentInputRanges(VREF=4.
096V)INPUTRANGEPOSITIVEFULL-SCALE(V)NEGATIVEFULL-SCALE(V)FULL-SCALERANGE(V)LSB±3*VREF12.
288–12.
28824.
57693.
75V±2.
5*VREF10.
24–10.
2420.
4878.
125V±1.
5*VREF6.
144–6.
14412.
28846.
875V±1.
25*VREF5.
12–5.
1210.
2439.
06V±0.
625*VREF2.
56–2.
565.
1219.
53V0to3*VREF12.
288012.
28846.
875V0to2.
5*VREF10.
24010.
2439.
06V0to1.
5*VREF6.
14406.
14423.
43V0to1.
25*VREF5.
1205.
1219.
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3.
9AlarmFeaturesThedevicefeaturesanactive-highalarmoutputontheALARM/SDO-1/GPOpin,providedthatthepinisconfiguredforalarmfunctionality.
ToenabletheALARMoutputonthemulti-functionpin,setheSDO1_CONFIG[1:0]bitsoftheSDO_CTL_REGregisterto01b(seetheSDO_CTL_REGregister).
Thedevicefeaturestwotypesofalarmfunctions:aninputalarmandanAVDDalarm.
Fortheinputalarm,thevoltageattheinputoftheADCismonitoredandcomparedagainstuser-programmablehighandlowthresholdvalues.
Thedevicesetsanactivehighalarmoutputwhenthecorrespondingdigitalvalueoftheinputsignalgoesbeyondthehighorlowthresholdsetbytheuser;seetheInputAlarmsectionforadetailedexplanationoftheinputalarmfeaturefunctionality.
FortheAVDDalarm,theanalogsupplyvoltage(AVDD)oftheADCismonitoredandcomparedagainstthespecifiedtypicallowthreshold(4.
7V)andhighthreshold(5.
3V)valuesoftheAVDDsupply.
ThedevicesetsanactivehighalarmoutputifthevalueofAVDDcrossesthespecifiedlow(4.
7V)andhighthreshold(5.
3V)valuesineitherdirection.
Whenthealarmfunctionalityisturnedon,boththeinputandAVDDalarmfunctionsareenabledbydefault.
ThesealarmfunctionscanbeselectivelydisabledbyprogrammingtheIN_AL_DISandVDD_AL_DISbits(respectively)oftheRST_PWRCTL_REGregister.
Eachalarm(inputalarmorAVDDalarm)hastwotypesofalarmflagsassociatedwithit:theactivealarmflagandthetrippedalarmflag.
AllthealarmflagscanbereadintheALARM_REGregister.
Bothflagsaresetwhentheassociatedalarmistriggered.
HoweverwhiletheactivealarmisclearedattheendofthecurrentADCconversion(andsetagainifthealarmconditionpersists),thetrippedflagisclearedonlyafterALARM_REGisread.
TheALARMoutputflagsareupdatedinternallyattheendofeveryconversion.
TheseoutputflagscanbereadduringanydataframethattheuserinitiatesbybringingtheCONVST/CSsignaltoalowlevel.
TheALARMoutputflagscanbereadinthreedifferentways:eitherviatheALARMoutputpin,byreadingtheinternalALARMregisters,orbyappendingtheALARMflagstothedataoutput.
AhighlevelontheALARMpinindicatesanover-orundervoltageconditiononAVDDorontheanaloginputchannelofthedevice.
Thispincanbewiredtointerruptthehostinput.
TheinternalALARMflagbitsintheALARM_REGregisterareupdatedattheendofconversion.
AfterreceivinganALARMinterruptontheoutputpin,theinternalalarmflagregisterscanbereadtoobtainmoredetailsontheconditionsthatgeneratedthealarm.
Thealarmoutputflagscanbeselectivelyappendedtothedataoutputbitstream(seetheDATAOUT_CTL_REGregisterforconfigurationdetails).
Figure62showsafunctionalblockdiagramforthedevicealarmfunctionality.
Figure62.
AlarmFunctionalitySchematic33ADS8691,ADS8695,ADS8699www.
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3.
9.
1InputAlarmThedevicefeaturesahighandalowalarmontheanaloginput.
Thealarmscorrespondingtotheinputsignalhaveindependently-programmablethresholdsandacommonhysteresissettingthatcanbecontrolledthroughtheALARM_H_TH_REGandALARM_L_TH_REGregisters.
Thedevicesetstheinputhighalarmwhenthedigitaloutputexceedsthehighalarmupperlimit[highalarmthreshold(T)].
Thealarmresetswhenthedigitaloutputislessthanorequaltothehighalarmlowerlimit[highalarm(T)–H–1).
ThisfunctionisshowninFigure63.
Similarly,theinputlowalarmistriggeredwhenthedigitaloutputfallsbelowthelowalarmlowerlimit[lowalarmthreshold(T)].
Thealarmresetswhenthedigitaloutputisgreaterthanorequaltothelowalarmhigherlimit[lowalarm(T)+H+1].
ThisfunctionisshowninFigure64.
Figure63.
HighALARMHysteresisFigure64.
LowALARMHysteresis7.
3.
9.
2AVDDAlarmThedevicefeaturesahighandalowalarmontheanalogvoltagesupply,AVDD.
Unliketheinputsignalalarm,theAVDDalarmhasfixedtrippointsthataresetbydesign.
Thedevicefeaturesaninternalanalogcomparatorthatconstantlymonitorstheanalogsupplyagainstthehighandlowthresholdvoltages.
ThehighalarmissetifAVDDexceedsatypicalvalueof5.
3VandthelowalarmisassertedifAVDDdropsbelow4.
7V.
Thisfeatureisspeciallyusefulfordebuggingunusualdevicebehaviorcausedbyaglitchorbrown-outconditionontheanalogAVDDsupply.
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4DeviceFunctionalModesThedevicefeaturesthemultiSPIdigitalinterfaceforcommunicationanddatatransferbetweenthedeviceandthehostcontroller.
ThemultiSPIinterfacesupportsmanydatatransferprotocolsthatthehostusestoexchangedataandcommandswiththedevice.
ThehostcantransferdataintothedeviceusingoneofthestandardSPImodes.
However,thedevicecanbeconfiguredtooutputdatainanumberofwaystosuittheapplicationdemandsofthroughputandlatency.
Thedataoutputinthesemodescanbecontrolledeitherbythehostorthedevice,andthetimingcaneitherbesystemsynchronousorsourcesynchronous.
Fordetailedexplanationofthesupporteddatatransferprotocols,seetheDataTransferProtocolssection.
Thissectiondescribesthemaincomponentsofthedigitalinterfacemoduleaswellassupportedconfigurationsandprotocols.
AsshowninFigure65,theinterfacemoduleiscomprisedofshiftregisters(bothinputandoutput),configurationregisters,andaprotocolunit.
Duringanyparticulardataframe,dataaretransferredbothintoandoutofthedevice.
Asaresult,thehostalwaysperceivesthedeviceasa32-bitinput-outputshiftregister,asshowninFigure65.
Figure65.
DeviceInterfaceModuleThePinConfigurationandFunctionssectionprovidesdescriptionsoftheinterfacepins;theDataTransferFramesectiondetailsthefunctionsofshiftregisters,theSCLKcounter,andthecommandprocessor;theDataTransferProtocolssectiondetailssupportedprotocols;andtheRegisterMapssectionexplainstheconfigurationregistersandbitsettings.
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4.
1Host-to-DeviceConnectionTopologiesThemultiSPIinterfaceanddeviceconfigurationregistersoffergreatflexibilityinthewaysahostcontrollercanexchangedataorcommandswiththedevice.
Thissectiondescribeshowtoselectthehardwareconnectiontopologytomeetdifferentsystemrequirements.
7.
4.
1.
1SingleDevice:AllmultiSPIOptionsFigure66showsthepinconnectionbetweenahostcontrollerandastand-alonedevicetoexercisealloptionsprovidedbythemultiSPIinterface.
Figure66.
AllmultiSPIProtocolsPinConfiguration7.
4.
1.
2SingleDevice:StandardSPIInterfaceFigure67showstheminimumpininterfaceforapplicationsusingastandardSPIprotocol.
Figure67.
StandardSPIProtocolPinConfigurationTheCONVST/CS,SCLK,SDI,andSDO-0pinsconstituteastandardSPIportofthehostcontroller.
TheRSTpincanbetiedtoDVDD.
TheRVSpincanbemonitoredfortimingbenefits.
TheALARM/SDO-1/GPOpinmaynothaveanyexternalconnection.
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4.
1.
3MultipleDevices:Daisy-ChainTopologyAtypicalconnectiondiagramshowingmultipledevicesinadaisy-chaintopologyisshowninFigure68.
Figure68.
Daisy-ChainConnectionSchematicTheCONVST/CSandSCLKinputsofalldevicesareconnectedtogetherandcontrolledbyasingleCONVST/CSandSCLKpinofthehostcontroller,respectively.
TheSDIinputpinofthefirstdeviceinthechain(device1)isconnectedtotheSDO-xpinofthehostcontroller,theSDO-0outputpinofdevice1isconnectedtotheSDIinputpinofdevice2,andsoforth.
TheSDO-0outputpinofthelastdeviceinthechain(deviceN)isconnectedtotheSDIpinofthehostcontroller.
Tooperatemultipledevicesinadaisy-chaintopology,thehostcontrollermustprogramtheconfigurationregistersineachdevicewithidenticalvalues.
ThedevicesmustoperatewithasingleSDO-0output,usingtheexternalclockwithanyofthelegacy,SPI-compatibleprotocolsfordatareadanddatawriteoperations.
IntheSDO_CTL_REGregister,bits7-0mustbeprogrammedto00h.
Alldevicesinthedaisy-chaintopologysampletheiranaloginputsignalsontherisingedgeoftheCONVST/CSsignalandthedatatransferframestartswithafallingedgeofthesamesignal.
AtthelaunchedgeoftheSCLKsignal,everydeviceinthechainshiftsouttheMSBtotheSDO-0pin.
OneverySCLKcaptureedge,eachdeviceinthechainshiftsindatareceivedonitsSDIpinastheLSBbitoftheunifiedshiftregister;seeFigure65.
Therefore,inadaisy-chainconfiguration,thehostcontrollerreceivesthedataofdeviceN,followedbythedataofdeviceN-1,andsoforth(inMSB-firstfashion).
OntherisingedgeoftheCONVST/CSsignal,eachdevicedecodesthecontentsinitsunifiedandtakesappropriateaction.
ForNdevicesconnectedinadaisy-chaintopology,anoptimaldatatransferframemustcontain32*NSCLKcaptureedges(seeFigure69).
Ashorterdatatransferframecanresultinanerroneousdeviceconfigurationandmustbeavoided.
Foradatatransferframewith>32*NSCLKcaptureedges,thehostcontrollermustappropriatelyaligntheconfigurationdataforeachdevicebeforebringingCONVST/CShigh.
Theoverallthroughputofthesystemisproportionallyreducedwiththenumberofdevicesconnectedinadaisy-chaintopology.
37ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedDeviceFunctionalModes(continued)Atypicaltimingdiagramforthreedevicesconnectedinadaisy-chaintopologyandusingtheSPI-00-SprotocolisshowninFigure69.
Figure69.
ThreeDevicesinDaisy-ChainModeTimingDiagram7.
4.
2DeviceOperationalModesAsshowninFigure70,thedevicesupportsthreefunctionalstates:RESET,ACQ,andCONV.
ThedevicestateisdeterminedbythestatusoftheCONVST/CSandRSTcontrolsignalsprovidedbythehostcontroller.
Figure70.
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4.
2.
1RESETStateThedevicefeaturesanactive-lowRSTpinthatisanasynchronousdigitalinput.
InordertoenteraRESETstate,theRSTpinmustbepulledlowandkeptlowforthetwl_RSTduration(asspecifiedintheTimingRequirements:AsynchronousResettable).
Thedevicefeaturestwodifferenttypesofresetfunctions:anapplicationresetorapower-onreset(POR).
ThefunctionalityoftheRSTpinisdeterminedbythestateoftheRSTn_APPbitintheRST_PWRCTL_REGregister.
InordertoconfiguretheRSTpintoissueanapplicationreset,theRSTn_APPbitintheRST_PWRCTL_REGregistermustbeconfiguredto1b.
InthisRESETstate,allconfigurationregisters(seetheRegisterMapssection)areresettotheirdefaultvalues,theRVSpinsremainlow,andtheSDO-xpinsaretri-stated.
ThedefaultconfigurationfortheRSTpinistoissueapower-onresetwhenpulledtoalowlevel.
TheRSTn_APPbitissetto0binthisstate.
WhenaPORisissued,allinternalcircuitryofthedevice(includingthePGA,ADCdriver,andvoltagereference)arereset.
WhenthedevicecomesoutofthePORstate,thetD_RST_PORtimedurationmustbeallowedfor(seetheTimingRequirements:AsynchronousResettable)inorderfortheinternalcircuitrytoaccuratelysettle.
InordertoexitanyoftheRESETstates,theRSTpinmustbepulledhighwithCONVST/CSandSCLKheldlow.
AfteradelayoftD_RST_PORortD_RST_APP(seetheTimingRequirements:AsynchronousResettable),thedeviceentersACQstateandtheRVSpingoeshigh.
Tooperatethedeviceinanyoftheothertwostates(ACQorCONV),theRSTpinmustbeheldhigh.
WiththeRSTpinheldhigh,transitionsontheCONVST/CSpindeterminethefunctionalstateofthedevice.
AtypicalconversioncycleisillustratedinFigure1.
7.
4.
2.
2ACQStateInACQstate,thedeviceacquirestheanaloginputsignal.
ThedeviceentersACQstateonpower-up,afteranyasynchronousreset,oraftertheendofeveryconversion.
ThefallingedgeoftheRSTfallingedgetakesthedevicefromanACQstatetoaRESETstate.
ArisingedgeoftheCONVST/CSsignaltakesthedevicefromACQstatetoaCONVstate.
Thedeviceoffersalow-powerNAPmodetoreducepowerconsumptionintheACQstate;seetheNAPModesectionformoredetailsonNAPmode.
7.
4.
2.
3CONVStateThedevicemovesfromACQstatetoCONVstateontherisingedgeoftheCONVST/CSsignal.
TheconversionprocessusesaninternalclockandthedeviceignoresanyfurthertransitionsontheCONVST/CSsignaluntiltheongoingconversioniscomplete(thatis,duringthetimeintervaloftconv).
Attheendofconversion,thedeviceentersACQstate.
ThecycletimeforthedeviceisgivenbyEquation1:(1)NOTETheconversiontime,tconv,canvarywithinthespecifiedlimitsoftconv_minandtconv_max(asspecifiedintheTimingRequirements:ConversionCycletable).
Afterinitiatingaconversion,thehostcontrollermustmonitorforalow-to-hightransitionontheRVSpinorwaitforthetconv_maxdurationtoelapsebeforeinitiatinganewoperation(datatransferorconversion).
IfRVSisnotmonitored,substitutetconvinEquation1withtconv_max.
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5ProgrammingThedevicefeaturesnineconfigurationregisters(asdescribedintheRegisterMapssection)andsupportstwotypesofdatatransferoperations:datawrite(thehostconfiguresthedevice),anddataread(thehostreadsdatafromthedevice).
7.
5.
1DataTransferFrameAdatatransferframebetweenthedeviceandthehostcontrollerbeginsatthefallingedgeoftheCONVST/CSpinandendswhenthedevicestartsconversionatthesubsequentrisingedge.
ThehostcontrollercaninitiateadatatransferframebybringingtheCONVST/CSsignallow(asshowninFigure71)aftertheendoftheCONVphase,asdescribedintheCONVStatesection.
Figure71.
DataTransferFrame40ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedProgramming(continued)ForatypicaldatatransferframeF:1.
ThehostcontrollerpullsCONVST/CSlowtoinitiateadatatransferframe.
OnthefallingedgeoftheCONVST/CSsignal:–RVSgoeslow,indicatingthebeginningofthedatatransferframe.
–TheinternalSCLKcounterisresetto0.
–Thedevicetakescontrolofthedatabus.
AsillustratedinFigure71,thecontentsoftheoutputdatawordareloadedintothe32-bitoutputshiftregister(OSR).
–Theinternalconfigurationregisterisresetto0000h,correspondingtoaNOPcommand.
2.
Duringtheframe,thehostcontrollerprovidesclocksontheSCLKpin:–OneachSCLKcaptureedge,theSCLKcounterisincrementedandthedatabitreceivedontheSDIpinisshiftedintotheLSBoftheinputshiftregister.
–Oneachlaunchedgeoftheoutputclock(SCLKinthiscase),theMSBoftheoutputshiftregisterdataisshiftedoutontheselectedSDO-xpins.
–ThestatusoftheRVSpindependsontheoutputprotocolselection(seetheProtocolsforReadingFromtheDevicesection).
3.
ThehostcontrollerpullstheCONVST/CSpinhightoendthedatatransferframe.
OntherisingedgeofCONVST/CS:–TheSDO-xpinsgototri-state.
–AsillustratedinFigure71,thecontentsoftheinputshiftregisteraretransferredtothecommandprocessorfordecodingandfurtheraction.
–RVSoutputgoeslow,indicatingthebeginningofconversion.
AfterpullingCONVST/CShigh,thehostcontrollermustmonitorforalow-to-hightransitionontheRVSpinorwaitforthetconv_maxtime(seetheTimingRequirements:ConversionCycletable)toelapsebeforeinitiatinganewdatatransferframe.
AttheendofthedatatransferframeF:IftheSCLKcounter=32,thenthedevicetreatstheframeFasanoptimaldatatransferframeforanyreadorwriteoperation.
Attheendofanoptimaldatatransferframe,thecommandprocessortreatsthe32-bitcontentsoftheinputshiftregisterasavalidcommandword.
IftheSCLKcounteris32,thenthedevicetreatstheframeFasalongdatatransferframe.
Attheendofalongdatatransferframe,thecommandprocessortreatsthe32-bitcontentsoftheinputshiftregisterasavalidcommandword.
ThereisnorestrictiononthemaximumnumberofclocksthatcanbeprovidedwithinanydatatransferframeF.
However,whenthehostcontrollerprovidesalongdatatransferframe,thelast32bitsshiftedintothedevicepriortotheCONVST/CSrisingedgemustconstitutethedesiredcommand.
41ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedProgramming(continued)(1)isrealizedbyaddinga0attheMSBlocationfollowedbyan8-bitregisteraddressasdefinedinTable10.
Theforregister0x04his0x0-0000-0100b.
(2)AnHWORDcommandoperatesonasetof16bitsintheregistermapthatisusuallyidentifiedastworegistersofeightbitseach.
Forexample,thecommand11000_xx_istreatedthesameasthecommand11000_xx_forbits15:0oftheRST_PWRCTL_REGregister.
7.
5.
2InputCommandWordandRegisterWriteOperationAnydatawriteoperationtothedeviceisalwayssynchronoustotheexternalclockprovidedontheSCLKpin.
Thedeviceallowseitheronebyteortwobytes(equivalenttohalfaword)tobereadorwrittenduringanydeviceprogrammingoperation.
Table5liststheinputcommandssupportedbythedevice.
TheinputcommandsassociatedwithreadingorwritingtwobytesinasingleoperationaresuffixedasHWORD.
ForanyHWORDcommand,theLSBofthe9-bitaddressisalwaysignoredandconsideredas0b.
Forexample,regardlesswhetheraddress04hor05hisenteredforanyparticularHWORDcommand,thedevicealwaysexercisesthecommandonaddress04h.
Table5.
ListofInputCommandsOPCODEB[31:0]COMMANDACRONYMCOMMANDDESCRIPTION00000000_000000000_00000000_00000000NOPNooperation11000_xx__(1)CLEAR_HWORDCommandusedtoclearany(oragroupof)bitsofaregister.
Anybitmarked1inthedatafieldresultsinthatparticularbitofthespecifiedregisterbeingresetto0,leavingtheotherbitsunchanged.
Half-wordcommand(thatis,thecommandfunctionson16bitsatatime).
LSBofthe9-bitaddressisalwaysignoredandconsideredas0b.
(2)11001_xx__00000000_00000000READ_HWORDCommandusedtoperforma16-bitreadoperation.
Half-wordcommand(thatis,thedeviceoutputs16bitsofregisterdataatatime).
LSBofthe9-bitaddressisalwaysignoredandconsideredas0b.
Uponreceivingthiscommand,thedevicesendsout16bitsoftheregisterinthenextframe.
01001_xx__00000000_00000000READSameastheREAD_HWORDexceptthatonlyeightbitsoftheregister(byteread)arereturnedinthenextframe.
11010_00__WRITEHalf-wordwritecommand(twobytesofinputdataarewrittenintothespecifiedaddress).
LSBofthe9-bitaddressisalwaysignoredandconsideredas0b.
11010_01__Half-wordwritecommand.
LSBofthe9-bitaddressisalwaysignoredandconsideredas0b.
Withthiscommand,onlytheMSbyteofthe16-bitdatawordiswrittenatthespecifiedregisteraddress.
TheLSbyteisignored.
11010_10__Half-wordwritecommand.
LSBofthe9-bitaddressisalwaysignoredandconsideredas0b.
Withthiscommand,onlytheLSbyteofthe16-bitdatawordiswrittenatthespecifiedregisteraddress.
TheMSbyteisignored.
11011_xx__SET_HWORDCommandusedtosetany(oragroupof)bitsofaregister.
Anybitmarked1inthedatafieldresultsinthatparticularbitofthespecifiedregisterbeingsetto1,leavingtheotherbitsunchanged.
Half-wordcommand(thatis,thecommandfunctionson16bitsatatime).
LSBofthe9-bitaddressisalwaysignoredandconsideredas0b.
AllotherinputcommandcombinationsNOPNooperationAllinputcommands(includingtheCLEAR_HWORD,WRITE,andSET_HWORDcommandslistedinTable5)usedtoconfiguretheinternalregistersmustbe32bitslong.
IfanyofthesecommandsareprovidedinaparticulardataframeF,thatcommandgetsexecutedattherisingedgeoftheCONVST/CSsignal.
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5.
3OutputDataWordThedatareadfromthedevicecanbesynchronizedtotheexternalclockontheSCLKpinortoaninternalclockofthedevicebyprogrammingtheconfigurationregisters(seetheDataTransferProtocolssectionfordetails).
Inanydatatransferframe,thecontentsoftheinternaloutputshiftregisterareshiftedoutontheSDO-xpins.
Theoutputdataforanyframe(F+1)isdeterminedbythecommandissuedinframeFandthestatusofDATA_VAL[2:0]bits:IfDATA_VAL[2:0]bitsinDATAOUT_CTL_REGregisteraresetto1xxb,thentheoutputdatawordforframe(F+1)containsfixeddatapatternasdescribedintheDATAOUT_CTL_REGregister.
IfavalidREADcommandisissuedinframeF,theoutputdatawordforframe(F+1)contains8-bitregisterdata,followedby0's.
IfavalidREAD_HWORDcommandisissuedinframeF,theoutputdatawordforframe(F+1)contains16-bitregisterdata,followedby0's.
Forallothercombinations,theoutputdatawordforframe(F+1)containsthelatest18-bitconversionresult.
ProgramtheDATAOUT_CTL_REGregistertoappendvariousdataflagstotheconversionresult.
Thedataflagsareappendedasperfollowingsequence:1.
DEVICE_ADDR[3:0]bitsareappendediftheDEVICE_ADDR_INCLbitissetto12.
AVDDALARMFLAGSareappendediftheVDD_ACTIVE_ALARM_INCLbitissetto13.
INPUTALARMFLAGSareappendediftheIN_ACTIVE_ALARM_INCLbitissetto14.
ADCINPUTRANGEFLAGSareappendediftheRANGE_INCLbitissetto15.
PARITYbitsareappendedifthePAR_ENbitissetto16.
Alltheremainingbitsinthe32-bitoutputdatawordaresetto0.
Table6showstheoutputdatawordwithalldataflagsenabled.
Table6.
OutputDataWordWithAllDataFlagsEnabledDEVICE_ADDR_INCL=1b,VDD_ACTIVE_ALARM_INCL=1b,IN_ACTIVE_ALARM_INCL=1b,RANGE_INCL=1b,andPAR_EN=1bD[31:14]D[13:10]D[9:8]D[7:6]D[5:2]D[1:0]Notrailing0'sConversionresultDeviceaddressAVDDalarmflagsInputalarmflagsADCinputrangeParitybitsNotrailing0'sTable7showsoutputdatawordwithonlysomeofthedataflagsenabled.
Table7.
OutputDataWordWithOnlySomeDataFlagsEnabledDEVICE_ADDR_INCL=0b,VDD_ACTIVE_ALARM_INCL=1b,IN_ACTIVE_ALARM_INCL=0b,RANGE_INCL=1b,andPAR_EN=1bD[31:14]D[13:12]D[11:8]D[7:6]D[5:0]ConversionresultAVDDalarmflagsADCinputrangeParitybits000000b43ADS8691,ADS8695,ADS8699www.
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5.
4DataTransferProtocolsThedevicefeaturesamultiSPIinterfacethatallowsthehostcontrollertooperateatslowerSCLKspeedsandstillachievetherequiredcycletimewithafasterresponsetime.
Foranydatawriteoperation,thehostcontrollercanuseanyofthefourlegacy,SPI-compatibleprotocolstoconfigurethedevice,asdescribedintheProtocolsforConfiguringtheDevicesection.
Foranydatareadoperationfromthedevice,themultiSPIinterfacemoduleoffersthefollowingoptions:–Legacy,SPI-compatibleprotocolwithasingleSDO-x(seetheLegacy,SPI-Compatible(SYS-xy-S)ProtocolswithaSingleSDO-xsection)–Legacy,SPI-compatibleprotocolwithdualSDO-x(seetheLegacy,SPI-Compatible(SYS-xy-S)ProtocolswithDualSDO-xsection)–ADCmasterclockorsource-synchronous(SRC)protocolfordatatransfer(seetheSource-Synchronous(SRC)Protocolssection)7.
5.
4.
1ProtocolsforConfiguringtheDeviceAsdescribedinTable8,thehostcontrollercanuseanyofthefourlegacy,SPI-compatibleprotocols(SPI-00-S,SPI-01-S,SPI-10-S,orSPI-11-S)towritedataintothedevice.
Table8.
SPIProtocolsforConfiguringtheDevicePROTOCOLSCLKPOLARITY(AtCSFallingEdge)SCLKPHASE(CaptureEdge)SDI_CTL_REGSDO_CTL_REGDIAGRAMSPI-00-SLowRising00h00hFigure72SPI-01-SLowFalling01h00hFigure72SPI-10-SHighFalling02h00hFigure73SPI-11-SHighRising03h00hFigure73Onpower-uporaftercomingoutofanyasynchronousreset,thedevicesupportstheSPI-00-Sprotocolfordatareadanddatawriteoperations.
ToselectadifferentSPI-compatibleprotocol,programtheSDI_MODE[1:0]bitsintheSDI_CNTL_REGregister.
ThisfirstwriteoperationmustadheretotheSPI-00-Sprotocol.
Anysubsequentdatatransferframesmustadheretothenewly-selectedprotocol.
TheSPIprotocolselectedbytheconfigurationoftheSDI_MODE[1:0]isapplicabletobothreadandwriteoperations.
Figure72andFigure73detailthefourprotocolsusinganoptimaldataframe;seetheTimingRequirements:SPI-CompatibleSerialInterfacetableforassociatedtimingparameters.
NOTEAsexplainedintheDataTransferFramesection,avalidwriteoperationtothedevicerequiresaminimumof32SCLKstobeprovidedwithinadatatransferframe.
Figure72.
StandardSPITimingProtocol(CPHA=0,32SCLKCycles)Figure73.
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5.
4.
2ProtocolsforReadingFromtheDeviceTheprotocolsforthedatareadoperationcanbebroadlyclassifiedintothreecategories:1.
Legacy,SPI-compatibleprotocolswithasingleSDO-x2.
Legacy,SPI-compatibleprotocolswithdualSDO-x3.
ADCmasterclockorsource-synchronous(SRC)protocolfordatatransfer7.
5.
4.
2.
1Legacy,SPI-Compatible(SYS-xy-S)ProtocolswithaSingleSDO-xAsshowninTable9,thehostcontrollercanuseanyofthefourlegacy,SPI-compatibleprotocols(SPI-00-S,SPI-01-S,SPI-10-S,orSPI-11-S)toreaddatafromthedevice.
Table9.
SPIProtocolsforReadingFromtheDevicePROTOCOLSCLKPOLARITY(AtCSFallingEdge)SCLKPHASE(CaptureEdge)MSBBITLAUNCHEDGESDI_CTL_REGSDO_CTL_REGDIAGRAMSPI-00-SLowRisingCSfalling00h00hFigure74SPI-01-SLowFalling1stSCLKrising01h00hFigure74SPI-10-SHighFallingCSfalling02h00hFigure75SPI-11-SHighRising1stSCLKfalling03h00hFigure75Onpower-uporaftercomingoutofanyasynchronousreset,thedevicesupportstheSPI-00-Sprotocolfordatareadanddatawriteoperations.
ToselectadifferentSPI-compatibleprotocolforboththedatatransferoperations:1.
ProgramtheSDI_MODE[1:0]bitsintheSDI_CTL_REGregister.
ThisfirstwriteoperationmustadheretotheSPI-00-Sprotocol.
Anysubsequentdatatransferframesmustadheretothenewly-selectedprotocol.
2.
SettheSDO_MODE[1:0]bits=00bintheSDO_CTL_REGregister.
NOTETheSPItransferprotocolselectedbyconfiguringtheSDI_MODE[1:0]bitsintheSDI_CTL_REGregisterdeterminesthedatatransferprotocolforbothwriteandreadoperations.
EitherdatacanbereadfromthedeviceusingtheselectedSPIprotocolbyconfiguringtheSDO_MODE[1:0]bits=00bintheSDO_CTL_REGregister,oroneoftheSRCprotocolscanbeselectedfordataread,asexplainedintheSource-Synchronous(SRC)Protocolssection.
WhenusinganyoftheSPI-compatibleprotocols,theRVSoutputremainslowthroughoutthedatatransferframe;seetheTimingRequirements:SPI-CompatibleSerialInterfacetableforassociatedtimingparameters.
Figure74andFigure75explainthedetailsofthefourprotocols.
AsexplainedintheDataTransferFramesection,thehostcontrollercanuseashortdatatransferframetoreadonlytherequirednumberofMSBbitsfromthe32-bitoutputdataword.
IfthehostcontrollerusesalongdatatransferframewithSDO_CNTL_REG[7:0]=00h,thenthedeviceexhibitsdaisy-chainoperation(seetheMultipleDevices:Daisy-ChainTopologysection).
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StandardSPITimingProtocol(CPHA=0,SingleSDO-x)Figure75.
StandardSPITimingProtocol(CPHA=1,SingleSDO-x)7.
5.
4.
2.
2Legacy,SPI-Compatible(SYS-xy-S)ProtocolswithDualSDO-xThedeviceprovidesanoptiontoincreasetheSDO-xbuswidthfromonebit(default,singleSDO-x)totwobits(dualSDO-x)whenoperatingwithanyofthedatatransferprotocols.
InordertooperatethedeviceindualSDOmode,theSDO1_CONFIG[1:0]bitsintheSDO_CTL_REGregistermustbesetto11b.
Inthismode,theALARM/SDO-1/GPOpinfunctionsasSDO-1.
IndualSDOmode,twobitsofdataarelaunchedonthetwoSDO-xpins(SDO-0andSDO-1)oneverySCLKlaunchedge,asshowninFigure76andFigure77.
Figure76.
StandardSPITimingProtocol(CPHA=0,DualSDO-x)Figure77.
StandardSPITimingProtocol(CPHA=1,DualSDO-x)NOTEForanyparticularSPIprotocol,thedevicefollowsthesametimingspecificationsforsingleanddualSDOmodes.
TheonlydifferenceisthatthedevicerequireshalfasmanySCLKcyclestooutputthesamenumberofbitswheninsingleSDOmode,thusreducingtheminimumrequiredSCLKfrequencyforacertainsamplingrateoftheADC.
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5.
4.
2.
3Source-Synchronous(SRC)ProtocolsThemultiSPIinterfacesupportsanADCmasterclockorsource-synchronousmodeofdatatransferbetweenthedeviceandhostcontroller.
Inthismode,thedeviceprovidesanoutputclockthatissynchronouswiththeoutputdata.
Furthermore,thehostcontrollercanalsoselecttheoutputclocksourceanddatabuswidthoptionsinthismodeofoperation.
InallSRCmodesofoperation,theRVSpinprovidestheoutputclock,synchronoustothedevicedataoutput.
TheSRCprotocolallowstheclocksource(internalorexternal)andthewidthoftheoutputbustobeconfigured,similartotheSPIprotocols.
7.
5.
4.
2.
3.
1OutputClockSourceOptionsThedeviceallowstheoutputclockontheRVSpintobesynchronoustoeithertheexternalclockprovidedontheSCLKpinortotheinternalclockofthedevice.
ThisselectionisdonebyconfiguringtheSSYNC_CLKbit,asexplainedintheSDO_CTL_REGregister.
ThetimingdiagramandspecificationsforoperatingthedevicewithanSRCprotocolinexternalCLKmodeareprovidedinFigure7andtheTimingRequirements:Source-SynchronousSerialInterface(ExternalClock)table.
ThetimingdiagramandspecificationsforoperatingthedevicewithanSRCprotocolininternalCLKmodeareprovidedinFigure8andtheTimingRequirements:Source-SynchronousSerialInterface(InternalClock)table.
7.
5.
4.
2.
3.
2OutputBusWidthOptionsThedeviceprovidesanoptiontoincreasetheSDO-xbuswidthfromonebit(default,singleSDO-x)totwobits(dualSDO-x)whenoperatingwithanyoftheSRCprotocols.
InordertooperatethedeviceindualSDOmode,theSDO1_CONFIG[1:0]bitsintheSDO_CTL_REGregistermustbesetto11b.
Inthismode,theALARM/SDO-1/GPOpinfunctionsasSDO-1.
NOTEForanyparticularSRCprotocol,thedevicefollowsthesametimingspecificationsforsingleanddualSDOmodes.
TheonlydifferenceisthatthedevicerequireshalfasmanyclockcyclestooutputthesamenumberofbitswheninsingleSDOmode,thusreducingtheminimumrequiredclockfrequencyforacertainsamplingrateoftheADC.
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6RegisterMaps7.
6.
1DeviceConfigurationandRegisterMapsThedevicefeaturesnineconfigurationregisters,mappedasdescribedinTable10.
Eachconfigurationregistersiscomprisedoffourregisters,eachcontainingadatabyte.
Table10.
ConfigurationRegistersMappingADDRESSREGISTERNAMEREGISTERFUNCTION00hDEVICE_ID_REGDeviceIDregister04hRST_PWRCTL_REGResetandpowercontrolregister08hSDI_CTL_REGSDIdatainputcontrolregister0ChSDO_CTL_REGSDO-xdatainputcontrolregister10hDATAOUT_CTL_REGOutputdatacontrolregister14hRANGE_SEL_REGInputrangeselectioncontrolregister20hALARM_REGALARMoutputregister24hALARM_H_TH_REGALARMhighthresholdandhysteresisregister28hALARM_L_TH_REGALARMlowthresholdregister7.
6.
1.
1DEVICE_ID_REGRegister(address=00h)Thisregistercontainstheuniqueidentificationnumbersassociatedtoadevicethatisusedinadaisy-chainconfigurationinvolvingmultipledevices.
Figure78.
DEVICE_ID_REGRegister31302928272625242322212019181716ReservedReservedDEVICE_ADDR[3:0]R-00hR-0000bR/W-0000b1514131211109876543210ReservedR-0000hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;LEGEND:-,-=Conditionafterpower-onresetAddressforbits7-0=00hAddressforbits15-8=01hAddressforbits23-16=02hAddressforbits31-24=03h(1)Thesebitsareusefulindaisy-chainmode.
Table11.
DEVICE_ID_REGRegisterFieldDescriptionsBitFieldTypeResetDescription31-24ReservedR00hReserved.
Readsreturn00h.
23-20ReservedR0000bReserved.
Readsreturn0000b.
19-16DEVICE_ADDR[3:0](1)R0000bThesebitscanbeusedtoidentifyupto16differentdevicesinasystem.
15-0ReservedR0000hReserved.
Readsreturn0000h.
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6.
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2RST_PWRCTL_REGRegister(address=04h)Thisregistercontrolstheresetandpower-downfeaturesofferedbytheconverter.
AnywriteoperationtotheRST_PWRCTL_REGregistermustbeprecededbyawriteoperationwiththeregisteraddresssetto05handtheregisterdatasetto69h.
Figure79.
RST_PWRCTL_REGRegister31302928272625242322212019181716ReservedR-0000h1514131211109876543210WKEY[7:0]ReservedVDD_AL_DISIN_AL_DISReservedRSTn_APPNAP_ENPWRDNR/W-00hR-00bR/W-0bR/W-0bR-0bR/W-bR/W-bR/W-0bLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;LEGEND:-,-=Conditionafterpower-onresetAddressforbits7-0=04hAddressforbits15-8=05hAddressforbits23-16=06hAddressforbits31-24=07h(1)SettingthisbitforcestheRSTpintofunctionasanapplicationresetuntilthenextpowercycle.
(2)SeetheElectricalCharacteristicstablefordetailsonthelatencyencounteredwhenenteringandexitingtheassociatedlow-powermode.
Table12.
RST_PWRCTL_REGRegisterFieldDescriptionsBitFieldTypeResetDescription31-16ReservedR0000hReserved.
Readsreturn0000h.
15-8WKEY[7:0]R/W00hThisvaluefunctionsasaprotectionkeytoenablewritestobits5-0.
BitsarewrittenonlyifWKEYissetto69hfirst.
7-6ReservedR00bReserved.
Readsreturn00b5VDD_AL_DISR/W0b0b=VDDalarmisenabled1b=VDDalarmisdisabled4IN_AL_DISR/W0b0b=Inputalarmisenabled1b=Inputalarmisdisabled3ReservedR0bReserved.
Readsreturn0h.
2RSTn_APP(1)R/W0b0b=RSTpinfunctionsasaPORclassreset(causesfulldeviceinitialization)1b=RSTpinfunctionsasanapplicationreset(onlyuser-programmedmodesarecleared)1NAP_EN(2)R/W0b0b=DisablestheNAPmodeoftheconverter1b=EnablestheconvertertoenterNAPmodeifCONVST/CSisheldhighafterthecurrentconversioncompletes0PWRDN(2)R/W0b0b=Putstheconverterintoactivemode1b=Putstheconverterintopower-downmode49ADS8691,ADS8695,ADS8699www.
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6.
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3SDI_CTL_REGRegister(address=08h)Thisregisterconfigurestheprotocolusedforwritingdatatothedevice.
Figure80.
SDI_CTL_REGRegister31302928272625242322212019181716ReservedR-0000h1514131211109876543210ReservedReservedSDI_MODE[1:0]R-00hR-000000bR/W-bLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;LEGEND:-,-=Conditionafterpower-onresetAddressforbits7-0=08hAddressforbits15-8=09hAddressforbits23-16=0AhAddressforbits31-24=0BhTable13.
SDI_CTL_REGRegisterFieldDescriptionsBitFieldTypeResetDescription31-16ReservedR0000hReserved.
Readsreturn0000h.
15-8ReservedR00hReserved.
Readsreturn00h.
7-2ReservedR000000bReserved.
Readsreturn000000b.
1-0SDI_MODE[1:0]R/W00bThesebitsselecttheprotocolforreadingfromorwritingtothedevice.
00b=StandardSPIwithCPOL=0andCPHASE=001b=StandardSPIwithCPOL=0andCPHASE=110b=StandardSPIwithCPOL=1andCPHASE=011b=StandardSPIwithCPOL=1andCPHASE=150ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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4SDO_CTL_REGRegister(address=0Ch)ThisregistercontrolsthedataprotocolusedtotransmitdataoutfromtheSDO-xpinsofthedevice.
Figure81.
SDO_CTL_REGRegister31302928272625242322212019181716ReservedR-0000h1514131211109876543210ReservedGPO_VALReservedSDO1_CONFIG[1:0]ReservedSSYNC_CLKReservedSDO_MODE[1:0]R-000bR/W-0bR-00bR/W-00bR-0bR/W-bR-0hR/W-bLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;LEGEND:-,-=Conditionafterpower-onresetAddressforbits7-0=0ChAddressforbits15-8=0DhAddressforbits23-16=0EhAddressforbits31-24=0Fh(1)ThisbittakeseffectonlyintheADCmasterclockorsource-synchronousmodeofoperation.
Table14.
SDO_CTL_REGRegisterFieldDescriptionsBitFieldTypeResetDescription31-16ReservedR0000hReserved.
Readsreturn0h.
15-13ReservedR000bReserved.
Readsreturn000b.
12GPO_VALR/W0b1-bitvaluefortheoutputontheGPOpin.
11-10ReservedR00bReserved.
Readsreturn00b.
9-8SDO1_CONFIG[1:0]R/W00bTwobitsareusedtoconfigureALARM/SDO-1/GPO:00b=SDO-1isalwaystri-stated;1-bitSDOmode01b=SDO-1functionsasALARM;1-bitSDOmode10b=SDO-1functionsasGPO;1-bitSDOmode11b=SDO-1combinedwithSDO-0offersa2-bitSDOmode7ReservedR0bReserved.
Readsreturn0b.
6SSYNC_CLK(1)R/W0bThisbitcontrolsthesourceoftheclockselectedforsource-synchronoustransmission.
0b=ExternalSCLK(nodivision)1b=Internalclock(nodivision)5-2ReservedR0000bReserved.
Readsreturn0000b.
1-0SDO_MODE[1:0]R/W00bThesebitscontrolthedataoutputmodesofthedevice.
0xb=SDOmodefollowsthesameSPIprotocolasthatusedforSDI;seetheSDI_CTL_REGregister10b=Invalidconfiguration11b=SDOmodefollowstheADCmasterclockorsource-synchronousprotocol51ADS8691,ADS8695,ADS8699www.
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6.
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5DATAOUT_CTL_REGRegister(address=10h)Thisregistercontrolsthedataoutputbythedevice.
Figure82.
DATAOUT_CTL_REGRegister31302928272625242322212019181716ReservedR-0000h1514131211109876543210ReservedDEVICE_ADDR_INCLVDD_ACTIVE_ALARM_INCL[1:0]IN_ACTIVE_ALARM_INCL[1:0]ReservedRANGE_INCLReservedPAR_ENDATA_VAL[2:0]R-0bR/W-0bR/W-0bR/W-0bR-0bR/W-0bR-0000bR/W-bR/W-000bLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;LEGEND:-,-=Conditionafterpower-onresetAddressforbits7-0=10hAddressforbits15-8=11hAddressforbits23-16=12hAddressforbits31-24=13h(1)Settingthisbitincreasesthelengthoftheoutputdatabytwobits.
Table15.
DATAOUT_CTL_REGRegisterFieldDescriptionsBitFieldTypeResetDescription31-16ReservedR0000hReserved.
Readsreturn0000h.
15ReservedR0bReserved.
Readsreturn0b.
14DEVICE_ADDR_INCLR/W0bControltoincludethe4-bitDEVICE_ADDRregistervalueintheSDO-xoutputbitstream.
0b=Donotincludetheregistervalue1b=Includetheregistervalue13-12VDD_ACTIVE_ALARM_INCL[1:0]R/W00bControltoincludetheactiveVDDALARMflagsintheSDO-xoutputbitstream.
00b=Donotinclude01b=IncludeACTIVE_VDD_H_FLAG10b=IncludeACTIVE_VDD_L_FLAG11b=Includebothflags11-10IN_ACTIVE_ALARM_INCL[1:0]R/W00bControltoincludetheactiveinputALARMflagsintheSDO-xoutputbitstream.
00b=Donotinclude01b=IncludeACTIVE_IN_H_FLAG10b=IncludeACTIVE_IN_L_FLAG11b=Includebothflags9ReservedR0bReserved.
Readsreturn0h.
8RANGE_INCLR/W0bControltoincludethe4-bitinputrangesettingintheSDO-xoutputbitstream.
0b=Donotincludetherangeconfigurationregistervalue1b=Includetherangeconfigurationregistervalue7-4ReservedR0000bReserved.
Readsreturn0000b.
3PAR_EN(1)R/W0b0b=Outputdatadoesnotcontainparityinformation1b=Twoparitybits(ADCoutputandoutputdataframe)areappendedtotheLSBsoftheoutputdataTheADCoutputparitybitreflectsanevenparityfortheADCoutputbitsonly.
Theoutputdataframeparitybitreflectsanevenparitysignaturefortheentireoutputdataframe,includingtheADCoutputbitsandanyinternalflagsorregistersettings.
2-0DATA_VAL[2:0]R/W000bThesebitscontrolthedatavalueoutputbytheconverter.
0xxb=Valueoutputistheconversiondata100b=Valueoutputisall0's101b=Valueoutputisall1's110b=Valueoutputisalternating0'sand1's111b=Valueoutputisalternating00'sand11's52ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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6.
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6RANGE_SEL_REGRegister(address=14h)Thisregistercontrolstheconfigurationoftheinternalreferenceandinputvoltagerangesfortheconverter.
Figure83.
RANGE_SEL_REGRegister31302928272625242322212019181716ReservedR-0000h1514131211109876543210ReservedReservedINTREF_DISReservedRANGE_SEL[3:0]R-00hR-0bR/W-0bR-00bR/W-bLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;LEGEND:-,-=Conditionafterpower-onresetAddressforbits7-0=14hAddressforbits15-8=15hAddressforbits23-16=16hAddressforbits31-24=17hTable16.
RANGE_SEL_REGRegisterFieldDescriptionsBitFieldTypeResetDescription31-16ReservedR0000hReserved.
Readsreturn0000h.
15-8ReservedR00hReserved.
Readsreturn00h.
7ReservedR0bReserved.
Readsreturn0b.
6INTREF_DISR/W0bControltodisabletheADCinternalreference.
0b=Internalreferenceisenabled1b=Internalreferenceisdisabled5-4ReservedR00bReserved.
Readsreturn00b.
3-0RANGE_SEL[3:0]R/W0000bThesebitscomprisethe4-bitregisterthatselectsthenineinputrangesoftheADC.
0000b=±3*VREF0001b=±2.
5*VREF0010b=±1.
5*VREF0011b=±1.
25*VREF0100b=±0.
625*VREF1000b=3*VREF1001b=2.
5*VREF1010b=1.
5*VREF1011b=1.
25*VREF53ADS8691,ADS8695,ADS8699www.
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6.
1.
7ALARM_REGRegister(address=20h)Thisregistercontainstheoutputalarmflags(activeandtripped)fortheinputandAVDDalarm.
Figure84.
ALARM_REGRegister31302928272625242322212019181716ReservedR-0000h1514131211109876543210ACTIVE_VDD_L_FLAGACTIVE_VDD_H_FLAGReservedACTIVE_IN_L_FLAGACTIVE_IN_H_FLAGReservedTRP_VDD_L_FLAGTRP_VDD_H_FLAGTRP_IN_L_FLAGTRP_IN_H_FLAGReservedOVW_ALARMR-0bR-0bR-00bR-0bR-0bR-00bR-0bR-0bR-0bR-0bR-000bR-0bLEGEND:R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;-,-=Conditionafterpower-onresetAddressforbits7-0=20hAddressforbits15-8=21hAddressforbits23-16=22hAddressforbits31-24=23hTable17.
ALARM_REGRegisterFieldDescriptionsBitFieldTypeResetDescription31-16ReservedR0000hReserved.
Readsreturn0000h.
15ACTIVE_VDD_L_FLAGR0bActiveALARMoutputflagforlowAVDDvoltage.
0b=NoALARMcondition1b=ALARMconditionexists14ACTIVE_VDD_H_FLAGR0bActiveALARMoutputflagforhighAVDDvoltage.
0b=NoALARMcondition1b=ALARMconditionexists13-12ReservedR00bReserved.
Readsreturn00b.
11ACTIVE_IN_L_FLAGR0bActiveALARMoutputflagforhighinputvoltage.
0b=NoALARMcondition1b=ALARMconditionexists10ACTIVE_IN_H_FLAGR0bActiveALARMoutputflagforlowinputvoltage.
0b=NoALARMcondition1b=ALARMconditionexists9-8ReservedR00bReserved.
Readsreturn00b.
7TRP_VDD_L_FLAGR0bTrippedALARMoutputflagforlowAVDDvoltage.
0b=NoALARMcondition1b=ALARMconditionexists6TRP_VDD_H_FLAGR0bTrippedALARMoutputflagforhighAVDDvoltage.
0b=NoALARMcondition1b=ALARMconditionexists5TRP_IN_L_FLAGR0bTrippedALARMoutputflagforhighinputvoltage.
0b=NoALARMcondition1b=ALARMconditionexists4TRP_IN_H_FLAGR0bTrippedALARMoutputflagforlowinputvoltage.
0b=NoALARMcondition1b=ALARMconditionexists3-1ReservedR000bReserved.
Readsreturn000b.
0OVW_ALARMR0bLogicalORoutputsalltrippedALARMflags.
0b=NoALARMcondition1b=ALARMconditionexists54ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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6.
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8ALARM_H_TH_REGRegister(address=24h)Thisregistercontrolsthehysteresisandhighthresholdfortheinputalarm.
Figure85.
ALARM_H_TH_REGRegister31302928272625242322212019181716INP_ALRM_HYST[7:0]ReservedR/W-00hR-00h1514131211109876543210INP_ALRM_HIGH_TH[15:0]R/W-FFFFhLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;LEGEND:-,-=Conditionafterpower-onresetAddressforbits7-0=24hAddressforbits15-8=25hAddressforbits23-16=26hAddressforbits31-24=27hTable18.
ALARM_H_TH_REGRegisterFieldDescriptionsBitFieldTypeResetDescription31-24INP_ALRM_HYST[7:0]R/W00hINP_ALRM_HYST[7:2]:6-bithysteresisvaluefortheinputALARM.
INP_ALRM_HYST[1:0]mustbesetto00b.
23-16ReservedR00hReserved.
Readsreturn00h.
15-0INP_ALRM_HIGH_TH[15:0]R/WFFFFhThresholdforcomparisonisINP_ALRM_HIGH_TH[15:0]appendedwith00b.
7.
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9ALARM_L_TH_REGRegister(address=28h)Thisregistercontrolsthelowthresholdfortheinputalarm.
Figure86.
ALARM_L_TH_REGRegister31302928272625242322212019181716ReservedR-0000h1514131211109876543210INP_ALRM_LOW_TH[15:0]R/W-0000hLEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset;-0,-1=Conditionafterapplicationreset;LEGEND:-,-=Conditionafterpower-onresetAddressforbits7-0=28hAddressforbits15-8=29hAddressforbits23-16=2AhAddressforbits31-24=2BhTable19.
ALARM_L_TH_REGRegisterFieldDescriptionsBitFieldTypeResetDescription32:16ReservedR0000hReserved.
Readsreturn0000h.
15-0INP_ALRM_LOW_TH[15:0]R/W0000hThresholdforcomparisonisINP_ALRM_LOW_TH[15:0]appendedwith00b.
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TI'scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.
Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.
8.
1ApplicationInformationTheADS869xisafully-integrateddataacquisition(DAQ)systembasedona18-bitsuccessiveapproximation(SAR)analog-to-digitalconverter(ADC).
Thedeviceincludesanintegratedanalogfront-end(AFE)circuittodrivetheinputsoftheADCandanintegratedprecisionreferencewithabuffer.
Assuch,thisdevicedoesnotrequireanyadditionalexternalcircuitsfordrivingthereferenceoranaloginputpinsoftheADC.
8.
2TypicalApplicationNOTE:ThepotentialdifferencebetweenIGNDandGNDcanbeashighasthebarrierbreakdownvoltage(oftenthousandsofvolts).
Figure87.
18-BitIsolatedDAQSystemforHighCommon-ModeRejection8.
2.
1DesignRequirementsDesigna18-bitDAQsystemforprocessinginputsignalsupto±12Vsuperimposedonlargedcoraccommon-modeoffsetsrelativetothegroundpotentialofthesystemmainpowersupply.
Thespecificperformancerequirementsareasfollows:Inputsignal:±12-Vamplitudesignalofa1-kHzfrequencysuperimposedona±75-Vcommon-modewithfrequencybetweendcand15kHzCMRR>100dBoverstipulatedcommon-modefrequencyrangeSNR>91dBTHD1maintainslineregulationattheLDOoutputsSchottkyrectifiersforminimalforwardvoltagedropSmoothingcapacitorforsufficientlylowrippleattheLDOinputTheTPS7A4901LDOsforanultra-lownoisecontributionrelativetotheADS869xandhighPSRRoverawidefrequencyrangetoattenuateoutputrippletolevelsbelowtheLDOoutputnoiselevelWithregardtothedigitalisolator,theISO7640FMisrecommendedforthefollowingreasons:Supports>a50-MHzSCLKandtherequiredlogiclevelsforoperatingtheADS869xatthefullthroughputQuad-channeldevicethatfacilitatesexcellentdelay-matchingbetweencriticalinterfacesignalsforreliableoperationathighspeed57ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporatedTypicalApplication(continued)8.
2.
3ApplicationCurvesfSAMPLE=1MSPS,VIN=±12V,fIN=1kHz,VCM=50VDC,SINAD=92.
2dB,THD=–109dBFigure89.
FFTPlotWithaDCCommon-Modeat1MSPSfSAMPLE=1Msps,VIN=±12V,fIN=1kHz,VCM=155VPP,SINAD=91.
5dB,THD=–109dBFigure90.
FFTPlotWithanACCommon-Modeat1MSPSfSAMPLE=500kSPS,VIN=±12V,fIN=1kHz,VCM=50VDC,SINAD=92.
3dB,THD=–109dBFigure91.
FFTPlotWithaDCCommon-Modeat500kSPSfSAMPLE=500kSPS,VIN=±12V,fIN=1kHz,VCM=155VPP,SINAD=91.
9dB,THD=–109dBFigure92.
FFTPlotWithanACCommon-Modeat500kSPSfSAMPLE=100kSPS,VIN=±12V,fIN=1kHz,VCM=50VDC,SINAD=91.
9dB,THD=–109dBFigure93.
FFTPlotWithaDCCommon-Modeat100kSPSfSAMPLE=100kSPS,VIN=±12V,fIN=1kHz,VCM=155VPP,SINAD=91.
4dB,THD=–109dBFigure94.
FFTPlotWithanACCommon-Modeat100kSPS58ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedTypicalApplication(continued)Figure95.
Common-ModeRejectionRatiovsFrequency59ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018Copyright2016–2018,TexasInstrumentsIncorporated9PowerSupplyRecommendationsThedeviceusestwoseparatepowersupplies:AVDDandDVDD.
TheinternalcircuitsofthedeviceoperateonAVDDandDVDDisusedforthedigitalinterface.
AVDDandDVDDcanbeindependentlysettoanyvaluewithinthepermissiblerange.
9.
1PowerSupplyDecouplingTheAVDDsupplypinsmustbedecoupledwithAGNDbyusingaminimum10-Fand1-Fcapacitoroneachsupply.
Placethe1-Fcapacitorasclosetothesupplypinsaspossible.
Placeaminimum10-FdecouplingcapacitorveryclosetotheDVDDsupplytoprovidethehigh-frequencydigitalswitchingcurrent.
Theeffectofusingthedecouplingcapacitorisillustratedinthedifferencebetweenthepower-supplyrejectionratio(PSRR)performanceofthedevice.
Figure96showsthePSRRofthedevicewithoutusingadecouplingcapacitor.
ThePSRRimproveswhenthedecouplingcapacitorsareused,asshowninFigure97.
Figure96.
PSRRWithoutaDecouplingCapacitorFigure97.
PSRRWithaDecouplingCapacitor9.
2PowerSavingInnormalmodeofoperation,thedevicedoesnotpowerdownbetweenconversions,andthereforeachieveshighthroughput.
However,thedeviceofferstwoprogrammablelow-powermodes:NAPandpower-down(PD)toreducepowerconsumptionwhenthedeviceisoperatedatlowerthroughputrates.
9.
2.
1NAPModeInNAPmode,theinternalblocksofthedeviceareplacedintoalow-powermodetoreducetheoverallpowerconsumptionofthedeviceintheACQstate.
ToenableNAPmode:Write69htoregisteraddress05htounlocktheRST_PWRCTL_REGregister.
TheNAP_ENbitintheRST_PWRCTL_REGregistermustbesetto1b.
TheCONVST/CSpinmustbekepthighattheendoftheconversionprocess.
ThedevicethenentersNAPmodeattheendofconversionandremainsinNAPmodeaslongastheCONVST/CSpinisheldhigh.
AfallingedgeontheCONVST/CSbringsthedeviceoutofNAPmode;however,thehostcontrollercaninitiateanewconversion(CONVST/CSrisingedge)onlyafterthetNAP_WKUPtimehaselapsed(seetheTimingRequirements:AsynchronousResettable).
60ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cnCopyright2016–2018,TexasInstrumentsIncorporatedPowerSaving(continued)9.
2.
2Power-Down(PD)ModeThedevicealsofeaturesadeeppower-downmode(PD)toreducethepowerconsumptionatverylowthroughputrates.
ThefollowingstepsmustbetakentoenterPDmode:1.
Write69htoregisteraddress05htounlocktheRST_PWRCTL_REGregister.
2.
SetthePWRDNbitintheRST_PWRCTL_REGregisterto1b.
ThedeviceentersPDmodeontherisingedgeoftheCONVST/CSsignal.
InPDmode,allanalogblockswithinthedevicearepowereddown;however,theinterfaceremainsactiveandtheregistercontentsarealsoretained.
TheRVSpinishigh,indicatingthatthedeviceisreadytoreceivethenextcommand.
InordertoexitPDmode:1.
ClearthePWRDNbitintheRST_PWRCTL_REGregisterto0b.
2.
TheRVSpingoeshigh,indicatingthatthedevicehasstartedcomingoutofPDmode.
However,thehostcontrollermustwaitforthetPWRUPtime(seetheTimingRequirements:AsynchronousResettable)toelapsebeforeinitiatinganewconversion.
10Layout10.
1LayoutGuidelinesFigure98illustratesaPCBlayoutexamplefortheADS869x.
PartitionthePCBintoanaloganddigitalsections.
Caremustbetakentoensurethattheanalogsignalsarekeptawayfromthedigitallines.
Thislayouthelpskeeptheanaloginputandreferenceinputsignalsawayfromthedigitalnoise.
Inthislayoutexample,theanaloginputandreferencesignalsareroutedonthelowersideoftheboardandthedigitalconnectionsareroutedonthetopsideoftheboard.
Usingasinglededicatedgroundplaneisstronglyencouraged.
PowersourcestotheADS869xmustbecleanandwell-bypassed.
Usinga1-μF,X7R-grade,0603-sizeceramiccapacitorwithatleasta10-Vratingincloseproximitytotheanalog(AVDD)supplypinsisrecommended.
Fordecouplingthedigitalsupplypin(DVDD),a1-μF,X7R-grade,0603-sizeceramiccapacitorwithatleasta10-Vratingisrecommended.
PlacingviasbetweentheAVDD,DVDDpinsandthebypasscapacitorsmustbeavoided.
Allgroundpinsmustbeconnectedtothegroundplaneusingshort,low-impedancepaths.
TherearetwodecouplingcapacitorsusedfortheREFCAPpin.
Thefirstisasmall,1-μF,0603-sizeceramiccapacitorplacedclosetothedevicepinsfordecouplingthehigh-frequencysignalsandthesecondisa10-μF,0805-sizeceramiccapacitortoprovidethechargerequiredbythereferencecircuitofthedevice.
AcapacitorwithanESRlessthan0.
2Ωisrecommendedforthe10-μFcapacitor.
Bothofthesecapacitorsmustbedirectlyconnectedtothedevicepinswithoutanyviasbetweenthepinsandcapacitors.
TheREFIOpinalsomustbedecoupledwithaminimumof4.
7-μFceramiccapacitoriftheinternalreferenceofthedeviceisused.
Thecapacitormustbeplacedclosetothedevicepins.
61ADS8691,ADS8695,ADS8699www.
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cnZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018版权2016–2018,TexasInstrumentsIncorporated10.
2LayoutExampleFigure98.
BoardLayoutfortheADS869x62ADS8691,ADS8695,ADS8699ZHCSFT8A–DECEMBER2016–REVISEDOCTOBER2018www.
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cn版权2016–2018,TexasInstrumentsIncorporated11器器件件和和文文档档支支持持11.
1文文档档支支持持11.
1.
1相相关关文文档档请参阅如下相关文档:德州仪器(TI),《具有关断功能的OPA320高精度、20MHz、0.
9pA、低噪声、RRIO、CMOS运算放大器》数据表德州仪器(TI),《SN6501用于隔离式电源的变压器驱动器》数据表德州仪器(TI),《TPS7A4936V、150mA、超低噪声、正线性稳压器》数据表德州仪器(TI),《ISO764xFM低功耗四通道数字隔离器》数据表德州仪器(TI),《AN-2029操作和处理建议》应用报告11.
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类别包括技术文档、支持和社区资源、工具和软件,以及立即订购快速访问.
表表20.
相相关关链链接接器器件件产产品品文文件件夹夹立立即即订订购购技技术术文文档档工工具具与与软软件件支支持持和和社社区区ADS8691请单击此处请单击此处请单击此处请单击此处请单击此处ADS8695请单击此处请单击此处请单击此处请单击此处请单击此处ADS8699请单击此处请单击此处请单击此处请单击此处请单击此处11.
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这些内容并不构成TI技术规范,并且不一定反映TI的观点;请参阅TI的《使用条款》.
TIE2E在在线线社社区区TI的的工工程程师师对对工工程程师师(E2E)社社区区.
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设设计计支支持持TI参参考考设设计计支支持持可帮助您快速查找有帮助的E2E论坛、设计支持工具以及技术支持的联系信息.
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multiSPIisatrademarkofMotorolaMobilityLLC.
Allothertrademarksarethepropertyoftheirrespectiveowners.
11.
6静静电电放放电电警警告告ESD可能会损坏该集成电路.
德州仪器(TI)建议通过适当的预防措施处理所有集成电路.
如果不遵守正确的处理措施和安装程序,可能会损坏集成电路.
ESD的损坏小至导致微小的性能降级,大至整个器件故障.
精密的集成电路可能更容易受到损坏,这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符.
11.
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这份术语表列出并解释术语、缩写和定义.
12机机械械、、封封装装和和可可订订购购信信息息以下页面包含机械、封装和可订购信息.
这些信息是指定器件的最新可用数据.
数据如有变更,恕不另行通知,且不会对此文档进行修订.
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IMPORTANTNOTICE邮寄地址:上海市浦东新区世纪大道1568号中建大厦32楼,邮政编码:200122Copyright2018德州仪器半导体技术(上海)有限公司PACKAGEOPTIONADDENDUMwww.
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com10-Dec-2020Addendum-Page1PACKAGINGINFORMATIONOrderableDeviceStatus(1)PackageTypePackageDrawingPinsPackageQtyEcoPlan(2)Leadfinish/Ballmaterial(6)MSLPeakTemp(3)OpTemp(°C)DeviceMarking(4/5)SamplesADS8691IPWACTIVETSSOPPW1690RoHS&GreenNIPDAULevel-3-260C-168HR-40to125ADS8691ADS8691IPWRACTIVETSSOPPW162000RoHS&GreenNIPDAULevel-3-260C-168HR-40to125ADS8691ADS8695IPWACTIVETSSOPPW1690RoHS&GreenNIPDAULevel-3-260C-168HR-40to125ADS8695ADS8695IPWRACTIVETSSOPPW162000RoHS&GreenNIPDAULevel-3-260C-168HR-40to125ADS8695ADS8699IPWACTIVETSSOPPW1690RoHS&GreenNIPDAULevel-3-260C-168HR-40to125ADS8699ADS8699IPWRACTIVETSSOPPW162000RoHS&GreenNIPDAULevel-3-260C-168HR-40to125ADS8699(1)Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.
LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.
NRND:Notrecommendedfornewdesigns.
Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.
PREVIEW:Devicehasbeenannouncedbutisnotinproduction.
Samplesmayormaynotbeavailable.
OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.
(2)RoHS:TIdefines"RoHS"tomeansemiconductorproductsthatarecompliantwiththecurrentEURoHSrequirementsforall10RoHSsubstances,includingtherequirementthatRoHSsubstancedonotexceed0.
1%byweightinhomogeneousmaterials.
Wheredesignedtobesolderedathightemperatures,"RoHS"productsaresuitableforuseinspecifiedlead-freeprocesses.
TImayreferencethesetypesofproductsas"Pb-Free".
RoHSExempt:TIdefines"RoHSExempt"tomeanproductsthatcontainleadbutarecompliantwithEURoHSpursuanttoaspecificEURoHSexemption.
Green:TIdefines"Green"tomeanthecontentofChlorine(Cl)andBromine(Br)basedflameretardantsmeetJS709Blowhalogenrequirementsof<=1000ppmthreshold.
Antimonytrioxidebasedflameretardantsmustalsomeetthe<=1000ppmthresholdrequirement.
(3)MSL,PeakTemp.
-TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.
(4)Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice.
(5)MultipleDeviceMarkingswillbeinsideparentheses.
OnlyoneDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.
IfalineisindentedthenitisacontinuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice.
(6)Leadfinish/Ballmaterial-OrderableDevicesmayhavemultiplematerialfinishoptions.
Finishoptionsareseparatedbyaverticalruledline.
Leadfinish/Ballmaterialvaluesmaywraptotwolinesifthefinishvalueexceedsthemaximumcolumnwidth.
PACKAGEOPTIONADDENDUMwww.
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TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.
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InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.
TAPEANDREELINFORMATION*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQReelDiameter(mm)ReelWidthW1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantADS8691IPWRTSSOPPW162000330.
012.
46.
95.
61.
68.
012.
0Q1ADS8695IPWRTSSOPPW162000330.
012.
46.
95.
61.
68.
012.
0Q1ADS8699IPWRTSSOPPW162000330.
012.
46.
95.
61.
68.
012.
0Q1PACKAGEMATERIALSINFORMATIONwww.
ti.
com22-Oct-2018PackMaterials-Page1*AlldimensionsarenominalDevicePackageTypePackageDrawingPinsSPQLength(mm)Width(mm)Height(mm)ADS8691IPWRTSSOPPW162000367.
0367.
035.
0ADS8695IPWRTSSOPPW162000367.
0367.
035.
0ADS8699IPWRTSSOPPW162000367.
0367.
035.
0PACKAGEMATERIALSINFORMATIONwww.
ti.
com22-Oct-2018PackMaterials-Page2www.
ti.
comPACKAGEOUTLINEC14X0.
652X4.
5516X0.
300.
19TYP6.
66.
21.
2MAX0.
150.
050.
25GAGEPLANE-80BNOTE44.
54.
3ANOTE35.
14.
90.
750.
50(0.
15)TYPTSSOP-1.
2mmmaxheightPW0016ASMALLOUTLINEPACKAGE4220204/A02/2017189160.
1CABPIN1INDEXAREASEEDETAILA0.
1CNOTES:1.
Alllineardimensionsareinmillimeters.
Anydimensionsinparenthesisareforreferenceonly.
DimensioningandtolerancingperASMEY14.
5M.
2.
Thisdrawingissubjecttochangewithoutnotice.
3.
Thisdimensiondoesnotincludemoldflash,protrusions,orgateburrs.
Moldflash,protrusions,orgateburrsshallnotexceed0.
15mmperside.
4.
Thisdimensiondoesnotincludeinterleadflash.
Interleadflashshallnotexceed0.
25mmperside.
5.
ReferenceJEDECregistrationMO-153.
SEATINGPLANEA20DETAILATYPICALSCALE2.
500www.
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05MAXALLAROUND0.
05MINALLAROUND16X(1.
5)16X(0.
45)14X(0.
65)(5.
8)(R0.
05)TYPTSSOP-1.
2mmmaxheightPW0016ASMALLOUTLINEPACKAGE4220204/A02/2017NOTES:(continued)6.
PublicationIPC-7351mayhavealternatedesigns.
7.
Soldermasktolerancesbetweenandaroundsignalpadscanvarybasedonboardfabricationsite.
LANDPATTERNEXAMPLEEXPOSEDMETALSHOWNSCALE:10XSYMMSYMM1891615.
000METALSOLDERMASKOPENINGMETALUNDERSOLDERMASKSOLDERMASKOPENINGEXPOSEDMETALEXPOSEDMETALSOLDERMASKDETAILSNON-SOLDERMASKDEFINED(PREFERRED)SOLDERMASKDEFINEDwww.
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5)16X(0.
45)14X(0.
65)(5.
8)(R0.
05)TYPTSSOP-1.
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Lasercuttingapertureswithtrapezoidalwallsandroundedcornersmayofferbetterpasterelease.
IPC-7525mayhavealternatedesignrecommendations.
9.
Boardassemblysitemayhavedifferentrecommendationsforstencildesign.
SOLDERPASTEEXAMPLEBASEDON0.
125mmTHICKSTENCILSCALE:10XSYMMSYMM18916重重要要声声明明和和免免责责声声明明TI均以"原样"提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示担保.
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IMPORTANTNOTICE邮寄地址:上海市浦东新区世纪大道1568号中建大厦32楼,邮政编码:200122Copyright2020德州仪器半导体技术(上海)有限公司