5.ios

AS4C64M16MD1Confidential1Rev1.
0Mar/20141Gb(64Mx16bit)1.
8vHighPerformanceMobileDDRSDRAMConfidentialAdvanced(Rev.
1.
0,Mar.
/2014)Features-4banksx16Mx16organization-DataMaskforWriteControl(DM)-FourBankscontrolledbyBA0&BA1-ProgrammableCASLatency:2,3-ProgrammableWrapSequence:SequentialorInterleave-ProgrammableBurstLength:2,4,8or16forSequentialType2,4,8or16forInterleaveType-AutomaticandControlledPrechargeCommand-PowerDownMode-AutoRefreshandSelfRefresh-RefreshInterval:8192cycles/64ms-DoubleDataRate(DDR)-BidirectionalDataStrobe(DQS)forinputandoutputdata,activeonbothedges-DifferentialclockinputsCLKand/CLK-PowerSupply1.
7V-1.
90;BACKGROUND-COLOR:#4ae2f7">5V-DriveStrength(DS)Option:Full,1/2,1/4,1/8-AutoTemperature-CompensatedSelfRefresh(AutoTCSR)-Partial-ArraySelfRefresh(PASR)Option:Full,1/2,1/4,1/8,1/16-DeepPowerDown(DPD)mode-OperatingTemperatureRangeExtended-20;BACKGROUND-COLOR:#4ae2f7">5°Cto80;BACKGROUND-COLOR:#4ae2f7">5°CIndustrial-40°Cto80;BACKGROUND-COLOR:#4ae2f7">5°C-60ballFPBGApackageALLPRODUCTSROHSCOMPLIANTDescriptionTheAS4C64M16MD1isafourbankmobileDDRDRAMorganizedas4banksx16Mx16.
Itachieveshighspeeddatatransferratesbyemployingachiparchitecturethatprefetchesmultiplebitsandthensynchronizestheoutputdatatoasystemclock.
Allofthecontrol,address,circuitsissynchronizedwiththepositiveedgeofanexternallysup-pliedclock.
I/OtransactionsarepossibleonbothedgesofDQS.
OperatingthefourmemorybanksinaninterleavedfashionallowsrandomaccessoperationtooccuratahigherratethanispossiblewithstandardDRAMs.
Asequentialandgaplessdatarateispossibledependingonburstlength,CASlatencyandspeedgradeofthedevice.
Additionally,thedevicesupportslowpowersavingfeatureslikePASR,Auto-TCSR,DPDaswellasoptionsfordifferentdrivestrength.
It'sideallysuit-ableformobileapplication.
6UnitSystemFrequency(fCK)166MHzMHzClockCycleTime(tCK3)6.
0nsOutputdataaccessTime(tAC(CL3))0;BACKGROUND-COLOR:#4ae2f7">5.
0nsORDERINGINFORMATIONPartNo.
ClockFrequencyVdd/VddqOrganisationPackageAS4C64M16MD1-6BCN*DDR333166MHz1.
8V/1.
8V16Mx16Bitsx4Banks60-FPBGAAS4C64M16MD1-6BIN*DDR333166MHz1.
8V/1.
8V16Mx16Bitsx4Banks60-FPBGA*B=FPBGApackage*C=usuallyrepresentscommercialtemperaturebutinthiscaseitExtended(-20;BACKGROUND-COLOR:#4ae2f7">5°Cto+80;BACKGROUND-COLOR:#4ae2f7">5°C)I=Industrialtemperature-40°Cto80;BACKGROUND-COLOR:#4ae2f7">5°C*N=ROHSCompliantAS4C64M16MD1Confidential2Rev1.
0Mar/2014BlockDiagramAS4C64M16MD1Confidential3Rev1.
0Mar/201460Ball(6x10)CSP123789AVSSDQ10;BACKGROUND-COLOR:#4ae2f7">5VSSQVDDQDQ0VDDBVDDQDQ13DQ14DQ1DQ2VSSQCVSSQDQ11DQ12DQ3DQ4VDDQDVDDQDQ9DQ10DQ0;BACKGROUND-COLOR:#4ae2f7">5DQ6VSSQEVSSQUDQSDQ8DQ7LDQSVDDQFVSSUDMN.
C.
A13LDMVDDGCKECKCKWECASRASHA9A11A12CSBA0BA1JA6A7A8A10/APA0A1KVSSA4A0;BACKGROUND-COLOR:#4ae2f7">5A2A3VDD60BALLBGACONFIGURATIONTopView98760;BACKGROUND-COLOR:#4ae2f7">541ABCDEFGHJKPinNamesCLK,CLKDifferentialClockInputCKEClockEnableCSChipSelectRASRowAddressStrobeCASColumnAddressStrobeWEWriteEnableLDQS,UDQSDataStrobe(Bidirectional)A0–A13AddressInputsBA0,BA1BankSelectDQ0–DQ10;BACKGROUND-COLOR:#4ae2f7">5DataInput/OutputLDM,UDMDataMaskVDDPower(1.
7V-1.
90;BACKGROUND-COLOR:#4ae2f7">5V)VSSGroundVDDQPowerforI/O's(1.
7V-1.
90;BACKGROUND-COLOR:#4ae2f7">5V)VSSQGroundforI/O'sAS4C64M16MD1Confidential4Rev1.
0Mar/2014SignalPinDescriptionPinTypeSignalPolarityFunctionCLKCLKInputPulsePositiveEdgeThesystemclockinput.
AllinputsexceptDQsandDMsaresampledontherisingedgeofCLK.
CKEInputLevelActiveHighActivatestheCLKsignalwhenhighanddeactivatestheCLKsignalwhenlow,therebyinitiateseitherthePowerDownmode,Suspendmode,ortheSelfRefreshmode.
CSInputPulseActiveLowCSenablesthecommanddecoderwhenlowanddisablesthecommanddecoderwhenhigh.
Whenthecommanddecoderisdisabled,newcommandsareignoredbutpreviousoperationscontinue.
InputPulseActiveLowWhensampledatthepositiverisingedgeoftheclock,CAS,RAS,andWEdefinethecommandtobeexecutedbytheSDRAM.
RAS,CASWEA0-A13InputLevel—DuringaBankActivatecommandcycle,A0-A13definestherowaddress(RA0-RA13)whensampledattherisingclockedge.
DuringaReadorWritecommandcycle,A0-A9definesthecolumnaddress(CA0-CA9)whensampledattherisingclockedge.
Inadditiontothecolumnaddress,A10isusedtoinvokeautoprechargeoperationattheendoftheburstreadorwritecycle.
IfA10ishigh,autoprechargeisselectedandBA0,BA1definesthebanktobeprecharged.
IfA10islow,autoprechargeisdisabled.
DuringaPrechargecommandcycle,A10(=AP)isusedinconjunctionwithBA0andBA1tocontrolwhichbank(s)toprecharge.
IfA10ishigh,allfourbankswillbeprechargedsimultaneouslyregardlessofstateofBA0andBA1.
DQxInput/OutputLevelDataInput/OutputpinsoperateinthesamemannerasconventionalDRAMs.
BA0,BA1InputLevel—Selectswhichbankistobeactive.
LDQS,UDQSInput/OutputLevel—DataInput/OutputaresynchronousedgesoftheDQS.
LDQSforDQ0-DQ7,UDQSforDQ8-DQ10;BACKGROUND-COLOR:#4ae2f7">5.
Activeonbothedgesfordatainput/output.
CenteralignedtoinputdataandEdgealignedtooutputdata.
UDM,LDMInputPulseActiveHighInWritemode,DQMhasalatencyofzeroandoperatesasawordmaskbyallowinginputdatatobewrittenifitislowbutblocksthewriteoperationifishigh.
Ifit'shigh,LDMcorrespondstoDQ0-DQ7,andUDMcorrespondstodataonDQ8-DQ10;BACKGROUND-COLOR:#4ae2f7">5.
VDD,VSSSupplyPowerandgroundfortheinputbuffersandthecorelogic.
VDDQVSSQSupply——Isolatedpowersupplyandgroundfortheoutputbufferstoprovideimprovednoiseimmunity.
AS4C64M16MD1Confidential32Rev1.
0Mar/2014ModeRegisterSetThemoderegisterstoresthedataforcontrollingthevariousoperatingmodesofthemobileDDR,includesCASlatency,addressingmode,burstlength,testmode,andvariousvendorspecificoptions.
Thedefaultvalueofthemoderegisterisnotdefined.
ThereforethemoderegistermustbewrittenafterpoweruptooperatethemobileDDR.
ThedeviceshouldbeactivatedwiththeCKEalreadyhighpriortowritingintotheModeRegister.
TheModeRegisteriswrittenbyusingtheMRScommand.
ThestateoftheaddresssignalsregisteredinthesamecycleasMRScommandiswritteninthemoderegister.
Thevaluecanbechangedaslongasallbanksareintheidlestate.
Themoderegisterisdividedintovariousfieldsdependingonfunctionality.
TheburstlengthusesA2.
.
A0,CASlatency(readlatencyfromcolumnaddress)usesA6.
.
A4.
BA0mustbesettolowfornormaloperation.
A9.
.
A13isreservedforfutureuse.
BA1selectsExtendedModeRegisterSetupoperationwhensetto1.
Refertothetableforspecificcodesforvariousburstlength,addressingmodesandCASlatencies.
AS4C64M16MD1Confidential33Rev1.
0Mar/2014EMRSTheExtendedModeRegisterisresponsibleforsettingtheDrivestrengthoptionsandPartialarraySelfRefresh.
TheEMRScanbeprogrammedbyperforminganormalModeRegisterSetupoperationandsettingtheBA1=1andBA0=0.
Inordertosavepowerconsumption,themobileDDRSDRAMhasfive(PASR)options:Fullarray,1/2,1/4,1/8,1/16ofFullArray.
Additionally,thedevicehasinternaltemperaturesensortocontrolselfrefreshcycleautomaticallyaccordingtothetwotemperaturerange;Max.
40degC,andMax.
80;BACKGROUND-COLOR:#4ae2f7">5degC.
ThisisthedeviceinternalTemperatureCompensatedSelfRefresh(TCSR).
Thedevicehasfourdrivestrengthoptions:Full,1/2,1/4or1/8.
AS4C64M16MD1Confidential34Rev1.
0Mar/2014SignalandTimingDescriptionGeneralDescriptionThe1GbitmobileDDRisa128MbytemobileDDRSDRAM.
Itconsistsoffourbanks.
Eachbankisorganizedas16384rowsx1024columnsx16bits.
ReadandWriteaccessesareburstoriented.
AccessesbeginwiththeregistrationofanActivatecommand,whichisthenfollowedbyaReadorWritecommand.
TheaddressbitsregisteredcoincidentwiththeActivatecommandareusedtoselectthebankandtherowtobeaccessed.
BA1andBA0selectthebank,addressbitsA13.
.
A0selecttherow.
AddressbitsA9.
.
A0registeredcoincidentwiththeReadorWritecommandsareusedtoselectthestartingcolumnlocationfortheburstaccess.
TheregularSingleDataRateSDRAMreadandwritecyclesonlyusetherisingedgeoftheexternalclockinput.
ForthemobileSDRAMthespecialsignalsDQSx(DataStrobe)areusedtomarkthedatavalidwindow.
Duringreadbursts,thedatavalidwindowcoincideswiththehighorlowleveloftheDQSxsignals.
Duringwritebursts,theDQSxsignalmarksthecenterofthevaliddatawindow.
DataisavailableateveryrisingandfallingedgeofDQSx,thereforethedatatransferrateisdoubled.
ForReadaccesses,theDQSxsignalsarealignedtotheclocksignalCLK.
SpecialSignalDescriptionClockSignalThemobileDDRoperateswithadifferentialclock(CLKandCLK)input.
CLKisusedtolatchtheaddressandcommandsignals.
DatainputandDMxsignalsarelatchedwithDQSx.
TheminimumandmaximumclockcycletimeisdefinedbytCK.
TheminimumandmaximumclockdutycyclearespecifiedusingtheminimumclockhightimetCHandtheminimumclocklowtimetCLrespectively.
CommandInputsandAddressesLikesingledatarateSDRAMs,eachcombinationofRAS,CASandWEinputinconjunctionwithCSinputatarisingedgeoftheclockdeterminesamobileDDRcommand.
AS4C64M16MD1Confidential30;BACKGROUND-COLOR:#4ae2f7">5Rev1.
0Mar/2014DataStrobeandDataMaskOperationatBurstReadsTheDataStrobesprovidea3-stateoutputsignaltothereceivercircuitsofthecontrollerduringareadburst.
Thedatastrobesignalgoes1clockcyclelowbeforedataisdrivenbythemobileDDRandthentoggleslowtohighandhightolowtilltheendoftheburst.
CASlatencyisspecifiedtothefirstlowtohightransition.
TheedgesoftheOutputDatasignalsandtheedgesofthedatastrobesignalsduringareadarenominallycoincidentwithedgesoftheinputclock.
ThetoleranceoftheseedgesisspecifiedbytheparameterstACandtDQSCKandisreferencedtothecrossingpointoftheCLKand/CLKsignal.
ThetDQSQtimingparameterdescribestheskewbetweenthedatastrobeedgeandtheoutputdataedge.
ThefollowingtablesummarizesthemappingofLDQS,UDQS,LDMandUDMsignalstothedatabus.
MappingofLDQS,UDQS,LDMandUDMDatastrobesignalDatamasksignalControlleddatabusLDQSLDMDQ7.
.
DQ0UDQSUDMDQ8.
.
DQ10;BACKGROUND-COLOR:#4ae2f7">5Theminimumtimeduringwhichtheoutputdataisvalidiscriticalforthereceivingdevice.
ThisalsoappliestotheDataStrobeDQSduringareadsinceitistightlycoupledtotheoutputdata.
TheparameterstQHandtDQSQdefinethemini-mumoutputdatavalidwindow.
Priortoaburstofreaddata,giventhatthedeviceisnotcurrentlyinburstreadmode,thedatastrobesignalstransitfromHi-Ztoavalidlogiclow.
Thisisreferredtoasthedatastrobe"readpreamble"tRPRE.
Thistransitionhappensoneclockpriortothefirstedgeofvaliddata.
Oncetheburstofreaddataisconcluded,giventhatnosubsequentburstreadoperationisinitiated,thedatastrobesignalstransitfromavalidlogiclowtoHi-Z.
Thisisreferredtoasthedatastrobe"readpostamble"tRPST.
AS4C64M16MD1Confidential36Rev1.
0Mar/2014DataOutputTiming-tACandtDQSCKAS4C64M16MD1Confidential37Rev1.
0Mar/2014OperationatBurstWriteDuringawriteburst,controlofthedatastrobeisdrivenbythememorycontroller.
TheLDQS,UDQSsignalsarecenteredwithrespecttodataanddatamask.
Thetoleranceofthedataanddatamaskedgesversusthedatastrobeedgesduringwritesarespecifiedbythesetupandholdtimeparametersofdata(tQDQSS&tQDQSH)anddatamask(tDMDQSS&tDMDQSH).
TheinputdataismaskedinthesamecyclewhenthecorrespondingLDM,UDMsignalishigh(i.
e.
theLDM,UDMmasktowritelatencyiszero.
)Priortoaburstofwritedata,giventhatthecontrollerisnotcurrentlyinburstwritemode,thedatastrobesignalLDQS,UDQSchangesfromHi-Ztoavalidlogiclow.
ThisisreferredtoasthedatastrobeWritePreamble.
Oncetheburstofwritedataisconcluded,givennosubsequentburstwriteoperationisinitiated,thedatastrobesignalLDQS,UDQStransitsfromavalidlogiclowtoHi-Z.
ThisisreferredthedatastrobeWritePostamble,tWPST.
FormobileDRRdataiswrittenwithadelaywhichisdefinedbytheparametertDQSS,writelatency).
ThisisdifferentthanthesingledatarateSDRAMwheredataiswritteninthesamecycleastheWritecommandisissued.
AS4C64M16MD1Confidential38Rev1.
0Mar/2014Power-UpSequenceThefollowingsequenceishighlyrecommendedforPower-Up:1.
Applypowerandstartclock.
MaintainCKEandtheotherpinsareinNOPconditionsattheinput2.
ApplyVDDbeforeoratthesametimeasVDDQ,applyVDDQbeforeoratthesametimeasVREF,VTT3.
Startclock,maintainstableconditionsfor200us4.
ApplyNOPandsetCKEtohigh0;BACKGROUND-COLOR:#4ae2f7">5.
ApplyAllBankPrechargecommand6.
IssueAutoRefreshcommandtwiceandmustsatisfyminimumtRFC7.
IssueMRS(ModeRegisterSetcommand)8.
IssueaEMRS(ExtendedModeRegisterSetcommand),notnecessaryModeRegisterSetTimingThemobileDDRshouldbeactivatedwithCKEalreadyhighpriortowritingintothemoderegister.
TwoClockcyclesarerequiredcompletethewriteoperationinthemoderegister.
Themoderegistercontentscanbechangedusingthesamecommandandclockcyclerequirementsduringoperationaslongasallbanksareintheidlestate.
AS4C64M16MD1Confidential39Rev1.
0Mar/2014BankActivationCommand(ACT)TheBankActivationcommandisinitiatedbyissuinganACTcommandattherisingedgeoftheclock.
ThemobileDDRhas4independentbankswhichareselectedbythetwoBankselectAddresses(BA0,BA1).
TheBankActivationcommandmustbeappliedbeforeanyReadorWriteoperationcanbeexecuted.
ThedelayfromtheBankActivationcommandtothefirstreadorwritecommandmustmeetorexceedtheminimumofRAStoCASdelaytime(tRCDRDmin.
forreadcommandsandtRCDWRmin.
forwritecommands).
Onceabankhasbeenactivated,itmustbeprechargedbeforeanotherBankActivatecommandcanbeappliedtothesamebank.
TheminimumtimeintervalbetweeninterleavedBankActivatecommands(BankAtoBankBandviceversa)istheBanktoBankactivationdelaytime(tRRDmin).
AS4C64M16MD1Confidential40Rev1.
0Mar/2014PrechargeCommandThiscommandisusedtoprechargeorcloseabankthathasbeenactivated.
PrechargeisinitiatedbyissuingaPrechargecommandattherisingedgeoftheclock.
ThePrechargecommandcanbeusedtoprechargeeachbankrespectivelyorallbankssimultaneously.
TheBankaddressesBA0andBA1selectthebanktobeprecharged.
AfteraPrechargecommand,theanalogdelaytRPhastobemetuntilanewActivatecommandcanbeinitiatedtothesamebank.
TablePrechargeControlAS4C64M16MD1Confidential41Rev1.
0Mar/2014SelfRefreshTheSelfRefreshmodecanbeusedtoretainthedatainthemobileDDRifthechipispowereddown.
TosetthemobileDDRintoaSelfRefreshingmode,aSelfRefreshcommandmustbeissuedandCKEheldlowattherisingedgeoftheclock.
OncetheSelfRefreshcommandisinitiated,CKEmuststaylowtokeepthedeviceinSelfRefreshmode.
DuringtheSelfRefreshmode,alloftheexternalcontrolsignalsaredisabledexceptCKE.
TheclockisinternallydisabledduringSelfRefreshoperationtoreducepower.
Aninternaltiminggeneratorguaranteestheself-refreshingofthememorycontent.
AS4C64M16MD1Confidential42Rev1.
0Mar/2014AutoRefreshTheautorefreshfunctionisinitiatedbyissuinganAutoRefreshcommandattherisingedgeoftheclock.
AllbanksmustbeprechargedandidlebeforetheAutoRefreshcommandisapplied.
Nocontroloftheexternaladdresspinsisrequiredoncethiscyclehasstarted.
Allnecessaryaddressesaregeneratedinthedeviceitself.
Whentherefreshcyclehascompleted,allbankswillbeintheidlestate.
AdelaybetweentheAutoRefreshcommandandthenextActivateCommandorsubsequentAutoRefreshCommandmustbegreaterthanorequaltothetRFC(min).
PowerDownModeThePowerDownModeisenteredwhenCKEissetlowandexitedwhenCKEissethigh.
TheCKEsignalissampledattherisingedgeoftheclock.
OncethePowerDownModeisinitiated,allofthereceivercircuitsexceptCLKandtheCKEcircuitsaregatedofftoreducepowerconsumption.
AllbankscanbesettoidlestateorstayactivateduringPowerdownMode,butburstactivitymaynotbeperformed.
AfterexitingfromPowerDownMode,atleastoneclockcycleofcommanddelaymustbeinsertedbeforestartinganewcommand.
DuringPowerDownMode,refreshoperationscannotbeperformed;therefore,thedevicecannotremaininPowerDownModelongerthantherefreshperiod(tREF)ofthedevice.
AS4C64M16MD1Confidential43Rev1.
0Mar/2014DeepPowerDownModeTheDeepPowerDownmodeisauniquefunctionwithverylowstandbycurrents.
AllinternalvoltagegeneratorsinsidethemobileDDRarestoppedandallmemorydataislostinthismode.
ToentertheDeepPowerDownmodeallbanksmustbeprecharged.
Thedeeppowerdownmodehastobemaintainedforaminimumof100s.
AS4C64M16MD1Confidential44Rev1.
0Mar/2014DeepPowerDownExitThedeeppowerdownmodeisexitedbyassertingCKEhigh.
Aftertheexit,thefollowingsequenceisneededtoenteranewcommand:1.
MaintainNOPinputconditionsforaminimumof200us2.
Issueprechargecommandsforallbanksofthedevice3.
IssuetwoormoreautorefreshcommandsandsatisfyminimumtRFC4.
Issueamoderegistersetcommandtoinitializethemoderegister0;BACKGROUND-COLOR:#4ae2f7">5.
IssueanextendedmoderegistersetcommandtoinitializetheextendedmoderegisterAS4C64M16MD1Confidential40;BACKGROUND-COLOR:#4ae2f7">5Rev1.
0Mar/2014BurstModeOperationBurstmodeoperationisusedtoprovideaconstantflowofdatatothememory(writecycle)orfromthememory(readcycle).
TheburstlengthisprogrammableandsetbyaddressbitsA0-A3duringtheModeRegisterSetupcommand.
Theburstlengthcontrolsthenumberofwordsthatwillbeoutputafterareadcommandorthenumberofwordstobeinputafterawritecommand.
Onewordis32bitswide.
Thesequentialburstlengthcanbesetto2,4,8or16datawords.
AS4C64M16MD1Confidential46Rev1.
0Mar/2014BurstReadOperation:(READ)TheBurstReadoperationisinitiatedbyissuingaREADcommandattherisingedgeoftheclockaftertRCDfromthebankactivation.
Theaddressinputs(A8.
.
A0)determinethestartingaddressfortheburst.
Theburstlength(2,4or8)mustbedefinedintheModeRegister.
ThefirstdataaftertheREADcommandisavailabledependingontheCASlatency.
ThesubsequentdataisclockedoutontherisingandfallingedgeofLDQS,UDQSuntiltheburstiscompleted.
TheLDQS,UDQSsignalsaregeneratedbythemobileDDRduringtheBurstReadOperation.
AS4C64M16MD1Confidential47Rev1.
0Mar/2014BurstWriteOperation(WRITE)TheBurstWriteisinitiatedbyissuingaWRITEcommandattherisingedgeoftheclock.
Theaddressinputs(A8.
.
A0)determinestartingcolumnaddress.
DataforthefirstburstwritecyclemustbeappliedontheDQpinsonthefirstriseedgeofLDQS,UDQSfollowWRITEcommand.
ThetimebetweentheWRITEcommandandthefirstcorrespondingedgeofthedatastrobeistDQSS.
Theremainingdatainputsmustbesuppliedoneachsubsequentrisingandfallingedgeofthedatastrobeuntiltheburstlengthiscompleted.
Whenthebursthasbeenfinished,anyadditionaldatasuppliedtotheDQpinswillbeignored.
AS4C64M16MD1Confidential48Rev1.
0Mar/2014BurstStopCommand(BST)ABurstStopisinitiatedbyissuingaBURSTSTOPcommandattherisingedgeoftheclock.
TheBurstStopCommandhasthefewestrestrictions,makingittheeasiestmethodtoterminateaburstoperationbeforeithasbeencompleted.
WhentheBurstStopCommandisissuedduringaburstreadcycle,readdataandLDQS,UDQSgotoahigh-ZstateafteradelaywhichisequaltotheCASlatencysetintheModeRegister.
TheBurstStoplatencyisequaltotheCASlatencyCL.
TheBurstStopcommandisnotsupportedduringawriteburstoperation.
BurstStopisalsoillegalduringReadwithAuto-PrechargeAS4C64M16MD1Confidential49Rev1.
0Mar/2014DataMask(LDM,UDM)FunctionThemobileDDRhasaDataMaskfunctionthatcanbeusedonlyduringwritecycles.
WhentheDataMaskisactivated,activehighduringburstwrite,thewriteoperationismaskedimmediately.
TheLDM,UDMtodata-masklatencyzero.
LDMandUDMcanbeissuedattherisingornegativeedgeofDataStrobe.
AS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">50Rev1.
0Mar/2014AS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">51Rev1.
0Mar/2014WritewithAutoprecharge(WRITEA)IfA8ishighwhenaWritecommandisissued,theWritewithAuto-Prechargefunctionisperformed.
TheinternalprechargebeginsafterthewriterecoverytimetWRandtRAS(min)aresatisfied.
IfaWritewithAutoPrechargecommandisinitiated,themobileDDRautomaticallyenterstheprechargeoperationatthefirstrisingedgeofCLKafterthelastvalidedgeofDQS(completionoftheburst)plusthewriterecoverytimetWR.
Oncetheprechargeoperationhasstarted,thebankcannotbereactivatedandthenewcommandcannotbeasserteduntilthePrechargetime(tRP)hasbeensatisfied.
IftRAS(min)hasnotbeensatisfiedyet,aninternalinterlockwilldelaytheprechargeoperationuntilitissatisfied.
AS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">52Rev1.
0Mar/2014WriteInterruptedbyaPrechargeABurstWriteoperationcanbeinterruptedbeforecompletionoftheburstbyaPrechargeofthesamebank.
Randomcolumnaccessisallowed.
AWriteRecoverytime(tWR)isrequiredfromthelastdatatoPrechargecommand.
WhenPrechargecommandisasserted,anyresidualdatafromtheburstwritecyclemustbemaskedbyLDM.
,UDM.
AS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">53Rev1.
0Mar/2014AS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">54Rev1.
0Mar/2014AS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5Rev1.
0Mar/2014AS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">56Rev1.
0Mar/2014AS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">57Rev1.
0Mar/2014Note:AllentriesassumetheCKEwasHighduringtheprecedingclockcycleNote:1.
Illegaltobankspecifiedstates;functionmaybelegalinthebankindicatedbyBAx,dependingonthestateofthatbankNote:2.
Mustsatisfybuscontention,busturnaround,writerecoveryrequirements.
Note:3.
Ifbothbanksareidle,andCKEisinactive,thedevicewillenterPowerDownMode.
AllinputbuffersexceptCKE,CLKandCLK#willbedisabled.
Note:4.
Ifbothbanksareidle,andCKEisdeactivatedcoincidentallywithanAutoRefreshcommand,thedevicewillenterSelfRefreshMode.
AllinputbuffersexceptCKEwillbedisabled.
Note:0;BACKGROUND-COLOR:#4ae2f7">5.
Illegal,iftRRDisnotsatisfied.
Note:6.
Illegal,iftRASisnotsatisfied.
Note:7.
Mustsatisfyburstinterruptcondition.
Note:8.
MustmasktwoprecedingdatabitswiththeDMpin.
Note:9.
Illegal,iftRCDisnotsatisfied.
Note:10.
Illegal,iftWRisnotsatisfied.
Note:11.
Illegal,iftRCisnotsatisfied.
Abbreviations:HHighLevelLLowLevelXDon'tCareVValidDataInputRARowAddressBABankAddressPAPrechargeAllNOPNoOperationCAColumnAddressAxAddressLinexAS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">58Rev1.
0Mar/2014Abbreviations:HHighLevelLLowLevelXDon'tCareVValidDataInputRARowAddressBABankAddressPAPrechargeAllNOPNoOperationCAColumnAddressAS4C64M16MD1Confidential0;BACKGROUND-COLOR:#4ae2f7">59Rev1.
0Mar/2014AS4C64M16MD1Confidential60Rev1.
0Mar/2014IDDMaxSpecificationsandConditionsConditionsVersionSymbol-6UnitOperatingcurrent-OnebankActive-Precharge;tRC=tRC(min);tCK=tCK(min);CKE=High;CS=Highbetweenvalidcommand;Addressinputsareswitchingevery2clockcycles;DatabusinputsarestableIDD00;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5mAPrechargepower-downstandbycurrent;Allbanksidle;CKE=Low;CS=High;tCK=tCK(min);Addressandcontrolinputsareswitching;DatabusinputsarestableIDD2P2mAPrechargepower-downstandbycurrent;Clockstopped;Allbanksidle;CKE=Low;CS=High;CK=Low;CK=High;Addressandcontrolinputsareswitching;DatabusinputsarestableIDD2PS2mAPrechargenonpower-downstandbycurrent;Allbanksidle;CKE=High;CS=High;tCK=tCK(min);Addressandcontrolinputsareswitching;DatabusinputsarestableIDD2N20;BACKGROUND-COLOR:#4ae2f7">5mAPrechargenonpower-downstandbycurrent;Clockstopped;Allbanksidle;CKE=High;CS=High;CK=Low;CK=High;Addressandcontrolinputsareswitching;DatabusinputsarestableIDD2NS18mAActivepower-downstandbycurrent;Onebankactive;CKE=Low;CS=High;tCK=tCK(min);Addressandcontrolinputsareswitching;DatabusinputsarestableIDD3P2mAActivepower-downstandbycurrent;Clockstopped;Onebankactive;CKE=Low;CS=High;CK=Low;CK=High;Addressandcontrolinputsareswitching;DatabusinputsarestableIDD3PS2mAActivenonpower-downstandbycurrent;Onebankactive;CKE=High;CS=High;tCK=tCK(min);Addressandcontrolinputsareswitching;DatabusinputsarestableIDD3N20;BACKGROUND-COLOR:#4ae2f7">5mAActivenonpower-downstandbycurrent;Clockstopped;Onebankactive;CKE=High;CS=High;CK=Low;CK=High;Addressandcontrolinputsareswitching;DatabusinputsarestableIDD3NS18mAOperatingcurrent-burstread;Onebankactive;Burstlength=4;tCK=tCK(min);ContinuousReadburst;Addressinputsareswitchingevery2clockcycles;0;BACKGROUND-COLOR:#4ae2f7">50%ofdatachangingateveryburst;lout=0mAIDD4R80;BACKGROUND-COLOR:#4ae2f7">5mAOperatingcurrent-burstwrite;Onebankactive;Burstlength=4;tCK=tCK(min);ContinuousWriteburst;Addressinputsareswitchingevery2clockcycles;0;BACKGROUND-COLOR:#4ae2f7">50%ofdatachangingateveryburstIDD4W80;BACKGROUND-COLOR:#4ae2f7">5mAAutorefreshcurrent;Burstrefresh;CKE=High;Addressandcontrolinputsareswitching;DatabusinputsarestableIDD0;BACKGROUND-COLOR:#4ae2f7">590mADeepPowerDownCurrent;Addressandcontrolinputsarestable;DatabusinputsarestableIDD80;BACKGROUND-COLOR:#4ae2f7">5uAAS4C64M16MD1Confidential61Rev1.
0Mar/2014PartialArraySelfRefreshCurrent(PASR)Parameter&TestConditionExtendedModeRegisterA[2:0]Tcase[oC]Symb.
max.
UnitNoteSelfRefreshCurrentSelfRefreshModeCKE=0.
2V,tck=infinity,fullarrayactivations,allbanks80;BACKGROUND-COLOR:#4ae2f7">5oCmax.
ICC62.
0mASelfRefreshCurrentSelfRefreshModeCKE=0.
2V,tck=infinity,1/2arrayactivations80;BACKGROUND-COLOR:#4ae2f7">5oCmax.
ICC61.
6mASelfRefreshCurrentSelfRefreshModeCKE=0.
2V,tck=infinity,1/4arrayactivation80;BACKGROUND-COLOR:#4ae2f7">5oCmax.
ICC61.
4mASelfRefreshCurrentSelfRefreshModeCKE=0.
2V,tck=infinity,1/8arrayactivation80;BACKGROUND-COLOR:#4ae2f7">5oCmax.
ICC61.
2mASelfRefreshCurrentSelfRefreshModeCKE=0.
2V,tck=infinity,1/16arrayactivation80;BACKGROUND-COLOR:#4ae2f7">5oCmax.
ICC61.
2mAAS4C64M16MD1Confidential62Rev1.
0Mar/2014AbsoluteMaximumRatingsParameterSymbolValueUnitVoltageonanypinrelativetoVSSVIN,VOUT-0.
0;BACKGROUND-COLOR:#4ae2f7">5~2.
7VVoltageonVDDsupplyrelativetoVSSVDD,VDDQ-0.
0;BACKGROUND-COLOR:#4ae2f7">5~2.
7VStoragetemperatureTSTG-0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5~+10;BACKGROUND-COLOR:#4ae2f7">50°CPowerdissipationPD1.
0WShortcircuitcurrent000000;BACKGROUND-COLOR:#ffff00">IOS0;BACKGROUND-COLOR:#4ae2f7">50mANote:PermanentdevicedamagemayoccurifABSOLUTEMAXIMUMRATINGSareexceeded.
FunctionaloperationshouldberestrictedtorecommendedoperatingconditionExposuretohigherthanrecommendedvoltageforextendedperiodsoftimecouldaffectdevicereliability.
Capacitance(VDD=1.
8V,TA=20;BACKGROUND-COLOR:#4ae2f7">5°C,f=1MHz)ParameterSymbolMinMaxUnitInputcapacitance(A0~A13,BA0~BA1,CKE,CS,RAS,CAS,WE)CIN11.
0;BACKGROUND-COLOR:#4ae2f7">53.
0pFInputcapacitance(CK,CK)CIN21.
0;BACKGROUND-COLOR:#4ae2f7">53.
0pFData&DQSinput/outputcapacitance(DQ0~DQ10;BACKGROUND-COLOR:#4ae2f7">5)COUT3.
00;BACKGROUND-COLOR:#4ae2f7">5.
0pFInputcapacitance(DMs)CIN33.
00;BACKGROUND-COLOR:#4ae2f7">5.
0pFAS4C64M16MD1Confidential63Rev1.
0Mar/2014Power&DCOperatingConditions(LVCMOSIn/Out)Recommendedoperatingconditions(VoltagereferencedtoVSS=0V)ParameterSymbolMinTypMaxUnitDeviceSupplyvoltageVDD1.
71.
81.
90;BACKGROUND-COLOR:#4ae2f7">5VOutputSupplyvoltageVDDQ1.
71.
81.
90;BACKGROUND-COLOR:#4ae2f7">5VInputlogichighvoltageVIH0.
7*VDDQ-VDDQ+0.
30VInputlogiclowvoltageVIL-0.
3-0.
3*VDDQVInputLeakagecurrentII-2-2uAOutputLeakagecurrentIOZ-0;BACKGROUND-COLOR:#4ae2f7">5-0;BACKGROUND-COLOR:#4ae2f7">5uAACInputOperatingConditionsRecommendedoperatingconditions(VoltagereferencedtoVSS=0V,VDD=1.
7V~1.
90;BACKGROUND-COLOR:#4ae2f7">5V)ParameterSymbolMinTypMaxUnitInputHigh(Logic1)Voltage;DQVIHVCCQ*0.
8-VCCQ+0.
3VInputLow(Logic0)Voltage;DQVIL-0.
3-0.
2*VDDQVClockInputCrossingPointVoltage;CKandCKVIX0.
4*VDDQ-0.
6*VDDQVACOperatingTestConditionsRecommendedoperatingconditions(VoltagereferencedtoVSS=0V,VDD=1.
7V~1.
90;BACKGROUND-COLOR:#4ae2f7">5V)ParameterValueUnitACinputlevels(Vih/Vil)0.
8*VDDQ/0.
2*VDDQVInputtimingmeasurementreferencelevel0.
0;BACKGROUND-COLOR:#4ae2f7">5*VDDQVInputsignalminimumslewrate1.
0V/nsOutputtimingmeasurementreferencelevel0.
0;BACKGROUND-COLOR:#4ae2f7">5*VDDQVOutputloadconditionSeebelowfiguresAS4C64M16MD1Confidential64Rev1.
0Mar/2014ACCHARACTERISTICS-6PARAMETERSYMBOLMINMAXUNITSNOTESOutputdataaccesstimefromCK/CKtAC20;BACKGROUND-COLOR:#4ae2f7">5ns3CKhigh-levelwidthtCH0.
40;BACKGROUND-COLOR:#4ae2f7">50.
0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5tCKCKlow-levelwidthtCL0.
40;BACKGROUND-COLOR:#4ae2f7">50.
0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">5tCKClockcycletimeCL=3tCK(3)6-ns1DQandDMinputholdtimerelativetoDQStDH0.
6ns0;BACKGROUND-COLOR:#4ae2f7">5,6DQandDMinputsetuptimerelativetoDQStDS0.
6ns0;BACKGROUND-COLOR:#4ae2f7">5,6DQandDMinputpulsewidth(foreachinput)tDIPW1.
6nsAccesswindowofDQSfromCK/CKtDQSCK20;BACKGROUND-COLOR:#4ae2f7">5nsDQSinputhighpulsewidthtDQSH0.
40.
6tCKDQSinputlowpulsewidthtDQSL0.
40.
6tCKDQS-DQskew,DQStolastDQvalid,pergroup,peraccesstDQSQ0.
0;BACKGROUND-COLOR:#4ae2f7">5ns1WritecommandtofirstDQSlatchingtransitiontDQSS0.
70;BACKGROUND-COLOR:#4ae2f7">51.
20;BACKGROUND-COLOR:#4ae2f7">5tCKHalfclockperiodtHPttCLnsData-outhigh-impedancewindowfromCK/CKtHZ0.
40.
6tCKData-outlow-impedancewindowfromCK/CKtLZ1nsAddressandcontrolinputholdtimetIH1.
1ns1AddressandcontrolinputsetuptimetIS1.
1ns1LOADMODEREGISTERcommandcycletimetMRD2tCKDQ-DQShold,DQStofirstDQtogonon-valid,peraccesstQHt-tQHSnsDataholdskewfactortQHS0.
60;BACKGROUND-COLOR:#4ae2f7">5nsACTIVEtoPRECHARGEcommandtRAS4270KnsACTIVEtoREADwithAutoprechargecommandtRAP10;BACKGROUND-COLOR:#4ae2f7">5nsACTIVEtoACTIVE/AUTOREFRESHcommandperiodtRC60nsAUTOREFRESHcommandperiodtRFC72nsACTIVEtoREADorWRITEdelaytRCD18nsPRECHARGEcommandperiodtRP18nsACTimingParameters&SpecificationAS4C64M16MD1Confidential60;BACKGROUND-COLOR:#4ae2f7">5Rev1.
0Mar/2014ACCHARACTERISTICS-6PARAMETERSYMBOLMINMAXUNITSNOTESDQSreadpreambletRPRE0.
91.
1tCKDQSreadpostambletRPST0.
40.
6tCKACTIVEbankAtoACTIVEbankBcommandtRRD12nsDQSwritepreambletWPRE0.
20;BACKGROUND-COLOR:#4ae2f7">5tCKDQSwritepreamblesetuptimetWPRES0ns4DQSwritepostambletWPST0.
40.
6tCKWriterecoverytimetWR10;BACKGROUND-COLOR:#4ae2f7">5nsInternalWRITEtoREADcommanddelaytWTR2tCKAverageperiodicrefreshintervaltREFI7.
8usPowerdownexittimetPDEX1*t+tISnsAS4C64M16MD1Confidential66Rev1.
0Mar/20141.
InputSetup/HoldSlewRateDeratingInputSetup/HoldSlewRatetIStIH(V/ns)(ps)(ps)1.
0000.
8+0;BACKGROUND-COLOR:#4ae2f7">50+0;BACKGROUND-COLOR:#4ae2f7">500.
6+100+100ThisderatingtableisusedtoincreasetIS/tIHinthecasewheretheinputslewrateisbelow1.
0V/ns.
2.
Minimum3CLKoftDAL(=tWR+tRP)isrequiredbecauseitneedminimum2CLKfortWRandminimum1CLKfortRP.
3.
tAC(min)valueismeasuredatthehighVdd(1.
90;BACKGROUND-COLOR:#4ae2f7">5V)andcoldtemperature(-20;BACKGROUND-COLOR:#4ae2f7">5C).
tAC(max)valueismeasuredatthelowVdd(1.
7V)andhottemperature(80;BACKGROUND-COLOR:#4ae2f7">5C).
tACismeasuredinthedevicewithhalfdriverstrengthandundertheACoutputloadcondition.
4.
ThespecificrequirementisthatDQSbevalid(HighorLow)onorbeforethisCKedge.
Thecaseshown(DQSgoingfromHigh_ZtologicLow)applieswhennowriteswerepreviouslyinprogressonthebus.
Ifapreviouswritewasinprogress,DQScouldbeHighatthistime,dependingontDQSS.
0;BACKGROUND-COLOR:#4ae2f7">5.
I/OSetup/HoldSlewRateDeratingI/OSetup/HoldSlewRatetDStDH(V/ns)(ps)(ps)1.
0000.
8+70;BACKGROUND-COLOR:#4ae2f7">5+70;BACKGROUND-COLOR:#4ae2f7">50.
6+10;BACKGROUND-COLOR:#4ae2f7">50+10;BACKGROUND-COLOR:#4ae2f7">50ThisderatingtableisusedtoincreasetDS/tDHinthecasewheretheI/Oslewrateisbelow1.
0V/ns.
6.
I/ODeltaRise/FallRate(1/slew-rate)DeratingDeltaRise/FallRatetDStDH(ns/V)(ps)(ps)0000.
20;BACKGROUND-COLOR:#4ae2f7">5+0;BACKGROUND-COLOR:#4ae2f7">50+0;BACKGROUND-COLOR:#4ae2f7">500.
0;BACKGROUND-COLOR:#4ae2f7">5+100+100ThisderatingtableisusedtoincreasetDS/tDHinthecasewheretheDQandDQSslewratesdiffer.
TheDeltaRise/FallRateiscalculatedas1/SlewRate1-1/SlewRate2.
Forexample,ifslewrate1=1.
0V/nsandslewrate2=0.
8V/ns,thentheDeltaRise/FallRate=-0.
20;BACKGROUND-COLOR:#4ae2f7">5ns/AS4C64M16MD1Confidential67Rev1.
0Mar/2014AS4C64M16MD1Confidential68Rev1.
0Mar/2014RevisionHistoryRev.
HistoryDateRemark1.
0ReleaseMar.
2014SMAllianceMemoryInc.
reservestherightstochangethespecificationsandproductswithoutnotice.
AllianceMemory,Inc.
,0;BACKGROUND-COLOR:#4ae2f7">50;BACKGROUND-COLOR:#4ae2f7">51TaylorWay,Suite#1,SanCarlos,CA94070,USATel:+160;BACKGROUND-COLOR:#4ae2f7">506106800Fax:+160;BACKGROUND-COLOR:#4ae2f7">506209211MouserElectronicsAuthorizedDistributorClicktoViewPricing,Inventory,Delivery&LifecycleInformation:AllianceMemory:AS4C64M16MD1-6BCNTRAS4C64M16MD1-6BINTR