Ambient1魅族mx

OrderingInformationSeeTable1onpage3MCIMX7DxDVx1nSDMCIMX7DxEVx1nSDNXPSemiconductorsDataSheet:TechnicalDataDocumentNumber:IMX7DCECRev.
6,03/2019PackageInformationPlasticPackageBGA12x12mm,0.
4mmpitchBGA19x19mm,0.
75mmpitch2016,2017,2019NXPB.
V.
NXPreservestherighttochangethedetailspecificationsasmayberequiredtopermitimprovementsinthedesignofitsproducts.
1i.
MX7DualintroductionThei.
MX7DualfamilyofprocessorsrepresentsNXP'slatestachievementinhigh-performanceprocessingforlow-powerrequirementswithahighdegreeoffunctionalintegration.
Theseprocessorsaretargetedtowardsthegrowingmarketofconnectedandportabledevices.
Thei.
MX7DualfamilyofprocessorsfeaturesadvancedimplementationoftheArmCortex-A7core,whichoperatesatspeedsofupto1GHzand1.
2GHz,dependingonthepartnumber.
Thei.
MX7Dualfamilyprovidesupto32-bitDDR3/DDR3L/LPDDR2/LPDDR3-1066memoryinterfaceandanumberofotherinterfacesforconnectingperipherals,suchasWLAN,Bluetooth,GPS,displays,andcamerasensors.
i.
MX7DualFamilyofApplicationsProcessorsDatasheet1i.
MX7Dualintroduction.
11.
1Orderinginformation31.
2Features42Architecturaloverview.
82.
1Blockdiagram83Moduleslist93.
1Specialsignalconsiderations163.
2Recommendedconnectionsforunusedanaloginterfaces.
194Electricalcharacteristics204.
1Chip-levelconditions204.
2IntegratedLDOvoltageregulatorparameters.
.
.
.
404.
3PLLelectricalcharacteristics.
424.
4On-chiposcillators.
424.
5I/ODCparameters434.
6I/OACparameters474.
7Outputbufferimpedanceparameters514.
8Systemmodulestiming534.
9General-purposemediainterface(GPMI)timing.
.
734.
10Externalperipheralinterfaceparameters814.
1112-BitA/Dconverter(ADC)1185Bootmodeconfiguration1195.
1Bootmodeconfigurationpins1195.
2Bootdeviceinterfaceallocation.
1206Packageinformationandcontactassignments.
1226.
112x12mmpackageinformation1226.
219x19mmpackageinformation1397Releasenotes157i.
MX7Dualintroductioni.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors2Thei.
MX7Dualfamilyofprocessorsisspecificallyusefulforapplicationssuchas:AudioConnecteddevicesAccesscontrolpanelsHuman-machineinterfaces(HMI)PortablemedicalandhealthcareIPphonesSmartappliancesPointofSaleeReadersWearablesHomeenergymanagementsystemsThefeaturesofthei.
MX7Dualfamilyofprocessorsincludethefollowing:ArmCortex-A7plusArmCortex-M4—HeterogeneousMulticoreProcessingarchitectureenablesthedevicetorunanopenoperatingsystemlikeLinux/AndroidontheCortex-A7coreandanRTOSlikeFreeRTOSontheCortex-M4core.
TwoArmCortex-A7cores—Theprocessorenhancesthecapabilitiesofportable,connectedapplicationsbyfulfillingtheever-increasingMIPSneedsofoperatingsystemsandapplicationsatlowestpowerconsumptionlevelsperMHz.
Multilevelmemorysystem—ThemultilevelCortex-A7memorysystemisbasedontheL1instructionanddatacaches,L2cache,andinternalandexternalmemory.
Theprocessorsupportsmanytypesofexternalmemorydevices,includingDDR3,DDR3L,LPDDR2andLPDDR3,NORFlash,NANDFlash(MLCandSLC),QSPIFlash,andmanagedNAND,includingeMMCrev.
Powerefficiency—PowermanagementimplementedthroughouttheICenablesfeaturesandperipheralstoconsumeminimumpowerinbothactiveandvariouslow-powermodes.
Multimedia—Themultimediaperformanceisenhancedbyamultilevelcachesystem,NEONMPE(MediaProcessorEngine)coprocessor,aprogrammablesmartDMA(SDMA)controller.
UptotwoGigabitEthernetwithAVB—10/100/1000MbpsEthernetcontrollerssupportingIEEEStd1588timesynchronization.
ElectronicPaperDisplayController(EPDC)—TheprocessorintegratesanEPDcontrollerthatsupportsEInkcolorandmonochromepanelswithupto2048x1536resolutionat106Hzrefresh,4096x4096resolutionat20Hzrefresh,and5-bitgrayscale(32-levelspercolorchannel).
Human-machineinterface(HMI)—i.
MX7Dualprocessorprovidesuptotwoseparatedisplayinterfaces(paralleldisplayandtwo-laneMIPI-DSI),CMOSsensorinterface(two-laneMIPI-CSIandparallel).
Interfaceflexibility—i.
MX7Dualprocessorsupportsconnectionstoavarietyofinterfaces:twohigh-speedUSBon-the-gomoduleswithPHY,High-SpeedInter-ChipUSB,multipleexpansioncardports(high-speedMMC/SDIOhostandother),twoGigabitEthernetcontrollerswithsupportforEthernetAVB,PCIe-II,two12-bitADCswithatotalof8single-endedinputs,twoCANports,andavarietyofotherpopularinterfaces(suchasUART,I2C,andI2S).
i.
MX7Dualintroductioni.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors3Advancedsecurity—Theprocessorsdeliverhardware-enabledsecurityfeaturesthatenablesecuree-commerce,digitalrightsmanagement(DRM),informationencryption,secureboot,andsecuresoftwaredownloads.
Thesecurityfeaturesarediscussedindetailinthei.
MX7Dualsecurityreferencemanual.
Integratedpowermanagement—Theprocessorsintegratelinearregulatorsandinternallygeneratevoltagelevelsfordifferentpowerdomains.
Thissignificantlysimplifiessystempowermanagementstructure.
Foracomprehensivelistofthei.
MX7Dualfeatures,seeSection1.
2,"Features.
"1.
1OrderinginformationTable1providesexamplesoforderablesamplepartnumberscoveredbythisdatasheet.
Table1.
OrderablepartsPartNumberOptionsCortex-A7CPUSpeedGradeQualificationTierTemperature(Tj)PackageMCIMX7D7DVK10SDEPDC,CAN2xGigabitEthernet4tamperpins1xADC1GHzConsumer10to+95°C12x12mm0.
4mmpitchBGAMCIMX7D7DVM10SDEPDC,CAN2xGigabitEthernet10tamperpins2xADC1GHzConsumer10to+95°C19x19mm0.
75mmpitchBGAMCIMX7D5EVK10SDNoEPDC,CAN2xGigabitEthernet4tamperpins1xADC1GHzIndustrial2-20to105°C12x12mm0.
4mmpitchBGAMCIMX7D5EVM10SDNoEPDC,CAN2xGigabitEthernet10tamperpins2xADC1GHzIndustrial2-20to105°C19x19mm0.
75mmpitchBGAMCIMX7D3DVK10SDNoEPDC,NoCAN2xGigabitEthernet4tamperpins1xADC1GHzConsumer10to+95°C12x12mm0.
4mmpitchBGAMCIMX7D3EVK10SDNoEPDC,NoCAN2xGigabitEthernet4tamperpins1xADC1GHzIndustrial2–20to+105°C12x12mm0.
4mmpitchBGAi.
MX7Dualintroductioni.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors4Figure1describesthepartnumbernomenclaturesothattheuserscanidentifythecharacteristicsofthespecificpartnumber.
1RestrictedelectricalspecificationsforpartswithCPUmaximumfrequencyof1.
2GHz:Temperaturerange0to85degreesC(seeTable1)VDD_ARMrequirements(seeTable9)Figure1.
Partnumbernomenclature—i.
MX7Dualfamilyofprocessors1.
2FeaturesThei.
MX7DualfamilyofprocessorsisbasedonArmCortex-A7MPCorePlatform,whichhasthefollowingfeatures:TwoArmCortex-A7Cores(withTrustZonetechnology)Thecoreconfigurationissymmetric,whereeachcoreincludes:MCIMX7D2DVK12SDNoEPDC,NoCAN2xGigabitEthernet4tamperpins1xADC1.
2GHzConsumer0to85°C12x12mm0.
4mmpitchBGAMCIMX7D2DVM12SDNoEPDC,NoCAN2xGigabitEthernet10tamperpins2xADC1.
2GHzConsumer0to85°C19x19mm0.
75mmpitchBGA1Consumerqualificationgradeassumes5-yearlifetimewith50%dutycycle.
2Industrialqualificationgradeassumes10-yearlifetimewith100%dutycycle.
Table1.
Orderableparts(continued)i.
MX7Dualintroductioni.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors5—32KByteL1InstructionCache—32KByteL1DataCache—PrivateTimerandWatchdog—NEONMPE(mediaprocessingengine)coprocessorTheArmCortex-A7Corecomplexshares:Generalinterruptcontroller(GIC)with128interruptsupportGlobaltimerSnoopcontrolunit(SCU)512KBunifiedI/DL2cacheTwomasterAXIbusinterfacesoutputofL2cacheFrequencyofthecore(includingNEONandL1cache),asperTable9.
NEONMPEcoprocessor—SIMDMediaProcessingArchitecture—NEONregisterfilewith32x64-bitgeneral-purposeregisters—NEONIntegerexecutepipeline(ALU,Shift,MAC)—NEONdual,single-precisionfloatingpointexecutepipeline(FADD,FMUL)—NEONload/storeandpermutepipelineTheArmCortex-M4platform:Cortex-M4CPUcoreMPU(memoryprotectionunit)FPU(floating-pointunit)16KByteinstructioncache16KBytedatacache64KByteTCM(tightly-coupledmemory)TheSoC-levelmemorysystemconsistsofthefollowingadditionalcomponents:—BootROM,includingHAB(96KB)—Internalmultimedia/shared,fastaccessRAM(256KBoftotalOCRAM)—Secure/nonsecureRAM(32KB)Externalmemoryinterfaces:Thei.
MX7Dualfamilyofprocessorssupportsthelatest,high-volume,costeffectiveDRAM,NOR,andNANDFlashmemorystandards.
—Upto32-bitLP-DDR2-1066,DDR3-1066,DDR3L-1066,andLPDDR3-1066—8-bitNAND-Flash,includingsupportforRawMLC/SLC,2KB,4KB,and8KBpagesize,BA-NAND,PBA-NAND,LBA-NAND,OneNANDandothers.
BCHECCupto62bits.
—16/32-bitNORFlash.
AllEIMv2pinsaremuxedonotherinterfaces.
Eachi.
MX7Dualprocessorenablesthefollowinginterfacestoexternaldevices(someofthemaremuxedandnotavailablesimultaneously):Displays—Availableinterfaces.
i.
MX7Dualintroductioni.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors6—Oneparallel24-bitdisplayport—OneEPDport—OneMIPIDSIportCamerasensors:—OneparallelCameraport(upto24bitandupto133MHzpeak)—OneMIPI-CSIportExpansioncards:—ThreeMMC/SD/SDIOcardportsallsupportingthefollowing.
Moreover,thethirdportcansupportHS400.
–1-bitor4-bittransfermodespecificationsforSDandSDIOcards,upto208MHz–1-bit,4-bit,or8-bittransfermodespecificationsforMMCcardsupto200MHzinbothSDRandDDRmodes,includingHS200andHS400DDRmodesUSB:—Twohigh-speed(HS)USB2.
0OTG(Upto480Mbps),withintegratedHSUSBPHY—Onehigh-speedUSB2.
0(480Mbps)hostwithintegratedHSICUSB(high-speedinter-chipUSB)PHYExpansionPCIExpressport(PCIe)v.
2.
1onelane—PCIExpress(Gen2.
0)dualmodecomplex,supportingrootcomplexoperationsandendpointoperations.
Usesx1PHYconfiguration.
MiscellaneousIPsandinterfaces:—ThreeinstancesofSAIsupportinguptothreeI2SandAC97ports—SevenUARTs,upto4.
0Mbps:–ProvidingRS232interface–Supporting9-bitRS485Multidropmode—FoureCSPI(EnhancedCSPI)—FourI2C,supporting400kbps—Two1-gigabitEthernetcontrollers(designedtobecompatiblewithIEEEStd1588),10/100/1000MbpswithAVBsupport—Fourpulsewidthmodulators(PWM)—SystemJTAGcontroller(SJC)—GPIOwithinterruptcapabilities—8x8keypadport(KPP)—OnequadSPI—Fourwatchdogtimers(WDOG)—One(12x12mm)ortwo(19x19mm)2-channel,12-bitanalog-to-digitalconverters(ADC)—effectivenumberofbits(ENOB)canvary(typically9–10bits)dependingonthesystemimplementationandtheconditionofthepower/groundnoiseconditioni.
MX7Dualintroductioni.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors7Thei.
MX7Dualfamilyofprocessorsintegratesadvancedpowermanagementunitandcontrollers:PMU(power-managementunit),multipleLDOsupplies,foron-chipresourcesTemperaturesensorformonitoringthedietemperatureSoftwarestateretentionandpowergatingforArmandNEONSupportforvariouslevelsofsystempowermodesFlexibleclockgatingcontrolschemeThei.
MX7Dualfamilyofprocessorsusesdedicatedhardwareacceleratorstomeetthetargetedmultimediaperformance.
Theuseofhardwareacceleratorsisakeyfactorinobtaininghighperformanceatlowpowerconsumptionnumbers,whilehavingtheCPUcorerelativelyfreeforperformingothertasks.
Thei.
MX7Dualfamilyofprocessorsincorporatesthefollowinghardwareaccelerators:PXP—PiXelprocessingpipelineforimagineresize,rotation,overlayandCSC.
OffloadingkeypixelprocessingoperationsarerequiredtosupporttheLCDandEPDCdisplayapplications.
EPDC—Low-power,high-performance,direct-drive,active-matrixelectrophoreticdisplaycontroller,specificallydesignedtodriveEInkEPDpanels.
Securityfunctionsareimplementedbythefollowinghardware:ArmTrustZonetechnologyincludingseparationofinterruptsandmemorymappingSJC—SystemJTAGController.
ProtectingJTAGfromdebugportattacksbyregulatingorblockingtheaccesstothesystemdebugfeatures.
CAAM—CryptographicAccelerationandAssuranceModule,containingcryptographicandhashengines,32KBsecureRAM,andtrueandpseudorandomnumbergenerator.
SNVS—SecureNon-VolatileStorage,includingsecurerealtimeclockCSU—CentralSecurityUnit.
Responsibleforsettingcomprehensivesecuritypolicyofthedevice.
ConfiguredduringbootandbyeFusesanddeterminesthesecurity-leveloperationmodeaswellastheTrustZonepolicy.
HAB—HighAssuranceBoot—HABv4withthenewembeddedenhancements:SHA-256,2048-bitRSAkey,SRKrevocationmechanism,warmboot,CSU,andTrustZoneinitialization.
NOTETheactualfeaturesetdependsonthepartnumbersasdescribedinTable1.
Functions,suchasdisplayandcamerainterfaces,connectivityinterfaces,maynotbeenabledforspecificpartnumbers.
Architecturaloverviewi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors82ArchitecturaloverviewThefollowingsubsectionsprovideanarchitecturaloverviewofthei.
MX7Dualprocessorsystem.
2.
1BlockdiagramFigure2showsthefunctionalmodulesinthei.
MX7Dualprocessorsystem.
Figure2.
i.
MX7DualSystemblockdiagramDebugDAPTPIUCTIsSJCSharedPeripheralsInternalMemoryOCRAM320KBROM96KBExternalMemoryDDRControllerEIMSPBAPLLsCCMGPCSRCXTALOSCRCOSCTimersSystemCounterCameraInterfaceCSIEPDControllerImageProcessingSecurityCSUOCOTP(eFuse)PowerManagementLDOsAPPeripheralsKPPSensorsModemICEPDPanelPCIeBusCameraLCDPanelTamperDetectionKeypadWLANTouchPanelControlGPMI&BCHQSPIMPUFPUNANDFLASHDisplayInterfaceLCDIFMIPIDSISmartDMASDMARDCMUSEMAPHORENEONFPUTempMonitorIOMUXADC(2)LPDDR2/LPDDR3BatteryCtrlDeviceJTAG(IEEE1149.
6)Crystal&ClockSourceNORFlash(Parallel)CAAM(32KBRAM)SNVS(SRTC)NORFLASH(QuadSPI)MIPICSI(2lane)USBOTG(dev/host)CANx2PixelProcessingPipeline(PXP)Multi-CoreUnitTCM64KBI$16KBD$16KBCortex-M4CoreARMCortexM4PlatformL2Cache512KBSCU&TimerI$32KBD$32KBCPU0CPU1ARMCortexA7MPCorePlatformWDOG(4)GPT(4)FlexTimer(2)eCSPI(3)SAI(3)UART(3)GPIO(7)UART(4)PWM(4)eCSPI(1)I2C(4)SIMv2(2)FlexCAN(2)PCIev2.
1AVBENET(2)uSDHC(3)Clock&Reset10/100/1000MEthernetx2AXIandAHBSwitchFabricMMC/SDeMMC/eSDMMC/SDSDXC/DDR3/DDR3LSmartCardx2OCOTPHost(1)/OTG(2)USB2.
0Moduleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors93ModuleslistThei.
MX7Dualfamilyofprocessorscontainsavarietyofdigitalandanalogmodules.
Table2describesthesemodulesinalphabeticalorder.
Table2.
i.
MX7DualmoduleslistBlockMnemonicBlockNameSubsystemBriefDescriptionADC1ADC2AnalogtoDigitalConverterTheADCisa12-bitgeneralpurposeanalogtodigitalconverter(ADC2isnotavailableinthe12x12package).
ArmArmPlatformArmTheArmCorePlatformincludestwoCortex-A7coresand1xCortex-M4.
Italsoincludesassociatedsub-blocks,suchastheLevel2CacheController,SCU(SnoopControlUnit),GIC(GeneralInterruptController),privatetimers,watchdog,andCoreSightdebugmodules.
BCHBinary-BCHECCProcessorSystemcontrolperipheralsTheBCHmoduleprovidesupto62-bitECCencryption/decryptionforNANDFlashcontroller(GPMI)CAAMCryptographicacceleratorandassurancemoduleSecurityCAAMisacryptographicacceleratorandassurancemodule.
CAAMimplementsseveralencryptionandhashingfunctions,arun-timeintegritychecker,entropysourcegenerator,andaPseudoRandomNumberGenerator(PRNG).
ThepseudorandomnumbergeneratoriscertifiablebyCryptographicAlgorithmValidationProgram(CAVP)ofNationalInstituteofStandardsandTechnology(NIST).
CAAMalsoimplementsaSecureMemorymechanism.
Ini.
MX7Dualprocessors,thesecuritymemoryprovidedis32KB.
CCMGPCSRCClockControlModule,GeneralPowerController,SystemResetControllerClocks,resets,andpowercontrolThesemodulesareresponsibleforclockandresetdistributioninthesystem,andalsoforthesystempowermanagement.
CSIParallelCSIMultimediaperipheralsTheCSIIPprovidesparallelCSIstandardcamerainterfaceport.
TheCSIparalleldataportsareupto24bits.
Itisdesignedtosupport24-bitRGB888/YUV444,CCIR656videointerface,8-bitYCbCr,YUVorRGB,and8-bit/10-bit/16-bitBayerdatainput.
CSUCentralSecurityUnitsecurityTheCentralSecurityUnit(CSU)isresponsibleforsettingcomprehensivesecuritypolicywithinthei.
MX7Dualplatform.
DAPDebugAccessPortSystemcontrolperipheralsTheDAPprovidesreal-timeaccessforthedebuggerwithouthaltingthecoretoaccess:SystemmemoryandperipheralregistersAlldebugconfigurationregistersTheDAPalsoprovidesdebuggeraccesstoJTAGscanchains.
Moduleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors10eCSPI1eCSPI2eCSPI3eCSPI4ConfigurableSPIConnectivityPeripheralsFull-duplexenhancedSynchronousSerialInterface,withdatarateupto52Mbit/s.
ItisconfigurabletosupportMaster/Slavemodes,fourchipselectstosupportmultipleperipherals.
EIMNOR-Flash/PSRAMinterfaceConnectivityPeripheralsTheEIMNOR-FLASH/PSRAMprovides:Supportfor16-bit(inMuxedI/Omodeonly)PSRAMmemories(syncandasyncoperatingmodes),atslowfrequencySupportfor16-bit(inmuxedandnon-muxedI/Omodes)NOR-Flashmemories,atslowfrequencyMultiplechipselectsENET1ENET2EthernetControllerConnectivityperipheralsTheEthernetMediaAccessController(MAC)isdesignedtosupport10/100/1000MbpsEthernet/IEEE802.
3networks.
Anexternaltransceiverinterfaceandtransceiverfunctionarerequiredtocompletetheinterfacetothemedia.
ThemodulehasdedicatedhardwaretosupporttheIEEE1588standard.
SeetheENETchapterofthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)fordetails.
EPDCElectrophoreticDisplayControllerConnectivityperipheralsTheEPDCisafeature-rich,lowpower,andhigh-performancedirect-drive,activematrixEPDcontroller.
ItisspecificallydesignedtodriveEInkEPDpanels,supportingawidevarietyofTFTbackplanes.
Variouslevelsofflexibilityandprogrammabilityhavebeenintroduced,aswellashardwaresupportfordifferentEInkimageenhancingalgorithms,suchasRegalDwaveformsupport.
FLEXCAN1FLEXCAN2FlexibleControllerAreaNetworkConnectivityperipheralsTheCANprotocolwasprimarily,butnotonly,designedtobeusedasavehicleserialdatabus,meetingthespecificrequirementsofthisfield:real-timeprocessing,reliableoperationintheElectromagneticinterference(EMI)environmentofavehicle,cost-effectivenessandrequiredbandwidth.
TheFlexCANmoduleisafullimplementationoftheCANprotocolspecification,Version2.
0B,whichsupportsbothstandardandextendedmessageframes.
FLEXTIMER1FLEXTIMER2FlexibleTimerModuleTimerPeripheralsProvideinputsignalcaptureandPWMsupportGPIO1GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7GeneralPurposeI/OModulesSystemcontrolperipheralsUsedforgeneralpurposeinput/outputtoexternalICs.
EachGPIOmodulesupportsupto32bitsofI/O.
GPMIGeneralPurposeMemoryInterfaceConnectivityperipheralsTheGPMImodulesupportsupto8xNANDdevicesand62-bitECCencryption/decryptionforNANDFlashController(GPMI2).
GPMIsupportsseparateDMAchannelsforeachNANDdevice.
Table2.
i.
MX7Dualmoduleslist(continued)BlockMnemonicBlockNameSubsystemBriefDescriptionModuleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors11GPTGeneralPurposeTimerTimerperipheralsEachGPTisa32-bit"free-running"or"setandforget"modetimerwithprogrammableprescalerandcompareandcaptureregister.
Atimercountervaluecanbecapturedusinganexternaleventandcanbeconfiguredtotriggeracaptureeventoneithertheleadingortrailingedgesofaninputpulse.
Whenthetimerisconfiguredtooperatein"setandforget"mode,itiscapableofprovidingpreciseinterruptsatregularintervalswithminimalprocessorintervention.
Thecounterhasoutputcomparelogictoprovidethestatusandinterruptatcomparison.
Thistimercanbeconfiguredtoruneitheronanexternalclockoronaninternalclock.
I2C1I2C2I2C3I2C4I2CInterfaceConnectivityperipheralsI2Cprovideserialinterfaceforexternaldevices.
Dataratesofupto320kbpsaresupported.
IOMUXCIOMUXControlSystemcontrolperipheralsThismoduleenablesflexibleIOmultiplexing.
EachIOpadhasdefaultandseveralalternatefunctions.
Thealternatefunctionsaresoftwareconfigurable.
KPPKeyPadPortConnectivityperipheralsKPPSupports8x8externalkeypadmatrix.
KPPfeaturesare:OpendraindesignGlitchsuppressioncircuitdesignMultiplekeysdetectionStandbykeypressdetectionLCDIFLCDinterfaceMultimediaperipheralsTheLCDIFisageneralpurposedisplaycontrollerusedtodriveawiderangeofdisplaydevicesvaryinginsizeandcapability.
TheLCDIFisdesignedtosupportdumb(synchronous24-bitParallelRGBinterface).
MIPI-CSI(two-lane)MIPICameraInterfaceMultimediaperipheralsThismoduleprovidesatwo-laneMIPIcamerainterfaceoperatinguptoamaximumbitrateof1.
5Gbps.
MIPIDSI(two-lane)MIPIDisplayInterfaceConnectivityperipheralsThismoduleprovidesatwo-laneMIPIdisplayinterfaceoperatinguptoamaximumbitrateof1.
5Gbps.
DDRCDDRControllerConnectivityperipheralsTheDDRControllerhasthefollowingfeatures:Supports16/32-bitDDR3/DDR3L,LPDDR3,andLPDDR2-1066Supportsupto2GbyteDDRmemoryspaceMQSMedium-qualitysoundmoduleMultimediaperipheralsMQSisusedtogenerate2-channel,medium-quality,PWM-likeaudio,viatwostandarddigitalGPIOpins.
TheelectronicspecificationisthesameastheGPIOdigitaloutput.
Table2.
i.
MX7Dualmoduleslist(continued)BlockMnemonicBlockNameSubsystemBriefDescriptionModuleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors12OCOTP_CTRLOTPControllerSecurityTheOn-ChipOTPcontroller(OCOTP_CTRL)providesaninterfaceforreading,programming,and/oroverridingidentificationandcontrolinformationstoredinon-chipfuseelements.
Themodulesupportselectrically-programmablepolyfuses(eFUSEs).
TheOCOTP_CTRLalsoprovidesasetofvolatilesoftware-accessiblesignalsthatcanbeusedforsoftwarecontrolofhardwareelements,notrequiringnon-volatility.
TheOCOTP_CTRLprovidestheprimaryuser-visiblemechanismforinterfacingwithon-chipfuseelements.
Amongtheusesforthefusesareuniquechipidentifiers,maskrevisionnumbers,cryptographickeys,JTAGsecuremode,bootcharacteristics,andvariouscontrolsignals,requiringpermanentnon-volatility.
OCRAMOn-ChipMemorycontrollerDatapathTheOn-ChipMemorycontroller(OCRAM)moduleisdesignedasaninterfacebetweensystem'sAXIbusandinternal(on-chip)SRAMmemorymodule.
Ini.
MX7Dualprocessors,theOCRAMisusedforcontrollingthe128KBmultimediaRAMthrougha64-bitAXIbus.
PCIePCIExpress2.
0ConnectivityperipheralsThePCIeIPprovidesPCIExpressGen2.
0functionality.
PMUPowerManagementUnitDatapathIntegratedpowermanagementunit.
UsedtoprovidepowertovariousSoCdomains.
PWM1PWM2PWM3PWM4PulseWidthModulationConnectivityperipheralsThepulse-widthmodulator(PWM)hasa16-bitcounterandisoptimizedtogeneratesoundfromstoredsampleaudioimagesanditcanalsogeneratetones.
Ituses16-bitresolutionanda4x16dataFIFOtogeneratesound.
PXPPiXelProcessingPipelineDisplayperipheralsAhigh-performancepixelprocessorcapableof1pixel/clockperformanceforcombinedoperations,suchascolor-spaceconversion,alphablending,gamma-mapping,androtation.
ThePXPisenhancedwithfeaturesspecificallyforgrayscaleapplications.
Inaddition,thePXPsupportstraditionalpixel/frameprocessingpathsforstill-imageandvideoprocessingapplications,allowingittointerfacewiththeintegratedEPD.
Table2.
i.
MX7Dualmoduleslist(continued)BlockMnemonicBlockNameSubsystemBriefDescriptionModuleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors13QSPIQuadSPIConnectivityperipheralsQuadSPImoduleactasaninterfacetoexternalserialflashdevices.
Thismodulecontainsthefollowingfeatures:FlexiblesequenceenginetosupportvariousflashvendordevicesSinglepad/Dualpad/QuadpadmodeofoperationSingleDataRate/DoubleDataRatemodeofoperationParallelFlashmodeDMAsupportMemorymappedreadaccesstoconnectedflashdevicesMulti-masteraccesswithpriorityandflexibleandconfigurablebufferforeachmasterSAI1SAI2SAI3SynchronousAudioInterfaceConnectivityperipheralsTheSAImoduleprovidesasynchronousaudiointerface(SAI)thatsupportsfullduplexserialinterfaceswithframesynchronization,suchasI2S,AC97,TDM,andcodec/DSPinterfaces.
SDMASmartDirectMemoryAccessSystemcontrolperipheralsTheSDMAisamultichannelflexibleDMAengine.
Ithelpsinmaximizingsystemperformancebyoffloadingthevariouscoresindynamicdatarouting.
Ithasthefollowingfeatures:Poweredbya16-bitInstruction-Setmicro-RISCengineMulti-channelDMAsupportingupto32time-divisionmultiplexedDMAchannels48eventswithtotalflexibilitytotriggeranycombinationofchannelsMemoryaccessesincludinglinear,FIFO,and2DaddressingSharedperipheralsbetweenArmandSDMAVeryfastContext-Switchingwith2-levelprioritybasedpreemptivemulti-taskingDMAunitswithauto-flushandprefetchcapabilityFlexibleaddressmanagementforDMAtransfers(increment,decrement,andnoaddresschangesonsourceanddestinationaddress)DMAportscanhandleunidirectionalandbidirectionalflows(Copymode)Upto8-wordbufferforconfigurablebursttransfersforEMIv2.
5Supportofbyte-swappingandCRCcalculationsLibraryofScriptsandAPIisavailableSIMv2-1SIMv2-2SmartCardConnectivityperipheralsSmartcardinterfacedesignedtobecompatiblewithISO7816.
Table2.
i.
MX7Dualmoduleslist(continued)BlockMnemonicBlockNameSubsystemBriefDescriptionModuleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors14SJCSystemJTAGControllerSystemcontrolperipheralsTheSJCprovidesJTAGinterface(designedtobecompatiblewithJTAGTAPstandards)tointernallogic.
Thei.
MX7DualfamilyofprocessorsusesJTAGportforproduction,testing,andsystemdebugging.
Additionally,theSJCprovidesBSR(BoundaryScanRegister)standardsupport,designedtobecompatiblewithIEEE1149.
1andIEEE1149.
6standards.
TheJTAGportmustbeaccessibleduringplatforminitiallaboratorybring-up,formanufacturingtestsandtroubleshooting,aswellasforsoftwaredebuggingbyauthorizedentities.
Thei.
MX7DualSJCincorporatesthreesecuritymodesforprotectingagainstunauthorizedaccesses.
ModesareselectedthrougheFUSEconfiguration.
SNVSSecureNon-VolatileStorageSecuritySecureNon-VolatileStorage,includingSecureRealTimeClock,SecurityStateMachine,MasterKeyControl,andViolation/TamperDetectionandreporting.
TEMPSENSORTemperatureSensorSystemcontrolperipheralsTemperaturesensorTZASCTrust-ZoneAddressSpaceControllerSecurityTheTZASC(TZC-380byArm)providessecurityaddressregioncontrolfunctionsrequiredforintendedapplication.
ItisusedonthepathtotheDRAMcontroller.
UART1UART2UART3UART4UART5UART6UART7UARTInterfaceConnectivityperipheralsEachoftheUARTv2modulessupportthefollowingserialdatatransmit/receiveprotocolsandconfigurations:7-or8-bitdatawords,1or2stopbits,programmableparity(even,oddornone)Programmablebaudratesupto4Mbps.
Thisisahighermaxbaudraterelativetothe1.
875MHz,whichisstatedbytheTIA/EIA-232-Fstandard.
32-byteFIFOonTxand32half-wordFIFOonRxsupportingauto-baudTable2.
i.
MX7Dualmoduleslist(continued)BlockMnemonicBlockNameSubsystemBriefDescriptionModuleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors15uSDHC1uSDHC2uSDHC3SD/MMCandSDXCEnhancedMulti-MediaCard/SecureDigitalHostControllerConnectivityperipheralsi.
MX7DualSoCcharacteristics:AlltheMMC/SD/SDIOcontrollerIPsarebasedontheuSDHCIP.
Theyaredesignedtobe:FullycompatiblewithMMCcommand/responsesetsandPhysicalLayerasdefinedintheMultimediaCardSystemSpecification,v5.
0/v4.
4/v4.
41/v4.
4/v4.
3/v4.
2.
FullycompatiblewithSDcommand/responsesetsandPhysicalLayerasdefinedintheSDMemoryCardSpecificationsv3.
0includinghigh-capacitySDXCcardsupto2TB.
FullycompatiblewithSDIOcommand/responsesetsandinterrupt/Read-WaitmodeasdefinedintheSDIOCardSpecification,PartE1,v.
3.
0Alltheportssupport:1-bitor4-bittransfermodespecificationsforSDandSDIOcardsuptoUHS-ISDR104mode(104MB/smax)1-bit,4-bit,or8-bittransfermodespecificationsforMMCcardsupto200MHzinbothSDRandDDRmodes,includingHS200andHS400.
However,theSoClevelintegrationandI/Omuxinglogicrestrictthefunctionalitytothefollowing:uSDHC1anduSDHC2areprimarilyintendedtoserveasexternalslotsorinterfacestoon-boardSDIOdevices.
Theseportsareequippedwith"Carddetection"and"WriteProtection"padsanddonotsupporthardwarereset.
uSDHC3isprimarilyintendedtoserveinterfacestoembeddedMMCmemoryorinterfacestoon-boardSDIOdevices.
Theseportsdonothave"Carddetection"and"WriteProtection"padsanddosupporthardwarereset.
Allportscanworkwith1.
8Vand3.
3Vcards.
TherearetwocompletelyindependentI/OpowerdomainsforuSDHC1anduSDHC2in4-bitconfiguration(SDinterface).
uSDHC3isplacedinhisownindependentpowerdomain.
USBOTG22xUSB2.
0HighSpeedOTGandHSICUSBConnectivityperipheralsUSBOTG2contains:Twohigh-speedOTGmoduleswithintegratedHSUSBPHYsOnehigh-speedHostmoduleconnectedtoHSICUSBport.
Table2.
i.
MX7Dualmoduleslist(continued)BlockMnemonicBlockNameSubsystemBriefDescriptionModuleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors163.
1SpecialsignalconsiderationsTable3listsspecialsignalconsiderationsforthei.
MX7Dualfamilyofprocessors.
Thesignalnamesarelistedinalphabeticalorder.
WDOG1WDOG3WDOG4WatchdogTimerperipheralsTheWatchdogtimersupportstwocomparisonpointsduringeachcountingperiod.
EachofthecomparisonpointsisconfigurabletoevokeaninterrupttotheArmcore,andasecondpointevokesanexternaleventontheWDOGline.
WDOG2(TrustZone)Watchdog(TrustZonetechnology)TimerperipheralsTheTrustZoneWatchdog(TZWDOG)timermoduleprotectsagainstTrustZonestarvationbyprovidingamethodofescapingNormalmodeandforcingaswitchtotheTZmode.
TZstarvationisasituationwherethenormalOSpreventsswitchingtotheTZmode.
Suchsituationisundesirableasitcancompromisethesystem'ssecurity.
OncetheTZWDOGmoduleisactivated,itmustbeservicedbyTZsoftwareonaperiodicbasis.
Ifservicingdoesnottakeplace,thetimertimesout.
Uponatime-out,theTZWDOGassertsaTZmappedinterruptthatforcesswitchingtotheTZmode.
Ifitisstillnotserved,theTZWDOGassertsasecurityviolationsignaltotheCSU.
TheTZWDOGmodulecannotbeprogrammedordeactivatedbyanormalmodeSW.
Table2.
i.
MX7Dualmoduleslist(continued)BlockMnemonicBlockNameSubsystemBriefDescriptionModuleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors17ThepackagecontactassignmentscanbefoundinSection6,"Packageinformationandcontactassignments.
"Signaldescriptionsareprovidedinthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
Table3.
SpecialsignalconsiderationsSignalNameRemarksCCM_CLK1_P/CCM_CLK1_NCCM_CLK2Onegeneralpurposedifferentialhighspeedclockinput/outputandonesingle-endedclockinputareprovided.
Eitherorbothofthemcanbeused:TofeedanexternalreferenceclocktothePLLsandtothemodulesinsidetheSoC,forexample,asanalternatereferenceclockforPCIe,Video/Audiointerfacesandsoforth.
TooutputtheinternalSoCclocktobeusedoutsidetheSoCaseitherareferenceclockorasafunctionalclockforperipherals;forexample,itcanbeusedasanoutputofthePCIemasterclock(rootcomplexuse)Seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)fordetailsontherespectiveclocktrees.
TheCCM_CLK1_*inputs/outputsareanLVDSdifferentialpair.
Alternatively,asingle-endedsignalmaybeusedtodriveCCM_CLK1_Pinput.
InthiscasecorrespondingCCM_CLK1_Ninputshouldbetiedtotheconstantvoltagelevelequalto1/2oftheinputsignalswing.
Terminationshouldbeprovidedincaseofhighfrequencysignals.
SeetheLVDSpadelectricalspecificationforfurtherdetails.
CCM_CLK2isasingle-endedinputreferencedtoground.
Afterinitialization:TheCCM_CLK1_*inputs/outputscanbedisabledifnotused.
AnyoftheunusedCCM_CLK1_*pinsmaybeleftfloating.
TheCCM_CLK2inputshouldbegroundedifnotused.
RTC_XTALI/RTC_XTALOIftheuserwishestoconfigureRTC_XTALIandRTC_XTALOasanRTCoscillator,a32.
768kHzcrystal,(100kESR,10pFload)shouldbeconnectedbetweenRTC_XTALIandRTC_XTALO.
ItisrecommendedtousetheconfigurableloadcapacitorsprovidedintheIPinsteadofaddingthemexternally.
Tohittheexactoscillationfrequency,theconfigurablecapacitorsneedtobereducedtoaccountforboardandchipparasitics.
Theintegratedoscillationamplifierisselfbiasing,butrelativelyweak.
CaremustbetakentolimitparasiticleakagefromRTC_XTALIandRTC_XTALOtoeitherpowerorground(>100M).
Thiswilldebiastheamplifierandcauseareductionofstartupmargin.
TypicallyRTC_XTALIandRTC_XTALOshouldbiastoapproximately0.
5V.
IfitisdesiredtofeedanexternallowfrequencyclockintoRTC_XTALI,theRTC_XTALOpinshouldbeleftfloatingordrivenwithacomplimentarysignal.
ThelogiclevelofthisforcingclockshouldnotexceedVDD_SNVS_CAPlevel.
Inthecasewhenahigh-accuracyrealtimeclockisnotrequired,thesystemmayuseinternallowfrequencyoscillator.
ItisrecommendedtoconnectRTC_XTALItogroundandkeepRTC_XTALOfloating.
Thiswillhoweverresultinincreasedpowerconsumption,becausetheinternaloscillatoruseshigherpowerthantheRTCoscillator.
Thusforlowestpowerconfigurationitisrecommendedtoalwaysinstallacrystal.
XTALI/XTALOA24.
0MHzcrystalshouldbeconnectedbetweenXTALIandXTALO.
Moduleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors18DRAM_VREFWhenusingDDR_VREFwithDDRI/O,thenominalreferencevoltagemustbehalfoftheNVCC_DRAMsupply.
TheusermusttieDDR_VREFtoaprecisionexternalresistordivider.
Usea1kΩ0.
5%resistortoGNDanda1kΩ0.
5%resistortoNVCC_DRAM.
Shunteachresistorwithaclosely-mounted0.
1Fcapacitor.
Toreducesupplycurrent,apairof1.
5kΩ0.
1%resistorscanbeused.
Usingresistorswithrecommendedtolerancesensuresthe±2%DDR_VREFtolerance(pertheDDR3specification)ismaintainedwhenfourDDR3ICsplusthei.
MX7Dualaredrawingcurrentontheresistordivider.
Itisrecommendedtouseregulatedpowersupplyfor"big"memoryconfigurations(morethaneightdevices)ZQPADDRAMcalibrationresistor240Ω1%usedasreferenceduringDRAMoutputbufferdrivercalibrationshouldbeconnectedbetweenthispadandGND.
PCIE_VPH/PCIE_VPH_TX/PCIE_VPH_RXShortthesepinstoVDDA_PHY1P8ifusingPCIe.
UsercantiethesepinstogroundifnotusingPCIe.
PCIE_VP/PCIE_VP_TX/PCIE_VP_RXShortthesepinstoVDDD_1P0CAPifusingPCIe.
Usercantiethesepinstogroundwitha10KΩresistorifnotusingPCIe.
VDDA_MIPI_1P8ShortthesepinstoVDDA_PHY_1P8ifusingMIPI.
UsercanleavethesepinsfloatingorgroundedifnotusingMIPI.
VDD_MIPI_1P0ShortthesepinstoVDDD_1P0_CAPifusingMIPI.
UsercanleavethesepinsfloatingorgroundedifnotusingMIPI.
GPANAIOThissignalisreservedformanufacturinguseonly.
Usermustleavethisconnectionfloating.
JTAG_nnnnTheJTAGinterfaceissummarizedinTable4.
Useofexternalresistorsisunnecessary.
However,ifexternalresistorsareused,theusermustensurethattheon-chippull-up/downconfigurationisfollowed.
Forexample,donotuseanexternalpulldownonaninputthathason-chippull-up.
JTAG_TDOisconfiguredwithakeepercircuitsuchthatthefloatingconditioniseliminatedifanexternalpullresistorisnotpresent.
AnexternalpullresistoronJTAG_TDOisdetrimentalandshouldbeavoided.
JTAG_MODisreferencedasSJC_MODinthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
Bothnamesrefertothesamesignal.
JTAG_MODmustbeexternallyconnectedtoGNDfornormaloperation.
TerminationtoGNDthroughanexternalpull-downresistor(suchas1kΩ)isallowed.
JTAG_MODsettohighconfigurestheJTAGinterfacetoamodecompatiblewiththeIEEE1149.
1standard.
JTAG_MODsettolowconfigurestheJTAGinterfaceforcommonSWdebugaddingallthesystemTAPstothechain.
NCDonotconnect.
Thesesignalsarereservedandshouldbefloatedbytheuser.
POR_BThiscoldresetnegativelogicinputresetsallmodulesandlogicintheIC.
Maybeusedinadditiontointernallygeneratedpoweronresetsignal(logicalAND,bothinternalandexternalsignalsareconsideredactivelow).
ONOFFInNormalmode,maybeconnectedtoON/OFFbutton(De-bouncingprovidedatthisinput).
Internallythispadispulledup.
ShortconnectiontoGNDinOFFmodecausesinternalpowermanagementstatemachinetochangestatetoON.
InONmodeshortconnectiontoGNDgeneratesinterrupt(intendedtoSWcontrollablepowerdown).
Longabove~5sconnectiontoGNDcauses"forced"OFF.
TEST_MODETEST_MODEisforfactoryuse.
Thissignalisinternallyconnectedtoanon-chippull-downdevice.
TheusermusttiethissignaltoGND.
Table3.
Specialsignalconsiderations(continued)SignalNameRemarksModuleslisti.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors193.
2RecommendedconnectionsforunusedanaloginterfacesTable5showstherecommendedconnectionsforunusedanaloginterfaces.
PCIE_REXTTheimpedancecalibrationprocessrequiresconnectionofreferenceresistor4.
7KΩ1%precisionresistoronPCIE_REXTpadtoground.
USB_OTG1_REXT/USB_OTG2_REXTThebiasgenerationandimpedancecalibrationprocessfortheUSBOTGPHYsrequiresconnectionof200Ω(1%precision)referenceresistorsoneachoftheUSB_OTG1_REXTandUSB_OTG2_REXTpadstoground.
USB_OTG1_CHD_BAnexternalpullupresistorwithvalueinrangefrom10kΩto100kΩshouldbeconnectedbetweenopen-drainoutputUSB_OTG1_CHD_BandsupplyVDD_USB_OTG1_3P3_INfor3.
3Vsignaling.
Optionally,asimilarlyvaluedpullupresistorcouldbeconnectedinsteadbetweenUSB_OTG1_CHD_Bandanunrelatedsupplyupto1.
8V,butinthatcasetheoutputisonlyvalidwhenboththatsupplyandVDD_USB_OTG1_3P3_INarepowered.
TEMPSENSOR_REXTExternal100KΩ(1%precision)resistorconnectionpinTable4.
JTAGcontrollerinterfacesummaryJTAGI/OTypeOn-chipTerminationJTAG_TCKInput47kΩpull-upJTAG_TMSInput47kΩpull-upJTAG_TDIInput47kΩpull-upJTAG_TDO3-stateoutput100kΩpull-upJTAG_TRSTBInput47kΩpull-upJTAG_MODInput100kΩpull-upTable5.
RecommendedconnectionsforunusedanaloginterfacesModulePackageNetNameRecommendationifUnusedADCVDDA_ADC2_1P8,VDDA_ADC2_1P8,VDDA_ADC1_1P8,VDDA_ADC1_1P81.
8VADC2_IN3,ADC2_IN2,ADC2_IN1,ADC2_IN0,ADC1_IN0,ADC1_IN1,ADC1_IN2,ADC1_IN3TietogroundLDOVDD_1P2_CAPFloatingifUSB_HSICisnotusedMIPIVDD_MIPI_1P0,VDDA_MIPI_1P8FloatingortietogroundMIPI_DSI_D0_N,MIPI_DSI_D0_P,MIPI_VREG_0P4V,MIPI_DSI_CLK_N,MIPI_DSI_CLK_P,MIPI_DSI_D1_N,MIPI_DSI_D1_P,MIPI_CSI_D0_N,MIPI_CSI_D0_P,MIPI_CSI_CLK_N,MIPI_CSI_CLK_P,MIPI_CSI_D1_N,MIPI_CSI_D1_PNoconnectTable3.
Specialsignalconsiderations(continued)SignalNameRemarksElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors204ElectricalcharacteristicsThissectionprovidesthedeviceandmodule-levelelectricalcharacteristicsforthei.
MX7Dualfamilyofprocessors.
4.
1Chip-levelconditionsThissectionprovidesthedevice-levelelectricalcharacteristicsfortheIC.
SeeTable6foraquickreferencetotheindividualtablesandsections.
PCIePCIE_REFCLKIN_N,PCIE_REFCLKIN_P,PCIE_REFCLKOUT_N,PCIE_REFCLKOUT_P,PCIE_RX_N,PCIE_RX_P,PCIE_TX_N,PCIE_TX_PFloatingPCIE_VP,PCIE_VP_RX,PCIE_VP_TX,PCIE_VPH,PCIE_VPH_RX,PCIE_VPH_TX,PCIE_REXTTietogroundSNVSSNVS_TAMPER00,SNVS_TAMPER01,SNVS_TAMPER02,SNVS_TAMPER03,SNVS_TAMPER04,SNVS_TAMPER05,SNVS_TAMPER06,SNVS_TAMPER07,SNVS_TAMPER08,SNVS_TAMPER09Float—configurewithsoftwareTemperaturesensorTEMPSENSOR_REXTTietogroundorpulldownwith100KΩresistorTEMPSENSOR_RESERVEFloatingVDD_TEMPSENSOR_1P81.
8VUSBHSICVDD_USB_H_1P2TietogroundUSB_H_DATA,USB_H_STROBEFloatingUSBOTG1VDD_USB_OTG1_3P3_IN,VDD_USB_OTG1_1P0_CAPTietogroundUSB_OTG1_VBUS,USB_OTG1_DP,USB_OTG1_DN,USB_OTG1_ID,USB_OTG1_REXT,USB_OTG1_CHD_BFloatingUSBOTG2VDD_USB_OTG2_3P3_IN,VDD_USB_OTG2_1P0_CAPTietogroundUSB_OTG2_VBUS,USB_OTG2_DP,USB_OTG2_DN,USB_OTG2_ID,USB_OTG2_REXTFloatingTable6.
i.
MX7DualChip-levelconditionsForthesecharacteristics,…Topicappears…Absolutemaximumratingsonpage21FPBGAcase"X"andcase"Y"packagethermalresistanceonpage22Operatingrangesonpage23Externalclocksourcesonpage25Table5.
Recommendedconnectionsforunusedanaloginterfaces(continued)ModulePackageNetNameRecommendationifUnusedElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors214.
1.
1AbsolutemaximumratingsCAUTIONStressesbeyondthoselistedunderTable7mayaffectreliabilityorcausepermanentdamagetothedevice.
Thesearestressratingsonly.
Functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedintheoperatingrangesorparameterstablesisnotimplied.
Maximumsupplycurrentsonpage26Powermodesonpage29USBPHYSuspendcurrentconsumptiononpage32Table7.
AbsolutemaximumratingsParameterDescriptionSymbolMinMaxUnitCoresupplyvoltagesVDD_ARMVDD_SOC–0.
51.
5VGPIOsupplyvoltageNVCC_ENET1NVCC_EPDC1NVCC_EPDC2NVCC_I2CNVCC_LCDNVCC_SAINVCC_SD1NVCC_SD2NVArmCC_SD3NVCC_SPINVCC_UART–0.
33.
6VDDRI/OsupplyvoltageNVCC_DRAM–0.
31.
975VClockI/OsupplyvoltageNVCC_DRAM_CKE–0.
31.
98VVDD_SNVS_INsupplyvoltageVDD_SNVS_IN–0.
33.
6VUSBOTGPHYsupplyvoltageVDD_USB_OTG1_3P3_INVDD_USB_OTG2_3P3_IN–0.
33.
6VUSB_VBUSinputdetectedUSB_OTG1_VBUSUSB_OTG2_VBUS–0.
35.
25VInputvoltageonUSB_OTG*_DP,USB_OTG*_DNpinsUSB_OTG1_DP/USB_OTG1_DNUSB_OTG2_DP/USB_OTG2_DN–0.
33.
63VUSB_OTG1_CHD_Bopen-drainpullupvoltagewhenexternalpullupresistorisconnectedtoVDD_USB_OTG1_3P3_INsupplyonlyUSB_OTG1_CHD_B—3.
6VTable6.
i.
MX7DualChip-levelconditions(continued)Forthesecharacteristics,…Topicappears…Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors224.
1.
2Thermalresistance4.
1.
2.
1FPBGAcase"X"andcase"Y"packagethermalresistanceTable8displaysthethermalresistancedata.
PerJEDECJESD51-2,theintentofthermalresistancemeasurementsissolelyforathermalperformancecomparisonofonepackagetoanotherinastandardizedenvironment.
Thismethodologyisnotmeanttoanddoesnotpredicttheperformanceofapackageinanapplication-specificenvironment.
USB_OTG1_CHD_Bopen-drainpullupvoltagewhenexternalpullupresistorisconnectedtoanysupplyotherthanVDD_USB_OTG1_3P3_INUSB_OTG2_CHD_B—1.
975VInput/outputvoltagerangeVin/Vout–0.
3OVDD1+0.
3VESDdamageimmunity:VesdVHumanBodyModel(HBM)ChargeDeviceModel(CDM)——2000500StoragetemperaturerangeTSTORAGE–40150oC1OVDDistheI/Osupplyvoltage.
Table8.
ThermalResistanceDataRatingTestconditionsSymbol12x12pkgvalue19x19pkgvalueUnitJunctiontoAmbient11Junctiontemperatureisafunctionofdiesize,on-chippowerdissipation,packagethermalresistance,mountingsite(board)temperature,ambienttemperature,airflow,powerdissipationofothercomponentsontheboard,andboardthermalresistance.
Single-layerboard(1s);naturalconvection2Four-layerboard(2s2p);naturalconvection22PerJEDECJESD51-2withthesinglelayerboardhorizontal.
ThermaltestboardmeetsJEDECspecificationforthespecifiedpackage.
RθJARθJA55.
432.
644.
430.
2oC/WoC/WJunctiontoAmbient1Single-layerboard(1s);airflow200ft/min2,3Four-layerboard(2s2p);airflow200ft/min2,33PerJEDECJESD51-6withtheboardhorizontal.
RθJARθJA41.
828.
034.
325.
8oC/WoC/WJunctiontoBoard1,44ThermalresistancebetweenthedieandtheprintedcircuitboardperJEDECJESD51-8.
Boardtemperatureismeasuredonthetopsurfaceoftheboardnearthepackage.
—RθJB16.
017.
4oC/WJunctiontoCase1,5—RθJC10.
510.
4oC/WJunctiontoPackageTop1,6NaturalConvectionΨJT0.
20.
2oC/WJunctiontoPackageBottomNaturalConvectionRθB_CSB15.
317.
3oC/WTable7.
Absolutemaximumratings(continued)ParameterDescriptionSymbolMinMaxUnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors234.
1.
3OperatingrangesTable9providestheoperatingrangesofthei.
MX7Dualfamilyofprocessors.
Fordetailsonthechip'spowerstructure,seethe"PowerManagementUnit(PMU)"chapterofthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
5Thermalresistancebetweenthedieandthecasetopsurfaceasmeasuredbythecoldplatemethod(MILSPEC-883Method1012.
1).
6ThermalcharacterizationparameterindicatingthetemperaturedifferencebetweenpackagetopandthejunctiontemperatureperJEDECJESD51-2.
WhenGreeklettersarenotavailable,thethermalcharacterizationparameteriswrittenasPsi-JT.
Table9.
OperatingrangesParameterDescriptionSymbolMinTypMax1UnitCommentRunModeVDD_ARM0.
951.
01.
25VOperationat800MHzandbelow1.
0451.
11.
25VOperationbetween800MHzand1GHz1.
21.
2251.
25VOperationbetween1.
0GHzand1.
2GHz.
SeeTable1formaximumfrequencies.
VDD_SOC0.
951.
01.
25V—Standby/DeepSleepmodeVDD_ARM01.
01.
25VSeeTable14,"Powermodes,"onpage29.
VDD_SOC0.
951.
01.
155VPowerSupplyAnalogDomainandLDOsVDDA_1P81.
711.
81.
89VPowerforanalogLDOandinternalanalogblocks.
Mustmatchtherangeofvoltagesthattherechargeablebackupbatterysupports.
BackupbatterysupplyrangeVDD_SNVS_IN2.
43.
03.
6V—LDOforLow-PowerStateRetentionmodeVDD_LPSR1.
711.
81.
89VPowerrailforLowPowerStateRetentionmodeSupplyfor24MHzcrystalVDD_XTAL_1P81.
6501.
81.
950V—TemperaturesensorVDD_TEMPSENSOR1.
7101.
81.
890V—USBsupplyvoltagesVDD_USB_OTG1_3P3_IN3.
03.
33.
6VThisrailisforUSBVDD_USB_OTG2_3P3_IN3.
03.
33.
6VThisrailisforUSBElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors24DDRI/OsupplyvoltageNVCC_DRAM,NVCC_DRAM_CKE1.
141.
21.
3VLPDDR2,LPDDR31.
4251.
51.
575VDDR31.
2831.
351.
45VDDR3LDRAM_VREF0.
49*NVCC_DRAM)0.
5*NVCC_DRAM0.
51*NVCC_DRAMVSettoone-halfNVCC_DRAMGPIOsupplyvoltagesNVCC_ENET1NVCC_EPDC1NVCC_EPDC2NVCC_I2CNVCC_LCDNVCC_SAINVCC_SD1NVCC_SD2NVCC_SD3NVCC_SPINVCC_UART1.
65,3.
01.
8,3.
31.
95,3.
6V—NVCC_GPIO11.
653.
01.
8,3.
31.
95,3.
6VPowerforGPIO1_DATA00~GPIO1_DATA07NVCC_GPIO21.
653.
01.
8,3.
31.
95,3.
6VPowerforGPIO1_DATA08~GPIO1_DATA15andJTAGportVoltagerailssuppliedfrominternalLDOPCIE_VPHPCIE_VPH_RXPCIE_VPH_TXVDDA_MIPI_1P81.
711.
81.
89VSuppliedfromVDDA_PHY_1P8PCIE_VPPCIE_VP_RXPCIE_VP_TXVDD_MIPI_1P00.
951.
01.
050VSuppliedfromVDDD_CAP_1P0VDD_USB_H_1P21.
1501.
21.
250VSuppliedfromVDD_1P2_CAPTemperaturesensoraccuracyTdelta—±3—°CTypicalaccuracyovertherange–40°Cto125°CA/DconverterVDDA_ADC1_1P81.
711.
81.
89V—VDDA_ADC2_1P81.
711.
81.
89V—FusepowerFUSE_FSOURCE1.
7101.
81.
890VPowersupplyforinternaluseJunctiontemperature,industrialTJ-20—105oCSeeTable1forcompletelistofjunctiontemperaturecapabilities.
1Applyingthemaximumvoltageresultsinmaximumpowerconsumptionandheatgeneration.
Avoltagesetpoint=(Vmin+thesupplytolerance)isrecommended.
Thisresultsinanoptimizedpower/speedratio.
Operatingavoltageof1.
2Vandabovewillreducetheoveralllifetimeofthepart.
Fordetails,seei.
MX7Dual/SoloProductLifetimeUsage(AN5334).
Table9.
Operatingranges(continued)ParameterDescriptionSymbolMinTypMax1UnitCommentElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors25Table10showson-chipLDOregulatorsthatcansupplyon-chiploads.
4.
1.
4ExternalclocksourcesEachi.
MX7Dualprocessorhastwoexternalinputsystemclocks:alowfrequency(RTC_XTALI)andahighfrequency(XTALI).
TheRTC_XTALIisusedforlow-frequencyfunctions.
Itsuppliestheclockforwake-upcircuit,power-downrealtimeclockoperation,andslowsystemandwatch-dogcounters.
Theclockinputcanbeconnectedtoeitherexternaloscillatororacrystalusinginternaloscillatoramplifier.
Additionally,thereisaninternalresistor-capacitor(RC)oscillator,whichcanbeusedinsteadoftheRTC_XTALIifaccuracyisnotimportant.
ThesystemclockinputXTALIisusedtogeneratethemainsystemclock.
ItsuppliesthePLLsandotherperipherals.
Thesystemclockinputcanbeconnectedtoeitheranexternaloscillatororacrystalusinginternaloscillatoramplifier.
Table11showstheinterfacefrequencyrequirements.
Table10.
On-chipLDOs1andtheiron-chiploads1On-chipLDOsaredesignedtosupplyi.
MX7Dualloadsandmustnotbeusedtosupplyexternalloads.
VoltageSourceLoadCommentVDDD_1P0_CAPVDD_MIPI_1P0Connectdirectly(short)viaboardlevelPCIE_VPPCIE_VP_RXPCIE_VP_TXVDD_1P2_CAPVDD_USB_H_1P2Connectdirectly(short)viaboardlevelVDDA_PHY_1P8VDDA_MIPI_1P8Connectdirectly(short)viaboardlevelPCIE_VPHPCIE_VPH_RXPCIE_VPH_TXTable11.
ExternalinputclockfrequencyParameterDescriptionSymbolMinTypMaxUnitRTC_XTALIOscillator1,21Externaloscillatororacrystalwithinternaloscillatoramplifier.
2Therequiredfrequencystabilityofthisclocksourceisapplicationdependent.
SeeHardwareDevelopmentGuidefori.
MX7Dualand7SoloApplicationsProcessors.
fckil—32.
76833Recommendednominalfrequency32.
768kHz.
—kHzXTALIOscillator2,44Externaloscillatororafundamentalfrequencycrystalappropriatelycoupledtotheinternaloscillatoramplifier.
fxtal24MHzElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors26ThetypicalvaluesshowninTable11arerequiredforusewithNXPBSPstoensureprecisetimekeepingandUSBoperation.
ForRTC_XTALIoperation,twoclocksourcesareavailable.
IfthereisnotanexternallyappliedoscillatortoRTC_XTALI,theinternaloscillatortakesover.
On-chip32kHzRCoscillator—thisclocksourcehasthefollowingcharacteristics:—Approximately25AmoreIDDthancrystaloscillator—Approximately±10%tolerance—Noexternalcomponentrequired—Startsupfasterthan32kHzcrystaloscillator—Threeconfigurationsforthisinput:–Externaloscillator–ExternalcrystalcoupledtoRTC_XTALIandRTC_XTALO–InternaloscillatorExternalcrystaloscillatorwithon-chipsupportcircuit:—Atpowerup,RCoscillatorisutilized.
Aftercrystaloscillatorisstable,theclockcircuitswitchesovertothecrystaloscillatorautomatically.
—HigheraccuracythanRCoscillator—Ifnoexternalcrystalispresent,thentheRCoscillatorisutilizedThedecisionofchoosingaclocksourceshouldbetakenbasedonreal-timeclockuseandprecisiontimeout.
4.
1.
5MaximumsupplycurrentsThePowerVirusnumbersshowninTable12representausecasedesignedspecificallytoshowthemaximumcurrentconsumptionpossible.
AllcoresarerunningatthedefinedmaximumfrequencyandarelimitedtoL1cacheaccessesonlytoensurenopipelinestalls.
Althoughavalidcondition,itwouldhaveaverylimitedpracticalusecase,ifatall,andbelimitedtoanextremelylowdutycycleunlesstheintentionwastospecificallyshowtheworstcasepowerconsumption.
TheMC3xPF3000xxxx,NXP'spowermanagementICtargetedforthei.
MX7Dualfamilyofprocessors,supportsthePowerVirusmodeoperatingat1%dutycycle.
Higherdutycyclesareallowed,butarobustthermaldesignisrequiredfortheincreasedsystempowerdissipation.
Table12representsthemaximummomentarycurrenttransientsonpowerlines,andshouldbeusedforpowersupplyselection.
Maximumcurrentsarehigherbyfarthantheaveragepowerconsumptionoftypicalusecases.
Fortypicalpowerconsumptioninformation,seetheapplicationnote,i.
MX7DSPowerConsumptionMeasurement(AN5383).
Table12.
MaximumsupplycurrentsPowerRailSourceConditionsMaxCurrentUnitVDD_ARMFromPMIC—500mAVDD_SOCFromPMIC—1000mAElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors27VDDA_1P8_INFromPMIC—1501mAVDD_SNVS_INFromPMICorCoincell—1mAVDD_XTAL_1P8FromPMIC—5mAVDD_LPSR_INFromPMIC—5mAVDD_TEMPSENSOR_1P8FromPMIC—1mAVDDA_ADC1_1P8FromPMIC—5mAVDDA_ADC2_1P8FromPMIC—5mAFUSE_FSOURCEFromPMIC—150mAVDD_MIPI_1P0Fromi.
MX7internalLDO—80mAPCIE_VPFromi.
MX7internalLDO—70mAPCIE_VP_RXFromi.
MX7internalLDO—35mAPCIE_VP_TXFromi.
MX7internalLDO—35mAPCIE_VPHFromi.
MX7internalLDO—25mAPCIE_VPH_RXFromi.
MX7internalLDO—15mAPCIE_VPH_TXFromi.
MX7internalLDO—15mANVCC_GPIO1FromPMICN=12UsemaxIOequation2mANVCC_GPIO2FromPMICN=14mANVCC_SD2FromPMICN=9mANVCC_SD3FromPMICN=12mANVCC_SD1FromPMICN=9mANVCC_ENET1FromPMICN=16mANVCC_EPDC1FromPMICN=16mANVCC_EPDC2FromPMICN=17mANVCC_SAIFromPMICN=11mANVCC_LCDFromPMICN=29mANVCC_SPIFromPMICN=8mANVCC_ECSPIFromPMICN=8mANVCC_I2CFromPMICN=8mANVCC_UARTFromPMICN=8mAVDD_USB_OTG1_3P3_INFromPMIC—50mAVDD_USB_OTG2_3P3_INFromPMIC—50mAVDD_USB_H_1P2Fromi.
MX7internalLDO—20mAVDDA_MIPI_1P8Fromi.
MX7internalLDO—5mATable12.
Maximumsupplycurrents(continued)PowerRailSourceConditionsMaxCurrentUnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors284.
1.
6PowermodesThei.
MX7Dualhasthefollowingpowermodes:OFFmode:allpowerrailsareoffSNVSmode:onlyRTCandtamperdetectionlogicisactiveLPSRmode:anextensionofSNVSmode,with16GPIOsinlowpowerstateretentionmodeRUNMode:allexternalpowerrailsareon,CPUisactiveandrunning,otherinternalmodulecanbeon/offbasedonapplication;LowPowermode(SystemIdle,LowPowerIdle,andDeepSleep):mostexternalpowerrailsarestillon,CPUisinWFIstateorpowergated,mostoftheinternalmodulesareclockgatedorpowergatedDRAM_VREFFromPMIC—1mANVCC_DRAM_CKEFromPMIC—30mANVCC_DRAMFromPMIC——3mA1TheactualmaximumcurrentdrawnfromVDDA_1P8_INisasshownplusanyadditionalcurrentdrawnfromtheVDDD_1P0_CAP,VDD_1P2_CAP,VDDA_PHY_1P8outputs,dependingonactualapplicationconfiguration(forexample,VDD_MIPI_1P0,VDD_USB_H_1P2andPCIE_VP/VPHsupplies).
2Generalequationforestimated,maximalpowerconsumptionofanI/Opowersupply:Imax=N*C*V*(0.
5*F)where:N=NumberofI/OpinssuppliedbythepowerlineC=EquivalentexternalcapacitiveloadV=IOvoltage(0.
5*F)=Datachangerate,upto0.
5oftheclockrate(F)Inthisequation,Imaxisinamps,Cinfarads,Vinvolts,andFinhertz.
3TheDRAMpowerconsumptionisdependentonseveralfactors,suchasexternalsignaltermination.
DRAMpowercalculatorsaretypicallyavailablefromthememoryvendors.
Theytakeintoaccountfactorssuchassignaltermination.
Seetheapplicationnote,i.
MX7DSPowerConsumptionMeasurement(AN5383)forexamplesofDRAMpowerconsumptionduringspecificusecasescenarios.
Table12.
Maximumsupplycurrents(continued)PowerRailSourceConditionsMaxCurrentUnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors29Thevalidpowermodetransitionisshowninthisdiagram.
Figure3.
i.
MX7DualPowerModesThepowermodetransitionconditionisdefinedinthefollowingtable.
Thefollowingtablesummarizestheexternalpowersupplystateinallthepowermodes.
Table13.
PowerModeTransitionTransitionFromToCondition1OFFRUNVDD_SVNS_INsupplypresent.
2SNVSOFFVDD_SNVS_INsupplyremoval.
3RUNSNVSONOFFlongpress,orSW.
4SNVSRUNONOFFpress,orRTC,ortamperevent.
5RUNLPSRSW.
6LPSRRUNONOFFpress,orRTC,ortamperevent,orGPIOevent.
7RUNLowPowerSW(CPUexecuteWFI)8LowPowerRUNRTC,tamperevent,IRQ.
Table14.
PowermodesPowerrailOFFSVNSLPSRRUNLowPowerVDD_ARMOFFOFFOFFONON/OFFVDD_SOCOFFOFFOFFONONVDDA_1P8_INOFFOFFOFFONONVDD_SNVS_INOFFONONONONVDD_LPSR_INOFFOFFONONONNVCC_GPIO1/2OFFOFFONONONNVCC_DRAMOFFOFFOFFONONOFFRUNSNVSLPSRLowPower12345678Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors30TheNVCC_DRAM_CKEcanbestillONduringSNVS/LPSRmodetokeeptheCKE/RESETpadincorrectstatetoholdDRAMdeviceinself-refreshmode.
TheNVCC_XXXcanbeoffinRUNmode/LowPowermodeifallthepadsinthatIObankisnotusedintheapplication,theNVCC_XXXsupplycouldbetiedtoGND.
TheVDD_USB_OTG1_3P3_INandVDD_USB_OTG2_3P3_INarefullyasynchronoustootherpowerrails,soitcanbeeitherON/OFFinanyofthepowermodes.
4.
1.
6.
1OFFModeInOFFmode,allthepowerrailsareshutoff.
4.
1.
6.
2SNVSModeSNVSmodeisalsocalledRTCmode,whereonlythepowerfortheSNVSdomainremainon.
Inthismode,onlytheRTCandtamperdetectionlogicisstillactive.
ThepowerconsumptioninSNVSmodelwithallthetamperdetectionlogicenabledwillbelessthan5uA@3.
0VonVDD_SNVS_INfortypicalsiliconat25°C.
TheexternalDRAMdevicecankeepinself-refreshwhenthechipstaysinSNVSmodewithNVCC_DRAM_CKEstillpowered.
DuringthestatetransitionbetweenSNVSmodeto/fromONmode,theDRAM_CKEpadandDRAM_RESETpadhastoalwaysstayincorrectstatetokeepDRAMinself-refreshmode.
Noglitch/floatingisallowed.
4.
1.
6.
3LPSRModeLPSRisconsideredasanextensionoftheSNVSmode.
AllthefeaturessupportedinSNVSmodeisalsosupportedinLPSRmode,includingthecapabilityofkeepingDRAMdeviceinself-refresh.
InLPSRmode,threeadditionalpowerrailswillremainon:VDD_LPSR_IN,NVCC_GPIO1,andNVCC_GPIO2.
ThesethreepowerrailsareusedtosupplythelogicandIOpadsintheLPSRdomain.
Thepurposeofthismodeistoretainthestateof16GPIOpads,sotheothercomponentsinthewholesystemwillhavetheircontrolsignalincorrectstate.
Amongallthe16GPIOpads,theNVCC_GPIO1supplythepowerfor8GPIOpads,andtheNVCC_GPIO2supplythepowerfortheother8GPIOpads.
ThisallowstheSoCtohavesomeofitsGPIOworkingat1.
8Vwhileothersworkingat3.
3VintheLPSRmode.
NVCC_DRAM_CKEOFFOFF/ONOFF/ONONONNVCC_XXXOFFOFFOFFON/OFFON/OFFVDD_USB_OTG1_3P3_INVDD_USB_OTG2_3P3_INOFF/ONOFF/ONOFF/ONON/OFFON/OFFTable14.
Powermodes(continued)PowerrailOFFSVNSLPSRRUNLowPowerElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors31WhenLPSRmodeisnotneededfortheapplication,theVDD_LPSRcanbeconnectedtoVDDA_1P8andNVCC_GPIO1/2canbeconnectedtothesamepowersupplyasNVCC_XXXforotherGPIObanks.
InLPSRmode,thesupportedwakeupsourceareRTCalarm,ONOFFevent,security/tamperandalsothe16GPIOpads.
4.
1.
6.
4RUNModeInRUNmode,theCPUisactiveandrunning,andtheanalog/digitalperipheralmodulesinsidetheprocessorwillbeenabled.
Inthismode,alltheexternalpowerrailstotheprocessorhavetobeONandtheSoCwillbeabletodrawasmanycurrentaslistedintheTable5MaximumPowerRequirement.
Inthismode,thePMICshouldallowSoCtochangethevoltageofpowerrailsthroughI2C/SPIinterface.
Typically,whentheCPUisdoingDVFS,itswitchestheVDD_ARMvoltageaccordingtoTable9whentheCPU'sfrequencyisswitchingbetween1GHzand800MHz(orbelow).
4.
1.
6.
5LowPowerModeWhentheCPUisnotrunning,theprocessorcanenterlowpowermode.
i.
MX7Dualprocessorsupportsaveryflexiblesetofpowermodeconfigurationsinlowpowermode.
Typicallythereare3lowpowermodesused,SystemIDLE,LowPowerIDLEandSUSPEND:SystemIDLE—ThisisamodethattheCPUcanautomaticallyenterwhenthereisnothreadrunning.
AlltheperipheralscankeepworkingandtheCPU'sstateisretainedsotheinterruptresponsecanbeveryshort.
ThecoresareabletoindividuallyentertheWAITstate.
LowPowerIDLE—Thismodeisforthecasewhenthesystemneedstohavelowerpowerbutstillkeepsomeoftheperipheralsalive.
Mostoftheperipherals,analogmodules,andPHYsareshutoff;seeTable5-5,"LowPowerModeDefinition,"inthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)fordetails.
TheinterruptresponseinthismodeisexpectedtobelongerthantheSystemIDLE,butitspowerismuchlower.
Suspend—Thismodehasthegreatestpowersavings;allclocks,unusedanalog/PHYs,andperipheralsareoff.
TheexternalDRAMstaysinSelf-Refreshmode.
Theexittimefromthismodeismuchlonger.
InSystemIDLEandLowPowerIDLEmode,thevoltageonexternalpowersuppliesremainsthesameasinRUNmode,sotheexternalPMICisnotawareofthestateoftheprocessor.
Ifanylow-powersettingneedstobeappliedtoPMIC,itisdonethroughtheI2C/SPIinterfacebeforetheprocessorentersalow-powermode.
WhentheprocessorentersSUSPENDmode,itwillassertthePMIC_STBY_REQsignaltoPMIC.
Whenthissignalisasserted,theprocessorallowsthePMICtoshutoffVDD_ARMexternally.
However,insomeapplicationscenario,SWwanttokeepthedatainL2Cachetoavoidperformanceimpactoncachemiss.
Inthiscase,theVDD_ARMcannotbeshutoff.
Tosupportbothscenarios,thePMICshouldhaveanoptiontoshutofforkeepVDD_ARMwhenitreceivesthePMIC_STBY_REQ.
ThisshouldbeconfiguredthroughI2C/SPIinterfacebeforetheprocessorentersSUSPENDmode.
ExcepttheVDD_ARM,theotherpowerrailshavetokeepactiveinSUSPENDmode.
Sincethecurrentoneachpowerrailisgreatlyreducedinthismode,PMICcanenteritsownlowpowermodetogetextraElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors32powersaving.
Forexample,thePMICcanchangetheDCDCrailstoPFMmodetoreducethepowerconsumption.
ThepowerconsumptioninlowpowermodesisdefinedinTable15.
AllthepowernumbersdefinedinTable15arebasedontypicalsiliconat25°C.
4.
1.
7USBPHYSuspendcurrentconsumption4.
1.
7.
1LowPowerSuspendModeTheVBUSValidcomparatorsandtheirassociatedbandgapcircuitsareenabledbydefault.
Table16showstheUSBinterfacecurrentconsumptioninSuspendmodewithdefaultsettings.
Table15.
LowPowerMeasurementsPowerrailSystemIDLELowPowerIDLESUSPENDLPSRVoltageCurrentPowerVoltageCurrentPowerVoltageCurrentPowerVoltageCurrentPower(V)(mA)(mW)(V)(mA)(mW)(V)(mA)(mW)(V)(mA)(mW)VDD_ARM1.
02.
72.
701.
00.
4280.
431.
00.
30.
300.
0—0.
00VDD_SOC1.
019.
3819.
381.
01.
4231.
421.
00.
60.
600.
0—0.
00VDDA_1P8_IN1.
83.
466.
231.
80.
2060.
371.
80.
40.
720.
0—0.
00VDD_SNVS_IN3.
00.
0060.
0183.
00.
0050.
0153.
00.
0060.
0183.
00.
0030.
009VDD_LPSR_IN1.
80.
040.
071.
80.
0410.
071.
80.
0390.
07021.
80.
040.
07NVCC_GPIO1/21.
80.
0720.
131.
80.
0730.
131.
80.
0720.
131.
80.
0720.
13Total——28.
53——2.
45——1.
84——0.
21Table16.
USBPHYcurrentconsumptionwithdefaultsettings11LowPowerSuspendisenabledbysettingUSBx_PORTSC1[PHCD]=1[ClockDisable(PLPSCD)].
VDD_USB_OTG1_3P3_INVDD_USB_OTG2_3P3_INCurrent790uA790uAElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors334.
1.
7.
24.
1.
7.
2Power-DownmodesTable17showstheUSBinterfacecurrentconsumptionwithonlytheOTGblockpowereddown.
InPower-Downmode,everythingispowereddown,includingtheUSB_VBUSvalidcomparatorsandtheirassociatedbandgapcircuityintypicalcondition.
Table18showstheUSBinterfacecurrentconsumptioninPower-Downmode.
4.
1.
8PCIephy2.
1DCelectricalcharacteristicsNote:VDDshouldhavenomorethan40mVppACpowersupplynoisesuperimposedonthehighpowersupplyvoltageforthePHYcore(1.
8VnominalDCvalue).
Atthesametime,VDDshouldhavenomorethan20mVppACpowersupplynoisesuperimposedonthelowpowersupplyvoltageforthePHYcore.
ThepowersupplyvoltagevariationforthePHYcoreshouldhavelessthan+/-5%includingtheboard-levelpowersupplyvariationandon-chippowersupplyvariationduetothefiniteimpedancesinthepackage.
Table17.
USBPHYcurrentconsumptionwithVBUSValidComparatorsdisabled11VBUSValidcomparatorscanbedisabledthroughsoftwarebysettingUSBNC_OTG*_PHY_CFG2[OTGDISABLE0]to1.
ThissignalpowersdownonlytheVBUSValidcomparator,anddoesnotcontrolpowertotheSessionValidComparator,ADPProbeandSensecomparators,ortheIDdetectioncircuitry.
VDD_USB_OTG1_3P3_INVDD_USB_OTG2_3P3_INCurrent730uA730uATable18.
USBPHYcurrentconsumptioninPower-Downmode11TheVBUSValidComparatorsandtheirassociatedbandgapcircuitscanbedisabledthroughsoftwarebysettingUSBNC_OTG*_PHY_CFG2[OTGDISABLE0]to1andUSBNC_OTG*_PHY_CFG2[DRVVBUS0]to0,respectively.
VDD_USB_OTG1_3P3_INVDD_USB_OTG2_3P3_INCurrent200uA200uATable19.
PCIerecommendedoperatingconditionsParameterDescriptionMinMaxUnitVDDLowPowerSupplyVoltageforPHYCore1V0.
951.
05VHighPowerSupplyVoltageforPHYCore1.
8V1.
711.
89TACommercialTemperatureRange070°CTJSimulationJunctionTemperatureRange-40125°CElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors34Table20.
PCIeDCelectricalcharacteristicsParameterDescriptionMinTypMaxUnitVDDPowerSupplyVoltage(VDDof1.
0Vnominalgateoxide/1.
8Vforthickgateoxide)1.
0-5%1.
01.
0+5%V1.
8-5%1.
81.
8+5%VPDPowerConsumptionNormal—130—mWPartialMode—108—mWSlumberMode—7—mWFullPowerdown—0.
2—mWTable21.
PCIePHYhigh-speedcharacteristicsHighSpeedI/OCharacteristicsDescriptionSymbolSpeedMin.
Typ.
Max.
UnitUnitIntervalUI1.
5Gbps—666.
67—ps2.
5Gbps—400—3.
0Gbps—333.
33—5.
0Gbps—200—6.
0Gbps—166.
67—TXSerialoutputrisetime(20%to80%)TTXRISE1.
5Gbps50—273ps2.
5Gbps50——3.
0Gbps50—1365.
0Gbps30——6.
0Gbps33—80TXSerialoutputfalltime(80%to20%)TTXFALL1.
5Gbps50—273ps2.
5Gbps50——3.
0Gbps50—1365.
0Gbps30——6.
0Gbps33—80TXSerialdataoutputvoltage(Differential,pk–pk)ΔVTX1.
5Gbps400—600mVp–p2.
5Gbps400—12003.
0Gbps400—7005.
0Gbps400—12006.
0Gbps240—900Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors35PCIeTxdeterministicjitter1.
5MHzTDJ5.
0Gbps/2.
5Gbps——30ps/60psps,pk–pkRXSerialdatainputvoltage(Differentialpk–pk)ΔVRX1.
5Gbps325—600mVp–p2.
5Gbps120—12003.
0Gbps275—7505.
0Gbps120—12006.
0Gbps240—1000Table22.
PCIePHYreferenceclocktimingrequirementsDescriptionSymbolMin.
Typ.
Max.
UnitFrequencyToleranceFTOL-100—100ppmDutyCycleDC40—60%RiseandFallTimeTR,TF——1.
5nsPeaktopeakJitterJitter——40ps,pk–pkRMSJitter——2.
5ps,rmsPeriodJitter——25psExternalClocksourceoutputimpedenceZC,DC40—60ΩDifferentialinputhighvoltageVIH150——mVDifferentialinputlowvoltageVIL——-150mVAbsolutemaximuminputvoltageVMAX——1.
15VAbsoluteminimuminputvoltageVMIN-0.
3——VAbsolutecrossingpointvoltageVCROSS250—550mVTable21.
PCIePHYhigh-speedcharacteristics(continued)HighSpeedI/OCharacteristicsDescriptionSymbolSpeedMin.
Typ.
Max.
UnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors36Table23.
PCIePHYreferenceclockTransmitrequirementsDescriptionSymbolInterfaceSpeedMinTypMaxUnitFrequencyofTBCFTBC20-bit1.
5Gbps—75—MHz3.
0Gbps—150—6.
0Gbps—300—40-bit1.
5Gbps—37.
5—3.
0Gbps—75—6.
0Gbps—150—8-bit2.
5Gbps—250—16-bit5.
0Gbps——DutycycleofTBCDCTBC——40—60%TXD[0:30]setuptimetotherisingedgeofTBCTSETUP.
TX20-bit1.
5Gbps2.
0——ns3.
0Gbps6.
0Gbps1.
0——40-bit1.
5Gbps2.
0——3.
0Gbps6.
0Gbps8-bit2.
5Gbps1.
0——16-bit5.
0GbpsTXD[0:30]holdtimetotherisingedgeofTBCTHOLD.
TX20-bit1.
5Gbps2.
0——ns3.
0Gbps6.
0Gbps1.
0——40-bit1.
5Gbps2.
0——3.
0Gbps6.
0Gbps8-bit2.
5Gbps1.
0——16-bit5.
0GbpsLatencyfromtherisingedgeofTBCtotheleadingedgeofthecorrespondingfirsttransmittedserialoutputbitTXP/TXNTLAT.
TX—1.
5Gbps—70—bits2.
5Gbps—100—3.
0Gbps—95—5.
0Gbps—200—6.
0Gbps—120—Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors37Thesystemdesignmustcomplywithpower-upsequence,power-downsequence,andsteadystateguidelinesasdescribedinthissectiontoguaranteethereliableoperationofthedevice.
Anydeviationfromthesesequencesmayresultinthefollowingsituations:Excessivecurrentduringpower-upphasePreventionofthedevicefrombootingTable24.
PCIePHYreferenceclockReceiverequirementsDescriptionSymbolInterfaceSpeedMinTypMaxUnitFrequencyofRBCFRBC20-bit1.
5Gbps—75—MHz3.
0Gbps—150—6.
0Gbps—300—40-bit1.
5Gbps—37.
5—3.
0Gbps—75—6.
0Gbps—150—DutycycleofTBCDCRBC——40—60%RXD[0:30]delaytimefromthefallingedgeofRBCTDLY,RX————1.
33nsLatencyfromtheleadingedgeofthecorrespondingfirstreceivedserialinputbit,RXP/RXN,totherisingedgeofRBCTLAT.
RX20-bit1.
5Gbps—100—bits2.
5Gbps—230—3.
0Gbps—100—5.
0Gbps—260—6.
0Gbps—100—Table25.
PCIePHYoutputclockcharacteristicsDescriptionSymbolInterfaceSpeedMinTypMaxUnitFrequencyofPC_CLKFPC_CLKHIGH_SPEED=1MHzPCIe——250—DutyCycleofPC_CLKDCPC_CLK——40—60%FrequencyofTX_CLKFTX_CLK20-bit1.
5Gbps—75—MHz3.
0Gbps—150—6.
0Gbps—300—40-bit1.
5Gbps—37.
5—3.
0Gbps—75—6.
0Gbps—150—DutycycleofTX_CLKDCTX_CLK——40—60%Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors38Irreversibledamagetotheprocessor(worst-casescenario)4.
1.
9Power-upsequenceThei.
MX7processorhasthefollowingpower-upsequencerequirements:VDD_SNVS_INtobeturnedonbeforeanyotherpowersupply.
IfacoincellisusedtopowerVDD_SNVS_IN,thenensurethatitisconnectedbeforeanyothersupplyisswitchedon.
VDD_SOCtobeturnedonbeforeNVCC_DRAMandNVCC_DRAM_CKE.
VDD_ARM,VDD_SOC,VDDA_1P8_IN,VDD_LPSR_INandallI/Opower(NVCC_*)shouldbeturnedonafterVDD_SVNS_INisactive.
ButthereisnosequencerequirementamongthesepowerrailsotherthanthesequencerequirementbetweenVDD_SOCandNVCC_DRAM/NVCC_DRAM_CKE.
TherearenospecialtimingrequirementsforVDD_USB_OTG1_3P3_INandVDD_USB_OTG2_3P3_IN.
ThePOR_Binput(ifused)mustbeimmediatelyassertedatpower-upandremainasserteduntilthelastpowerrailreachesitsworkingvoltage.
IntheabsenceofanexternalresetfeedingthePOR_Binput,theinternalPORmoduletakescontrol.
Thepower-upsequenceisshowninFigure4withthefollowingtimingparameters:T1TimefromSVNSpowerstabletootherpowerrailsstarttoramp,minimaldelayis2ms,nomaxdelayrequirement.
T2Timefromfirstpowerrails(exceptSNVS)rampuptoallthepowerrailsgetstable,minimaldelayis0ms,nomaxdelayrequirement.
T3Timefromallpowerrailsgetstabletopower-onreset,minimaldelayis0ms,nomaxdelayrequirement.
T6TimefromVDD_SOCgetstabletoNVCC_DRAM/NVCC_DRAM_CKEstarttoramp,minimaldelayis0ms,nomaxdelayrequirement.
Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors39Figure4.
i.
MX7Dualpower-upsequence4.
1.
10Power-downsequenceThei.
MX7processorshavethefollowingpower-downsequencerequirements:VDD_SNVS_INtobeturnedofflastafteranyotherpowersupply.
NVCC_DRAM/NVCC_DRAM_CKEtobeturnedoffbeforeVDD_SOC.
TherearenospecialtimingrequirementsforVDD_USB_OTG1_3P3_INandVDD_USB_OTG2_3P3_IN.
Thepower-downsequenceisshowninFigure5withthefollowingtimingparameters:T4Timefromfirstpowerrails(exceptSNVS)torampdowntoallthepowerrails(exceptSNVS)gettoground,minimaldelayis0ms,nomaxdelayrequirement.
T5Timefromallthepowerrailspowerdown(exceptSNVS)toSVNSpowerdown,minimaldelayis0ms,nomaxdelayrequirement.
T7TimefromNVCC_DRAM/NVCC_DRAM_CKEpowerdowntoVDD_SOCpowerdown,minimaldelayis0ms,nomaxdelayrequirement.
Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors40Figure5.
i.
MX7Dualpower-downsequence4.
1.
11PowersuppliesusageI/OpinsshouldnotbeexternallydrivenwhiletheI/Opowersupplyforthepin(NVCC_xxx)isOFF.
Thiscancauseinternallatch-upandmalfunctionsduetoreversecurrentflows.
ForinformationaboutI/Opowersupplyofeachpin,see"PowerRail"columnsinpinlisttablesofSection6,"Packageinformationandcontactassignments.
"4.
2IntegratedLDOvoltageregulatorparametersVariousinternalsuppliescanbepoweredfrominternalLDOvoltageregulators.
Allthesupplypinsnamed*_CAPmustbeconnectedtoexternalcapacitors.
TheonboardLDOsareintendedforinternaluseonlyandshouldnotbeusedtopoweranyexternalcircuitry.
Seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)fordetailsonthepowertreescheme.
NOTEThe*_CAPsignalsmustnotbepoweredexternally.
The*_CAPpinsareforthebypasscapacitorconnectiononly.
Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors414.
2.
1Internalregulators4.
2.
1.
1LDO_1P2TheLDO_1P2regulatorimplementsaprogrammablelinear-regulatorfunctionfromVDDA_1P8_IN(seeTable9forminimumandmaximuminputrequirements).
ThetypicaloutputoftheLDO,VDD_1P2_CAP,is1.
2V.
ItisintendedforusewiththeUSBHSICPHY,whichusesthisvoltagelevelforitsoutputdriver.
Foradditionalinformation,seethe"PowerManagementUnit(PMU)"chapterofthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
4.
2.
1.
2LDO_1P0DTheLDO_1P0Dregulatorimplementsaprogrammablelinear-regulatorfunctionfromVDDA_1P8_IN(seeTable9forminimumandmaximuminputrequirements).
ThetypicaloutputoftheLDO,VDD_1P0D_CAP,is1.
0V.
Itisintendedforusewiththeinternalphysicalinterfaces,includingMIPIandPCIePHY.
Foradditionalinformation,seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
4.
2.
1.
3LDO_1P0ATheLDO_1P0Aregulatorimplementsaprogrammablelinear-regulatorfunctionfromVDDA_1P8_IN(seeTable9forminimumandmaximuminputrequirements).
ThetypicaloutputoftheLDO,VDD_1P0A_CAP,is1.
0V.
Itisintendedforusewiththeinternalanalogmodules,includingtheXTAL,ADC,PLL,andTemperatureSensor.
Foradditionalinformation,seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
4.
2.
1.
4LDO_USB1_1PO/LDO_USB2_1P0TheLDO_USB1_1P0/LDO_USB2_1P0regulatorsimplementafixedlinear-regulatorfunctionfromVDD_USB_OTG1_3P3_INandVDD_USB_OTG2_3P3_INpowerinputsrespectively(seeTable9forminimumandmaximuminputrequirements).
Thetypicaloutputvoltageis1.
0V.
ItisintendedforusewiththeinternalUSBphysicalinterfaces(USBPHY1andUSBPHY2).
Foradditionalinformation,seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
Table26.
LDOparametersParameterMinMaxUnitsPVCC_GPIO_AT3P3_1P81.
61.
98VVDD_1P21.
11.
32VLPSR_1P00.
951.
155VVDDA_PHY_1P81.
61.
98VUSB_OTG1_1P00.
951.
155VElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors424.
2.
1.
5LDO_SVNS_1P81.
8VLDOfromcoincelltogenerate1.
8VpowerforSNVSand32KRTC.
TheLDO_SNVS_1P8regulatorimplementsafixedlinear-regulatorfunctionfromVDD_SNVS_IN(seeTable9forminimumandmaximuminputrequirements).
Thetypicaloutputis1.
7V.
ItisintendedforusewiththeinternalSNVScircuitryand32KRTC.
Foradditionalinformation,seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
4.
3PLLelectricalcharacteristics4.
4On-chiposcillators4.
4.
1OSC24MPowerfortheoscillatorissuppliedfromacleansourceofVDDA_1P8.
Thisblockimplementsanamplifierthatwhencombinedwithasuitablequartzcrystalandexternalloadcapacitorsimplementsanoscillator.
TheoscillatorispoweredfromVDDA_1P8.
Table27.
PLLElectricalParametersPLLtypeParameterValueAUDIO_PLLClockoutputrange650MHz–1.
3GHzReferenceclock24MHzLocktime2250referencecyclesElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors43ThesystemcrystaloscillatorconsistsofaPierce-typestructurerunningoffthedigitalsupply.
Astraightforwardbiased-inverterimplementationisused.
4.
4.
2OSC32KThisblockimplementsaninternalamplifier,trimableloadcapacitorsandaresistorthatwhencombinedwithasuitablequartzcrystalimplementsalowpoweroscillator.
Inaddition,iftheclockmonitordeterminesthattheOSC32Kisnotpresentthenthesourceofthe32kHzclockwillautomaticallyswitchtotheinternalrelaxationoscillatoroflesserfrequencyaccuracy.
CAUTIONTheinternalRTCoscillatordoesnotprovideanaccuratefrequencyandisaffectedbyprocess,voltageandtemperaturevariations.
NXPstronglyrecommendsusinganexternalcrystalastheRTC_XTALIreference.
Iftheinternaloscillatorisusedinstead,carefulconsiderationmustbegiventothetimingimplicationsonalloftheSoCmodulesdependentonthisclock.
TheOSC32krunsfromVDD_SNVS_1p8_CAP,whichisregulatedfromVDD_SNVS.
Thetargetbatteryisan~3VcoincellforVDD_SNVSandtheregulatedoutputis~1.
75V.
4.
5I/ODCparametersThissectionincludestheDCparametersofthefollowingI/Otypes:Table28.
OSC32KMainCharacteristicsMinTypMaxCommentsFosc—32.
768KHz—Thisfrequencyisnominalanddeterminedbythecrystalselected.
32.
0Kwouldworkaswell.
Currentconsumption—350nA—Thetypicalvalueshownisonlyfortheoscillator,drivenbyanexternalcrystal.
Iftheinterrelaxationoscillatorisusedinsteadofanexternalcrystalthenapproximately250nAshouldbeaddedtothisvalue.
Biasresistor—200MΩThisistheintegratedbiasresistorthatsetstheamplifierintoahighgainstate.
AnyleakagethroughtheESDnetwork,externalboardleakage,orevenascopeprobethatissignificantrelativetothisvaluewilldebiastheamp.
Thedebiasingwillresultinlowgainandwillimpactthecircuit'sabilitytostartupandmaintainoscillations.
TargetCrystalPropertiesCload—10pF—Usually,crystalscanbepurchasedtunedfordifferentCload.
ThisCloadvalueistypically1/2ofthecapacitancesrealizedonthePCBoneithersideofthequartz.
AhigherCloadwilldecreaseoscillationmarginbutincreasescurrentoscillatingthroughthecrystal.
TheCloadisprogrammablein2pFsteps.
ESR—50KΩ—Equivalentseriesresistanceofthecrystal.
Choosingacrystalwithahighervaluewilldecreaseoscillatingmargin.
Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors44GeneralPurposeI/O(GPIO)DoubleDataRateI/O(DDR)forLPDDR3andDDR3modesDifferentialI/O(CCM_CLK1)4.
5.
1GeneralpurposeI/O(GPIO)DCparametersTable29showsDCparametersforGPIOpads.
TheparametersinTable29areguaranteedpertheoperatingrangesinTable9,unlessotherwisenoted.
4.
5.
2DDRI/ODCelectricalcharacteristicsTheDDRI/OpadssupportDDR3/DDR3L,LPDDR2,andLPDDR3operationalmodes.
TheDDRMemoryController(DDRMC)isdesignedtobecompatiblewithJEDEC-compliantSDRAMs.
TheDDRCsupportsthefollowingmemorytypes:DDR3SDRAMcomplianttoJESD79-3EDDR3JEDECstandardreleaseJuly,2010LPDDR2SDRAMcomplianttoJESD209-2BLPDDR2JEDECstandardreleaseJune,2009LPDDR3SDRAMcomplianttoJESD209-3BLPDDR3JEDECstandardreleaseAugust,2013Table29.
GPIODCParametersParameterSymbolTestConditionsMinMaxUnitsHigh-leveloutputvoltageVOHIOH=–1.
8mA,–3.
6mA,–7.
2mA,–10.
8mA0.
8*OVDDOVDDVLow-leveloutputvoltageVOLIOL=1.
8mA,3.
6mA,7.
2mA,10.
8mA00.
2*OVDDVHigh-levelinputvoltageVIH—0.
7*OVDDOVDD+0.
3VLow-levelinputvoltageVIL—–0.
30.
3*OVDDVInputhysteresisVHYS—0.
15—VPull-upresistor(5_kΩPU)—VDD=1.
8±0.
15V5.
945.
98KΩPull-upresistor(5_kΩPU)—VDD=3.
3±0.
3V4.
85.
3KΩPull-upresistor(47_kΩPU)—VDD=1.
8±0.
15V46.
150.
6KΩPull-upresistor(47_kΩPU)—VDD=3.
3±0.
3V45.
849.
8KΩPull-upresistor(100_kΩPU)—VDD=1.
8±0.
15V97.
5105.
9KΩPull-upresistor(100_kΩPU)—VDD=3.
3±0.
3V101105KΩPull-downresistor(100_kΩPU)—VDD=1.
8±0.
15V101108.
6KΩPull-downresistor(100_kΩPD)—VDD=3.
3±0.
3V101108KΩInputcurrent(noPU/PD)IOZ—–55μΑSink/sourcecurrentinPush-Pullmode—Drivingcurrents(@100MHz,VOL/H=0.
5*OVDD,SS,125°C)OVDD=2.
7V–32.
932.
9mAElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors45DDRMCoperationwiththestandardsstatedaboveiscontingentupontheboardDDRdesignadherencetotheDDRdesignandlayoutrequirementsstatedinthehardwaredevelopmentguideforthei.
MX7applicationprocessor.
4.
5.
2.
1LPDDR3modeI/ODCparametersTable30.
DCinputlogiclevelCharacteristicsSymbolMinMaxUnitDCinputlogichigh11ItistherelationshipoftheVDDQofthedrivingdeviceandtheVREFofthereceivingdevicethatdeterminesnoisemargins.
However,inthecaseofVIH(DC)max(thatis,inputoverdrive),itistheVDDQofthereceivingdevicethatisreferenced.
VIH(DC)VREF+100—mVDCinputlogiclow1VIL(DC)—VREF–100Table31.
OutputDCcurrentdriveCharacteristicsSymbolMinMaxUnitOutputminimumsourceDCcurrent11WhenDDS=[111]andwithoutZQcalibration.
IOH(DC)–4—mAOutputminimumsinkDCcurrent1IOL(DC)4—mADCoutputhighvoltage(IOH=–0.
1mA)1,22ThevaluesofVOHandVOLarevalidonlyfor1.
2Vrange.
VOH0.
9*VDDQ—VDCoutputlowvoltage(IOL=0.
1mA)1,2VOL—0.
1*VDDQVTable32.
InputDCcurrentCharacteristicsSymbolMinMaxUnitHighlevelinputcurrent1,21ThevaluesofVOHandVOLarevalidonlyfor1.
2Vrange.
2DriverHi-Zandinputpower-down(PD=High)IIH–2525μALowlevelinputcurrent1,2IIL–2525μATable33.
LPDDR3I/ODCelectricalparametersParametersSymbolTestConditionsMinMaxUnitHigh-leveloutputvoltageVOHIoh=-0.
1mA0.
9*OVDD—VLow-leveloutputvoltageVOLIol=0.
1mA—0.
1*OVDDVInputReferenceVoltageVref—0.
49*OVDD0.
51*OVDDVElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors464.
5.
3DifferentialI/Oport(CCM_CLK1P/N)TheclockI/OinterfaceisdesignedtobecompatiblewithTIA/EIA644-Astandard.
SeeTIA/EIASTANDARD644-A,ElectricalCharacteristicsofLowVoltageDifferentialSignaling(LVDS)InterfaceCircuits(2001),fordetails.
Table34showstheclockI/ODCparameters.
DCHigh-LevelinputvoltageVih_DC—VRef+0.
100OVDDVDCLow-LevelinputvoltageVil_DC—OVSSVRef–0.
100VDifferentialInputLogicHighVih_diff—0.
26Seenote1—DifferentialInputLogicLowVil_diff—Seenote1-0.
26—Pull-up/Pull-downImpedanceMismatchMmpupd—–1515%240unitcalibrationresolutionRres——10KeeperCircuitResistanceRkeep—110175kInputcurrent(nopull-up/down)IinVI=0,VI=OVDD-2.
52.
5μA1Thesingle-endedsignalsneedtobewithintherespectivelimits(Vih(dc)max,Vil(dc)min)forsingle-endedsignalsaswellasthelimitationsforovershootandundershoot.
Table34.
DifferentialclockI/ODCelectricalcharacteristicsSymbolParameterTestconditionsMinTypMaxUnitNotesVodOutputDifferentialVoltageRload=100Ωbetweenpadpandpadn250350450mVVpadp–VpadnVohHigh-leveloutputvoltage1.
0251.
1751.
325V1VolLow-leveloutputvoltage0.
6750.
8250.
9752VocmOutputcommonmodevoltage0.
911.
1CoresupplyisusedVidInputDifferentialVoltage100600mVVpadp–VpadnVicmInputcommonmodevoltage50m1.
57VVicm(max)=ovdd(min)–Vid(min)/2Icc-ovddTri-stateI/Osupplycurrentipp_ibe=ipp_obe=0irefindisabled(0uA)0.
46uATable33.
LPDDR3I/ODCelectricalparameters(continued)ParametersSymbolTestConditionsMinMaxUnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors474.
6I/OACparametersThissectionincludestheACparametersofthefollowingI/Otypes:GeneralPurposeI/O(GPIO)DoubleDataRateI/O(DDR)forLPDDR2,LPDDR3andDDR3/DDR3LmodesDifferentialI/O(CCM_CLK1)TheGPIOandDDRI/OloadcircuitandoutputtransitiontimewaveformsareshowninFigure6andFigure7.
Figure6.
LoadcircuitforoutputFigure7.
Outputtransitiontimewaveform4.
6.
1GeneralpurposeI/OACparametersThissectionpresentstheI/OACparametersforGPIOindifferentmodes.
NotethatthefastorslowI/ObehaviorisdeterminedbytheappropriatecontrolbitsintheIOMUXCcontrolregisters.
Icc-ovdd-lpTri-stateI/Osupplycurrentinlow-powermodeipp_pwr_stable_b_1p8=1(means1.
8V)vddiisOFFirefindisabled(0uA)0.
351uAIcc-vddiTri-statecoresupplycurrentipp_ibe=ipp_obe=0irefindisabled(0uA)0.
8IccPowersupplycurrent(ovdd)Rload=100Ωbetweenpadpandpadn4.
7mAThisisnotincludingcurrentthroughexternalRload=100Ω1VOH_max=Vos_max+Vod_max/2=1.
1+0.
225=1.
325V.
VOH_min=Vos_min+Vod_min/2=0.
9+0.
125=1.
025V.
2VOL_max=Vos_max-Vod_min/2=1.
1-0.
125=0.
975V.
VOL_min=Vos_min-Vod_max/2=0.
9-0.
225=0.
675VTable34.
DifferentialclockI/ODCelectricalcharacteristics(continued)SymbolParameterTestconditionsMinTypMaxUnitNotesTestPointFromOutputUnderTestCLCLincludespackage,probeandfixturecapacitance0VOVDD20%80%80%20%trtfOutput(atpad)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors48Table35.
MaximuminputcelldelaytimeCellnameMaxDelayPAD→Y(ns)VDD=1.
65VT=125°CProcess=SlowVDD=2.
3VT=125°CProcess=SlowVDD=3.
0VT=125°CProcess=SlowPBIDIRPUD_E33_33_NT_DR0.
91.
51.
4Table36.
OutputcelldelaytimeforfixedloadParameterSimulatedCellDelayAPAD(ns)VDD=1.
65V,T=125°CVDD=2.
3V,T=125°CVDD=3.
0V,T=125°CDS0DS1SRDriverTypeCL=5pFCL=10pFCL=40pFCL=5pFCL=10pFCL=40pFCL=5pFCL=10pFCL=40pF0011*SlowSlew4.
96.
012.
54.
86.
111.
95.
46.
714.
60001*FastSlew3.
84.
711.
23.
85.
112.
84.
25.
313.
50112*SlowSlew4.
14.
88.
24.
24.
98.
84.
55.
39.
10102*FastSlew2.
83.
36.
42.
93.
47.
23.
13.
77.
21014*SlowSlew3.
64.
16.
03.
74.
16.
43.
94.
46.
61004*FastSlew2.
22.
54.
12.
32.
64.
62.
42.
84.
81116*SlowSlew3.
64.
05.
53.
64.
05.
93.
84.
36.
21106*FastSlew2.
02.
33.
42.
12.
33.
82.
22.
53.
9Table37.
MaximumfrequencyofoperationforinputMaximumfrequency(MHz)VDD=1.
8V,CL=50fFVDD=2.
5V,CL=50fFVDD=3.
3V,CL=50fF550400430Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors494.
6.
2ClockI/OACparameters—CCM_CLK1_N/CCM_CLK1_PThedifferentialoutputtransitiontimewaveformisshowninFigure8.
Table38.
Maximumfrequencyofoperationforoutput11Maximumfrequencyvalueisobtainedwithlumpedcapacitorload.
IfyouconsidertransmissionlineorSSNnoiseeffect,itcouldbeworsethansuggestedvalue.
ParameterMaximumfrequency(MHz)VDD=1.
8VVDD=2.
5VVDD=3.
3VDS0DS1SRDriverTypeCL=5pFCL=10pFCL=40pFCL=5pFCL=10pFCL=40pFCL=5pFCL=10pFCL=40pF0011*SlowSlew10070259060209560200001*FastSlew1107525100652010065200112*SlowSlew120100501201004011595400102*FastSlew1851455018013040170130401014*SlowSlew1401258513512070130115701004*FastSlew23520010022519580215185801116*SlowSlew1401259013512085130115801106*FastSlew250225140240215120235205120Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors50Figure8.
DifferentialLVDSdrivertransitiontimewaveformTable39showstheACparametersforclockI/O.
Table39.
I/OACParametersofLVDSPadSymbolParameterTestconditionsMinTypMaxUnitNotesTphldOutputDifferentialpropagationdelayhightolowRload=100Ωbetweenpadpandpadn,Cload=2pF——0.
61ns11AtWCS,125C,1.
62Vovdd,0.
9Vvddi.
Measurementlevelsare50-50%.
Outputdifferentialsignalmeasured.
TplhdOutputDifferentialpropagationdelaylowtohigh——0.
61TtlhOutputTransitiontimelowtohigh——0.
1722WCS,125C,1.
62Vovdd,0.
9Vvddi.
Measurementlevelsare20-80%.
OutputdifferentialsignalmeasuredTthlOutputTransitiontimehightolow——0.
17TphlrInputDifferentialpropagationdelayhightolowRload=100Ωbetweenpadpandpadn,Cloadonipp_ind=0.
1pF——0.
33ns33AtWCS,125C,1.
62Vovdd,0.
9Vvddi.
Measurementlevelsare50-50%.
TplhrInputDifferentialpropagationdelaylowtohigh——0.
33TtxTransmitterstartuptime(ipp-obelowtohigh)———40ns44TXstartuptimeisdefinedasthetimetakenbytransmitterforsettlingafteritsipp_obehasbeenasserted.
Itistostabilizethecurrentreference.
FunctionalityisguaranteedonlyafterthestartuptimeFOperatingfrequency——5001000MHz—Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors514.
7OutputbufferimpedanceparametersThissectiondefinestheI/Oimpedanceparametersofthei.
MX7DualfamilyofprocessorsforthefollowingI/Otypes:DoubleDataRateI/O(DDR)forLPDDR2,LPDDR3,andDDR3/DDR3LmodesDifferentialI/O(CCM_CLK1)USBbatterychargerdetectionopen-drainoutput(USB_OTG1_CHD_B)NOTEDDRI/Ooutputdriverimpedanceismeasuredwith"long"transmissionlineofimpedanceZtlattachedtoI/Opadandincidentwavelaunchedintotransmissionline.
Rpu/RpdandZtlformavoltagedividerthatdefinesspecificvoltageofincidentwaverelativetoOVDD.
Outputdriverimpedanceiscalculatedfromthisvoltagedivider(seeFigure9).
Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors52Figure9.
Impedancematchingloadformeasurement4.
7.
1DDRI/OoutputbufferimpedanceTheLPDDR2interfaceisdesignedtobefullycompatiblewithJESD209-2BLPDDR2JEDECstandardreleaseJune,2009.
TheLPDDR3interfacemodeisdesignedtobecompatiblewithJESD209-3BJEDECstandardreleasedAugust,2013.
TheDDR3interfaceisdesignedtobefullycompatiblewithJESD79-3FDDR3JEDECstandardreleaseJuly,2012.
ipp_doCload=1pZtlΩ,L=20inchespredriverPMOS(Rpu)NMOS(Rpd)padOVDDOVSSt,(ns)0U,(V)OVDDt,(ns)0VDDVin(do)Vout(pad)U,(V)VrefRpu=Vovdd-Vref1Vref1*ZtlRpd=*ZtlVref2Vovdd-Vref2Vref1Vref2Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors53Table40showsDDRI/Ooutputbufferimpedanceofi.
MX7Dualfamilyofprocessors.
Note:1.
OutputdriverimpedanceiscontrolledacrossPVTsusingZQcalibrationprocedure.
2.
Calibrationisdoneagainst240Ωexternalreferenceresistor.
3.
Outputdriverimpedancedeviation(calibrationaccuracy)is±5%(max/minimpedance)acrossPVTs.
4.
7.
2DifferentialI/OoutputbufferimpedanceTheDifferentialCCMinterfaceisdesignedtobecompatiblewithTIA/EIA644-Astandard.
See,TIA/EIASTANDARD644-A,ElectricalCharacteristicsofLowVoltageDifferentialSignaling(LVDS)InterfaceCircuits(2001)fordetails.
4.
7.
3USBbatterychargerdetectiondriverimpedanceTheUSB_OTG1_CHD_Bopen-drainoutputpincanbeusedtosignaltheresultsofUSBBatteryChargerdetectionroutinesfortheUSB_OTG1PHYinstancetopowermanagementandmonitoringdevices.
Useofthispinrequiresanexternalpullupresistor,formoreinformationseeTable3,andTable7.
Table41showstheUSB_OTG1_CHD_BpulldowndriverimpedancefortheUSB_OTG1_CHD_Bpin.
4.
8SystemmodulestimingThissectioncontainsthetimingandelectricalparametersforthemodulesineachi.
MX7Dualprocessor.
Table40.
DDRI/OoutputbufferimpedanceParameterSymbolTestConditionsDSE(DriveStrength)TypicalUnitNVCC_DRAM=1.
5V(DDR3)DDR_SEL=11NVCC_DRAM=1.
2V(LPDDR2)DDR_SEL=10OutputDriverImpedanceRdrv000001010011100101110111Hi-Z2401208060484034Hi-Z2401208060484034ΩTable41.
USB_OTG1_CHD_Bpulldowndriverimpedance(VDD_USB_OTG1_3P3_IN3.
3V)ParameterSymbolTypicalUnitOpen-drainoutputdriverpulldownimpedanceRdrv_pd1000ΩElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors544.
8.
1ResettimingsparametersFigure10showstheresettimingandTable42liststhetimingparameters.
Figure10.
Resettimingdiagram4.
8.
2WDOGResettimingparametersFigure11showstheWDOGresettimingandTable43liststhetimingparameters.
Figure11.
WDOGx_BtimingdiagramNOTERTC_XTALIisapproximately32kHz.
RTC_XTALIcycleisoneperiodorapproximately30μs.
NOTEWDOGx_Boutputsignals(foreachoneoftheWatchdogmodules)donothavededicatedpins,butaremuxedoutthroughtheIOMUX.
SeetheIOMUXCchapterofthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)fordetailedinformation.
4.
8.
3Externalinterfacemodule(EIM)ThefollowingsubsectionsprovideinformationontheEIM.
Table42.
ResettimingparametersIDParameterMinMaxUnitCC1DurationofPOR_Btobequalifiedasvalid.
Note:POR_Brise/falltimesmustbe5nsorless.
1—RTC_XTALIcycleTable43.
WDOGx_BtimingparametersIDParameterMinMaxUnitCC3DurationofWDOG1_BAssertion1—RTC_XTALIcyclePOR_BCC1(Input)WDOGx_BCC3(Output)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors554.
8.
3.
1EIMinterfacepadsallocationEIMsupports16-bitand8-bitdevicesoperatinginaddress/dataseparateormultiplexedmodes.
Table44providesEIMinterfacepadsallocationindifferentmodes.
Table44.
EIMinternalmodulemultiplexing11Formoreinformationonconfigurationportsmentionedinthistable,seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
SetupNonMultiplexedAddress/DataModeMultiplexedAddress/DataMode8Bit16Bit16BitMUM=0,DSZ=100MUM=0,DSZ=101MUM=0,DSZ=001MUM=1,DSZ=001EIM_ADDR[15:00]EIM_AD[15:00]EIM_AD[15:00]EIM_AD[15:00]EIM_AD[15:00]EIM_ADDR[25:16]EIM_ADDR[25:16]EIM_ADDR[25:16]EIM_ADDR[25:16]EIM_ADDR[25:16]EIM_DATA[07:00],EIM_EB0_BEIM_DATA[07:00]—EIM_DATA[07:00]EIM_AD[07:00]EIM_DATA[15:08],EIM_EB1_B—EIM_DATA[15:08]EIM_DATA[15:08]EIM_AD[15:08]Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors564.
8.
3.
2GeneralEIMTiming—SynchronousmodeFigure12,Figure13,andTable45specifythetimingsrelatedtotheEIMmodule.
AllEIMoutputcontrolsignalsmaybeassertedanddeassertedbyaninternalclocksynchronizedtotheEIM_BCLKrisingedgeaccordingtocorrespondingassertion/negationcontrolfields.
,Figure12.
EIMoutputstimingdiagramFigure13.
EIMinputstimingdiagramWE4EIM_ADDRxxEIM_CSx_BEIM_WE_BEIM_OE_BEIM_BCLKEIM_EBx_BEIM_LBA_BOutputData.
.
.
WE5WE6WE7WE8WE9WE10WE11WE12WE13WE14WE15WE16WE17WE3WE2WE1InputDataEIM_WAIT_BEIM_BCLKWE19WE18WE21WE20Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors574.
8.
3.
3ExamplesofEIMsynchronousaccessesTable45.
EIMbustimingparameters1IDParameterBCD=0BCD=1BCD=2BCD=3MinMaxMinMaxMinMaxMinMaxWE1EIM_BCLKCycletime2t—2xt—3xt—4xt—WE2EIM_BCLKLowLevelWidth0.
4xt—0.
8xt—1.
2xt—1.
6xt—WE3EIM_BCLKHighLevelWidth0.
4xt—0.
8xt—1.
2xt—1.
6xt—WE4Clockrisetoaddressvalid3-0.
5xt-1.
25-0.
5xt+1.
75-t-1.
25-t+1.
75-1.
5xt-1.
25-1.
5xt+1.
75-2xt-1.
25-2xt+1.
75WE5Clockrisetoaddressinvalid0.
5xt-1.
250.
5xt+1.
75t-1.
25t+1.
751.
5xt-1.
251.
5xt+1.
752xt-1.
252xt+1.
75WE6ClockrisetoEIM_CSx_Bvalid-0.
5xt-1.
25-0.
5xt+1.
75-t-1.
25-t+1.
75-1.
5xt-1.
25-1.
5xt+1.
75-2xt-1.
25-2xt+1.
75WE7ClockrisetoEIM_CSx_Binvalid0.
5xt-1.
250.
5xt+1.
75t-1.
25t+1.
751.
5xt-1.
251.
5xt+1.
752xt-1.
252xt+1.
75WE8ClockrisetoEIM_WE_BValid-0.
5xt-1.
25-0.
5xt+1.
75-t-1.
25-t+1.
75-1.
5xt-1.
25-1.
5xt+1.
75-2xt-1.
25-2xt+1.
75WE9ClockrisetoEIM_WE_BInvalid0.
5xt-1.
250.
5xt+1.
75t-1.
25t+1.
751.
5xt-1.
251.
5xt+1.
752xt-1.
252xt+1.
75WE10ClockrisetoEIM_OE_BValid-0.
5xt-1.
25-0.
5xt+1.
75-t-1.
25-t+1.
75-1.
5xt-1.
25-1.
5xt+1.
75-2xt-1.
25-2xt+1.
75WE11ClockrisetoEIM_OE_BInvalid0.
5xt-1.
250.
5xt+1.
75t-1.
25t+1.
751.
5xt-1.
251.
5xt+1.
752xt-1.
252xt+1.
75WE12ClockrisetoEIM_EBx_BValid-0.
5xt-1.
25-0.
5xt+1.
75-t-1.
25-t+1.
75-1.
5xt-1.
25-1.
5xt+1.
75-2xt-1.
25-2xt+1.
75WE13ClockrisetoEIM_EBx_BInvalid0.
5xt-1.
250.
5xt+1.
75t-1.
25t+1.
751.
5xt-1.
251.
5xt+1.
752xt-1.
252xt+1.
75WE14ClockrisetoEIM_LBA_BValid-0.
5xt-1.
25-0.
5xt+1.
75-t-1.
25-t+1.
75-1.
5xt-1.
25-1.
5xt+1.
75-2xt-1.
25-2xt+1.
75WE15ClockrisetoEIM_LBA_BInvalid0.
5xt-1.
250.
5xt+1.
75t-1.
25t+1.
751.
5xt-1.
251.
5xt+1.
752xt-1.
252xt+1.
75WE16ClockrisetoOutputDataValid-0.
5xt-1.
25-0.
5xt+1.
75-t-1.
25-t+1.
75-1.
5xt-1.
25-1.
5xt+1.
75-2xt-1.
25-2xt+1.
75WE17ClockrisetoOutputDataInvalid0.
5xt-1.
250.
5xt+1.
75t-1.
25t+1.
751.
5xt-1.
251.
5xt+1.
752xt-1.
252xt+1.
75WE18InputDatasetuptimetoClockrise2—4WE19InputDataholdtimefromClockrise2—2WE20EIM_WAIT_BsetuptimetoClockrise2—4WE21EIM_WAIT_BholdtimefromClockrise2—2Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors58Figure14toFigure17providefewexamplesofbasicEIMaccessestoexternalmemorydeviceswiththetimingparametersmentionedpreviouslyforspecificcontrolparameterssettings.
Figure14.
Synchronousmemoryreadaccess,WSC=11tisthemaximumEIMlogic(axi_clk)cycletime.
Themaximumallowedaxi_clkfrequencydependsonthefixed/non-fixedlatencyconfiguration,whereasthemaximumallowedEIM_BCLKfrequencyis:—Fixedlatencyforbothreadandwriteis132MHz.
—Variablelatencyforreadonlyis132MHz.
—Variablelatencyforwriteonlyis52MHz.
Invariablelatencyconfigurationforwrite,ifBCD=0&WBCDD=1orBCD=1,axi_clkmustbe104MHz.
WriteBCD=1and104MHzaxi_clk,willresultinaEIM_BCLKof52MHz.
WhentheclockbranchtoEIMisdecreasedto104MHz,otherbusesareimpactedwhichareclockedfromthissource.
SeetheCCMchapterofthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)foradetailedclocktreedescription.
2EIM_BCLKparametersarebeingmeasuredfromthe50%point,thatis,highisdefinedas50%ofsignalvalueandlowisdefinedas50%assignalvalue.
3Forsignalmeasurements,"High"isdefinedas80%ofsignalvalueand"Low"isdefinedas20%ofsignalvalue.
LastValidAddressAddressv1D(v1)EIM_BCLKEIM_ADDRxxEIM_DATAxxEIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BWE4WE5WE6WE7WE10WE11WE13WE12WE14WE15WE18WE19Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors59Figure15.
Synchronousmemory,writeaccess,WSC=1,WBEA=0andWADVN=0Figure16.
MuxedAddress/Data(A/D)mode,synchronouswriteaccess,WSC=6,ADVA=0,ADVN=1,andADH=1NOTEIn32-bitMuxedAddress/Data(A/D)modethe16MSBsaredrivenonthedatabus.
LastValidAddressAddressV1D(V1)EIM_BCLKEIM_ADDRxxEIM_DATAxxEIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BWE4WE5WE6WE7WE8WE9WE12WE13WE14WE15WE16WE17EIM_BCLKEIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BAddressV1WriteDataWE4WE16WE6WE7WE9WE8WE10WE11WE14WE15WE17WE5LastValidAddressEIM_ADDRxx/EIM_ADxxElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors60Figure17.
16-BitMuxedA/DMode,SynchronousReadAccess,WSC=7,RADVN=1,ADH=1,OEA=04.
8.
3.
4GeneralEIMtiming—AsynchronousmodeFigure18throughFigure22,andTable46helpyoudeterminetimingparametersrelativetothechipselect(CS)stateforasynchronousandDTACKEIMaccesseswithcorrespondingEIMbitfieldsandthetimingparametersmentionedabove.
Asynchronousread&writeaccesslengthincyclesmayvaryfromwhatisshowninFigure18throughFigure21asRWSC,OENandCSNisconfigureddifferently.
Seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)fortheEIMprogrammingmodel.
Figure18.
Asynchronousmemoryreadaccess(RWSC=5)LastEIM_BCLKEIM_ADDRxx/EIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BAddressV1DataValidAddressEIM_ADxxWE5WE6WE7WE14WE15WE10WE11WE12WE13WE18WE19WE4LastValidAddressAddressV1D(V1)EIM_ADDRxx/EIM_DATAxx[7:0]EIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BNextAddressWE39WE35WE37WE32WE36WE38WE43WE40WE31WE44INT_CLKstartofaccessendofaccessMAXDIMAXCSOMAXCOEIM_ADxxElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors61Figure19.
AsynchronousA/Dmuxedreadaccess(RWSC=5)Figure20.
AsynchronousmemorywriteaccessAddr.
V1D(V1)EIM_ADDRxx/EIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BWE39WE35AWE37WE36WE38WE40AWE31WE44INT_CLKstartofaccessendofaccessMAXDIMAXCSOMAXCOWE32AEIM_ADxxLastValidAddressAddressV1D(V1)EIM_ADDRxxEIM_DATAxxEIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BNextAddressWE31WE39WE33WE45WE32WE40WE34WE46WE42WE41Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors62Figure21.
AsynchronousA/DmuxedwriteaccessFigure22.
DTACKmodereadaccess(DAP=0)EIM_WE_BEIM_OE_BEIM_EBx_BEIM_CSx_BWE33WE45WE34WE46WE42Addr.
V1D(V1)EIM_ADDRxx/WE31WE42WE41WE32AEIM_DATAxxEIM_LBA_BWE39WE40ALastValidAddressAddressV1D(V1)EIM_ADDRxxEIM_DATAxx[7:0]EIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BNextAddressWE39WE35WE37WE32WE36WE38WE43WE40WE31WE44EIM_DTACK_BWE47WE48Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors63Figure23.
DTACKModewriteaccess(DAP=0)Table46.
EIMasynchronoustimingparameterstablerelativechiptoselectRefNo.
ParameterDeterminationbySynchronousmeasuredparameters1MinMaxUnitWE31EIM_CSx_BvalidtoAddressValidWE4–WE6–CSA2—3–CSAnsWE32AddressInvalidtoEIM_CSx_BinvalidWE7–WE5–CSN3—3–CSNnsWE32A(muxedA/DEIM_CSx_BvalidtoAddressInvalidt4+WE4–WE7+(ADVN5+ADVA6+1–CSA)–3+(ADVN+ADVA+1–CSA)—nsWE33EIM_CSx_BValidtoEIM_WE_BValidWE8–WE6+(WEA–WCSA)—3+(WEA–WCSA)nsWE34EIM_WE_BInvalidtoEIM_CSx_BInvalidWE7–WE9+(WEN–WCSN)—3+(WEN–WCSN)nsWE35EIM_CSx_BValidtoEIM_OE_BValidWE10–WE6+(OEA–RCSA)—3+(OEA–RCSA)nsWE35A(muxedA/D)EIM_CSx_BValidtoEIM_OE_BValidWE10–WE6+(OEA+RADVN+RADVA+ADH+1–RCSA)–3+(OEA+RADVN+RADVA+ADH+1–RCSA)3+(OEA+RADVN+RADVA+ADH+1–RCSA)nsWE36EIM_OE_BInvalidtoEIM_CSx_BInvalidWE7–WE11+(OEN–RCSN)—3–(OEN–RCSN)nsWE37EIM_CSx_BValidtoEIM_EBx_BValid(Readaccess)WE12–WE6+(RBEA–RCSA)—3+(RBEA–RCSA)nsLastValidAddressAddressV1D(V1)EIM_ADDRxxEIM_DATAxxEIM_WE_BEIM_LBA_BEIM_OE_BEIM_EBx_BEIM_CSx_BNextAddressWE31WE39WE33WE45WE32WE40WE34WE46WE42WE41EIM_DTACK_BWE48WE47Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors64WE38EIM_EBx_BInvalidtoEIM_CSx_BInvalid(Readaccess)WE7–WE13+(RBEN–RCSN)—3–(RBEN–RCSN)nsWE39EIM_CSx_BValidtoEIM_LBA_BValidWE14–WE6+(ADVA–CSA)—3+(ADVA–CSA)nsWE40EIM_LBA_BInvalidtoEIM_CSx_BInvalid(ADVLisasserted)WE7–WE15–CSN—3–CSNnsWE40A(muxedA/D)EIM_CSx_BValidtoEIM_LBA_BInvalidWE14–WE6+(ADVN+ADVA+1–CSA)–3+(ADVN+ADVA+1–CSA)3+(ADVN+ADVA+1–CSA)nsWE41EIM_CSx_BValidtoOutputDataValidWE16–WE6–WCSA—3–WCSAnsWE41A(muxedA/D)EIM_CSx_BValidtoOutputDataValidWE16–WE6+(WADVN+WADVA+ADH+1–WCSA)—3+(WADVN+WADVA+ADH+1–WCSA)nsWE42OutputDataInvalidtoEIM_CSx_BInvalidWE17–WE7–CSN—3–CSNnsMAXCOOutputmaximumdelayfrominternaldrivingEIM_ADDRxx/controlFFstochipoutputs10——nsMAXCSOOutputmaximumdelayfromCSxinternaldrivingFFstoCSxout10——nsMAXDIEIM_DATAxxmaximumdelayfromchipinputdatatoitsinternalFF5——nsWE43InputDataValidtoEIM_CSx_BInvalidMAXCO–MAXCSO+MAXDIMAXCO–MAXCSO+MAXDI—nsWE44EIM_CSx_BInvalidtoInputDatainvalid00—nsWE45EIM_CSx_BValidtoEIM_EBx_BValid(Writeaccess)WE12–WE6+(WBEA–WCSA)—3+(WBEA–WCSA)nsWE46EIM_EBx_BInvalidtoEIM_CSx_BInvalid(Writeaccess)WE7–WE13+(WBEN–WCSN)—–3+(WBEN–WCSN)nsTable46.
EIMasynchronoustimingparameterstablerelativechiptoselect(continued)RefNo.
ParameterDeterminationbySynchronousmeasuredparameters1MinMaxUnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors65MAXDTIMAXIMUMdelayfromEIM_DTACK_BtoitsinternalFF+2cyclesforsynchronization10——nsWE47EIM_DTACK_BActivetoEIM_CSx_BInvalidMAXCO–MAXCSO+MAXDTIMAXCO–MAXCSO+MAXDTI—nsWE48EIM_CSx_BInvalidtoEIM_DTACK_BInvalid00—ns1Formoreinformationonconfigurationparametersmentionedinthistable,seethei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
2Inthistable,CSAmeansWCSAwhenwriteoperationorRCSAwhenreadoperation.
3Inthistable,CSNmeansWCSNwhenwriteoperationorRCSNwhenreadoperation.
4tisaxi_clkcycletime.
5Inthistable,ADVNmeansWADVNwhenwriteoperationorRADVNwhenreadoperation.
6Inthistable,ADVAmeansWADVAwhenwriteoperationorRADVAwhenreadoperation.
Table46.
EIMasynchronoustimingparameterstablerelativechiptoselect(continued)RefNo.
ParameterDeterminationbySynchronousmeasuredparameters1MinMaxUnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors664.
8.
4DDRSDRAM-specificparameters(DDR3,DDR3L,LPDDR3,andLPDDR2)4.
8.
4.
1DDR3/DDR3LparametersFigure24showstheDDR3basictimingdiagramwiththetimingparametersprovidedinTable47.
Figure24.
DDR3CommandandAddressTimingDiagramTable47.
DDR3timingparametersIDParameterSymbolCK=533MHzUnitMinMaxDDR1DRAM_SDCLKx_Pclockhigh-levelwidthtCH0.
470.
53tCKDDR2DRAM_SDCLKx_Pclocklow-levelwidthtCL0.
470.
53tCKDDR4DRAM_CSx_B,DRAM_RAS_B,DRAM_CAS_B,DRAM_SDCKE,DRAM_SDWE_B,DRAM_SDODTxsetuptimetIS425—psDDR5DRAM_CSx_B,DRAM_RAS_B,DRAM_CAS_B,DRAM_SDCKE,DRAM_SDWE_B,DRAM_SDODTxholdtimetIH375—psDDR6AddressoutputsetuptimetIS425—psDDR7AddressoutputholdtimetIH375—psDRAM_SDWE_BDRAM_ADDRxxROW/BACOL/BADDR1DDR2DDR4DDR4DDR5DDR5DDR5DDR5DDR6DDR7DRAM_SDCLKx_PDRAM_ODTx/DDR4DRAM_SDCKExDRAM_SDCLKx_NDRAM_CSx_BDRAM_RAS_BDRAM_CAS_BDDR4Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors672AllmeasurementsareinreferencetoVreflevel.
3Measurementsweredoneusingbalancedloadand25ΩresistorfromoutputstoVDD_REF.
Figure25showstheDDR3writetimingdiagram.
ThetimingparametersforthisdiagramappearinTable48.
Figure25.
DDR3writecycle1Toreceivethereportedsetupandholdvalues,writecalibrationshouldbeperformedinordertolocatetheDRAM_SDQSx_PinthemiddleofDRAM_DATAxxwindow.
2AllmeasurementsareinreferencetoVreflevel.
3Measurementsweretakenusingbalancedloadand25ΩresistorfromoutputstoDDR_VREF.
Table48.
DDR3writecycleIDParameterSymbolCK=533MHzUnitMinMaxDDR17DRAM_DATAxxandDRAM_DQMxsetuptimetoDRAM_SDQSx_P(differentialstrobe)tDS225—psDDR18DRAM_DATAxxandDRAM_DQMxholdtimetoDRAM_SDQSx_P(differentialstrobe)tDH250—psDDR21DRAM_SDQSx_PlatchingrisingtransitionstoassociatedclockedgestDQSS-0.
25+0.
25tCKDDR22DRAM_SDQSx_PhighlevelwidthtDQSH0.
450.
55tCKDDR23DRAM_SDQSx_PlowlevelwidthtDQSL0.
450.
55tCKDRAM_SDCLKx_PDRAM_SDCLKx_NDRAM_SDQSx_PDRAM_DATAxxDRAM_DQMxDataDataDataDataDataDataDataDataDMDMDMDMDMDMDMDMDDR17DDR17DDR17DDR17DDR18DDR18DDR18DDR18DDR21DDR23DDR22(output)(output)(output)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors68Figure26showstheDDR3readtimingdiagram.
ThetimingparametersforthisdiagramappearinTable49.
Figure26.
DDR3readcycle1Toreceivethereportedsetupandholdvalues,readcalibrationshouldbeperformedinordertolocatetheDRAM_SDQSx_PinthemiddleofDRAM_DATAxxwindow.
2AllmeasurementsareinreferencetoVreflevel.
3Measurementsweredoneusingbalancedloadand25ΩresistorfromoutputstoVDD_REF.
4.
8.
4.
2LPDDR3parametersFigure27showstheLPDDR3basictimingdiagram.
ThetimingparametersforthisdiagramappearinTable50.
Figure27.
LPDDR3commandandaddresstimingdiagramTable49.
DDR3readcycleIDParameterSymbolCK=533MHzUnitMinMaxDDR26MinimumrequiredDRAM_DATAxxvalidwindowwidth—510—psDRAM_SDCLKx_PDRAM_SDCLKx_NDRAM_SDQSx_PDRAM_DATAxxDATADATADATADATADATADATADATADATADDR26(input)(input)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors69Figure28showstheLPDDR3writetimingdiagram.
ThetimingparametersforthisdiagramappearinTable51.
Figure28.
LPDDR3writecycleTable50.
LPDDR3timingparameters1,21AllmeasurementsareinreferencetoVreflevel.
2Measurementsweredoneusingbalancedloadand25ΩresistorfromoutputstoDDR_VREF.
IDParameterSymbolCK=533MHzUnitMinMaxLP1SDRAMclockhigh-levelwidthtCH0.
450.
55tCKLP2SDRAMclocklow-levelwidthtCL0.
450.
55tCKLP3DRAM_CSx_BtIS390—psLP4DRAM_CSx_EtIH390—psLP3DRAM_CAS_BsetuptimetIS275—psLP4DRAM_CAS_BholdtimetIH275—psElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors70Figure29showstheLPDDR3readtimingdiagram.
ThetimingparametersforthisdiagramappearinTable52.
Figure29.
LPDDR3readcycleTable51.
LPDDR3writecycle1,2,31Toreceivethereportedsetupandholdvalues,writecalibrationshouldbeperformedinordertolocatetheDRAM_SDQSinthemiddleofDRAM_DATAxxwindow.
2AllmeasurementsareinreferencetoVreflevel.
3Measurementsweredoneusingbalancedloadand25ΩresistorfromoutputstoDDR_VREF.
IDParameterSymbolCK=533MHzUnitMinMaxLP17DRAM_DATAxxandDRAM_DQMxsetuptimetoDRAM_SDQSx_P(differentialstrobe)tDS275—psLP18DRAM_DATAxxandDRAM_DQMxholdtimetoDRAM_SDQSx_P(differentialstrobe)tDH275—psLP21DRAM_SDQSx_PlatchingrisingtransitionstoassociatedclockedgestDQSS-0.
25+0.
25tCKLP22DRAM_SDQSx_PhighlevelwidthtDQSH0.
4—tCKLP23DRAM_SDQSx_PlowlevelwidthtDQSL0.
4—tCKTable52.
LPDDR3readcycle1,2,31Toreceivethereportedsetupandholdvalues,readcalibrationshouldbeperformedinordertolocatetheDRAM_SDQSx_PinthemiddleofDRAM_DATA_xxwindow.
2AllmeasurementsareinreferencetoVreflevel.
3Measurementsweredoneusingbalancedloadand25ΩresistorfromoutputstoDDR_VREF.
IDParameterSymbolCK=533MHzUnitMinMaxLP26MinimumrequiredDRAM_DATAxxvalidwindowwidthforLPDDR3—460—psElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors714.
8.
4.
3LPDDR2parametersFigure30showstheLPDDR2basictimingdiagram.
ThetimingparametersforthisdiagramappearinTable53.
Figure30.
LPDDR2commandandaddresstimingdiagramTable53.
LPDDR2timingparameters1,21AllmeasurementsareinreferencetoVreflevel.
2Measurementsweredoneusingbalancedloadand25ΩresistorfromoutputstoDDR_VREFIDParameterSymbolCK=533MHzUnitMinMaxLP1SDRAMclockhigh-levelwidthtCH0.
450.
55tCKLP2SDRAMclocklow-levelwidthtCL0.
450.
55tCKLP3DRAM_CSx_B,DRAM_SDCKExsetuptimetIS370—psLP4DRAM_CSx_B,DRAM_SDCKExholdtimetIH370—psLP3DRAM_CAS_BsetuptimetIS770—psLP4DRAM_CAS_BholdtimetIH770—psDRAM_SDCLKx_PDRAM_CSx_BDRAM_SDCKExDRAM_CAS_BLP4LP4LP3LP4LP3LP2LP3LP3LP1Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors72Figure31showstheLPDDR2writetimingdiagram.
ThetimingparametersforthisdiagramappearinTable54.
Figure31.
LPDDR2writecycle1Toreceivethereportedsetupandholdvalues,writecalibrationshouldbeperformedinordertolocatetheDRAM_SDQSinthemiddleofDRAM_DATAxxwindow.
2AllmeasurementsareinreferencetoVreflevel.
3Measurementsweredoneusingbalancedloadand25ΩresistorfromoutputstoDDR_VREF.
Table54.
LPDDR2writecycleIDParameterSymbolCK=533MHzUnitMinMaxLP17DRAM_DATAxxandDRAM_DQMxsetuptimetoDRAM_SDQSx_P(differentialstrobe)tDS360—psLP18DRAM_DATAxxandDRAM_DQMxholdtimetoDRAM_SDQSx_P(differentialstrobe)tDH360—psLP21DRAM_SDQSx_PlatchingrisingtransitionstoassociatedclockedgestDQSS-0.
25+0.
25tCKLP22DRAM_SDQSx_PhighlevelwidthtDQSH0.
4—tCKLP23DRAM_SDQSx_PlowlevelwidthtDQSL0.
4—tCKDRAM_SDCLKx_PDRAM_SDCLKx_NDRAM_SDCLKx_PDRAM_DATAxxDRAM_DQMxDataDataDataDataDataDataDataDataDMDMDMDMDMDMDMDMLP17LP17LP17LP17LP18LP18LP18LP18LP21LP23LP22(output)(output)(output)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors73Figure32showstheLPDDR2readtimingdiagram.
ThetimingparametersforthisdiagramappearinTable55.
Figure32.
LPDDR2readcycle1Toreceivethereportedsetupandholdvalues,readcalibrationshouldbeperformedinordertolocatetheDRAM_SDQSx_PinthemiddleofDRAM_DATA_xxwindow.
2AllmeasurementsareinreferencetoVreflevel.
3Measurementsweredoneusingbalancedloadand25ΩresistorfromoutputstoDDR_VREF.
4.
9General-purposemediainterface(GPMI)timingThei.
MX7DualGPMIcontrollerisaflexibleinterfaceNANDFlashcontrollerwith8-bitdatawidth,upto200MB/sI/Ospeedandindividualchipselect.
ItsupportsAsynchronousTimingmode,SourceSynchronousTimingmodeandToggleTimingmodeseparately,asdescribedinthefollowingsubsections.
4.
9.
1AsynchronousmodeACtiming(ONFI1.
0compatible)AsynchronousmodeACtimingsareprovidedasmultiplicationsoftheclockcycleandfixeddelay.
ThemaximumI/OspeedofGPMIinasynchronousmodeisabout50MB/s.
Figure33throughFigure36depictstherelativetimingbetweenGPMIsignalsatthemodulelevelfordifferentoperationsunderasynchronousmode.
Table56describesthetimingparameters(NF1–NF17)thatareshowninthefigures.
Table55.
LPDDR2readcycleIDParameterSymbolCK=533MHzUnitMinMaxLP26MinimumrequiredDRAM_DATAxxvalidwindowwidthforLPDDR2—230—psDRAM_SDCLKx_PDRAM_SDCLKx_NDRAM_SDQSx_PDRAM_DATAxxDATADATADATADATADATADATADATADATALP26(input)(input)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors74Figure33.
CommandLatchcycletimingdiagramFigure34.
AddressLatchcycletimingdiagramFigure35.
WriteDataLatchcycletimingdiagramFigure36.
ReadDataLatchcycletimingdiagram(Non-EDOMode).
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MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors75Figure37.
ReadDataLatchcycletimingdiagram(EDOmode)Table56.
Asynchronousmodetimingparameters11GPMI'sAsynchronousmodeoutputtimingcanbecontrolledbythemodule'sinternalregistersHW_GPMI_TIMING0_ADDRESS_SETUP,HW_GPMI_TIMING0_DATA_SETUP,andHW_GPMI_TIMING0_DATA_HOLD.
ThisACtimingdependsontheseregisterssettings.
Inthetable,AS/DS/DHrepresentseachofthesesettings.
IDParameterSymbolTimingT=GPMIClockCycleUnitMin.
Max.
NF1NAND_CLEsetuptimetCLS(AS+DS)*T-0.
12[seenotes2,3]2ASminimumvaluecanbe0,whileDS/DHminimumvalueis1.
3T=GPMIclockperiod-0.
075ns(halfofmaximump-pjitter).
nsNF2NAND_CLEholdtimetCLHDH*T-0.
72[seenote2]nsNF3NAND_CE0_BsetuptimetCS(AS+DS+1)*T[seenotes3,2]nsNF4NAND_CE0_BholdtimetCH(DH+1)*T-1[seenote2]nsNF5NAND_WE_BpulsewidthtWPDS*T[seenote2]nsNF6NAND_ALEsetuptimetALS(AS+DS)*T-0.
49[seenotes3,2]nsNF7NAND_ALEholdtimetALH(DH*T-0.
42[seenote2]nsNF8DatasetuptimetDSDS*T-0.
26[seenote2]nsNF9DataholdtimetDHDH*T-1.
37[seenote2]nsNF10WritecycletimetWC(DS+DH)*T[seenote2]nsNF11NAND_WE_BholdtimetWHDH*T[seenote2]nsNF12ReadytoNAND_RE_BlowtRR44NF12isguaranteedbythedesign.
(AS+2)*T[see3,2]—nsNF13NAND_RE_BpulsewidthtRPDS*T[seenote2]nsNF14READcycletimetRC(DS+DH)*T[seenote2]nsNF15NAND_RE_BhighholdtimetREHDH*T[seenote2]nsNF16DatasetuponreadtDSR—(DS*T-0.
67)/18.
38[seenotes5,6]5Non-EDOmode.
6EDOmode,GPMIclock≈100MHz(AS=DS=DH=1,GPMI_CTL1[RDN_DELAY]=8,GPMI_CTL1[HALF_PERIOD]=0).
nsNF17DataholdonreadtDHR0.
82/11.
83[seenotes5,6]—nsE&E&E&E&E&E&E&.
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MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors76InEDOmode(Figure36),NF16/NF17aredifferentfromthedefinitioninnon-EDOmode(Figure35).
TheyarecalledtREA/tRHOH(RE#accesstime/RE#HIGHtooutputhold).
Thetypicalvalueforthemare16ns(maxfortREA)/15ns(minfortRHOH)at50MB/sEDOmode.
InEDOmode,GPMIwillsampleNAND_DATAxxatrisingedgeofdelayedNAND_RE_BprovidedbyaninternalDPLL.
ThedelayvaluecanbecontrolledbyGPMI_CTRL1.
RDN_DELAY(seetheGPMIchapterofthei.
MX7DualApplicationProcessorReferenceManual[IMX7DRM]).
Thetypicalvalueofthiscontrolregisteris0x8at50MT/sEDOmode.
Butiftheboarddelayisbigenoughandcannotbeignored,thedelayvalueshouldbemadelargertocompensatetheboarddelay.
4.
9.
2SourceSynchronousmodeACtiming(ONFI2.
xcompatible)Figure38toFigure40showthewriteandreadtimingofSourceSynchronousmode.
Figure38.
SourceSynchronousmodecommandandaddresstimingdiagram1)1)1)1)1)1)1)1)1)1)1)1)1)&0'$''1$1'B&/(1$1'B$/(1$1'B:(5(B%1$1'B&/.
1$1'B'461$1'B'462XWSXWHQDEOH1$1'B'$7$>@1$1'B'$7$>@2XWSXWHQDEOHElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors77Figure39.
SourceSynchronousmodedatawritetimingdiagramFigure40.
SourceSynchronousmodedatareadtimingdiagram1)1)1)1)1)1)1)1)1)1)1)1)1)1)1)1)1).
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MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors78Figure41.
NAND_DQS/NAND_DQReadValidwindowForDDRSourceSynchronousmode,Figure41showsthetimingdiagramofNAND_DQS/NAND_DATAxxreadvalidwindow.
ThetypicalvalueoftDQSQis0.
85ns(max)and1ns(max)fortQHSat200MB/s.
GPMIwillsampleNAND_DATA[7:0]atbothrisingandfallingedgeofandelayedNAND_DQSsignal,whichcanbeprovidedbyaninternalDPLL.
ThedelayvaluecanbecontrolledbyGPMIregisterGPMI_READ_DDR_DLL_CTRL.
SLV_DLY_TARGET(seetheGPMIchapterofthei.
MX7DualApplicationProcessorReferenceManual[IMX7DRM]).
Generally,thetypicaldelayvalueofthisregisterisequalto0x7whichmeans1/4clockcycledelayexpected.
Butiftheboarddelayisbigenoughandcannotbeignored,thedelayvalueshouldbemadelargertocompensatetheboarddelay.
Table57.
SourceSynchronousmodetimingparameters11GPMI'sSourceSynchronousmodeoutputtimingcanbecontrolledbythemodule'sinternalregistersGPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.
ThisACtimingdependsontheseregisterssettings.
Inthetable,CE_DELAY/PRE_DELAY/POST_DELAYrepresentseachofthesesettings.
IDParameterSymbolTimingT=GPMIClockCycleUnitMin.
Max.
NF18NAND_CE0_BaccesstimetCECE_DELAY*T-0.
79[seenote2]2T=tCK(GPMIclockperiod)–0.
075ns(halfofmaximump-pjitter).
nsNF19NAND_CE0_BholdtimetCH0.
5*tCK-0.
63[seenote2]nsNF20Command/addressNAND_DATAxxsetuptimetCAS0.
5*tCK-0.
05nsNF21Command/addressNAND_DATAxxholdtimetCAH0.
5*tCK-1.
23nsNF22clockperiodtCK—nsNF23preambledelaytPREPRE_DELAY*T-0.
29[seenote2]nsNF24postambledelaytPOSTPOST_DELAY*T-0.
78[seenote2]nsNF25NAND_CLEandNAND_ALEsetuptimetCALS0.
5*tCK-0.
86nsNF26NAND_CLEandNAND_ALEholdtimetCALH0.
5*tCK-0.
37nsNF27NAND_CLKtofirstNAND_DQSlatchingtransitiontDQSST-0.
41[seenote2]nsNF28Datawritesetup0.
25*tCK-0.
35NF29Datawritehold0.
25*tCK-0.
85NF30NAND_DQS/NAND_DQreadsetupskew—2.
06NF31NAND_DQS/NAND_DQreadholdskew—1.
95.
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MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors794.
9.
3ONFINV-DDR2mode(ONFI3.
2compatible)4.
9.
3.
1CommandandaddresstimingONFI3.
2modecommandandaddresstimingisthesameasONFI1.
0compatibleAsyncmodeACtiming.
SeeSection4.
9.
1,"AsynchronousmodeACtiming(ONFI1.
0compatible),"fordetails.
4.
9.
3.
2ReadandwritetimingONFI3.
2modereadandwritetimingisthesameasTogglemodeACtiming.
SeeSection4.
9.
4,"TogglemodeACTiming,"fordetails.
4.
9.
4TogglemodeACTiming4.
9.
4.
1CommandandaddresstimingNOTETogglemodecommandandaddresstimingisthesameasONFI1.
0compatibleAsynchronousmodeACtiming.
SeeSection4.
9.
1,"AsynchronousmodeACtiming(ONFI1.
0compatible),"fordetails.
4.
9.
4.
2ReadandwritetimingFigure42.
TogglemodedatawritetimingElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors80Figure43.
TogglemodedatareadtimingTable58.
Togglemodetimingparameters1IDParameterSymbolTimingT=GPMIClockCycleUnitMin.
Max.
NF1NAND_CLEsetuptimetCLS(AS+DS)*T-0.
12[seenote2s,3]NF2NAND_CLEholdtimetCLHDH*T-0.
72[seenote2]NF3NAND_CE0_BsetuptimetCS(AS+DS)*T-0.
58[seenotes,2]NF4NAND_CE0_BholdtimetCHDH*T-1[seenote2]NF5NAND_WE_BpulsewidthtWPDS*T[seenote2]NF6NAND_ALEsetuptimetALS(AS+DS)*T-0.
49[seenotes,2]NF7NAND_ALEholdtimetALHDH*T-0.
42[seenote2]NF8Command/addressNAND_DATAxxsetuptimetCASDS*T-0.
26[seenote2]NF9Command/addressNAND_DATAxxholdtimetCAHDH*T-1.
37[seenote2]NF18NAND_CEx_BaccesstimetCECE_DELAY*T[seenotes4,2]—nsNF22clockperiodtCK——nsNF23preambledelaytPREPRE_DELAY*T[seenotes5,2]—nsNF24postambledelaytPOSTPOST_DELAY*T+0.
43[seenote2]—nsDEVCLK.
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&T#+T#+.
&T#+Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors81ForDDRTogglemode,Figure41showsthetimingdiagramofNAND_DQS/NAND_DATAxxreadvalidwindow.
ThetypicalvalueoftDQSQis1.
4ns(max)and1.
4ns(max)fortQHSat133MB/s.
GPMIwillsampleNAND_DATA[7:0]atbothrisingandfallingedgeofandelayedNAND_DQSsignal,whichisprovidedbyaninternalDPLL.
ThedelayvalueofthisregistercanbecontrolledbyGPMIregisterGPMI_READ_DDR_DLL_CTRL.
SLV_DLY_TARGET(seetheGPMIchapterofthei.
MX7DualApplicationProcessorReferenceManual[IMX7DRM]).
Generally,thetypicaldelayvalueisequalto0x7whichmeans1/4clockcycledelayexpected.
Butiftheboarddelayisbigenoughandcannotbeignored,thedelayvalueshouldbemadelargertocompensatetheboarddelay.
4.
10ExternalperipheralinterfaceparametersThefollowingsubsectionsprovideinformationonexternalperipheralinterfaces.
4.
10.
1ECSPItimingparametersThissectiondescribesthetimingparametersoftheECSPIblocks.
TheECSPIhaveseparatetimingparametersformasterandslavemodes.
NF28DatawritesetuptDS60.
25*tCK-0.
32—nsNF29DatawriteholdtDH60.
25*tCK-0.
79—nsNF30NAND_DQS/NAND_DQreadsetupskewtDQSQ7—3.
18NF31NAND_DQS/NAND_DQreadholdskewtQHS7—3.
271TheGPMItogglemodeoutputtimingcanbecontrolledbythemodule'sinternalregistersHW_GPMI_TIMING0_ADDRESS_SETUP,HW_GPMI_TIMING0_DATA_SETUP,andHW_GPMI_TIMING0_DATA_HOLD.
ThisACtimingdependsontheseregisterssettings.
Inthetable,AS/DS/DHrepresentseachofthesesettings.
2ASminimumvaluecanbe0,whileDS/DHminimumvalueis1.
3T=tCK(GPMIclockperiod)-0.
075ns(halfofmaximump-pjitter).
4CE_DELAYrepresentsHW_GPMI_TIMING2[CE_DELAY].
NF18isguaranteedbythedesign.
Read/WriteoperationisstartedwithenoughtimeofALE/CLEassertiontolowlevel.
5PRE_DELAY+1)≥(AS+DS)6ShowninFigure42.
7ShowninFigure43.
Table58.
Togglemodetimingparameters1(continued)IDParameterSymbolTimingT=GPMIClockCycleUnitMin.
Max.
Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors824.
10.
1.
1ECSPIMastermodetimingFigure44depictsthetimingofECSPIinmastermode.
Table59liststheECSPImastermodetimingcharacteristics.
Figure44.
ECSPIMastermodetimingdiagramTable59.
ECSPIMastermodetimingparametersIDParameterSymbolMinMaxUnitCS1ECSPIx_SCLKCycleTime–ReadECSPIx_SCLKCycleTime–Writetclk4315—nsCS2ECSPIx_SCLKHighorLowTime–ReadECSPIx_SCLKHighorLowTime–WritetSW21.
57—nsCS3ECSPIx_SCLKRiseorFall11SeespecificI/OACparametersSection4.
6,"I/OACparameters.
"tRISE/FALL——nsCS4ECSPIx_SS_BpulsewidthtCSLHHalfECSPIx_SCLKperiod—nsCS5ECSPIx_SS_BLeadTime(CSsetuptime)tSCSHalfECSPIx_SCLKperiod-4—nsCS6ECSPIx_SS_BLagTime(CSholdtime)tHCSHalfECSPIx_SCLKperiod-2—nsCS7ECSPIx_MOSIPropagationDelay(CLOAD=20pF)tPDmosi-11nsCS8ECSPIx_MISOSetupTimetSmiso18—nsCS9ECSPIx_MISOHoldTimetHmiso0—nsCS10RDYtoECSPIx_SS_BTime22SPI_RDYissampledinternallybyipg_clkandisasynchronoustoallotherCSPIsignals.
tSDRY5—nsCS7CS2CS2CS4CS6CS5CS8CS9ECSPIx_SCLKECSPIx_SS_BECSPIx_MOSIECSPIx_MISOECSPIx_RDY_BCS10CS3CS3CS1Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors834.
10.
1.
2ECSPISlavemodetimingFigure45depictsthetimingofECSPIinSlavemode.
Table60liststheECSPISlavemodetimingcharacteristics.
Figure45.
ECSPISlavemodetimingdiagramTable60.
ECSPISlavemodetimingparametersIDParameterSymbolMinMaxUnitCS1ECSPIx_SCLKCycleTime–ReadECSPI_SCLKCycleTime–Writetclk1543—nsCS2ECSPIx_SCLKHighorLowTime–ReadECSPIx_SCLKHighorLowTime–WritetSW721.
5—nsCS4ECSPIx_SS_BpulsewidthtCSLHHalfECSPIx_SCLKperiod—nsCS5ECSPIx_SS_BLeadTime(CSsetuptime)tSCS5—nsCS6ECSPIx_SS_BLagTime(CSholdtime)tHCS5—nsCS7ECSPIx_MOSISetupTimetSmosi4—nsCS8ECSPIx_MOSIHoldTimetHmosi4—nsCS9ECSPIx_MISOPropagationDelay(CLOAD=20pF)tPDmiso419nsCS1CS7CS8CS2CS2CS4CS6CS5CS9ECSPIx_SCLKECSPIx_SS_BECSPIx_MISOECSPIx_MOSIElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors844.
10.
2Ultra-high-speedSD/SDIO/MMChostinterface(uSDHC)ACtimingThissectiondescribestheelectricalinformationoftheuSDHC,whichincludesSD/eMMC4.
3(singledatarate)timing,eMMC4.
4/4.
41(dualdatarate)timingandSDR104/50(SD3.
0)timing.
4.
10.
2.
1SD/eMMC4.
3(singledatarate)ACtimingFigure46depictsthetimingofSD/eMMC4.
3,andTable61liststheSD/eMMC4.
3timingcharacteristics.
Figure46.
SD/eMMC4.
3TimingTable61.
SD/eMMC4.
3interfacetimingspecificationIDParameterSymbolsMinMaxUnitCardInputClockSD1ClockFrequency(LowSpeed)fPP10400kHzClockFrequency(SD/SDIOFullSpeed/HighSpeed)fPP2025/50MHzClockFrequency(MMCFullSpeed/HighSpeed)fPP3020/52MHzClockFrequency(IdentificationMode)fOD100400kHzSD2ClockLowTimetWL7—nsSD3ClockHighTimetWH7—nsSD4ClockRiseTimetTLH—3nsSD5ClockFallTimetTHL—3nsuSDHCOutput/CardInputsSD_CMD,SDx_DATAx(ReferencetoCLK)SD6uSDHCOutputDelaytOD-6.
63.
6nsSD1SD3SD5SD4SD7SDx_CLKSD2SD8SD6OutputfromuSDHCtocardInputfromcardtouSDHCSDx_DATA[7:0]SDx_DATA[7:0]Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors854.
10.
2.
2eMMC4.
4/4.
41(dualdatarate)ACtimingFigure47depictsthetimingofeMMC4.
4/4.
41.
Table62liststheeMMC4.
4/4.
41timingcharacteristics.
BeawarethatonlyDATAissampledonbothedgesoftheclock(notapplicabletoCMD).
Figure47.
eMMC4.
4/4.
41timinguSDHCInput/CardOutputsSD_CMD,SDx_DATAx(ReferencetoCLK)SD7uSDHCInputSetupTimetISU2.
5—nsSD8uSDHCInputHoldTime4tIH1.
5—ns1InLow-Speedmode,cardclockmustbelowerthan400kHz,voltagerangesfrom2.
7to3.
6V.
2InNormal(Full)-SpeedmodeforSD/SDIOcard,clockfrequencycanbeanyvaluebetween0–25MHz.
InHigh-speedmode,clockfrequencycanbeanyvaluebetween0–50MHz.
3InNormal(Full)-SpeedmodeforMMCcard,clockfrequencycanbeanyvaluebetween0–20MHz.
InHigh-speedmode,clockfrequencycanbeanyvaluebetween0–52MHz.
4Tosatisfyholdtiming,thedelaydifferencebetweenclockinputandcmd/datainputmustnotexceed2ns.
Table62.
eMMC4.
4/4.
41interfacetimingspecificationIDParameterSymbolsMinMaxUnitCardInputClockSD1ClockFrequency(eMMC4.
4/4.
41DDR)fPP052MHzSD1ClockFrequency(SD3.
0DDR)fPP050MHzuSDHCOutput/CardInputsSD_CMD,SDx_DATAx(ReferencetoCLK)SD2uSDHCOutputDelaytOD2.
76.
9nsuSDHCInput/CardOutputsSD_CMD,SDx_DATAx(ReferencetoCLK)Table61.
SD/eMMC4.
3interfacetimingspecification(continued)IDParameterSymbolsMinMaxUnitSD1SD2SD3OutputfromeSDHCv3tocardInputfromcardtoeSDHCv3SDx_DATA[7:0]SDx_CLKSD4SD2.
.
.
.
.
.
.
.
.
.
.
.
SDx_DATA[7:0]Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors864.
10.
2.
3HS400ACtiming—eMMC5.
0onlyFigure48depictsthetimingofHS400.
Table63liststheHS400timingcharacteristics.
Beawarethatonlydataissampledonbothedgesoftheclock(notapplicabletoCMD).
TheCMDinput/outputtimingforHS400modeisthesameasCMDinput/outputtimingforSDR104mode.
CheckSD5,SD6andSD7parametersinTable65SDR50/SDR104InterfaceTimingSpecificationforCMDinput/outputtimingforHS400mode.
Figure48.
HS400timingSD3uSDHCInputSetupTimetISU2.
4—nsSD4uSDHCInputHoldTimetIH1.
3—nsTable63.
HS400interfacetimingspecificationsIDParameterSymbolsMinMaxUnitCardInputclockSD1ClockFrequencyfPP0200MhzSD2ClockLowTimetCL0.
46*tCLK0.
54*tCLKnsSD3ClockHighTimetCH0.
46*tCLK0.
54*tCLKnsuSDHCOutput/CardinputsDAT(ReferencetoSCK)SD4OutputSkewfromDataofEdgeofSCKtOSkew10.
45—nsSD5OutputSkewfromEdgeofSCKtoDatatOSkew20.
45—nsTable62.
eMMC4.
4/4.
41interfacetimingspecification(continued)IDParameterSymbolsMinMaxUnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors874.
10.
2.
4HS200ModeTimingFigure49depictsthetimingofHS200mode,andTable64liststheHS200timingcharacteristics.
Figure49.
HS200ModeTiminguSDHCinput/CardOutputsDAT(ReferencetoStrobe)SD6uSDHCinputskewtRQ—0.
45nsSD7uSDHCholdskewtRQH—0.
45nsTable64.
HS200InterfaceTimingSpecificationIDParameterSymbolsMinMaxUnitCardInputClockSD1ClockFrequencyPeriodtCLK5.
0—nsSD2ClockLowTimetCL0.
3*tCLK0.
7*tCLKnsSD2ClockHighTimetCH0.
3*tCLK0.
7*tCLKnsuSDHCOutput/CardInputsSD_CMD,SDx_DATAxinHS200(ReferencetoCLK)SD5uSDHCOutputDelaytOD–1.
61nsuSDHCInput/CardOutputsSD_CMD,SDx_DATAxinHS200(ReferencetoCLK)11HS200isfor8bitswhileSDR104isfor4bits.
SD8CardOutputDataWindowtODW0.
5*tCLK—nsTable63.
HS400interfacetimingspecifications(continued)IDParameterSymbolsMinMaxUnit6&.
ELWRXWSXWIURPX6'+&WRH00&ELWLQSXWIURPH00&WRX6'+&6'6'6'6'6'6'6'6'Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors884.
10.
2.
5SDR50/SDR104ACtimingFigure50depictsthetimingofSDR50/SDR104,andTable65liststheSDR50/SDR104timingcharacteristics.
Figure50.
SDR50/SDR104timingTable65.
SDR50/SDR104interfacetimingspecificationIDParameterSymbolsMinMaxUnitCardInputClockSD1ClockFrequencyPeriodtCLK5—nsSD2ClockLowTimetCL0.
46*tCLK0.
54*tCLKnsSD3ClockHighTimetCH0.
46*tCLK0.
54*tCLKnsuSDHCOutput/CardInputsSD_CMD,SDx_DATAxinSDR50(ReferencetoCLK)SD4uSDHCOutputDelaytOD–31nsuSDHCOutput/CardInputsSD_CMD,SDx_DATAxinSDR104(ReferencetoCLK)SD5uSDHCOutputDelaytOD–1.
61nsuSDHCInput/CardOutputsSD_CMD,SDx_DATAxinSDR50(ReferencetoCLK)SD6uSDHCInputSetupTimetISU2.
4—nsSD7uSDHCInputHoldTimetIH1.
4—nsuSDHCInput/CardOutputsSD_CMD,SDx_DATAxinSDR104(ReferencetoCLK)11DatawindowinSDR100modeisvariable.
SD8CardOutputDataWindowtODW0.
5*tCLK—nsSCK8-bitoutputfromuSDHCtoeMMC8-bitinputfromeMMCtouSDHCSD8SD7SD6SD4/SD5SD2SD3SD1Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors894.
10.
2.
6Busoperationconditionfor3.
3Vand1.
8VsignalingSignalinglevelofSD/eMMC4.
3andeMMC4.
4/4.
41modesis3.
3V.
SignalinglevelofSDR104/SDR50modeis1.
8V.
TheDCparametersfortheNVCC_SD1,NVCC_SD2andNVCC_SD3suppliesareidenticaltothoseshowninTable29,"GPIODCParameters,"onpage44.
4.
10.
3Ethernetcontroller(ENET)ACelectricalspecificationsThefollowingtimingspecsaredefinedatthechipI/Opinandmustbetranslatedappropriatelytoarriveattimingspecs/constraintsforthephysicalinterface.
4.
10.
3.
1ENETMIImodetimingThissubsectiondescribesMIIreceive,transmit,asynchronousinputs,andserialmanagementsignaltimings.
4.
10.
3.
1.
1MIIreceivesignaltiming(ENET_RX_DATA3,2,1,0,ENET_RX_EN,ENET_RX_ER,andENET_RX_CLK)ThereceiverfunctionscorrectlyuptoanENET_RX_CLKmaximumfrequencyof25MHz+1%.
Thereisnominimumfrequencyrequirement.
Additionally,theprocessorclockfrequencymustexceedtwicetheENET_RX_CLKfrequency.
Figure51showsMIIreceivesignaltimings.
Table66describesthetimingparameters(M1–M4)showninthefigure.
Figure51.
MIIreceivesignaltimingdiagramENET_RX_CLK(input)ENET_RX_DATA3,2,1,0M3M4M1M2ENET_RX_ERENET_RX_EN(inputs)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors901ENET_RX_EN,ENET_RX_CLK,andENET0_RXD0havethesametimingin10Mbps7-wireinterfacemode.
4.
10.
3.
1.
2MIItransmitsignaltiming(ENET_TX_DATA3,2,1,0,ENET_TX_EN,ENET_TX_ER,andENET_TX_CLK)ThetransmitterfunctionscorrectlyuptoanENET_TX_CLKmaximumfrequencyof25MHz+1%.
Thereisnominimumfrequencyrequirement.
Additionally,theprocessorclockfrequencymustexceedtwicetheENET_TX_CLKfrequency.
Figure52showsMIItransmitsignaltimings.
Table67describesthetimingparameters(M5–M8)showninthefigure.
Figure52.
MIItransmitsignaltimingdiagram1ENET_TX_EN,ENET_TX_CLK,andENET0_TXD0havethesametimingin10-Mbps7-wireinterfacemode.
Table66.
MIIreceivesignaltimingIDCharacteristic1Min.
Max.
UnitM1ENET_RX_DATA3,2,1,0,ENET_RX_EN,ENET_RX_ERtoENET_RX_CLKsetup5—nsM2ENET_RX_CLKtoENET_RX_DATA3,2,1,0,ENET_RX_EN,ENET_RX_ERhold5—nsM3ENET_RX_CLKpulsewidthhigh35%65%ENET_RX_CLKperiodM4ENET_RX_CLKpulsewidthlow35%65%ENET_RX_CLKperiodTable67.
MIItransmitsignaltimingIDCharacteristic1Min.
Max.
UnitM5ENET_TX_CLKtoENET_TX_DATA3,2,1,0,ENET_TX_EN,ENET_TX_ERinvalid5—nsM6ENET_TX_CLKtoENET_TX_DATA3,2,1,0,ENET_TX_EN,ENET_TX_ERvalid—20nsM7ENET_TX_CLKpulsewidthhigh35%65%ENET_TX_CLKperiodM8ENET_TX_CLKpulsewidthlow35%65%ENET_TX_CLKperiodENET_TX_CLK(input)ENET_TX_DATA3,2,1,0M7M8M5M6ENET_TX_ERENET_TX_EN(outputs)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors914.
10.
3.
1.
3MIIasynchronousinputssignaltiming(ENET_CRSandENET_COL)Figure53showsMIIasynchronousinputtimings.
Table68describesthetimingparameter(M9)showninthefigure.
Figure53.
MIIasyncinputstimingdiagram1ENET_COLhasthesametimingin10-Mbit7-wireinterfacemode.
4.
10.
3.
1.
4MIISerialmanagementchanneltiming(ENET_MDIOandENET_MDC)TheMDCfrequencyisdesignedtobeequaltoorlessthan2.
5MHztobecompatiblewiththeIEEE802.
3MIIspecification.
HowevertheENETcanfunctioncorrectlywithamaximumMDCfrequencyof15MHz.
Figure54showsMIIasynchronousinputtimings.
Table69describesthetimingparameters(M10–M15)showninthefigure.
Figure54.
MIIserialmanagementchanneltimingdiagramTable68.
MIIasynchronousinputssignaltimingIDCharacteristicMin.
Max.
UnitM91ENET_CRStoENET_COLminimumpulsewidth1.
5—ENET_TX_CLKperiodENET_CRS,ENET_COLM9ENET_MDC(output)ENET_MDIO(output)M14M15M10M11M12M13ENET_MDIO(input)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors924.
10.
3.
2RMIImodetimingInRMIImode,ENET_CLKisusedastheREF_CLK,whichisa50MHz±50ppmcontinuousreferenceclock.
ENET_RX_ENisusedastheENET_RX_ENinRMII.
OthersignalsunderRMIImodeincludeENET_TX_EN,ENET_TX_DATA[1:0],ENET_RX_DATA[1:0]andENET_RX_ER.
Figure55showsRMIImodetimings.
Table70describesthetimingparameters(M16–M21)showninthefigure.
Figure55.
RMIImodesignaltimingdiagramTable69.
MIIserialmanagementchanneltimingIDCharacteristicMin.
Max.
UnitM10ENET_MDCfallingedgetoENET_MDIOoutputinvalid(min.
propagationdelay)0—nsM11ENET_MDCfallingedgetoENET_MDIOoutputvalid(max.
propagationdelay)—5nsM12ENET_MDIO(input)toENET_MDCrisingedgesetup18—nsM13ENET_MDIO(input)toENET_MDCrisingedgehold0—nsM14ENET_MDCpulsewidthhigh40%60%ENET_MDCperiodM15ENET_MDCpulsewidthlow40%60%ENET_MDCperiodENET_CLK(input)ENET_TX_ENM16M17M18M19M20M21ENET_RX_DATA[1:0]ENET_TX_DATA(output)ENET_RX_ERENET_RX_EN(input)Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors934.
10.
3.
3SignalswitchingspecificationsThefollowingtimingspecificationsmeettherequirementsforRGMIIinterfacesforarangeoftransceiverdevices.
Table70.
RMIIsignaltimingIDCharacteristicMin.
Max.
UnitM16ENET_CLKpulsewidthhigh35%65%ENET_CLKperiodM17ENET_CLKpulsewidthlow35%65%ENET_CLKperiodM18ENET_CLKtoENET0_TXD[1:0],ENET_TX_DATAinvalid4—nsM19ENET_CLKtoENET0_TXD[1:0],ENET_TX_DATAvalid—15nsM20ENET_RX_DATAD[1:0],ENET_RX_EN(ENET_RX_EN),ENET_RX_ERtoENET_CLKsetup4—nsM21ENET_CLKtoENET_RX_DATAD[1:0],ENET_RX_EN,ENET_RX_ERhold2—nsTable71.
RGMIIsignalswitchingspecifications11Thetimingsassumethefollowingconfiguration:DDR_SEL=(11)bDSE(drive-strength)=(111)bSymbolDescriptionMin.
Max.
UnitTcyc22For10Mbpsand100Mbps,Tcycwillscaleto400ns±40nsand40ns±4nsrespectively.
Clockcycleduration7.
28.
8nsTskewT33ForallversionsofRGMIIpriorto2.
0;ThisimpliesthatPCboarddesignwillrequireclockstoberoutedsuchthatanadditionaltracedelayofgreaterthan1.
5nsandlessthan2.
0nswillbeaddedtotheassociatedclocksignal.
For10/100,theMaxvalueisunspecified.
Datatoclockoutputskewattransmitter-500500psTskewR3Datatoclockinputskewatreceiver12.
6nsDuty_G44Dutycyclemaybestretched/shrunkduringspeedchangesorwhiletransitioningtoareceivedpacket'sclockdomainaslongasminimumdutycycleisnotviolatedandstretchingoccursfornomorethanthreeTcycofthelowestspeedtransitionedbetween.
DutycycleforGigabit4555%Duty_T4Dutycyclefor10/100T4060%Tr/TfRise/falltime(20–80%)—0.
75nsElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors94Figure56.
RGMIItransmitsignaltimingdiagramoriginalFigure57.
RGMIIreceivesignaltimingdiagramoriginalFigure58.
RGMIIreceivesignaltimingdiagramwithinternaldelay4.
10.
4Flexiblecontrollerareanetwork(flexcan)acelectricalspecificationsTheFlexibleControllerAreaNetwork(FlexCAN)moduleisacommunicationcontrollerimplementingtheCANprotocolaccordingtotheCAN2.
0Bprotocolspecification.
TheprocessorhastwoCANmodulesavailableforsystemsdesign.
TxandRxportsforbothmodulesaremultiplexedwithotherI/Opins.
SeetheIOMUXCchapterofthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)toseewhichpinsexposeTxandRxpins;theseportsarenamedFLEXCAN_TXandFLEXCAN_RX,respectively.
2'-))48#ATTRANSMITTER2'-))48$NNTO2'-))48#4,2'-))48#ATRECEIVER4SKEW448%.
48%224SKEW22'-))28#ATTRANSMITTER2'-))28$NNTO2'-))28#4,2'-))28#ATRECEIVER4SKEW428$628%224SKEW22'-))28#SOURCEOFDATA2'-))28$NNTO2'-))28#4,2'-))28#ATRECEIVER)NTERNALDELAY4SETUP44HOLD44SETUP24HOLD228$628%22Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors954.
10.
5I2CmoduletimingparametersThissectiondescribesthetimingparametersoftheI2Cmodule.
Figure59depictsthetimingofI2Cmodule,andTable72liststheI2Cmoduletimingcharacteristics.
Figure59.
I2CbustimingTable72.
I2CmoduletimingparametersIDParameterStandardModeFastModeUnitMinMaxMinMaxIC1I2Cx_SCLcycletime10—2.
5—sIC2Holdtime(repeated)STARTcondition4.
0—0.
6—sIC3Set-uptimeforSTOPcondition4.
0—0.
6—sIC4Dataholdtime011Adevicemustinternallyprovideaholdtimeofatleast300nsforI2Cx_SDAsignaltobridgetheundefinedregionofthefallingedgeofI2Cx_SCL.
3.
4522ThemaximumholdtimehasonlytobemetifthedevicedoesnotstretchtheLOWperiod(IDnoIC5)oftheI2Cx_SCLsignal.
010.
92sIC5HIGHPeriodofI2Cx_SCLClock4.
0—0.
6—sIC6LOWPeriodoftheI2Cx_SCLClock4.
7—1.
3—sIC7Set-uptimeforarepeatedSTARTcondition4.
7—0.
6—sIC8Dataset-uptime250—10033AFast-modeI2C-busdevicecanbeusedinaStandard-modeI2C-bussystem,buttherequirementofSet-uptime(IDNoIC7)of250nsmustbemet.
ThisautomaticallyisthecaseifthedevicedoesnotstretchtheLOWperiodoftheI2Cx_SCLsignal.
IfsuchadevicedoesstretchtheLOWperiodoftheI2Cx_SCLsignal,itmustoutputthenextdatabittotheI2Cx_SDAlinemax_rise_time(IC9)+data_setup_time(IC7)=1000+250=1250ns(accordingtotheStandard-modeI2C-busspecification)beforetheI2Cx_SCLlineisreleased.
—nsIC9BusfreetimebetweenaSTOPandSTARTcondition4.
7—1.
3—sIC10RisetimeofbothI2Cx_SDAandI2Cx_SCLsignals—100020+0.
1Cb44Cb=totalcapacitanceofonebuslineinpF.
300nsIC11FalltimeofbothI2Cx_SDAandI2Cx_SCLsignals—30020+0.
1Cb4300nsIC12Capacitiveloadforeachbusline(Cb)—400—400pFIC10IC11IC9IC2IC8IC4IC7IC3IC6IC10IC5IC11STARTSTOPSTARTSTARTI2Cx_SDAI2Cx_SCLIC1Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors964.
10.
6LCDcontroller(LCDIF)timingparametersFigure60showstheLCDIFtimingandTableyyliststhetimingparameters.
Figure60.
LCDtiming4.
10.
7ParallelCMOSsensorinterface(CSI)timingparameters4.
10.
7.
1GatedclockmodetimingFigure61andFigure62showsthegatedclockmodetimingsforCSI,andTable74describesthetimingparameters(P1–P7)showninthefigures.
Aframestartswitharising/fallingedgeonCSI_VSYNCTable73.
LCDtimingparametersIDParameterSymbolMinMaxUnitL1LCDpixelclockfrequencytCLK(LCD)-150MHzL2LCDpixelclockhigh(fallingedgecapture)tCLKH(LCD)3-nsL3LCDpixelclocklow(risingedgecapture)tCLKL(LCD)3-nsL4LCDpixelclockhightodatavalid(fallingedgecapture)td(CLKH-DV)-11nsL5LCDpixelclocklowtodatavalid(risingedgecapture)td(CLKL-DV)-11nsL6LCDpixelclockhightocontrolsignalsvalid(fallingedgecapture)td(CLKH-CTRLV)-11nsL7LCDpixelclocklowtocontrolsignalsvalid(risingedgecapture)td(CLKL-CTRLV)-11nsElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors97(VSYNC),thenCSI_HSYNC(HSYNC)isassertedandholdsfortheentireline.
Thepixelclock,CSI_PIXCLK(PIXCLK),isvalidaslongasHSYNCisasserted.
Figure61.
CSIGatedClockMode—SensorDataatFallingEdge,LatchDataatRisingEdgeFigure62.
CSIGatedClockMode—SensorDataatRisingEdge,LatchDataatFallingEdgeTable74.
CSIGatedClockModeTimingParametersIDParameterSymbolMin.
Max.
UnitsP1CSI_VSYNCtoCSI_HSYNCtimetV2H33.
5—nsP2CSI_HSYNCsetuptimetHsu1—nsP3CSIDATAsetuptimetDsu1—nsCSI_PIXCLKCSI_VSYNCCSI_DATA[15:00]P5P1P3P4CSI_HSYNCP2P6P7CSI_PIXCLKCSI_VSYNCCSI_DATA[15:00]P6P1P3P4CSI_HSYNCP2P5P7Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors984.
10.
7.
2UngatedclockmodetimingFigure63showstheungatedclockmodetimingsofCSI,andTable75describesthetimingparameters(P1–P6)thatareshowninthefigure.
InungatedmodetheCSI_VSYNCandCSI_PIXCLKsignalsareused,andtheCSI_HSYNCsignalisignored.
Figure63.
CSIUngatedClockMode—SensorDataatFallingEdge,LatchDataatRisingEdgeTheCSIenablesthechiptoconnectdirectlytoexternalCMOSimagesensors,whichareclassifiedasdumborsmartasfollows:Dumbsensorsonlysupporttraditionalsensortiming(verticalsync(VSYNC)andhorizontalsync(HSYNC))andoutput-onlyBayerandstatisticsdata.
SmartsensorssupportCCIR656videodecoderformatsandperformadditionalprocessingoftheimage(forexample,imagecompression,imagepre-filtering,andvariousdataoutputformats).
P4CSIDATAholdtimetDh1—nsP5CSIpixelclockhightimetCLKh3.
75—nsP6CSIpixelclocklowtimetCLKl3.
75—nsP7CSIpixelclockfrequencyfCLK—148.
5MHzTable75.
CSIUngatedClockModeTimingParametersIDParameterSymbolMin.
Max.
UnitsP1CSI_VSYNCtopixelclocktimetVSYNC33.
5—nsP2CSIDATAsetuptimetDsu1—nsP3CSIDATAholdtimetDh1—nsP4CSIpixelclockhightimetCLKh3.
75—nsP5CSIpixelclocklowtimetCLKl3.
75—nsP6CSIpixelclockfrequencyfCLK—148.
5MHzTable74.
CSIGatedClockModeTimingParameters(continued)IDParameterSymbolMin.
Max.
UnitsCSI_PIXCLKCSI_VSYNCCSI_DATA[15:00]P4P1P2P3P5P6Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors99ThefollowingsubsectionsdescribetheCSItimingingatedandungatedclockmodes.
4.
10.
8MIPIPHYtimingparameters4.
10.
8.
1ThissectiondescribesMIPIPHYelectricalspecifications.
ElectricalandTimingInformationTable76.
ElectricalandTimingInformationSymbolParametersTestConditionsMinTypMaxUnitInputDCSpecifications-ApplytoDSI_CLK_P/DSI_CLK_NandDSI_DATA_P/DSI_DATA_NinputsVIInputsignalvoltagerangeTransientvoltagerangeislimitedfrom-300mVto1600mV-50—1350mVVLEAKInputleakagecurrentVGNDSH(min)=VI=VGNDSH(max)+VOH(absmax)LanemoduleinLPReceiveMode-10—10mAVGNDSHGroundShift—-50—50mVVOH(absmax)Maximumtransientoutputvoltagelevel———1.
45Vtvoh(absmax)MaximumtransienttimeaboveVOH(absmax)———20nsHSLineDriversDCSpecifications|VOD|HSTransmitDifferentialoutputvoltagemagnitude80Ω@7,67,67,+7,+463,[B6&/.
463,[B'$7$>@463,[B'46Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors107NOTEForinternalsampling,thetimingvaluesassumesusingsamplepoint0,thatisQuadSPIx_SMPR[SDRSMP]=0.
ForloopbackDQSsampling,thedatastrobeisoutputtotheDQSpadtogetherwiththeserialclock.
ThedatastrobeisloopedbackfromDQSpadandusedtosampleinputdata.
Figure73.
QuadSPIOutput/WriteTiming(SDRmode)NOTETcssandTcshareconfiguredbytheQuadSPIx_FLSHCRregister,thedefaultvalueof3areshownonthetiming.
Pleaserefertothei.
MX6SoloXReferenceManual(IMX6ULLRM)formoredetails.
Table80.
QuadSPIInput/ReadTiming(SDRmodewithloopbackDQSsampling)SymbolParameterValueUnitMinMaxTISSetuptimeforincomingdata2—nsTIHHoldtimerequirementforincomingdata1—nsTable81.
QuadSPIOutput/WriteTiming(SDRmode)SymbolParameterValueUnitMinMaxTDVOOutputdatavalidtime—2.
5nsTDHOOutputdataholdtime-0.
5—nsTCKSCKclockperiod10—nsTCSSChipselectoutputsetuptime3—SCKcycle(s)TCSHChipselectoutputholdtime3—SCKcycle(s)7&667&.
7&6+7'927'+27'927'+2463,[B6&/.
463,[B&6463,[B6,2Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1084.
10.
11.
2DDRModeFigure74.
QuadSPIInput/ReadTiming(DDRmodewithinternalsampling)Figure75.
QuadSPIInput/ReadTiming(DDRmodewithloopbackDQSsampling)NOTEForinternalsampling,thetimingvaluesassumesusingsamplepoint0,thatisQuadSPIx_SMPR[SDRSMP]=0.
Table82.
QuadSPIInput/ReadTiming(DDRmodewithinternalsampling)SymbolParameterValueUnitMinMaxTISSetuptimeforincomingdata8.
67—nsTIHHoldtimerequirementforincomingdata0—nsTable83.
QuadSPIInput/ReadTiming(DDRmodewithloopbackDQSsampling)SymbolParameterValueUnitMinMaxTISSetuptimeforincomingdata2—nsTIHHoldtimerequirementforincomingdata1—ns7,67,+7,67,+463,[B6&/.
463,[B'$7$>@7,67,+7,67,+463,[B6&/.
463,[B'$7$>@463,[B'46Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors109ForloopbackDQSsampling,thedatastrobeisoutputtotheDQSpadtogetherwiththeserialclock.
ThedatastrobeisloopedbackfromDQSpadandusedtosampleinputdata.
Figure76.
QuadSPIOutput/WriteTiming(DDRmode)NOTETcssandTcshareconfiguredbytheQuadSPIx_FLSHCRregister,thedefaultvalueof3areshownonthetiming.
Seethei.
MX7DualReferenceManual(IMX7DRM)formoredetails.
4.
10.
12SAI/I2SswitchingspecificationsThissectionprovidestheACtimingsfortheSAIinmaster(clocksdriven)andslave(clocksinput)modes.
Alltimingsaregivenfornoninvertedserialclockpolarity(SAI_TCR[TSCKP]=0,SAI_RCR[RSCKP]=0)andnoninvertedframesync(SAI_TCR[TFSI]=0,SAI_RCR[RFSI]=0).
Ifthepolarityoftheclockand/ortheframesynchavebeeninverted,allthetimingsremainvalidbyinvertingtheclocksignal(SAI_BCLK)and/ortheframesync(SAI_FS)showninthefiguresbelow.
Table84.
QuadSPIOutput/WriteTiming(DDRmode)SymbolParameterValueUnitMinMaxTDVOOutputdatavalidtime—(0.
25xTSCLK)+2.
5nsTDHOOutputdataholdtime(0.
25xTSCLK)-0.
5—nsTCKSCKclockperiod20—nsTCSSChipselectoutputsetuptime3—SCKcycle(s)TCSHChipselectoutputholdtime3—SCKcycle(s)Table85.
MastermodeSAItimingNumCharacteristicMinMaxUnitS1SAI_MCLKcycletime20—nsS2SAI_MCLKpulsewidthhigh/low40%60%MCLKperiodS3SAI_BCLKcycletime40—nsS4SAI_BCLKpulsewidthhigh/low40%60%BCLKperiod7&667&.
7'927'+27'927'+27&6+463,[B6&/.
463,[B&6463,[B6,2Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors110Figure77.
SAItiming—mastermodesS5SAI_BCLKtoSAI_FSoutputvalid—15nsS6SAI_BCLKtoSAI_FSoutputinvalid0—nsS7SAI_BCLKtoSAI_TXDvalid—15nsS8SAI_BCLKtoSAI_TXDinvalid0—nsS9SAI_RXD/SAI_FSinputsetupbeforeSAI_BCLK15—nsS10SAI_RXD/SAI_FSinputholdafterSAI_BCLK0—nsTable86.
MastermodeSAItimingNumCharacteristicMinMaxUnitS11SAI_BCLKcycletime(input)40—nsS12SAI_BCLKpulsewidthhigh/low(input)40%60%BCLKperiodS13SAI_FSinputsetupbeforeSAI_BCLK10—nsS14SAI_FAinputholdafterSAI_BCLK2—nsS15SAI_BCLKtoSAI_TXD/SAI_FSoutputvalid—20nsS16SAI_BCLKtoSAI_TXD/SAI_FSoutputinvalid0—nsS17SAI_RXDsetupbeforeSAI_BCLK10—nsS18SAI_RXDholdafterSAI_BCLK2—nsTable85.
MastermodeSAItiming(continued)NumCharacteristicMinMaxUnitElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors111Figure78.
SAItiming—slavemodes4.
10.
13SCANJTAGcontroller(SJC)timingparametersFigure79depictstheSJCtestclockinputtiming.
Figure80depictstheSJCboundaryscantiming.
Figure81depictstheSJCtestaccessport.
SignalparametersarelistedinTable87.
Figure79.
TestclockinputtimingdiagramJTAG_TCK(Input)VMVMVIHVILSJ1SJ2SJ2SJ3SJ3Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors112Figure80.
Boundaryscan(JTAG)timingdiagramJTAG_TCK(Input)DataInputsDataOutputsDataOutputsDataOutputsVIHVILInputDataValidOutputDataValidOutputDataValidSJ4SJ5SJ6SJ7SJ6Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors113Figure81.
TestaccessporttimingdiagramFigure82.
JTAG_TRST_BtimingdiagramTable87.
JTAGtimingIDParameter1,2AllFrequenciesUnitMinMaxSJ0JTAG_TCKfrequencyofoperation1/(3TDC)10.
00122MHzSJ1JTAG_TCKcycletimeinCrystalmode45—nsSJ2JTAG_TCKclockpulsewidthmeasuredatVM222.
5—nsSJ3JTAG_TCKriseandfalltimes—3nsSJ4Boundaryscaninputdataset-uptime5—nsSJ5Boundaryscaninputdataholdtime24—nsSJ6JTAG_TCKlowtooutputdatavalid—40nsSJ7JTAG_TCKlowtooutputhighimpedance—40nsSJ8JTAG_TMS,JTAG_TDIdataset-uptime5—nsJTAG_TCK(Input)JTAG_TDI(Input)JTAG_TDO(Output)JTAG_TDO(Output)JTAG_TDO(Output)VIHVILInputDataValidOutputDataValidOutputDataValidJTAG_TMSSJ8SJ9SJ10SJ11SJ10JTAG_TCK(Input)JTAG_TRST_B(Input)SJ13SJ12Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1144.
10.
14UARTI/Oconfigurationandtimingparameters4.
10.
14.
1UARTRS-232I/OconfigurationindifferentmodesThei.
MX7DualUARTinterfacescanservebothasDTEorDCEdevice.
ThiscanbeconfiguredbytheDCEDTEcontrolbit(default0—DCEmode).
Table88showstheUARTI/Oconfigurationbasedontheenabledmode.
4.
10.
14.
2UARTRS-232SerialmodetimingThissectiondescribestheelectricalinformationoftheUARTmoduleintheRS-232mode.
SJ9JTAG_TMS,JTAG_TDIdataholdtime25—nsSJ10JTAG_TCKlowtoJTAG_TDOdatavalid—44nsSJ11JTAG_TCKlowtoJTAG_TDOhighimpedance—44nsSJ12JTAG_TRST_Basserttime100—nsSJ13JTAG_TRST_Bset-uptimetoJTAG_TCKlow40—ns1TDC=targetfrequencyofSJC2VM=mid-pointvoltageTable88.
UARTI/Oconfigurationvs.
modePortDTEModeDCEModeDirectionDescriptionDirectionDescriptionUARTx_RTS_BOutputUARTx_RTS_BfromDTEtoDCEInputUARTx_RTS_BfromDTEtoDCEUARTx_CTS_BInputUARTx_CTS_BfromDCEtoDTEOutputUARTx_CTS_BfromDCEtoDTEUARTx_TX_DATAInputSerialdatafromDCEtoDTEOutputSerialdatafromDCEtoDTEUARTx_RX_DATAOutputSerialdatafromDTEtoDCEInputSerialdatafromDTEtoDCETable87.
JTAGtiming(continued)IDParameter1,2AllFrequenciesUnitMinMaxElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1154.
10.
14.
2.
1UARTtransmitterFigure83depictsthetransmittimingofUARTintheRS-232Serialmode,with8databit/1stopbitformat.
Table89liststheUARTRS-232Serialmodetransmittimingcharacteristics.
Figure83.
UARTRS-232Serialmodetransmittimingdiagram4.
10.
14.
2.
2UARTreceiverFigure84depictstheRS-232Serialmodereceivetimingwith8databit/1stopbitformat.
Table90listsSerialmodereceivetimingcharacteristics.
Figure84.
UARTRS-232Serialmodereceivetimingdiagram4.
10.
15USBHSICtimingThissectiondescribestheelectricalinformationoftheUSBHSICport.
Table89.
RS-232SerialmodetransmittimingparametersIDParameterSymbolMinMaxUnitUA1TransmitBitTimetTbit1/Fbaud_rate1-Tref_clk21Fbaud_rate:Baudratefrequency.
ThemaximumbaudratetheUARTcansupportis(ipg_perclkfrequency)/16.
2Tref_clk:TheperiodofUARTreferenceclockref_clk(ipg_perclkafterRFDIVdivider).
1/Fbaud_rate+Tref_clk—Table90.
RS-232SerialmodereceivetimingparametersIDParameterSymbolMinMaxUnitUA2ReceiveBitTime11TheUARTreceivercantolerate1/(16xFbaud_rate)toleranceineachbit.
Butaccumulationtoleranceinoneframemustnotexceed3/(16xFbaud_rate).
tRbit1/Fbaud_rate2-1/(16xFbaud_rate)2Fbaud_rate:Baudratefrequency.
ThemaximumbaudratetheUARTcansupportis(ipg_perclkfrequency)/16.
1/Fbaud_rate+1/(16xFbaud_rate)—StartBitBit1Bit2Bit0Bit4Bit5Bit6Bit7UARTx_TX_DATA(output)Bit3STOPBITNextStartBitPossibleParityBitParBitUA1UA1UA1UA1Bit1Bit2Bit0Bit4Bit5Bit6Bit7UARTx_RX_DATA(output)Bit3StartBitSTOPBITNextStartBitPossibleParityBitParBitUA2UA2UA2UA2Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors116NOTEHSICisDDRsignal,followingtimingspecisforbothrisingandfallingedge.
4.
10.
15.
1TransmittimingFigure85.
USBHSICtransmitwaveform4.
10.
15.
2ReceivetimingFigure86.
USBHSICreceivewaveformTable91.
USBHSICtransmitparametersNameParameterMinMaxUnitCommentTstrobestrobeperiod4.
1654.
169nsTodelaydataoutputdelaytime5501350psMeasuredat50%pointTslewstrobe/datarising/fallingtime0.
72V/nsAveragedfrom30%–70%pointsTable92.
USBHSICreceiveparameters11Thetimingsinthetableareguaranteedwhen:—ACI/Ovoltageisbetween0.
9xto1xoftheI/Osupply—DDR_SELconfigurationbitsoftheI/Oaresetto(10)bNameParameterMinMaxUnitCommentTstrobestrobeperiod4.
1654.
169nsTholddataholdtime300psMeasuredat50%pointTsetupdatasetuptime365psMeasuredat50%pointTslewstrobe/datarising/fallingtime0.
72V/nsAveragedfrom30%–70%pointsUSB_H_STROBEUSB_H_DATATodelayTstrobeTodelayUSB_H_STROBEUSB_H_DATATholdTstrobeTsetupElectricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1174.
10.
16USBPHYparametersThissectiondescribestheUSB-OTGPHYparameters.
TheUSBPHYmeetstheelectricalcompliancerequirementsdefinedintheUniversalSerialBusRevision2.
0OTG,USBHostwiththeamendmentsbelow(On-The-GoandEmbeddedHostSupplementtotheUSBRevision2.
0SpecificationisnotapplicabletoHostport):USBENGINEERINGCHANGENOTICE—Title:5VShortCircuitWithstandRequirementChange—Appliesto:UniversalSerialBusSpecification,Revision2.
0ErrataforUSBRevision2.
0April27,2000asof12/7/2000USBENGINEERINGCHANGENOTICE—Title:Pull-up/Pull-downresistors—Appliesto:UniversalSerialBusSpecification,Revision2.
0USBENGINEERINGCHANGENOTICE—Title:SuspendCurrentLimitChanges—Appliesto:UniversalSerialBusSpecification,Revision2.
0USBENGINEERINGCHANGENOTICE—Title:USB2.
0PhaseLockedSOFs—Appliesto:UniversalSerialBusSpecification,Revision2.
0On-The-GoandEmbeddedHostSupplementtotheUSBRevision2.
0Specification—Revision2.
0,version1.
1a,July27,2010BatteryChargingSpecification(availablefromUSB-IF)—Revision1.
2,December7,20104.
10.
16.
1USB_OTG*_REXTreferenceresistorconnectionThebiasgenerationandimpedancecalibrationprocessfortheUSBOTGPHYsrequiresconnectionofreferenceresistors200Ω1%precisiononeachofUSB_OTG1_REXTandUSB_OTG2_REXTpadstoground.
4.
10.
16.
2USB_OTG_CHD_BUSBbatterychargerdetectionexternalpullupresistorconnectionTheusageandexternalresistorconnectionfortheUSB_OTG_CHD_BpinaredescribedinTable3,Table7,andSection4.
7.
3,"USBbatterychargerdetectiondriverimpedance.
"Electricalcharacteristicsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1184.
1112-BitA/Dconverter(ADC)Table93.
Recommendedoperatingconditionsfor12-bitADCCharacteristicsSymbolMinTypMaxUnitSupplyVoltageAVDD181.
71.
81.
9VVDDA100.
9511.
05VOperatingTempTJ–25—105CAnalogInputChannel———16ChannelAnalogInputRange11DO=111111111111@AIN=AVDD18&DO=000000000000@AIN=AVSS18(Inputfull-scalevoltage=AVDD18)ADCx_INxAGND—VREFVMainClockFrequencyFCLK300K—6MHzStartofconversionclkfrequency(FCLK/3)FSOC50K—1MHzExternalInputResistanceofADC22RIEXT=OutputresistanceoftheADCdriver=Outputresistanceofsignalgenerator+SeriesparasiticresistancebetweensignalsourceandADCinput(forexample,PCBandbondingwireresistanceandESDprotectionresistance)RIEXT—50250ΩTable94.
DCElectricalcharacteristicsSpecificationSymbolMinTypMaxUnitConditionsResolution——1212Bits—DifferentialNon-LinearityDNL—±2.
0±2.
0LSBPD=LowFCLK=6MHzFSOC=1MHzFAIN=10kHzRampwaveIntegralNon-LinearityINL—±6.
0±6.
0LSBTopOffsetVoltageEOT—±10±100LSBBottomOffsetVoltageEOB—±11±100LSBTable95.
ACElectricalcharacteristicsSpecificationSymbolMinTypMaxUnitMainClockDutyRatio—454555%AnalogInputFrequencyCH#15-0FAINDC50k100KHzNormalOperationCurrentConsumption1VDDA_ADCx_1P82—0.
531.
90mAVDDA_1P0_CAP2—0.
020.
10mABootmodeconfigurationi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1195BootmodeconfigurationThissectionprovidesinformationonBootmodeconfigurationpinsallocationandbootdevicesinterfacesallocation.
5.
1BootmodeconfigurationpinsTable96providesbootoptions,functionality,fusevalues,andassociatedpins.
Severalinputpinsarealsosampledatresetandcanbeusedtooverridefusevalues,dependingonthevalueofBT_FUSE_SELfuse.
ThebootoptionpinsareineffectwhenBT_FUSE_SELfuseis'0'(cleared,whichisthecaseforanunblownfuse).
FordetailedBootmodeoptionsconfiguredbytheBootmodepins,seethe"SystemBoot,Fusemap,andeFuse"chapterinthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM).
PowerDownCurrent2IPD3—3.
0300μΑSignaltoNoiseandDistortionRatioSNDR5460—dB1NormaloperationcurrentconsumptionincludesonlythecurrentfromtheADCcore.
Itdoesnotincludestaticcurrentfromthepowerpads.
2Power-downcurrentincludesonlythecurrentfromtheADCcore.
Itdoesnotincludestaticcurrentfromthepowerpads.
3IOPandIPDaremeasurableonlyontheADCcore'stestchips.
BecauseAVDD10issharedwithinternallogicpower,IOPandIPDinthetestplanonlymeasurecurrentconsumption@AVDD18,VREF.
Table96.
FusesandassociatedpinsusedforbootPinDirectionatReseteFusenameStateduringreset(POR_Basserted)Stateafterreset(POR_Bdeasserted)DetailsBOOT_MODE0InputN/AHi-ZHi-ZBootmodeselectionBOOT_MODE1InputN/AHi-ZHi-ZBootmodeselectionTable95.
ACElectricalcharacteristics(continued)SpecificationSymbolMinTypMaxUnitBootmodeconfigurationi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1205.
2BootdeviceinterfaceallocationTable97liststheinterfacesthatcanbeusedbythebootprocessinaccordancewiththespecificBootmodeconfiguration.
Thetablealsodescribestheinterface'sspecificmodesandIOMUXCallocation,whichareconfiguredduringbootwhenappropriate.
LCD1_DATA00InputBT_CFG[0]100KPullDownKeeperBootoptions,pinvalueoverridesfusesettingsforBT_FUSE_SEL='0'.
Signalconfigurationasfuseoverrideinputatpowerup.
ThesearespecialI/Olinesthatcontrolthebootconfigurationduringproductdevelopment.
Inproduction,thebootconfigurationcanbecontrolledbyfuses.
LCD1_DATA01InputBT_CFG[1]100KPullDownKeeperLCD1_DATA02InputBT_CFG[2]100KPullDownKeeperLCD1_DATA03InputBT_CFG[3]100KPullDownKeeperLCD1_DATA04InputBT_CFG[4]100KPullDownKeeperLCD1_DATA05InputBT_CFG[5]100KPullDownKeeperLCD1_DATA06InputBT_CFG[6]100KPullDownKeeperLCD1_DATA07InputBT_CFG[7]100KPullDownKeeperLCD1_DATA08InputBT_CFG[8]100KPullDownKeeperLCD1_DATA09InputBT_CFG[9]100KPullDownKeeperLCD1_DATA10InputBT_CFG[10]100KPullDownKeeperLCD1_DATA11InputBT_CFG[11]100KPullDownKeeperLCD1_DATA12InputBT_CFG[12]100KPullDownKeeperLCD1_DATA13InputBT_CFG[13]100KPullDownKeeperLCD1_DATA14InputBT_CFG[14]100KPullDownKeeperLCD1_DATA15InputBT_CFG[15]100KPullDownKeeperLCD1_DATA16InputBT_CFG[16]100KPullDownKeeperLCD1_DATA17InputBT_CFG[17]100KPullDownKeeperLCD1_DATA18InputBT_CFG[18]100KPullDownKeeperLCD1_DATA19InputBT_CFG[19]100KPullDownKeeperTable97.
InterfaceallocationduringbootInterfaceIPInstanceAllocatedPadsDuringBootCommentQSPIQSPIEPDC_D0,EPDC_D1,EPDC_D2,EPDC_D3,EPDC_D4,EPDC_D5,EPDC_D6,EPDC_D7,EPDC_D8,EPDC_D9,EPDC_D10,EPDC_D11,EPDC_D12,EPDC_D13,EPDC_D14,EPDC_D15SPIECSPI-1ECSPI1_SCLK,ECSPI1_MOSI,ECSPI1_MISO,ECSPI1_SS0,UART1_RXD,UART1_TXD,UART2_RXDThechip-selectpinuseddependsonthefuse"CSselect(SPIonly)"Table96.
Fusesandassociatedpinsusedforboot(continued)PinDirectionatReseteFusenameStateduringreset(POR_Basserted)Stateafterreset(POR_Bdeasserted)DetailsBootmodeconfigurationi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors121SPIECSPI-2ECSPI2_SCLK,ECSPI2_MOSI,ECSPI2_MISO,ECSPI2_SS0,ENET1_RX_CTL,ENET1_RXC,ENET1_TD0Thechip-selectpinuseddependsonthefuse"CSselect(SPIonly)"SPIECSPI-3SAI2_TXFS,SAI2_TXC,SAI2_RXD,SAI2_TXD,SD1_DATA3,SD2_CD_B,SD2_WPThechip-selectpinuseddependsonthefuse"CSselect(SPIonly)"SPIECSPI-4SD1_CD_B,SD1_WP,SD1_RESET_B,SD1_CLK,SD1_CMD,SD1_DATA0,SD1_DATA1Thechip-selectpinuseddependsonthefuse"CSselect(SPIonly)"EIMEIMEPDC_SDCE2,EPDC_SDCE3,EPDC_GDCLK,EPDC_GDOE,EPDC_GDRL,EPDC_GDSP,EPDC_BDR0,LCD_DAT20,LCD_DAT21,LCD_DAT22,LCD_DAT23,EPDC_D8,EPDC_D9,EPDC_D10,EPDC_D12,EPDC_D14,EPDC_PWRSTATUsedforNOR,OneNANDbootOnlyCS0issupported.
Allocatedpadsmaydifferdependingonmuxmode.
Seethe"SystemBoot,Fusemap,andeFuse"chapterofthei.
MX7DualApplicationProcessorReferenceManual(IMX7DRM)fordetails.
NANDFlashGPMISD3_CLK,SD3_CMD,SD3_DATA0,SD3_DATA1,SD3_DATA2,SD3_DATA3,SD3_DATA4,SD3_DATA5,SD3_DATA6,SD3_DATA7,SD3_STROBE,SD3_RESET_B,SAI1_TXC,SAI1_TXFS,SAI1_TXD8bitOnlyCS0issupportedSD/MMCUSDHC-1SD1_CD_B,SD1_RESET_B,SD1_CLK,SD1_CMD,SD1_DATA0,SD1_DATA1,SD1_DATA2,SD1_DATA3,GPIO1_IO08,ECSPI2_SCLK,ECSPI2_MOSI,ECSPI2_MISO,ECSPI2_SS01,4,or8bitSD/MMCUSDHC-2SD2_RESET_B,SD2_CLK,SD2_CMD,SD2_DATA0,SD2_DATA1,SD2_DATA2,SD2_DATA3,GPIO1_IO12,ECSPI1_SCLK,ECSPI1_MOSI,ECSPI1_MISO,ECSPI1_SS01,4,or8bitSD/MMCUSDHC-3SD3_CLK,SD3_CMD,SD3_DAT0,SD3_DAT1,SD3_DAT2,SD3_DAT3,SD3_DAT4,SD3_DAT5,SD3_DAT6,SD3_DAT7,SD3_RESET_B1,4,or8bitUSBUSB-OTGPHY—Table97.
Interfaceallocationduringboot(continued)InterfaceIPInstanceAllocatedPadsDuringBootCommentPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1226PackageinformationandcontactassignmentsThissectionincludesthecontactassignmentinformationandmechanicalpackagedrawing.
6.
112x12mmpackageinformation6.
1.
1Case1997-01,12x12,0.
4mmpitch,ballmatrixThefollowingfigureshowsthetop,bottom,andsideviewsofthe12*12mmBGApackage.
Figure87.
12x12mmBGA,CasexPackageTop,Bottom,andSideViewsPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1236.
1.
212x12mmsuppliescontactassignmentsandfunctionalcontactassignmentsTable98showssuppliescontactassignmentsforthe12x12mmpackage.
Table98.
i.
MX7Dual12x12mmsuppliescontactassignmentsRailBallCommentsDRAM_VREFT20DDRvoltagereferenceinput.
Connecttoavoltagesourcethatis50%ofNVCC_DRAMDRAM_ZQPADY18DDRoutputbufferdrivercalibrationreferencevoltageinput.
ConnectDRAM_ZQPADtoanexternal240Ω1%resistortoVssFUSE_FSOURCEV09GNDA01,A28,B05,B23,B26,C03,C05,C07,C10,C13,C14,C15,C23,C24,C25,C26,D08,D12,D17,D21,E03,E05,E24,E26,F08,F10,F12,F14,F15,F17,F21,H04,H06,H23,H25,L13,L16,M04,M06,M23,M25,N11,N18,T11,T18,U04,U06,U23,U25,V13,V16,W03,W06,AA04,AA06,AA23,AA25,AC08,AC10,AC12,AC14,AC15,AC17,AC21,AD03,AD05,AD06,AD24,AD26,AE06,AE07,AE08,AE09,AE17,AE21,AF03,AF05,AF08,AF09,AF10,AF11,AF13,AF14,AF15,AF24,AF26,AG10,AH01,AH28GPANAIOAF02Testsignal.
Shouldbeleftunconnected.
MIPI_VREG_0P4VB19NVCC_DRAMV27,V28,W21,W23,W26,Y20,AA19,AC19,AF17,AF18,AF19,AG18,AH18SupplyinputfortheDDRI/OinterfaceNVCC_DRAM_CKEV20NVCC_ENET1J18SupplyinputfortheENETinterfacesNVCC_EPDC1P20SupplyforEPDCNVCC_EPDC2N20SupplyforEPDCNVCC_GPIO1Y09SupplyforGPIO1NVCC_GPIO2Y11SupplyforGPIO2NVCC_I2CR09SupplyforI2CNVCC_LCDL20SupplyforLCDNVCC_SAIJ13SupplyforSAINVCC_SD1J11SupplyforSDcardNVCC_SD2L09SupplyforSDcardNVCC_SD3N09SupplyforSDcardNVCC_SPIP09SupplyforSPIPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors124NVCC_UARTT09SupplyforUARTPCIE_VPAB13SupplyinputforthePCIePHYPCIE_VPHY15SupplyinputforthePCIePHYPVCC_ENET_CAPG16SecondarysupplyforENET.
RequiresexternalcapacitorPVCC_EPDC_LCD_CAPR20SecondarysupplyforEPDC,LCD.
RequiresexternalcapacitorPVCC_GPIO_CAPAB11SecondarysupplyforGPIO.
RequiresexternalcapacitorPVCC_I2C_SPI_UART_CAPW08SecondarysupplyforI2C,SPI,UART.
RequiresexternalcapacitorPVCC_SAI_SD_CAPJ14SecondarysupplyforSAI,SD.
RequiresexternalcapacitorUSB_OTG1_VBUSC09VBUSinputforUSB_OTG1USB_OTG2_VBUSC11VBUSinputforUSB_OTG2VDD_1P2_CAPAA10SupplyforHSICVDD_ARMA20,B20,C16,C17,C18,C19,C20,C21,C22,F19,H19,J20,K21,K23,K26,L27,L28SupplyvoltageforArmVDD_LPSR_1P0_CAPAG06SecondarysupplyforLPSR.
RequiresexternalcapacitorVDD_LPSR_INAG05SupplytoLPSRVDD_MIPI_1P0J16SupplyforMIPIVDD_SNVS_1P8_CAPAG07SecondarysupplyforSNVS.
RequiresexternalcapacitorVDD_SNVS_INY13SupplyforSNVSVDD_SOCH10,J09,K03,K06,K08,L01,L02,L11,L18,N13,N16,P03,P06,P23,P26,R26,T13,T16,V11,V18,R03,R06,R23SupplyforSOCVDD_TEMPSENSOR_1P8AH05SupplyfortempsensorVDD_USB_H_1P2C12,G13SupplyinputfortheUSBHSICinterfaceVDD_USB_OTG1_1P0_CAPE09SecondarysupplyforOTG1.
RequiresexternalcapacitorVDD_USB_OTG1_3P3_IND09SecondarysupplyforOTG1.
RequiresexternalcapacitorVDD_USB_OTG2_1P0_CAPF09SecondarysupplyforOTG2.
RequiresexternalcapacitorVDD_USB_OTG2_3P3_IND11SecondarysupplyforOTG2.
RequiresexternalcapacitorTable98.
i.
MX7Dual12x12mmsuppliescontactassignments(continued)RailBallCommentsPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors125Table99showsanalpha-sortedlistoffunctionalcontactassignmentsforthe12x12mmpackage.
VDD_XTAL_1P8AH02VDDA_1P0_CAPAH07Secondarysupplyfor1.
0V.
RequiresexternalcapacitorVDDA_1P8_INAF04,AG03,AG04Supplyfor1.
8VVDDA_ADC1_1P8AH04SupplyforADCVDDA_MIPI_1P8J15SupplyforMIPIVDDA_PHY_1P8Y14VDDD_1P0_CAPAC13,AE12,AF12Secondarysupplyfor1.
0V.
RequiresexternalcapacitorTable99.
i.
MX7Dual12x12mmfunctionalcontactassignmentsBallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUAB07ADC1_IN0ADC1_VDDA_1P8ADC1_IN0AC07ADC1_IN1ADC1_VDDA_1P8ADC1_IN1AD07ADC1_IN2ADC1_VDDA_1P8ADC1_IN2AD09ADC1_IN3ADC1_VDDA_1P8ADC1_IN3Y01BOOT_MODE0NVCC_GPIO1GPIOALT0BOOT_MODE0100KPDY02BOOT_MODE1NVCC_GPIO1GPIOALT0BOOT_MODE1100KPDAE04CCM_CLK1_NVDDA_1P8CCM_CLK1_NAE03CCM_CLK1_PVDDA_1P8CCM_CLK1_PAE02CCM_CLK2VDDA_1P8CCM_CLK2AC24DRAM_ADDR00NVCC_DRAMDDRDRAM_ADDR00AC25DRAM_ADDR01NVCC_DRAMDDRDRAM_ADDR01AC26DRAM_ADDR02NVCC_DRAMDDRDRAM_ADDR02AB25DRAM_ADDR03NVCC_DRAMDDRDRAM_ADDR03AB24DRAM_ADDR04NVCC_DRAMDDRDRAM_ADDR04AE23DRAM_ADDR05NVCC_DRAMDDRDRAM_ADDR05AF23DRAM_ADDR06NVCC_DRAMDDRDRAM_ADDR06AE22DRAM_ADDR07NVCC_DRAMDDRDRAM_ADDR07AD22DRAM_ADDR08NVCC_DRAMDDRDRAM_ADDR08AC22DRAM_ADDR09NVCC_DRAMDDRDRAM_ADDR09Table98.
i.
MX7Dual12x12mmsuppliescontactassignments(continued)RailBallCommentsPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors126AD23DRAM_ADDR10NVCC_DRAMDDRDRAM_ADDR10AG27DRAM_ADDR11NVCC_DRAMDDRDRAM_ADDR11AE27DRAM_ADDR12NVCC_DRAMDDRDRAM_ADDR12AG28DRAM_ADDR13NVCC_DRAMDDRDRAM_ADDR13AE20DRAM_ADDR14NVCC_DRAMDDRDRAM_ADDR14AG26DRAM_ADDR15NVCC_DRAMDDRDRAM_ADDR15AG25DRAM_CAS_BNVCC_DRAMDDRDRAM_CAS_BAE26DRAM_CS0_BNVCC_DRAMDDRDRAM_CS0_BAC23DRAM_CS1_BNVCC_DRAMDDRDRAM_CS1_BAH22DRAM_DATA00NVCC_DRAMDDRDRAM_DATA00AG19DRAM_DATA01NVCC_DRAMDDRDRAM_DATA01AG20DRAM_DATA02NVCC_DRAMDDRDRAM_DATA02AF22DRAM_DATA03NVCC_DRAMDDRDRAM_DATA03AF20DRAM_DATA04NVCC_DRAMDDRDRAM_DATA04AG22DRAM_DATA05NVCC_DRAMDDRDRAM_DATA05AF21DRAM_DATA06NVCC_DRAMDDRDRAM_DATA06AH20DRAM_DATA07NVCC_DRAMDDRDRAM_DATA07AC18DRAM_DATA08NVCC_DRAMDDRDRAM_DATA08AB18DRAM_DATA09NVCC_DRAMDDRDRAM_DATA09AD16DRAM_DATA10NVCC_DRAMDDRDRAM_DATA10AC16DRAM_DATA11NVCC_DRAMDDRDRAM_DATA11AD18DRAM_DATA12NVCC_DRAMDDRDRAM_DATA12AE18DRAM_DATA13NVCC_DRAMDDRDRAM_DATA13AB16DRAM_DATA14NVCC_DRAMDDRDRAM_DATA14AE16DRAM_DATA15NVCC_DRAMDDRDRAM_DATA15W27DRAM_DATA16NVCC_DRAMDDRDRAM_DATA16Y27DRAM_DATA17NVCC_DRAMDDRDRAM_DATA17Y26DRAM_DATA18NVCC_DRAMDDRDRAM_DATA18Y28DRAM_DATA19NVCC_DRAMDDRDRAM_DATA19AA26DRAM_DATA20NVCC_DRAMDDRDRAM_DATA20AB26DRAM_DATA21NVCC_DRAMDDRDRAM_DATA21AB27DRAM_DATA22NVCC_DRAMDDRDRAM_DATA22Table99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors127AB28DRAM_DATA23NVCC_DRAMDDRDRAM_DATA23V23DRAM_DATA24NVCC_DRAMDDRDRAM_DATA24V22DRAM_DATA25NVCC_DRAMDDRDRAM_DATA25T23DRAM_DATA26NVCC_DRAMDDRDRAM_DATA26T22DRAM_DATA27NVCC_DRAMDDRDRAM_DATA27V24DRAM_DATA28NVCC_DRAMDDRDRAM_DATA28V25DRAM_DATA29NVCC_DRAMDDRDRAM_DATA29T25DRAM_DATA30NVCC_DRAMDDRDRAM_DATA30T24DRAM_DATA31NVCC_DRAMDDRDRAM_DATA31AH24DRAM_DQM0NVCC_DRAMDDRDRAM_DQM0AD20DRAM_DQM1NVCC_DRAMDDRDRAM_DQM1AD28DRAM_DQM2NVCC_DRAMDDRDRAM_DQM2Y25DRAM_DQM3NVCC_DRAMDDRDRAM_DQM3AF16DRAM_ODT0NVCC_DRAMDDRDRAM_ODT0AH25DRAM_RAS_BNVCC_DRAMDDRDRAM_RAS_BV26DRAM_RESETNVCC_DRAM_CKEDDRDRAM_RESETAE28DRAM_SDBA0NVCC_DRAMDDRDRAM_SDBA0AB22DRAM_SDBA1NVCC_DRAMDDRDRAM_SDBA1AF27DRAM_SDBA2NVCC_DRAMDDRDRAM_SDBA2Y22DRAM_SDCKE0NVCC_DRAM_CKEDDRDRAM_SDCKE0AB23DRAM_SDCKE1NVCC_DRAM_CKEDDRDRAM_SDCKE1AF25DRAM_SDCLK0_NNVCC_DRAMDDRCLKDRAM_SDCLK0_NAE25DRAM_SDCLK0_PNVCC_DRAMDDRCLKDRAM_SDCLK0_PAG23DRAM_SDQS0_NNVCC_DRAMDDRCLKDRAM_SDQS0_NAG24DRAM_SDQS0_PNVCC_DRAMDDRCLKDRAM_SDQS0_PAC20DRAM_SDQS1_NNVCC_DRAMDDRCLKDRAM_SDQS1_NAB20DRAM_SDQS1_PNVCC_DRAMDDRCLKDRAM_SDQS1_PAD27DRAM_SDQS2_NNVCC_DRAMDDRCLKDRAM_SDQS2_NAC27DRAM_SDQS2_PNVCC_DRAMDDRCLKDRAM_SDQS2_PY24DRAM_SDQS3_NNVCC_DRAMDDRCLKDRAM_SDQS3_NY23DRAM_SDQS3_PNVCC_DRAMDDRCLKDRAM_SDQS3_PAH27DRAM_SDWE_BNVCC_DRAMDDRDRAM_SDWE_BTable99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors128M03ECSPI1_MISONVCC_SPIGPIOALT5GPIO4_IO[18]100KPDL03ECSPI1_MOSINVCC_SPIGPIOALT5GPIO4_IO[17]100KPDK02ECSPI1_SCLKNVCC_SPIGPIOALT5GPIO4_IO[16]100KPDN03ECSPI1_SS0NVCC_SPIGPIOALT5GPIO4_IO[19]100KPDP02ECSPI2_MISONVCC_SPIGPIOALT5GPIO4_IO[22]100KPDN02ECSPI2_MOSINVCC_SPIGPIOALT5GPIO4_IO[21]100KPDN01ECSPI2_SCLKNVCC_SPIGPIOALT5GPIO4_IO[20]100KPDR02ECSPI2_SS0NVCC_SPIGPIOALT5GPIO4_IO[23]100KPDG18ENET1_COLNVCC_ENET1GPIOALT5GPIO7_IO[15]100KPDF18ENET1_CRSNVCC_ENET1GPIOALT5GPIO7_IO[14]100KPDF07ENET1_RD0NVCC_ENET1GPIOALT5GPIO7_IO[0]100KPDE07ENET1_RD1NVCC_ENET1GPIOALT5GPIO7_IO[1]100KPDD07ENET1_RD2NVCC_ENET1GPIOALT5GPIO_IO[2]100KPDD16ENET1_RD3NVCC_ENET1GPIOALT5GPIO7_IO[3]100KPDC06ENET1_RX_CLKNVCC_ENET1GPIOALT5GPIO7_IO[13]100KPDE11ENET1_RX_CTLNVCC_ENET1GPIOALT5GPIO7_IO[4]100KPDF11ENET1_RXCNVCC_ENET1GPIOALT5GPIO7_IO[5]100KPDE13ENET1_TD0NVCC_ENET1GPIOALT5GPIO7_IO[6]100KPDD13ENET1_TD1NVCC_ENET1GPIOALT5GPIO_IO[7]100KPDE16ENET1_TD2NVCC_ENET1GPIOALT5GPIO7_IO[8]100KPDF16ENET1_TD3NVCC_ENET1GPIOALT5GPIO7_IO[9]100KPDF13ENET1_TX_CLKNVCC_ENET1GPIOALT5GPIO7_IO[12]100KPDG11ENET1_TX_CTLNVCC_ENET1GPIOALT5GPIO7_IO[10]100KPDG09ENET1_TXCNVCC_ENET1GPIOALT5GPIO7_IO[11]100KPDL23EPDC_BDR0NVCC_EPDC2GPIOALT5GPIO2_IO[28]100KPDL22EPDC_BDR1NVCC_EPDC2GPIOALT5GPIO2_IO[29]100KPDT27EPDC_D00NVCC_EPDC1GPIOALT5GPIO2_IO[0]100KPDU26EPDC_D01NVCC_EPDC1GPIOALT5GPIO2_IO[1]100KPDT26EPDC_D02NVCC_EPDC1GPIOALT5GPIO2_IO[2]100KPDR27EPDC_D03NVCC_EPDC1GPIOALT5GPIO2_IO[3]100KPDN23EPDC_D04NVCC_EPDC1GPIOALT5GPIO2_IO[4]100KPDT28EPDC_D05NVCC_EPDC1GPIOALT5GPIO2_IO[5]100KPDTable99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors129P27EPDC_D06NVCC_EPDC1GPIOALT5GPIO2_IO[6]100KPDN28EPDC_D07NVCC_EPDC1GPIOALT5GPIO2_IO[7]100KPDN27EPDC_D08NVCC_EPDC1GPIOALT5GPIO2_IO[8]100KPDN26EPDC_D09NVCC_EPDC1GPIOALT5GPIO2_IO[9]100KPDN25EPDC_D10NVCC_EPDC1GPIOALT5GPIO2_IO[10]100KPDN24EPDC_D11NVCC_EPDC1GPIOALT5GPIO2_IO[11]100KPDM26EPDC_D12NVCC_EPDC1GPIOALT5GPIO2_IO[12]100KPDL26EPDC_D13NVCC_EPDC1GPIOALT5GPIO2_IO[13]100KPDL25EPDC_D14NVCC_EPDC1GPIOALT5GPIO2_IO[14]100KPDN22EPDC_D15NVCC_EPDC1GPIOALT5GPIO2_IO[15]100KPDJ23EPDC_GDCLKNVCC_EPDC2GPIOALT5GPIO2_IO[24]100KPDJ22EPDC_GDOENVCC_EPDC2GPIOALT5GPIO2_IO[25]100KPDL24EPDC_GDRLNVCC_EPDC2GPIOALT5GPIO2_IO[26]100KPDK27EPDC_GDSPNVCC_EPDC2GPIOALT5GPIO2_IO[27]100KPDJ27EPDC_PWRCOMNVCC_EPDC2GPIOALT5GPIO2_IO[30]100KPDJ26EPDC_PWRSTATNVCC_EPDC2GPIOALT5GPIO2_IO[31]100KPDJ25EPDC_SDCE0NVCC_EPDC2GPIOALT5GPIO2_IO[20]100KPDJ24EPDC_SDCE1NVCC_EPDC2GPIOALT5GPIO2_IO[21]100KPDG22EPDC_SDCE2NVCC_EPDC2GPIOALT5GPIO2_IO[22]100KPDG23EPDC_SDCE3NVCC_EPDC2GPIOALT5GPIO2_IO[23]100KPDG24EPDC_SDCLKNVCC_EPDC2GPIOALT5GPIO2_IO[16]100KPDJ28EPDC_SDLENVCC_EPDC2GPIOALT5GPIO2_IO[17]100KPDG25EPDC_SDOENVCC_EPDC2GPIOALT5GPIO2_IO[18]100KPDF26EPDC_SDSHRNVCC_EPDC2GPIOALT5GPIO2_IO[19]100KPDAF02GPANAIOVDDA_1P8GPIOGPANAIOV04GPIO1_IO00NVCC_GPIO1GPIOALT0GPIO1_IO00100KPUV05GPIO1_IO01NVCC_GPIO1GPIOALT0GPIO1_IO01100KPDY07GPIO1_IO02NVCC_GPIO1GPIOALT0GPIO1_IO02100KPDY06GPIO1_IO03NVCC_GPIO1GPIOALT0GPIO1_IO03100KPDY05GPIO1_IO04NVCC_GPIO1GPIOALT0GPIO1_IO04100KPDY04GPIO1_IO05NVCC_GPIO1GPIOALT0GPIO1_IO05100KPDV06GPIO1_IO06NVCC_GPIO1GPIOALT0GPIO1_IO06100KPDTable99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors130V07GPIO1_IO07NVCC_GPIO1GPIOALT0GPIO1_IO07100KPDAB03GPIO1_IO08NVCC_GPIO2GPIOALT0GPIO1_IO08100KPDAB04GPIO1_IO09NVCC_GPIO2GPIOALT0GPIO1_IO09100KPDAB05GPIO1_IO10NVCC_GPIO2GPIOALT0GPIO1_IO10100KPDAB06GPIO1_IO11NVCC_GPIO2GPIOALT0GPIO1_IO11100KPDAC06GPIO1_IO12NVCC_GPIO2GPIOALT0GPIO1_IO12100KPDAC05GPIO1_IO13NVCC_GPIO2GPIOALT0GPIO1_IO13100KPDAC04GPIO1_IO14NVCC_GPIO2GPIOALT0GPIO1_IO14100KPDAC03GPIO1_IO15NVCC_GPIO2GPIOALT0GPIO1_IO15100KPDN04I2C1_SCLNVCC_I2CGPIOALT5GPIO4_IO[8]100KPDN05I2C1_SDANVCC_I2CGPIOALT5GPIO4_IO[9]100KPDN06I2C2_SCLNVCC_I2CGPIOALT5GPIO4_IO[10]100KPDN07I2C2_SDANVCC_I2CGPIOALT5GPIO4_IO[11]100KPDT06I2C3_SCLNVCC_I2CGPIOALT5GPIO4_IO[12]100KPDT07I2C3_SDANVCC_I2CGPIOALT5GPIO4_IO[13]100KPDT05I2C4_SCLNVCC_I2CGPIOALT5GPIO4_IO[14]100KPDT04I2C4_SDANVCC_I2CGPIOALT5GPIO4_IO[15]100KPDAB01JTAG_MODNVCC_GPIO2GPIOALT0JTAG_MOD100KPUAD01JTAG_TCKNVCC_GPIO2GPIOALT0JTAG_TCK47KPUAC02JTAG_TDINVCC_GPIO2GPIOALT0JTAG_TDI47KPUAE01JTAG_TDONVCC_GPIO2GPIOALT0JTAG_TDO100KPUAD02JTAG_TMSNVCC_GPIO2GPIOALT0JTAG_TMS47KPUAB02JTAG_TRST_BNVCC_GPIO2GPIOALT0JTAG_TRST_B47KPUD20LCD_CLKNVCC_LCDGPIOALT5GPIO3_IO[0]100KPDF22LCD_DATA00NVCC_LCDGPIOALT5GPIO3_IO[5]100KPDF23LCD_DATA01NVCC_LCDGPIOALT5GPIO3_IO[6]100KPDE23LCD_DATA02NVCC_LCDGPIOALT5GPIO3_IO[7]100KPDE22LCD_DATA03NVCC_LCDGPIOALT5GPIO3_IO[8]100KPDD22LCD_DATA04NVCC_LCDGPIOALT5GPIO3_IO[9]100KPDD23LCD_DATA05NVCC_LCDGPIOALT5GPIO3_IO[10]100KPDE18LCD_DATA06NVCC_LCDGPIOALT5GPIO3_IO[11]100KPDD18LCD_DATA07NVCC_LCDGPIOALT5GPIO3_IO[12]100KPDTable99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors131F20LCD_DATA08NVCC_LCDGPIOALT5GPIO3_IO[13]100KPDG20LCD_DATA09NVCC_LCDGPIOALT5GPIO3_IO[14]100KPDA27LCD_DATA10NVCC_LCDGPIOALT5GPIO3_IO[15]100KPDE27LCD_DATA11NVCC_LCDGPIOALT5GPIO3_IO[16]100KPDF27LCD_DATA12NVCC_LCDGPIOALT5GPIO3_IO[17]100KPDE28LCD_DATA13NVCC_LCDGPIOALT5GPIO3_IO[18]100KPDG27LCD_DATA14NVCC_LCDGPIOALT5GPIO3_IO[19]100KPDB28LCD_DATA15NVCC_LCDGPIOALT5GPIO3_IO[20]100KPDC27LCD_DATA16NVCC_LCDGPIOALT5GPIO3_IO[21]100KPDD26LCD_DATA17NVCC_LCDGPIOALT5GPIO3_IO[22]100KPDD27LCD_DATA18NVCC_LCDGPIOALT5GPIO3_IO[23]100KPDD28LCD_DATA19NVCC_LCDGPIOALT5GPIO3_IO[24]100KPDG26LCD_DATA20NVCC_LCDGPIOALT5GPIO3_IO[25]100KPDH26LCD_DATA21NVCC_LCDGPIOALT5GPIO3_IO[26]100KPDB27LCD_DATA22NVCC_LCDGPIOALT5GPIO3_IO[27]100KPDD25LCD_DATA23NVCC_LCDGPIOALT5GPIO3_IO[28]100KPDG28LCD_ENABLENVCC_LCDGPIOALT5GPIO3_IO[1]100KPDF25LCD_HSYNCNVCC_LCDGPIOALT5GPIO3_IO[2]100KPDE20LCD_RESETNVCC_LCDGPIOALT5GPIO3_IO[4]100KPDF24LCD_VSYNCNVCC_LCDGPIOALT5GPIO3_IO[3]100KPDB16MIPI_CSI_CLK_NMIPI_VDDA_1P8MIPI_CSI_CLK_NA16MIPI_CSI_CLK_PMIPI_VDDA_1P8MIPI_CSI_CLK_PB18MIPI_CSI_D0_NMIPI_VDDA_1P8MIPI_CSI_D0_NA18MIPI_CSI_D0_PMIPI_VDDA_1P8MIPI_CSI_D0_PB15MIPI_CSI_D1_NMIPI_VDDA_1P8MIPI_CSI_D1_NB14MIPI_CSI_D1_PMIPI_VDDA_1P8MIPI_CSI_D1_PB24MIPI_DSI_CLK_NMIPI_VDDA_1P8MIPI_DSI_CLK_NA24MIPI_DSI_CLK_PMIPI_VDDA_1P8MIPI_DSI_CLK_PB25MIPI_DSI_D0_NMIPI_VDDA_1P8MIPI_DSI_D0_NA25MIPI_DSI_D0_PMIPI_VDDA_1P8MIPI_DSI_D0_PA22MIPI_DSI_D1_NMIPI_VDDA_1P8MIPI_DSI_D1_NB22MIPI_DSI_D1_PMIPI_VDDA_1P8MIPI_DSI_D1_PTable99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors132AD13ONOFFVDD_SNVS_INONOFFAG13PCIE_REFCLKIN_NPCIE_VPHPCIE_REFCLKIN_NAH13PCIE_REFCLKIN_PPCIE_VPHPCIE_REFCLKIN_PAG11PCIE_REFCLKOUT_NPCIE_VPHPCIE_REFCLKOUT_NAH11PCIE_REFCLKOUT_PPCIE_VPHPCIE_REFCLKOUT_PY16PCIE_REXTPCIE_VPHPCIE_REXTAG16PCIE_RX_NPCIE_VPH_RXPCIE_RX_NAH16PCIE_RX_PPCIE_VPH_RXPCIE_RX_PAG14PCIE_TX_NPCIE_VPH_TXPCIE_TX_NAG15PCIE_TX_PPCIE_VPH_TXPCIE_TX_PAD11CCM_PMIC_STBY_REQVDD_SNVS_INGPIOCCM_PMIC_STBY_REQY03POR_BNVCC_GPIO1GPIOALT0POR_B100KPUAG09RTC_XTALIVDD_SNVS_1P8_CAPRTC_XTALIAH09RTC_XTALOVDD_SNVS_1P8_CAPRTC_XTALOD03SAI1_MCLKNVCC_SAIGPIOALT5GPIO6_IO[18]100KPDG04SAI1_RXCNVCC_SAIGPIOALT5GPIO6_IO[17]100KPDF03SAI1_RXDNVCC_SAIGPIOALT5GPIO6_IO[12]100KPDC04SAI1_RXFSNVCC_SAIGPIOALT5GPIO6_IO[16]100KPDF04SAI1_TXCNVCC_SAIGPIOALT5GPIO6_IO[13]100KPDG05SAI1_TXDNVCC_SAIGPIOALT5GPIO6_IO[15]100KPDF05SAI1_TXFSNVCC_SAIGPIOALT5GPIO6_IO[14]100KPDE06SAI2_RXDNVCC_SAIGPIOALT5GPIO6_IO[21]100KPDD04SAI2_TXCNVCC_SAIGPIOALT5GPIO6_IO[20]100KPDD06SAI2_TXDNVCC_SAIGPIOALT5GPIO6_IO[22]100KPDF06SAI2_TXFSNVCC_SAIGPIOALT5GPIO6_IO[19]100KPDA05SD1_CD_BNVCC_SD1GPIOALT5GPIO5_IO[0]100KPDB03SD1_CLKNVCC_SD1GPIOALT5GPIO5_IO[3]100KPDA02SD1_CMDNVCC_SD1GPIOALT5GPIO5_IO[4]100KPDB04SD1_DATA0NVCC_SD1GPIOALT5GPIO5_IO[5]100KPDA04SD1_DATA1NVCC_SD1GPIOALT5GPIO5_IO[6]100KPDB02SD1_DATA2NVCC_SD1GPIOALT5GPIO5_IO[7]100KPDB01SD1_DATA3NVCC_SD1GPIOALT5GPIO5_IO[8]100KPDTable99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors133C02SD1_RESET_BNVCC_SD1GPIOALT5GPIO5_IO[2]100KPDD02SD1_WPNVCC_SD1GPIOALT5GPIO5_IO[1]100KPDE01SD2_CD_BNVCC_SD2GPIOALT5GPIO5_IO[9]100KPDG01SD2_CLKNVCC_SD2GPIOALT5GPIO5_IO[12]100KPDG02SD2_CMDNVCC_SD2GPIOALT5GPIO5_IO[13]100KPDF02SD2_DATA0NVCC_SD2GPIOALT5GPIO5_IO[14]100KPDE02SD2_DATA1NVCC_SD2GPIOALT5GPIO5_IO[15]100KPDH03SD2_DATA2NVCC_SD2GPIOALT5GPIO5_IO[16]100KPDG03SD2_DATA3NVCC_SD2GPIOALT5GPIO5_IO[17]100KPDJ03SD2_RESET_BNVCC_SD2GPIOALT5GPIO5_IO[11]100KPDD01SD2_WPNVCC_SD2GPIOALT5GPIO5_IO[10]100KPDJ06SD3_CLKNVCC_SD3GPIOALT5GPIO6_IO[0]100KPDL04SD3_CMDNVCC_SD3GPIOALT5GPIO6_IO[1]100KPDG06SD3_DATA0NVCC_SD3GPIOALT5GPIO6_IO[2]100KPDG07SD3_DATA1NVCC_SD3GPIOALT5GPIO6_IO[3]100KPDL07SD3_DATA2NVCC_SD3GPIOALT5GPIO6_IO[4]100KPDL06SD3_DATA3NVCC_SD3GPIOALT5GPIO6_IO[5]100KPDL05SD3_DATA4NVCC_SD3GPIOALT5GPIO6_IO[6]100KPDJ07SD3_DATA5NVCC_SD3GPIOALT5GPIO6_IO[7]100KPDJ05SD3_DATA6NVCC_SD3GPIOALT5GPIO6_IO[8]100KPDJ04SD3_DATA7NVCC_SD3GPIOALT5GPIO6_IO[9]100KPDJ02SD3_RESET_BNVCC_SD3GPIOALT5GPIO6_IO[11]100KPDJ01SD3_STROBENVCC_SD3GPIOALT5GPIO6_IO[10]100KPDAE13SNVS_PMIC_ON_REQVDD_SNVS_INSNVS_PMIC_ON_REQAE11SNVS_TAMPER0VDDD_SNVS_1P8_CAPAnalogSNVS_TAMPER0AC11SNVS_TAMPER1VDD_SNVS_1P8_CAPAnalogSNVS_TAMPER1AC09SNVS_TAMPER2VDDD_SNVS_1P8_CAPAnalogSNVS_TAMPER2AB09SNVS_TAMPER9VDD_SNVS_1P8_CAPAnalogSNVS_TAMPER9AF06TEMPSENSOR_RESERVEVDD_TEMPSENSOR_1P8AF07TEMPSENSOR_REXTVDD_TEMPSENSOR_1P8TEMPSENSOR_REXTAA03TEST_MODENVCC_GPIO1GPIOALT0TEST_MODE100KPDT01UART1_RXDNVCC_UARTGPIOALT5GPIO4_IO[0]100KPDTable99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors134V01UART1_TXDNVCC_UARTGPIOALT5GPIO4_IO[1]100KPDT02UART2_RXDNVCC_UARTGPIOALT5GPIO4_IO[2]100KPDT03UART2_TXDNVCC_UARTGPIOALT5GPIO4_IO[3]100KPDV03UART3_CTSNVCC_UARTGPIOALT5GPIO4_IO[7]100KPDW02UART3_RTSNVCC_UARTGPIOALT5GPIO4_IO[6]100KPDV02UART3_RXDNVCC_UARTGPIOALT5GPIO4_IO[4]100KPDU03UART3_TXDNVCC_UARTGPIOALT5GPIO4_IO[5]100KPDA13USB_H_DATAUSB_H_VDD_1P2USB_H_DATAB13USB_H_STROBEUSB_H_VDD_1P2USB_H_STROBEB06USB_OTG1_CHD_BUSB_OTG1_VDDA_3P3USB_OTG1_CHD_BB07USB_OTG1_DNUSB_OTG1_VDDA_3P3USB_OTG1_DNA07USB_OTG1_DPUSB_OTG1_VDDA_3P3USB_OTG1_DPB09USB_OTG1_IDUSB_OTG1_VDDA_3P3USB_OTG1_IDC08USB_OTG1_REXTUSB_OTG1_VDDA_3P3USB_OTG1_REXTB11USB_OTG2_DNUSB_OTG2_VDDA_3P3USB_OTG2_DNA11USB_OTG2_DPUSB_OTG2_VDDA_3P3USB_OTG2_DPB10USB_OTG2_IDUSB_OTG2_VDDA_3P3USB_OTG2_IDA09USB_OTG2_REXTUSB_OTG2_VDDA_3P3USB_OTG2_REXTAG02XTALIVDDA_1P8XTALIAG01XTALOVDDA_1P8XTALO1ThestateimmediatelyafterRESETandbeforeROMfirmwareorsoftwarehasexecuted.
Table99.
i.
MX7Dual12x12mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1356.
1.
3i.
MX7Dual12x12mm0.
4mmPitchBallMapThefollowingtableshowsthei.
MX7Dual12x12mm0.
4mmpitchballmap.
Table100.
i.
MX7Dual12x12mm0.
4mmpitchballmap12345678910111213141516171819202122232425262728AVSSSD1_CMDSD1_DATA1SD1_CD_BUSB_OTG1_DPUSB_OTG2_REXTUSB_OTG2_DPUSB_H_DATAMIPI_CSI_CLK_PMIPI_CSI_D0_PVDD_ARMMIPI_DSI_D1_NMIPI_DSI_CLK_PMIPI_DSI_D0_PLCD1_DATA10VSSABSD1_DATA3SD1_DATA2SD1_CLKSD1_DATA0VSSUSB_OTG1_CHD_BUSB_OTG1_DNUSB_OTG1_IDUSB_OTG2_IDUSB_OTG2_DNUSB_H_STROBEMIPI_CSI_D1_PMIPI_CSI_D1_NMIPI_CSI_CLK_NMIPI_CSI_D0_NMIPI_VREG_0P4VVDD_ARMMIPI_DSI_D1_PVSSMIPI_DSI_CLK_NMIPI_DSI_D0_NVSSLCD1_DATA22LCD1_DATA15BCSD1_RESET_BVSSSAI1_RXFSVSSENET1_RX_CLKVSSUSB_OTG1_REXTUSB_OTG1_VBUSVSSUSB_OTG2_VBUSVDD_USB_H_1P2VSSVSSVSSVDD_ARMVDD_ARMVDD_ARMVDD_ARMVDD_ARMVDD_ARMVDD_ARMVSSVSSVSSVSSLCD1_DATA16CDSD2_WPSD1_WPSAI1_MCLKSAI2_TXCSAI2_TXDENET1_RDATA2VSSVDD_USB_OTG1_3P3_INVDD_USB_OTG2_3P3_INVSSENET1_TDATA1ENET1_RDATA3VSSLCD1_DATA07LCD1_CLKVSSLCD1_DATA04LCD1_DATA05LCD1_DATA23LCD1_DATA17LCD1_DATA18LCD1_DATA19DESD2_CD_BSD2_DATA1VSSVSSSAI2_RXDENET1_RDATA1VDD_USB_OTG1_1P0_CAPENET1_RX_CTLENET1_TDATA0ENET1_TDATA2LCD1_DATA06LCD1_RESETLCD1_DATA03LCD1_DATA02VSSVSSLCD1_DATA11LCD1_DATA13EFSD2_DATA0SAI1_RXDSAI1_TXCSAI1_TXFSSAI2_TXFSENET1_RDATA0VSSVDD_USB_OTG2_1P0_CAPVSSENET1_RXCVSSENET1_TX_CLKVSSVSSENET1_TDATA3VSSENET1_CRSVDD_ARMLCD1_DATA08VSSLCD1_DATA00LCD1_DATA01LCD1_VSYNCLCD1_HSYNCEPDC1_SDSHRLCD1_DATA12FGSD2_CLKSD2_CMDSD2_DATA3SAI1_RXCSAI1_TXDSD3_DATA0SD3_DATA1ENET1_TXCENET1_TX_CTLVDD_USB_H_1P2PVCC_ENET_CAPENET1_COLLCD1_DATA09EPDC1_SDCE2EPDC1_SDCE3EPDC1_SDCLKEPDC1_SDOELCD1_DATA20LCD1_DATA14LCD1_ENABLEG12345678910111213141516171819202122232425262728Packageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors136HSD2_DATA2VSSVSSVDD_SOCVDD_ARMVSSVSSLCD1_DATA21HJSD3_STROBESD3_RESET_BSD2_RESET_BSD3_DATA7SD3_DATA6SD3_CLKSD3_DATA5VDD_SOCNVCC_SD1NVCC_SAIPVCC_SAI_SD_CAPVDDA_MIPI_1P8VDD_MIPI_1P0NVCC_ENET1VDD_ARMEPDC1_GDOEEPDC1_GDCLKEPDC1_SDCE1EPDC1_SDCE0EPDC1_PWRSTATEPDC1_PWRCOMEPDC1_SDLEJKECSPI1_SCLKVDD_SOCVDD_SOCVDD_SOCVDD_ARMVDD_ARMVDD_ARMEPDC1_GDSPKLVDD_SOCVDD_SOCECSPI1_MOSISD3_CMDSD3_DATA4SD3_DATA3SD3_DATA2NVCC_SD2VDD_SOCVSSVSSVDD_SOCNVCC_LCDEPDC1_BDR1EPDC1_BDR0EPDC1_GDRLEPDC1_DATA14EPDC1_DATA13VDD_ARMVDD_ARMLMECSPI1_MISOVSSVSSVSSVSSEPDC1_DATA12MNECSPI2_SCLKECSPI2_MOSIECSPI1_SS0I2C1_SCLI2C1_SDAI2C2_SCLI2C2_SDANVCC_SD3VSSVDD_SOCVDD_SOCVSSNVCC_EPDC2EPDC1_DATA15EPDC1_DATA04EPDC1_DATA11EPDC1_DATA10EPDC1_DATA09EPDC1_DATA08EPDC1_DATA07NPECSPI2_MISOVDD_SOCVDD_SOCNVCC_SPINVCC_EPDC1VDD_SOCVDD_SOCEPDC1_DATA06PRECSPI2_SS0VDD_SOCVDD_SOCNVCC_I2CPVCC_EPDC_LCD_CAPVDD_SOCVDD_SOCEPDC1_DATA03RTUART1_RXDUART2_RXDUART2_TXDI2C4_SDAI2C4_SCLI2C3_SCLI2C3_SDANVCC_UARTVSSVDD_SOCVDD_SOCVSSDRAM_VREFDRAM_DATA27DRAM_DATA26DRAM_DATA31DRAM_DATA30EPDC1_DATA02EPDC1_DATA00EPDC1_DATA05TUUART3_TXDVSSVSSVSSVSSEPDC1_DATA01UTable100.
i.
MX7Dual12x12mm0.
4mmpitchballmap(continued)1234567891011121314151617181920212223242526272812345678910111213141516171819202122232425262728Packageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors137VUART1_TXDUART3_RXDUART3_CTSGPIO1_IO00GPIO1_IO01GPIO1_IO06GPIO1_IO07FUSE_FSOURCEVDD_SOCVSSVSSVDD_SOCNVCC_DRAM_CKEDRAM_DATA25DRAM_DATA24DRAM_DATA28DRAM_DATA29DRAM_RESETNVCC_DRAMNVCC_DRAMVWUART3_RTSVSSVSSPVCC_I2C_SPI_UART_CAPNVCC_DRAMNVCC_DRAMNVCC_DRAMDRAM_DATA16WYBOOT_MODE0BOOT_MODE1POR_BGPIO1_IO05GPIO1_IO04GPIO1_IO03GPIO1_IO02NVCC_GPIO1NVCC_GPIO2VDD_SNVS_INVDDA_PHY_1P8PCIE_VPHPCIE_REXTDRAM_ZQPADNVCC_DRAMDRAM_SDCKE0DRAM_SDQS3_PDRAM_SDQS3_NDRAM_DQM3DRAM_DATA18DRAM_DATA17DRAM_DATA19YAATEST_MODEVSSVSSVDD_1P2_CAPNVCC_DRAMVSSVSSDRAM_DATA20AAABJTAG_MODJTAG_TRST_BGPIO1_IO08GPIO1_IO09GPIO1_IO10GPIO1_IO11ADC1_IN0SNVS_TAMPER09PVCC_GPIO_CAPPCIE_VPDRAM_DATA14DRAM_DATA09DRAM_SDQS1_PDRAM_SDBA1DRAM_SDCKE1DRAM_ADDR04DRAM_ADDR03DRAM_DATA21DRAM_DATA22DRAM_DATA23ABACJTAG_TDIGPIO1_IO15GPIO1_IO14GPIO1_IO13GPIO1_IO12ADC1_IN1VSSSNVS_TAMPER02VSSSNVS_TAMPER01VSSVDDD_1P0_CAPVSSVSSDRAM_DATA11VSSDRAM_DATA08NVCC_DRAMDRAM_SDQS1_NVSSDRAM_ADDR09DRAM_CS1_BDRAM_ADDR00DRAM_ADDR01DRAM_ADDR02DRAM_SDQS2_PACADJTAG_TCKJTAG_TMSVSSVSSVSSADC1_IN2ADC1_IN3PMIC_STBY_REQONOFFDRAM_DATA10DRAM_DATA12DRAM_DQM1DRAM_ADDR08DRAM_ADDR10VSSVSSDRAM_SDQS2_NDRAM_DQM2ADAEJTAG_TDOCCM_CLK2CCM_CLK1_PCCM_CLK1_NVSSVSSVSSVSSSNVS_TAMPER00VDDD_1P0_CAPSNVS_PMIC_ON_REQDRAM_DATA15VSSDRAM_DATA13DRAM_ADDR14VSSDRAM_ADDR07DRAM_ADDR05DRAM_SDCLK0_PDRAM_CS0_BDRAM_ADDR12DRAM_SDBA0AETable100.
i.
MX7Dual12x12mm0.
4mmpitchballmap(continued)1234567891011121314151617181920212223242526272812345678910111213141516171819202122232425262728Packageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors138AFGPANAIOVSSVDDA_1P8_INVSSTEMPSENSOR_RESERVETEMPSENSOR_REXTVSSVSSVSSVSSVDDD_1P0_CAPVSSVSSVSSDRAM_ODT0NVCC_DRAMNVCC_DRAMNVCC_DRAMDRAM_DATA04DRAM_DATA06DRAM_DATA03DRAM_ADDR06VSSDRAM_SDCLK0_NVSSDRAM_SDBA2AFAGXTALOXTALIVDDA_1P8_INVDDA_1P8_INVDD_LPSR_INVDD_LPSR_1P0_CAPVDD_SNVS_1P8_CAPRTC_XTALIVSSPCIE_REFCLKOUT_NPCIE_REFCLKIN_NPCIE_TX_NPCIE_TX_PPCIE_RX_NNVCC_DRAMDRAM_DATA01DRAM_DATA02DRAM_DATA05DRAM_SDQS0_NDRAM_SDQS0_PDRAM_CAS_BDRAM_ADDR15DRAM_ADDR11DRAM_ADDR13AGAHVSSVDD_XTAL_1P8VDDA_ADC1_1P8VDD_TEMPSENSOR_1P8VDDA_1P0_CAPRTC_XTALOPCIE_REFCLKOUT_PPCIE_REFCLKIN_PPCIE_RX_PNVCC_DRAMDRAM_DATA07DRAM_DATA00DRAM_DQM0DRAM_RAS_BDRAM_SDWE_BVSSAHTable100.
i.
MX7Dual12x12mm0.
4mmpitchballmap(continued)1234567891011121314151617181920212223242526272812345678910111213141516171819202122232425262728Packageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1396.
219x19mmpackageinformation6.
2.
1Case"Y",19x19mm,0.
75mmpitch,ballmatrixFigure88showsthetop,bottom,andsideviewsofthe19*19mmBGApackage.
Figure88.
19x19mmBGA,CasexPackageTop,Bottom,andSideViewsPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1406.
2.
219x19mmsuppliescontactassignmentsandfunctionalcontactassignmentsTable101showssuppliescontactassignmentsforthe19x19mmpackage.
Table101.
i.
MX7Dual19x19mmsuppliescontactassignmentsRailPinsCommentsADC2_VDDA_1P8AB03DRAM_VREFAC13DRAM_ZQPADAB13DDRoutputbufferdrivercalibrationreferencevoltageinput.
ConnectDRAM_ZQPADtoanexternal240Ω1%resistortoVssFUSE_FSOURCE0V08GNDA01,A03,A06,A09,A13,A17,A21,A25,B03,B06,B09,B13,B17,B21,C09,C13,C15,C16,C18,C19,D01,D02,D04,D07,D10,D22,F07,F08,F11,F13,G07,G04,G09,G11,G13,G15,G17,G19,G22,H01,H02,J07,J19,K04,K10,K12,K14,K16,K22,L07,L11,L13,L15,L19,M10,M12,M14,M16,M24,M25,N04,N07,N11,N13,N15,N19,P10,P12,P14,P16,R07,R11,R13,R15,R19,R20,R21,R23,T04,T10,T12,T14,T16,T20,U07,U11,U19,U20,U23,V20,W01,W02,W04,W07,W09,W11,W13,W15,W17,W19,W20,W23,Y06,Y13,Y14,Y15,Y16,Y17,Y18,Y19,AA01,AA02,AA06,AA08,AA15,AA23,AB04,AB05,AB07,AB09,AB12,AC06,AC09,AC12,AC15,AC17,AC19,AC21,AC23,AD02,AD07,AD09,AD12,AE01,AE05,AE07,AE09,AE12,AE24,AE25,AD05GroundGPANIOV04Testsignal.
Shouldbeleftunconnected.
MIPI_VREG_0P4VH18NVCC_DRAMT21,U21,V21,W21,Y21,AA16,AA17,AA18,AA19,AA20,AA21NVCC_DRAM_CKEY20NVCC_ENET1H16SupplyforENETinterfaceNVCC_EPDC1M18SupplyforEPDCinterfaceNVCC_EPDC2L17SupplyforEPDCinterfaceNVCC_GPIO1P08SupplyforGPIO1interfaceNVCC_GPIO2T08SupplyforGPIO2interfaceNVCC_I2CM08SupplyforI2CinterfaceNVCC_LCDK18SupplyforLCDinterfaceNVCC_SAIF12SupplyforSAIinterfaceNVCC_SD1E07SupplyforSDcardinterfacePackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors141NVCC_SD2H08SupplyforSDcardinterfaceNVCC_SD3K08SupplyforSDcardinterfaceNVCC_SPIL09SupplyforSPIinterfaceNVCC_UARTN09SupplyforUARTinterfacePCIE_VPAA10SupplyforPCIe'interfacePCIE_VP_RXAA12SupplyforPCIePHYPCIE_VP_TXAA11SupplyforPCIePHYPCIE_VPHY10PCIE_VPH_RXY12PCIE_VPH_TXY11PVCC_ENET_CAPH14SecondarysupplyforENET(internalregulatoroutput).
RequiresexternalcapacitorsPVCC_EPDC_LCD_CAPN17SecondarysupplyforEPDC_LCD(internalregulatoroutput).
RequiresexternalcapacitorsPVCC_GPIO_CAPV10SecondarysupplyforGPIO(internalregulatoroutput).
RequiresexternalcapacitorsPVCC_I2C_SPI_UART_CAPR09SecondarysupplyforI2C_SPI_UART(internalregulatoroutput).
RequiresexternalcapacitorsPVCC_SAI_SD_CAPJ09SecondarysupplyforSAI_SD(internalregulatoroutput).
RequiresexternalcapacitorsUSB_OTG1_VBUSC08USB_OTG1_VDDA_3P3_INF10USB_OTG2_VBUSC10USB_OTG2_VDDA_3P3_INF09VDD_1P2_CAPU09SupplyforHSICVDD_ARMC17,C20,D17,D20,F22,F23,J22,J23SupplyforArmVDD_LPSR_1P0_CAPAC05SecondarysupplyforLPSR(internalregulatoroutput).
RequiresexternalcapacitorsVDD_LPSR_INW06SupplyforLPSRVDD_SNVS_1P8_CAPAE08SecondarysupplyforSNVS(internalregulatoroutput).
RequiresexternalcapacitorsVDD_SNVS_INAD08PrimarysupplyfortheSNVSregulatorVDD_SOCC14,D14,F03,F04,F18,F19,J03,J04,M03,M04,P18,R03,R04,R17,T18,U13,U15,U17,V12,V14,V16,V18SupplyforSOCVDD_TEMPSENSOR_1P8AC04SupplyforVDDePHYTable101.
i.
MX7Dual19x19mmsuppliescontactassignments(continued)RailPinsCommentsPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors142Table102showsanalpha-sortedlistoffunctionalcontactassignmentsforthe19x19mmpackage.
VDD_USB_H_1P2H12SupplyinputfortheUSBHSICInterfaceVDD_USB_OTG1_1P0_CAPH10SecondarysupplyforUSBOTG(internalregulatoroutput).
RequiresexternalcapacitorsVDD_USB_OTG2_1P0_CAPJ11SecondarysupplyforUSBOTG(internalregulatoroutput).
RequiresexternalcapacitorsVDD_XTAL_1P8V05VDDA_1P0_CAPV03Secondarysupplyfor1P0(internalregulatoroutput).
RequiresexternalcapacitorsVDDA_1P8_INV06,W05VDDA_ADC1_1P8AC03SupplyforADCVDDA_PHY_1P8Y09VDDD_1P0_CAPAA09Secondarysupplyfor1P0(internalregulatoroutput).
RequiresexternalcapacitorsTable102.
i.
MX7Dual19x19mmfunctionalcontactassignmentsBallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUAD01ADC1_IN0ADC1_VDDA_1P8ADC1_IN0AD03ADC1_IN1ADC1_VDDA_1P8ADC1_IN1AE02ADC1_IN2ADC1_VDDA_1P8ADC1_IN2AE03ADC1_IN3ADC1_VDDA_1P8ADC1_IN3AC01ADC2_IN0ADC2_VDDA_1P8ADC2_IN0AC02ADC2_IN1ADC2_VDDA_1P8ADC2_IN1AB01ADC2_IN2ADC2_VDDA_1P8ADC2_IN2AB02ADC2_IN3ADC2_VDDA_1P8ADC2_IN3P04BOOT_MODE0NVCC_GPIO1GPIOALT0BOOT_MODE0100KPDP05BOOT_MODE1NVCC_GPIO1GPIOALT0BOOT_MODE1100KPDY01CCM_CLK1_NVDDA_1P8CCM_CLK1_NY02CCM_CLK1_PVDDA_1P8CCM_CLK1_PW03CCM_CLK2VDDA_1P8CCM_CLK2AC07CCM_PMIC_STBY_REQVDD_SNVS_INCCM_PMIC_STBY_REQAB19DRAM_ADDR00NVCC_DRAMDDRDRAM_ADDR00AB16DRAM_ADDR01NVCC_DRAMDDRDRAM_ADDR01Table101.
i.
MX7Dual19x19mmsuppliescontactassignments(continued)RailPinsCommentsPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors143AC18DRAM_ADDR02NVCC_DRAMDDRDRAM_ADDR02AC20DRAM_ADDR03NVCC_DRAMDDRDRAM_ADDR03AB21DRAM_ADDR04NVCC_DRAMDDRDRAM_ADDR04Y23DRAM_ADDR05NVCC_DRAMDDRDRAM_ADDR05V22DRAM_ADDR06NVCC_DRAMDDRDRAM_ADDR06Y22DRAM_ADDR07NVCC_DRAMDDRDRAM_ADDR07W22DRAM_ADDR08NVCC_DRAMDDRDRAM_ADDR08V23DRAM_ADDR09NVCC_DRAMDDRDRAM_ADDR09T23DRAM_ADDR10NVCC_DRAMDDRDRAM_ADDR10U22DRAM_ADDR11NVCC_DRAMDDRDRAM_ADDR11T22DRAM_ADDR12NVCC_DRAMDDRDRAM_ADDR12P23DRAM_ADDR13NVCC_DRAMDDRDRAM_ADDR13AB18DRAM_ADDR14NVCC_DRAMDDRDRAM_ADDR14AB20DRAM_ADDR15NVCC_DRAMDDRDRAM_ADDR15AC14DRAM_CAS_BNVCC_DRAMDDRDRAM_CAS_BAB23DRAM_CS0_BNVCC_DRAMDDRDRAM_CS0_BAA22DRAM_CS1_BNVCC_DRAMDDRDRAM_CS1_BAD22DRAM_DATA00NVCC_DRAMDDRDRAM_DATA00AD23DRAM_DATA01NVCC_DRAMDDRDRAM_DATA01AE20DRAM_DATA02NVCC_DRAMDDRDRAM_DATA02AE23DRAM_DATA03NVCC_DRAMDDRDRAM_DATA03AE22DRAM_DATA04NVCC_DRAMDDRDRAM_DATA04AD19DRAM_DATA05NVCC_DRAMDDRDRAM_DATA05AD18DRAM_DATA06NVCC_DRAMDDRDRAM_DATA06AE19DRAM_DATA07NVCC_DRAMDDRDRAM_DATA07AE14DRAM_DATA08NVCC_DRAMDDRDRAM_DATA08AE18DRAM_DATA09NVCC_DRAMDDRDRAM_DATA09AE17DRAM_DATA10NVCC_DRAMDDRDRAM_DATA10AD16DRAM_DATA11NVCC_DRAMDDRDRAM_DATA11AE16DRAM_DATA12NVCC_DRAMDDRDRAM_DATA12AD14DRAM_DATA13NVCC_DRAMDDRDRAM_DATA13AD13DRAM_DATA14NVCC_DRAMDDRDRAM_DATA14Table102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors144AE13DRAM_DATA15NVCC_DRAMDDRDRAM_DATA15AA25DRAM_DATA16NVCC_DRAMDDRDRAM_DATA16W24DRAM_DATA17NVCC_DRAMDDRDRAM_DATA17V25DRAM_DATA18NVCC_DRAMDDRDRAM_DATA18W25DRAM_DATA19NVCC_DRAMDDRDRAM_DATA19AC25DRAM_DATA20NVCC_DRAMDDRDRAM_DATA20AB25DRAM_DATA21NVCC_DRAMDDRDRAM_DATA21AB24DRAM_DATA22NVCC_DRAMDDRDRAM_DATA22AC24DRAM_DATA23NVCC_DRAMDDRDRAM_DATA23R25DRAM_DATA24NVCC_DRAMDDRDRAM_DATA24N24DRAM_DATA25NVCC_DRAMDDRDRAM_DATA25P25DRAM_DATA26NVCC_DRAMDDRDRAM_DATA26N25DRAM_DATA27NVCC_DRAMDDRDRAM_DATA27U25DRAM_DATA28NVCC_DRAMDDRDRAM_DATA28R24DRAM_DATA29NVCC_DRAMDDRDRAM_DATA29U24DRAM_DATA30NVCC_DRAMDDRDRAM_DATA30V24DRAM_DATA31NVCC_DRAMDDRDRAM_DATA31AD20DRAM_DQM0NVCC_DRAMDDRDRAM_DQM0AD17DRAM_DQM1NVCC_DRAMDDRDRAM_DQM1AA24DRAM_DQM2NVCC_DRAMDDRDRAM_DQM2P24DRAM_DQM3NVCC_DRAMDDRDRAM_DQM3AC16DRAM_ODT0NVCC_DRAMDDRDRAM_ODT0AA14DRAM_ODT1NVCC_DRAMDDRDRAM_ODT1AB15DRAM_RAS_BNVCC_DRAMDDRDRAM_RAS_BAC22DRAM_RESETNVCC_DRAM_CKEDDRDRAM_RESETR22DRAM_SDBA0NVCC_DRAMDDRDRAM_SDBA0P22DRAM_SDBA1NVCC_DRAMDDRDRAM_SDBA1N23DRAM_SDBA2NVCC_DRAMDDRDRAM_SDBA2AB17DRAM_SDCKE0NVCC_DRAM_CKEDDRDRAM_SDCKE0AB22DRAM_SDCKE1NVCC_DRAM_CKEDDRDRAM_SDCKE1AD25DRAM_SDCLK0_NNVCC_DRAMDDRCLKDRAM_SDCLK0_NAD24DRAM_SDCLK0_PNVCC_DRAMDDRCLKDRAM_SDCLK0_PTable102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors145AD21DRAM_SDQS0_NNVCC_DRAMDDRCLKDRAM_SDQS0_NAE21DRAM_SDQS0_PNVCC_DRAMDDRCLKDRAM_SDQS0_PAE15DRAM_SDQS1_NNVCC_DRAMDDRCLKDRAM_SDQS1_NAD15DRAM_SDQS1_PNVCC_DRAMDDRCLKDRAM_SDQS1_PY25DRAM_SDQS2_NNVCC_DRAMDDRCLKDRAM_SDQS2_NY24DRAM_SDQS2_PNVCC_DRAMDDRCLKDRAM_SDQS2_PT25DRAM_SDQS3_NNVCC_DRAMDDRCLKDRAM_SDQS3_NT24DRAM_SDQS3_PNVCC_DRAMDDRCLKDRAM_SDQS3_PAB14DRAM_SDWE_BNVCC_DRAMDDRDRAM_SDWE_BH04ECSPI1_MISONVCC_SPIGPIOALT5GPIO4_IO[18]100KPDG05ECSPI1_MOSINVCC_SPIGPIOALT5GPIO4_IO[17]100KPDH03ECSPI1_SCLKNVCC_SPIGPIOALT5GPIO4_IO[16]100KPDH05ECSPI1_SS0NVCC_SPIGPIOALT5GPIO4_IO[19]100KPDH06ECSPI2_MISONVCC_SPIGPIOALT5GPIO4_IO[22]100KPDG06ECSPI2_MOSINVCC_SPIGPIOALT5GPIO4_IO[21]100KPDJ05ECSPI2_SCLKNVCC_SPIGPIOALT5GPIO4_IO[20]100KPDJ06ECSPI2_SS0NVCC_SPIGPIOALT5GPIO4_IO[23]100KPDD19ENET1_COLNVCC_ENET1GPIOALT5GPIO7_IO[15]100KPDE19ENET1_CRSNVCC_ENET1GPIOALT5GPIO7_IO[14]100KPDE14ENET1_RD0NVCC_ENET1GPIOALT5GPIO7_IO[0]100KPDF14ENET1_RD1NVCC_ENET1GPIOALT5GPIO7_IO[1]100KPDD13ENET1_RD2NVCC_ENET1GPIOALT5GPIO_IO[2]100KPDE13ENET1_RD3NVCC_ENET1GPIOALT5GPIO7_IO[3]100KPDD15ENET1_RX_CLKNVCC_ENET1GPIOALT5GPIO7_IO[13]100KPDE15ENET1_RX_CTLNVCC_ENET1GPIOALT5GPIO7_IO[4]100KPDF15ENET1_RXCNVCC_ENET1GPIOALT5GPIO7_IO[5]100KPDF17ENET1_TD0NVCC_ENET1GPIOALT5GPIO7_IO[6]100KPDE17ENET1_TD1NVCC_ENET1GPIOALT5GPIO_IO[7]100KPDE18ENET1_TD2NVCC_ENET1GPIOALT5GPIO7_IO[8]100KPDD18ENET1_TD3NVCC_ENET1GPIOALT5GPIO7_IO[9]100KPDD16ENET1_TX_CLKNVCC_ENET1GPIOALT5GPIO7_IO[12]100KPDE16ENET1_TX_CTLNVCC_ENET1GPIOALT5GPIO7_IO[10]100KPDTable102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors146F16ENET1_TXCNVCC_ENET1GPIOALT5GPIO7_IO[11]100KPDK24EPDC_BDR0NVCC_EPDC2GPIOALT5GPIO2_IO[28]100KPDK23EPDC_BDR1NVCC_EPDC2GPIOALT5GPIO2_IO[29]100KPDP20EPDC_D00NVCC_EPDC1GPIOALT5GPIO2_IO[0]100KPDP21EPDC_D01NVCC_EPDC1GPIOALT5GPIO2_IO[1]100KPDN20EPDC_D02NVCC_EPDC1GPIOALT5GPIO2_IO[2]100KPDN21EPDC_D03NVCC_EPDC1GPIOALT5GPIO2_IO[3]100KPDN22EPDC_D04NVCC_EPDC1GPIOALT5GPIO2_IO[4]100KPDM20EPDC_D05NVCC_EPDC1GPIOALT5GPIO2_IO[5]100KPDM21EPDC_D06NVCC_EPDC1GPIOALT5GPIO2_IO[6]100KPDM22EPDC_D07NVCC_EPDC1GPIOALT5GPIO2_IO[7]100KPDM23EPDC_D08NVCC_EPDC1GPIOALT5GPIO2_IO[8]100KPDL25EPDC_D09NVCC_EPDC1GPIOALT5GPIO2_IO[9]100KPDL24EPDC_D10NVCC_EPDC1GPIOALT5GPIO2_IO[10]100KPDL23EPDC_D11NVCC_EPDC1GPIOALT5GPIO2_IO[11]100KPDL22EPDC_D12NVCC_EPDC1GPIOALT5GPIO2_IO[12]100KPDL21EPDC_D13NVCC_EPDC1GPIOALT5GPIO2_IO[13]100KPDL20EPDC_D14NVCC_EPDC1GPIOALT5GPIO2_IO[14]100KPDK25EPDC_D15NVCC_EPDC1GPIOALT5GPIO2_IO[15]100KPDJ25EPDC_GDCLKNVCC_EPDC2GPIOALT5GPIO2_IO[24]100KPDJ24EPDC_GDOENVCC_EPDC2GPIOALT5GPIO2_IO[25]100KPDK21EPDC_GDRLNVCC_EPDC2GPIOALT5GPIO2_IO[26]100KPDH25EPDC_GDSPNVCC_EPDC2GPIOALT5GPIO2_IO[27]100KPDH24EPDC_PWRCOMNVCC_EPDC2GPIOALT5GPIO2_IO[30]100KPDK20EPDC_PWRSTATNVCC_EPDC2GPIOALT5GPIO2_IO[31]100KPDG25EPDC_SDCE0NVCC_EPDC2GPIOALT5GPIO2_IO[20]100KPDG24EPDC_SDCE1NVCC_EPDC2GPIOALT5GPIO2_IO[21]100KPDH23EPDC_SDCE2NVCC_EPDC2GPIOALT5GPIO2_IO[22]100KPDH22EPDC_SDCE3NVCC_EPDC2GPIOALT5GPIO2_IO[23]100KPDJ21EPDC_SDCLKNVCC_EPDC2GPIOALT5GPIO2_IO[16]100KPDJ20EPDC_SDLENVCC_EPDC2GPIOALT5GPIO2_IO[17]100KPDH21EPDC_SDOENVCC_EPDC2GPIOALT5GPIO2_IO[18]100KPDTable102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors147H20EPDC_SDSHRNVCC_EPDC2GPIOALT5GPIO2_IO[19]100KPDN01GPIO1_IO00NVCC_GPIO1GPIOALT0GPIO1_IO00100KPUN02GPIO1_IO01NVCC_GPIO1GPIOALT0GPIO1_IO01100KPDN03GPIO1_IO02NVCC_GPIO1GPIOALT0GPIO1_IO02100KPDN05GPIO1_IO03NVCC_GPIO1GPIOALT0GPIO1_IO03100KPDN06GPIO1_IO04NVCC_GPIO1GPIOALT0GPIO1_IO04100KPDP01GPIO1_IO05NVCC_GPIO1GPIOALT0GPIO1_IO05100KPDP02GPIO1_IO06NVCC_GPIO1GPIOALT0GPIO1_IO06100KPDP03GPIO1_IO07NVCC_GPIO1GPIOALT0GPIO1_IO07100KPDR01GPIO1_IO08NVCC_GPIO2GPIOALT0GPIO1_IO08100KPDR02GPIO1_IO09NVCC_GPIO2GPIOALT0GPIO1_IO09100KPDR05GPIO1_IO10NVCC_GPIO2GPIOALT0GPIO1_IO10100KPDT01GPIO1_IO11NVCC_GPIO2GPIOALT0GPIO1_IO11100KPDT02GPIO1_IO12NVCC_GPIO2GPIOALT0GPIO1_IO12100KPDT03GPIO1_IO13NVCC_GPIO2GPIOALT0GPIO1_IO13100KPDT05GPIO1_IO14NVCC_GPIO2GPIOALT0GPIO1_IO14100KPDT06GPIO1_IO15NVCC_GPIO2GPIOALT0GPIO1_IO15100KPDJ02I2C1_SCLNVCC_I2CGPIOALT5GPIO4_IO[8]100KPDK01I2C1_SDANVCC_I2CGPIOALT5GPIO4_IO[9]100KPDK02I2C2_SCLNVCC_I2CGPIOALT5GPIO4_IO[10]100KPDK03I2C2_SDANVCC_I2CGPIOALT5GPIO4_IO[11]100KPDK05I2C3_SCLNVCC_I2CGPIOALT5GPIO4_IO[12]100KPDK06I2C3_SDANVCC_I2CGPIOALT5GPIO4_IO[13]100KPDL01I2C4_SCLNVCC_I2CGPIOALT5GPIO4_IO[14]100KPDL02I2C4_SDANVCC_I2CGPIOALT5GPIO4_IO[15]100KPDU01JTAG_MODNVCC_GPIO2GPIOALT0JTAG_MOD100KPUU05JTAG_TCKNVCC_GPIO2GPIOALT0JTAG_TCK47KPUU03JTAG_TDINVCC_GPIO2GPIOALT0JTAG_TDI47KPUU06JTAG_TDONVCC_GPIO2GPIOALT0JTAG_TDO100KPUU04JTAG_TMSNVCC_GPIO2GPIOALT0JTAG_TMS47KPUU02JTAG_TRST_BNVCC_GPIO2GPIOALT0JTAG_TRST_B47KPUE20LCD_CLKNVCC_LCDGPIOALT5GPIO3_IO[0]100KPDTable102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors148D21LCD_DATA00NVCC_LCDGPIOALT5GPIO3_IO[5]100KPDA22LCD_DATA01NVCC_LCDGPIOALT5GPIO3_IO[6]100KPDB22LCD_DATA02NVCC_LCDGPIOALT5GPIO3_IO[7]100KPDA23LCD_DATA03NVCC_LCDGPIOALT5GPIO3_IO[8]100KPDC22LCD_DATA04NVCC_LCDGPIOALT5GPIO3_IO[9]100KPDB23LCD_DATA05NVCC_LCDGPIOALT5GPIO3_IO[10]100KPDA24LCD_DATA06NVCC_LCDGPIOALT5GPIO3_IO[11]100KPDF20LCD_DATA07NVCC_LCDGPIOALT5GPIO3_IO[12]100KPDE21LCD_DATA08NVCC_LCDGPIOALT5GPIO3_IO[13]100KPDC23LCD_DATA09NVCC_LCDGPIOALT5GPIO3_IO[14]100KPDB24LCD_DATA10NVCC_LCDGPIOALT5GPIO3_IO[15]100KPDG20LCD_DATA11NVCC_LCDGPIOALT5GPIO3_IO[16]100KPDF21LCD_DATA12NVCC_LCDGPIOALT5GPIO3_IO[17]100KPDE22LCD_DATA13NVCC_LCDGPIOALT5GPIO3_IO[18]100KPDD23LCD_DATA14NVCC_LCDGPIOALT5GPIO3_IO[19]100KPDC24LCD_DATA15NVCC_LCDGPIOALT5GPIO3_IO[20]100KPDB25LCD_DATA16NVCC_LCDGPIOALT5GPIO3_IO[21]100KPDG21LCD_DATA17NVCC_LCDGPIOALT5GPIO3_IO[22]100KPDE23LCD_DATA18NVCC_LCDGPIOALT5GPIO3_IO[23]100KPDD24LCD_DATA19NVCC_LCDGPIOALT5GPIO3_IO[24]100KPDC25LCD_DATA20NVCC_LCDGPIOALT5GPIO3_IO[25]100KPDE24LCD_DATA21NVCC_LCDGPIOALT5GPIO3_IO[26]100KPDD25LCD_DATA22NVCC_LCDGPIOALT5GPIO3_IO[27]100KPDG23LCD_DATA23NVCC_LCDGPIOALT5GPIO3_IO[28]100KPDF25LCD_ENABLENVCC_LCDGPIOALT5GPIO3_IO[1]100KPDE25LCD_HSYNCNVCC_LCDGPIOALT5GPIO3_IO[2]100KPDC21LCD_RESETNVCC_LCDGPIOALT5GPIO3_IO[4]100KPDF24LCD_VSYNCNVCC_LCDGPIOALT5GPIO3_IO[3]100KPDA15MIPI_CSI_CLK_NMIPI_VDDA_1P8MIPI_CSI_CLK_NB15MIPI_CSI_CLK_PMIPI_VDDA_1P8MIPI_CSI_CLK_PA16MIPI_CSI_D0_NMIPI_VDDA_1P8MIPI_CSI_D0_NB16MIPI_CSI_D0_PMIPI_VDDA_1P8MIPI_CSI_D0_PTable102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors149A14MIPI_CSI_D1_NMIPI_VDDA_1P8MIPI_CSI_D1_NB14MIPI_CSI_D1_PMIPI_VDDA_1P8MIPI_CSI_D1_PA19MIPI_DSI_CLK_NMIPI_VDDA_1P8MIPI_DSI_CLK_NB19MIPI_DSI_CLK_PMIPI_VDDA_1P8MIPI_DSI_CLK_PA20MIPI_DSI_D0_NMIPI_VDDA_1P8MIPI_DSI_D0_NB20MIPI_DSI_D0_PMIPI_VDDA_1P8MIPI_DSI_D0_PA18MIPI_DSI_D1_NMIPI_VDDA_1P8MIPI_DSI_D1_NB18MIPI_DSI_D1_PMIPI_VDDA_1P8MIPI_DSI_D1_PJ13MIPI_VDDA_1P8MIPI_VDDA_1P8MIPI_VDDA_1P8J15MIPI_VDDD_1P0MIPI_VDDD_1P0MIPI_VDDD_1P0J17MIPI_VDDD_1P0MIPI_VDDD_1P0MIPI_VDDD_1P0AC08ONOFFVDD_SNVS_INONOFFAE10PCIE_REFCLKIN_NPCIE_VPHPCIE_REFCLKIN_NAD10PCIE_REFCLKIN_PPCIE_VPHPCIE_REFCLKIN_PAC10PCIE_REFCLKOUT_NPCIE_VPHPCIE_REFCLKOUT_NAB10PCIE_REFCLKOUT_PPCIE_VPHPCIE_REFCLKOUT_PAA13PCIE_REXTPCIE_VPHPCIE_REXTAE11PCIE_RX_NPCIE_VPH_RXPCIE_RX_NAD11PCIE_RX_PPCIE_VPH_RXPCIE_RX_PAC11PCIE_TX_NPCIE_VPH_TXPCIE_TX_NAB11PCIE_TX_PPCIE_VPH_TXPCIE_TX_PAA10PCIE_VPPCIE_VPPCIE_VPAA12PCIE_VP_RXPCIE_VP_RXPCIE_VP_RXAA11PCIE_VP_TXPCIE_VP_TXPCIE_VP_TXY10PCIE_VPHPCIE_VPHPCIE_VPHY12PCIE_VPH_RXPCIE_VPH_RXPCIE_VPH_RXY11PCIE_VPH_TXPCIE_VPH_TXPCIE_VPH_TXR06POR_BNVCC_GPIO1GPIOALT0POR_B100KPUAE06RTC_XTALIVDD_SNVS_1P8_CAPRTC_XTALIAD06RTC_XTALOVDD_SNVS_1P8_CAPRTC_XTALOE10SAI1_MCLKNVCC_SAIGPIOALT5GPIO6_IO[18]100KPDD12SAI1_RXCNVCC_SAIGPIOALT5GPIO6_IO[17]100KPDTable102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors150E12SAI1_RXDNVCC_SAIGPIOALT5GPIO6_IO[12]100KPDC12SAI1_RXFSNVCC_SAIGPIOALT5GPIO6_IO[16]100KPDC11SAI1_TXCNVCC_SAIGPIOALT5GPIO6_IO[13]100KPDE11SAI1_TXDNVCC_SAIGPIOALT5GPIO6_IO[15]100KPDD11SAI1_TXFSNVCC_SAIGPIOALT5GPIO6_IO[14]100KPDE09SAI2_RXDNVCC_SAIGPIOALT5GPIO6_IO[21]100KPDD08SAI2_TXCNVCC_SAIGPIOALT5GPIO6_IO[20]100KPDE08SAI2_TXDNVCC_SAIGPIOALT5GPIO6_IO[22]100KPDD09SAI2_TXFSNVCC_SAIGPIOALT5GPIO6_IO[19]100KPDC06SD1_CD_BNVCC_SD1GPIOALT5GPIO5_IO[0]100KPDB05SD1_CLKNVCC_SD1GPIOALT5GPIO5_IO[3]100KPDC05SD1_CMDNVCC_SD1GPIOALT5GPIO5_IO[4]100KPDA05SD1_DATA0NVCC_SD1GPIOALT5GPIO5_IO[5]100KPDD06SD1_DATA1NVCC_SD1GPIOALT5GPIO5_IO[6]100KPDA04SD1_DATA2NVCC_SD1GPIOALT5GPIO5_IO[7]100KPDD05SD1_DATA3NVCC_SD1GPIOALT5GPIO5_IO[8]100KPDB04SD1_RESET_BNVCC_SD1GPIOALT5GPIO5_IO[2]100KPDC04SD1_WPNVCC_SD1GPIOALT5GPIO5_IO[1]100KPDD03SD2_CD_BNVCC_SD2GPIOALT5GPIO5_IO[9]100KPDE03SD2_CLKNVCC_SD2GPIOALT5GPIO5_IO[12]100KPDF06SD2_CMDNVCC_SD2GPIOALT5GPIO5_IO[13]100KPDE04SD2_DATA0NVCC_SD2GPIOALT5GPIO5_IO[14]100KPDE05SD2_DATA1NVCC_SD2GPIOALT5GPIO5_IO[15]100KPDF05SD2_DATA2NVCC_SD2GPIOALT5GPIO5_IO[16]100KPDE06SD2_DATA3NVCC_SD2GPIOALT5GPIO5_IO[17]100KPDG03SD2_RESET_BNVCC_SD2GPIOALT5GPIO5_IO[11]100KPDC03SD2_WPNVCC_SD2GPIOALT5GPIO5_IO[10]100KPDC01SD3_CLKNVCC_SD3GPIOALT5GPIO6_IO[0]100KPDE01SD3_CMDNVCC_SD3GPIOALT5GPIO6_IO[1]100KPDB02SD3_DATA0NVCC_SD3GPIOALT5GPIO6_IO[2]100KPDA02SD3_DATA1NVCC_SD3GPIOALT5GPIO6_IO[3]100KPDG02SD3_DATA2NVCC_SD3GPIOALT5GPIO6_IO[4]100KPDTable102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors151F01SD3_DATA3NVCC_SD3GPIOALT5GPIO6_IO[5]100KPDF02SD3_DATA4NVCC_SD3GPIOALT5GPIO6_IO[6]100KPDE02SD3_DATA5NVCC_SD3GPIOALT5GPIO6_IO[7]100KPDC02SD3_DATA6NVCC_SD3GPIOALT5GPIO6_IO[8]100KPDB01SD3_DATA7NVCC_SD3GPIOALT5GPIO6_IO[9]100KPDG01SD3_RESET_BNVCC_SD3GPIOALT5GPIO6_IO[11]100KPDJ01SD3_STROBENVCC_SD3GPIOALT5GPIO6_IO[10]100KPDAB08SNVS_PMIC_ON_REQVDD_SNVS_INSNVS_PMIC_ON_REQAA07SNVS_TAMPER0VDDD_SNVS_1P8_CAPAnalogSNVS_TAMPER0Y08SNVS_TAMPER1VDD_SNVS_1P8_CAPAnalogSNVS_TAMPER1AB06SNVS_TAMPER2VDDD_SNVS_1P8_CAPAnalogSNVS_TAMPER2Y07SNVS_TAMPER3VDD_SNVS_1P8_CAPAnalogSNVS_TAMPER3AA05SNVS_TAMPER4VDDD_SNVS_1P8_CAPAnalogSNVS_TAMPER4Y05SNVS_TAMPER5VDD_SNVS_1P8_CAPAnalogSNVS_TAMPER5AA04SNVS_TAMPER6VDDD_SNVS_1P8_CAPAnalogSNVS_TAMPER6Y04SNVS_TAMPER7VDD_SNVS_1P8_CAPAnalogSNVS_TAMPER7AA03SNVS_TAMPER8VDDD_SNVS_1P8_CAPAnalogSNVS_TAMPER8Y03SNVS_TAMPER9VDD_SNVS_1P8_CAPAnalogSNVS_TAMPER9AE04TEMPSENSOR_REXTVDD_TEMPSENSOR_1P8TEMPSENSOR_REXTAD04TEMPSENSOR_RESERVEVDD_TEMPSENSOR_1P8TEMPSENSOR_RESERVEP06TEST_MODENVCC_GPIO1GPIOALT0TEST_MODE100KPDL03UART1_RXDNVCC_UARTGPIOALT5GPIO4_IO[0]100KPDL04UART1_TXDNVCC_UARTGPIOALT5GPIO4_IO[1]100KPDL05UART2_RXDNVCC_UARTGPIOALT5GPIO4_IO[2]100KPDL06UART2_TXDNVCC_UARTGPIOALT5GPIO4_IO[3]100KPDM06UART3_CTSNVCC_UARTGPIOALT5GPIO4_IO[7]100KPDM05UART3_RTSNVCC_UARTGPIOALT5GPIO4_IO[6]100KPDM01UART3_RXDNVCC_UARTGPIOALT5GPIO4_IO[4]100KPDM02UART3_TXDNVCC_UARTGPIOALT5GPIO4_IO[5]100KPDA12USB_H_DATAUSB_H_VDD_1P2USB_H_DATAB12USB_H_STROBEUSB_H_VDD_1P2USB_H_STROBEC07USB_OTG1_CHD_BUSB_OTG1_VDDA_3P3USB_OTG1_CHD_BTable102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1526.
2.
3Case"Y",i.
MX7Dual19*19mm0.
75mmpitchballmapThefollowingtableshowsthei.
MX7Dual19*19mm,0.
75mmpitchballmap.
A08USB_OTG1_DNUSB_OTG1_VDDA_3P3USB_OTG1_DNB08USB_OTG1_DPUSB_OTG1_VDDA_3P3USB_OTG1_DPB07USB_OTG1_IDUSB_OTG1_VDDA_3P3USB_OTG1_IDA07USB_OTG1_REXTUSB_OTG1_VDDA_3P3USB_OTG1_REXTA10USB_OTG2_DNUSB_OTG2_VDDA_3P3USB_OTG2_DNB10USB_OTG2_DPUSB_OTG2_VDDA_3P3USB_OTG2_DPB11USB_OTG2_IDUSB_OTG2_VDDA_3P3USB_OTG2_IDA11USB_OTG2_REXTUSB_OTG2_VDDA_3P3USB_OTG2_REXTV01XTALIVDDA_1P8XTALIV02XTALOVDDA_1P8XTALO1ThestateimmediatelyafterRESETandbeforeROMfirmwareorsoftwarehasexecuted.
Table103.
i.
MX7Dual19*19mm0.
75mmpitchballmap12345678910111213141516171819202122232425AVSSSD3_DATA1VSSSD1_DATA2SD1_DATA0VSSUSB_OTG1_REXTUSB_OTG1_DNVSSUSB_OTG2_DNUSB_OTG2_REXTUSB_H_DATAVSSMIPI_CSI_D1_NMIPI_CSI_CLK_NMIPI_CSI_D0_NVSSMIPI_DSI_D1_NMIPI_DSI_CLK_NMIPI_DSI_D0_NVSSLCD1_DATA01LCD1_DATA03LCD1_DATA06VSSABSD3_DATA7SD3_DATA0VSSSD1_RESET_BSD1_CLKVSSUSB_OTG1_IDUSB_OTG1_DPVSSUSB_OTG2_DPUSB_OTG2_IDUSB_H_STROBEVSSMIPI_CSI_D1_PMIPI_CSI_CLK_PMIPI_CSI_D0_PVSSMIPI_DSI_D1_PMIPI_DSI_CLK_PMIPI_DSI_D0_PVSSLCD1_DATA02LCD1_DATA05LCD1_DATA10LCD1_DATA16BCSD3_CLKSD3_DATA6SD2_WPSD1_WPSD1_CMDSD1_CD_BUSB_OTG1_CHD_BUSB_OTG1_VBUSVSSUSB_OTG2_VBUSSAI1_TXCSAI1_RXFSVSSVDD_SOCVSSVSSVDD_ARMVSSVSSVDD_ARMLCD1_RESETLCD1_DATA04LCD1_DATA09LCD1_DATA15LCD1_DATA20C12345678910111213141516171819202122232425Table102.
i.
MX7Dual19x19mmfunctionalcontactassignments(continued)BallBallNamePowerGroupBalltype1DefaultMode1DefaultFunction1PD/PUPackageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors153DVSSVSSSD2_CD_BVSSSD1_DATA3SD1_DATA1VSSSAI2_TXCSAI2_TXFSVSSSAI1_TXFSSAI1_RXCENET1_RDATA2VDD_SOCENET1_RX_CLKENET1_TX_CLKVDD_ARMENET1_TDATA3ENET1_COLVDD_ARMLCD1_DATA00VSSLCD1_DATA14LCD1_DATA19LCD1_DATA22DESD3_CMDSD3_DATA5SD2_CLKSD2_DATA0SD2_DATA1SD2_DATA3NVCC_SD1SAI2_TXDSAI2_RXDSAI1_MCLKSAI1_TXDSAI1_RXDENET1_RDATA3ENET1_RD0ENET1_RX_CTLENET1_TX_CTLENET1_TDATA1ENET1_TDATA2ENET1_CRSLCD1_CLKLCD1_DATA08LCD1_DATA13LCD1_DATA18LCD1_DATA21LCD1_HSYNCEFSD3_DATA3SD3_DATA4VDD_SOCVDD_SOCSD2_DATA2SD2_CMDVSSVSSVDD_USB_OTG2_3P3_INVDD_USB_OTG1_3P3_INVSSNVCC_SAIVSSENET1_RDATA1ENET1_RXCENET1_TXCENET1_TD0VDD_SOCVDD_SOCLCD1_DATA07LCD1_DATA12VDD_ARMVDD_ARMLCD1_VSYNCLCD1_ENABLEFGSD3_RESET_BSD3_DATA2SD2_RESET_BVSSECSPI1_MOSIECSPI2_MOSIVSSVSSVSSVSSVSSVSSVSSLCD1_DATA11LCD1_DATA17VSSLCD1_DATA23EPDC1_SDCE1EPDC1_SDCE0GHVSSVSSECSPI1_SCLKECSPI1_MISOECSPI1_SS0ECSPI2_MISONVCC_SD2VDD_USB_OTG1_1P0_CAPVDD_USB_H_1P2PVCC_ENET_CAPNVCC_ENET1MIPI_VREG_0P4VEPDC1_SDSHREPDC1_SDOEEPDC1_SDCE3EPDC1_SDCE2EPDC1_PWRCOMEPDC1_GDSPHJSD3_STROBEI2C1_SCLVDD_SOCVDD_SOCECSPI2_SCLKECSPI2_SS0VSSPVCC_SAI_SD_CAPVDD_USB_OTG2_1P0_CAPVDDA_MIPI_1P8VDD_MIPI_1P0VDD_MIPI_1P0VSSEPDC1_SDLEEPDC1_SDCLKVDD_ARMVDD_ARMEPDC1_GDOEEPDC1_GDCLKJKI2C1_SDAI2C2_SCLI2C2_SDAVSSI2C3_SCLI2C3_SDANVCC_SD3VSSVSSVSSVSSNVCC_LCDEPDC1_PWRSTATEPDC1_GDRLVSSEPDC1_BDR1EPDC1_BDR0EPDC1_DATA15KTable103.
i.
MX7Dual19*19mm0.
75mmpitchballmap(continued)1234567891011121314151617181920212223242512345678910111213141516171819202122232425Packageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors154LI2C4_SCLI2C4_SDAUART1_RXDUART1_TXDUART2_RXDUART2_TXDVSSNVCC_SPIVSSVSSVSSNVCC_EPDC2VSSEPDC1_DATA14EPDC1_DATA13EPDC1_DATA12EPDC1_DATA11EPDC1_DATA10EPDC1_DATA09LMUART3_RXDUART3_TXDVDD_SOCVDD_SOCUART3_RTSUART3_CTSNVCC_I2CVSSVSSVSSVSSNVCC_EPDC1EPDC1_DATA05EPDC1_DATA06EPDC1_DATA07EPDC1_DATA08VSSVSSMNGPIO1_IO00GPIO1_IO01GPIO1_IO02VSSGPIO1_IO03GPIO1_IO04VSSNVCC_UARTVSSVSSVSSPVCC_EPDC_LCD_CAPVSSEPDC1_DATA02EPDC1_DATA03EPDC1_DATA04DRAM_SDBA2DRAM_DATA25DRAM_DATA27NPGPIO1_IO05GPIO1_IO06GPIO1_IO07BOOT_MODE0BOOT_MODE1TEST_MODENVCC_GPIO1VSSVSSVSSVSSVDD_SOCEPDC_D00EPDC1_DATA01DRAM_SDBA1DRAM_ADDR13DRAM_DQM3DRAM_DATA26PRGPIO1_IO08GPIO1_IO09VDD_SOCVDD_SOCGPIO1_IO10POR_BVSSPVCC_I2C_SPI_UART_CAPVSSVSSVSSVDD_SOCVSSVSSVSSDRAM_SDBA0VSSDRAM_DATA29DRAM_DATA24RTGPIO1_IO11GPIO1_IO12GPIO1_IO13VSSGPIO1_IO14GPIO1_IO15NVCC_GPIO2VSSVSSVSSVSSVDD_SOCVSSNVCC_DRAMDRAM_ADDR12DRAM_ADDR10DRAM_SDQS3_PDRAM_SDQS3_NTUJTAG_MODJTAG_TRST_BJTAG_TDIJTAG_TMSJTAG_TCKJTAG_TDOVSSVDD_1P2_CAPVSSVDD_SOCVDD_SOCVDD_SOCVSSVSSNVCC_DRAMDRAM_ADDR11VSSDRAM_DATA30DRAM_DATA28UTable103.
i.
MX7Dual19*19mm0.
75mmpitchballmap(continued)1234567891011121314151617181920212223242512345678910111213141516171819202122232425Packageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors155VXTALIXTALOVDDA_1P0_CAPGPANAIOVDD_XTAL_1P8VDDA_1P8_INFUSE_FSOURCEPVCC_GPIO_CAPVDD_SOCVDD_SOCVDD_SOCVDD_SOCVSSNVCC_DRAMDRAM_ADDR06DRAM_ADDR09DRAM_DATA31DRAM_DATA18VWVSSVSSCCM_CLK2VSSVDDA_1P8_INVDD_LPSR_INVSSVSSVSSVSSVSSVSSVSSVSSNVCC_DRAMDRAM_ADDR08VSSDRAM_DATA17DRAM_DATA19WYCCM_CLK1_NCCM_CLK1_PSNVS_TAMPER09SNVS_TAMPER07SNVS_TAMPER05VSSSNVS_TAMPER03SNVS_TAMPER01VDDA_PHY_1P8PCIE_VPHPCIE_VPH_TXPCIE_VPH_RXVSSVSSVSSVSSVSSVSSVSSNVCC_DRAM_CKENVCC_DRAMDRAM_ADDR07DRAM_ADDR05DRAM_SDQS2_PDRAM_SDQS2_NYAAVSSVSSSNVS_TAMPER08SNVS_TAMPER06SNVS_TAMPER04VSSSNVS_TAMPER00VSSVDDD_1P0_CAPPCIE_VPPCIE_VP_TXPCIE_VP_RXPCIE_REXTDRAM_ODT1VSSNVCC_DRAMNVCC_DRAMNVCC_DRAMNVCC_DRAMNVCC_DRAMNVCC_DRAMDRAM_CS1_BVSSDRAM_DQM2DRAM_DATA16AAABADC2_IN2ADC2_IN3VDDA_ADC2_1P8VSSVSSSNVS_TAMPER02VSSSNVS_PMIC_ON_REQVSSPCIE_REFCLKOUT_PPCIE_TX_PVSSDRAM_ZQPADDRAM_SDWE_BDRAM_RAS_BDRAM_ADDR01DRAM_SDCKE0DRAM_ADDR14DRAM_ADDR00DRAM_ADDR15DRAM_ADDR04DRAM_SDCKE1DRAM_CS0_BDRAM_DATA22DRAM_DATA21ABACADC2_IN0ADC2_IN1VDDA_ADC1_1P8VDD_TEMPSENSOR_1P8VDD_LPSR_1P0_CAPVSSPMIC_STBY_REQONOFFVSSPCIE_REFCLKOUT_NPCIE_TX_NVSSDRAM_VREFDRAM_CAS_BVSSDRAM_ODT0VSSDRAM_ADDR02VSSDRAM_ADDR03VSSDRAM_RESETVSSDRAM_DATA23DRAM_DATA20ACADADC1_IN0VSSADC1_IN1TEMPSENSOR_RESERVEVSSRTC_XTALOVSSVDD_SNVS_INVSSPCIE_REFCLKIN_PPCIE_RX_PVSSDRAM_DATA14DRAM_DATA13DRAM_SDQS1_PDRAM_DATA11DRAM_DQM1DRAM_DATA06DRAM_DATA05DRAM_DQM0DRAM_SDQS0_NDRAM_DATA00DRAM_DATA01DRAM_SDCLK0_PDRAM_SDCLK0_NADTable103.
i.
MX7Dual19*19mm0.
75mmpitchballmap(continued)1234567891011121314151617181920212223242512345678910111213141516171819202122232425Packageinformationandcontactassignmentsi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors156AEVSSADC1_IN2ADC1_IN3TEMPSENSOR_REXTVSSRTC_XTALIVSSVDD_SNVS_1P8_CAPVSSPCIE_REFCLKIN_NPCIE_RX_NVSSDRAM_DATA15DRAM_DATA08DRAM_SDQS1_NDRAM_DATA12DRAM_DATA10DRAM_DATA09DRAM_DATA07DRAM_DATA02DRAM_SDQS0_PDRAM_DATA04DRAM_DATA03VSSVSSAETable103.
i.
MX7Dual19*19mm0.
75mmpitchballmap(continued)1234567891011121314151617181920212223242512345678910111213141516171819202122232425Revisionhistoryi.
MX7DualFamilyofApplicationsProcessorsDatasheet,Rev.
6,02/2019NXPSemiconductors1577ReleasenotesTable104providesreleasenotesforthisdatasheet.
Table104.
ReleasenotesRev.
NumberDateSubstantiveChange(s)Rev.
62/2019Onp.
1andinTable1,"Orderableparts,"addedinformationrelatedtonewpartnumber,MCIMX7D5EVK10SDInTable12,"Maximumsupplycurrents,"updatedmaximumvalueforDRAM_VREFInTable22,"PCIePHYreferenceclocktimingrequirements":In'Absolutemaximuminputvoltage'row,updated'Min.
'valueIn'Absoluteminimuminputvoltage'row,updated'Min.
'and'Max.
'valuesIn'Absolutecrossingpointvoltage'row,updated'Max'.
valueDocumentNumber:IMX7DCECRev.
603/2019InformationinthisdocumentisprovidedsolelytoenablesystemandsoftwareimplementerstouseNXPproducts.
Therearenoexpressorimpliedcopyrightlicensesgrantedhereundertodesignorfabricateanyintegratedcircuitsbasedontheinformationinthisdocument.
NXPreservestherighttomakechangeswithoutfurthernoticetoanyproductsherein.
NXPmakesnowarranty,representation,orguaranteeregardingthesuitabilityofitsproductsforanyparticularpurpose,nordoesNXPassumeanyliabilityarisingoutoftheapplicationoruseofanyproductorcircuit,andspecificallydisclaimsanyandallliability,includingwithoutlimitationconsequentialorincidentaldamages.
"Typical"parametersthatmaybeprovidedinNXPdatasheetsand/orspecificationscananddovaryindifferentapplications,andactualperformancemayvaryovertime.
Alloperatingparameters,including"typicals,"mustbevalidatedforeachcustomerapplicationbycustomer'stechnicalexperts.
NXPdoesnotconveyanylicenseunderitspatentrightsnortherightsofothers.
NXPsellsproductspursuanttostandardtermsandconditionsofsale,whichcanbefoundatthefollowingaddress:nxp.
com/SalesTermsandConditions.
WhileNXPhasimplementedadvancedsecurityfeatures,allproductsmaybesubjecttounidentifiedvulnerabilities.
Customersareresponsibleforthedesignandoperationoftheirapplicationsandproductstoreducetheeffectofthesevulnerabilitiesoncustomer'sapplicationsandproducts,andNXPacceptsnoliabilityforanyvulnerabilitythatisdiscovered.
Customersshouldimplementappropriatedesignandoperatingsafeguardstominimizetherisksassociatedwiththeirapplicationsandproducts.
NXP,theNXPlogo,NXPSECURECONNECTIONSFORASMARTERWORLD,COOLFLUX,EMBRACE,GREENCHIP,HITAG,I2CBUS,ICODE,JCOP,LIFEVIBES,MIFARE,MIFARECLASSIC,MIFAREDESFire,MIFAREPLUS,MIFAREFLEX,MANTIS,MIFAREULTRALIGHT,MIFARE4MOBILE,MIGLO,NTAG,ROADLINK,SMARTLX,SMARTMX,STARPLUG,TOPFET,TRENCHMOS,UCODE,Freescale,theFreescalelogo,AltiVec,C-5,CodeTEST,CodeWarrior,ColdFire,ColdFire+,C-Ware,theEnergyEfficientSolutionslogo,Kinetis,Layerscape,MagniV,mobileGT,PEG,PowerQUICC,ProcessorExpert,QorIQ,QorIQQonverge,ReadyPlay,SafeAssure,theSafeAssurelogo,StarCore,Symphony,VortiQa,Vybrid,Airfast,BeeKit,BeeStack,CoreNet,Flexis,MXC,PlatforminaPackage,QUICCEngine,SMARTMOS,Tower,TurboLink,andUMEMSaretrademarksofNXPB.
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